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netxen: pre calculate register addresses
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / netxen / netxen_nic_ctx.c
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
28 *
29 */
30
31 #include "netxen_nic_hw.h"
32 #include "netxen_nic.h"
33
34 #define NXHAL_VERSION 1
35
36 static u32
37 netxen_poll_rsp(struct netxen_adapter *adapter)
38 {
39 u32 rsp = NX_CDRP_RSP_OK;
40 int timeout = 0;
41
42 do {
43 /* give atleast 1ms for firmware to respond */
44 msleep(1);
45
46 if (++timeout > NX_OS_CRB_RETRY_COUNT)
47 return NX_CDRP_RSP_TIMEOUT;
48
49 rsp = NXRD32(adapter, NX_CDRP_CRB_OFFSET);
50 } while (!NX_CDRP_IS_RSP(rsp));
51
52 return rsp;
53 }
54
55 static u32
56 netxen_issue_cmd(struct netxen_adapter *adapter,
57 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd)
58 {
59 u32 rsp;
60 u32 signature = 0;
61 u32 rcode = NX_RCODE_SUCCESS;
62
63 signature = NX_CDRP_SIGNATURE_MAKE(pci_fn, version);
64
65 /* Acquire semaphore before accessing CRB */
66 if (netxen_api_lock(adapter))
67 return NX_RCODE_TIMEOUT;
68
69 NXWR32(adapter, NX_SIGN_CRB_OFFSET, signature);
70
71 NXWR32(adapter, NX_ARG1_CRB_OFFSET, arg1);
72
73 NXWR32(adapter, NX_ARG2_CRB_OFFSET, arg2);
74
75 NXWR32(adapter, NX_ARG3_CRB_OFFSET, arg3);
76
77 NXWR32(adapter, NX_CDRP_CRB_OFFSET, NX_CDRP_FORM_CMD(cmd));
78
79 rsp = netxen_poll_rsp(adapter);
80
81 if (rsp == NX_CDRP_RSP_TIMEOUT) {
82 printk(KERN_ERR "%s: card response timeout.\n",
83 netxen_nic_driver_name);
84
85 rcode = NX_RCODE_TIMEOUT;
86 } else if (rsp == NX_CDRP_RSP_FAIL) {
87 rcode = NXRD32(adapter, NX_ARG1_CRB_OFFSET);
88
89 printk(KERN_ERR "%s: failed card response code:0x%x\n",
90 netxen_nic_driver_name, rcode);
91 }
92
93 /* Release semaphore */
94 netxen_api_unlock(adapter);
95
96 return rcode;
97 }
98
99 int
100 nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu)
101 {
102 u32 rcode = NX_RCODE_SUCCESS;
103 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
104
105 if (recv_ctx->state == NX_HOST_CTX_STATE_ACTIVE)
106 rcode = netxen_issue_cmd(adapter,
107 adapter->ahw.pci_func,
108 NXHAL_VERSION,
109 recv_ctx->context_id,
110 mtu,
111 0,
112 NX_CDRP_CMD_SET_MTU);
113
114 if (rcode != NX_RCODE_SUCCESS)
115 return -EIO;
116
117 return 0;
118 }
119
120 static int
121 nx_fw_cmd_create_rx_ctx(struct netxen_adapter *adapter)
122 {
123 void *addr;
124 nx_hostrq_rx_ctx_t *prq;
125 nx_cardrsp_rx_ctx_t *prsp;
126 nx_hostrq_rds_ring_t *prq_rds;
127 nx_hostrq_sds_ring_t *prq_sds;
128 nx_cardrsp_rds_ring_t *prsp_rds;
129 nx_cardrsp_sds_ring_t *prsp_sds;
130 struct nx_host_rds_ring *rds_ring;
131 struct nx_host_sds_ring *sds_ring;
132
133 dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
134 u64 phys_addr;
135
136 int i, nrds_rings, nsds_rings;
137 size_t rq_size, rsp_size;
138 u32 cap, reg, val;
139
140 int err;
141
142 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
143
144 nrds_rings = adapter->max_rds_rings;
145 nsds_rings = adapter->max_sds_rings;
146
147 rq_size =
148 SIZEOF_HOSTRQ_RX(nx_hostrq_rx_ctx_t, nrds_rings, nsds_rings);
149 rsp_size =
150 SIZEOF_CARDRSP_RX(nx_cardrsp_rx_ctx_t, nrds_rings, nsds_rings);
151
152 addr = pci_alloc_consistent(adapter->pdev,
153 rq_size, &hostrq_phys_addr);
154 if (addr == NULL)
155 return -ENOMEM;
156 prq = (nx_hostrq_rx_ctx_t *)addr;
157
158 addr = pci_alloc_consistent(adapter->pdev,
159 rsp_size, &cardrsp_phys_addr);
160 if (addr == NULL) {
161 err = -ENOMEM;
162 goto out_free_rq;
163 }
164 prsp = (nx_cardrsp_rx_ctx_t *)addr;
165
166 prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
167
168 cap = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN);
169 cap |= (NX_CAP0_JUMBO_CONTIGUOUS | NX_CAP0_LRO_CONTIGUOUS);
170
171 prq->capabilities[0] = cpu_to_le32(cap);
172 prq->host_int_crb_mode =
173 cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED);
174 prq->host_rds_crb_mode =
175 cpu_to_le32(NX_HOST_RDS_CRB_MODE_UNIQUE);
176
177 prq->num_rds_rings = cpu_to_le16(nrds_rings);
178 prq->num_sds_rings = cpu_to_le16(nsds_rings);
179 prq->rds_ring_offset = cpu_to_le32(0);
180
181 val = le32_to_cpu(prq->rds_ring_offset) +
182 (sizeof(nx_hostrq_rds_ring_t) * nrds_rings);
183 prq->sds_ring_offset = cpu_to_le32(val);
184
185 prq_rds = (nx_hostrq_rds_ring_t *)(prq->data +
186 le32_to_cpu(prq->rds_ring_offset));
187
188 for (i = 0; i < nrds_rings; i++) {
189
190 rds_ring = &recv_ctx->rds_rings[i];
191
192 prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
193 prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
194 prq_rds[i].ring_kind = cpu_to_le32(i);
195 prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
196 }
197
198 prq_sds = (nx_hostrq_sds_ring_t *)(prq->data +
199 le32_to_cpu(prq->sds_ring_offset));
200
201 for (i = 0; i < nsds_rings; i++) {
202
203 sds_ring = &recv_ctx->sds_rings[i];
204
205 prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
206 prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
207 prq_sds[i].msi_index = cpu_to_le16(i);
208 }
209
210 phys_addr = hostrq_phys_addr;
211 err = netxen_issue_cmd(adapter,
212 adapter->ahw.pci_func,
213 NXHAL_VERSION,
214 (u32)(phys_addr >> 32),
215 (u32)(phys_addr & 0xffffffff),
216 rq_size,
217 NX_CDRP_CMD_CREATE_RX_CTX);
218 if (err) {
219 printk(KERN_WARNING
220 "Failed to create rx ctx in firmware%d\n", err);
221 goto out_free_rsp;
222 }
223
224
225 prsp_rds = ((nx_cardrsp_rds_ring_t *)
226 &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
227
228 for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
229 rds_ring = &recv_ctx->rds_rings[i];
230
231 reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
232 rds_ring->crb_rcv_producer = netxen_get_ioaddr(adapter,
233 NETXEN_NIC_REG(reg - 0x200));
234 }
235
236 prsp_sds = ((nx_cardrsp_sds_ring_t *)
237 &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
238
239 for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
240 sds_ring = &recv_ctx->sds_rings[i];
241
242 reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
243 sds_ring->crb_sts_consumer = netxen_get_ioaddr(adapter,
244 NETXEN_NIC_REG(reg - 0x200));
245
246 reg = le32_to_cpu(prsp_sds[i].interrupt_crb);
247 sds_ring->crb_intr_mask = netxen_get_ioaddr(adapter,
248 NETXEN_NIC_REG(reg - 0x200));
249 }
250
251 recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
252 recv_ctx->context_id = le16_to_cpu(prsp->context_id);
253 recv_ctx->virt_port = prsp->virt_port;
254
255 out_free_rsp:
256 pci_free_consistent(adapter->pdev, rsp_size, prsp, cardrsp_phys_addr);
257 out_free_rq:
258 pci_free_consistent(adapter->pdev, rq_size, prq, hostrq_phys_addr);
259 return err;
260 }
261
262 static void
263 nx_fw_cmd_destroy_rx_ctx(struct netxen_adapter *adapter)
264 {
265 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
266
267 if (netxen_issue_cmd(adapter,
268 adapter->ahw.pci_func,
269 NXHAL_VERSION,
270 recv_ctx->context_id,
271 NX_DESTROY_CTX_RESET,
272 0,
273 NX_CDRP_CMD_DESTROY_RX_CTX)) {
274
275 printk(KERN_WARNING
276 "%s: Failed to destroy rx ctx in firmware\n",
277 netxen_nic_driver_name);
278 }
279 }
280
281 static int
282 nx_fw_cmd_create_tx_ctx(struct netxen_adapter *adapter)
283 {
284 nx_hostrq_tx_ctx_t *prq;
285 nx_hostrq_cds_ring_t *prq_cds;
286 nx_cardrsp_tx_ctx_t *prsp;
287 void *rq_addr, *rsp_addr;
288 size_t rq_size, rsp_size;
289 u32 temp;
290 int err = 0;
291 u64 offset, phys_addr;
292 dma_addr_t rq_phys_addr, rsp_phys_addr;
293 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
294 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
295
296 rq_size = SIZEOF_HOSTRQ_TX(nx_hostrq_tx_ctx_t);
297 rq_addr = pci_alloc_consistent(adapter->pdev,
298 rq_size, &rq_phys_addr);
299 if (!rq_addr)
300 return -ENOMEM;
301
302 rsp_size = SIZEOF_CARDRSP_TX(nx_cardrsp_tx_ctx_t);
303 rsp_addr = pci_alloc_consistent(adapter->pdev,
304 rsp_size, &rsp_phys_addr);
305 if (!rsp_addr) {
306 err = -ENOMEM;
307 goto out_free_rq;
308 }
309
310 memset(rq_addr, 0, rq_size);
311 prq = (nx_hostrq_tx_ctx_t *)rq_addr;
312
313 memset(rsp_addr, 0, rsp_size);
314 prsp = (nx_cardrsp_tx_ctx_t *)rsp_addr;
315
316 prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
317
318 temp = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN | NX_CAP0_LSO);
319 prq->capabilities[0] = cpu_to_le32(temp);
320
321 prq->host_int_crb_mode =
322 cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED);
323
324 prq->interrupt_ctl = 0;
325 prq->msi_index = 0;
326
327 prq->dummy_dma_addr = cpu_to_le64(adapter->dummy_dma.phys_addr);
328
329 offset = recv_ctx->phys_addr + sizeof(struct netxen_ring_ctx);
330 prq->cmd_cons_dma_addr = cpu_to_le64(offset);
331
332 prq_cds = &prq->cds_ring;
333
334 prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
335 prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
336
337 phys_addr = rq_phys_addr;
338 err = netxen_issue_cmd(adapter,
339 adapter->ahw.pci_func,
340 NXHAL_VERSION,
341 (u32)(phys_addr >> 32),
342 ((u32)phys_addr & 0xffffffff),
343 rq_size,
344 NX_CDRP_CMD_CREATE_TX_CTX);
345
346 if (err == NX_RCODE_SUCCESS) {
347 temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
348 tx_ring->crb_cmd_producer = netxen_get_ioaddr(adapter,
349 NETXEN_NIC_REG(temp - 0x200));
350 #if 0
351 adapter->tx_state =
352 le32_to_cpu(prsp->host_ctx_state);
353 #endif
354 adapter->tx_context_id =
355 le16_to_cpu(prsp->context_id);
356 } else {
357 printk(KERN_WARNING
358 "Failed to create tx ctx in firmware%d\n", err);
359 err = -EIO;
360 }
361
362 pci_free_consistent(adapter->pdev, rsp_size, rsp_addr, rsp_phys_addr);
363
364 out_free_rq:
365 pci_free_consistent(adapter->pdev, rq_size, rq_addr, rq_phys_addr);
366
367 return err;
368 }
369
370 static void
371 nx_fw_cmd_destroy_tx_ctx(struct netxen_adapter *adapter)
372 {
373 if (netxen_issue_cmd(adapter,
374 adapter->ahw.pci_func,
375 NXHAL_VERSION,
376 adapter->tx_context_id,
377 NX_DESTROY_CTX_RESET,
378 0,
379 NX_CDRP_CMD_DESTROY_TX_CTX)) {
380
381 printk(KERN_WARNING
382 "%s: Failed to destroy tx ctx in firmware\n",
383 netxen_nic_driver_name);
384 }
385 }
386
387 int
388 nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val)
389 {
390 u32 rcode;
391
392 rcode = netxen_issue_cmd(adapter,
393 adapter->ahw.pci_func,
394 NXHAL_VERSION,
395 reg,
396 0,
397 0,
398 NX_CDRP_CMD_READ_PHY);
399
400 if (rcode != NX_RCODE_SUCCESS)
401 return -EIO;
402
403 return NXRD32(adapter, NX_ARG1_CRB_OFFSET);
404 }
405
406 int
407 nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val)
408 {
409 u32 rcode;
410
411 rcode = netxen_issue_cmd(adapter,
412 adapter->ahw.pci_func,
413 NXHAL_VERSION,
414 reg,
415 val,
416 0,
417 NX_CDRP_CMD_WRITE_PHY);
418
419 if (rcode != NX_RCODE_SUCCESS)
420 return -EIO;
421
422 return 0;
423 }
424
425 static u64 ctx_addr_sig_regs[][3] = {
426 {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
427 {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
428 {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
429 {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
430 };
431
432 #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
433 #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
434 #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
435
436 #define lower32(x) ((u32)((x) & 0xffffffff))
437 #define upper32(x) ((u32)(((u64)(x) >> 32) & 0xffffffff))
438
439 static struct netxen_recv_crb recv_crb_registers[] = {
440 /* Instance 0 */
441 {
442 /* crb_rcv_producer: */
443 {
444 NETXEN_NIC_REG(0x100),
445 /* Jumbo frames */
446 NETXEN_NIC_REG(0x110),
447 /* LRO */
448 NETXEN_NIC_REG(0x120)
449 },
450 /* crb_sts_consumer: */
451 {
452 NETXEN_NIC_REG(0x138),
453 NETXEN_NIC_REG_2(0x000),
454 NETXEN_NIC_REG_2(0x004),
455 NETXEN_NIC_REG_2(0x008),
456 },
457 /* sw_int_mask */
458 {
459 CRB_SW_INT_MASK_0,
460 NETXEN_NIC_REG_2(0x044),
461 NETXEN_NIC_REG_2(0x048),
462 NETXEN_NIC_REG_2(0x04c),
463 },
464 },
465 /* Instance 1 */
466 {
467 /* crb_rcv_producer: */
468 {
469 NETXEN_NIC_REG(0x144),
470 /* Jumbo frames */
471 NETXEN_NIC_REG(0x154),
472 /* LRO */
473 NETXEN_NIC_REG(0x164)
474 },
475 /* crb_sts_consumer: */
476 {
477 NETXEN_NIC_REG(0x17c),
478 NETXEN_NIC_REG_2(0x020),
479 NETXEN_NIC_REG_2(0x024),
480 NETXEN_NIC_REG_2(0x028),
481 },
482 /* sw_int_mask */
483 {
484 CRB_SW_INT_MASK_1,
485 NETXEN_NIC_REG_2(0x064),
486 NETXEN_NIC_REG_2(0x068),
487 NETXEN_NIC_REG_2(0x06c),
488 },
489 },
490 /* Instance 2 */
491 {
492 /* crb_rcv_producer: */
493 {
494 NETXEN_NIC_REG(0x1d8),
495 /* Jumbo frames */
496 NETXEN_NIC_REG(0x1f8),
497 /* LRO */
498 NETXEN_NIC_REG(0x208)
499 },
500 /* crb_sts_consumer: */
501 {
502 NETXEN_NIC_REG(0x220),
503 NETXEN_NIC_REG_2(0x03c),
504 NETXEN_NIC_REG_2(0x03c),
505 NETXEN_NIC_REG_2(0x03c),
506 },
507 /* sw_int_mask */
508 {
509 CRB_SW_INT_MASK_2,
510 NETXEN_NIC_REG_2(0x03c),
511 NETXEN_NIC_REG_2(0x03c),
512 NETXEN_NIC_REG_2(0x03c),
513 },
514 },
515 /* Instance 3 */
516 {
517 /* crb_rcv_producer: */
518 {
519 NETXEN_NIC_REG(0x22c),
520 /* Jumbo frames */
521 NETXEN_NIC_REG(0x23c),
522 /* LRO */
523 NETXEN_NIC_REG(0x24c)
524 },
525 /* crb_sts_consumer: */
526 {
527 NETXEN_NIC_REG(0x264),
528 NETXEN_NIC_REG_2(0x03c),
529 NETXEN_NIC_REG_2(0x03c),
530 NETXEN_NIC_REG_2(0x03c),
531 },
532 /* sw_int_mask */
533 {
534 CRB_SW_INT_MASK_3,
535 NETXEN_NIC_REG_2(0x03c),
536 NETXEN_NIC_REG_2(0x03c),
537 NETXEN_NIC_REG_2(0x03c),
538 },
539 },
540 };
541
542 static int
543 netxen_init_old_ctx(struct netxen_adapter *adapter)
544 {
545 struct netxen_recv_context *recv_ctx;
546 struct nx_host_rds_ring *rds_ring;
547 struct nx_host_sds_ring *sds_ring;
548 struct nx_host_tx_ring *tx_ring;
549 int ring;
550 int port = adapter->portnum;
551 struct netxen_ring_ctx *hwctx;
552 u32 signature;
553
554 tx_ring = adapter->tx_ring;
555 recv_ctx = &adapter->recv_ctx;
556 hwctx = recv_ctx->hwctx;
557
558 hwctx->cmd_ring_addr = cpu_to_le64(tx_ring->phys_addr);
559 hwctx->cmd_ring_size = cpu_to_le32(tx_ring->num_desc);
560
561
562 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
563 rds_ring = &recv_ctx->rds_rings[ring];
564
565 hwctx->rcv_rings[ring].addr =
566 cpu_to_le64(rds_ring->phys_addr);
567 hwctx->rcv_rings[ring].size =
568 cpu_to_le32(rds_ring->num_desc);
569 }
570
571 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
572 sds_ring = &recv_ctx->sds_rings[ring];
573
574 if (ring == 0) {
575 hwctx->sts_ring_addr = cpu_to_le64(sds_ring->phys_addr);
576 hwctx->sts_ring_size = cpu_to_le32(sds_ring->num_desc);
577 }
578 hwctx->sts_rings[ring].addr = cpu_to_le64(sds_ring->phys_addr);
579 hwctx->sts_rings[ring].size = cpu_to_le32(sds_ring->num_desc);
580 hwctx->sts_rings[ring].msi_index = cpu_to_le16(ring);
581 }
582 hwctx->sts_ring_count = cpu_to_le32(adapter->max_sds_rings);
583
584 signature = (adapter->max_sds_rings > 1) ?
585 NETXEN_CTX_SIGNATURE_V2 : NETXEN_CTX_SIGNATURE;
586
587 NXWR32(adapter, CRB_CTX_ADDR_REG_LO(port),
588 lower32(recv_ctx->phys_addr));
589 NXWR32(adapter, CRB_CTX_ADDR_REG_HI(port),
590 upper32(recv_ctx->phys_addr));
591 NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port),
592 signature | port);
593 return 0;
594 }
595
596 int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
597 {
598 void *addr;
599 int err = 0;
600 int ring;
601 struct netxen_recv_context *recv_ctx;
602 struct nx_host_rds_ring *rds_ring;
603 struct nx_host_sds_ring *sds_ring;
604 struct nx_host_tx_ring *tx_ring;
605
606 struct pci_dev *pdev = adapter->pdev;
607 struct net_device *netdev = adapter->netdev;
608 int port = adapter->portnum;
609
610 recv_ctx = &adapter->recv_ctx;
611 tx_ring = adapter->tx_ring;
612
613 addr = pci_alloc_consistent(pdev,
614 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
615 &recv_ctx->phys_addr);
616 if (addr == NULL) {
617 dev_err(&pdev->dev, "failed to allocate hw context\n");
618 return -ENOMEM;
619 }
620
621 memset(addr, 0, sizeof(struct netxen_ring_ctx));
622 recv_ctx->hwctx = (struct netxen_ring_ctx *)addr;
623 recv_ctx->hwctx->ctx_id = cpu_to_le32(port);
624 recv_ctx->hwctx->cmd_consumer_offset =
625 cpu_to_le64(recv_ctx->phys_addr +
626 sizeof(struct netxen_ring_ctx));
627 tx_ring->hw_consumer =
628 (__le32 *)(((char *)addr) + sizeof(struct netxen_ring_ctx));
629
630 /* cmd desc ring */
631 addr = pci_alloc_consistent(pdev, TX_DESC_RINGSIZE(tx_ring),
632 &tx_ring->phys_addr);
633
634 if (addr == NULL) {
635 dev_err(&pdev->dev, "%s: failed to allocate tx desc ring\n",
636 netdev->name);
637 return -ENOMEM;
638 }
639
640 tx_ring->desc_head = (struct cmd_desc_type0 *)addr;
641
642 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
643 rds_ring = &recv_ctx->rds_rings[ring];
644 addr = pci_alloc_consistent(adapter->pdev,
645 RCV_DESC_RINGSIZE(rds_ring),
646 &rds_ring->phys_addr);
647 if (addr == NULL) {
648 dev_err(&pdev->dev,
649 "%s: failed to allocate rds ring [%d]\n",
650 netdev->name, ring);
651 err = -ENOMEM;
652 goto err_out_free;
653 }
654 rds_ring->desc_head = (struct rcv_desc *)addr;
655
656 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
657 rds_ring->crb_rcv_producer =
658 netxen_get_ioaddr(adapter,
659 recv_crb_registers[port].crb_rcv_producer[ring]);
660 }
661
662 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
663 sds_ring = &recv_ctx->sds_rings[ring];
664
665 addr = pci_alloc_consistent(adapter->pdev,
666 STATUS_DESC_RINGSIZE(sds_ring),
667 &sds_ring->phys_addr);
668 if (addr == NULL) {
669 dev_err(&pdev->dev,
670 "%s: failed to allocate sds ring [%d]\n",
671 netdev->name, ring);
672 err = -ENOMEM;
673 goto err_out_free;
674 }
675 sds_ring->desc_head = (struct status_desc *)addr;
676
677 sds_ring->crb_sts_consumer =
678 netxen_get_ioaddr(adapter,
679 recv_crb_registers[port].crb_sts_consumer[ring]);
680
681 sds_ring->crb_intr_mask =
682 netxen_get_ioaddr(adapter,
683 recv_crb_registers[port].sw_int_mask[ring]);
684 }
685
686
687 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
688 if (test_and_set_bit(__NX_FW_ATTACHED, &adapter->state))
689 goto done;
690
691 err = nx_fw_cmd_create_rx_ctx(adapter);
692 if (err)
693 goto err_out_free;
694 err = nx_fw_cmd_create_tx_ctx(adapter);
695 if (err)
696 goto err_out_free;
697 } else {
698 err = netxen_init_old_ctx(adapter);
699 if (err)
700 goto err_out_free;
701 }
702
703 done:
704 return 0;
705
706 err_out_free:
707 netxen_free_hw_resources(adapter);
708 return err;
709 }
710
711 void netxen_free_hw_resources(struct netxen_adapter *adapter)
712 {
713 struct netxen_recv_context *recv_ctx;
714 struct nx_host_rds_ring *rds_ring;
715 struct nx_host_sds_ring *sds_ring;
716 struct nx_host_tx_ring *tx_ring;
717 int ring;
718
719 int port = adapter->portnum;
720
721 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
722 if (!test_and_clear_bit(__NX_FW_ATTACHED, &adapter->state))
723 goto done;
724
725 nx_fw_cmd_destroy_rx_ctx(adapter);
726 nx_fw_cmd_destroy_tx_ctx(adapter);
727 } else {
728 netxen_api_lock(adapter);
729 NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port),
730 NETXEN_CTX_D3_RESET | port);
731 netxen_api_unlock(adapter);
732 }
733
734 /* Allow dma queues to drain after context reset */
735 msleep(20);
736
737 done:
738 recv_ctx = &adapter->recv_ctx;
739
740 if (recv_ctx->hwctx != NULL) {
741 pci_free_consistent(adapter->pdev,
742 sizeof(struct netxen_ring_ctx) +
743 sizeof(uint32_t),
744 recv_ctx->hwctx,
745 recv_ctx->phys_addr);
746 recv_ctx->hwctx = NULL;
747 }
748
749 tx_ring = adapter->tx_ring;
750 if (tx_ring->desc_head != NULL) {
751 pci_free_consistent(adapter->pdev,
752 TX_DESC_RINGSIZE(tx_ring),
753 tx_ring->desc_head, tx_ring->phys_addr);
754 tx_ring->desc_head = NULL;
755 }
756
757 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
758 rds_ring = &recv_ctx->rds_rings[ring];
759
760 if (rds_ring->desc_head != NULL) {
761 pci_free_consistent(adapter->pdev,
762 RCV_DESC_RINGSIZE(rds_ring),
763 rds_ring->desc_head,
764 rds_ring->phys_addr);
765 rds_ring->desc_head = NULL;
766 }
767 }
768
769 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
770 sds_ring = &recv_ctx->sds_rings[ring];
771
772 if (sds_ring->desc_head != NULL) {
773 pci_free_consistent(adapter->pdev,
774 STATUS_DESC_RINGSIZE(sds_ring),
775 sds_ring->desc_head,
776 sds_ring->phys_addr);
777 sds_ring->desc_head = NULL;
778 }
779 }
780 }
781
kernel source for telekom puls (alcatel/mediatek)