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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / myri10ge / myri10ge.c
1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005 - 2007 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/inet_lro.h>
52 #include <linux/ip.h>
53 #include <linux/inet.h>
54 #include <linux/in.h>
55 #include <linux/ethtool.h>
56 #include <linux/firmware.h>
57 #include <linux/delay.h>
58 #include <linux/version.h>
59 #include <linux/timer.h>
60 #include <linux/vmalloc.h>
61 #include <linux/crc32.h>
62 #include <linux/moduleparam.h>
63 #include <linux/io.h>
64 #include <linux/log2.h>
65 #include <net/checksum.h>
66 #include <net/ip.h>
67 #include <net/tcp.h>
68 #include <asm/byteorder.h>
69 #include <asm/io.h>
70 #include <asm/processor.h>
71 #ifdef CONFIG_MTRR
72 #include <asm/mtrr.h>
73 #endif
74
75 #include "myri10ge_mcp.h"
76 #include "myri10ge_mcp_gen_header.h"
77
78 #define MYRI10GE_VERSION_STR "1.3.2-1.269"
79
80 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81 MODULE_AUTHOR("Maintainer: help@myri.com");
82 MODULE_VERSION(MYRI10GE_VERSION_STR);
83 MODULE_LICENSE("Dual BSD/GPL");
84
85 #define MYRI10GE_MAX_ETHER_MTU 9014
86
87 #define MYRI10GE_ETH_STOPPED 0
88 #define MYRI10GE_ETH_STOPPING 1
89 #define MYRI10GE_ETH_STARTING 2
90 #define MYRI10GE_ETH_RUNNING 3
91 #define MYRI10GE_ETH_OPEN_FAILED 4
92
93 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
94 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
95 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96 #define MYRI10GE_LRO_MAX_PKTS 64
97
98 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
99 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
101 #define MYRI10GE_ALLOC_ORDER 0
102 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
105 struct myri10ge_rx_buffer_state {
106 struct page *page;
107 int page_offset;
108 DECLARE_PCI_UNMAP_ADDR(bus)
109 DECLARE_PCI_UNMAP_LEN(len)
110 };
111
112 struct myri10ge_tx_buffer_state {
113 struct sk_buff *skb;
114 int last;
115 DECLARE_PCI_UNMAP_ADDR(bus)
116 DECLARE_PCI_UNMAP_LEN(len)
117 };
118
119 struct myri10ge_cmd {
120 u32 data0;
121 u32 data1;
122 u32 data2;
123 };
124
125 struct myri10ge_rx_buf {
126 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
127 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
128 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
129 struct myri10ge_rx_buffer_state *info;
130 struct page *page;
131 dma_addr_t bus;
132 int page_offset;
133 int cnt;
134 int fill_cnt;
135 int alloc_fail;
136 int mask; /* number of rx slots -1 */
137 int watchdog_needed;
138 };
139
140 struct myri10ge_tx_buf {
141 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
142 u8 __iomem *wc_fifo; /* w/c send fifo address */
143 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
144 char *req_bytes;
145 struct myri10ge_tx_buffer_state *info;
146 int mask; /* number of transmit slots -1 */
147 int boundary; /* boundary transmits cannot cross */
148 int req ____cacheline_aligned; /* transmit slots submitted */
149 int pkt_start; /* packets started */
150 int done ____cacheline_aligned; /* transmit slots completed */
151 int pkt_done; /* packets completed */
152 };
153
154 struct myri10ge_rx_done {
155 struct mcp_slot *entry;
156 dma_addr_t bus;
157 int cnt;
158 int idx;
159 struct net_lro_mgr lro_mgr;
160 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
161 };
162
163 struct myri10ge_priv {
164 int running; /* running? */
165 int csum_flag; /* rx_csums? */
166 struct myri10ge_tx_buf tx; /* transmit ring */
167 struct myri10ge_rx_buf rx_small;
168 struct myri10ge_rx_buf rx_big;
169 struct myri10ge_rx_done rx_done;
170 int small_bytes;
171 int big_bytes;
172 struct net_device *dev;
173 struct napi_struct napi;
174 struct net_device_stats stats;
175 u8 __iomem *sram;
176 int sram_size;
177 unsigned long board_span;
178 unsigned long iomem_base;
179 __be32 __iomem *irq_claim;
180 __be32 __iomem *irq_deassert;
181 char *mac_addr_string;
182 struct mcp_cmd_response *cmd;
183 dma_addr_t cmd_bus;
184 struct mcp_irq_data *fw_stats;
185 dma_addr_t fw_stats_bus;
186 struct pci_dev *pdev;
187 int msi_enabled;
188 __be32 link_state;
189 unsigned int rdma_tags_available;
190 int intr_coal_delay;
191 __be32 __iomem *intr_coal_delay_ptr;
192 int mtrr;
193 int wc_enabled;
194 int wake_queue;
195 int stop_queue;
196 int down_cnt;
197 wait_queue_head_t down_wq;
198 struct work_struct watchdog_work;
199 struct timer_list watchdog_timer;
200 int watchdog_tx_done;
201 int watchdog_tx_req;
202 int watchdog_pause;
203 int watchdog_resets;
204 int tx_linearized;
205 int pause;
206 char *fw_name;
207 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
208 char fw_version[128];
209 int fw_ver_major;
210 int fw_ver_minor;
211 int fw_ver_tiny;
212 int adopted_rx_filter_bug;
213 u8 mac_addr[6]; /* eeprom mac address */
214 unsigned long serial_number;
215 int vendor_specific_offset;
216 int fw_multicast_support;
217 u32 read_dma;
218 u32 write_dma;
219 u32 read_write_dma;
220 u32 link_changes;
221 u32 msg_enable;
222 };
223
224 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
225 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
226
227 static char *myri10ge_fw_name = NULL;
228 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
229 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
230
231 static int myri10ge_ecrc_enable = 1;
232 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
233 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
234
235 static int myri10ge_max_intr_slots = 1024;
236 module_param(myri10ge_max_intr_slots, int, S_IRUGO);
237 MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
238
239 static int myri10ge_small_bytes = -1; /* -1 == auto */
240 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
241 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
242
243 static int myri10ge_msi = 1; /* enable msi by default */
244 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
245 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
246
247 static int myri10ge_intr_coal_delay = 75;
248 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
249 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
250
251 static int myri10ge_flow_control = 1;
252 module_param(myri10ge_flow_control, int, S_IRUGO);
253 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
254
255 static int myri10ge_deassert_wait = 1;
256 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
257 MODULE_PARM_DESC(myri10ge_deassert_wait,
258 "Wait when deasserting legacy interrupts\n");
259
260 static int myri10ge_force_firmware = 0;
261 module_param(myri10ge_force_firmware, int, S_IRUGO);
262 MODULE_PARM_DESC(myri10ge_force_firmware,
263 "Force firmware to assume aligned completions\n");
264
265 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
266 module_param(myri10ge_initial_mtu, int, S_IRUGO);
267 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
268
269 static int myri10ge_napi_weight = 64;
270 module_param(myri10ge_napi_weight, int, S_IRUGO);
271 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
272
273 static int myri10ge_watchdog_timeout = 1;
274 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
275 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
276
277 static int myri10ge_max_irq_loops = 1048576;
278 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
279 MODULE_PARM_DESC(myri10ge_max_irq_loops,
280 "Set stuck legacy IRQ detection threshold\n");
281
282 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
283
284 static int myri10ge_debug = -1; /* defaults above */
285 module_param(myri10ge_debug, int, 0);
286 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
287
288 static int myri10ge_lro = 1;
289 module_param(myri10ge_lro, int, S_IRUGO);
290 MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload\n");
291
292 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
293 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
294 MODULE_PARM_DESC(myri10ge_lro, "Number of LRO packets to be aggregated\n");
295
296 static int myri10ge_fill_thresh = 256;
297 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
298 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
299
300 static int myri10ge_reset_recover = 1;
301
302 static int myri10ge_wcfifo = 0;
303 module_param(myri10ge_wcfifo, int, S_IRUGO);
304 MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
305
306 #define MYRI10GE_FW_OFFSET 1024*1024
307 #define MYRI10GE_HIGHPART_TO_U32(X) \
308 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
309 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
310
311 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
312
313 static void myri10ge_set_multicast_list(struct net_device *dev);
314
315 static inline void put_be32(__be32 val, __be32 __iomem * p)
316 {
317 __raw_writel((__force __u32) val, (__force void __iomem *)p);
318 }
319
320 static int
321 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
322 struct myri10ge_cmd *data, int atomic)
323 {
324 struct mcp_cmd *buf;
325 char buf_bytes[sizeof(*buf) + 8];
326 struct mcp_cmd_response *response = mgp->cmd;
327 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
328 u32 dma_low, dma_high, result, value;
329 int sleep_total = 0;
330
331 /* ensure buf is aligned to 8 bytes */
332 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
333
334 buf->data0 = htonl(data->data0);
335 buf->data1 = htonl(data->data1);
336 buf->data2 = htonl(data->data2);
337 buf->cmd = htonl(cmd);
338 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
339 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
340
341 buf->response_addr.low = htonl(dma_low);
342 buf->response_addr.high = htonl(dma_high);
343 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
344 mb();
345 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
346
347 /* wait up to 15ms. Longest command is the DMA benchmark,
348 * which is capped at 5ms, but runs from a timeout handler
349 * that runs every 7.8ms. So a 15ms timeout leaves us with
350 * a 2.2ms margin
351 */
352 if (atomic) {
353 /* if atomic is set, do not sleep,
354 * and try to get the completion quickly
355 * (1ms will be enough for those commands) */
356 for (sleep_total = 0;
357 sleep_total < 1000
358 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
359 sleep_total += 10)
360 udelay(10);
361 } else {
362 /* use msleep for most command */
363 for (sleep_total = 0;
364 sleep_total < 15
365 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
366 sleep_total++)
367 msleep(1);
368 }
369
370 result = ntohl(response->result);
371 value = ntohl(response->data);
372 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
373 if (result == 0) {
374 data->data0 = value;
375 return 0;
376 } else if (result == MXGEFW_CMD_UNKNOWN) {
377 return -ENOSYS;
378 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
379 return -E2BIG;
380 } else {
381 dev_err(&mgp->pdev->dev,
382 "command %d failed, result = %d\n",
383 cmd, result);
384 return -ENXIO;
385 }
386 }
387
388 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
389 cmd, result);
390 return -EAGAIN;
391 }
392
393 /*
394 * The eeprom strings on the lanaiX have the format
395 * SN=x\0
396 * MAC=x:x:x:x:x:x\0
397 * PT:ddd mmm xx xx:xx:xx xx\0
398 * PV:ddd mmm xx xx:xx:xx xx\0
399 */
400 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
401 {
402 char *ptr, *limit;
403 int i;
404
405 ptr = mgp->eeprom_strings;
406 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
407
408 while (*ptr != '\0' && ptr < limit) {
409 if (memcmp(ptr, "MAC=", 4) == 0) {
410 ptr += 4;
411 mgp->mac_addr_string = ptr;
412 for (i = 0; i < 6; i++) {
413 if ((ptr + 2) > limit)
414 goto abort;
415 mgp->mac_addr[i] =
416 simple_strtoul(ptr, &ptr, 16);
417 ptr += 1;
418 }
419 }
420 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
421 ptr += 3;
422 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
423 }
424 while (ptr < limit && *ptr++) ;
425 }
426
427 return 0;
428
429 abort:
430 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
431 return -ENXIO;
432 }
433
434 /*
435 * Enable or disable periodic RDMAs from the host to make certain
436 * chipsets resend dropped PCIe messages
437 */
438
439 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
440 {
441 char __iomem *submit;
442 __be32 buf[16];
443 u32 dma_low, dma_high;
444 int i;
445
446 /* clear confirmation addr */
447 mgp->cmd->data = 0;
448 mb();
449
450 /* send a rdma command to the PCIe engine, and wait for the
451 * response in the confirmation address. The firmware should
452 * write a -1 there to indicate it is alive and well
453 */
454 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
455 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
456
457 buf[0] = htonl(dma_high); /* confirm addr MSW */
458 buf[1] = htonl(dma_low); /* confirm addr LSW */
459 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
460 buf[3] = htonl(dma_high); /* dummy addr MSW */
461 buf[4] = htonl(dma_low); /* dummy addr LSW */
462 buf[5] = htonl(enable); /* enable? */
463
464 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
465
466 myri10ge_pio_copy(submit, &buf, sizeof(buf));
467 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
468 msleep(1);
469 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
470 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
471 (enable ? "enable" : "disable"));
472 }
473
474 static int
475 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
476 struct mcp_gen_header *hdr)
477 {
478 struct device *dev = &mgp->pdev->dev;
479
480 /* check firmware type */
481 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
482 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
483 return -EINVAL;
484 }
485
486 /* save firmware version for ethtool */
487 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
488
489 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
490 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
491
492 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
493 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
494 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
495 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
496 MXGEFW_VERSION_MINOR);
497 return -EINVAL;
498 }
499 return 0;
500 }
501
502 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
503 {
504 unsigned crc, reread_crc;
505 const struct firmware *fw;
506 struct device *dev = &mgp->pdev->dev;
507 struct mcp_gen_header *hdr;
508 size_t hdr_offset;
509 int status;
510 unsigned i;
511
512 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
513 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
514 mgp->fw_name);
515 status = -EINVAL;
516 goto abort_with_nothing;
517 }
518
519 /* check size */
520
521 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
522 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
523 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
524 status = -EINVAL;
525 goto abort_with_fw;
526 }
527
528 /* check id */
529 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
530 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
531 dev_err(dev, "Bad firmware file\n");
532 status = -EINVAL;
533 goto abort_with_fw;
534 }
535 hdr = (void *)(fw->data + hdr_offset);
536
537 status = myri10ge_validate_firmware(mgp, hdr);
538 if (status != 0)
539 goto abort_with_fw;
540
541 crc = crc32(~0, fw->data, fw->size);
542 for (i = 0; i < fw->size; i += 256) {
543 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
544 fw->data + i,
545 min(256U, (unsigned)(fw->size - i)));
546 mb();
547 readb(mgp->sram);
548 }
549 /* corruption checking is good for parity recovery and buggy chipset */
550 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
551 reread_crc = crc32(~0, fw->data, fw->size);
552 if (crc != reread_crc) {
553 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
554 (unsigned)fw->size, reread_crc, crc);
555 status = -EIO;
556 goto abort_with_fw;
557 }
558 *size = (u32) fw->size;
559
560 abort_with_fw:
561 release_firmware(fw);
562
563 abort_with_nothing:
564 return status;
565 }
566
567 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
568 {
569 struct mcp_gen_header *hdr;
570 struct device *dev = &mgp->pdev->dev;
571 const size_t bytes = sizeof(struct mcp_gen_header);
572 size_t hdr_offset;
573 int status;
574
575 /* find running firmware header */
576 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
577
578 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
579 dev_err(dev, "Running firmware has bad header offset (%d)\n",
580 (int)hdr_offset);
581 return -EIO;
582 }
583
584 /* copy header of running firmware from SRAM to host memory to
585 * validate firmware */
586 hdr = kmalloc(bytes, GFP_KERNEL);
587 if (hdr == NULL) {
588 dev_err(dev, "could not malloc firmware hdr\n");
589 return -ENOMEM;
590 }
591 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
592 status = myri10ge_validate_firmware(mgp, hdr);
593 kfree(hdr);
594
595 /* check to see if adopted firmware has bug where adopting
596 * it will cause broadcasts to be filtered unless the NIC
597 * is kept in ALLMULTI mode */
598 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
599 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
600 mgp->adopted_rx_filter_bug = 1;
601 dev_warn(dev, "Adopting fw %d.%d.%d: "
602 "working around rx filter bug\n",
603 mgp->fw_ver_major, mgp->fw_ver_minor,
604 mgp->fw_ver_tiny);
605 }
606 return status;
607 }
608
609 static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
610 {
611 char __iomem *submit;
612 __be32 buf[16];
613 u32 dma_low, dma_high, size;
614 int status, i;
615
616 size = 0;
617 status = myri10ge_load_hotplug_firmware(mgp, &size);
618 if (status) {
619 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
620
621 /* Do not attempt to adopt firmware if there
622 * was a bad crc */
623 if (status == -EIO)
624 return status;
625
626 status = myri10ge_adopt_running_firmware(mgp);
627 if (status != 0) {
628 dev_err(&mgp->pdev->dev,
629 "failed to adopt running firmware\n");
630 return status;
631 }
632 dev_info(&mgp->pdev->dev,
633 "Successfully adopted running firmware\n");
634 if (mgp->tx.boundary == 4096) {
635 dev_warn(&mgp->pdev->dev,
636 "Using firmware currently running on NIC"
637 ". For optimal\n");
638 dev_warn(&mgp->pdev->dev,
639 "performance consider loading optimized "
640 "firmware\n");
641 dev_warn(&mgp->pdev->dev, "via hotplug\n");
642 }
643
644 mgp->fw_name = "adopted";
645 mgp->tx.boundary = 2048;
646 return status;
647 }
648
649 /* clear confirmation addr */
650 mgp->cmd->data = 0;
651 mb();
652
653 /* send a reload command to the bootstrap MCP, and wait for the
654 * response in the confirmation address. The firmware should
655 * write a -1 there to indicate it is alive and well
656 */
657 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
658 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
659
660 buf[0] = htonl(dma_high); /* confirm addr MSW */
661 buf[1] = htonl(dma_low); /* confirm addr LSW */
662 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
663
664 /* FIX: All newest firmware should un-protect the bottom of
665 * the sram before handoff. However, the very first interfaces
666 * do not. Therefore the handoff copy must skip the first 8 bytes
667 */
668 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
669 buf[4] = htonl(size - 8); /* length of code */
670 buf[5] = htonl(8); /* where to copy to */
671 buf[6] = htonl(0); /* where to jump to */
672
673 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
674
675 myri10ge_pio_copy(submit, &buf, sizeof(buf));
676 mb();
677 msleep(1);
678 mb();
679 i = 0;
680 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
681 msleep(1);
682 i++;
683 }
684 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
685 dev_err(&mgp->pdev->dev, "handoff failed\n");
686 return -ENXIO;
687 }
688 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
689 myri10ge_dummy_rdma(mgp, 1);
690
691 return 0;
692 }
693
694 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
695 {
696 struct myri10ge_cmd cmd;
697 int status;
698
699 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
700 | (addr[2] << 8) | addr[3]);
701
702 cmd.data1 = ((addr[4] << 8) | (addr[5]));
703
704 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
705 return status;
706 }
707
708 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
709 {
710 struct myri10ge_cmd cmd;
711 int status, ctl;
712
713 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
714 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
715
716 if (status) {
717 printk(KERN_ERR
718 "myri10ge: %s: Failed to set flow control mode\n",
719 mgp->dev->name);
720 return status;
721 }
722 mgp->pause = pause;
723 return 0;
724 }
725
726 static void
727 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
728 {
729 struct myri10ge_cmd cmd;
730 int status, ctl;
731
732 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
733 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
734 if (status)
735 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
736 mgp->dev->name);
737 }
738
739 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
740 {
741 struct myri10ge_cmd cmd;
742 int status;
743 u32 len;
744 struct page *dmatest_page;
745 dma_addr_t dmatest_bus;
746 char *test = " ";
747
748 dmatest_page = alloc_page(GFP_KERNEL);
749 if (!dmatest_page)
750 return -ENOMEM;
751 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
752 DMA_BIDIRECTIONAL);
753
754 /* Run a small DMA test.
755 * The magic multipliers to the length tell the firmware
756 * to do DMA read, write, or read+write tests. The
757 * results are returned in cmd.data0. The upper 16
758 * bits or the return is the number of transfers completed.
759 * The lower 16 bits is the time in 0.5us ticks that the
760 * transfers took to complete.
761 */
762
763 len = mgp->tx.boundary;
764
765 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
766 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
767 cmd.data2 = len * 0x10000;
768 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
769 if (status != 0) {
770 test = "read";
771 goto abort;
772 }
773 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
774 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
775 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
776 cmd.data2 = len * 0x1;
777 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
778 if (status != 0) {
779 test = "write";
780 goto abort;
781 }
782 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
783
784 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
785 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
786 cmd.data2 = len * 0x10001;
787 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
788 if (status != 0) {
789 test = "read/write";
790 goto abort;
791 }
792 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
793 (cmd.data0 & 0xffff);
794
795 abort:
796 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
797 put_page(dmatest_page);
798
799 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
800 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
801 test, status);
802
803 return status;
804 }
805
806 static int myri10ge_reset(struct myri10ge_priv *mgp)
807 {
808 struct myri10ge_cmd cmd;
809 int status;
810 size_t bytes;
811
812 /* try to send a reset command to the card to see if it
813 * is alive */
814 memset(&cmd, 0, sizeof(cmd));
815 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
816 if (status != 0) {
817 dev_err(&mgp->pdev->dev, "failed reset\n");
818 return -ENXIO;
819 }
820
821 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
822
823 /* Now exchange information about interrupts */
824
825 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
826 memset(mgp->rx_done.entry, 0, bytes);
827 cmd.data0 = (u32) bytes;
828 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
829 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
830 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
831 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
832
833 status |=
834 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
835 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
836 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
837 &cmd, 0);
838 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
839
840 status |= myri10ge_send_cmd
841 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
842 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
843 if (status != 0) {
844 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
845 return status;
846 }
847 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
848
849 memset(mgp->rx_done.entry, 0, bytes);
850
851 /* reset mcp/driver shared state back to 0 */
852 mgp->tx.req = 0;
853 mgp->tx.done = 0;
854 mgp->tx.pkt_start = 0;
855 mgp->tx.pkt_done = 0;
856 mgp->rx_big.cnt = 0;
857 mgp->rx_small.cnt = 0;
858 mgp->rx_done.idx = 0;
859 mgp->rx_done.cnt = 0;
860 mgp->link_changes = 0;
861 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
862 myri10ge_change_pause(mgp, mgp->pause);
863 myri10ge_set_multicast_list(mgp->dev);
864 return status;
865 }
866
867 static inline void
868 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
869 struct mcp_kreq_ether_recv *src)
870 {
871 __be32 low;
872
873 low = src->addr_low;
874 src->addr_low = htonl(DMA_32BIT_MASK);
875 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
876 mb();
877 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
878 mb();
879 src->addr_low = low;
880 put_be32(low, &dst->addr_low);
881 mb();
882 }
883
884 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
885 {
886 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
887
888 if ((skb->protocol == htons(ETH_P_8021Q)) &&
889 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
890 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
891 skb->csum = hw_csum;
892 skb->ip_summed = CHECKSUM_COMPLETE;
893 }
894 }
895
896 static inline void
897 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
898 struct skb_frag_struct *rx_frags, int len, int hlen)
899 {
900 struct skb_frag_struct *skb_frags;
901
902 skb->len = skb->data_len = len;
903 skb->truesize = len + sizeof(struct sk_buff);
904 /* attach the page(s) */
905
906 skb_frags = skb_shinfo(skb)->frags;
907 while (len > 0) {
908 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
909 len -= rx_frags->size;
910 skb_frags++;
911 rx_frags++;
912 skb_shinfo(skb)->nr_frags++;
913 }
914
915 /* pskb_may_pull is not available in irq context, but
916 * skb_pull() (for ether_pad and eth_type_trans()) requires
917 * the beginning of the packet in skb_headlen(), move it
918 * manually */
919 skb_copy_to_linear_data(skb, va, hlen);
920 skb_shinfo(skb)->frags[0].page_offset += hlen;
921 skb_shinfo(skb)->frags[0].size -= hlen;
922 skb->data_len -= hlen;
923 skb->tail += hlen;
924 skb_pull(skb, MXGEFW_PAD);
925 }
926
927 static void
928 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
929 int bytes, int watchdog)
930 {
931 struct page *page;
932 int idx;
933
934 if (unlikely(rx->watchdog_needed && !watchdog))
935 return;
936
937 /* try to refill entire ring */
938 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
939 idx = rx->fill_cnt & rx->mask;
940 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
941 /* we can use part of previous page */
942 get_page(rx->page);
943 } else {
944 /* we need a new page */
945 page =
946 alloc_pages(GFP_ATOMIC | __GFP_COMP,
947 MYRI10GE_ALLOC_ORDER);
948 if (unlikely(page == NULL)) {
949 if (rx->fill_cnt - rx->cnt < 16)
950 rx->watchdog_needed = 1;
951 return;
952 }
953 rx->page = page;
954 rx->page_offset = 0;
955 rx->bus = pci_map_page(mgp->pdev, page, 0,
956 MYRI10GE_ALLOC_SIZE,
957 PCI_DMA_FROMDEVICE);
958 }
959 rx->info[idx].page = rx->page;
960 rx->info[idx].page_offset = rx->page_offset;
961 /* note that this is the address of the start of the
962 * page */
963 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
964 rx->shadow[idx].addr_low =
965 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
966 rx->shadow[idx].addr_high =
967 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
968
969 /* start next packet on a cacheline boundary */
970 rx->page_offset += SKB_DATA_ALIGN(bytes);
971
972 #if MYRI10GE_ALLOC_SIZE > 4096
973 /* don't cross a 4KB boundary */
974 if ((rx->page_offset >> 12) !=
975 ((rx->page_offset + bytes - 1) >> 12))
976 rx->page_offset = (rx->page_offset + 4096) & ~4095;
977 #endif
978 rx->fill_cnt++;
979
980 /* copy 8 descriptors to the firmware at a time */
981 if ((idx & 7) == 7) {
982 if (rx->wc_fifo == NULL)
983 myri10ge_submit_8rx(&rx->lanai[idx - 7],
984 &rx->shadow[idx - 7]);
985 else {
986 mb();
987 myri10ge_pio_copy(rx->wc_fifo,
988 &rx->shadow[idx - 7], 64);
989 }
990 }
991 }
992 }
993
994 static inline void
995 myri10ge_unmap_rx_page(struct pci_dev *pdev,
996 struct myri10ge_rx_buffer_state *info, int bytes)
997 {
998 /* unmap the recvd page if we're the only or last user of it */
999 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1000 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1001 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1002 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1003 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1004 }
1005 }
1006
1007 #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1008 * page into an skb */
1009
1010 static inline int
1011 myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1012 int bytes, int len, __wsum csum)
1013 {
1014 struct sk_buff *skb;
1015 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1016 int i, idx, hlen, remainder;
1017 struct pci_dev *pdev = mgp->pdev;
1018 struct net_device *dev = mgp->dev;
1019 u8 *va;
1020
1021 len += MXGEFW_PAD;
1022 idx = rx->cnt & rx->mask;
1023 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1024 prefetch(va);
1025 /* Fill skb_frag_struct(s) with data from our receive */
1026 for (i = 0, remainder = len; remainder > 0; i++) {
1027 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1028 rx_frags[i].page = rx->info[idx].page;
1029 rx_frags[i].page_offset = rx->info[idx].page_offset;
1030 if (remainder < MYRI10GE_ALLOC_SIZE)
1031 rx_frags[i].size = remainder;
1032 else
1033 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1034 rx->cnt++;
1035 idx = rx->cnt & rx->mask;
1036 remainder -= MYRI10GE_ALLOC_SIZE;
1037 }
1038
1039 if (mgp->csum_flag && myri10ge_lro) {
1040 rx_frags[0].page_offset += MXGEFW_PAD;
1041 rx_frags[0].size -= MXGEFW_PAD;
1042 len -= MXGEFW_PAD;
1043 lro_receive_frags(&mgp->rx_done.lro_mgr, rx_frags,
1044 len, len, (void *)(unsigned long)csum, csum);
1045 return 1;
1046 }
1047
1048 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1049
1050 /* allocate an skb to attach the page(s) to. */
1051
1052 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1053 if (unlikely(skb == NULL)) {
1054 mgp->stats.rx_dropped++;
1055 do {
1056 i--;
1057 put_page(rx_frags[i].page);
1058 } while (i != 0);
1059 return 0;
1060 }
1061
1062 /* Attach the pages to the skb, and trim off any padding */
1063 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1064 if (skb_shinfo(skb)->frags[0].size <= 0) {
1065 put_page(skb_shinfo(skb)->frags[0].page);
1066 skb_shinfo(skb)->nr_frags = 0;
1067 }
1068 skb->protocol = eth_type_trans(skb, dev);
1069
1070 if (mgp->csum_flag) {
1071 if ((skb->protocol == htons(ETH_P_IP)) ||
1072 (skb->protocol == htons(ETH_P_IPV6))) {
1073 skb->csum = csum;
1074 skb->ip_summed = CHECKSUM_COMPLETE;
1075 } else
1076 myri10ge_vlan_ip_csum(skb, csum);
1077 }
1078 netif_receive_skb(skb);
1079 dev->last_rx = jiffies;
1080 return 1;
1081 }
1082
1083 static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1084 {
1085 struct pci_dev *pdev = mgp->pdev;
1086 struct myri10ge_tx_buf *tx = &mgp->tx;
1087 struct sk_buff *skb;
1088 int idx, len;
1089
1090 while (tx->pkt_done != mcp_index) {
1091 idx = tx->done & tx->mask;
1092 skb = tx->info[idx].skb;
1093
1094 /* Mark as free */
1095 tx->info[idx].skb = NULL;
1096 if (tx->info[idx].last) {
1097 tx->pkt_done++;
1098 tx->info[idx].last = 0;
1099 }
1100 tx->done++;
1101 len = pci_unmap_len(&tx->info[idx], len);
1102 pci_unmap_len_set(&tx->info[idx], len, 0);
1103 if (skb) {
1104 mgp->stats.tx_bytes += skb->len;
1105 mgp->stats.tx_packets++;
1106 dev_kfree_skb_irq(skb);
1107 if (len)
1108 pci_unmap_single(pdev,
1109 pci_unmap_addr(&tx->info[idx],
1110 bus), len,
1111 PCI_DMA_TODEVICE);
1112 } else {
1113 if (len)
1114 pci_unmap_page(pdev,
1115 pci_unmap_addr(&tx->info[idx],
1116 bus), len,
1117 PCI_DMA_TODEVICE);
1118 }
1119 }
1120 /* start the queue if we've stopped it */
1121 if (netif_queue_stopped(mgp->dev)
1122 && tx->req - tx->done < (tx->mask >> 1)) {
1123 mgp->wake_queue++;
1124 netif_wake_queue(mgp->dev);
1125 }
1126 }
1127
1128 static inline int myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int budget)
1129 {
1130 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1131 unsigned long rx_bytes = 0;
1132 unsigned long rx_packets = 0;
1133 unsigned long rx_ok;
1134
1135 int idx = rx_done->idx;
1136 int cnt = rx_done->cnt;
1137 int work_done = 0;
1138 u16 length;
1139 __wsum checksum;
1140
1141 while (rx_done->entry[idx].length != 0 && work_done++ < budget) {
1142 length = ntohs(rx_done->entry[idx].length);
1143 rx_done->entry[idx].length = 0;
1144 checksum = csum_unfold(rx_done->entry[idx].checksum);
1145 if (length <= mgp->small_bytes)
1146 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1147 mgp->small_bytes,
1148 length, checksum);
1149 else
1150 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1151 mgp->big_bytes,
1152 length, checksum);
1153 rx_packets += rx_ok;
1154 rx_bytes += rx_ok * (unsigned long)length;
1155 cnt++;
1156 idx = cnt & (myri10ge_max_intr_slots - 1);
1157 }
1158 rx_done->idx = idx;
1159 rx_done->cnt = cnt;
1160 mgp->stats.rx_packets += rx_packets;
1161 mgp->stats.rx_bytes += rx_bytes;
1162
1163 if (myri10ge_lro)
1164 lro_flush_all(&rx_done->lro_mgr);
1165
1166 /* restock receive rings if needed */
1167 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1168 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1169 mgp->small_bytes + MXGEFW_PAD, 0);
1170 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1171 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1172
1173 return work_done;
1174 }
1175
1176 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1177 {
1178 struct mcp_irq_data *stats = mgp->fw_stats;
1179
1180 if (unlikely(stats->stats_updated)) {
1181 unsigned link_up = ntohl(stats->link_up);
1182 if (mgp->link_state != link_up) {
1183 mgp->link_state = link_up;
1184
1185 if (mgp->link_state == MXGEFW_LINK_UP) {
1186 if (netif_msg_link(mgp))
1187 printk(KERN_INFO
1188 "myri10ge: %s: link up\n",
1189 mgp->dev->name);
1190 netif_carrier_on(mgp->dev);
1191 mgp->link_changes++;
1192 } else {
1193 if (netif_msg_link(mgp))
1194 printk(KERN_INFO
1195 "myri10ge: %s: link %s\n",
1196 mgp->dev->name,
1197 (link_up == MXGEFW_LINK_MYRINET ?
1198 "mismatch (Myrinet detected)" :
1199 "down"));
1200 netif_carrier_off(mgp->dev);
1201 mgp->link_changes++;
1202 }
1203 }
1204 if (mgp->rdma_tags_available !=
1205 ntohl(mgp->fw_stats->rdma_tags_available)) {
1206 mgp->rdma_tags_available =
1207 ntohl(mgp->fw_stats->rdma_tags_available);
1208 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1209 "%d tags left\n", mgp->dev->name,
1210 mgp->rdma_tags_available);
1211 }
1212 mgp->down_cnt += stats->link_down;
1213 if (stats->link_down)
1214 wake_up(&mgp->down_wq);
1215 }
1216 }
1217
1218 static int myri10ge_poll(struct napi_struct *napi, int budget)
1219 {
1220 struct myri10ge_priv *mgp = container_of(napi, struct myri10ge_priv, napi);
1221 struct net_device *netdev = mgp->dev;
1222 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1223 int work_done;
1224
1225 /* process as many rx events as NAPI will allow */
1226 work_done = myri10ge_clean_rx_done(mgp, budget);
1227
1228 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1229 netif_rx_complete(netdev, napi);
1230 put_be32(htonl(3), mgp->irq_claim);
1231 }
1232 return work_done;
1233 }
1234
1235 static irqreturn_t myri10ge_intr(int irq, void *arg)
1236 {
1237 struct myri10ge_priv *mgp = arg;
1238 struct mcp_irq_data *stats = mgp->fw_stats;
1239 struct myri10ge_tx_buf *tx = &mgp->tx;
1240 u32 send_done_count;
1241 int i;
1242
1243 /* make sure it is our IRQ, and that the DMA has finished */
1244 if (unlikely(!stats->valid))
1245 return (IRQ_NONE);
1246
1247 /* low bit indicates receives are present, so schedule
1248 * napi poll handler */
1249 if (stats->valid & 1)
1250 netif_rx_schedule(mgp->dev, &mgp->napi);
1251
1252 if (!mgp->msi_enabled) {
1253 put_be32(0, mgp->irq_deassert);
1254 if (!myri10ge_deassert_wait)
1255 stats->valid = 0;
1256 mb();
1257 } else
1258 stats->valid = 0;
1259
1260 /* Wait for IRQ line to go low, if using INTx */
1261 i = 0;
1262 while (1) {
1263 i++;
1264 /* check for transmit completes and receives */
1265 send_done_count = ntohl(stats->send_done_count);
1266 if (send_done_count != tx->pkt_done)
1267 myri10ge_tx_done(mgp, (int)send_done_count);
1268 if (unlikely(i > myri10ge_max_irq_loops)) {
1269 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1270 mgp->dev->name);
1271 stats->valid = 0;
1272 schedule_work(&mgp->watchdog_work);
1273 }
1274 if (likely(stats->valid == 0))
1275 break;
1276 cpu_relax();
1277 barrier();
1278 }
1279
1280 myri10ge_check_statblock(mgp);
1281
1282 put_be32(htonl(3), mgp->irq_claim + 1);
1283 return (IRQ_HANDLED);
1284 }
1285
1286 static int
1287 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1288 {
1289 cmd->autoneg = AUTONEG_DISABLE;
1290 cmd->speed = SPEED_10000;
1291 cmd->duplex = DUPLEX_FULL;
1292 return 0;
1293 }
1294
1295 static void
1296 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1297 {
1298 struct myri10ge_priv *mgp = netdev_priv(netdev);
1299
1300 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1301 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1302 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1303 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1304 }
1305
1306 static int
1307 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1308 {
1309 struct myri10ge_priv *mgp = netdev_priv(netdev);
1310 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1311 return 0;
1312 }
1313
1314 static int
1315 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1316 {
1317 struct myri10ge_priv *mgp = netdev_priv(netdev);
1318
1319 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1320 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1321 return 0;
1322 }
1323
1324 static void
1325 myri10ge_get_pauseparam(struct net_device *netdev,
1326 struct ethtool_pauseparam *pause)
1327 {
1328 struct myri10ge_priv *mgp = netdev_priv(netdev);
1329
1330 pause->autoneg = 0;
1331 pause->rx_pause = mgp->pause;
1332 pause->tx_pause = mgp->pause;
1333 }
1334
1335 static int
1336 myri10ge_set_pauseparam(struct net_device *netdev,
1337 struct ethtool_pauseparam *pause)
1338 {
1339 struct myri10ge_priv *mgp = netdev_priv(netdev);
1340
1341 if (pause->tx_pause != mgp->pause)
1342 return myri10ge_change_pause(mgp, pause->tx_pause);
1343 if (pause->rx_pause != mgp->pause)
1344 return myri10ge_change_pause(mgp, pause->tx_pause);
1345 if (pause->autoneg != 0)
1346 return -EINVAL;
1347 return 0;
1348 }
1349
1350 static void
1351 myri10ge_get_ringparam(struct net_device *netdev,
1352 struct ethtool_ringparam *ring)
1353 {
1354 struct myri10ge_priv *mgp = netdev_priv(netdev);
1355
1356 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1357 ring->rx_max_pending = mgp->rx_big.mask + 1;
1358 ring->rx_jumbo_max_pending = 0;
1359 ring->tx_max_pending = mgp->rx_small.mask + 1;
1360 ring->rx_mini_pending = ring->rx_mini_max_pending;
1361 ring->rx_pending = ring->rx_max_pending;
1362 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1363 ring->tx_pending = ring->tx_max_pending;
1364 }
1365
1366 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1367 {
1368 struct myri10ge_priv *mgp = netdev_priv(netdev);
1369 if (mgp->csum_flag)
1370 return 1;
1371 else
1372 return 0;
1373 }
1374
1375 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1376 {
1377 struct myri10ge_priv *mgp = netdev_priv(netdev);
1378 if (csum_enabled)
1379 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1380 else
1381 mgp->csum_flag = 0;
1382 return 0;
1383 }
1384
1385 static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1386 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1387 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1388 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1389 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1390 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1391 "tx_heartbeat_errors", "tx_window_errors",
1392 /* device-specific stats */
1393 "tx_boundary", "WC", "irq", "MSI",
1394 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1395 "serial_number", "tx_pkt_start", "tx_pkt_done",
1396 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1397 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
1398 "link_changes", "link_up", "dropped_link_overflow",
1399 "dropped_link_error_or_filtered",
1400 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1401 "dropped_unicast_filtered", "dropped_multicast_filtered",
1402 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1403 "dropped_no_big_buffer", "LRO aggregated", "LRO flushed",
1404 "LRO avg aggr", "LRO no_desc"
1405 };
1406
1407 #define MYRI10GE_NET_STATS_LEN 21
1408 #define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1409
1410 static void
1411 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1412 {
1413 switch (stringset) {
1414 case ETH_SS_STATS:
1415 memcpy(data, *myri10ge_gstrings_stats,
1416 sizeof(myri10ge_gstrings_stats));
1417 break;
1418 }
1419 }
1420
1421 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1422 {
1423 switch (sset) {
1424 case ETH_SS_STATS:
1425 return MYRI10GE_STATS_LEN;
1426 default:
1427 return -EOPNOTSUPP;
1428 }
1429 }
1430
1431 static void
1432 myri10ge_get_ethtool_stats(struct net_device *netdev,
1433 struct ethtool_stats *stats, u64 * data)
1434 {
1435 struct myri10ge_priv *mgp = netdev_priv(netdev);
1436 int i;
1437
1438 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1439 data[i] = ((unsigned long *)&mgp->stats)[i];
1440
1441 data[i++] = (unsigned int)mgp->tx.boundary;
1442 data[i++] = (unsigned int)mgp->wc_enabled;
1443 data[i++] = (unsigned int)mgp->pdev->irq;
1444 data[i++] = (unsigned int)mgp->msi_enabled;
1445 data[i++] = (unsigned int)mgp->read_dma;
1446 data[i++] = (unsigned int)mgp->write_dma;
1447 data[i++] = (unsigned int)mgp->read_write_dma;
1448 data[i++] = (unsigned int)mgp->serial_number;
1449 data[i++] = (unsigned int)mgp->tx.pkt_start;
1450 data[i++] = (unsigned int)mgp->tx.pkt_done;
1451 data[i++] = (unsigned int)mgp->tx.req;
1452 data[i++] = (unsigned int)mgp->tx.done;
1453 data[i++] = (unsigned int)mgp->rx_small.cnt;
1454 data[i++] = (unsigned int)mgp->rx_big.cnt;
1455 data[i++] = (unsigned int)mgp->wake_queue;
1456 data[i++] = (unsigned int)mgp->stop_queue;
1457 data[i++] = (unsigned int)mgp->watchdog_resets;
1458 data[i++] = (unsigned int)mgp->tx_linearized;
1459 data[i++] = (unsigned int)mgp->link_changes;
1460 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1461 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1462 data[i++] =
1463 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
1464 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_pause);
1465 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_phy);
1466 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_crc32);
1467 data[i++] =
1468 (unsigned int)ntohl(mgp->fw_stats->dropped_unicast_filtered);
1469 data[i++] =
1470 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
1471 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1472 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1473 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1474 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1475 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated;
1476 data[i++] = mgp->rx_done.lro_mgr.stats.flushed;
1477 if (mgp->rx_done.lro_mgr.stats.flushed)
1478 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated /
1479 mgp->rx_done.lro_mgr.stats.flushed;
1480 else
1481 data[i++] = 0;
1482 data[i++] = mgp->rx_done.lro_mgr.stats.no_desc;
1483 }
1484
1485 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1486 {
1487 struct myri10ge_priv *mgp = netdev_priv(netdev);
1488 mgp->msg_enable = value;
1489 }
1490
1491 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1492 {
1493 struct myri10ge_priv *mgp = netdev_priv(netdev);
1494 return mgp->msg_enable;
1495 }
1496
1497 static const struct ethtool_ops myri10ge_ethtool_ops = {
1498 .get_settings = myri10ge_get_settings,
1499 .get_drvinfo = myri10ge_get_drvinfo,
1500 .get_coalesce = myri10ge_get_coalesce,
1501 .set_coalesce = myri10ge_set_coalesce,
1502 .get_pauseparam = myri10ge_get_pauseparam,
1503 .set_pauseparam = myri10ge_set_pauseparam,
1504 .get_ringparam = myri10ge_get_ringparam,
1505 .get_rx_csum = myri10ge_get_rx_csum,
1506 .set_rx_csum = myri10ge_set_rx_csum,
1507 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1508 .set_sg = ethtool_op_set_sg,
1509 .set_tso = ethtool_op_set_tso,
1510 .get_link = ethtool_op_get_link,
1511 .get_strings = myri10ge_get_strings,
1512 .get_sset_count = myri10ge_get_sset_count,
1513 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1514 .set_msglevel = myri10ge_set_msglevel,
1515 .get_msglevel = myri10ge_get_msglevel
1516 };
1517
1518 static int myri10ge_allocate_rings(struct net_device *dev)
1519 {
1520 struct myri10ge_priv *mgp;
1521 struct myri10ge_cmd cmd;
1522 int tx_ring_size, rx_ring_size;
1523 int tx_ring_entries, rx_ring_entries;
1524 int i, status;
1525 size_t bytes;
1526
1527 mgp = netdev_priv(dev);
1528
1529 /* get ring sizes */
1530
1531 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1532 tx_ring_size = cmd.data0;
1533 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1534 if (status != 0)
1535 return status;
1536 rx_ring_size = cmd.data0;
1537
1538 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1539 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1540 mgp->tx.mask = tx_ring_entries - 1;
1541 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1542
1543 status = -ENOMEM;
1544
1545 /* allocate the host shadow rings */
1546
1547 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1548 * sizeof(*mgp->tx.req_list);
1549 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1550 if (mgp->tx.req_bytes == NULL)
1551 goto abort_with_nothing;
1552
1553 /* ensure req_list entries are aligned to 8 bytes */
1554 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1555 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1556
1557 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1558 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1559 if (mgp->rx_small.shadow == NULL)
1560 goto abort_with_tx_req_bytes;
1561
1562 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1563 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1564 if (mgp->rx_big.shadow == NULL)
1565 goto abort_with_rx_small_shadow;
1566
1567 /* allocate the host info rings */
1568
1569 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1570 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1571 if (mgp->tx.info == NULL)
1572 goto abort_with_rx_big_shadow;
1573
1574 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1575 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1576 if (mgp->rx_small.info == NULL)
1577 goto abort_with_tx_info;
1578
1579 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1580 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1581 if (mgp->rx_big.info == NULL)
1582 goto abort_with_rx_small_info;
1583
1584 /* Fill the receive rings */
1585 mgp->rx_big.cnt = 0;
1586 mgp->rx_small.cnt = 0;
1587 mgp->rx_big.fill_cnt = 0;
1588 mgp->rx_small.fill_cnt = 0;
1589 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1590 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1591 mgp->rx_small.watchdog_needed = 0;
1592 mgp->rx_big.watchdog_needed = 0;
1593 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1594 mgp->small_bytes + MXGEFW_PAD, 0);
1595
1596 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1597 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1598 dev->name, mgp->rx_small.fill_cnt);
1599 goto abort_with_rx_small_ring;
1600 }
1601
1602 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1603 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1604 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1605 dev->name, mgp->rx_big.fill_cnt);
1606 goto abort_with_rx_big_ring;
1607 }
1608
1609 return 0;
1610
1611 abort_with_rx_big_ring:
1612 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1613 int idx = i & mgp->rx_big.mask;
1614 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1615 mgp->big_bytes);
1616 put_page(mgp->rx_big.info[idx].page);
1617 }
1618
1619 abort_with_rx_small_ring:
1620 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1621 int idx = i & mgp->rx_small.mask;
1622 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1623 mgp->small_bytes + MXGEFW_PAD);
1624 put_page(mgp->rx_small.info[idx].page);
1625 }
1626
1627 kfree(mgp->rx_big.info);
1628
1629 abort_with_rx_small_info:
1630 kfree(mgp->rx_small.info);
1631
1632 abort_with_tx_info:
1633 kfree(mgp->tx.info);
1634
1635 abort_with_rx_big_shadow:
1636 kfree(mgp->rx_big.shadow);
1637
1638 abort_with_rx_small_shadow:
1639 kfree(mgp->rx_small.shadow);
1640
1641 abort_with_tx_req_bytes:
1642 kfree(mgp->tx.req_bytes);
1643 mgp->tx.req_bytes = NULL;
1644 mgp->tx.req_list = NULL;
1645
1646 abort_with_nothing:
1647 return status;
1648 }
1649
1650 static void myri10ge_free_rings(struct net_device *dev)
1651 {
1652 struct myri10ge_priv *mgp;
1653 struct sk_buff *skb;
1654 struct myri10ge_tx_buf *tx;
1655 int i, len, idx;
1656
1657 mgp = netdev_priv(dev);
1658
1659 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1660 idx = i & mgp->rx_big.mask;
1661 if (i == mgp->rx_big.fill_cnt - 1)
1662 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1663 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1664 mgp->big_bytes);
1665 put_page(mgp->rx_big.info[idx].page);
1666 }
1667
1668 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1669 idx = i & mgp->rx_small.mask;
1670 if (i == mgp->rx_small.fill_cnt - 1)
1671 mgp->rx_small.info[idx].page_offset =
1672 MYRI10GE_ALLOC_SIZE;
1673 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1674 mgp->small_bytes + MXGEFW_PAD);
1675 put_page(mgp->rx_small.info[idx].page);
1676 }
1677 tx = &mgp->tx;
1678 while (tx->done != tx->req) {
1679 idx = tx->done & tx->mask;
1680 skb = tx->info[idx].skb;
1681
1682 /* Mark as free */
1683 tx->info[idx].skb = NULL;
1684 tx->done++;
1685 len = pci_unmap_len(&tx->info[idx], len);
1686 pci_unmap_len_set(&tx->info[idx], len, 0);
1687 if (skb) {
1688 mgp->stats.tx_dropped++;
1689 dev_kfree_skb_any(skb);
1690 if (len)
1691 pci_unmap_single(mgp->pdev,
1692 pci_unmap_addr(&tx->info[idx],
1693 bus), len,
1694 PCI_DMA_TODEVICE);
1695 } else {
1696 if (len)
1697 pci_unmap_page(mgp->pdev,
1698 pci_unmap_addr(&tx->info[idx],
1699 bus), len,
1700 PCI_DMA_TODEVICE);
1701 }
1702 }
1703 kfree(mgp->rx_big.info);
1704
1705 kfree(mgp->rx_small.info);
1706
1707 kfree(mgp->tx.info);
1708
1709 kfree(mgp->rx_big.shadow);
1710
1711 kfree(mgp->rx_small.shadow);
1712
1713 kfree(mgp->tx.req_bytes);
1714 mgp->tx.req_bytes = NULL;
1715 mgp->tx.req_list = NULL;
1716 }
1717
1718 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1719 {
1720 struct pci_dev *pdev = mgp->pdev;
1721 int status;
1722
1723 if (myri10ge_msi) {
1724 status = pci_enable_msi(pdev);
1725 if (status != 0)
1726 dev_err(&pdev->dev,
1727 "Error %d setting up MSI; falling back to xPIC\n",
1728 status);
1729 else
1730 mgp->msi_enabled = 1;
1731 } else {
1732 mgp->msi_enabled = 0;
1733 }
1734 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1735 mgp->dev->name, mgp);
1736 if (status != 0) {
1737 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1738 if (mgp->msi_enabled)
1739 pci_disable_msi(pdev);
1740 }
1741 return status;
1742 }
1743
1744 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1745 {
1746 struct pci_dev *pdev = mgp->pdev;
1747
1748 free_irq(pdev->irq, mgp);
1749 if (mgp->msi_enabled)
1750 pci_disable_msi(pdev);
1751 }
1752
1753 static int
1754 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
1755 void **ip_hdr, void **tcpudp_hdr,
1756 u64 * hdr_flags, void *priv)
1757 {
1758 struct ethhdr *eh;
1759 struct vlan_ethhdr *veh;
1760 struct iphdr *iph;
1761 u8 *va = page_address(frag->page) + frag->page_offset;
1762 unsigned long ll_hlen;
1763 __wsum csum = (__wsum) (unsigned long)priv;
1764
1765 /* find the mac header, aborting if not IPv4 */
1766
1767 eh = (struct ethhdr *)va;
1768 *mac_hdr = eh;
1769 ll_hlen = ETH_HLEN;
1770 if (eh->h_proto != htons(ETH_P_IP)) {
1771 if (eh->h_proto == htons(ETH_P_8021Q)) {
1772 veh = (struct vlan_ethhdr *)va;
1773 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
1774 return -1;
1775
1776 ll_hlen += VLAN_HLEN;
1777
1778 /*
1779 * HW checksum starts ETH_HLEN bytes into
1780 * frame, so we must subtract off the VLAN
1781 * header's checksum before csum can be used
1782 */
1783 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
1784 VLAN_HLEN, 0));
1785 } else {
1786 return -1;
1787 }
1788 }
1789 *hdr_flags = LRO_IPV4;
1790
1791 iph = (struct iphdr *)(va + ll_hlen);
1792 *ip_hdr = iph;
1793 if (iph->protocol != IPPROTO_TCP)
1794 return -1;
1795 *hdr_flags |= LRO_TCP;
1796 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
1797
1798 /* verify the IP checksum */
1799 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
1800 return -1;
1801
1802 /* verify the checksum */
1803 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
1804 ntohs(iph->tot_len) - (iph->ihl << 2),
1805 IPPROTO_TCP, csum)))
1806 return -1;
1807
1808 return 0;
1809 }
1810
1811 static int myri10ge_open(struct net_device *dev)
1812 {
1813 struct myri10ge_priv *mgp;
1814 struct myri10ge_cmd cmd;
1815 struct net_lro_mgr *lro_mgr;
1816 int status, big_pow2;
1817
1818 mgp = netdev_priv(dev);
1819
1820 if (mgp->running != MYRI10GE_ETH_STOPPED)
1821 return -EBUSY;
1822
1823 mgp->running = MYRI10GE_ETH_STARTING;
1824 status = myri10ge_reset(mgp);
1825 if (status != 0) {
1826 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
1827 goto abort_with_nothing;
1828 }
1829
1830 status = myri10ge_request_irq(mgp);
1831 if (status != 0)
1832 goto abort_with_nothing;
1833
1834 /* decide what small buffer size to use. For good TCP rx
1835 * performance, it is important to not receive 1514 byte
1836 * frames into jumbo buffers, as it confuses the socket buffer
1837 * accounting code, leading to drops and erratic performance.
1838 */
1839
1840 if (dev->mtu <= ETH_DATA_LEN)
1841 /* enough for a TCP header */
1842 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1843 ? (128 - MXGEFW_PAD)
1844 : (SMP_CACHE_BYTES - MXGEFW_PAD);
1845 else
1846 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1847 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
1848
1849 /* Override the small buffer size? */
1850 if (myri10ge_small_bytes > 0)
1851 mgp->small_bytes = myri10ge_small_bytes;
1852
1853 /* get the lanai pointers to the send and receive rings */
1854
1855 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1856 mgp->tx.lanai =
1857 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1858
1859 status |=
1860 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1861 mgp->rx_small.lanai =
1862 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1863
1864 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1865 mgp->rx_big.lanai =
1866 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1867
1868 if (status != 0) {
1869 printk(KERN_ERR
1870 "myri10ge: %s: failed to get ring sizes or locations\n",
1871 dev->name);
1872 mgp->running = MYRI10GE_ETH_STOPPED;
1873 goto abort_with_irq;
1874 }
1875
1876 if (myri10ge_wcfifo && mgp->wc_enabled) {
1877 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1878 mgp->rx_small.wc_fifo =
1879 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1880 mgp->rx_big.wc_fifo =
1881 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
1882 } else {
1883 mgp->tx.wc_fifo = NULL;
1884 mgp->rx_small.wc_fifo = NULL;
1885 mgp->rx_big.wc_fifo = NULL;
1886 }
1887
1888 /* Firmware needs the big buff size as a power of 2. Lie and
1889 * tell him the buffer is larger, because we only use 1
1890 * buffer/pkt, and the mtu will prevent overruns.
1891 */
1892 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
1893 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
1894 while (!is_power_of_2(big_pow2))
1895 big_pow2++;
1896 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
1897 } else {
1898 big_pow2 = MYRI10GE_ALLOC_SIZE;
1899 mgp->big_bytes = big_pow2;
1900 }
1901
1902 status = myri10ge_allocate_rings(dev);
1903 if (status != 0)
1904 goto abort_with_irq;
1905
1906 /* now give firmware buffers sizes, and MTU */
1907 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1908 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1909 cmd.data0 = mgp->small_bytes;
1910 status |=
1911 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1912 cmd.data0 = big_pow2;
1913 status |=
1914 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1915 if (status) {
1916 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1917 dev->name);
1918 goto abort_with_rings;
1919 }
1920
1921 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1922 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
1923 cmd.data2 = sizeof(struct mcp_irq_data);
1924 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1925 if (status == -ENOSYS) {
1926 dma_addr_t bus = mgp->fw_stats_bus;
1927 bus += offsetof(struct mcp_irq_data, send_done_count);
1928 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1929 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1930 status = myri10ge_send_cmd(mgp,
1931 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1932 &cmd, 0);
1933 /* Firmware cannot support multicast without STATS_DMA_V2 */
1934 mgp->fw_multicast_support = 0;
1935 } else {
1936 mgp->fw_multicast_support = 1;
1937 }
1938 if (status) {
1939 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1940 dev->name);
1941 goto abort_with_rings;
1942 }
1943
1944 mgp->link_state = htonl(~0U);
1945 mgp->rdma_tags_available = 15;
1946
1947 lro_mgr = &mgp->rx_done.lro_mgr;
1948 lro_mgr->dev = dev;
1949 lro_mgr->features = LRO_F_NAPI;
1950 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
1951 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
1952 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
1953 lro_mgr->lro_arr = mgp->rx_done.lro_desc;
1954 lro_mgr->get_frag_header = myri10ge_get_frag_header;
1955 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
1956 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
1957 lro_mgr->max_aggr = MAX_SKB_FRAGS;
1958
1959 napi_enable(&mgp->napi); /* must happen prior to any irq */
1960
1961 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1962 if (status) {
1963 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1964 dev->name);
1965 goto abort_with_rings;
1966 }
1967
1968 mgp->wake_queue = 0;
1969 mgp->stop_queue = 0;
1970 mgp->running = MYRI10GE_ETH_RUNNING;
1971 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1972 add_timer(&mgp->watchdog_timer);
1973 netif_wake_queue(dev);
1974 return 0;
1975
1976 abort_with_rings:
1977 myri10ge_free_rings(dev);
1978
1979 abort_with_irq:
1980 myri10ge_free_irq(mgp);
1981
1982 abort_with_nothing:
1983 mgp->running = MYRI10GE_ETH_STOPPED;
1984 return -ENOMEM;
1985 }
1986
1987 static int myri10ge_close(struct net_device *dev)
1988 {
1989 struct myri10ge_priv *mgp;
1990 struct myri10ge_cmd cmd;
1991 int status, old_down_cnt;
1992
1993 mgp = netdev_priv(dev);
1994
1995 if (mgp->running != MYRI10GE_ETH_RUNNING)
1996 return 0;
1997
1998 if (mgp->tx.req_bytes == NULL)
1999 return 0;
2000
2001 del_timer_sync(&mgp->watchdog_timer);
2002 mgp->running = MYRI10GE_ETH_STOPPING;
2003 napi_disable(&mgp->napi);
2004 netif_carrier_off(dev);
2005 netif_stop_queue(dev);
2006 old_down_cnt = mgp->down_cnt;
2007 mb();
2008 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2009 if (status)
2010 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2011 dev->name);
2012
2013 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2014 if (old_down_cnt == mgp->down_cnt)
2015 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2016
2017 netif_tx_disable(dev);
2018 myri10ge_free_irq(mgp);
2019 myri10ge_free_rings(dev);
2020
2021 mgp->running = MYRI10GE_ETH_STOPPED;
2022 return 0;
2023 }
2024
2025 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2026 * backwards one at a time and handle ring wraps */
2027
2028 static inline void
2029 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2030 struct mcp_kreq_ether_send *src, int cnt)
2031 {
2032 int idx, starting_slot;
2033 starting_slot = tx->req;
2034 while (cnt > 1) {
2035 cnt--;
2036 idx = (starting_slot + cnt) & tx->mask;
2037 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2038 mb();
2039 }
2040 }
2041
2042 /*
2043 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2044 * at most 32 bytes at a time, so as to avoid involving the software
2045 * pio handler in the nic. We re-write the first segment's flags
2046 * to mark them valid only after writing the entire chain.
2047 */
2048
2049 static inline void
2050 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2051 int cnt)
2052 {
2053 int idx, i;
2054 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2055 struct mcp_kreq_ether_send *srcp;
2056 u8 last_flags;
2057
2058 idx = tx->req & tx->mask;
2059
2060 last_flags = src->flags;
2061 src->flags = 0;
2062 mb();
2063 dst = dstp = &tx->lanai[idx];
2064 srcp = src;
2065
2066 if ((idx + cnt) < tx->mask) {
2067 for (i = 0; i < (cnt - 1); i += 2) {
2068 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2069 mb(); /* force write every 32 bytes */
2070 srcp += 2;
2071 dstp += 2;
2072 }
2073 } else {
2074 /* submit all but the first request, and ensure
2075 * that it is submitted below */
2076 myri10ge_submit_req_backwards(tx, src, cnt);
2077 i = 0;
2078 }
2079 if (i < cnt) {
2080 /* submit the first request */
2081 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2082 mb(); /* barrier before setting valid flag */
2083 }
2084
2085 /* re-write the last 32-bits with the valid flags */
2086 src->flags = last_flags;
2087 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2088 tx->req += cnt;
2089 mb();
2090 }
2091
2092 static inline void
2093 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2094 struct mcp_kreq_ether_send *src, int cnt)
2095 {
2096 tx->req += cnt;
2097 mb();
2098 while (cnt >= 4) {
2099 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2100 mb();
2101 src += 4;
2102 cnt -= 4;
2103 }
2104 if (cnt > 0) {
2105 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2106 * needs to be so that we don't overrun it */
2107 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2108 src, 64);
2109 mb();
2110 }
2111 }
2112
2113 /*
2114 * Transmit a packet. We need to split the packet so that a single
2115 * segment does not cross myri10ge->tx.boundary, so this makes segment
2116 * counting tricky. So rather than try to count segments up front, we
2117 * just give up if there are too few segments to hold a reasonably
2118 * fragmented packet currently available. If we run
2119 * out of segments while preparing a packet for DMA, we just linearize
2120 * it and try again.
2121 */
2122
2123 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2124 {
2125 struct myri10ge_priv *mgp = netdev_priv(dev);
2126 struct mcp_kreq_ether_send *req;
2127 struct myri10ge_tx_buf *tx = &mgp->tx;
2128 struct skb_frag_struct *frag;
2129 dma_addr_t bus;
2130 u32 low;
2131 __be32 high_swapped;
2132 unsigned int len;
2133 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2134 u16 pseudo_hdr_offset, cksum_offset;
2135 int cum_len, seglen, boundary, rdma_count;
2136 u8 flags, odd_flag;
2137
2138 again:
2139 req = tx->req_list;
2140 avail = tx->mask - 1 - (tx->req - tx->done);
2141
2142 mss = 0;
2143 max_segments = MXGEFW_MAX_SEND_DESC;
2144
2145 if (skb_is_gso(skb)) {
2146 mss = skb_shinfo(skb)->gso_size;
2147 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2148 }
2149
2150 if ((unlikely(avail < max_segments))) {
2151 /* we are out of transmit resources */
2152 mgp->stop_queue++;
2153 netif_stop_queue(dev);
2154 return 1;
2155 }
2156
2157 /* Setup checksum offloading, if needed */
2158 cksum_offset = 0;
2159 pseudo_hdr_offset = 0;
2160 odd_flag = 0;
2161 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2162 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2163 cksum_offset = skb_transport_offset(skb);
2164 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2165 /* If the headers are excessively large, then we must
2166 * fall back to a software checksum */
2167 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
2168 if (skb_checksum_help(skb))
2169 goto drop;
2170 cksum_offset = 0;
2171 pseudo_hdr_offset = 0;
2172 } else {
2173 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2174 flags |= MXGEFW_FLAGS_CKSUM;
2175 }
2176 }
2177
2178 cum_len = 0;
2179
2180 if (mss) { /* TSO */
2181 /* this removes any CKSUM flag from before */
2182 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2183
2184 /* negative cum_len signifies to the
2185 * send loop that we are still in the
2186 * header portion of the TSO packet.
2187 * TSO header must be at most 134 bytes long */
2188 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2189
2190 /* for TSO, pseudo_hdr_offset holds mss.
2191 * The firmware figures out where to put
2192 * the checksum by parsing the header. */
2193 pseudo_hdr_offset = mss;
2194 } else
2195 /* Mark small packets, and pad out tiny packets */
2196 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2197 flags |= MXGEFW_FLAGS_SMALL;
2198
2199 /* pad frames to at least ETH_ZLEN bytes */
2200 if (unlikely(skb->len < ETH_ZLEN)) {
2201 if (skb_padto(skb, ETH_ZLEN)) {
2202 /* The packet is gone, so we must
2203 * return 0 */
2204 mgp->stats.tx_dropped += 1;
2205 return 0;
2206 }
2207 /* adjust the len to account for the zero pad
2208 * so that the nic can know how long it is */
2209 skb->len = ETH_ZLEN;
2210 }
2211 }
2212
2213 /* map the skb for DMA */
2214 len = skb->len - skb->data_len;
2215 idx = tx->req & tx->mask;
2216 tx->info[idx].skb = skb;
2217 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2218 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2219 pci_unmap_len_set(&tx->info[idx], len, len);
2220
2221 frag_cnt = skb_shinfo(skb)->nr_frags;
2222 frag_idx = 0;
2223 count = 0;
2224 rdma_count = 0;
2225
2226 /* "rdma_count" is the number of RDMAs belonging to the
2227 * current packet BEFORE the current send request. For
2228 * non-TSO packets, this is equal to "count".
2229 * For TSO packets, rdma_count needs to be reset
2230 * to 0 after a segment cut.
2231 *
2232 * The rdma_count field of the send request is
2233 * the number of RDMAs of the packet starting at
2234 * that request. For TSO send requests with one ore more cuts
2235 * in the middle, this is the number of RDMAs starting
2236 * after the last cut in the request. All previous
2237 * segments before the last cut implicitly have 1 RDMA.
2238 *
2239 * Since the number of RDMAs is not known beforehand,
2240 * it must be filled-in retroactively - after each
2241 * segmentation cut or at the end of the entire packet.
2242 */
2243
2244 while (1) {
2245 /* Break the SKB or Fragment up into pieces which
2246 * do not cross mgp->tx.boundary */
2247 low = MYRI10GE_LOWPART_TO_U32(bus);
2248 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2249 while (len) {
2250 u8 flags_next;
2251 int cum_len_next;
2252
2253 if (unlikely(count == max_segments))
2254 goto abort_linearize;
2255
2256 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2257 seglen = boundary - low;
2258 if (seglen > len)
2259 seglen = len;
2260 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2261 cum_len_next = cum_len + seglen;
2262 if (mss) { /* TSO */
2263 (req - rdma_count)->rdma_count = rdma_count + 1;
2264
2265 if (likely(cum_len >= 0)) { /* payload */
2266 int next_is_first, chop;
2267
2268 chop = (cum_len_next > mss);
2269 cum_len_next = cum_len_next % mss;
2270 next_is_first = (cum_len_next == 0);
2271 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2272 flags_next |= next_is_first *
2273 MXGEFW_FLAGS_FIRST;
2274 rdma_count |= -(chop | next_is_first);
2275 rdma_count += chop & !next_is_first;
2276 } else if (likely(cum_len_next >= 0)) { /* header ends */
2277 int small;
2278
2279 rdma_count = -1;
2280 cum_len_next = 0;
2281 seglen = -cum_len;
2282 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2283 flags_next = MXGEFW_FLAGS_TSO_PLD |
2284 MXGEFW_FLAGS_FIRST |
2285 (small * MXGEFW_FLAGS_SMALL);
2286 }
2287 }
2288 req->addr_high = high_swapped;
2289 req->addr_low = htonl(low);
2290 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2291 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2292 req->rdma_count = 1;
2293 req->length = htons(seglen);
2294 req->cksum_offset = cksum_offset;
2295 req->flags = flags | ((cum_len & 1) * odd_flag);
2296
2297 low += seglen;
2298 len -= seglen;
2299 cum_len = cum_len_next;
2300 flags = flags_next;
2301 req++;
2302 count++;
2303 rdma_count++;
2304 if (unlikely(cksum_offset > seglen))
2305 cksum_offset -= seglen;
2306 else
2307 cksum_offset = 0;
2308 }
2309 if (frag_idx == frag_cnt)
2310 break;
2311
2312 /* map next fragment for DMA */
2313 idx = (count + tx->req) & tx->mask;
2314 frag = &skb_shinfo(skb)->frags[frag_idx];
2315 frag_idx++;
2316 len = frag->size;
2317 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2318 len, PCI_DMA_TODEVICE);
2319 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2320 pci_unmap_len_set(&tx->info[idx], len, len);
2321 }
2322
2323 (req - rdma_count)->rdma_count = rdma_count;
2324 if (mss)
2325 do {
2326 req--;
2327 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2328 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2329 MXGEFW_FLAGS_FIRST)));
2330 idx = ((count - 1) + tx->req) & tx->mask;
2331 tx->info[idx].last = 1;
2332 if (tx->wc_fifo == NULL)
2333 myri10ge_submit_req(tx, tx->req_list, count);
2334 else
2335 myri10ge_submit_req_wc(tx, tx->req_list, count);
2336 tx->pkt_start++;
2337 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2338 mgp->stop_queue++;
2339 netif_stop_queue(dev);
2340 }
2341 dev->trans_start = jiffies;
2342 return 0;
2343
2344 abort_linearize:
2345 /* Free any DMA resources we've alloced and clear out the skb
2346 * slot so as to not trip up assertions, and to avoid a
2347 * double-free if linearizing fails */
2348
2349 last_idx = (idx + 1) & tx->mask;
2350 idx = tx->req & tx->mask;
2351 tx->info[idx].skb = NULL;
2352 do {
2353 len = pci_unmap_len(&tx->info[idx], len);
2354 if (len) {
2355 if (tx->info[idx].skb != NULL)
2356 pci_unmap_single(mgp->pdev,
2357 pci_unmap_addr(&tx->info[idx],
2358 bus), len,
2359 PCI_DMA_TODEVICE);
2360 else
2361 pci_unmap_page(mgp->pdev,
2362 pci_unmap_addr(&tx->info[idx],
2363 bus), len,
2364 PCI_DMA_TODEVICE);
2365 pci_unmap_len_set(&tx->info[idx], len, 0);
2366 tx->info[idx].skb = NULL;
2367 }
2368 idx = (idx + 1) & tx->mask;
2369 } while (idx != last_idx);
2370 if (skb_is_gso(skb)) {
2371 printk(KERN_ERR
2372 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2373 mgp->dev->name);
2374 goto drop;
2375 }
2376
2377 if (skb_linearize(skb))
2378 goto drop;
2379
2380 mgp->tx_linearized++;
2381 goto again;
2382
2383 drop:
2384 dev_kfree_skb_any(skb);
2385 mgp->stats.tx_dropped += 1;
2386 return 0;
2387
2388 }
2389
2390 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2391 {
2392 struct myri10ge_priv *mgp = netdev_priv(dev);
2393 return &mgp->stats;
2394 }
2395
2396 static void myri10ge_set_multicast_list(struct net_device *dev)
2397 {
2398 struct myri10ge_cmd cmd;
2399 struct myri10ge_priv *mgp;
2400 struct dev_mc_list *mc_list;
2401 __be32 data[2] = { 0, 0 };
2402 int err;
2403 DECLARE_MAC_BUF(mac);
2404
2405 mgp = netdev_priv(dev);
2406 /* can be called from atomic contexts,
2407 * pass 1 to force atomicity in myri10ge_send_cmd() */
2408 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2409
2410 /* This firmware is known to not support multicast */
2411 if (!mgp->fw_multicast_support)
2412 return;
2413
2414 /* Disable multicast filtering */
2415
2416 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2417 if (err != 0) {
2418 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2419 " error status: %d\n", dev->name, err);
2420 goto abort;
2421 }
2422
2423 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
2424 /* request to disable multicast filtering, so quit here */
2425 return;
2426 }
2427
2428 /* Flush the filters */
2429
2430 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2431 &cmd, 1);
2432 if (err != 0) {
2433 printk(KERN_ERR
2434 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2435 ", error status: %d\n", dev->name, err);
2436 goto abort;
2437 }
2438
2439 /* Walk the multicast list, and add each address */
2440 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
2441 memcpy(data, &mc_list->dmi_addr, 6);
2442 cmd.data0 = ntohl(data[0]);
2443 cmd.data1 = ntohl(data[1]);
2444 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2445 &cmd, 1);
2446
2447 if (err != 0) {
2448 printk(KERN_ERR "myri10ge: %s: Failed "
2449 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2450 "%d\t", dev->name, err);
2451 printk(KERN_ERR "MAC %s\n",
2452 print_mac(mac, mc_list->dmi_addr));
2453 goto abort;
2454 }
2455 }
2456 /* Enable multicast filtering */
2457 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2458 if (err != 0) {
2459 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2460 "error status: %d\n", dev->name, err);
2461 goto abort;
2462 }
2463
2464 return;
2465
2466 abort:
2467 return;
2468 }
2469
2470 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2471 {
2472 struct sockaddr *sa = addr;
2473 struct myri10ge_priv *mgp = netdev_priv(dev);
2474 int status;
2475
2476 if (!is_valid_ether_addr(sa->sa_data))
2477 return -EADDRNOTAVAIL;
2478
2479 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2480 if (status != 0) {
2481 printk(KERN_ERR
2482 "myri10ge: %s: changing mac address failed with %d\n",
2483 dev->name, status);
2484 return status;
2485 }
2486
2487 /* change the dev structure */
2488 memcpy(dev->dev_addr, sa->sa_data, 6);
2489 return 0;
2490 }
2491
2492 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2493 {
2494 struct myri10ge_priv *mgp = netdev_priv(dev);
2495 int error = 0;
2496
2497 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2498 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2499 dev->name, new_mtu);
2500 return -EINVAL;
2501 }
2502 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2503 dev->name, dev->mtu, new_mtu);
2504 if (mgp->running) {
2505 /* if we change the mtu on an active device, we must
2506 * reset the device so the firmware sees the change */
2507 myri10ge_close(dev);
2508 dev->mtu = new_mtu;
2509 myri10ge_open(dev);
2510 } else
2511 dev->mtu = new_mtu;
2512
2513 return error;
2514 }
2515
2516 /*
2517 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2518 * Only do it if the bridge is a root port since we don't want to disturb
2519 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2520 */
2521
2522 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2523 {
2524 struct pci_dev *bridge = mgp->pdev->bus->self;
2525 struct device *dev = &mgp->pdev->dev;
2526 unsigned cap;
2527 unsigned err_cap;
2528 u16 val;
2529 u8 ext_type;
2530 int ret;
2531
2532 if (!myri10ge_ecrc_enable || !bridge)
2533 return;
2534
2535 /* check that the bridge is a root port */
2536 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2537 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2538 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2539 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2540 if (myri10ge_ecrc_enable > 1) {
2541 struct pci_dev *old_bridge = bridge;
2542
2543 /* Walk the hierarchy up to the root port
2544 * where ECRC has to be enabled */
2545 do {
2546 bridge = bridge->bus->self;
2547 if (!bridge) {
2548 dev_err(dev,
2549 "Failed to find root port"
2550 " to force ECRC\n");
2551 return;
2552 }
2553 cap =
2554 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2555 pci_read_config_word(bridge,
2556 cap + PCI_CAP_FLAGS, &val);
2557 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2558 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2559
2560 dev_info(dev,
2561 "Forcing ECRC on non-root port %s"
2562 " (enabling on root port %s)\n",
2563 pci_name(old_bridge), pci_name(bridge));
2564 } else {
2565 dev_err(dev,
2566 "Not enabling ECRC on non-root port %s\n",
2567 pci_name(bridge));
2568 return;
2569 }
2570 }
2571
2572 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
2573 if (!cap)
2574 return;
2575
2576 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2577 if (ret) {
2578 dev_err(dev, "failed reading ext-conf-space of %s\n",
2579 pci_name(bridge));
2580 dev_err(dev, "\t pci=nommconf in use? "
2581 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2582 return;
2583 }
2584 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2585 return;
2586
2587 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2588 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2589 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2590 }
2591
2592 /*
2593 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2594 * when the PCI-E Completion packets are aligned on an 8-byte
2595 * boundary. Some PCI-E chip sets always align Completion packets; on
2596 * the ones that do not, the alignment can be enforced by enabling
2597 * ECRC generation (if supported).
2598 *
2599 * When PCI-E Completion packets are not aligned, it is actually more
2600 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2601 *
2602 * If the driver can neither enable ECRC nor verify that it has
2603 * already been enabled, then it must use a firmware image which works
2604 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2605 * should also ensure that it never gives the device a Read-DMA which is
2606 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2607 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2608 * firmware image, and set tx.boundary to 4KB.
2609 */
2610
2611 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
2612 {
2613 struct pci_dev *pdev = mgp->pdev;
2614 struct device *dev = &pdev->dev;
2615 int status;
2616
2617 mgp->tx.boundary = 4096;
2618 /*
2619 * Verify the max read request size was set to 4KB
2620 * before trying the test with 4KB.
2621 */
2622 status = pcie_get_readrq(pdev);
2623 if (status < 0) {
2624 dev_err(dev, "Couldn't read max read req size: %d\n", status);
2625 goto abort;
2626 }
2627 if (status != 4096) {
2628 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
2629 mgp->tx.boundary = 2048;
2630 }
2631 /*
2632 * load the optimized firmware (which assumes aligned PCIe
2633 * completions) in order to see if it works on this host.
2634 */
2635 mgp->fw_name = myri10ge_fw_aligned;
2636 status = myri10ge_load_firmware(mgp);
2637 if (status != 0) {
2638 goto abort;
2639 }
2640
2641 /*
2642 * Enable ECRC if possible
2643 */
2644 myri10ge_enable_ecrc(mgp);
2645
2646 /*
2647 * Run a DMA test which watches for unaligned completions and
2648 * aborts on the first one seen.
2649 */
2650
2651 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
2652 if (status == 0)
2653 return; /* keep the aligned firmware */
2654
2655 if (status != -E2BIG)
2656 dev_warn(dev, "DMA test failed: %d\n", status);
2657 if (status == -ENOSYS)
2658 dev_warn(dev, "Falling back to ethp! "
2659 "Please install up to date fw\n");
2660 abort:
2661 /* fall back to using the unaligned firmware */
2662 mgp->tx.boundary = 2048;
2663 mgp->fw_name = myri10ge_fw_unaligned;
2664
2665 }
2666
2667 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2668 {
2669 if (myri10ge_force_firmware == 0) {
2670 int link_width, exp_cap;
2671 u16 lnk;
2672
2673 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2674 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2675 link_width = (lnk >> 4) & 0x3f;
2676
2677 /* Check to see if Link is less than 8 or if the
2678 * upstream bridge is known to provide aligned
2679 * completions */
2680 if (link_width < 8) {
2681 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2682 link_width);
2683 mgp->tx.boundary = 4096;
2684 mgp->fw_name = myri10ge_fw_aligned;
2685 } else {
2686 myri10ge_firmware_probe(mgp);
2687 }
2688 } else {
2689 if (myri10ge_force_firmware == 1) {
2690 dev_info(&mgp->pdev->dev,
2691 "Assuming aligned completions (forced)\n");
2692 mgp->tx.boundary = 4096;
2693 mgp->fw_name = myri10ge_fw_aligned;
2694 } else {
2695 dev_info(&mgp->pdev->dev,
2696 "Assuming unaligned completions (forced)\n");
2697 mgp->tx.boundary = 2048;
2698 mgp->fw_name = myri10ge_fw_unaligned;
2699 }
2700 }
2701 if (myri10ge_fw_name != NULL) {
2702 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2703 myri10ge_fw_name);
2704 mgp->fw_name = myri10ge_fw_name;
2705 }
2706 }
2707
2708 #ifdef CONFIG_PM
2709
2710 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2711 {
2712 struct myri10ge_priv *mgp;
2713 struct net_device *netdev;
2714
2715 mgp = pci_get_drvdata(pdev);
2716 if (mgp == NULL)
2717 return -EINVAL;
2718 netdev = mgp->dev;
2719
2720 netif_device_detach(netdev);
2721 if (netif_running(netdev)) {
2722 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2723 rtnl_lock();
2724 myri10ge_close(netdev);
2725 rtnl_unlock();
2726 }
2727 myri10ge_dummy_rdma(mgp, 0);
2728 pci_save_state(pdev);
2729 pci_disable_device(pdev);
2730
2731 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
2732 }
2733
2734 static int myri10ge_resume(struct pci_dev *pdev)
2735 {
2736 struct myri10ge_priv *mgp;
2737 struct net_device *netdev;
2738 int status;
2739 u16 vendor;
2740
2741 mgp = pci_get_drvdata(pdev);
2742 if (mgp == NULL)
2743 return -EINVAL;
2744 netdev = mgp->dev;
2745 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2746 msleep(5); /* give card time to respond */
2747 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2748 if (vendor == 0xffff) {
2749 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2750 mgp->dev->name);
2751 return -EIO;
2752 }
2753
2754 status = pci_restore_state(pdev);
2755 if (status)
2756 return status;
2757
2758 status = pci_enable_device(pdev);
2759 if (status) {
2760 dev_err(&pdev->dev, "failed to enable device\n");
2761 return status;
2762 }
2763
2764 pci_set_master(pdev);
2765
2766 myri10ge_reset(mgp);
2767 myri10ge_dummy_rdma(mgp, 1);
2768
2769 /* Save configuration space to be restored if the
2770 * nic resets due to a parity error */
2771 pci_save_state(pdev);
2772
2773 if (netif_running(netdev)) {
2774 rtnl_lock();
2775 status = myri10ge_open(netdev);
2776 rtnl_unlock();
2777 if (status != 0)
2778 goto abort_with_enabled;
2779
2780 }
2781 netif_device_attach(netdev);
2782
2783 return 0;
2784
2785 abort_with_enabled:
2786 pci_disable_device(pdev);
2787 return -EIO;
2788
2789 }
2790
2791 #endif /* CONFIG_PM */
2792
2793 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2794 {
2795 struct pci_dev *pdev = mgp->pdev;
2796 int vs = mgp->vendor_specific_offset;
2797 u32 reboot;
2798
2799 /*enter read32 mode */
2800 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2801
2802 /*read REBOOT_STATUS (0xfffffff0) */
2803 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2804 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2805 return reboot;
2806 }
2807
2808 /*
2809 * This watchdog is used to check whether the board has suffered
2810 * from a parity error and needs to be recovered.
2811 */
2812 static void myri10ge_watchdog(struct work_struct *work)
2813 {
2814 struct myri10ge_priv *mgp =
2815 container_of(work, struct myri10ge_priv, watchdog_work);
2816 u32 reboot;
2817 int status;
2818 u16 cmd, vendor;
2819
2820 mgp->watchdog_resets++;
2821 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2822 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2823 /* Bus master DMA disabled? Check to see
2824 * if the card rebooted due to a parity error
2825 * For now, just report it */
2826 reboot = myri10ge_read_reboot(mgp);
2827 printk(KERN_ERR
2828 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
2829 mgp->dev->name, reboot,
2830 myri10ge_reset_recover ? " " : " not");
2831 if (myri10ge_reset_recover == 0)
2832 return;
2833
2834 myri10ge_reset_recover--;
2835
2836 /*
2837 * A rebooted nic will come back with config space as
2838 * it was after power was applied to PCIe bus.
2839 * Attempt to restore config space which was saved
2840 * when the driver was loaded, or the last time the
2841 * nic was resumed from power saving mode.
2842 */
2843 pci_restore_state(mgp->pdev);
2844
2845 /* save state again for accounting reasons */
2846 pci_save_state(mgp->pdev);
2847
2848 } else {
2849 /* if we get back -1's from our slot, perhaps somebody
2850 * powered off our card. Don't try to reset it in
2851 * this case */
2852 if (cmd == 0xffff) {
2853 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2854 if (vendor == 0xffff) {
2855 printk(KERN_ERR
2856 "myri10ge: %s: device disappeared!\n",
2857 mgp->dev->name);
2858 return;
2859 }
2860 }
2861 /* Perhaps it is a software error. Try to reset */
2862
2863 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2864 mgp->dev->name);
2865 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2866 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2867 mgp->tx.pkt_start, mgp->tx.pkt_done,
2868 (int)ntohl(mgp->fw_stats->send_done_count));
2869 msleep(2000);
2870 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2871 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2872 mgp->tx.pkt_start, mgp->tx.pkt_done,
2873 (int)ntohl(mgp->fw_stats->send_done_count));
2874 }
2875 rtnl_lock();
2876 myri10ge_close(mgp->dev);
2877 status = myri10ge_load_firmware(mgp);
2878 if (status != 0)
2879 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2880 mgp->dev->name);
2881 else
2882 myri10ge_open(mgp->dev);
2883 rtnl_unlock();
2884 }
2885
2886 /*
2887 * We use our own timer routine rather than relying upon
2888 * netdev->tx_timeout because we have a very large hardware transmit
2889 * queue. Due to the large queue, the netdev->tx_timeout function
2890 * cannot detect a NIC with a parity error in a timely fashion if the
2891 * NIC is lightly loaded.
2892 */
2893 static void myri10ge_watchdog_timer(unsigned long arg)
2894 {
2895 struct myri10ge_priv *mgp;
2896 u32 rx_pause_cnt;
2897
2898 mgp = (struct myri10ge_priv *)arg;
2899
2900 if (mgp->rx_small.watchdog_needed) {
2901 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2902 mgp->small_bytes + MXGEFW_PAD, 1);
2903 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2904 myri10ge_fill_thresh)
2905 mgp->rx_small.watchdog_needed = 0;
2906 }
2907 if (mgp->rx_big.watchdog_needed) {
2908 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2909 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2910 myri10ge_fill_thresh)
2911 mgp->rx_big.watchdog_needed = 0;
2912 }
2913 rx_pause_cnt = ntohl(mgp->fw_stats->dropped_pause);
2914
2915 if (mgp->tx.req != mgp->tx.done &&
2916 mgp->tx.done == mgp->watchdog_tx_done &&
2917 mgp->watchdog_tx_req != mgp->watchdog_tx_done) {
2918 /* nic seems like it might be stuck.. */
2919 if (rx_pause_cnt != mgp->watchdog_pause) {
2920 if (net_ratelimit())
2921 printk(KERN_WARNING "myri10ge %s:"
2922 "TX paused, check link partner\n",
2923 mgp->dev->name);
2924 } else {
2925 schedule_work(&mgp->watchdog_work);
2926 return;
2927 }
2928 }
2929 /* rearm timer */
2930 mod_timer(&mgp->watchdog_timer,
2931 jiffies + myri10ge_watchdog_timeout * HZ);
2932 mgp->watchdog_tx_done = mgp->tx.done;
2933 mgp->watchdog_tx_req = mgp->tx.req;
2934 mgp->watchdog_pause = rx_pause_cnt;
2935 }
2936
2937 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2938 {
2939 struct net_device *netdev;
2940 struct myri10ge_priv *mgp;
2941 struct device *dev = &pdev->dev;
2942 size_t bytes;
2943 int i;
2944 int status = -ENXIO;
2945 int dac_enabled;
2946
2947 netdev = alloc_etherdev(sizeof(*mgp));
2948 if (netdev == NULL) {
2949 dev_err(dev, "Could not allocate ethernet device\n");
2950 return -ENOMEM;
2951 }
2952
2953 SET_NETDEV_DEV(netdev, &pdev->dev);
2954
2955 mgp = netdev_priv(netdev);
2956 mgp->dev = netdev;
2957 netif_napi_add(netdev, &mgp->napi,
2958 myri10ge_poll, myri10ge_napi_weight);
2959 mgp->pdev = pdev;
2960 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2961 mgp->pause = myri10ge_flow_control;
2962 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
2963 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2964 init_waitqueue_head(&mgp->down_wq);
2965
2966 if (pci_enable_device(pdev)) {
2967 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2968 status = -ENODEV;
2969 goto abort_with_netdev;
2970 }
2971
2972 /* Find the vendor-specific cap so we can check
2973 * the reboot register later on */
2974 mgp->vendor_specific_offset
2975 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2976
2977 /* Set our max read request to 4KB */
2978 status = pcie_set_readrq(pdev, 4096);
2979 if (status != 0) {
2980 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2981 status);
2982 goto abort_with_netdev;
2983 }
2984
2985 pci_set_master(pdev);
2986 dac_enabled = 1;
2987 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2988 if (status != 0) {
2989 dac_enabled = 0;
2990 dev_err(&pdev->dev,
2991 "64-bit pci address mask was refused, trying 32-bit");
2992 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2993 }
2994 if (status != 0) {
2995 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2996 goto abort_with_netdev;
2997 }
2998 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2999 &mgp->cmd_bus, GFP_KERNEL);
3000 if (mgp->cmd == NULL)
3001 goto abort_with_netdev;
3002
3003 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3004 &mgp->fw_stats_bus, GFP_KERNEL);
3005 if (mgp->fw_stats == NULL)
3006 goto abort_with_cmd;
3007
3008 mgp->board_span = pci_resource_len(pdev, 0);
3009 mgp->iomem_base = pci_resource_start(pdev, 0);
3010 mgp->mtrr = -1;
3011 mgp->wc_enabled = 0;
3012 #ifdef CONFIG_MTRR
3013 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3014 MTRR_TYPE_WRCOMB, 1);
3015 if (mgp->mtrr >= 0)
3016 mgp->wc_enabled = 1;
3017 #endif
3018 /* Hack. need to get rid of these magic numbers */
3019 mgp->sram_size =
3020 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3021 if (mgp->sram_size > mgp->board_span) {
3022 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3023 mgp->board_span);
3024 goto abort_with_wc;
3025 }
3026 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
3027 if (mgp->sram == NULL) {
3028 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3029 mgp->board_span, mgp->iomem_base);
3030 status = -ENXIO;
3031 goto abort_with_wc;
3032 }
3033 memcpy_fromio(mgp->eeprom_strings,
3034 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3035 MYRI10GE_EEPROM_STRINGS_SIZE);
3036 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3037 status = myri10ge_read_mac_addr(mgp);
3038 if (status)
3039 goto abort_with_ioremap;
3040
3041 for (i = 0; i < ETH_ALEN; i++)
3042 netdev->dev_addr[i] = mgp->mac_addr[i];
3043
3044 /* allocate rx done ring */
3045 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
3046 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3047 &mgp->rx_done.bus, GFP_KERNEL);
3048 if (mgp->rx_done.entry == NULL)
3049 goto abort_with_ioremap;
3050 memset(mgp->rx_done.entry, 0, bytes);
3051
3052 myri10ge_select_firmware(mgp);
3053
3054 status = myri10ge_load_firmware(mgp);
3055 if (status != 0) {
3056 dev_err(&pdev->dev, "failed to load firmware\n");
3057 goto abort_with_rx_done;
3058 }
3059
3060 status = myri10ge_reset(mgp);
3061 if (status != 0) {
3062 dev_err(&pdev->dev, "failed reset\n");
3063 goto abort_with_firmware;
3064 }
3065
3066 pci_set_drvdata(pdev, mgp);
3067 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3068 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3069 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3070 myri10ge_initial_mtu = 68;
3071 netdev->mtu = myri10ge_initial_mtu;
3072 netdev->open = myri10ge_open;
3073 netdev->stop = myri10ge_close;
3074 netdev->hard_start_xmit = myri10ge_xmit;
3075 netdev->get_stats = myri10ge_get_stats;
3076 netdev->base_addr = mgp->iomem_base;
3077 netdev->change_mtu = myri10ge_change_mtu;
3078 netdev->set_multicast_list = myri10ge_set_multicast_list;
3079 netdev->set_mac_address = myri10ge_set_mac_address;
3080 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
3081 if (dac_enabled)
3082 netdev->features |= NETIF_F_HIGHDMA;
3083
3084 /* make sure we can get an irq, and that MSI can be
3085 * setup (if available). Also ensure netdev->irq
3086 * is set to correct value if MSI is enabled */
3087 status = myri10ge_request_irq(mgp);
3088 if (status != 0)
3089 goto abort_with_firmware;
3090 netdev->irq = pdev->irq;
3091 myri10ge_free_irq(mgp);
3092
3093 /* Save configuration space to be restored if the
3094 * nic resets due to a parity error */
3095 pci_save_state(pdev);
3096
3097 /* Setup the watchdog timer */
3098 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3099 (unsigned long)mgp);
3100
3101 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3102 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3103 status = register_netdev(netdev);
3104 if (status != 0) {
3105 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3106 goto abort_with_state;
3107 }
3108 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3109 (mgp->msi_enabled ? "MSI" : "xPIC"),
3110 netdev->irq, mgp->tx.boundary, mgp->fw_name,
3111 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3112
3113 return 0;
3114
3115 abort_with_state:
3116 pci_restore_state(pdev);
3117
3118 abort_with_firmware:
3119 myri10ge_dummy_rdma(mgp, 0);
3120
3121 abort_with_rx_done:
3122 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
3123 dma_free_coherent(&pdev->dev, bytes,
3124 mgp->rx_done.entry, mgp->rx_done.bus);
3125
3126 abort_with_ioremap:
3127 iounmap(mgp->sram);
3128
3129 abort_with_wc:
3130 #ifdef CONFIG_MTRR
3131 if (mgp->mtrr >= 0)
3132 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3133 #endif
3134 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3135 mgp->fw_stats, mgp->fw_stats_bus);
3136
3137 abort_with_cmd:
3138 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3139 mgp->cmd, mgp->cmd_bus);
3140
3141 abort_with_netdev:
3142
3143 free_netdev(netdev);
3144 return status;
3145 }
3146
3147 /*
3148 * myri10ge_remove
3149 *
3150 * Does what is necessary to shutdown one Myrinet device. Called
3151 * once for each Myrinet card by the kernel when a module is
3152 * unloaded.
3153 */
3154 static void myri10ge_remove(struct pci_dev *pdev)
3155 {
3156 struct myri10ge_priv *mgp;
3157 struct net_device *netdev;
3158 size_t bytes;
3159
3160 mgp = pci_get_drvdata(pdev);
3161 if (mgp == NULL)
3162 return;
3163
3164 flush_scheduled_work();
3165 netdev = mgp->dev;
3166 unregister_netdev(netdev);
3167
3168 myri10ge_dummy_rdma(mgp, 0);
3169
3170 /* avoid a memory leak */
3171 pci_restore_state(pdev);
3172
3173 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
3174 dma_free_coherent(&pdev->dev, bytes,
3175 mgp->rx_done.entry, mgp->rx_done.bus);
3176
3177 iounmap(mgp->sram);
3178
3179 #ifdef CONFIG_MTRR
3180 if (mgp->mtrr >= 0)
3181 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3182 #endif
3183 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3184 mgp->fw_stats, mgp->fw_stats_bus);
3185
3186 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3187 mgp->cmd, mgp->cmd_bus);
3188
3189 free_netdev(netdev);
3190 pci_set_drvdata(pdev, NULL);
3191 }
3192
3193 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
3194 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
3195
3196 static struct pci_device_id myri10ge_pci_tbl[] = {
3197 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
3198 {PCI_DEVICE
3199 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
3200 {0},
3201 };
3202
3203 static struct pci_driver myri10ge_driver = {
3204 .name = "myri10ge",
3205 .probe = myri10ge_probe,
3206 .remove = myri10ge_remove,
3207 .id_table = myri10ge_pci_tbl,
3208 #ifdef CONFIG_PM
3209 .suspend = myri10ge_suspend,
3210 .resume = myri10ge_resume,
3211 #endif
3212 };
3213
3214 static __init int myri10ge_init_module(void)
3215 {
3216 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3217 MYRI10GE_VERSION_STR);
3218 return pci_register_driver(&myri10ge_driver);
3219 }
3220
3221 module_init(myri10ge_init_module);
3222
3223 static __exit void myri10ge_cleanup_module(void)
3224 {
3225 pci_unregister_driver(&myri10ge_driver);
3226 }
3227
3228 module_exit(myri10ge_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)