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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / myri10ge / myri10ge.c
1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005 - 2007 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/inet_lro.h>
52 #include <linux/dca.h>
53 #include <linux/ip.h>
54 #include <linux/inet.h>
55 #include <linux/in.h>
56 #include <linux/ethtool.h>
57 #include <linux/firmware.h>
58 #include <linux/delay.h>
59 #include <linux/timer.h>
60 #include <linux/vmalloc.h>
61 #include <linux/crc32.h>
62 #include <linux/moduleparam.h>
63 #include <linux/io.h>
64 #include <linux/log2.h>
65 #include <net/checksum.h>
66 #include <net/ip.h>
67 #include <net/tcp.h>
68 #include <asm/byteorder.h>
69 #include <asm/io.h>
70 #include <asm/processor.h>
71 #ifdef CONFIG_MTRR
72 #include <asm/mtrr.h>
73 #endif
74
75 #include "myri10ge_mcp.h"
76 #include "myri10ge_mcp_gen_header.h"
77
78 #define MYRI10GE_VERSION_STR "1.4.3-1.375"
79
80 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81 MODULE_AUTHOR("Maintainer: help@myri.com");
82 MODULE_VERSION(MYRI10GE_VERSION_STR);
83 MODULE_LICENSE("Dual BSD/GPL");
84
85 #define MYRI10GE_MAX_ETHER_MTU 9014
86
87 #define MYRI10GE_ETH_STOPPED 0
88 #define MYRI10GE_ETH_STOPPING 1
89 #define MYRI10GE_ETH_STARTING 2
90 #define MYRI10GE_ETH_RUNNING 3
91 #define MYRI10GE_ETH_OPEN_FAILED 4
92
93 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
94 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
95 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96 #define MYRI10GE_LRO_MAX_PKTS 64
97
98 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
99 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
101 #define MYRI10GE_ALLOC_ORDER 0
102 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
105 #define MYRI10GE_MAX_SLICES 32
106
107 struct myri10ge_rx_buffer_state {
108 struct page *page;
109 int page_offset;
110 DECLARE_PCI_UNMAP_ADDR(bus)
111 DECLARE_PCI_UNMAP_LEN(len)
112 };
113
114 struct myri10ge_tx_buffer_state {
115 struct sk_buff *skb;
116 int last;
117 DECLARE_PCI_UNMAP_ADDR(bus)
118 DECLARE_PCI_UNMAP_LEN(len)
119 };
120
121 struct myri10ge_cmd {
122 u32 data0;
123 u32 data1;
124 u32 data2;
125 };
126
127 struct myri10ge_rx_buf {
128 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
129 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
130 struct myri10ge_rx_buffer_state *info;
131 struct page *page;
132 dma_addr_t bus;
133 int page_offset;
134 int cnt;
135 int fill_cnt;
136 int alloc_fail;
137 int mask; /* number of rx slots -1 */
138 int watchdog_needed;
139 };
140
141 struct myri10ge_tx_buf {
142 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
143 __be32 __iomem *send_go; /* "go" doorbell ptr */
144 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
145 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
146 char *req_bytes;
147 struct myri10ge_tx_buffer_state *info;
148 int mask; /* number of transmit slots -1 */
149 int req ____cacheline_aligned; /* transmit slots submitted */
150 int pkt_start; /* packets started */
151 int stop_queue;
152 int linearized;
153 int done ____cacheline_aligned; /* transmit slots completed */
154 int pkt_done; /* packets completed */
155 int wake_queue;
156 int queue_active;
157 };
158
159 struct myri10ge_rx_done {
160 struct mcp_slot *entry;
161 dma_addr_t bus;
162 int cnt;
163 int idx;
164 struct net_lro_mgr lro_mgr;
165 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
166 };
167
168 struct myri10ge_slice_netstats {
169 unsigned long rx_packets;
170 unsigned long tx_packets;
171 unsigned long rx_bytes;
172 unsigned long tx_bytes;
173 unsigned long rx_dropped;
174 unsigned long tx_dropped;
175 };
176
177 struct myri10ge_slice_state {
178 struct myri10ge_tx_buf tx; /* transmit ring */
179 struct myri10ge_rx_buf rx_small;
180 struct myri10ge_rx_buf rx_big;
181 struct myri10ge_rx_done rx_done;
182 struct net_device *dev;
183 struct napi_struct napi;
184 struct myri10ge_priv *mgp;
185 struct myri10ge_slice_netstats stats;
186 __be32 __iomem *irq_claim;
187 struct mcp_irq_data *fw_stats;
188 dma_addr_t fw_stats_bus;
189 int watchdog_tx_done;
190 int watchdog_tx_req;
191 #ifdef CONFIG_MYRI10GE_DCA
192 int cached_dca_tag;
193 int cpu;
194 __be32 __iomem *dca_tag;
195 #endif
196 char irq_desc[32];
197 };
198
199 struct myri10ge_priv {
200 struct myri10ge_slice_state *ss;
201 int tx_boundary; /* boundary transmits cannot cross */
202 int num_slices;
203 int running; /* running? */
204 int csum_flag; /* rx_csums? */
205 int small_bytes;
206 int big_bytes;
207 int max_intr_slots;
208 struct net_device *dev;
209 struct net_device_stats stats;
210 spinlock_t stats_lock;
211 u8 __iomem *sram;
212 int sram_size;
213 unsigned long board_span;
214 unsigned long iomem_base;
215 __be32 __iomem *irq_deassert;
216 char *mac_addr_string;
217 struct mcp_cmd_response *cmd;
218 dma_addr_t cmd_bus;
219 struct pci_dev *pdev;
220 int msi_enabled;
221 int msix_enabled;
222 struct msix_entry *msix_vectors;
223 #ifdef CONFIG_MYRI10GE_DCA
224 int dca_enabled;
225 #endif
226 u32 link_state;
227 unsigned int rdma_tags_available;
228 int intr_coal_delay;
229 __be32 __iomem *intr_coal_delay_ptr;
230 int mtrr;
231 int wc_enabled;
232 int down_cnt;
233 wait_queue_head_t down_wq;
234 struct work_struct watchdog_work;
235 struct timer_list watchdog_timer;
236 int watchdog_resets;
237 int watchdog_pause;
238 int pause;
239 char *fw_name;
240 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
241 char *product_code_string;
242 char fw_version[128];
243 int fw_ver_major;
244 int fw_ver_minor;
245 int fw_ver_tiny;
246 int adopted_rx_filter_bug;
247 u8 mac_addr[6]; /* eeprom mac address */
248 unsigned long serial_number;
249 int vendor_specific_offset;
250 int fw_multicast_support;
251 unsigned long features;
252 u32 max_tso6;
253 u32 read_dma;
254 u32 write_dma;
255 u32 read_write_dma;
256 u32 link_changes;
257 u32 msg_enable;
258 };
259
260 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
261 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
262 static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
263 static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
264
265 static char *myri10ge_fw_name = NULL;
266 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
267 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
268
269 static int myri10ge_ecrc_enable = 1;
270 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
271 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
272
273 static int myri10ge_small_bytes = -1; /* -1 == auto */
274 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
275 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
276
277 static int myri10ge_msi = 1; /* enable msi by default */
278 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
279 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
280
281 static int myri10ge_intr_coal_delay = 75;
282 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
283 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
284
285 static int myri10ge_flow_control = 1;
286 module_param(myri10ge_flow_control, int, S_IRUGO);
287 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
288
289 static int myri10ge_deassert_wait = 1;
290 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
291 MODULE_PARM_DESC(myri10ge_deassert_wait,
292 "Wait when deasserting legacy interrupts");
293
294 static int myri10ge_force_firmware = 0;
295 module_param(myri10ge_force_firmware, int, S_IRUGO);
296 MODULE_PARM_DESC(myri10ge_force_firmware,
297 "Force firmware to assume aligned completions");
298
299 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
300 module_param(myri10ge_initial_mtu, int, S_IRUGO);
301 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
302
303 static int myri10ge_napi_weight = 64;
304 module_param(myri10ge_napi_weight, int, S_IRUGO);
305 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
306
307 static int myri10ge_watchdog_timeout = 1;
308 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
309 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
310
311 static int myri10ge_max_irq_loops = 1048576;
312 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
313 MODULE_PARM_DESC(myri10ge_max_irq_loops,
314 "Set stuck legacy IRQ detection threshold");
315
316 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
317
318 static int myri10ge_debug = -1; /* defaults above */
319 module_param(myri10ge_debug, int, 0);
320 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
321
322 static int myri10ge_lro = 1;
323 module_param(myri10ge_lro, int, S_IRUGO);
324 MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
325
326 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
327 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
328 MODULE_PARM_DESC(myri10ge_lro_max_pkts,
329 "Number of LRO packets to be aggregated");
330
331 static int myri10ge_fill_thresh = 256;
332 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
333 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
334
335 static int myri10ge_reset_recover = 1;
336
337 static int myri10ge_max_slices = 1;
338 module_param(myri10ge_max_slices, int, S_IRUGO);
339 MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
340
341 static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
342 module_param(myri10ge_rss_hash, int, S_IRUGO);
343 MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
344
345 static int myri10ge_dca = 1;
346 module_param(myri10ge_dca, int, S_IRUGO);
347 MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
348
349 #define MYRI10GE_FW_OFFSET 1024*1024
350 #define MYRI10GE_HIGHPART_TO_U32(X) \
351 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
352 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
353
354 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
355
356 static void myri10ge_set_multicast_list(struct net_device *dev);
357 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
358
359 static inline void put_be32(__be32 val, __be32 __iomem * p)
360 {
361 __raw_writel((__force __u32) val, (__force void __iomem *)p);
362 }
363
364 static int
365 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
366 struct myri10ge_cmd *data, int atomic)
367 {
368 struct mcp_cmd *buf;
369 char buf_bytes[sizeof(*buf) + 8];
370 struct mcp_cmd_response *response = mgp->cmd;
371 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
372 u32 dma_low, dma_high, result, value;
373 int sleep_total = 0;
374
375 /* ensure buf is aligned to 8 bytes */
376 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
377
378 buf->data0 = htonl(data->data0);
379 buf->data1 = htonl(data->data1);
380 buf->data2 = htonl(data->data2);
381 buf->cmd = htonl(cmd);
382 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
383 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
384
385 buf->response_addr.low = htonl(dma_low);
386 buf->response_addr.high = htonl(dma_high);
387 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
388 mb();
389 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
390
391 /* wait up to 15ms. Longest command is the DMA benchmark,
392 * which is capped at 5ms, but runs from a timeout handler
393 * that runs every 7.8ms. So a 15ms timeout leaves us with
394 * a 2.2ms margin
395 */
396 if (atomic) {
397 /* if atomic is set, do not sleep,
398 * and try to get the completion quickly
399 * (1ms will be enough for those commands) */
400 for (sleep_total = 0;
401 sleep_total < 1000
402 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
403 sleep_total += 10) {
404 udelay(10);
405 mb();
406 }
407 } else {
408 /* use msleep for most command */
409 for (sleep_total = 0;
410 sleep_total < 15
411 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
412 sleep_total++)
413 msleep(1);
414 }
415
416 result = ntohl(response->result);
417 value = ntohl(response->data);
418 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
419 if (result == 0) {
420 data->data0 = value;
421 return 0;
422 } else if (result == MXGEFW_CMD_UNKNOWN) {
423 return -ENOSYS;
424 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
425 return -E2BIG;
426 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
427 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
428 (data->
429 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
430 0) {
431 return -ERANGE;
432 } else {
433 dev_err(&mgp->pdev->dev,
434 "command %d failed, result = %d\n",
435 cmd, result);
436 return -ENXIO;
437 }
438 }
439
440 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
441 cmd, result);
442 return -EAGAIN;
443 }
444
445 /*
446 * The eeprom strings on the lanaiX have the format
447 * SN=x\0
448 * MAC=x:x:x:x:x:x\0
449 * PT:ddd mmm xx xx:xx:xx xx\0
450 * PV:ddd mmm xx xx:xx:xx xx\0
451 */
452 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
453 {
454 char *ptr, *limit;
455 int i;
456
457 ptr = mgp->eeprom_strings;
458 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
459
460 while (*ptr != '\0' && ptr < limit) {
461 if (memcmp(ptr, "MAC=", 4) == 0) {
462 ptr += 4;
463 mgp->mac_addr_string = ptr;
464 for (i = 0; i < 6; i++) {
465 if ((ptr + 2) > limit)
466 goto abort;
467 mgp->mac_addr[i] =
468 simple_strtoul(ptr, &ptr, 16);
469 ptr += 1;
470 }
471 }
472 if (memcmp(ptr, "PC=", 3) == 0) {
473 ptr += 3;
474 mgp->product_code_string = ptr;
475 }
476 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
477 ptr += 3;
478 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
479 }
480 while (ptr < limit && *ptr++) ;
481 }
482
483 return 0;
484
485 abort:
486 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
487 return -ENXIO;
488 }
489
490 /*
491 * Enable or disable periodic RDMAs from the host to make certain
492 * chipsets resend dropped PCIe messages
493 */
494
495 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
496 {
497 char __iomem *submit;
498 __be32 buf[16] __attribute__ ((__aligned__(8)));
499 u32 dma_low, dma_high;
500 int i;
501
502 /* clear confirmation addr */
503 mgp->cmd->data = 0;
504 mb();
505
506 /* send a rdma command to the PCIe engine, and wait for the
507 * response in the confirmation address. The firmware should
508 * write a -1 there to indicate it is alive and well
509 */
510 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
511 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
512
513 buf[0] = htonl(dma_high); /* confirm addr MSW */
514 buf[1] = htonl(dma_low); /* confirm addr LSW */
515 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
516 buf[3] = htonl(dma_high); /* dummy addr MSW */
517 buf[4] = htonl(dma_low); /* dummy addr LSW */
518 buf[5] = htonl(enable); /* enable? */
519
520 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
521
522 myri10ge_pio_copy(submit, &buf, sizeof(buf));
523 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
524 msleep(1);
525 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
526 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
527 (enable ? "enable" : "disable"));
528 }
529
530 static int
531 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
532 struct mcp_gen_header *hdr)
533 {
534 struct device *dev = &mgp->pdev->dev;
535
536 /* check firmware type */
537 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
538 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
539 return -EINVAL;
540 }
541
542 /* save firmware version for ethtool */
543 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
544
545 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
546 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
547
548 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
549 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
550 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
551 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
552 MXGEFW_VERSION_MINOR);
553 return -EINVAL;
554 }
555 return 0;
556 }
557
558 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
559 {
560 unsigned crc, reread_crc;
561 const struct firmware *fw;
562 struct device *dev = &mgp->pdev->dev;
563 unsigned char *fw_readback;
564 struct mcp_gen_header *hdr;
565 size_t hdr_offset;
566 int status;
567 unsigned i;
568
569 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
570 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
571 mgp->fw_name);
572 status = -EINVAL;
573 goto abort_with_nothing;
574 }
575
576 /* check size */
577
578 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
579 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
580 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
581 status = -EINVAL;
582 goto abort_with_fw;
583 }
584
585 /* check id */
586 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
587 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
588 dev_err(dev, "Bad firmware file\n");
589 status = -EINVAL;
590 goto abort_with_fw;
591 }
592 hdr = (void *)(fw->data + hdr_offset);
593
594 status = myri10ge_validate_firmware(mgp, hdr);
595 if (status != 0)
596 goto abort_with_fw;
597
598 crc = crc32(~0, fw->data, fw->size);
599 for (i = 0; i < fw->size; i += 256) {
600 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
601 fw->data + i,
602 min(256U, (unsigned)(fw->size - i)));
603 mb();
604 readb(mgp->sram);
605 }
606 fw_readback = vmalloc(fw->size);
607 if (!fw_readback) {
608 status = -ENOMEM;
609 goto abort_with_fw;
610 }
611 /* corruption checking is good for parity recovery and buggy chipset */
612 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
613 reread_crc = crc32(~0, fw_readback, fw->size);
614 vfree(fw_readback);
615 if (crc != reread_crc) {
616 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
617 (unsigned)fw->size, reread_crc, crc);
618 status = -EIO;
619 goto abort_with_fw;
620 }
621 *size = (u32) fw->size;
622
623 abort_with_fw:
624 release_firmware(fw);
625
626 abort_with_nothing:
627 return status;
628 }
629
630 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
631 {
632 struct mcp_gen_header *hdr;
633 struct device *dev = &mgp->pdev->dev;
634 const size_t bytes = sizeof(struct mcp_gen_header);
635 size_t hdr_offset;
636 int status;
637
638 /* find running firmware header */
639 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
640
641 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
642 dev_err(dev, "Running firmware has bad header offset (%d)\n",
643 (int)hdr_offset);
644 return -EIO;
645 }
646
647 /* copy header of running firmware from SRAM to host memory to
648 * validate firmware */
649 hdr = kmalloc(bytes, GFP_KERNEL);
650 if (hdr == NULL) {
651 dev_err(dev, "could not malloc firmware hdr\n");
652 return -ENOMEM;
653 }
654 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
655 status = myri10ge_validate_firmware(mgp, hdr);
656 kfree(hdr);
657
658 /* check to see if adopted firmware has bug where adopting
659 * it will cause broadcasts to be filtered unless the NIC
660 * is kept in ALLMULTI mode */
661 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
662 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
663 mgp->adopted_rx_filter_bug = 1;
664 dev_warn(dev, "Adopting fw %d.%d.%d: "
665 "working around rx filter bug\n",
666 mgp->fw_ver_major, mgp->fw_ver_minor,
667 mgp->fw_ver_tiny);
668 }
669 return status;
670 }
671
672 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
673 {
674 struct myri10ge_cmd cmd;
675 int status;
676
677 /* probe for IPv6 TSO support */
678 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
679 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
680 &cmd, 0);
681 if (status == 0) {
682 mgp->max_tso6 = cmd.data0;
683 mgp->features |= NETIF_F_TSO6;
684 }
685
686 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
687 if (status != 0) {
688 dev_err(&mgp->pdev->dev,
689 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
690 return -ENXIO;
691 }
692
693 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
694
695 return 0;
696 }
697
698 static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
699 {
700 char __iomem *submit;
701 __be32 buf[16] __attribute__ ((__aligned__(8)));
702 u32 dma_low, dma_high, size;
703 int status, i;
704
705 size = 0;
706 status = myri10ge_load_hotplug_firmware(mgp, &size);
707 if (status) {
708 if (!adopt)
709 return status;
710 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
711
712 /* Do not attempt to adopt firmware if there
713 * was a bad crc */
714 if (status == -EIO)
715 return status;
716
717 status = myri10ge_adopt_running_firmware(mgp);
718 if (status != 0) {
719 dev_err(&mgp->pdev->dev,
720 "failed to adopt running firmware\n");
721 return status;
722 }
723 dev_info(&mgp->pdev->dev,
724 "Successfully adopted running firmware\n");
725 if (mgp->tx_boundary == 4096) {
726 dev_warn(&mgp->pdev->dev,
727 "Using firmware currently running on NIC"
728 ". For optimal\n");
729 dev_warn(&mgp->pdev->dev,
730 "performance consider loading optimized "
731 "firmware\n");
732 dev_warn(&mgp->pdev->dev, "via hotplug\n");
733 }
734
735 mgp->fw_name = "adopted";
736 mgp->tx_boundary = 2048;
737 myri10ge_dummy_rdma(mgp, 1);
738 status = myri10ge_get_firmware_capabilities(mgp);
739 return status;
740 }
741
742 /* clear confirmation addr */
743 mgp->cmd->data = 0;
744 mb();
745
746 /* send a reload command to the bootstrap MCP, and wait for the
747 * response in the confirmation address. The firmware should
748 * write a -1 there to indicate it is alive and well
749 */
750 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
751 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
752
753 buf[0] = htonl(dma_high); /* confirm addr MSW */
754 buf[1] = htonl(dma_low); /* confirm addr LSW */
755 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
756
757 /* FIX: All newest firmware should un-protect the bottom of
758 * the sram before handoff. However, the very first interfaces
759 * do not. Therefore the handoff copy must skip the first 8 bytes
760 */
761 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
762 buf[4] = htonl(size - 8); /* length of code */
763 buf[5] = htonl(8); /* where to copy to */
764 buf[6] = htonl(0); /* where to jump to */
765
766 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
767
768 myri10ge_pio_copy(submit, &buf, sizeof(buf));
769 mb();
770 msleep(1);
771 mb();
772 i = 0;
773 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
774 msleep(1 << i);
775 i++;
776 }
777 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
778 dev_err(&mgp->pdev->dev, "handoff failed\n");
779 return -ENXIO;
780 }
781 myri10ge_dummy_rdma(mgp, 1);
782 status = myri10ge_get_firmware_capabilities(mgp);
783
784 return status;
785 }
786
787 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
788 {
789 struct myri10ge_cmd cmd;
790 int status;
791
792 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
793 | (addr[2] << 8) | addr[3]);
794
795 cmd.data1 = ((addr[4] << 8) | (addr[5]));
796
797 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
798 return status;
799 }
800
801 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
802 {
803 struct myri10ge_cmd cmd;
804 int status, ctl;
805
806 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
807 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
808
809 if (status) {
810 printk(KERN_ERR
811 "myri10ge: %s: Failed to set flow control mode\n",
812 mgp->dev->name);
813 return status;
814 }
815 mgp->pause = pause;
816 return 0;
817 }
818
819 static void
820 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
821 {
822 struct myri10ge_cmd cmd;
823 int status, ctl;
824
825 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
826 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
827 if (status)
828 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
829 mgp->dev->name);
830 }
831
832 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
833 {
834 struct myri10ge_cmd cmd;
835 int status;
836 u32 len;
837 struct page *dmatest_page;
838 dma_addr_t dmatest_bus;
839 char *test = " ";
840
841 dmatest_page = alloc_page(GFP_KERNEL);
842 if (!dmatest_page)
843 return -ENOMEM;
844 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
845 DMA_BIDIRECTIONAL);
846
847 /* Run a small DMA test.
848 * The magic multipliers to the length tell the firmware
849 * to do DMA read, write, or read+write tests. The
850 * results are returned in cmd.data0. The upper 16
851 * bits or the return is the number of transfers completed.
852 * The lower 16 bits is the time in 0.5us ticks that the
853 * transfers took to complete.
854 */
855
856 len = mgp->tx_boundary;
857
858 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
859 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
860 cmd.data2 = len * 0x10000;
861 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
862 if (status != 0) {
863 test = "read";
864 goto abort;
865 }
866 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
867 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
868 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
869 cmd.data2 = len * 0x1;
870 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
871 if (status != 0) {
872 test = "write";
873 goto abort;
874 }
875 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
876
877 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
878 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
879 cmd.data2 = len * 0x10001;
880 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
881 if (status != 0) {
882 test = "read/write";
883 goto abort;
884 }
885 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
886 (cmd.data0 & 0xffff);
887
888 abort:
889 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
890 put_page(dmatest_page);
891
892 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
893 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
894 test, status);
895
896 return status;
897 }
898
899 static int myri10ge_reset(struct myri10ge_priv *mgp)
900 {
901 struct myri10ge_cmd cmd;
902 struct myri10ge_slice_state *ss;
903 int i, status;
904 size_t bytes;
905 #ifdef CONFIG_MYRI10GE_DCA
906 unsigned long dca_tag_off;
907 #endif
908
909 /* try to send a reset command to the card to see if it
910 * is alive */
911 memset(&cmd, 0, sizeof(cmd));
912 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
913 if (status != 0) {
914 dev_err(&mgp->pdev->dev, "failed reset\n");
915 return -ENXIO;
916 }
917
918 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
919 /*
920 * Use non-ndis mcp_slot (eg, 4 bytes total,
921 * no toeplitz hash value returned. Older firmware will
922 * not understand this command, but will use the correct
923 * sized mcp_slot, so we ignore error returns
924 */
925 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
926 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
927
928 /* Now exchange information about interrupts */
929
930 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
931 cmd.data0 = (u32) bytes;
932 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
933
934 /*
935 * Even though we already know how many slices are supported
936 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
937 * has magic side effects, and must be called after a reset.
938 * It must be called prior to calling any RSS related cmds,
939 * including assigning an interrupt queue for anything but
940 * slice 0. It must also be called *after*
941 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
942 * the firmware to compute offsets.
943 */
944
945 if (mgp->num_slices > 1) {
946
947 /* ask the maximum number of slices it supports */
948 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
949 &cmd, 0);
950 if (status != 0) {
951 dev_err(&mgp->pdev->dev,
952 "failed to get number of slices\n");
953 }
954
955 /*
956 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
957 * to setting up the interrupt queue DMA
958 */
959
960 cmd.data0 = mgp->num_slices;
961 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
962 if (mgp->dev->real_num_tx_queues > 1)
963 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
964 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
965 &cmd, 0);
966
967 /* Firmware older than 1.4.32 only supports multiple
968 * RX queues, so if we get an error, first retry using a
969 * single TX queue before giving up */
970 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
971 mgp->dev->real_num_tx_queues = 1;
972 cmd.data0 = mgp->num_slices;
973 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
974 status = myri10ge_send_cmd(mgp,
975 MXGEFW_CMD_ENABLE_RSS_QUEUES,
976 &cmd, 0);
977 }
978
979 if (status != 0) {
980 dev_err(&mgp->pdev->dev,
981 "failed to set number of slices\n");
982
983 return status;
984 }
985 }
986 for (i = 0; i < mgp->num_slices; i++) {
987 ss = &mgp->ss[i];
988 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
989 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
990 cmd.data2 = i;
991 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
992 &cmd, 0);
993 };
994
995 status |=
996 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
997 for (i = 0; i < mgp->num_slices; i++) {
998 ss = &mgp->ss[i];
999 ss->irq_claim =
1000 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1001 }
1002 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1003 &cmd, 0);
1004 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
1005
1006 status |= myri10ge_send_cmd
1007 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
1008 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
1009 if (status != 0) {
1010 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1011 return status;
1012 }
1013 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1014
1015 #ifdef CONFIG_MYRI10GE_DCA
1016 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1017 dca_tag_off = cmd.data0;
1018 for (i = 0; i < mgp->num_slices; i++) {
1019 ss = &mgp->ss[i];
1020 if (status == 0) {
1021 ss->dca_tag = (__iomem __be32 *)
1022 (mgp->sram + dca_tag_off + 4 * i);
1023 } else {
1024 ss->dca_tag = NULL;
1025 }
1026 }
1027 #endif /* CONFIG_DCA */
1028
1029 /* reset mcp/driver shared state back to 0 */
1030
1031 mgp->link_changes = 0;
1032 for (i = 0; i < mgp->num_slices; i++) {
1033 ss = &mgp->ss[i];
1034
1035 memset(ss->rx_done.entry, 0, bytes);
1036 ss->tx.req = 0;
1037 ss->tx.done = 0;
1038 ss->tx.pkt_start = 0;
1039 ss->tx.pkt_done = 0;
1040 ss->rx_big.cnt = 0;
1041 ss->rx_small.cnt = 0;
1042 ss->rx_done.idx = 0;
1043 ss->rx_done.cnt = 0;
1044 ss->tx.wake_queue = 0;
1045 ss->tx.stop_queue = 0;
1046 }
1047
1048 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
1049 myri10ge_change_pause(mgp, mgp->pause);
1050 myri10ge_set_multicast_list(mgp->dev);
1051 return status;
1052 }
1053
1054 #ifdef CONFIG_MYRI10GE_DCA
1055 static void
1056 myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1057 {
1058 ss->cpu = cpu;
1059 ss->cached_dca_tag = tag;
1060 put_be32(htonl(tag), ss->dca_tag);
1061 }
1062
1063 static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1064 {
1065 int cpu = get_cpu();
1066 int tag;
1067
1068 if (cpu != ss->cpu) {
1069 tag = dca_get_tag(cpu);
1070 if (ss->cached_dca_tag != tag)
1071 myri10ge_write_dca(ss, cpu, tag);
1072 }
1073 put_cpu();
1074 }
1075
1076 static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1077 {
1078 int err, i;
1079 struct pci_dev *pdev = mgp->pdev;
1080
1081 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1082 return;
1083 if (!myri10ge_dca) {
1084 dev_err(&pdev->dev, "dca disabled by administrator\n");
1085 return;
1086 }
1087 err = dca_add_requester(&pdev->dev);
1088 if (err) {
1089 if (err != -ENODEV)
1090 dev_err(&pdev->dev,
1091 "dca_add_requester() failed, err=%d\n", err);
1092 return;
1093 }
1094 mgp->dca_enabled = 1;
1095 for (i = 0; i < mgp->num_slices; i++)
1096 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1097 }
1098
1099 static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1100 {
1101 struct pci_dev *pdev = mgp->pdev;
1102 int err;
1103
1104 if (!mgp->dca_enabled)
1105 return;
1106 mgp->dca_enabled = 0;
1107 err = dca_remove_requester(&pdev->dev);
1108 }
1109
1110 static int myri10ge_notify_dca_device(struct device *dev, void *data)
1111 {
1112 struct myri10ge_priv *mgp;
1113 unsigned long event;
1114
1115 mgp = dev_get_drvdata(dev);
1116 event = *(unsigned long *)data;
1117
1118 if (event == DCA_PROVIDER_ADD)
1119 myri10ge_setup_dca(mgp);
1120 else if (event == DCA_PROVIDER_REMOVE)
1121 myri10ge_teardown_dca(mgp);
1122 return 0;
1123 }
1124 #endif /* CONFIG_DCA */
1125
1126 static inline void
1127 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1128 struct mcp_kreq_ether_recv *src)
1129 {
1130 __be32 low;
1131
1132 low = src->addr_low;
1133 src->addr_low = htonl(DMA_32BIT_MASK);
1134 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1135 mb();
1136 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
1137 mb();
1138 src->addr_low = low;
1139 put_be32(low, &dst->addr_low);
1140 mb();
1141 }
1142
1143 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
1144 {
1145 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1146
1147 if ((skb->protocol == htons(ETH_P_8021Q)) &&
1148 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1149 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1150 skb->csum = hw_csum;
1151 skb->ip_summed = CHECKSUM_COMPLETE;
1152 }
1153 }
1154
1155 static inline void
1156 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1157 struct skb_frag_struct *rx_frags, int len, int hlen)
1158 {
1159 struct skb_frag_struct *skb_frags;
1160
1161 skb->len = skb->data_len = len;
1162 skb->truesize = len + sizeof(struct sk_buff);
1163 /* attach the page(s) */
1164
1165 skb_frags = skb_shinfo(skb)->frags;
1166 while (len > 0) {
1167 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1168 len -= rx_frags->size;
1169 skb_frags++;
1170 rx_frags++;
1171 skb_shinfo(skb)->nr_frags++;
1172 }
1173
1174 /* pskb_may_pull is not available in irq context, but
1175 * skb_pull() (for ether_pad and eth_type_trans()) requires
1176 * the beginning of the packet in skb_headlen(), move it
1177 * manually */
1178 skb_copy_to_linear_data(skb, va, hlen);
1179 skb_shinfo(skb)->frags[0].page_offset += hlen;
1180 skb_shinfo(skb)->frags[0].size -= hlen;
1181 skb->data_len -= hlen;
1182 skb->tail += hlen;
1183 skb_pull(skb, MXGEFW_PAD);
1184 }
1185
1186 static void
1187 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1188 int bytes, int watchdog)
1189 {
1190 struct page *page;
1191 int idx;
1192
1193 if (unlikely(rx->watchdog_needed && !watchdog))
1194 return;
1195
1196 /* try to refill entire ring */
1197 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1198 idx = rx->fill_cnt & rx->mask;
1199 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
1200 /* we can use part of previous page */
1201 get_page(rx->page);
1202 } else {
1203 /* we need a new page */
1204 page =
1205 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1206 MYRI10GE_ALLOC_ORDER);
1207 if (unlikely(page == NULL)) {
1208 if (rx->fill_cnt - rx->cnt < 16)
1209 rx->watchdog_needed = 1;
1210 return;
1211 }
1212 rx->page = page;
1213 rx->page_offset = 0;
1214 rx->bus = pci_map_page(mgp->pdev, page, 0,
1215 MYRI10GE_ALLOC_SIZE,
1216 PCI_DMA_FROMDEVICE);
1217 }
1218 rx->info[idx].page = rx->page;
1219 rx->info[idx].page_offset = rx->page_offset;
1220 /* note that this is the address of the start of the
1221 * page */
1222 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1223 rx->shadow[idx].addr_low =
1224 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1225 rx->shadow[idx].addr_high =
1226 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1227
1228 /* start next packet on a cacheline boundary */
1229 rx->page_offset += SKB_DATA_ALIGN(bytes);
1230
1231 #if MYRI10GE_ALLOC_SIZE > 4096
1232 /* don't cross a 4KB boundary */
1233 if ((rx->page_offset >> 12) !=
1234 ((rx->page_offset + bytes - 1) >> 12))
1235 rx->page_offset = (rx->page_offset + 4096) & ~4095;
1236 #endif
1237 rx->fill_cnt++;
1238
1239 /* copy 8 descriptors to the firmware at a time */
1240 if ((idx & 7) == 7) {
1241 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1242 &rx->shadow[idx - 7]);
1243 }
1244 }
1245 }
1246
1247 static inline void
1248 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1249 struct myri10ge_rx_buffer_state *info, int bytes)
1250 {
1251 /* unmap the recvd page if we're the only or last user of it */
1252 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1253 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1254 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1255 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1256 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1257 }
1258 }
1259
1260 #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1261 * page into an skb */
1262
1263 static inline int
1264 myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
1265 int bytes, int len, __wsum csum)
1266 {
1267 struct myri10ge_priv *mgp = ss->mgp;
1268 struct sk_buff *skb;
1269 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1270 int i, idx, hlen, remainder;
1271 struct pci_dev *pdev = mgp->pdev;
1272 struct net_device *dev = mgp->dev;
1273 u8 *va;
1274
1275 len += MXGEFW_PAD;
1276 idx = rx->cnt & rx->mask;
1277 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1278 prefetch(va);
1279 /* Fill skb_frag_struct(s) with data from our receive */
1280 for (i = 0, remainder = len; remainder > 0; i++) {
1281 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1282 rx_frags[i].page = rx->info[idx].page;
1283 rx_frags[i].page_offset = rx->info[idx].page_offset;
1284 if (remainder < MYRI10GE_ALLOC_SIZE)
1285 rx_frags[i].size = remainder;
1286 else
1287 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1288 rx->cnt++;
1289 idx = rx->cnt & rx->mask;
1290 remainder -= MYRI10GE_ALLOC_SIZE;
1291 }
1292
1293 if (mgp->csum_flag && myri10ge_lro) {
1294 rx_frags[0].page_offset += MXGEFW_PAD;
1295 rx_frags[0].size -= MXGEFW_PAD;
1296 len -= MXGEFW_PAD;
1297 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
1298 /* opaque, will come back in get_frag_header */
1299 len, len,
1300 (void *)(__force unsigned long)csum, csum);
1301
1302 return 1;
1303 }
1304
1305 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1306
1307 /* allocate an skb to attach the page(s) to. This is done
1308 * after trying LRO, so as to avoid skb allocation overheads */
1309
1310 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1311 if (unlikely(skb == NULL)) {
1312 mgp->stats.rx_dropped++;
1313 do {
1314 i--;
1315 put_page(rx_frags[i].page);
1316 } while (i != 0);
1317 return 0;
1318 }
1319
1320 /* Attach the pages to the skb, and trim off any padding */
1321 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1322 if (skb_shinfo(skb)->frags[0].size <= 0) {
1323 put_page(skb_shinfo(skb)->frags[0].page);
1324 skb_shinfo(skb)->nr_frags = 0;
1325 }
1326 skb->protocol = eth_type_trans(skb, dev);
1327
1328 if (mgp->csum_flag) {
1329 if ((skb->protocol == htons(ETH_P_IP)) ||
1330 (skb->protocol == htons(ETH_P_IPV6))) {
1331 skb->csum = csum;
1332 skb->ip_summed = CHECKSUM_COMPLETE;
1333 } else
1334 myri10ge_vlan_ip_csum(skb, csum);
1335 }
1336 netif_receive_skb(skb);
1337 dev->last_rx = jiffies;
1338 return 1;
1339 }
1340
1341 static inline void
1342 myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
1343 {
1344 struct pci_dev *pdev = ss->mgp->pdev;
1345 struct myri10ge_tx_buf *tx = &ss->tx;
1346 struct netdev_queue *dev_queue;
1347 struct sk_buff *skb;
1348 int idx, len;
1349
1350 while (tx->pkt_done != mcp_index) {
1351 idx = tx->done & tx->mask;
1352 skb = tx->info[idx].skb;
1353
1354 /* Mark as free */
1355 tx->info[idx].skb = NULL;
1356 if (tx->info[idx].last) {
1357 tx->pkt_done++;
1358 tx->info[idx].last = 0;
1359 }
1360 tx->done++;
1361 len = pci_unmap_len(&tx->info[idx], len);
1362 pci_unmap_len_set(&tx->info[idx], len, 0);
1363 if (skb) {
1364 ss->stats.tx_bytes += skb->len;
1365 ss->stats.tx_packets++;
1366 dev_kfree_skb_irq(skb);
1367 if (len)
1368 pci_unmap_single(pdev,
1369 pci_unmap_addr(&tx->info[idx],
1370 bus), len,
1371 PCI_DMA_TODEVICE);
1372 } else {
1373 if (len)
1374 pci_unmap_page(pdev,
1375 pci_unmap_addr(&tx->info[idx],
1376 bus), len,
1377 PCI_DMA_TODEVICE);
1378 }
1379 }
1380
1381 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1382 /*
1383 * Make a minimal effort to prevent the NIC from polling an
1384 * idle tx queue. If we can't get the lock we leave the queue
1385 * active. In this case, either a thread was about to start
1386 * using the queue anyway, or we lost a race and the NIC will
1387 * waste some of its resources polling an inactive queue for a
1388 * while.
1389 */
1390
1391 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1392 __netif_tx_trylock(dev_queue)) {
1393 if (tx->req == tx->done) {
1394 tx->queue_active = 0;
1395 put_be32(htonl(1), tx->send_stop);
1396 mmiowb();
1397 }
1398 __netif_tx_unlock(dev_queue);
1399 }
1400
1401 /* start the queue if we've stopped it */
1402 if (netif_tx_queue_stopped(dev_queue)
1403 && tx->req - tx->done < (tx->mask >> 1)) {
1404 tx->wake_queue++;
1405 netif_tx_wake_queue(dev_queue);
1406 }
1407 }
1408
1409 static inline int
1410 myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1411 {
1412 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1413 struct myri10ge_priv *mgp = ss->mgp;
1414 unsigned long rx_bytes = 0;
1415 unsigned long rx_packets = 0;
1416 unsigned long rx_ok;
1417
1418 int idx = rx_done->idx;
1419 int cnt = rx_done->cnt;
1420 int work_done = 0;
1421 u16 length;
1422 __wsum checksum;
1423
1424 while (rx_done->entry[idx].length != 0 && work_done < budget) {
1425 length = ntohs(rx_done->entry[idx].length);
1426 rx_done->entry[idx].length = 0;
1427 checksum = csum_unfold(rx_done->entry[idx].checksum);
1428 if (length <= mgp->small_bytes)
1429 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
1430 mgp->small_bytes,
1431 length, checksum);
1432 else
1433 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
1434 mgp->big_bytes,
1435 length, checksum);
1436 rx_packets += rx_ok;
1437 rx_bytes += rx_ok * (unsigned long)length;
1438 cnt++;
1439 idx = cnt & (mgp->max_intr_slots - 1);
1440 work_done++;
1441 }
1442 rx_done->idx = idx;
1443 rx_done->cnt = cnt;
1444 ss->stats.rx_packets += rx_packets;
1445 ss->stats.rx_bytes += rx_bytes;
1446
1447 if (myri10ge_lro)
1448 lro_flush_all(&rx_done->lro_mgr);
1449
1450 /* restock receive rings if needed */
1451 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1452 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1453 mgp->small_bytes + MXGEFW_PAD, 0);
1454 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1455 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1456
1457 return work_done;
1458 }
1459
1460 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1461 {
1462 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
1463
1464 if (unlikely(stats->stats_updated)) {
1465 unsigned link_up = ntohl(stats->link_up);
1466 if (mgp->link_state != link_up) {
1467 mgp->link_state = link_up;
1468
1469 if (mgp->link_state == MXGEFW_LINK_UP) {
1470 if (netif_msg_link(mgp))
1471 printk(KERN_INFO
1472 "myri10ge: %s: link up\n",
1473 mgp->dev->name);
1474 netif_carrier_on(mgp->dev);
1475 mgp->link_changes++;
1476 } else {
1477 if (netif_msg_link(mgp))
1478 printk(KERN_INFO
1479 "myri10ge: %s: link %s\n",
1480 mgp->dev->name,
1481 (link_up == MXGEFW_LINK_MYRINET ?
1482 "mismatch (Myrinet detected)" :
1483 "down"));
1484 netif_carrier_off(mgp->dev);
1485 mgp->link_changes++;
1486 }
1487 }
1488 if (mgp->rdma_tags_available !=
1489 ntohl(stats->rdma_tags_available)) {
1490 mgp->rdma_tags_available =
1491 ntohl(stats->rdma_tags_available);
1492 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1493 "%d tags left\n", mgp->dev->name,
1494 mgp->rdma_tags_available);
1495 }
1496 mgp->down_cnt += stats->link_down;
1497 if (stats->link_down)
1498 wake_up(&mgp->down_wq);
1499 }
1500 }
1501
1502 static int myri10ge_poll(struct napi_struct *napi, int budget)
1503 {
1504 struct myri10ge_slice_state *ss =
1505 container_of(napi, struct myri10ge_slice_state, napi);
1506 struct net_device *netdev = ss->mgp->dev;
1507 int work_done;
1508
1509 #ifdef CONFIG_MYRI10GE_DCA
1510 if (ss->mgp->dca_enabled)
1511 myri10ge_update_dca(ss);
1512 #endif
1513
1514 /* process as many rx events as NAPI will allow */
1515 work_done = myri10ge_clean_rx_done(ss, budget);
1516
1517 if (work_done < budget) {
1518 netif_rx_complete(netdev, napi);
1519 put_be32(htonl(3), ss->irq_claim);
1520 }
1521 return work_done;
1522 }
1523
1524 static irqreturn_t myri10ge_intr(int irq, void *arg)
1525 {
1526 struct myri10ge_slice_state *ss = arg;
1527 struct myri10ge_priv *mgp = ss->mgp;
1528 struct mcp_irq_data *stats = ss->fw_stats;
1529 struct myri10ge_tx_buf *tx = &ss->tx;
1530 u32 send_done_count;
1531 int i;
1532
1533 /* an interrupt on a non-zero receive-only slice is implicitly
1534 * valid since MSI-X irqs are not shared */
1535 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
1536 netif_rx_schedule(ss->dev, &ss->napi);
1537 return (IRQ_HANDLED);
1538 }
1539
1540 /* make sure it is our IRQ, and that the DMA has finished */
1541 if (unlikely(!stats->valid))
1542 return (IRQ_NONE);
1543
1544 /* low bit indicates receives are present, so schedule
1545 * napi poll handler */
1546 if (stats->valid & 1)
1547 netif_rx_schedule(ss->dev, &ss->napi);
1548
1549 if (!mgp->msi_enabled && !mgp->msix_enabled) {
1550 put_be32(0, mgp->irq_deassert);
1551 if (!myri10ge_deassert_wait)
1552 stats->valid = 0;
1553 mb();
1554 } else
1555 stats->valid = 0;
1556
1557 /* Wait for IRQ line to go low, if using INTx */
1558 i = 0;
1559 while (1) {
1560 i++;
1561 /* check for transmit completes and receives */
1562 send_done_count = ntohl(stats->send_done_count);
1563 if (send_done_count != tx->pkt_done)
1564 myri10ge_tx_done(ss, (int)send_done_count);
1565 if (unlikely(i > myri10ge_max_irq_loops)) {
1566 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1567 mgp->dev->name);
1568 stats->valid = 0;
1569 schedule_work(&mgp->watchdog_work);
1570 }
1571 if (likely(stats->valid == 0))
1572 break;
1573 cpu_relax();
1574 barrier();
1575 }
1576
1577 /* Only slice 0 updates stats */
1578 if (ss == mgp->ss)
1579 myri10ge_check_statblock(mgp);
1580
1581 put_be32(htonl(3), ss->irq_claim + 1);
1582 return (IRQ_HANDLED);
1583 }
1584
1585 static int
1586 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1587 {
1588 struct myri10ge_priv *mgp = netdev_priv(netdev);
1589 char *ptr;
1590 int i;
1591
1592 cmd->autoneg = AUTONEG_DISABLE;
1593 cmd->speed = SPEED_10000;
1594 cmd->duplex = DUPLEX_FULL;
1595
1596 /*
1597 * parse the product code to deterimine the interface type
1598 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1599 * after the 3rd dash in the driver's cached copy of the
1600 * EEPROM's product code string.
1601 */
1602 ptr = mgp->product_code_string;
1603 if (ptr == NULL) {
1604 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
1605 netdev->name);
1606 return 0;
1607 }
1608 for (i = 0; i < 3; i++, ptr++) {
1609 ptr = strchr(ptr, '-');
1610 if (ptr == NULL) {
1611 printk(KERN_ERR "myri10ge: %s: Invalid product "
1612 "code %s\n", netdev->name,
1613 mgp->product_code_string);
1614 return 0;
1615 }
1616 }
1617 if (*ptr == 'R' || *ptr == 'Q') {
1618 /* We've found either an XFP or quad ribbon fiber */
1619 cmd->port = PORT_FIBRE;
1620 }
1621 return 0;
1622 }
1623
1624 static void
1625 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1626 {
1627 struct myri10ge_priv *mgp = netdev_priv(netdev);
1628
1629 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1630 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1631 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1632 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1633 }
1634
1635 static int
1636 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1637 {
1638 struct myri10ge_priv *mgp = netdev_priv(netdev);
1639
1640 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1641 return 0;
1642 }
1643
1644 static int
1645 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1646 {
1647 struct myri10ge_priv *mgp = netdev_priv(netdev);
1648
1649 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1650 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1651 return 0;
1652 }
1653
1654 static void
1655 myri10ge_get_pauseparam(struct net_device *netdev,
1656 struct ethtool_pauseparam *pause)
1657 {
1658 struct myri10ge_priv *mgp = netdev_priv(netdev);
1659
1660 pause->autoneg = 0;
1661 pause->rx_pause = mgp->pause;
1662 pause->tx_pause = mgp->pause;
1663 }
1664
1665 static int
1666 myri10ge_set_pauseparam(struct net_device *netdev,
1667 struct ethtool_pauseparam *pause)
1668 {
1669 struct myri10ge_priv *mgp = netdev_priv(netdev);
1670
1671 if (pause->tx_pause != mgp->pause)
1672 return myri10ge_change_pause(mgp, pause->tx_pause);
1673 if (pause->rx_pause != mgp->pause)
1674 return myri10ge_change_pause(mgp, pause->tx_pause);
1675 if (pause->autoneg != 0)
1676 return -EINVAL;
1677 return 0;
1678 }
1679
1680 static void
1681 myri10ge_get_ringparam(struct net_device *netdev,
1682 struct ethtool_ringparam *ring)
1683 {
1684 struct myri10ge_priv *mgp = netdev_priv(netdev);
1685
1686 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1687 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
1688 ring->rx_jumbo_max_pending = 0;
1689 ring->tx_max_pending = mgp->ss[0].rx_small.mask + 1;
1690 ring->rx_mini_pending = ring->rx_mini_max_pending;
1691 ring->rx_pending = ring->rx_max_pending;
1692 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1693 ring->tx_pending = ring->tx_max_pending;
1694 }
1695
1696 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1697 {
1698 struct myri10ge_priv *mgp = netdev_priv(netdev);
1699
1700 if (mgp->csum_flag)
1701 return 1;
1702 else
1703 return 0;
1704 }
1705
1706 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1707 {
1708 struct myri10ge_priv *mgp = netdev_priv(netdev);
1709
1710 if (csum_enabled)
1711 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1712 else
1713 mgp->csum_flag = 0;
1714 return 0;
1715 }
1716
1717 static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1718 {
1719 struct myri10ge_priv *mgp = netdev_priv(netdev);
1720 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1721
1722 if (tso_enabled)
1723 netdev->features |= flags;
1724 else
1725 netdev->features &= ~flags;
1726 return 0;
1727 }
1728
1729 static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1730 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1731 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1732 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1733 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1734 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1735 "tx_heartbeat_errors", "tx_window_errors",
1736 /* device-specific stats */
1737 "tx_boundary", "WC", "irq", "MSI", "MSIX",
1738 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1739 "serial_number", "watchdog_resets",
1740 #ifdef CONFIG_MYRI10GE_DCA
1741 "dca_capable_firmware", "dca_device_present",
1742 #endif
1743 "link_changes", "link_up", "dropped_link_overflow",
1744 "dropped_link_error_or_filtered",
1745 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1746 "dropped_unicast_filtered", "dropped_multicast_filtered",
1747 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1748 "dropped_no_big_buffer"
1749 };
1750
1751 static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1752 "----------- slice ---------",
1753 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1754 "rx_small_cnt", "rx_big_cnt",
1755 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1756 "LRO flushed",
1757 "LRO avg aggr", "LRO no_desc"
1758 };
1759
1760 #define MYRI10GE_NET_STATS_LEN 21
1761 #define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1762 #define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1763
1764 static void
1765 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1766 {
1767 struct myri10ge_priv *mgp = netdev_priv(netdev);
1768 int i;
1769
1770 switch (stringset) {
1771 case ETH_SS_STATS:
1772 memcpy(data, *myri10ge_gstrings_main_stats,
1773 sizeof(myri10ge_gstrings_main_stats));
1774 data += sizeof(myri10ge_gstrings_main_stats);
1775 for (i = 0; i < mgp->num_slices; i++) {
1776 memcpy(data, *myri10ge_gstrings_slice_stats,
1777 sizeof(myri10ge_gstrings_slice_stats));
1778 data += sizeof(myri10ge_gstrings_slice_stats);
1779 }
1780 break;
1781 }
1782 }
1783
1784 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1785 {
1786 struct myri10ge_priv *mgp = netdev_priv(netdev);
1787
1788 switch (sset) {
1789 case ETH_SS_STATS:
1790 return MYRI10GE_MAIN_STATS_LEN +
1791 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
1792 default:
1793 return -EOPNOTSUPP;
1794 }
1795 }
1796
1797 static void
1798 myri10ge_get_ethtool_stats(struct net_device *netdev,
1799 struct ethtool_stats *stats, u64 * data)
1800 {
1801 struct myri10ge_priv *mgp = netdev_priv(netdev);
1802 struct myri10ge_slice_state *ss;
1803 int slice;
1804 int i;
1805
1806 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1807 data[i] = ((unsigned long *)&mgp->stats)[i];
1808
1809 data[i++] = (unsigned int)mgp->tx_boundary;
1810 data[i++] = (unsigned int)mgp->wc_enabled;
1811 data[i++] = (unsigned int)mgp->pdev->irq;
1812 data[i++] = (unsigned int)mgp->msi_enabled;
1813 data[i++] = (unsigned int)mgp->msix_enabled;
1814 data[i++] = (unsigned int)mgp->read_dma;
1815 data[i++] = (unsigned int)mgp->write_dma;
1816 data[i++] = (unsigned int)mgp->read_write_dma;
1817 data[i++] = (unsigned int)mgp->serial_number;
1818 data[i++] = (unsigned int)mgp->watchdog_resets;
1819 #ifdef CONFIG_MYRI10GE_DCA
1820 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1821 data[i++] = (unsigned int)(mgp->dca_enabled);
1822 #endif
1823 data[i++] = (unsigned int)mgp->link_changes;
1824
1825 /* firmware stats are useful only in the first slice */
1826 ss = &mgp->ss[0];
1827 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1828 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1829 data[i++] =
1830 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1831 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1832 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1833 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1834 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
1835 data[i++] =
1836 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1837 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1838 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1839 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1840 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1841
1842 for (slice = 0; slice < mgp->num_slices; slice++) {
1843 ss = &mgp->ss[slice];
1844 data[i++] = slice;
1845 data[i++] = (unsigned int)ss->tx.pkt_start;
1846 data[i++] = (unsigned int)ss->tx.pkt_done;
1847 data[i++] = (unsigned int)ss->tx.req;
1848 data[i++] = (unsigned int)ss->tx.done;
1849 data[i++] = (unsigned int)ss->rx_small.cnt;
1850 data[i++] = (unsigned int)ss->rx_big.cnt;
1851 data[i++] = (unsigned int)ss->tx.wake_queue;
1852 data[i++] = (unsigned int)ss->tx.stop_queue;
1853 data[i++] = (unsigned int)ss->tx.linearized;
1854 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1855 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1856 if (ss->rx_done.lro_mgr.stats.flushed)
1857 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1858 ss->rx_done.lro_mgr.stats.flushed;
1859 else
1860 data[i++] = 0;
1861 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1862 }
1863 }
1864
1865 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1866 {
1867 struct myri10ge_priv *mgp = netdev_priv(netdev);
1868 mgp->msg_enable = value;
1869 }
1870
1871 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1872 {
1873 struct myri10ge_priv *mgp = netdev_priv(netdev);
1874 return mgp->msg_enable;
1875 }
1876
1877 static const struct ethtool_ops myri10ge_ethtool_ops = {
1878 .get_settings = myri10ge_get_settings,
1879 .get_drvinfo = myri10ge_get_drvinfo,
1880 .get_coalesce = myri10ge_get_coalesce,
1881 .set_coalesce = myri10ge_set_coalesce,
1882 .get_pauseparam = myri10ge_get_pauseparam,
1883 .set_pauseparam = myri10ge_set_pauseparam,
1884 .get_ringparam = myri10ge_get_ringparam,
1885 .get_rx_csum = myri10ge_get_rx_csum,
1886 .set_rx_csum = myri10ge_set_rx_csum,
1887 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1888 .set_sg = ethtool_op_set_sg,
1889 .set_tso = myri10ge_set_tso,
1890 .get_link = ethtool_op_get_link,
1891 .get_strings = myri10ge_get_strings,
1892 .get_sset_count = myri10ge_get_sset_count,
1893 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1894 .set_msglevel = myri10ge_set_msglevel,
1895 .get_msglevel = myri10ge_get_msglevel
1896 };
1897
1898 static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1899 {
1900 struct myri10ge_priv *mgp = ss->mgp;
1901 struct myri10ge_cmd cmd;
1902 struct net_device *dev = mgp->dev;
1903 int tx_ring_size, rx_ring_size;
1904 int tx_ring_entries, rx_ring_entries;
1905 int i, slice, status;
1906 size_t bytes;
1907
1908 /* get ring sizes */
1909 slice = ss - mgp->ss;
1910 cmd.data0 = slice;
1911 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1912 tx_ring_size = cmd.data0;
1913 cmd.data0 = slice;
1914 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1915 if (status != 0)
1916 return status;
1917 rx_ring_size = cmd.data0;
1918
1919 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1920 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1921 ss->tx.mask = tx_ring_entries - 1;
1922 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
1923
1924 status = -ENOMEM;
1925
1926 /* allocate the host shadow rings */
1927
1928 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1929 * sizeof(*ss->tx.req_list);
1930 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1931 if (ss->tx.req_bytes == NULL)
1932 goto abort_with_nothing;
1933
1934 /* ensure req_list entries are aligned to 8 bytes */
1935 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1936 ALIGN((unsigned long)ss->tx.req_bytes, 8);
1937 ss->tx.queue_active = 0;
1938
1939 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1940 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1941 if (ss->rx_small.shadow == NULL)
1942 goto abort_with_tx_req_bytes;
1943
1944 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1945 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1946 if (ss->rx_big.shadow == NULL)
1947 goto abort_with_rx_small_shadow;
1948
1949 /* allocate the host info rings */
1950
1951 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1952 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1953 if (ss->tx.info == NULL)
1954 goto abort_with_rx_big_shadow;
1955
1956 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1957 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1958 if (ss->rx_small.info == NULL)
1959 goto abort_with_tx_info;
1960
1961 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1962 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1963 if (ss->rx_big.info == NULL)
1964 goto abort_with_rx_small_info;
1965
1966 /* Fill the receive rings */
1967 ss->rx_big.cnt = 0;
1968 ss->rx_small.cnt = 0;
1969 ss->rx_big.fill_cnt = 0;
1970 ss->rx_small.fill_cnt = 0;
1971 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1972 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1973 ss->rx_small.watchdog_needed = 0;
1974 ss->rx_big.watchdog_needed = 0;
1975 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1976 mgp->small_bytes + MXGEFW_PAD, 0);
1977
1978 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
1979 printk(KERN_ERR
1980 "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
1981 dev->name, slice, ss->rx_small.fill_cnt);
1982 goto abort_with_rx_small_ring;
1983 }
1984
1985 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1986 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
1987 printk(KERN_ERR
1988 "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
1989 dev->name, slice, ss->rx_big.fill_cnt);
1990 goto abort_with_rx_big_ring;
1991 }
1992
1993 return 0;
1994
1995 abort_with_rx_big_ring:
1996 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1997 int idx = i & ss->rx_big.mask;
1998 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
1999 mgp->big_bytes);
2000 put_page(ss->rx_big.info[idx].page);
2001 }
2002
2003 abort_with_rx_small_ring:
2004 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2005 int idx = i & ss->rx_small.mask;
2006 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2007 mgp->small_bytes + MXGEFW_PAD);
2008 put_page(ss->rx_small.info[idx].page);
2009 }
2010
2011 kfree(ss->rx_big.info);
2012
2013 abort_with_rx_small_info:
2014 kfree(ss->rx_small.info);
2015
2016 abort_with_tx_info:
2017 kfree(ss->tx.info);
2018
2019 abort_with_rx_big_shadow:
2020 kfree(ss->rx_big.shadow);
2021
2022 abort_with_rx_small_shadow:
2023 kfree(ss->rx_small.shadow);
2024
2025 abort_with_tx_req_bytes:
2026 kfree(ss->tx.req_bytes);
2027 ss->tx.req_bytes = NULL;
2028 ss->tx.req_list = NULL;
2029
2030 abort_with_nothing:
2031 return status;
2032 }
2033
2034 static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
2035 {
2036 struct myri10ge_priv *mgp = ss->mgp;
2037 struct sk_buff *skb;
2038 struct myri10ge_tx_buf *tx;
2039 int i, len, idx;
2040
2041 /* If not allocated, skip it */
2042 if (ss->tx.req_list == NULL)
2043 return;
2044
2045 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2046 idx = i & ss->rx_big.mask;
2047 if (i == ss->rx_big.fill_cnt - 1)
2048 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2049 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2050 mgp->big_bytes);
2051 put_page(ss->rx_big.info[idx].page);
2052 }
2053
2054 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2055 idx = i & ss->rx_small.mask;
2056 if (i == ss->rx_small.fill_cnt - 1)
2057 ss->rx_small.info[idx].page_offset =
2058 MYRI10GE_ALLOC_SIZE;
2059 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2060 mgp->small_bytes + MXGEFW_PAD);
2061 put_page(ss->rx_small.info[idx].page);
2062 }
2063 tx = &ss->tx;
2064 while (tx->done != tx->req) {
2065 idx = tx->done & tx->mask;
2066 skb = tx->info[idx].skb;
2067
2068 /* Mark as free */
2069 tx->info[idx].skb = NULL;
2070 tx->done++;
2071 len = pci_unmap_len(&tx->info[idx], len);
2072 pci_unmap_len_set(&tx->info[idx], len, 0);
2073 if (skb) {
2074 ss->stats.tx_dropped++;
2075 dev_kfree_skb_any(skb);
2076 if (len)
2077 pci_unmap_single(mgp->pdev,
2078 pci_unmap_addr(&tx->info[idx],
2079 bus), len,
2080 PCI_DMA_TODEVICE);
2081 } else {
2082 if (len)
2083 pci_unmap_page(mgp->pdev,
2084 pci_unmap_addr(&tx->info[idx],
2085 bus), len,
2086 PCI_DMA_TODEVICE);
2087 }
2088 }
2089 kfree(ss->rx_big.info);
2090
2091 kfree(ss->rx_small.info);
2092
2093 kfree(ss->tx.info);
2094
2095 kfree(ss->rx_big.shadow);
2096
2097 kfree(ss->rx_small.shadow);
2098
2099 kfree(ss->tx.req_bytes);
2100 ss->tx.req_bytes = NULL;
2101 ss->tx.req_list = NULL;
2102 }
2103
2104 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2105 {
2106 struct pci_dev *pdev = mgp->pdev;
2107 struct myri10ge_slice_state *ss;
2108 struct net_device *netdev = mgp->dev;
2109 int i;
2110 int status;
2111
2112 mgp->msi_enabled = 0;
2113 mgp->msix_enabled = 0;
2114 status = 0;
2115 if (myri10ge_msi) {
2116 if (mgp->num_slices > 1) {
2117 status =
2118 pci_enable_msix(pdev, mgp->msix_vectors,
2119 mgp->num_slices);
2120 if (status == 0) {
2121 mgp->msix_enabled = 1;
2122 } else {
2123 dev_err(&pdev->dev,
2124 "Error %d setting up MSI-X\n", status);
2125 return status;
2126 }
2127 }
2128 if (mgp->msix_enabled == 0) {
2129 status = pci_enable_msi(pdev);
2130 if (status != 0) {
2131 dev_err(&pdev->dev,
2132 "Error %d setting up MSI; falling back to xPIC\n",
2133 status);
2134 } else {
2135 mgp->msi_enabled = 1;
2136 }
2137 }
2138 }
2139 if (mgp->msix_enabled) {
2140 for (i = 0; i < mgp->num_slices; i++) {
2141 ss = &mgp->ss[i];
2142 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2143 "%s:slice-%d", netdev->name, i);
2144 status = request_irq(mgp->msix_vectors[i].vector,
2145 myri10ge_intr, 0, ss->irq_desc,
2146 ss);
2147 if (status != 0) {
2148 dev_err(&pdev->dev,
2149 "slice %d failed to allocate IRQ\n", i);
2150 i--;
2151 while (i >= 0) {
2152 free_irq(mgp->msix_vectors[i].vector,
2153 &mgp->ss[i]);
2154 i--;
2155 }
2156 pci_disable_msix(pdev);
2157 return status;
2158 }
2159 }
2160 } else {
2161 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2162 mgp->dev->name, &mgp->ss[0]);
2163 if (status != 0) {
2164 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2165 if (mgp->msi_enabled)
2166 pci_disable_msi(pdev);
2167 }
2168 }
2169 return status;
2170 }
2171
2172 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2173 {
2174 struct pci_dev *pdev = mgp->pdev;
2175 int i;
2176
2177 if (mgp->msix_enabled) {
2178 for (i = 0; i < mgp->num_slices; i++)
2179 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2180 } else {
2181 free_irq(pdev->irq, &mgp->ss[0]);
2182 }
2183 if (mgp->msi_enabled)
2184 pci_disable_msi(pdev);
2185 if (mgp->msix_enabled)
2186 pci_disable_msix(pdev);
2187 }
2188
2189 static int
2190 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2191 void **ip_hdr, void **tcpudp_hdr,
2192 u64 * hdr_flags, void *priv)
2193 {
2194 struct ethhdr *eh;
2195 struct vlan_ethhdr *veh;
2196 struct iphdr *iph;
2197 u8 *va = page_address(frag->page) + frag->page_offset;
2198 unsigned long ll_hlen;
2199 /* passed opaque through lro_receive_frags() */
2200 __wsum csum = (__force __wsum) (unsigned long)priv;
2201
2202 /* find the mac header, aborting if not IPv4 */
2203
2204 eh = (struct ethhdr *)va;
2205 *mac_hdr = eh;
2206 ll_hlen = ETH_HLEN;
2207 if (eh->h_proto != htons(ETH_P_IP)) {
2208 if (eh->h_proto == htons(ETH_P_8021Q)) {
2209 veh = (struct vlan_ethhdr *)va;
2210 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2211 return -1;
2212
2213 ll_hlen += VLAN_HLEN;
2214
2215 /*
2216 * HW checksum starts ETH_HLEN bytes into
2217 * frame, so we must subtract off the VLAN
2218 * header's checksum before csum can be used
2219 */
2220 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2221 VLAN_HLEN, 0));
2222 } else {
2223 return -1;
2224 }
2225 }
2226 *hdr_flags = LRO_IPV4;
2227
2228 iph = (struct iphdr *)(va + ll_hlen);
2229 *ip_hdr = iph;
2230 if (iph->protocol != IPPROTO_TCP)
2231 return -1;
2232 *hdr_flags |= LRO_TCP;
2233 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2234
2235 /* verify the IP checksum */
2236 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2237 return -1;
2238
2239 /* verify the checksum */
2240 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2241 ntohs(iph->tot_len) - (iph->ihl << 2),
2242 IPPROTO_TCP, csum)))
2243 return -1;
2244
2245 return 0;
2246 }
2247
2248 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2249 {
2250 struct myri10ge_cmd cmd;
2251 struct myri10ge_slice_state *ss;
2252 int status;
2253
2254 ss = &mgp->ss[slice];
2255 status = 0;
2256 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2257 cmd.data0 = slice;
2258 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2259 &cmd, 0);
2260 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2261 (mgp->sram + cmd.data0);
2262 }
2263 cmd.data0 = slice;
2264 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2265 &cmd, 0);
2266 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2267 (mgp->sram + cmd.data0);
2268
2269 cmd.data0 = slice;
2270 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2271 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2272 (mgp->sram + cmd.data0);
2273
2274 ss->tx.send_go = (__iomem __be32 *)
2275 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2276 ss->tx.send_stop = (__iomem __be32 *)
2277 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
2278 return status;
2279
2280 }
2281
2282 static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2283 {
2284 struct myri10ge_cmd cmd;
2285 struct myri10ge_slice_state *ss;
2286 int status;
2287
2288 ss = &mgp->ss[slice];
2289 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2290 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
2291 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
2292 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2293 if (status == -ENOSYS) {
2294 dma_addr_t bus = ss->fw_stats_bus;
2295 if (slice != 0)
2296 return -EINVAL;
2297 bus += offsetof(struct mcp_irq_data, send_done_count);
2298 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2299 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2300 status = myri10ge_send_cmd(mgp,
2301 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2302 &cmd, 0);
2303 /* Firmware cannot support multicast without STATS_DMA_V2 */
2304 mgp->fw_multicast_support = 0;
2305 } else {
2306 mgp->fw_multicast_support = 1;
2307 }
2308 return 0;
2309 }
2310
2311 static int myri10ge_open(struct net_device *dev)
2312 {
2313 struct myri10ge_slice_state *ss;
2314 struct myri10ge_priv *mgp = netdev_priv(dev);
2315 struct myri10ge_cmd cmd;
2316 int i, status, big_pow2, slice;
2317 u8 *itable;
2318 struct net_lro_mgr *lro_mgr;
2319
2320 if (mgp->running != MYRI10GE_ETH_STOPPED)
2321 return -EBUSY;
2322
2323 mgp->running = MYRI10GE_ETH_STARTING;
2324 status = myri10ge_reset(mgp);
2325 if (status != 0) {
2326 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
2327 goto abort_with_nothing;
2328 }
2329
2330 if (mgp->num_slices > 1) {
2331 cmd.data0 = mgp->num_slices;
2332 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2333 if (mgp->dev->real_num_tx_queues > 1)
2334 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
2335 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2336 &cmd, 0);
2337 if (status != 0) {
2338 printk(KERN_ERR
2339 "myri10ge: %s: failed to set number of slices\n",
2340 dev->name);
2341 goto abort_with_nothing;
2342 }
2343 /* setup the indirection table */
2344 cmd.data0 = mgp->num_slices;
2345 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2346 &cmd, 0);
2347
2348 status |= myri10ge_send_cmd(mgp,
2349 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2350 &cmd, 0);
2351 if (status != 0) {
2352 printk(KERN_ERR
2353 "myri10ge: %s: failed to setup rss tables\n",
2354 dev->name);
2355 goto abort_with_nothing;
2356 }
2357
2358 /* just enable an identity mapping */
2359 itable = mgp->sram + cmd.data0;
2360 for (i = 0; i < mgp->num_slices; i++)
2361 __raw_writeb(i, &itable[i]);
2362
2363 cmd.data0 = 1;
2364 cmd.data1 = myri10ge_rss_hash;
2365 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2366 &cmd, 0);
2367 if (status != 0) {
2368 printk(KERN_ERR
2369 "myri10ge: %s: failed to enable slices\n",
2370 dev->name);
2371 goto abort_with_nothing;
2372 }
2373 }
2374
2375 status = myri10ge_request_irq(mgp);
2376 if (status != 0)
2377 goto abort_with_nothing;
2378
2379 /* decide what small buffer size to use. For good TCP rx
2380 * performance, it is important to not receive 1514 byte
2381 * frames into jumbo buffers, as it confuses the socket buffer
2382 * accounting code, leading to drops and erratic performance.
2383 */
2384
2385 if (dev->mtu <= ETH_DATA_LEN)
2386 /* enough for a TCP header */
2387 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2388 ? (128 - MXGEFW_PAD)
2389 : (SMP_CACHE_BYTES - MXGEFW_PAD);
2390 else
2391 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2392 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
2393
2394 /* Override the small buffer size? */
2395 if (myri10ge_small_bytes > 0)
2396 mgp->small_bytes = myri10ge_small_bytes;
2397
2398 /* Firmware needs the big buff size as a power of 2. Lie and
2399 * tell him the buffer is larger, because we only use 1
2400 * buffer/pkt, and the mtu will prevent overruns.
2401 */
2402 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2403 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
2404 while (!is_power_of_2(big_pow2))
2405 big_pow2++;
2406 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2407 } else {
2408 big_pow2 = MYRI10GE_ALLOC_SIZE;
2409 mgp->big_bytes = big_pow2;
2410 }
2411
2412 /* setup the per-slice data structures */
2413 for (slice = 0; slice < mgp->num_slices; slice++) {
2414 ss = &mgp->ss[slice];
2415
2416 status = myri10ge_get_txrx(mgp, slice);
2417 if (status != 0) {
2418 printk(KERN_ERR
2419 "myri10ge: %s: failed to get ring sizes or locations\n",
2420 dev->name);
2421 goto abort_with_rings;
2422 }
2423 status = myri10ge_allocate_rings(ss);
2424 if (status != 0)
2425 goto abort_with_rings;
2426
2427 /* only firmware which supports multiple TX queues
2428 * supports setting up the tx stats on non-zero
2429 * slices */
2430 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
2431 status = myri10ge_set_stats(mgp, slice);
2432 if (status) {
2433 printk(KERN_ERR
2434 "myri10ge: %s: Couldn't set stats DMA\n",
2435 dev->name);
2436 goto abort_with_rings;
2437 }
2438
2439 lro_mgr = &ss->rx_done.lro_mgr;
2440 lro_mgr->dev = dev;
2441 lro_mgr->features = LRO_F_NAPI;
2442 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2443 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2444 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2445 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2446 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2447 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2448 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2449 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2450
2451 /* must happen prior to any irq */
2452 napi_enable(&(ss)->napi);
2453 }
2454
2455 /* now give firmware buffers sizes, and MTU */
2456 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2457 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2458 cmd.data0 = mgp->small_bytes;
2459 status |=
2460 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2461 cmd.data0 = big_pow2;
2462 status |=
2463 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2464 if (status) {
2465 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2466 dev->name);
2467 goto abort_with_rings;
2468 }
2469
2470 /*
2471 * Set Linux style TSO mode; this is needed only on newer
2472 * firmware versions. Older versions default to Linux
2473 * style TSO
2474 */
2475 cmd.data0 = 0;
2476 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2477 if (status && status != -ENOSYS) {
2478 printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n",
2479 dev->name);
2480 goto abort_with_rings;
2481 }
2482
2483 mgp->link_state = ~0U;
2484 mgp->rdma_tags_available = 15;
2485
2486 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2487 if (status) {
2488 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2489 dev->name);
2490 goto abort_with_rings;
2491 }
2492
2493 mgp->running = MYRI10GE_ETH_RUNNING;
2494 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2495 add_timer(&mgp->watchdog_timer);
2496 netif_tx_wake_all_queues(dev);
2497
2498 return 0;
2499
2500 abort_with_rings:
2501 while (slice) {
2502 slice--;
2503 napi_disable(&mgp->ss[slice].napi);
2504 }
2505 for (i = 0; i < mgp->num_slices; i++)
2506 myri10ge_free_rings(&mgp->ss[i]);
2507
2508 myri10ge_free_irq(mgp);
2509
2510 abort_with_nothing:
2511 mgp->running = MYRI10GE_ETH_STOPPED;
2512 return -ENOMEM;
2513 }
2514
2515 static int myri10ge_close(struct net_device *dev)
2516 {
2517 struct myri10ge_priv *mgp = netdev_priv(dev);
2518 struct myri10ge_cmd cmd;
2519 int status, old_down_cnt;
2520 int i;
2521
2522 if (mgp->running != MYRI10GE_ETH_RUNNING)
2523 return 0;
2524
2525 if (mgp->ss[0].tx.req_bytes == NULL)
2526 return 0;
2527
2528 del_timer_sync(&mgp->watchdog_timer);
2529 mgp->running = MYRI10GE_ETH_STOPPING;
2530 for (i = 0; i < mgp->num_slices; i++) {
2531 napi_disable(&mgp->ss[i].napi);
2532 }
2533 netif_carrier_off(dev);
2534
2535 netif_tx_stop_all_queues(dev);
2536 old_down_cnt = mgp->down_cnt;
2537 mb();
2538 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2539 if (status)
2540 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2541 dev->name);
2542
2543 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2544 if (old_down_cnt == mgp->down_cnt)
2545 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2546
2547 netif_tx_disable(dev);
2548 myri10ge_free_irq(mgp);
2549 for (i = 0; i < mgp->num_slices; i++)
2550 myri10ge_free_rings(&mgp->ss[i]);
2551
2552 mgp->running = MYRI10GE_ETH_STOPPED;
2553 return 0;
2554 }
2555
2556 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2557 * backwards one at a time and handle ring wraps */
2558
2559 static inline void
2560 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2561 struct mcp_kreq_ether_send *src, int cnt)
2562 {
2563 int idx, starting_slot;
2564 starting_slot = tx->req;
2565 while (cnt > 1) {
2566 cnt--;
2567 idx = (starting_slot + cnt) & tx->mask;
2568 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2569 mb();
2570 }
2571 }
2572
2573 /*
2574 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2575 * at most 32 bytes at a time, so as to avoid involving the software
2576 * pio handler in the nic. We re-write the first segment's flags
2577 * to mark them valid only after writing the entire chain.
2578 */
2579
2580 static inline void
2581 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2582 int cnt)
2583 {
2584 int idx, i;
2585 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2586 struct mcp_kreq_ether_send *srcp;
2587 u8 last_flags;
2588
2589 idx = tx->req & tx->mask;
2590
2591 last_flags = src->flags;
2592 src->flags = 0;
2593 mb();
2594 dst = dstp = &tx->lanai[idx];
2595 srcp = src;
2596
2597 if ((idx + cnt) < tx->mask) {
2598 for (i = 0; i < (cnt - 1); i += 2) {
2599 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2600 mb(); /* force write every 32 bytes */
2601 srcp += 2;
2602 dstp += 2;
2603 }
2604 } else {
2605 /* submit all but the first request, and ensure
2606 * that it is submitted below */
2607 myri10ge_submit_req_backwards(tx, src, cnt);
2608 i = 0;
2609 }
2610 if (i < cnt) {
2611 /* submit the first request */
2612 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2613 mb(); /* barrier before setting valid flag */
2614 }
2615
2616 /* re-write the last 32-bits with the valid flags */
2617 src->flags = last_flags;
2618 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2619 tx->req += cnt;
2620 mb();
2621 }
2622
2623 /*
2624 * Transmit a packet. We need to split the packet so that a single
2625 * segment does not cross myri10ge->tx_boundary, so this makes segment
2626 * counting tricky. So rather than try to count segments up front, we
2627 * just give up if there are too few segments to hold a reasonably
2628 * fragmented packet currently available. If we run
2629 * out of segments while preparing a packet for DMA, we just linearize
2630 * it and try again.
2631 */
2632
2633 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2634 {
2635 struct myri10ge_priv *mgp = netdev_priv(dev);
2636 struct myri10ge_slice_state *ss;
2637 struct mcp_kreq_ether_send *req;
2638 struct myri10ge_tx_buf *tx;
2639 struct skb_frag_struct *frag;
2640 struct netdev_queue *netdev_queue;
2641 dma_addr_t bus;
2642 u32 low;
2643 __be32 high_swapped;
2644 unsigned int len;
2645 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2646 u16 pseudo_hdr_offset, cksum_offset, queue;
2647 int cum_len, seglen, boundary, rdma_count;
2648 u8 flags, odd_flag;
2649
2650 queue = skb_get_queue_mapping(skb);
2651 ss = &mgp->ss[queue];
2652 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
2653 tx = &ss->tx;
2654
2655 again:
2656 req = tx->req_list;
2657 avail = tx->mask - 1 - (tx->req - tx->done);
2658
2659 mss = 0;
2660 max_segments = MXGEFW_MAX_SEND_DESC;
2661
2662 if (skb_is_gso(skb)) {
2663 mss = skb_shinfo(skb)->gso_size;
2664 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2665 }
2666
2667 if ((unlikely(avail < max_segments))) {
2668 /* we are out of transmit resources */
2669 tx->stop_queue++;
2670 netif_tx_stop_queue(netdev_queue);
2671 return 1;
2672 }
2673
2674 /* Setup checksum offloading, if needed */
2675 cksum_offset = 0;
2676 pseudo_hdr_offset = 0;
2677 odd_flag = 0;
2678 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2679 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2680 cksum_offset = skb_transport_offset(skb);
2681 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2682 /* If the headers are excessively large, then we must
2683 * fall back to a software checksum */
2684 if (unlikely(!mss && (cksum_offset > 255 ||
2685 pseudo_hdr_offset > 127))) {
2686 if (skb_checksum_help(skb))
2687 goto drop;
2688 cksum_offset = 0;
2689 pseudo_hdr_offset = 0;
2690 } else {
2691 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2692 flags |= MXGEFW_FLAGS_CKSUM;
2693 }
2694 }
2695
2696 cum_len = 0;
2697
2698 if (mss) { /* TSO */
2699 /* this removes any CKSUM flag from before */
2700 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2701
2702 /* negative cum_len signifies to the
2703 * send loop that we are still in the
2704 * header portion of the TSO packet.
2705 * TSO header can be at most 1KB long */
2706 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2707
2708 /* for IPv6 TSO, the checksum offset stores the
2709 * TCP header length, to save the firmware from
2710 * the need to parse the headers */
2711 if (skb_is_gso_v6(skb)) {
2712 cksum_offset = tcp_hdrlen(skb);
2713 /* Can only handle headers <= max_tso6 long */
2714 if (unlikely(-cum_len > mgp->max_tso6))
2715 return myri10ge_sw_tso(skb, dev);
2716 }
2717 /* for TSO, pseudo_hdr_offset holds mss.
2718 * The firmware figures out where to put
2719 * the checksum by parsing the header. */
2720 pseudo_hdr_offset = mss;
2721 } else
2722 /* Mark small packets, and pad out tiny packets */
2723 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2724 flags |= MXGEFW_FLAGS_SMALL;
2725
2726 /* pad frames to at least ETH_ZLEN bytes */
2727 if (unlikely(skb->len < ETH_ZLEN)) {
2728 if (skb_padto(skb, ETH_ZLEN)) {
2729 /* The packet is gone, so we must
2730 * return 0 */
2731 ss->stats.tx_dropped += 1;
2732 return 0;
2733 }
2734 /* adjust the len to account for the zero pad
2735 * so that the nic can know how long it is */
2736 skb->len = ETH_ZLEN;
2737 }
2738 }
2739
2740 /* map the skb for DMA */
2741 len = skb->len - skb->data_len;
2742 idx = tx->req & tx->mask;
2743 tx->info[idx].skb = skb;
2744 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2745 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2746 pci_unmap_len_set(&tx->info[idx], len, len);
2747
2748 frag_cnt = skb_shinfo(skb)->nr_frags;
2749 frag_idx = 0;
2750 count = 0;
2751 rdma_count = 0;
2752
2753 /* "rdma_count" is the number of RDMAs belonging to the
2754 * current packet BEFORE the current send request. For
2755 * non-TSO packets, this is equal to "count".
2756 * For TSO packets, rdma_count needs to be reset
2757 * to 0 after a segment cut.
2758 *
2759 * The rdma_count field of the send request is
2760 * the number of RDMAs of the packet starting at
2761 * that request. For TSO send requests with one ore more cuts
2762 * in the middle, this is the number of RDMAs starting
2763 * after the last cut in the request. All previous
2764 * segments before the last cut implicitly have 1 RDMA.
2765 *
2766 * Since the number of RDMAs is not known beforehand,
2767 * it must be filled-in retroactively - after each
2768 * segmentation cut or at the end of the entire packet.
2769 */
2770
2771 while (1) {
2772 /* Break the SKB or Fragment up into pieces which
2773 * do not cross mgp->tx_boundary */
2774 low = MYRI10GE_LOWPART_TO_U32(bus);
2775 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2776 while (len) {
2777 u8 flags_next;
2778 int cum_len_next;
2779
2780 if (unlikely(count == max_segments))
2781 goto abort_linearize;
2782
2783 boundary =
2784 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2785 seglen = boundary - low;
2786 if (seglen > len)
2787 seglen = len;
2788 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2789 cum_len_next = cum_len + seglen;
2790 if (mss) { /* TSO */
2791 (req - rdma_count)->rdma_count = rdma_count + 1;
2792
2793 if (likely(cum_len >= 0)) { /* payload */
2794 int next_is_first, chop;
2795
2796 chop = (cum_len_next > mss);
2797 cum_len_next = cum_len_next % mss;
2798 next_is_first = (cum_len_next == 0);
2799 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2800 flags_next |= next_is_first *
2801 MXGEFW_FLAGS_FIRST;
2802 rdma_count |= -(chop | next_is_first);
2803 rdma_count += chop & !next_is_first;
2804 } else if (likely(cum_len_next >= 0)) { /* header ends */
2805 int small;
2806
2807 rdma_count = -1;
2808 cum_len_next = 0;
2809 seglen = -cum_len;
2810 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2811 flags_next = MXGEFW_FLAGS_TSO_PLD |
2812 MXGEFW_FLAGS_FIRST |
2813 (small * MXGEFW_FLAGS_SMALL);
2814 }
2815 }
2816 req->addr_high = high_swapped;
2817 req->addr_low = htonl(low);
2818 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2819 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2820 req->rdma_count = 1;
2821 req->length = htons(seglen);
2822 req->cksum_offset = cksum_offset;
2823 req->flags = flags | ((cum_len & 1) * odd_flag);
2824
2825 low += seglen;
2826 len -= seglen;
2827 cum_len = cum_len_next;
2828 flags = flags_next;
2829 req++;
2830 count++;
2831 rdma_count++;
2832 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2833 if (unlikely(cksum_offset > seglen))
2834 cksum_offset -= seglen;
2835 else
2836 cksum_offset = 0;
2837 }
2838 }
2839 if (frag_idx == frag_cnt)
2840 break;
2841
2842 /* map next fragment for DMA */
2843 idx = (count + tx->req) & tx->mask;
2844 frag = &skb_shinfo(skb)->frags[frag_idx];
2845 frag_idx++;
2846 len = frag->size;
2847 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2848 len, PCI_DMA_TODEVICE);
2849 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2850 pci_unmap_len_set(&tx->info[idx], len, len);
2851 }
2852
2853 (req - rdma_count)->rdma_count = rdma_count;
2854 if (mss)
2855 do {
2856 req--;
2857 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2858 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2859 MXGEFW_FLAGS_FIRST)));
2860 idx = ((count - 1) + tx->req) & tx->mask;
2861 tx->info[idx].last = 1;
2862 myri10ge_submit_req(tx, tx->req_list, count);
2863 /* if using multiple tx queues, make sure NIC polls the
2864 * current slice */
2865 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2866 tx->queue_active = 1;
2867 put_be32(htonl(1), tx->send_go);
2868 mmiowb();
2869 }
2870 tx->pkt_start++;
2871 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2872 tx->stop_queue++;
2873 netif_tx_stop_queue(netdev_queue);
2874 }
2875 dev->trans_start = jiffies;
2876 return 0;
2877
2878 abort_linearize:
2879 /* Free any DMA resources we've alloced and clear out the skb
2880 * slot so as to not trip up assertions, and to avoid a
2881 * double-free if linearizing fails */
2882
2883 last_idx = (idx + 1) & tx->mask;
2884 idx = tx->req & tx->mask;
2885 tx->info[idx].skb = NULL;
2886 do {
2887 len = pci_unmap_len(&tx->info[idx], len);
2888 if (len) {
2889 if (tx->info[idx].skb != NULL)
2890 pci_unmap_single(mgp->pdev,
2891 pci_unmap_addr(&tx->info[idx],
2892 bus), len,
2893 PCI_DMA_TODEVICE);
2894 else
2895 pci_unmap_page(mgp->pdev,
2896 pci_unmap_addr(&tx->info[idx],
2897 bus), len,
2898 PCI_DMA_TODEVICE);
2899 pci_unmap_len_set(&tx->info[idx], len, 0);
2900 tx->info[idx].skb = NULL;
2901 }
2902 idx = (idx + 1) & tx->mask;
2903 } while (idx != last_idx);
2904 if (skb_is_gso(skb)) {
2905 printk(KERN_ERR
2906 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2907 mgp->dev->name);
2908 goto drop;
2909 }
2910
2911 if (skb_linearize(skb))
2912 goto drop;
2913
2914 tx->linearized++;
2915 goto again;
2916
2917 drop:
2918 dev_kfree_skb_any(skb);
2919 ss->stats.tx_dropped += 1;
2920 return 0;
2921
2922 }
2923
2924 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2925 {
2926 struct sk_buff *segs, *curr;
2927 struct myri10ge_priv *mgp = netdev_priv(dev);
2928 int status;
2929
2930 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2931 if (IS_ERR(segs))
2932 goto drop;
2933
2934 while (segs) {
2935 curr = segs;
2936 segs = segs->next;
2937 curr->next = NULL;
2938 status = myri10ge_xmit(curr, dev);
2939 if (status != 0) {
2940 dev_kfree_skb_any(curr);
2941 if (segs != NULL) {
2942 curr = segs;
2943 segs = segs->next;
2944 curr->next = NULL;
2945 dev_kfree_skb_any(segs);
2946 }
2947 goto drop;
2948 }
2949 }
2950 dev_kfree_skb_any(skb);
2951 return 0;
2952
2953 drop:
2954 dev_kfree_skb_any(skb);
2955 mgp->stats.tx_dropped += 1;
2956 return 0;
2957 }
2958
2959 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2960 {
2961 struct myri10ge_priv *mgp = netdev_priv(dev);
2962 struct myri10ge_slice_netstats *slice_stats;
2963 struct net_device_stats *stats = &mgp->stats;
2964 int i;
2965
2966 memset(stats, 0, sizeof(*stats));
2967 for (i = 0; i < mgp->num_slices; i++) {
2968 slice_stats = &mgp->ss[i].stats;
2969 stats->rx_packets += slice_stats->rx_packets;
2970 stats->tx_packets += slice_stats->tx_packets;
2971 stats->rx_bytes += slice_stats->rx_bytes;
2972 stats->tx_bytes += slice_stats->tx_bytes;
2973 stats->rx_dropped += slice_stats->rx_dropped;
2974 stats->tx_dropped += slice_stats->tx_dropped;
2975 }
2976 return stats;
2977 }
2978
2979 static void myri10ge_set_multicast_list(struct net_device *dev)
2980 {
2981 struct myri10ge_priv *mgp = netdev_priv(dev);
2982 struct myri10ge_cmd cmd;
2983 struct dev_mc_list *mc_list;
2984 __be32 data[2] = { 0, 0 };
2985 int err;
2986
2987 /* can be called from atomic contexts,
2988 * pass 1 to force atomicity in myri10ge_send_cmd() */
2989 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2990
2991 /* This firmware is known to not support multicast */
2992 if (!mgp->fw_multicast_support)
2993 return;
2994
2995 /* Disable multicast filtering */
2996
2997 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2998 if (err != 0) {
2999 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
3000 " error status: %d\n", dev->name, err);
3001 goto abort;
3002 }
3003
3004 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
3005 /* request to disable multicast filtering, so quit here */
3006 return;
3007 }
3008
3009 /* Flush the filters */
3010
3011 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3012 &cmd, 1);
3013 if (err != 0) {
3014 printk(KERN_ERR
3015 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
3016 ", error status: %d\n", dev->name, err);
3017 goto abort;
3018 }
3019
3020 /* Walk the multicast list, and add each address */
3021 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
3022 memcpy(data, &mc_list->dmi_addr, 6);
3023 cmd.data0 = ntohl(data[0]);
3024 cmd.data1 = ntohl(data[1]);
3025 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3026 &cmd, 1);
3027
3028 if (err != 0) {
3029 printk(KERN_ERR "myri10ge: %s: Failed "
3030 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
3031 "%d\t", dev->name, err);
3032 printk(KERN_ERR "MAC %pM\n", mc_list->dmi_addr);
3033 goto abort;
3034 }
3035 }
3036 /* Enable multicast filtering */
3037 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3038 if (err != 0) {
3039 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
3040 "error status: %d\n", dev->name, err);
3041 goto abort;
3042 }
3043
3044 return;
3045
3046 abort:
3047 return;
3048 }
3049
3050 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3051 {
3052 struct sockaddr *sa = addr;
3053 struct myri10ge_priv *mgp = netdev_priv(dev);
3054 int status;
3055
3056 if (!is_valid_ether_addr(sa->sa_data))
3057 return -EADDRNOTAVAIL;
3058
3059 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3060 if (status != 0) {
3061 printk(KERN_ERR
3062 "myri10ge: %s: changing mac address failed with %d\n",
3063 dev->name, status);
3064 return status;
3065 }
3066
3067 /* change the dev structure */
3068 memcpy(dev->dev_addr, sa->sa_data, 6);
3069 return 0;
3070 }
3071
3072 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3073 {
3074 struct myri10ge_priv *mgp = netdev_priv(dev);
3075 int error = 0;
3076
3077 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3078 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
3079 dev->name, new_mtu);
3080 return -EINVAL;
3081 }
3082 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
3083 dev->name, dev->mtu, new_mtu);
3084 if (mgp->running) {
3085 /* if we change the mtu on an active device, we must
3086 * reset the device so the firmware sees the change */
3087 myri10ge_close(dev);
3088 dev->mtu = new_mtu;
3089 myri10ge_open(dev);
3090 } else
3091 dev->mtu = new_mtu;
3092
3093 return error;
3094 }
3095
3096 /*
3097 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3098 * Only do it if the bridge is a root port since we don't want to disturb
3099 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3100 */
3101
3102 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3103 {
3104 struct pci_dev *bridge = mgp->pdev->bus->self;
3105 struct device *dev = &mgp->pdev->dev;
3106 unsigned cap;
3107 unsigned err_cap;
3108 u16 val;
3109 u8 ext_type;
3110 int ret;
3111
3112 if (!myri10ge_ecrc_enable || !bridge)
3113 return;
3114
3115 /* check that the bridge is a root port */
3116 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3117 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3118 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3119 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3120 if (myri10ge_ecrc_enable > 1) {
3121 struct pci_dev *prev_bridge, *old_bridge = bridge;
3122
3123 /* Walk the hierarchy up to the root port
3124 * where ECRC has to be enabled */
3125 do {
3126 prev_bridge = bridge;
3127 bridge = bridge->bus->self;
3128 if (!bridge || prev_bridge == bridge) {
3129 dev_err(dev,
3130 "Failed to find root port"
3131 " to force ECRC\n");
3132 return;
3133 }
3134 cap =
3135 pci_find_capability(bridge, PCI_CAP_ID_EXP);
3136 pci_read_config_word(bridge,
3137 cap + PCI_CAP_FLAGS, &val);
3138 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3139 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3140
3141 dev_info(dev,
3142 "Forcing ECRC on non-root port %s"
3143 " (enabling on root port %s)\n",
3144 pci_name(old_bridge), pci_name(bridge));
3145 } else {
3146 dev_err(dev,
3147 "Not enabling ECRC on non-root port %s\n",
3148 pci_name(bridge));
3149 return;
3150 }
3151 }
3152
3153 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3154 if (!cap)
3155 return;
3156
3157 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3158 if (ret) {
3159 dev_err(dev, "failed reading ext-conf-space of %s\n",
3160 pci_name(bridge));
3161 dev_err(dev, "\t pci=nommconf in use? "
3162 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3163 return;
3164 }
3165 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3166 return;
3167
3168 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3169 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3170 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
3171 }
3172
3173 /*
3174 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3175 * when the PCI-E Completion packets are aligned on an 8-byte
3176 * boundary. Some PCI-E chip sets always align Completion packets; on
3177 * the ones that do not, the alignment can be enforced by enabling
3178 * ECRC generation (if supported).
3179 *
3180 * When PCI-E Completion packets are not aligned, it is actually more
3181 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3182 *
3183 * If the driver can neither enable ECRC nor verify that it has
3184 * already been enabled, then it must use a firmware image which works
3185 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
3186 * should also ensure that it never gives the device a Read-DMA which is
3187 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
3188 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
3189 * firmware image, and set tx_boundary to 4KB.
3190 */
3191
3192 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
3193 {
3194 struct pci_dev *pdev = mgp->pdev;
3195 struct device *dev = &pdev->dev;
3196 int status;
3197
3198 mgp->tx_boundary = 4096;
3199 /*
3200 * Verify the max read request size was set to 4KB
3201 * before trying the test with 4KB.
3202 */
3203 status = pcie_get_readrq(pdev);
3204 if (status < 0) {
3205 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3206 goto abort;
3207 }
3208 if (status != 4096) {
3209 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
3210 mgp->tx_boundary = 2048;
3211 }
3212 /*
3213 * load the optimized firmware (which assumes aligned PCIe
3214 * completions) in order to see if it works on this host.
3215 */
3216 mgp->fw_name = myri10ge_fw_aligned;
3217 status = myri10ge_load_firmware(mgp, 1);
3218 if (status != 0) {
3219 goto abort;
3220 }
3221
3222 /*
3223 * Enable ECRC if possible
3224 */
3225 myri10ge_enable_ecrc(mgp);
3226
3227 /*
3228 * Run a DMA test which watches for unaligned completions and
3229 * aborts on the first one seen.
3230 */
3231
3232 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3233 if (status == 0)
3234 return; /* keep the aligned firmware */
3235
3236 if (status != -E2BIG)
3237 dev_warn(dev, "DMA test failed: %d\n", status);
3238 if (status == -ENOSYS)
3239 dev_warn(dev, "Falling back to ethp! "
3240 "Please install up to date fw\n");
3241 abort:
3242 /* fall back to using the unaligned firmware */
3243 mgp->tx_boundary = 2048;
3244 mgp->fw_name = myri10ge_fw_unaligned;
3245
3246 }
3247
3248 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3249 {
3250 if (myri10ge_force_firmware == 0) {
3251 int link_width, exp_cap;
3252 u16 lnk;
3253
3254 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3255 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3256 link_width = (lnk >> 4) & 0x3f;
3257
3258 /* Check to see if Link is less than 8 or if the
3259 * upstream bridge is known to provide aligned
3260 * completions */
3261 if (link_width < 8) {
3262 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3263 link_width);
3264 mgp->tx_boundary = 4096;
3265 mgp->fw_name = myri10ge_fw_aligned;
3266 } else {
3267 myri10ge_firmware_probe(mgp);
3268 }
3269 } else {
3270 if (myri10ge_force_firmware == 1) {
3271 dev_info(&mgp->pdev->dev,
3272 "Assuming aligned completions (forced)\n");
3273 mgp->tx_boundary = 4096;
3274 mgp->fw_name = myri10ge_fw_aligned;
3275 } else {
3276 dev_info(&mgp->pdev->dev,
3277 "Assuming unaligned completions (forced)\n");
3278 mgp->tx_boundary = 2048;
3279 mgp->fw_name = myri10ge_fw_unaligned;
3280 }
3281 }
3282 if (myri10ge_fw_name != NULL) {
3283 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3284 myri10ge_fw_name);
3285 mgp->fw_name = myri10ge_fw_name;
3286 }
3287 }
3288
3289 #ifdef CONFIG_PM
3290 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3291 {
3292 struct myri10ge_priv *mgp;
3293 struct net_device *netdev;
3294
3295 mgp = pci_get_drvdata(pdev);
3296 if (mgp == NULL)
3297 return -EINVAL;
3298 netdev = mgp->dev;
3299
3300 netif_device_detach(netdev);
3301 if (netif_running(netdev)) {
3302 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
3303 rtnl_lock();
3304 myri10ge_close(netdev);
3305 rtnl_unlock();
3306 }
3307 myri10ge_dummy_rdma(mgp, 0);
3308 pci_save_state(pdev);
3309 pci_disable_device(pdev);
3310
3311 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
3312 }
3313
3314 static int myri10ge_resume(struct pci_dev *pdev)
3315 {
3316 struct myri10ge_priv *mgp;
3317 struct net_device *netdev;
3318 int status;
3319 u16 vendor;
3320
3321 mgp = pci_get_drvdata(pdev);
3322 if (mgp == NULL)
3323 return -EINVAL;
3324 netdev = mgp->dev;
3325 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
3326 msleep(5); /* give card time to respond */
3327 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3328 if (vendor == 0xffff) {
3329 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
3330 mgp->dev->name);
3331 return -EIO;
3332 }
3333
3334 status = pci_restore_state(pdev);
3335 if (status)
3336 return status;
3337
3338 status = pci_enable_device(pdev);
3339 if (status) {
3340 dev_err(&pdev->dev, "failed to enable device\n");
3341 return status;
3342 }
3343
3344 pci_set_master(pdev);
3345
3346 myri10ge_reset(mgp);
3347 myri10ge_dummy_rdma(mgp, 1);
3348
3349 /* Save configuration space to be restored if the
3350 * nic resets due to a parity error */
3351 pci_save_state(pdev);
3352
3353 if (netif_running(netdev)) {
3354 rtnl_lock();
3355 status = myri10ge_open(netdev);
3356 rtnl_unlock();
3357 if (status != 0)
3358 goto abort_with_enabled;
3359
3360 }
3361 netif_device_attach(netdev);
3362
3363 return 0;
3364
3365 abort_with_enabled:
3366 pci_disable_device(pdev);
3367 return -EIO;
3368
3369 }
3370 #endif /* CONFIG_PM */
3371
3372 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3373 {
3374 struct pci_dev *pdev = mgp->pdev;
3375 int vs = mgp->vendor_specific_offset;
3376 u32 reboot;
3377
3378 /*enter read32 mode */
3379 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3380
3381 /*read REBOOT_STATUS (0xfffffff0) */
3382 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3383 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3384 return reboot;
3385 }
3386
3387 /*
3388 * This watchdog is used to check whether the board has suffered
3389 * from a parity error and needs to be recovered.
3390 */
3391 static void myri10ge_watchdog(struct work_struct *work)
3392 {
3393 struct myri10ge_priv *mgp =
3394 container_of(work, struct myri10ge_priv, watchdog_work);
3395 struct myri10ge_tx_buf *tx;
3396 u32 reboot;
3397 int status;
3398 int i;
3399 u16 cmd, vendor;
3400
3401 mgp->watchdog_resets++;
3402 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3403 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3404 /* Bus master DMA disabled? Check to see
3405 * if the card rebooted due to a parity error
3406 * For now, just report it */
3407 reboot = myri10ge_read_reboot(mgp);
3408 printk(KERN_ERR
3409 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3410 mgp->dev->name, reboot,
3411 myri10ge_reset_recover ? " " : " not");
3412 if (myri10ge_reset_recover == 0)
3413 return;
3414
3415 myri10ge_reset_recover--;
3416
3417 /*
3418 * A rebooted nic will come back with config space as
3419 * it was after power was applied to PCIe bus.
3420 * Attempt to restore config space which was saved
3421 * when the driver was loaded, or the last time the
3422 * nic was resumed from power saving mode.
3423 */
3424 pci_restore_state(mgp->pdev);
3425
3426 /* save state again for accounting reasons */
3427 pci_save_state(mgp->pdev);
3428
3429 } else {
3430 /* if we get back -1's from our slot, perhaps somebody
3431 * powered off our card. Don't try to reset it in
3432 * this case */
3433 if (cmd == 0xffff) {
3434 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3435 if (vendor == 0xffff) {
3436 printk(KERN_ERR
3437 "myri10ge: %s: device disappeared!\n",
3438 mgp->dev->name);
3439 return;
3440 }
3441 }
3442 /* Perhaps it is a software error. Try to reset */
3443
3444 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3445 mgp->dev->name);
3446 for (i = 0; i < mgp->num_slices; i++) {
3447 tx = &mgp->ss[i].tx;
3448 printk(KERN_INFO
3449 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3450 mgp->dev->name, i, tx->queue_active, tx->req,
3451 tx->done, tx->pkt_start, tx->pkt_done,
3452 (int)ntohl(mgp->ss[i].fw_stats->
3453 send_done_count));
3454 msleep(2000);
3455 printk(KERN_INFO
3456 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3457 mgp->dev->name, i, tx->queue_active, tx->req,
3458 tx->done, tx->pkt_start, tx->pkt_done,
3459 (int)ntohl(mgp->ss[i].fw_stats->
3460 send_done_count));
3461 }
3462 }
3463
3464 rtnl_lock();
3465 myri10ge_close(mgp->dev);
3466 status = myri10ge_load_firmware(mgp, 1);
3467 if (status != 0)
3468 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3469 mgp->dev->name);
3470 else
3471 myri10ge_open(mgp->dev);
3472 rtnl_unlock();
3473 }
3474
3475 /*
3476 * We use our own timer routine rather than relying upon
3477 * netdev->tx_timeout because we have a very large hardware transmit
3478 * queue. Due to the large queue, the netdev->tx_timeout function
3479 * cannot detect a NIC with a parity error in a timely fashion if the
3480 * NIC is lightly loaded.
3481 */
3482 static void myri10ge_watchdog_timer(unsigned long arg)
3483 {
3484 struct myri10ge_priv *mgp;
3485 struct myri10ge_slice_state *ss;
3486 int i, reset_needed;
3487 u32 rx_pause_cnt;
3488
3489 mgp = (struct myri10ge_priv *)arg;
3490
3491 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3492 for (i = 0, reset_needed = 0;
3493 i < mgp->num_slices && reset_needed == 0; ++i) {
3494
3495 ss = &mgp->ss[i];
3496 if (ss->rx_small.watchdog_needed) {
3497 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3498 mgp->small_bytes + MXGEFW_PAD,
3499 1);
3500 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3501 myri10ge_fill_thresh)
3502 ss->rx_small.watchdog_needed = 0;
3503 }
3504 if (ss->rx_big.watchdog_needed) {
3505 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3506 mgp->big_bytes, 1);
3507 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3508 myri10ge_fill_thresh)
3509 ss->rx_big.watchdog_needed = 0;
3510 }
3511
3512 if (ss->tx.req != ss->tx.done &&
3513 ss->tx.done == ss->watchdog_tx_done &&
3514 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3515 /* nic seems like it might be stuck.. */
3516 if (rx_pause_cnt != mgp->watchdog_pause) {
3517 if (net_ratelimit())
3518 printk(KERN_WARNING
3519 "myri10ge %s slice %d:"
3520 "TX paused, check link partner\n",
3521 mgp->dev->name, i);
3522 } else {
3523 printk(KERN_WARNING
3524 "myri10ge %s slice %d stuck:",
3525 mgp->dev->name, i);
3526 reset_needed = 1;
3527 }
3528 }
3529 ss->watchdog_tx_done = ss->tx.done;
3530 ss->watchdog_tx_req = ss->tx.req;
3531 }
3532 mgp->watchdog_pause = rx_pause_cnt;
3533
3534 if (reset_needed) {
3535 schedule_work(&mgp->watchdog_work);
3536 } else {
3537 /* rearm timer */
3538 mod_timer(&mgp->watchdog_timer,
3539 jiffies + myri10ge_watchdog_timeout * HZ);
3540 }
3541 }
3542
3543 static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3544 {
3545 struct myri10ge_slice_state *ss;
3546 struct pci_dev *pdev = mgp->pdev;
3547 size_t bytes;
3548 int i;
3549
3550 if (mgp->ss == NULL)
3551 return;
3552
3553 for (i = 0; i < mgp->num_slices; i++) {
3554 ss = &mgp->ss[i];
3555 if (ss->rx_done.entry != NULL) {
3556 bytes = mgp->max_intr_slots *
3557 sizeof(*ss->rx_done.entry);
3558 dma_free_coherent(&pdev->dev, bytes,
3559 ss->rx_done.entry, ss->rx_done.bus);
3560 ss->rx_done.entry = NULL;
3561 }
3562 if (ss->fw_stats != NULL) {
3563 bytes = sizeof(*ss->fw_stats);
3564 dma_free_coherent(&pdev->dev, bytes,
3565 ss->fw_stats, ss->fw_stats_bus);
3566 ss->fw_stats = NULL;
3567 }
3568 }
3569 kfree(mgp->ss);
3570 mgp->ss = NULL;
3571 }
3572
3573 static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3574 {
3575 struct myri10ge_slice_state *ss;
3576 struct pci_dev *pdev = mgp->pdev;
3577 size_t bytes;
3578 int i;
3579
3580 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3581 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3582 if (mgp->ss == NULL) {
3583 return -ENOMEM;
3584 }
3585
3586 for (i = 0; i < mgp->num_slices; i++) {
3587 ss = &mgp->ss[i];
3588 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3589 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3590 &ss->rx_done.bus,
3591 GFP_KERNEL);
3592 if (ss->rx_done.entry == NULL)
3593 goto abort;
3594 memset(ss->rx_done.entry, 0, bytes);
3595 bytes = sizeof(*ss->fw_stats);
3596 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3597 &ss->fw_stats_bus,
3598 GFP_KERNEL);
3599 if (ss->fw_stats == NULL)
3600 goto abort;
3601 ss->mgp = mgp;
3602 ss->dev = mgp->dev;
3603 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3604 myri10ge_napi_weight);
3605 }
3606 return 0;
3607 abort:
3608 myri10ge_free_slices(mgp);
3609 return -ENOMEM;
3610 }
3611
3612 /*
3613 * This function determines the number of slices supported.
3614 * The number slices is the minumum of the number of CPUS,
3615 * the number of MSI-X irqs supported, the number of slices
3616 * supported by the firmware
3617 */
3618 static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3619 {
3620 struct myri10ge_cmd cmd;
3621 struct pci_dev *pdev = mgp->pdev;
3622 char *old_fw;
3623 int i, status, ncpus, msix_cap;
3624
3625 mgp->num_slices = 1;
3626 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3627 ncpus = num_online_cpus();
3628
3629 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3630 (myri10ge_max_slices == -1 && ncpus < 2))
3631 return;
3632
3633 /* try to load the slice aware rss firmware */
3634 old_fw = mgp->fw_name;
3635 if (myri10ge_fw_name != NULL) {
3636 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3637 myri10ge_fw_name);
3638 mgp->fw_name = myri10ge_fw_name;
3639 } else if (old_fw == myri10ge_fw_aligned)
3640 mgp->fw_name = myri10ge_fw_rss_aligned;
3641 else
3642 mgp->fw_name = myri10ge_fw_rss_unaligned;
3643 status = myri10ge_load_firmware(mgp, 0);
3644 if (status != 0) {
3645 dev_info(&pdev->dev, "Rss firmware not found\n");
3646 return;
3647 }
3648
3649 /* hit the board with a reset to ensure it is alive */
3650 memset(&cmd, 0, sizeof(cmd));
3651 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3652 if (status != 0) {
3653 dev_err(&mgp->pdev->dev, "failed reset\n");
3654 goto abort_with_fw;
3655 return;
3656 }
3657
3658 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3659
3660 /* tell it the size of the interrupt queues */
3661 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3662 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3663 if (status != 0) {
3664 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3665 goto abort_with_fw;
3666 }
3667
3668 /* ask the maximum number of slices it supports */
3669 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3670 if (status != 0)
3671 goto abort_with_fw;
3672 else
3673 mgp->num_slices = cmd.data0;
3674
3675 /* Only allow multiple slices if MSI-X is usable */
3676 if (!myri10ge_msi) {
3677 goto abort_with_fw;
3678 }
3679
3680 /* if the admin did not specify a limit to how many
3681 * slices we should use, cap it automatically to the
3682 * number of CPUs currently online */
3683 if (myri10ge_max_slices == -1)
3684 myri10ge_max_slices = ncpus;
3685
3686 if (mgp->num_slices > myri10ge_max_slices)
3687 mgp->num_slices = myri10ge_max_slices;
3688
3689 /* Now try to allocate as many MSI-X vectors as we have
3690 * slices. We give up on MSI-X if we can only get a single
3691 * vector. */
3692
3693 mgp->msix_vectors = kzalloc(mgp->num_slices *
3694 sizeof(*mgp->msix_vectors), GFP_KERNEL);
3695 if (mgp->msix_vectors == NULL)
3696 goto disable_msix;
3697 for (i = 0; i < mgp->num_slices; i++) {
3698 mgp->msix_vectors[i].entry = i;
3699 }
3700
3701 while (mgp->num_slices > 1) {
3702 /* make sure it is a power of two */
3703 while (!is_power_of_2(mgp->num_slices))
3704 mgp->num_slices--;
3705 if (mgp->num_slices == 1)
3706 goto disable_msix;
3707 status = pci_enable_msix(pdev, mgp->msix_vectors,
3708 mgp->num_slices);
3709 if (status == 0) {
3710 pci_disable_msix(pdev);
3711 return;
3712 }
3713 if (status > 0)
3714 mgp->num_slices = status;
3715 else
3716 goto disable_msix;
3717 }
3718
3719 disable_msix:
3720 if (mgp->msix_vectors != NULL) {
3721 kfree(mgp->msix_vectors);
3722 mgp->msix_vectors = NULL;
3723 }
3724
3725 abort_with_fw:
3726 mgp->num_slices = 1;
3727 mgp->fw_name = old_fw;
3728 myri10ge_load_firmware(mgp, 0);
3729 }
3730
3731 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3732 {
3733 struct net_device *netdev;
3734 struct myri10ge_priv *mgp;
3735 struct device *dev = &pdev->dev;
3736 int i;
3737 int status = -ENXIO;
3738 int dac_enabled;
3739
3740 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
3741 if (netdev == NULL) {
3742 dev_err(dev, "Could not allocate ethernet device\n");
3743 return -ENOMEM;
3744 }
3745
3746 SET_NETDEV_DEV(netdev, &pdev->dev);
3747
3748 mgp = netdev_priv(netdev);
3749 mgp->dev = netdev;
3750 mgp->pdev = pdev;
3751 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3752 mgp->pause = myri10ge_flow_control;
3753 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3754 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3755 init_waitqueue_head(&mgp->down_wq);
3756
3757 if (pci_enable_device(pdev)) {
3758 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3759 status = -ENODEV;
3760 goto abort_with_netdev;
3761 }
3762
3763 /* Find the vendor-specific cap so we can check
3764 * the reboot register later on */
3765 mgp->vendor_specific_offset
3766 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3767
3768 /* Set our max read request to 4KB */
3769 status = pcie_set_readrq(pdev, 4096);
3770 if (status != 0) {
3771 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3772 status);
3773 goto abort_with_netdev;
3774 }
3775
3776 pci_set_master(pdev);
3777 dac_enabled = 1;
3778 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3779 if (status != 0) {
3780 dac_enabled = 0;
3781 dev_err(&pdev->dev,
3782 "64-bit pci address mask was refused, "
3783 "trying 32-bit\n");
3784 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3785 }
3786 if (status != 0) {
3787 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3788 goto abort_with_netdev;
3789 }
3790 (void)pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3791 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3792 &mgp->cmd_bus, GFP_KERNEL);
3793 if (mgp->cmd == NULL)
3794 goto abort_with_netdev;
3795
3796 mgp->board_span = pci_resource_len(pdev, 0);
3797 mgp->iomem_base = pci_resource_start(pdev, 0);
3798 mgp->mtrr = -1;
3799 mgp->wc_enabled = 0;
3800 #ifdef CONFIG_MTRR
3801 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3802 MTRR_TYPE_WRCOMB, 1);
3803 if (mgp->mtrr >= 0)
3804 mgp->wc_enabled = 1;
3805 #endif
3806 /* Hack. need to get rid of these magic numbers */
3807 mgp->sram_size =
3808 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3809 if (mgp->sram_size > mgp->board_span) {
3810 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3811 mgp->board_span);
3812 goto abort_with_mtrr;
3813 }
3814 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
3815 if (mgp->sram == NULL) {
3816 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3817 mgp->board_span, mgp->iomem_base);
3818 status = -ENXIO;
3819 goto abort_with_mtrr;
3820 }
3821 memcpy_fromio(mgp->eeprom_strings,
3822 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3823 MYRI10GE_EEPROM_STRINGS_SIZE);
3824 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3825 status = myri10ge_read_mac_addr(mgp);
3826 if (status)
3827 goto abort_with_ioremap;
3828
3829 for (i = 0; i < ETH_ALEN; i++)
3830 netdev->dev_addr[i] = mgp->mac_addr[i];
3831
3832 myri10ge_select_firmware(mgp);
3833
3834 status = myri10ge_load_firmware(mgp, 1);
3835 if (status != 0) {
3836 dev_err(&pdev->dev, "failed to load firmware\n");
3837 goto abort_with_ioremap;
3838 }
3839 myri10ge_probe_slices(mgp);
3840 status = myri10ge_alloc_slices(mgp);
3841 if (status != 0) {
3842 dev_err(&pdev->dev, "failed to alloc slice state\n");
3843 goto abort_with_firmware;
3844 }
3845 netdev->real_num_tx_queues = mgp->num_slices;
3846 status = myri10ge_reset(mgp);
3847 if (status != 0) {
3848 dev_err(&pdev->dev, "failed reset\n");
3849 goto abort_with_slices;
3850 }
3851 #ifdef CONFIG_MYRI10GE_DCA
3852 myri10ge_setup_dca(mgp);
3853 #endif
3854 pci_set_drvdata(pdev, mgp);
3855 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3856 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3857 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3858 myri10ge_initial_mtu = 68;
3859 netdev->mtu = myri10ge_initial_mtu;
3860 netdev->open = myri10ge_open;
3861 netdev->stop = myri10ge_close;
3862 netdev->hard_start_xmit = myri10ge_xmit;
3863 netdev->get_stats = myri10ge_get_stats;
3864 netdev->base_addr = mgp->iomem_base;
3865 netdev->change_mtu = myri10ge_change_mtu;
3866 netdev->set_multicast_list = myri10ge_set_multicast_list;
3867 netdev->set_mac_address = myri10ge_set_mac_address;
3868 netdev->features = mgp->features;
3869
3870 if (dac_enabled)
3871 netdev->features |= NETIF_F_HIGHDMA;
3872
3873 /* make sure we can get an irq, and that MSI can be
3874 * setup (if available). Also ensure netdev->irq
3875 * is set to correct value if MSI is enabled */
3876 status = myri10ge_request_irq(mgp);
3877 if (status != 0)
3878 goto abort_with_firmware;
3879 netdev->irq = pdev->irq;
3880 myri10ge_free_irq(mgp);
3881
3882 /* Save configuration space to be restored if the
3883 * nic resets due to a parity error */
3884 pci_save_state(pdev);
3885
3886 /* Setup the watchdog timer */
3887 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3888 (unsigned long)mgp);
3889
3890 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3891 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3892 status = register_netdev(netdev);
3893 if (status != 0) {
3894 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3895 goto abort_with_state;
3896 }
3897 if (mgp->msix_enabled)
3898 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3899 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3900 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3901 else
3902 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3903 mgp->msi_enabled ? "MSI" : "xPIC",
3904 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3905 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3906
3907 return 0;
3908
3909 abort_with_state:
3910 pci_restore_state(pdev);
3911
3912 abort_with_slices:
3913 myri10ge_free_slices(mgp);
3914
3915 abort_with_firmware:
3916 myri10ge_dummy_rdma(mgp, 0);
3917
3918 abort_with_ioremap:
3919 iounmap(mgp->sram);
3920
3921 abort_with_mtrr:
3922 #ifdef CONFIG_MTRR
3923 if (mgp->mtrr >= 0)
3924 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3925 #endif
3926 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3927 mgp->cmd, mgp->cmd_bus);
3928
3929 abort_with_netdev:
3930
3931 free_netdev(netdev);
3932 return status;
3933 }
3934
3935 /*
3936 * myri10ge_remove
3937 *
3938 * Does what is necessary to shutdown one Myrinet device. Called
3939 * once for each Myrinet card by the kernel when a module is
3940 * unloaded.
3941 */
3942 static void myri10ge_remove(struct pci_dev *pdev)
3943 {
3944 struct myri10ge_priv *mgp;
3945 struct net_device *netdev;
3946
3947 mgp = pci_get_drvdata(pdev);
3948 if (mgp == NULL)
3949 return;
3950
3951 flush_scheduled_work();
3952 netdev = mgp->dev;
3953 unregister_netdev(netdev);
3954
3955 #ifdef CONFIG_MYRI10GE_DCA
3956 myri10ge_teardown_dca(mgp);
3957 #endif
3958 myri10ge_dummy_rdma(mgp, 0);
3959
3960 /* avoid a memory leak */
3961 pci_restore_state(pdev);
3962
3963 iounmap(mgp->sram);
3964
3965 #ifdef CONFIG_MTRR
3966 if (mgp->mtrr >= 0)
3967 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3968 #endif
3969 myri10ge_free_slices(mgp);
3970 if (mgp->msix_vectors != NULL)
3971 kfree(mgp->msix_vectors);
3972 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3973 mgp->cmd, mgp->cmd_bus);
3974
3975 free_netdev(netdev);
3976 pci_set_drvdata(pdev, NULL);
3977 }
3978
3979 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
3980 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
3981
3982 static struct pci_device_id myri10ge_pci_tbl[] = {
3983 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
3984 {PCI_DEVICE
3985 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
3986 {0},
3987 };
3988
3989 static struct pci_driver myri10ge_driver = {
3990 .name = "myri10ge",
3991 .probe = myri10ge_probe,
3992 .remove = myri10ge_remove,
3993 .id_table = myri10ge_pci_tbl,
3994 #ifdef CONFIG_PM
3995 .suspend = myri10ge_suspend,
3996 .resume = myri10ge_resume,
3997 #endif
3998 };
3999
4000 #ifdef CONFIG_MYRI10GE_DCA
4001 static int
4002 myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4003 {
4004 int err = driver_for_each_device(&myri10ge_driver.driver,
4005 NULL, &event,
4006 myri10ge_notify_dca_device);
4007
4008 if (err)
4009 return NOTIFY_BAD;
4010 return NOTIFY_DONE;
4011 }
4012
4013 static struct notifier_block myri10ge_dca_notifier = {
4014 .notifier_call = myri10ge_notify_dca,
4015 .next = NULL,
4016 .priority = 0,
4017 };
4018 #endif /* CONFIG_DCA */
4019
4020 static __init int myri10ge_init_module(void)
4021 {
4022 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
4023 MYRI10GE_VERSION_STR);
4024
4025 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
4026 printk(KERN_ERR
4027 "%s: Illegal rssh hash type %d, defaulting to source port\n",
4028 myri10ge_driver.name, myri10ge_rss_hash);
4029 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4030 }
4031 #ifdef CONFIG_MYRI10GE_DCA
4032 dca_register_notify(&myri10ge_dca_notifier);
4033 #endif
4034 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4035 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
4036
4037 return pci_register_driver(&myri10ge_driver);
4038 }
4039
4040 module_init(myri10ge_init_module);
4041
4042 static __exit void myri10ge_cleanup_module(void)
4043 {
4044 #ifdef CONFIG_MYRI10GE_DCA
4045 dca_unregister_notify(&myri10ge_dca_notifier);
4046 #endif
4047 pci_unregister_driver(&myri10ge_driver);
4048 }
4049
4050 module_exit(myri10ge_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)