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Merge branch 'for-2.6.27' of git://git.infradead.org/users/dwmw2/firmware-2.6
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / myri10ge / myri10ge.c
1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005 - 2007 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/inet_lro.h>
52 #include <linux/ip.h>
53 #include <linux/inet.h>
54 #include <linux/in.h>
55 #include <linux/ethtool.h>
56 #include <linux/firmware.h>
57 #include <linux/delay.h>
58 #include <linux/version.h>
59 #include <linux/timer.h>
60 #include <linux/vmalloc.h>
61 #include <linux/crc32.h>
62 #include <linux/moduleparam.h>
63 #include <linux/io.h>
64 #include <linux/log2.h>
65 #include <net/checksum.h>
66 #include <net/ip.h>
67 #include <net/tcp.h>
68 #include <asm/byteorder.h>
69 #include <asm/io.h>
70 #include <asm/processor.h>
71 #ifdef CONFIG_MTRR
72 #include <asm/mtrr.h>
73 #endif
74
75 #include "myri10ge_mcp.h"
76 #include "myri10ge_mcp_gen_header.h"
77
78 #define MYRI10GE_VERSION_STR "1.3.99-1.347"
79
80 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81 MODULE_AUTHOR("Maintainer: help@myri.com");
82 MODULE_VERSION(MYRI10GE_VERSION_STR);
83 MODULE_LICENSE("Dual BSD/GPL");
84
85 #define MYRI10GE_MAX_ETHER_MTU 9014
86
87 #define MYRI10GE_ETH_STOPPED 0
88 #define MYRI10GE_ETH_STOPPING 1
89 #define MYRI10GE_ETH_STARTING 2
90 #define MYRI10GE_ETH_RUNNING 3
91 #define MYRI10GE_ETH_OPEN_FAILED 4
92
93 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
94 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
95 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96 #define MYRI10GE_LRO_MAX_PKTS 64
97
98 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
99 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
101 #define MYRI10GE_ALLOC_ORDER 0
102 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
105 struct myri10ge_rx_buffer_state {
106 struct page *page;
107 int page_offset;
108 DECLARE_PCI_UNMAP_ADDR(bus)
109 DECLARE_PCI_UNMAP_LEN(len)
110 };
111
112 struct myri10ge_tx_buffer_state {
113 struct sk_buff *skb;
114 int last;
115 DECLARE_PCI_UNMAP_ADDR(bus)
116 DECLARE_PCI_UNMAP_LEN(len)
117 };
118
119 struct myri10ge_cmd {
120 u32 data0;
121 u32 data1;
122 u32 data2;
123 };
124
125 struct myri10ge_rx_buf {
126 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
127 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
128 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
129 struct myri10ge_rx_buffer_state *info;
130 struct page *page;
131 dma_addr_t bus;
132 int page_offset;
133 int cnt;
134 int fill_cnt;
135 int alloc_fail;
136 int mask; /* number of rx slots -1 */
137 int watchdog_needed;
138 };
139
140 struct myri10ge_tx_buf {
141 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
142 u8 __iomem *wc_fifo; /* w/c send fifo address */
143 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
144 char *req_bytes;
145 struct myri10ge_tx_buffer_state *info;
146 int mask; /* number of transmit slots -1 */
147 int req ____cacheline_aligned; /* transmit slots submitted */
148 int pkt_start; /* packets started */
149 int stop_queue;
150 int linearized;
151 int done ____cacheline_aligned; /* transmit slots completed */
152 int pkt_done; /* packets completed */
153 int wake_queue;
154 };
155
156 struct myri10ge_rx_done {
157 struct mcp_slot *entry;
158 dma_addr_t bus;
159 int cnt;
160 int idx;
161 struct net_lro_mgr lro_mgr;
162 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
163 };
164
165 struct myri10ge_slice_netstats {
166 unsigned long rx_packets;
167 unsigned long tx_packets;
168 unsigned long rx_bytes;
169 unsigned long tx_bytes;
170 unsigned long rx_dropped;
171 unsigned long tx_dropped;
172 };
173
174 struct myri10ge_slice_state {
175 struct myri10ge_tx_buf tx; /* transmit ring */
176 struct myri10ge_rx_buf rx_small;
177 struct myri10ge_rx_buf rx_big;
178 struct myri10ge_rx_done rx_done;
179 struct net_device *dev;
180 struct napi_struct napi;
181 struct myri10ge_priv *mgp;
182 struct myri10ge_slice_netstats stats;
183 __be32 __iomem *irq_claim;
184 struct mcp_irq_data *fw_stats;
185 dma_addr_t fw_stats_bus;
186 int watchdog_tx_done;
187 int watchdog_tx_req;
188 };
189
190 struct myri10ge_priv {
191 struct myri10ge_slice_state ss;
192 int tx_boundary; /* boundary transmits cannot cross */
193 int running; /* running? */
194 int csum_flag; /* rx_csums? */
195 int small_bytes;
196 int big_bytes;
197 int max_intr_slots;
198 struct net_device *dev;
199 struct net_device_stats stats;
200 spinlock_t stats_lock;
201 u8 __iomem *sram;
202 int sram_size;
203 unsigned long board_span;
204 unsigned long iomem_base;
205 __be32 __iomem *irq_deassert;
206 char *mac_addr_string;
207 struct mcp_cmd_response *cmd;
208 dma_addr_t cmd_bus;
209 struct pci_dev *pdev;
210 int msi_enabled;
211 u32 link_state;
212 unsigned int rdma_tags_available;
213 int intr_coal_delay;
214 __be32 __iomem *intr_coal_delay_ptr;
215 int mtrr;
216 int wc_enabled;
217 int down_cnt;
218 wait_queue_head_t down_wq;
219 struct work_struct watchdog_work;
220 struct timer_list watchdog_timer;
221 int watchdog_resets;
222 int watchdog_pause;
223 int pause;
224 char *fw_name;
225 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
226 char *product_code_string;
227 char fw_version[128];
228 int fw_ver_major;
229 int fw_ver_minor;
230 int fw_ver_tiny;
231 int adopted_rx_filter_bug;
232 u8 mac_addr[6]; /* eeprom mac address */
233 unsigned long serial_number;
234 int vendor_specific_offset;
235 int fw_multicast_support;
236 unsigned long features;
237 u32 max_tso6;
238 u32 read_dma;
239 u32 write_dma;
240 u32 read_write_dma;
241 u32 link_changes;
242 u32 msg_enable;
243 };
244
245 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
246 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
247
248 static char *myri10ge_fw_name = NULL;
249 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
250 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
251
252 static int myri10ge_ecrc_enable = 1;
253 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
254 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
255
256 static int myri10ge_small_bytes = -1; /* -1 == auto */
257 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
258 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
259
260 static int myri10ge_msi = 1; /* enable msi by default */
261 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
262 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
263
264 static int myri10ge_intr_coal_delay = 75;
265 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
266 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
267
268 static int myri10ge_flow_control = 1;
269 module_param(myri10ge_flow_control, int, S_IRUGO);
270 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
271
272 static int myri10ge_deassert_wait = 1;
273 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
274 MODULE_PARM_DESC(myri10ge_deassert_wait,
275 "Wait when deasserting legacy interrupts");
276
277 static int myri10ge_force_firmware = 0;
278 module_param(myri10ge_force_firmware, int, S_IRUGO);
279 MODULE_PARM_DESC(myri10ge_force_firmware,
280 "Force firmware to assume aligned completions");
281
282 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
283 module_param(myri10ge_initial_mtu, int, S_IRUGO);
284 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
285
286 static int myri10ge_napi_weight = 64;
287 module_param(myri10ge_napi_weight, int, S_IRUGO);
288 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
289
290 static int myri10ge_watchdog_timeout = 1;
291 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
292 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
293
294 static int myri10ge_max_irq_loops = 1048576;
295 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
296 MODULE_PARM_DESC(myri10ge_max_irq_loops,
297 "Set stuck legacy IRQ detection threshold");
298
299 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
300
301 static int myri10ge_debug = -1; /* defaults above */
302 module_param(myri10ge_debug, int, 0);
303 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
304
305 static int myri10ge_lro = 1;
306 module_param(myri10ge_lro, int, S_IRUGO);
307 MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
308
309 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
310 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
311 MODULE_PARM_DESC(myri10ge_lro_max_pkts,
312 "Number of LRO packets to be aggregated");
313
314 static int myri10ge_fill_thresh = 256;
315 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
316 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
317
318 static int myri10ge_reset_recover = 1;
319
320 static int myri10ge_wcfifo = 0;
321 module_param(myri10ge_wcfifo, int, S_IRUGO);
322 MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled");
323
324 #define MYRI10GE_FW_OFFSET 1024*1024
325 #define MYRI10GE_HIGHPART_TO_U32(X) \
326 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
327 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
328
329 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
330
331 static void myri10ge_set_multicast_list(struct net_device *dev);
332 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
333
334 static inline void put_be32(__be32 val, __be32 __iomem * p)
335 {
336 __raw_writel((__force __u32) val, (__force void __iomem *)p);
337 }
338
339 static int
340 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
341 struct myri10ge_cmd *data, int atomic)
342 {
343 struct mcp_cmd *buf;
344 char buf_bytes[sizeof(*buf) + 8];
345 struct mcp_cmd_response *response = mgp->cmd;
346 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
347 u32 dma_low, dma_high, result, value;
348 int sleep_total = 0;
349
350 /* ensure buf is aligned to 8 bytes */
351 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
352
353 buf->data0 = htonl(data->data0);
354 buf->data1 = htonl(data->data1);
355 buf->data2 = htonl(data->data2);
356 buf->cmd = htonl(cmd);
357 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
358 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
359
360 buf->response_addr.low = htonl(dma_low);
361 buf->response_addr.high = htonl(dma_high);
362 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
363 mb();
364 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
365
366 /* wait up to 15ms. Longest command is the DMA benchmark,
367 * which is capped at 5ms, but runs from a timeout handler
368 * that runs every 7.8ms. So a 15ms timeout leaves us with
369 * a 2.2ms margin
370 */
371 if (atomic) {
372 /* if atomic is set, do not sleep,
373 * and try to get the completion quickly
374 * (1ms will be enough for those commands) */
375 for (sleep_total = 0;
376 sleep_total < 1000
377 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
378 sleep_total += 10) {
379 udelay(10);
380 mb();
381 }
382 } else {
383 /* use msleep for most command */
384 for (sleep_total = 0;
385 sleep_total < 15
386 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
387 sleep_total++)
388 msleep(1);
389 }
390
391 result = ntohl(response->result);
392 value = ntohl(response->data);
393 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
394 if (result == 0) {
395 data->data0 = value;
396 return 0;
397 } else if (result == MXGEFW_CMD_UNKNOWN) {
398 return -ENOSYS;
399 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
400 return -E2BIG;
401 } else {
402 dev_err(&mgp->pdev->dev,
403 "command %d failed, result = %d\n",
404 cmd, result);
405 return -ENXIO;
406 }
407 }
408
409 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
410 cmd, result);
411 return -EAGAIN;
412 }
413
414 /*
415 * The eeprom strings on the lanaiX have the format
416 * SN=x\0
417 * MAC=x:x:x:x:x:x\0
418 * PT:ddd mmm xx xx:xx:xx xx\0
419 * PV:ddd mmm xx xx:xx:xx xx\0
420 */
421 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
422 {
423 char *ptr, *limit;
424 int i;
425
426 ptr = mgp->eeprom_strings;
427 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
428
429 while (*ptr != '\0' && ptr < limit) {
430 if (memcmp(ptr, "MAC=", 4) == 0) {
431 ptr += 4;
432 mgp->mac_addr_string = ptr;
433 for (i = 0; i < 6; i++) {
434 if ((ptr + 2) > limit)
435 goto abort;
436 mgp->mac_addr[i] =
437 simple_strtoul(ptr, &ptr, 16);
438 ptr += 1;
439 }
440 }
441 if (memcmp(ptr, "PC=", 3) == 0) {
442 ptr += 3;
443 mgp->product_code_string = ptr;
444 }
445 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
446 ptr += 3;
447 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
448 }
449 while (ptr < limit && *ptr++) ;
450 }
451
452 return 0;
453
454 abort:
455 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
456 return -ENXIO;
457 }
458
459 /*
460 * Enable or disable periodic RDMAs from the host to make certain
461 * chipsets resend dropped PCIe messages
462 */
463
464 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
465 {
466 char __iomem *submit;
467 __be32 buf[16] __attribute__ ((__aligned__(8)));
468 u32 dma_low, dma_high;
469 int i;
470
471 /* clear confirmation addr */
472 mgp->cmd->data = 0;
473 mb();
474
475 /* send a rdma command to the PCIe engine, and wait for the
476 * response in the confirmation address. The firmware should
477 * write a -1 there to indicate it is alive and well
478 */
479 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
480 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
481
482 buf[0] = htonl(dma_high); /* confirm addr MSW */
483 buf[1] = htonl(dma_low); /* confirm addr LSW */
484 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
485 buf[3] = htonl(dma_high); /* dummy addr MSW */
486 buf[4] = htonl(dma_low); /* dummy addr LSW */
487 buf[5] = htonl(enable); /* enable? */
488
489 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
490
491 myri10ge_pio_copy(submit, &buf, sizeof(buf));
492 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
493 msleep(1);
494 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
495 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
496 (enable ? "enable" : "disable"));
497 }
498
499 static int
500 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
501 struct mcp_gen_header *hdr)
502 {
503 struct device *dev = &mgp->pdev->dev;
504
505 /* check firmware type */
506 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
507 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
508 return -EINVAL;
509 }
510
511 /* save firmware version for ethtool */
512 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
513
514 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
515 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
516
517 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
518 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
519 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
520 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
521 MXGEFW_VERSION_MINOR);
522 return -EINVAL;
523 }
524 return 0;
525 }
526
527 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
528 {
529 unsigned crc, reread_crc;
530 const struct firmware *fw;
531 struct device *dev = &mgp->pdev->dev;
532 unsigned char *fw_readback;
533 struct mcp_gen_header *hdr;
534 size_t hdr_offset;
535 int status;
536 unsigned i;
537
538 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
539 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
540 mgp->fw_name);
541 status = -EINVAL;
542 goto abort_with_nothing;
543 }
544
545 /* check size */
546
547 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
548 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
549 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
550 status = -EINVAL;
551 goto abort_with_fw;
552 }
553
554 /* check id */
555 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
556 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
557 dev_err(dev, "Bad firmware file\n");
558 status = -EINVAL;
559 goto abort_with_fw;
560 }
561 hdr = (void *)(fw->data + hdr_offset);
562
563 status = myri10ge_validate_firmware(mgp, hdr);
564 if (status != 0)
565 goto abort_with_fw;
566
567 crc = crc32(~0, fw->data, fw->size);
568 for (i = 0; i < fw->size; i += 256) {
569 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
570 fw->data + i,
571 min(256U, (unsigned)(fw->size - i)));
572 mb();
573 readb(mgp->sram);
574 }
575 fw_readback = vmalloc(fw->size);
576 if (!fw_readback) {
577 status = -ENOMEM;
578 goto abort_with_fw;
579 }
580 /* corruption checking is good for parity recovery and buggy chipset */
581 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
582 reread_crc = crc32(~0, fw_readback, fw->size);
583 vfree(fw_readback);
584 if (crc != reread_crc) {
585 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
586 (unsigned)fw->size, reread_crc, crc);
587 status = -EIO;
588 goto abort_with_fw;
589 }
590 *size = (u32) fw->size;
591
592 abort_with_fw:
593 release_firmware(fw);
594
595 abort_with_nothing:
596 return status;
597 }
598
599 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
600 {
601 struct mcp_gen_header *hdr;
602 struct device *dev = &mgp->pdev->dev;
603 const size_t bytes = sizeof(struct mcp_gen_header);
604 size_t hdr_offset;
605 int status;
606
607 /* find running firmware header */
608 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
609
610 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
611 dev_err(dev, "Running firmware has bad header offset (%d)\n",
612 (int)hdr_offset);
613 return -EIO;
614 }
615
616 /* copy header of running firmware from SRAM to host memory to
617 * validate firmware */
618 hdr = kmalloc(bytes, GFP_KERNEL);
619 if (hdr == NULL) {
620 dev_err(dev, "could not malloc firmware hdr\n");
621 return -ENOMEM;
622 }
623 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
624 status = myri10ge_validate_firmware(mgp, hdr);
625 kfree(hdr);
626
627 /* check to see if adopted firmware has bug where adopting
628 * it will cause broadcasts to be filtered unless the NIC
629 * is kept in ALLMULTI mode */
630 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
631 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
632 mgp->adopted_rx_filter_bug = 1;
633 dev_warn(dev, "Adopting fw %d.%d.%d: "
634 "working around rx filter bug\n",
635 mgp->fw_ver_major, mgp->fw_ver_minor,
636 mgp->fw_ver_tiny);
637 }
638 return status;
639 }
640
641 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
642 {
643 struct myri10ge_cmd cmd;
644 int status;
645
646 /* probe for IPv6 TSO support */
647 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
648 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
649 &cmd, 0);
650 if (status == 0) {
651 mgp->max_tso6 = cmd.data0;
652 mgp->features |= NETIF_F_TSO6;
653 }
654
655 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
656 if (status != 0) {
657 dev_err(&mgp->pdev->dev,
658 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
659 return -ENXIO;
660 }
661
662 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
663
664 return 0;
665 }
666
667 static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
668 {
669 char __iomem *submit;
670 __be32 buf[16] __attribute__ ((__aligned__(8)));
671 u32 dma_low, dma_high, size;
672 int status, i;
673
674 size = 0;
675 status = myri10ge_load_hotplug_firmware(mgp, &size);
676 if (status) {
677 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
678
679 /* Do not attempt to adopt firmware if there
680 * was a bad crc */
681 if (status == -EIO)
682 return status;
683
684 status = myri10ge_adopt_running_firmware(mgp);
685 if (status != 0) {
686 dev_err(&mgp->pdev->dev,
687 "failed to adopt running firmware\n");
688 return status;
689 }
690 dev_info(&mgp->pdev->dev,
691 "Successfully adopted running firmware\n");
692 if (mgp->tx_boundary == 4096) {
693 dev_warn(&mgp->pdev->dev,
694 "Using firmware currently running on NIC"
695 ". For optimal\n");
696 dev_warn(&mgp->pdev->dev,
697 "performance consider loading optimized "
698 "firmware\n");
699 dev_warn(&mgp->pdev->dev, "via hotplug\n");
700 }
701
702 mgp->fw_name = "adopted";
703 mgp->tx_boundary = 2048;
704 myri10ge_dummy_rdma(mgp, 1);
705 status = myri10ge_get_firmware_capabilities(mgp);
706 return status;
707 }
708
709 /* clear confirmation addr */
710 mgp->cmd->data = 0;
711 mb();
712
713 /* send a reload command to the bootstrap MCP, and wait for the
714 * response in the confirmation address. The firmware should
715 * write a -1 there to indicate it is alive and well
716 */
717 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
718 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
719
720 buf[0] = htonl(dma_high); /* confirm addr MSW */
721 buf[1] = htonl(dma_low); /* confirm addr LSW */
722 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
723
724 /* FIX: All newest firmware should un-protect the bottom of
725 * the sram before handoff. However, the very first interfaces
726 * do not. Therefore the handoff copy must skip the first 8 bytes
727 */
728 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
729 buf[4] = htonl(size - 8); /* length of code */
730 buf[5] = htonl(8); /* where to copy to */
731 buf[6] = htonl(0); /* where to jump to */
732
733 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
734
735 myri10ge_pio_copy(submit, &buf, sizeof(buf));
736 mb();
737 msleep(1);
738 mb();
739 i = 0;
740 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
741 msleep(1 << i);
742 i++;
743 }
744 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
745 dev_err(&mgp->pdev->dev, "handoff failed\n");
746 return -ENXIO;
747 }
748 myri10ge_dummy_rdma(mgp, 1);
749 status = myri10ge_get_firmware_capabilities(mgp);
750
751 return status;
752 }
753
754 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
755 {
756 struct myri10ge_cmd cmd;
757 int status;
758
759 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
760 | (addr[2] << 8) | addr[3]);
761
762 cmd.data1 = ((addr[4] << 8) | (addr[5]));
763
764 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
765 return status;
766 }
767
768 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
769 {
770 struct myri10ge_cmd cmd;
771 int status, ctl;
772
773 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
774 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
775
776 if (status) {
777 printk(KERN_ERR
778 "myri10ge: %s: Failed to set flow control mode\n",
779 mgp->dev->name);
780 return status;
781 }
782 mgp->pause = pause;
783 return 0;
784 }
785
786 static void
787 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
788 {
789 struct myri10ge_cmd cmd;
790 int status, ctl;
791
792 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
793 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
794 if (status)
795 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
796 mgp->dev->name);
797 }
798
799 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
800 {
801 struct myri10ge_cmd cmd;
802 int status;
803 u32 len;
804 struct page *dmatest_page;
805 dma_addr_t dmatest_bus;
806 char *test = " ";
807
808 dmatest_page = alloc_page(GFP_KERNEL);
809 if (!dmatest_page)
810 return -ENOMEM;
811 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
812 DMA_BIDIRECTIONAL);
813
814 /* Run a small DMA test.
815 * The magic multipliers to the length tell the firmware
816 * to do DMA read, write, or read+write tests. The
817 * results are returned in cmd.data0. The upper 16
818 * bits or the return is the number of transfers completed.
819 * The lower 16 bits is the time in 0.5us ticks that the
820 * transfers took to complete.
821 */
822
823 len = mgp->tx_boundary;
824
825 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
826 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
827 cmd.data2 = len * 0x10000;
828 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
829 if (status != 0) {
830 test = "read";
831 goto abort;
832 }
833 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
834 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
835 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
836 cmd.data2 = len * 0x1;
837 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
838 if (status != 0) {
839 test = "write";
840 goto abort;
841 }
842 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
843
844 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
845 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
846 cmd.data2 = len * 0x10001;
847 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
848 if (status != 0) {
849 test = "read/write";
850 goto abort;
851 }
852 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
853 (cmd.data0 & 0xffff);
854
855 abort:
856 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
857 put_page(dmatest_page);
858
859 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
860 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
861 test, status);
862
863 return status;
864 }
865
866 static int myri10ge_reset(struct myri10ge_priv *mgp)
867 {
868 struct myri10ge_cmd cmd;
869 int status;
870 size_t bytes;
871
872 /* try to send a reset command to the card to see if it
873 * is alive */
874 memset(&cmd, 0, sizeof(cmd));
875 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
876 if (status != 0) {
877 dev_err(&mgp->pdev->dev, "failed reset\n");
878 return -ENXIO;
879 }
880
881 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
882
883 /* Now exchange information about interrupts */
884
885 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
886 memset(mgp->ss.rx_done.entry, 0, bytes);
887 cmd.data0 = (u32) bytes;
888 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
889 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->ss.rx_done.bus);
890 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->ss.rx_done.bus);
891 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
892
893 status |=
894 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
895 mgp->ss.irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
896 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
897 &cmd, 0);
898 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
899
900 status |= myri10ge_send_cmd
901 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
902 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
903 if (status != 0) {
904 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
905 return status;
906 }
907 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
908
909 memset(mgp->ss.rx_done.entry, 0, bytes);
910
911 /* reset mcp/driver shared state back to 0 */
912 mgp->ss.tx.req = 0;
913 mgp->ss.tx.done = 0;
914 mgp->ss.tx.pkt_start = 0;
915 mgp->ss.tx.pkt_done = 0;
916 mgp->ss.rx_big.cnt = 0;
917 mgp->ss.rx_small.cnt = 0;
918 mgp->ss.rx_done.idx = 0;
919 mgp->ss.rx_done.cnt = 0;
920 mgp->link_changes = 0;
921 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
922 myri10ge_change_pause(mgp, mgp->pause);
923 myri10ge_set_multicast_list(mgp->dev);
924 return status;
925 }
926
927 static inline void
928 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
929 struct mcp_kreq_ether_recv *src)
930 {
931 __be32 low;
932
933 low = src->addr_low;
934 src->addr_low = htonl(DMA_32BIT_MASK);
935 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
936 mb();
937 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
938 mb();
939 src->addr_low = low;
940 put_be32(low, &dst->addr_low);
941 mb();
942 }
943
944 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
945 {
946 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
947
948 if ((skb->protocol == htons(ETH_P_8021Q)) &&
949 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
950 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
951 skb->csum = hw_csum;
952 skb->ip_summed = CHECKSUM_COMPLETE;
953 }
954 }
955
956 static inline void
957 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
958 struct skb_frag_struct *rx_frags, int len, int hlen)
959 {
960 struct skb_frag_struct *skb_frags;
961
962 skb->len = skb->data_len = len;
963 skb->truesize = len + sizeof(struct sk_buff);
964 /* attach the page(s) */
965
966 skb_frags = skb_shinfo(skb)->frags;
967 while (len > 0) {
968 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
969 len -= rx_frags->size;
970 skb_frags++;
971 rx_frags++;
972 skb_shinfo(skb)->nr_frags++;
973 }
974
975 /* pskb_may_pull is not available in irq context, but
976 * skb_pull() (for ether_pad and eth_type_trans()) requires
977 * the beginning of the packet in skb_headlen(), move it
978 * manually */
979 skb_copy_to_linear_data(skb, va, hlen);
980 skb_shinfo(skb)->frags[0].page_offset += hlen;
981 skb_shinfo(skb)->frags[0].size -= hlen;
982 skb->data_len -= hlen;
983 skb->tail += hlen;
984 skb_pull(skb, MXGEFW_PAD);
985 }
986
987 static void
988 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
989 int bytes, int watchdog)
990 {
991 struct page *page;
992 int idx;
993
994 if (unlikely(rx->watchdog_needed && !watchdog))
995 return;
996
997 /* try to refill entire ring */
998 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
999 idx = rx->fill_cnt & rx->mask;
1000 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
1001 /* we can use part of previous page */
1002 get_page(rx->page);
1003 } else {
1004 /* we need a new page */
1005 page =
1006 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1007 MYRI10GE_ALLOC_ORDER);
1008 if (unlikely(page == NULL)) {
1009 if (rx->fill_cnt - rx->cnt < 16)
1010 rx->watchdog_needed = 1;
1011 return;
1012 }
1013 rx->page = page;
1014 rx->page_offset = 0;
1015 rx->bus = pci_map_page(mgp->pdev, page, 0,
1016 MYRI10GE_ALLOC_SIZE,
1017 PCI_DMA_FROMDEVICE);
1018 }
1019 rx->info[idx].page = rx->page;
1020 rx->info[idx].page_offset = rx->page_offset;
1021 /* note that this is the address of the start of the
1022 * page */
1023 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1024 rx->shadow[idx].addr_low =
1025 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1026 rx->shadow[idx].addr_high =
1027 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1028
1029 /* start next packet on a cacheline boundary */
1030 rx->page_offset += SKB_DATA_ALIGN(bytes);
1031
1032 #if MYRI10GE_ALLOC_SIZE > 4096
1033 /* don't cross a 4KB boundary */
1034 if ((rx->page_offset >> 12) !=
1035 ((rx->page_offset + bytes - 1) >> 12))
1036 rx->page_offset = (rx->page_offset + 4096) & ~4095;
1037 #endif
1038 rx->fill_cnt++;
1039
1040 /* copy 8 descriptors to the firmware at a time */
1041 if ((idx & 7) == 7) {
1042 if (rx->wc_fifo == NULL)
1043 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1044 &rx->shadow[idx - 7]);
1045 else {
1046 mb();
1047 myri10ge_pio_copy(rx->wc_fifo,
1048 &rx->shadow[idx - 7], 64);
1049 }
1050 }
1051 }
1052 }
1053
1054 static inline void
1055 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1056 struct myri10ge_rx_buffer_state *info, int bytes)
1057 {
1058 /* unmap the recvd page if we're the only or last user of it */
1059 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1060 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1061 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1062 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1063 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1064 }
1065 }
1066
1067 #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1068 * page into an skb */
1069
1070 static inline int
1071 myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
1072 int bytes, int len, __wsum csum)
1073 {
1074 struct myri10ge_priv *mgp = ss->mgp;
1075 struct sk_buff *skb;
1076 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1077 int i, idx, hlen, remainder;
1078 struct pci_dev *pdev = mgp->pdev;
1079 struct net_device *dev = mgp->dev;
1080 u8 *va;
1081
1082 len += MXGEFW_PAD;
1083 idx = rx->cnt & rx->mask;
1084 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1085 prefetch(va);
1086 /* Fill skb_frag_struct(s) with data from our receive */
1087 for (i = 0, remainder = len; remainder > 0; i++) {
1088 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1089 rx_frags[i].page = rx->info[idx].page;
1090 rx_frags[i].page_offset = rx->info[idx].page_offset;
1091 if (remainder < MYRI10GE_ALLOC_SIZE)
1092 rx_frags[i].size = remainder;
1093 else
1094 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1095 rx->cnt++;
1096 idx = rx->cnt & rx->mask;
1097 remainder -= MYRI10GE_ALLOC_SIZE;
1098 }
1099
1100 if (mgp->csum_flag && myri10ge_lro) {
1101 rx_frags[0].page_offset += MXGEFW_PAD;
1102 rx_frags[0].size -= MXGEFW_PAD;
1103 len -= MXGEFW_PAD;
1104 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
1105 len, len,
1106 /* opaque, will come back in get_frag_header */
1107 (void *)(__force unsigned long)csum, csum);
1108 return 1;
1109 }
1110
1111 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1112
1113 /* allocate an skb to attach the page(s) to. This is done
1114 * after trying LRO, so as to avoid skb allocation overheads */
1115
1116 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1117 if (unlikely(skb == NULL)) {
1118 mgp->stats.rx_dropped++;
1119 do {
1120 i--;
1121 put_page(rx_frags[i].page);
1122 } while (i != 0);
1123 return 0;
1124 }
1125
1126 /* Attach the pages to the skb, and trim off any padding */
1127 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1128 if (skb_shinfo(skb)->frags[0].size <= 0) {
1129 put_page(skb_shinfo(skb)->frags[0].page);
1130 skb_shinfo(skb)->nr_frags = 0;
1131 }
1132 skb->protocol = eth_type_trans(skb, dev);
1133
1134 if (mgp->csum_flag) {
1135 if ((skb->protocol == htons(ETH_P_IP)) ||
1136 (skb->protocol == htons(ETH_P_IPV6))) {
1137 skb->csum = csum;
1138 skb->ip_summed = CHECKSUM_COMPLETE;
1139 } else
1140 myri10ge_vlan_ip_csum(skb, csum);
1141 }
1142 netif_receive_skb(skb);
1143 dev->last_rx = jiffies;
1144 return 1;
1145 }
1146
1147 static inline void
1148 myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
1149 {
1150 struct pci_dev *pdev = ss->mgp->pdev;
1151 struct myri10ge_tx_buf *tx = &ss->tx;
1152 struct sk_buff *skb;
1153 int idx, len;
1154
1155 while (tx->pkt_done != mcp_index) {
1156 idx = tx->done & tx->mask;
1157 skb = tx->info[idx].skb;
1158
1159 /* Mark as free */
1160 tx->info[idx].skb = NULL;
1161 if (tx->info[idx].last) {
1162 tx->pkt_done++;
1163 tx->info[idx].last = 0;
1164 }
1165 tx->done++;
1166 len = pci_unmap_len(&tx->info[idx], len);
1167 pci_unmap_len_set(&tx->info[idx], len, 0);
1168 if (skb) {
1169 ss->stats.tx_bytes += skb->len;
1170 ss->stats.tx_packets++;
1171 dev_kfree_skb_irq(skb);
1172 if (len)
1173 pci_unmap_single(pdev,
1174 pci_unmap_addr(&tx->info[idx],
1175 bus), len,
1176 PCI_DMA_TODEVICE);
1177 } else {
1178 if (len)
1179 pci_unmap_page(pdev,
1180 pci_unmap_addr(&tx->info[idx],
1181 bus), len,
1182 PCI_DMA_TODEVICE);
1183 }
1184 }
1185 /* start the queue if we've stopped it */
1186 if (netif_queue_stopped(ss->dev)
1187 && tx->req - tx->done < (tx->mask >> 1)) {
1188 tx->wake_queue++;
1189 netif_wake_queue(ss->dev);
1190 }
1191 }
1192
1193 static inline int
1194 myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1195 {
1196 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1197 struct myri10ge_priv *mgp = ss->mgp;
1198 unsigned long rx_bytes = 0;
1199 unsigned long rx_packets = 0;
1200 unsigned long rx_ok;
1201
1202 int idx = rx_done->idx;
1203 int cnt = rx_done->cnt;
1204 int work_done = 0;
1205 u16 length;
1206 __wsum checksum;
1207
1208 while (rx_done->entry[idx].length != 0 && work_done < budget) {
1209 length = ntohs(rx_done->entry[idx].length);
1210 rx_done->entry[idx].length = 0;
1211 checksum = csum_unfold(rx_done->entry[idx].checksum);
1212 if (length <= mgp->small_bytes)
1213 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
1214 mgp->small_bytes,
1215 length, checksum);
1216 else
1217 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
1218 mgp->big_bytes,
1219 length, checksum);
1220 rx_packets += rx_ok;
1221 rx_bytes += rx_ok * (unsigned long)length;
1222 cnt++;
1223 idx = cnt & (mgp->max_intr_slots - 1);
1224 work_done++;
1225 }
1226 rx_done->idx = idx;
1227 rx_done->cnt = cnt;
1228 ss->stats.rx_packets += rx_packets;
1229 ss->stats.rx_bytes += rx_bytes;
1230
1231 if (myri10ge_lro)
1232 lro_flush_all(&rx_done->lro_mgr);
1233
1234 /* restock receive rings if needed */
1235 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1236 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1237 mgp->small_bytes + MXGEFW_PAD, 0);
1238 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1239 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1240
1241 return work_done;
1242 }
1243
1244 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1245 {
1246 struct mcp_irq_data *stats = mgp->ss.fw_stats;
1247
1248 if (unlikely(stats->stats_updated)) {
1249 unsigned link_up = ntohl(stats->link_up);
1250 if (mgp->link_state != link_up) {
1251 mgp->link_state = link_up;
1252
1253 if (mgp->link_state == MXGEFW_LINK_UP) {
1254 if (netif_msg_link(mgp))
1255 printk(KERN_INFO
1256 "myri10ge: %s: link up\n",
1257 mgp->dev->name);
1258 netif_carrier_on(mgp->dev);
1259 mgp->link_changes++;
1260 } else {
1261 if (netif_msg_link(mgp))
1262 printk(KERN_INFO
1263 "myri10ge: %s: link %s\n",
1264 mgp->dev->name,
1265 (link_up == MXGEFW_LINK_MYRINET ?
1266 "mismatch (Myrinet detected)" :
1267 "down"));
1268 netif_carrier_off(mgp->dev);
1269 mgp->link_changes++;
1270 }
1271 }
1272 if (mgp->rdma_tags_available !=
1273 ntohl(stats->rdma_tags_available)) {
1274 mgp->rdma_tags_available =
1275 ntohl(stats->rdma_tags_available);
1276 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1277 "%d tags left\n", mgp->dev->name,
1278 mgp->rdma_tags_available);
1279 }
1280 mgp->down_cnt += stats->link_down;
1281 if (stats->link_down)
1282 wake_up(&mgp->down_wq);
1283 }
1284 }
1285
1286 static int myri10ge_poll(struct napi_struct *napi, int budget)
1287 {
1288 struct myri10ge_slice_state *ss =
1289 container_of(napi, struct myri10ge_slice_state, napi);
1290 struct net_device *netdev = ss->mgp->dev;
1291 int work_done;
1292
1293 /* process as many rx events as NAPI will allow */
1294 work_done = myri10ge_clean_rx_done(ss, budget);
1295
1296 if (work_done < budget) {
1297 netif_rx_complete(netdev, napi);
1298 put_be32(htonl(3), ss->irq_claim);
1299 }
1300 return work_done;
1301 }
1302
1303 static irqreturn_t myri10ge_intr(int irq, void *arg)
1304 {
1305 struct myri10ge_slice_state *ss = arg;
1306 struct myri10ge_priv *mgp = ss->mgp;
1307 struct mcp_irq_data *stats = ss->fw_stats;
1308 struct myri10ge_tx_buf *tx = &ss->tx;
1309 u32 send_done_count;
1310 int i;
1311
1312 /* make sure it is our IRQ, and that the DMA has finished */
1313 if (unlikely(!stats->valid))
1314 return (IRQ_NONE);
1315
1316 /* low bit indicates receives are present, so schedule
1317 * napi poll handler */
1318 if (stats->valid & 1)
1319 netif_rx_schedule(ss->dev, &ss->napi);
1320
1321 if (!mgp->msi_enabled) {
1322 put_be32(0, mgp->irq_deassert);
1323 if (!myri10ge_deassert_wait)
1324 stats->valid = 0;
1325 mb();
1326 } else
1327 stats->valid = 0;
1328
1329 /* Wait for IRQ line to go low, if using INTx */
1330 i = 0;
1331 while (1) {
1332 i++;
1333 /* check for transmit completes and receives */
1334 send_done_count = ntohl(stats->send_done_count);
1335 if (send_done_count != tx->pkt_done)
1336 myri10ge_tx_done(ss, (int)send_done_count);
1337 if (unlikely(i > myri10ge_max_irq_loops)) {
1338 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1339 mgp->dev->name);
1340 stats->valid = 0;
1341 schedule_work(&mgp->watchdog_work);
1342 }
1343 if (likely(stats->valid == 0))
1344 break;
1345 cpu_relax();
1346 barrier();
1347 }
1348
1349 myri10ge_check_statblock(mgp);
1350
1351 put_be32(htonl(3), ss->irq_claim + 1);
1352 return (IRQ_HANDLED);
1353 }
1354
1355 static int
1356 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1357 {
1358 struct myri10ge_priv *mgp = netdev_priv(netdev);
1359 char *ptr;
1360 int i;
1361
1362 cmd->autoneg = AUTONEG_DISABLE;
1363 cmd->speed = SPEED_10000;
1364 cmd->duplex = DUPLEX_FULL;
1365
1366 /*
1367 * parse the product code to deterimine the interface type
1368 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1369 * after the 3rd dash in the driver's cached copy of the
1370 * EEPROM's product code string.
1371 */
1372 ptr = mgp->product_code_string;
1373 if (ptr == NULL) {
1374 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
1375 netdev->name);
1376 return 0;
1377 }
1378 for (i = 0; i < 3; i++, ptr++) {
1379 ptr = strchr(ptr, '-');
1380 if (ptr == NULL) {
1381 printk(KERN_ERR "myri10ge: %s: Invalid product "
1382 "code %s\n", netdev->name,
1383 mgp->product_code_string);
1384 return 0;
1385 }
1386 }
1387 if (*ptr == 'R' || *ptr == 'Q') {
1388 /* We've found either an XFP or quad ribbon fiber */
1389 cmd->port = PORT_FIBRE;
1390 }
1391 return 0;
1392 }
1393
1394 static void
1395 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1396 {
1397 struct myri10ge_priv *mgp = netdev_priv(netdev);
1398
1399 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1400 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1401 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1402 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1403 }
1404
1405 static int
1406 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1407 {
1408 struct myri10ge_priv *mgp = netdev_priv(netdev);
1409
1410 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1411 return 0;
1412 }
1413
1414 static int
1415 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1416 {
1417 struct myri10ge_priv *mgp = netdev_priv(netdev);
1418
1419 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1420 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1421 return 0;
1422 }
1423
1424 static void
1425 myri10ge_get_pauseparam(struct net_device *netdev,
1426 struct ethtool_pauseparam *pause)
1427 {
1428 struct myri10ge_priv *mgp = netdev_priv(netdev);
1429
1430 pause->autoneg = 0;
1431 pause->rx_pause = mgp->pause;
1432 pause->tx_pause = mgp->pause;
1433 }
1434
1435 static int
1436 myri10ge_set_pauseparam(struct net_device *netdev,
1437 struct ethtool_pauseparam *pause)
1438 {
1439 struct myri10ge_priv *mgp = netdev_priv(netdev);
1440
1441 if (pause->tx_pause != mgp->pause)
1442 return myri10ge_change_pause(mgp, pause->tx_pause);
1443 if (pause->rx_pause != mgp->pause)
1444 return myri10ge_change_pause(mgp, pause->tx_pause);
1445 if (pause->autoneg != 0)
1446 return -EINVAL;
1447 return 0;
1448 }
1449
1450 static void
1451 myri10ge_get_ringparam(struct net_device *netdev,
1452 struct ethtool_ringparam *ring)
1453 {
1454 struct myri10ge_priv *mgp = netdev_priv(netdev);
1455
1456 ring->rx_mini_max_pending = mgp->ss.rx_small.mask + 1;
1457 ring->rx_max_pending = mgp->ss.rx_big.mask + 1;
1458 ring->rx_jumbo_max_pending = 0;
1459 ring->tx_max_pending = mgp->ss.rx_small.mask + 1;
1460 ring->rx_mini_pending = ring->rx_mini_max_pending;
1461 ring->rx_pending = ring->rx_max_pending;
1462 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1463 ring->tx_pending = ring->tx_max_pending;
1464 }
1465
1466 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1467 {
1468 struct myri10ge_priv *mgp = netdev_priv(netdev);
1469
1470 if (mgp->csum_flag)
1471 return 1;
1472 else
1473 return 0;
1474 }
1475
1476 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1477 {
1478 struct myri10ge_priv *mgp = netdev_priv(netdev);
1479
1480 if (csum_enabled)
1481 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1482 else
1483 mgp->csum_flag = 0;
1484 return 0;
1485 }
1486
1487 static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1488 {
1489 struct myri10ge_priv *mgp = netdev_priv(netdev);
1490 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1491
1492 if (tso_enabled)
1493 netdev->features |= flags;
1494 else
1495 netdev->features &= ~flags;
1496 return 0;
1497 }
1498
1499 static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1500 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1501 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1502 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1503 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1504 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1505 "tx_heartbeat_errors", "tx_window_errors",
1506 /* device-specific stats */
1507 "tx_boundary", "WC", "irq", "MSI",
1508 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1509 "serial_number", "watchdog_resets",
1510 "link_changes", "link_up", "dropped_link_overflow",
1511 "dropped_link_error_or_filtered",
1512 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1513 "dropped_unicast_filtered", "dropped_multicast_filtered",
1514 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1515 "dropped_no_big_buffer"
1516 };
1517
1518 static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1519 "----------- slice ---------",
1520 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1521 "rx_small_cnt", "rx_big_cnt",
1522 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1523 "LRO flushed",
1524 "LRO avg aggr", "LRO no_desc"
1525 };
1526
1527 #define MYRI10GE_NET_STATS_LEN 21
1528 #define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1529 #define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1530
1531 static void
1532 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1533 {
1534 switch (stringset) {
1535 case ETH_SS_STATS:
1536 memcpy(data, *myri10ge_gstrings_main_stats,
1537 sizeof(myri10ge_gstrings_main_stats));
1538 data += sizeof(myri10ge_gstrings_main_stats);
1539 memcpy(data, *myri10ge_gstrings_slice_stats,
1540 sizeof(myri10ge_gstrings_slice_stats));
1541 data += sizeof(myri10ge_gstrings_slice_stats);
1542 break;
1543 }
1544 }
1545
1546 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1547 {
1548 switch (sset) {
1549 case ETH_SS_STATS:
1550 return MYRI10GE_MAIN_STATS_LEN + MYRI10GE_SLICE_STATS_LEN;
1551 default:
1552 return -EOPNOTSUPP;
1553 }
1554 }
1555
1556 static void
1557 myri10ge_get_ethtool_stats(struct net_device *netdev,
1558 struct ethtool_stats *stats, u64 * data)
1559 {
1560 struct myri10ge_priv *mgp = netdev_priv(netdev);
1561 struct myri10ge_slice_state *ss;
1562 int i;
1563
1564 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1565 data[i] = ((unsigned long *)&mgp->stats)[i];
1566
1567 data[i++] = (unsigned int)mgp->tx_boundary;
1568 data[i++] = (unsigned int)mgp->wc_enabled;
1569 data[i++] = (unsigned int)mgp->pdev->irq;
1570 data[i++] = (unsigned int)mgp->msi_enabled;
1571 data[i++] = (unsigned int)mgp->read_dma;
1572 data[i++] = (unsigned int)mgp->write_dma;
1573 data[i++] = (unsigned int)mgp->read_write_dma;
1574 data[i++] = (unsigned int)mgp->serial_number;
1575 data[i++] = (unsigned int)mgp->watchdog_resets;
1576 data[i++] = (unsigned int)mgp->link_changes;
1577
1578 /* firmware stats are useful only in the first slice */
1579 ss = &mgp->ss;
1580 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1581 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1582 data[i++] =
1583 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1584 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1585 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1586 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1587 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
1588 data[i++] =
1589 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1590 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1591 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1592 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1593 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1594
1595 data[i++] = 0;
1596 data[i++] = (unsigned int)ss->tx.pkt_start;
1597 data[i++] = (unsigned int)ss->tx.pkt_done;
1598 data[i++] = (unsigned int)ss->tx.req;
1599 data[i++] = (unsigned int)ss->tx.done;
1600 data[i++] = (unsigned int)ss->rx_small.cnt;
1601 data[i++] = (unsigned int)ss->rx_big.cnt;
1602 data[i++] = (unsigned int)ss->tx.wake_queue;
1603 data[i++] = (unsigned int)ss->tx.stop_queue;
1604 data[i++] = (unsigned int)ss->tx.linearized;
1605 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1606 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1607 if (ss->rx_done.lro_mgr.stats.flushed)
1608 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1609 ss->rx_done.lro_mgr.stats.flushed;
1610 else
1611 data[i++] = 0;
1612 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1613 }
1614
1615 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1616 {
1617 struct myri10ge_priv *mgp = netdev_priv(netdev);
1618 mgp->msg_enable = value;
1619 }
1620
1621 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1622 {
1623 struct myri10ge_priv *mgp = netdev_priv(netdev);
1624 return mgp->msg_enable;
1625 }
1626
1627 static const struct ethtool_ops myri10ge_ethtool_ops = {
1628 .get_settings = myri10ge_get_settings,
1629 .get_drvinfo = myri10ge_get_drvinfo,
1630 .get_coalesce = myri10ge_get_coalesce,
1631 .set_coalesce = myri10ge_set_coalesce,
1632 .get_pauseparam = myri10ge_get_pauseparam,
1633 .set_pauseparam = myri10ge_set_pauseparam,
1634 .get_ringparam = myri10ge_get_ringparam,
1635 .get_rx_csum = myri10ge_get_rx_csum,
1636 .set_rx_csum = myri10ge_set_rx_csum,
1637 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1638 .set_sg = ethtool_op_set_sg,
1639 .set_tso = myri10ge_set_tso,
1640 .get_link = ethtool_op_get_link,
1641 .get_strings = myri10ge_get_strings,
1642 .get_sset_count = myri10ge_get_sset_count,
1643 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1644 .set_msglevel = myri10ge_set_msglevel,
1645 .get_msglevel = myri10ge_get_msglevel
1646 };
1647
1648 static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1649 {
1650 struct myri10ge_priv *mgp = ss->mgp;
1651 struct myri10ge_cmd cmd;
1652 struct net_device *dev = mgp->dev;
1653 int tx_ring_size, rx_ring_size;
1654 int tx_ring_entries, rx_ring_entries;
1655 int i, status;
1656 size_t bytes;
1657
1658 /* get ring sizes */
1659 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1660 tx_ring_size = cmd.data0;
1661 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1662 if (status != 0)
1663 return status;
1664 rx_ring_size = cmd.data0;
1665
1666 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1667 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1668 ss->tx.mask = tx_ring_entries - 1;
1669 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
1670
1671 status = -ENOMEM;
1672
1673 /* allocate the host shadow rings */
1674
1675 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1676 * sizeof(*ss->tx.req_list);
1677 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1678 if (ss->tx.req_bytes == NULL)
1679 goto abort_with_nothing;
1680
1681 /* ensure req_list entries are aligned to 8 bytes */
1682 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1683 ALIGN((unsigned long)ss->tx.req_bytes, 8);
1684
1685 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1686 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1687 if (ss->rx_small.shadow == NULL)
1688 goto abort_with_tx_req_bytes;
1689
1690 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1691 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1692 if (ss->rx_big.shadow == NULL)
1693 goto abort_with_rx_small_shadow;
1694
1695 /* allocate the host info rings */
1696
1697 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1698 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1699 if (ss->tx.info == NULL)
1700 goto abort_with_rx_big_shadow;
1701
1702 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1703 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1704 if (ss->rx_small.info == NULL)
1705 goto abort_with_tx_info;
1706
1707 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1708 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1709 if (ss->rx_big.info == NULL)
1710 goto abort_with_rx_small_info;
1711
1712 /* Fill the receive rings */
1713 ss->rx_big.cnt = 0;
1714 ss->rx_small.cnt = 0;
1715 ss->rx_big.fill_cnt = 0;
1716 ss->rx_small.fill_cnt = 0;
1717 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1718 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1719 ss->rx_small.watchdog_needed = 0;
1720 ss->rx_big.watchdog_needed = 0;
1721 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1722 mgp->small_bytes + MXGEFW_PAD, 0);
1723
1724 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
1725 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1726 dev->name, ss->rx_small.fill_cnt);
1727 goto abort_with_rx_small_ring;
1728 }
1729
1730 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1731 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
1732 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1733 dev->name, ss->rx_big.fill_cnt);
1734 goto abort_with_rx_big_ring;
1735 }
1736
1737 return 0;
1738
1739 abort_with_rx_big_ring:
1740 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1741 int idx = i & ss->rx_big.mask;
1742 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
1743 mgp->big_bytes);
1744 put_page(ss->rx_big.info[idx].page);
1745 }
1746
1747 abort_with_rx_small_ring:
1748 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
1749 int idx = i & ss->rx_small.mask;
1750 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
1751 mgp->small_bytes + MXGEFW_PAD);
1752 put_page(ss->rx_small.info[idx].page);
1753 }
1754
1755 kfree(ss->rx_big.info);
1756
1757 abort_with_rx_small_info:
1758 kfree(ss->rx_small.info);
1759
1760 abort_with_tx_info:
1761 kfree(ss->tx.info);
1762
1763 abort_with_rx_big_shadow:
1764 kfree(ss->rx_big.shadow);
1765
1766 abort_with_rx_small_shadow:
1767 kfree(ss->rx_small.shadow);
1768
1769 abort_with_tx_req_bytes:
1770 kfree(ss->tx.req_bytes);
1771 ss->tx.req_bytes = NULL;
1772 ss->tx.req_list = NULL;
1773
1774 abort_with_nothing:
1775 return status;
1776 }
1777
1778 static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
1779 {
1780 struct myri10ge_priv *mgp = ss->mgp;
1781 struct sk_buff *skb;
1782 struct myri10ge_tx_buf *tx;
1783 int i, len, idx;
1784
1785 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1786 idx = i & ss->rx_big.mask;
1787 if (i == ss->rx_big.fill_cnt - 1)
1788 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1789 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
1790 mgp->big_bytes);
1791 put_page(ss->rx_big.info[idx].page);
1792 }
1793
1794 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
1795 idx = i & ss->rx_small.mask;
1796 if (i == ss->rx_small.fill_cnt - 1)
1797 ss->rx_small.info[idx].page_offset =
1798 MYRI10GE_ALLOC_SIZE;
1799 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
1800 mgp->small_bytes + MXGEFW_PAD);
1801 put_page(ss->rx_small.info[idx].page);
1802 }
1803 tx = &ss->tx;
1804 while (tx->done != tx->req) {
1805 idx = tx->done & tx->mask;
1806 skb = tx->info[idx].skb;
1807
1808 /* Mark as free */
1809 tx->info[idx].skb = NULL;
1810 tx->done++;
1811 len = pci_unmap_len(&tx->info[idx], len);
1812 pci_unmap_len_set(&tx->info[idx], len, 0);
1813 if (skb) {
1814 ss->stats.tx_dropped++;
1815 dev_kfree_skb_any(skb);
1816 if (len)
1817 pci_unmap_single(mgp->pdev,
1818 pci_unmap_addr(&tx->info[idx],
1819 bus), len,
1820 PCI_DMA_TODEVICE);
1821 } else {
1822 if (len)
1823 pci_unmap_page(mgp->pdev,
1824 pci_unmap_addr(&tx->info[idx],
1825 bus), len,
1826 PCI_DMA_TODEVICE);
1827 }
1828 }
1829 kfree(ss->rx_big.info);
1830
1831 kfree(ss->rx_small.info);
1832
1833 kfree(ss->tx.info);
1834
1835 kfree(ss->rx_big.shadow);
1836
1837 kfree(ss->rx_small.shadow);
1838
1839 kfree(ss->tx.req_bytes);
1840 ss->tx.req_bytes = NULL;
1841 ss->tx.req_list = NULL;
1842 }
1843
1844 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1845 {
1846 struct pci_dev *pdev = mgp->pdev;
1847 int status;
1848
1849 if (myri10ge_msi) {
1850 status = pci_enable_msi(pdev);
1851 if (status != 0)
1852 dev_err(&pdev->dev,
1853 "Error %d setting up MSI; falling back to xPIC\n",
1854 status);
1855 else
1856 mgp->msi_enabled = 1;
1857 } else {
1858 mgp->msi_enabled = 0;
1859 }
1860 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1861 mgp->dev->name, mgp);
1862 if (status != 0) {
1863 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1864 if (mgp->msi_enabled)
1865 pci_disable_msi(pdev);
1866 }
1867 return status;
1868 }
1869
1870 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1871 {
1872 struct pci_dev *pdev = mgp->pdev;
1873
1874 free_irq(pdev->irq, mgp);
1875 if (mgp->msi_enabled)
1876 pci_disable_msi(pdev);
1877 }
1878
1879 static int
1880 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
1881 void **ip_hdr, void **tcpudp_hdr,
1882 u64 * hdr_flags, void *priv)
1883 {
1884 struct ethhdr *eh;
1885 struct vlan_ethhdr *veh;
1886 struct iphdr *iph;
1887 u8 *va = page_address(frag->page) + frag->page_offset;
1888 unsigned long ll_hlen;
1889 /* passed opaque through lro_receive_frags() */
1890 __wsum csum = (__force __wsum) (unsigned long)priv;
1891
1892 /* find the mac header, aborting if not IPv4 */
1893
1894 eh = (struct ethhdr *)va;
1895 *mac_hdr = eh;
1896 ll_hlen = ETH_HLEN;
1897 if (eh->h_proto != htons(ETH_P_IP)) {
1898 if (eh->h_proto == htons(ETH_P_8021Q)) {
1899 veh = (struct vlan_ethhdr *)va;
1900 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
1901 return -1;
1902
1903 ll_hlen += VLAN_HLEN;
1904
1905 /*
1906 * HW checksum starts ETH_HLEN bytes into
1907 * frame, so we must subtract off the VLAN
1908 * header's checksum before csum can be used
1909 */
1910 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
1911 VLAN_HLEN, 0));
1912 } else {
1913 return -1;
1914 }
1915 }
1916 *hdr_flags = LRO_IPV4;
1917
1918 iph = (struct iphdr *)(va + ll_hlen);
1919 *ip_hdr = iph;
1920 if (iph->protocol != IPPROTO_TCP)
1921 return -1;
1922 *hdr_flags |= LRO_TCP;
1923 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
1924
1925 /* verify the IP checksum */
1926 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
1927 return -1;
1928
1929 /* verify the checksum */
1930 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
1931 ntohs(iph->tot_len) - (iph->ihl << 2),
1932 IPPROTO_TCP, csum)))
1933 return -1;
1934
1935 return 0;
1936 }
1937
1938 static int myri10ge_open(struct net_device *dev)
1939 {
1940 struct myri10ge_priv *mgp = netdev_priv(dev);
1941 struct myri10ge_cmd cmd;
1942 struct net_lro_mgr *lro_mgr;
1943 int status, big_pow2;
1944
1945 if (mgp->running != MYRI10GE_ETH_STOPPED)
1946 return -EBUSY;
1947
1948 mgp->running = MYRI10GE_ETH_STARTING;
1949 status = myri10ge_reset(mgp);
1950 if (status != 0) {
1951 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
1952 goto abort_with_nothing;
1953 }
1954
1955 status = myri10ge_request_irq(mgp);
1956 if (status != 0)
1957 goto abort_with_nothing;
1958
1959 /* decide what small buffer size to use. For good TCP rx
1960 * performance, it is important to not receive 1514 byte
1961 * frames into jumbo buffers, as it confuses the socket buffer
1962 * accounting code, leading to drops and erratic performance.
1963 */
1964
1965 if (dev->mtu <= ETH_DATA_LEN)
1966 /* enough for a TCP header */
1967 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1968 ? (128 - MXGEFW_PAD)
1969 : (SMP_CACHE_BYTES - MXGEFW_PAD);
1970 else
1971 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1972 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
1973
1974 /* Override the small buffer size? */
1975 if (myri10ge_small_bytes > 0)
1976 mgp->small_bytes = myri10ge_small_bytes;
1977
1978 /* get the lanai pointers to the send and receive rings */
1979
1980 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1981 mgp->ss.tx.lanai =
1982 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1983
1984 status |=
1985 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1986 mgp->ss.rx_small.lanai =
1987 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1988
1989 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1990 mgp->ss.rx_big.lanai =
1991 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1992
1993 if (status != 0) {
1994 printk(KERN_ERR
1995 "myri10ge: %s: failed to get ring sizes or locations\n",
1996 dev->name);
1997 mgp->running = MYRI10GE_ETH_STOPPED;
1998 goto abort_with_irq;
1999 }
2000
2001 if (myri10ge_wcfifo && mgp->wc_enabled) {
2002 mgp->ss.tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
2003 mgp->ss.rx_small.wc_fifo =
2004 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
2005 mgp->ss.rx_big.wc_fifo =
2006 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
2007 } else {
2008 mgp->ss.tx.wc_fifo = NULL;
2009 mgp->ss.rx_small.wc_fifo = NULL;
2010 mgp->ss.rx_big.wc_fifo = NULL;
2011 }
2012
2013 /* Firmware needs the big buff size as a power of 2. Lie and
2014 * tell him the buffer is larger, because we only use 1
2015 * buffer/pkt, and the mtu will prevent overruns.
2016 */
2017 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2018 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
2019 while (!is_power_of_2(big_pow2))
2020 big_pow2++;
2021 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2022 } else {
2023 big_pow2 = MYRI10GE_ALLOC_SIZE;
2024 mgp->big_bytes = big_pow2;
2025 }
2026
2027 status = myri10ge_allocate_rings(&mgp->ss);
2028 if (status != 0)
2029 goto abort_with_irq;
2030
2031 /* now give firmware buffers sizes, and MTU */
2032 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2033 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2034 cmd.data0 = mgp->small_bytes;
2035 status |=
2036 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2037 cmd.data0 = big_pow2;
2038 status |=
2039 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2040 if (status) {
2041 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2042 dev->name);
2043 goto abort_with_rings;
2044 }
2045
2046 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->ss.fw_stats_bus);
2047 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->ss.fw_stats_bus);
2048 cmd.data2 = sizeof(struct mcp_irq_data);
2049 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2050 if (status == -ENOSYS) {
2051 dma_addr_t bus = mgp->ss.fw_stats_bus;
2052 bus += offsetof(struct mcp_irq_data, send_done_count);
2053 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2054 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2055 status = myri10ge_send_cmd(mgp,
2056 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2057 &cmd, 0);
2058 /* Firmware cannot support multicast without STATS_DMA_V2 */
2059 mgp->fw_multicast_support = 0;
2060 } else {
2061 mgp->fw_multicast_support = 1;
2062 }
2063 if (status) {
2064 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
2065 dev->name);
2066 goto abort_with_rings;
2067 }
2068
2069 mgp->link_state = ~0U;
2070 mgp->rdma_tags_available = 15;
2071
2072 lro_mgr = &mgp->ss.rx_done.lro_mgr;
2073 lro_mgr->dev = dev;
2074 lro_mgr->features = LRO_F_NAPI;
2075 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2076 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2077 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2078 lro_mgr->lro_arr = mgp->ss.rx_done.lro_desc;
2079 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2080 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2081 lro_mgr->frag_align_pad = 2;
2082 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2083 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2084
2085 napi_enable(&mgp->ss.napi); /* must happen prior to any irq */
2086
2087 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2088 if (status) {
2089 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2090 dev->name);
2091 goto abort_with_rings;
2092 }
2093
2094 mgp->ss.tx.wake_queue = 0;
2095 mgp->ss.tx.stop_queue = 0;
2096 mgp->running = MYRI10GE_ETH_RUNNING;
2097 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2098 add_timer(&mgp->watchdog_timer);
2099 netif_wake_queue(dev);
2100 return 0;
2101
2102 abort_with_rings:
2103 myri10ge_free_rings(&mgp->ss);
2104
2105 abort_with_irq:
2106 myri10ge_free_irq(mgp);
2107
2108 abort_with_nothing:
2109 mgp->running = MYRI10GE_ETH_STOPPED;
2110 return -ENOMEM;
2111 }
2112
2113 static int myri10ge_close(struct net_device *dev)
2114 {
2115 struct myri10ge_priv *mgp = netdev_priv(dev);
2116 struct myri10ge_cmd cmd;
2117 int status, old_down_cnt;
2118
2119 if (mgp->running != MYRI10GE_ETH_RUNNING)
2120 return 0;
2121
2122 if (mgp->ss.tx.req_bytes == NULL)
2123 return 0;
2124
2125 del_timer_sync(&mgp->watchdog_timer);
2126 mgp->running = MYRI10GE_ETH_STOPPING;
2127 napi_disable(&mgp->ss.napi);
2128 netif_carrier_off(dev);
2129 netif_stop_queue(dev);
2130 old_down_cnt = mgp->down_cnt;
2131 mb();
2132 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2133 if (status)
2134 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2135 dev->name);
2136
2137 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2138 if (old_down_cnt == mgp->down_cnt)
2139 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2140
2141 netif_tx_disable(dev);
2142 myri10ge_free_irq(mgp);
2143 myri10ge_free_rings(&mgp->ss);
2144
2145 mgp->running = MYRI10GE_ETH_STOPPED;
2146 return 0;
2147 }
2148
2149 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2150 * backwards one at a time and handle ring wraps */
2151
2152 static inline void
2153 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2154 struct mcp_kreq_ether_send *src, int cnt)
2155 {
2156 int idx, starting_slot;
2157 starting_slot = tx->req;
2158 while (cnt > 1) {
2159 cnt--;
2160 idx = (starting_slot + cnt) & tx->mask;
2161 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2162 mb();
2163 }
2164 }
2165
2166 /*
2167 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2168 * at most 32 bytes at a time, so as to avoid involving the software
2169 * pio handler in the nic. We re-write the first segment's flags
2170 * to mark them valid only after writing the entire chain.
2171 */
2172
2173 static inline void
2174 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2175 int cnt)
2176 {
2177 int idx, i;
2178 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2179 struct mcp_kreq_ether_send *srcp;
2180 u8 last_flags;
2181
2182 idx = tx->req & tx->mask;
2183
2184 last_flags = src->flags;
2185 src->flags = 0;
2186 mb();
2187 dst = dstp = &tx->lanai[idx];
2188 srcp = src;
2189
2190 if ((idx + cnt) < tx->mask) {
2191 for (i = 0; i < (cnt - 1); i += 2) {
2192 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2193 mb(); /* force write every 32 bytes */
2194 srcp += 2;
2195 dstp += 2;
2196 }
2197 } else {
2198 /* submit all but the first request, and ensure
2199 * that it is submitted below */
2200 myri10ge_submit_req_backwards(tx, src, cnt);
2201 i = 0;
2202 }
2203 if (i < cnt) {
2204 /* submit the first request */
2205 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2206 mb(); /* barrier before setting valid flag */
2207 }
2208
2209 /* re-write the last 32-bits with the valid flags */
2210 src->flags = last_flags;
2211 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2212 tx->req += cnt;
2213 mb();
2214 }
2215
2216 static inline void
2217 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2218 struct mcp_kreq_ether_send *src, int cnt)
2219 {
2220 tx->req += cnt;
2221 mb();
2222 while (cnt >= 4) {
2223 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2224 mb();
2225 src += 4;
2226 cnt -= 4;
2227 }
2228 if (cnt > 0) {
2229 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2230 * needs to be so that we don't overrun it */
2231 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2232 src, 64);
2233 mb();
2234 }
2235 }
2236
2237 /*
2238 * Transmit a packet. We need to split the packet so that a single
2239 * segment does not cross myri10ge->tx_boundary, so this makes segment
2240 * counting tricky. So rather than try to count segments up front, we
2241 * just give up if there are too few segments to hold a reasonably
2242 * fragmented packet currently available. If we run
2243 * out of segments while preparing a packet for DMA, we just linearize
2244 * it and try again.
2245 */
2246
2247 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2248 {
2249 struct myri10ge_priv *mgp = netdev_priv(dev);
2250 struct myri10ge_slice_state *ss;
2251 struct mcp_kreq_ether_send *req;
2252 struct myri10ge_tx_buf *tx;
2253 struct skb_frag_struct *frag;
2254 dma_addr_t bus;
2255 u32 low;
2256 __be32 high_swapped;
2257 unsigned int len;
2258 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2259 u16 pseudo_hdr_offset, cksum_offset;
2260 int cum_len, seglen, boundary, rdma_count;
2261 u8 flags, odd_flag;
2262
2263 /* always transmit through slot 0 */
2264 ss = &mgp->ss;
2265 tx = &ss->tx;
2266 again:
2267 req = tx->req_list;
2268 avail = tx->mask - 1 - (tx->req - tx->done);
2269
2270 mss = 0;
2271 max_segments = MXGEFW_MAX_SEND_DESC;
2272
2273 if (skb_is_gso(skb)) {
2274 mss = skb_shinfo(skb)->gso_size;
2275 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2276 }
2277
2278 if ((unlikely(avail < max_segments))) {
2279 /* we are out of transmit resources */
2280 tx->stop_queue++;
2281 netif_stop_queue(dev);
2282 return 1;
2283 }
2284
2285 /* Setup checksum offloading, if needed */
2286 cksum_offset = 0;
2287 pseudo_hdr_offset = 0;
2288 odd_flag = 0;
2289 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2290 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2291 cksum_offset = skb_transport_offset(skb);
2292 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2293 /* If the headers are excessively large, then we must
2294 * fall back to a software checksum */
2295 if (unlikely(!mss && (cksum_offset > 255 ||
2296 pseudo_hdr_offset > 127))) {
2297 if (skb_checksum_help(skb))
2298 goto drop;
2299 cksum_offset = 0;
2300 pseudo_hdr_offset = 0;
2301 } else {
2302 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2303 flags |= MXGEFW_FLAGS_CKSUM;
2304 }
2305 }
2306
2307 cum_len = 0;
2308
2309 if (mss) { /* TSO */
2310 /* this removes any CKSUM flag from before */
2311 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2312
2313 /* negative cum_len signifies to the
2314 * send loop that we are still in the
2315 * header portion of the TSO packet.
2316 * TSO header can be at most 1KB long */
2317 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2318
2319 /* for IPv6 TSO, the checksum offset stores the
2320 * TCP header length, to save the firmware from
2321 * the need to parse the headers */
2322 if (skb_is_gso_v6(skb)) {
2323 cksum_offset = tcp_hdrlen(skb);
2324 /* Can only handle headers <= max_tso6 long */
2325 if (unlikely(-cum_len > mgp->max_tso6))
2326 return myri10ge_sw_tso(skb, dev);
2327 }
2328 /* for TSO, pseudo_hdr_offset holds mss.
2329 * The firmware figures out where to put
2330 * the checksum by parsing the header. */
2331 pseudo_hdr_offset = mss;
2332 } else
2333 /* Mark small packets, and pad out tiny packets */
2334 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2335 flags |= MXGEFW_FLAGS_SMALL;
2336
2337 /* pad frames to at least ETH_ZLEN bytes */
2338 if (unlikely(skb->len < ETH_ZLEN)) {
2339 if (skb_padto(skb, ETH_ZLEN)) {
2340 /* The packet is gone, so we must
2341 * return 0 */
2342 ss->stats.tx_dropped += 1;
2343 return 0;
2344 }
2345 /* adjust the len to account for the zero pad
2346 * so that the nic can know how long it is */
2347 skb->len = ETH_ZLEN;
2348 }
2349 }
2350
2351 /* map the skb for DMA */
2352 len = skb->len - skb->data_len;
2353 idx = tx->req & tx->mask;
2354 tx->info[idx].skb = skb;
2355 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2356 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2357 pci_unmap_len_set(&tx->info[idx], len, len);
2358
2359 frag_cnt = skb_shinfo(skb)->nr_frags;
2360 frag_idx = 0;
2361 count = 0;
2362 rdma_count = 0;
2363
2364 /* "rdma_count" is the number of RDMAs belonging to the
2365 * current packet BEFORE the current send request. For
2366 * non-TSO packets, this is equal to "count".
2367 * For TSO packets, rdma_count needs to be reset
2368 * to 0 after a segment cut.
2369 *
2370 * The rdma_count field of the send request is
2371 * the number of RDMAs of the packet starting at
2372 * that request. For TSO send requests with one ore more cuts
2373 * in the middle, this is the number of RDMAs starting
2374 * after the last cut in the request. All previous
2375 * segments before the last cut implicitly have 1 RDMA.
2376 *
2377 * Since the number of RDMAs is not known beforehand,
2378 * it must be filled-in retroactively - after each
2379 * segmentation cut or at the end of the entire packet.
2380 */
2381
2382 while (1) {
2383 /* Break the SKB or Fragment up into pieces which
2384 * do not cross mgp->tx_boundary */
2385 low = MYRI10GE_LOWPART_TO_U32(bus);
2386 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2387 while (len) {
2388 u8 flags_next;
2389 int cum_len_next;
2390
2391 if (unlikely(count == max_segments))
2392 goto abort_linearize;
2393
2394 boundary =
2395 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2396 seglen = boundary - low;
2397 if (seglen > len)
2398 seglen = len;
2399 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2400 cum_len_next = cum_len + seglen;
2401 if (mss) { /* TSO */
2402 (req - rdma_count)->rdma_count = rdma_count + 1;
2403
2404 if (likely(cum_len >= 0)) { /* payload */
2405 int next_is_first, chop;
2406
2407 chop = (cum_len_next > mss);
2408 cum_len_next = cum_len_next % mss;
2409 next_is_first = (cum_len_next == 0);
2410 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2411 flags_next |= next_is_first *
2412 MXGEFW_FLAGS_FIRST;
2413 rdma_count |= -(chop | next_is_first);
2414 rdma_count += chop & !next_is_first;
2415 } else if (likely(cum_len_next >= 0)) { /* header ends */
2416 int small;
2417
2418 rdma_count = -1;
2419 cum_len_next = 0;
2420 seglen = -cum_len;
2421 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2422 flags_next = MXGEFW_FLAGS_TSO_PLD |
2423 MXGEFW_FLAGS_FIRST |
2424 (small * MXGEFW_FLAGS_SMALL);
2425 }
2426 }
2427 req->addr_high = high_swapped;
2428 req->addr_low = htonl(low);
2429 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2430 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2431 req->rdma_count = 1;
2432 req->length = htons(seglen);
2433 req->cksum_offset = cksum_offset;
2434 req->flags = flags | ((cum_len & 1) * odd_flag);
2435
2436 low += seglen;
2437 len -= seglen;
2438 cum_len = cum_len_next;
2439 flags = flags_next;
2440 req++;
2441 count++;
2442 rdma_count++;
2443 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2444 if (unlikely(cksum_offset > seglen))
2445 cksum_offset -= seglen;
2446 else
2447 cksum_offset = 0;
2448 }
2449 }
2450 if (frag_idx == frag_cnt)
2451 break;
2452
2453 /* map next fragment for DMA */
2454 idx = (count + tx->req) & tx->mask;
2455 frag = &skb_shinfo(skb)->frags[frag_idx];
2456 frag_idx++;
2457 len = frag->size;
2458 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2459 len, PCI_DMA_TODEVICE);
2460 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2461 pci_unmap_len_set(&tx->info[idx], len, len);
2462 }
2463
2464 (req - rdma_count)->rdma_count = rdma_count;
2465 if (mss)
2466 do {
2467 req--;
2468 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2469 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2470 MXGEFW_FLAGS_FIRST)));
2471 idx = ((count - 1) + tx->req) & tx->mask;
2472 tx->info[idx].last = 1;
2473 if (tx->wc_fifo == NULL)
2474 myri10ge_submit_req(tx, tx->req_list, count);
2475 else
2476 myri10ge_submit_req_wc(tx, tx->req_list, count);
2477 tx->pkt_start++;
2478 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2479 tx->stop_queue++;
2480 netif_stop_queue(dev);
2481 }
2482 dev->trans_start = jiffies;
2483 return 0;
2484
2485 abort_linearize:
2486 /* Free any DMA resources we've alloced and clear out the skb
2487 * slot so as to not trip up assertions, and to avoid a
2488 * double-free if linearizing fails */
2489
2490 last_idx = (idx + 1) & tx->mask;
2491 idx = tx->req & tx->mask;
2492 tx->info[idx].skb = NULL;
2493 do {
2494 len = pci_unmap_len(&tx->info[idx], len);
2495 if (len) {
2496 if (tx->info[idx].skb != NULL)
2497 pci_unmap_single(mgp->pdev,
2498 pci_unmap_addr(&tx->info[idx],
2499 bus), len,
2500 PCI_DMA_TODEVICE);
2501 else
2502 pci_unmap_page(mgp->pdev,
2503 pci_unmap_addr(&tx->info[idx],
2504 bus), len,
2505 PCI_DMA_TODEVICE);
2506 pci_unmap_len_set(&tx->info[idx], len, 0);
2507 tx->info[idx].skb = NULL;
2508 }
2509 idx = (idx + 1) & tx->mask;
2510 } while (idx != last_idx);
2511 if (skb_is_gso(skb)) {
2512 printk(KERN_ERR
2513 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2514 mgp->dev->name);
2515 goto drop;
2516 }
2517
2518 if (skb_linearize(skb))
2519 goto drop;
2520
2521 tx->linearized++;
2522 goto again;
2523
2524 drop:
2525 dev_kfree_skb_any(skb);
2526 ss->stats.tx_dropped += 1;
2527 return 0;
2528
2529 }
2530
2531 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2532 {
2533 struct sk_buff *segs, *curr;
2534 struct myri10ge_priv *mgp = netdev_priv(dev);
2535 int status;
2536
2537 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2538 if (IS_ERR(segs))
2539 goto drop;
2540
2541 while (segs) {
2542 curr = segs;
2543 segs = segs->next;
2544 curr->next = NULL;
2545 status = myri10ge_xmit(curr, dev);
2546 if (status != 0) {
2547 dev_kfree_skb_any(curr);
2548 if (segs != NULL) {
2549 curr = segs;
2550 segs = segs->next;
2551 curr->next = NULL;
2552 dev_kfree_skb_any(segs);
2553 }
2554 goto drop;
2555 }
2556 }
2557 dev_kfree_skb_any(skb);
2558 return 0;
2559
2560 drop:
2561 dev_kfree_skb_any(skb);
2562 mgp->stats.tx_dropped += 1;
2563 return 0;
2564 }
2565
2566 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2567 {
2568 struct myri10ge_priv *mgp = netdev_priv(dev);
2569 return &mgp->stats;
2570 }
2571
2572 static void myri10ge_set_multicast_list(struct net_device *dev)
2573 {
2574 struct myri10ge_priv *mgp = netdev_priv(dev);
2575 struct myri10ge_cmd cmd;
2576 struct dev_mc_list *mc_list;
2577 __be32 data[2] = { 0, 0 };
2578 int err;
2579 DECLARE_MAC_BUF(mac);
2580
2581 /* can be called from atomic contexts,
2582 * pass 1 to force atomicity in myri10ge_send_cmd() */
2583 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2584
2585 /* This firmware is known to not support multicast */
2586 if (!mgp->fw_multicast_support)
2587 return;
2588
2589 /* Disable multicast filtering */
2590
2591 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2592 if (err != 0) {
2593 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2594 " error status: %d\n", dev->name, err);
2595 goto abort;
2596 }
2597
2598 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
2599 /* request to disable multicast filtering, so quit here */
2600 return;
2601 }
2602
2603 /* Flush the filters */
2604
2605 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2606 &cmd, 1);
2607 if (err != 0) {
2608 printk(KERN_ERR
2609 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2610 ", error status: %d\n", dev->name, err);
2611 goto abort;
2612 }
2613
2614 /* Walk the multicast list, and add each address */
2615 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
2616 memcpy(data, &mc_list->dmi_addr, 6);
2617 cmd.data0 = ntohl(data[0]);
2618 cmd.data1 = ntohl(data[1]);
2619 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2620 &cmd, 1);
2621
2622 if (err != 0) {
2623 printk(KERN_ERR "myri10ge: %s: Failed "
2624 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2625 "%d\t", dev->name, err);
2626 printk(KERN_ERR "MAC %s\n",
2627 print_mac(mac, mc_list->dmi_addr));
2628 goto abort;
2629 }
2630 }
2631 /* Enable multicast filtering */
2632 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2633 if (err != 0) {
2634 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2635 "error status: %d\n", dev->name, err);
2636 goto abort;
2637 }
2638
2639 return;
2640
2641 abort:
2642 return;
2643 }
2644
2645 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2646 {
2647 struct sockaddr *sa = addr;
2648 struct myri10ge_priv *mgp = netdev_priv(dev);
2649 int status;
2650
2651 if (!is_valid_ether_addr(sa->sa_data))
2652 return -EADDRNOTAVAIL;
2653
2654 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2655 if (status != 0) {
2656 printk(KERN_ERR
2657 "myri10ge: %s: changing mac address failed with %d\n",
2658 dev->name, status);
2659 return status;
2660 }
2661
2662 /* change the dev structure */
2663 memcpy(dev->dev_addr, sa->sa_data, 6);
2664 return 0;
2665 }
2666
2667 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2668 {
2669 struct myri10ge_priv *mgp = netdev_priv(dev);
2670 int error = 0;
2671
2672 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2673 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2674 dev->name, new_mtu);
2675 return -EINVAL;
2676 }
2677 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2678 dev->name, dev->mtu, new_mtu);
2679 if (mgp->running) {
2680 /* if we change the mtu on an active device, we must
2681 * reset the device so the firmware sees the change */
2682 myri10ge_close(dev);
2683 dev->mtu = new_mtu;
2684 myri10ge_open(dev);
2685 } else
2686 dev->mtu = new_mtu;
2687
2688 return error;
2689 }
2690
2691 /*
2692 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2693 * Only do it if the bridge is a root port since we don't want to disturb
2694 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2695 */
2696
2697 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2698 {
2699 struct pci_dev *bridge = mgp->pdev->bus->self;
2700 struct device *dev = &mgp->pdev->dev;
2701 unsigned cap;
2702 unsigned err_cap;
2703 u16 val;
2704 u8 ext_type;
2705 int ret;
2706
2707 if (!myri10ge_ecrc_enable || !bridge)
2708 return;
2709
2710 /* check that the bridge is a root port */
2711 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2712 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2713 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2714 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2715 if (myri10ge_ecrc_enable > 1) {
2716 struct pci_dev *prev_bridge, *old_bridge = bridge;
2717
2718 /* Walk the hierarchy up to the root port
2719 * where ECRC has to be enabled */
2720 do {
2721 prev_bridge = bridge;
2722 bridge = bridge->bus->self;
2723 if (!bridge || prev_bridge == bridge) {
2724 dev_err(dev,
2725 "Failed to find root port"
2726 " to force ECRC\n");
2727 return;
2728 }
2729 cap =
2730 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2731 pci_read_config_word(bridge,
2732 cap + PCI_CAP_FLAGS, &val);
2733 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2734 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2735
2736 dev_info(dev,
2737 "Forcing ECRC on non-root port %s"
2738 " (enabling on root port %s)\n",
2739 pci_name(old_bridge), pci_name(bridge));
2740 } else {
2741 dev_err(dev,
2742 "Not enabling ECRC on non-root port %s\n",
2743 pci_name(bridge));
2744 return;
2745 }
2746 }
2747
2748 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
2749 if (!cap)
2750 return;
2751
2752 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2753 if (ret) {
2754 dev_err(dev, "failed reading ext-conf-space of %s\n",
2755 pci_name(bridge));
2756 dev_err(dev, "\t pci=nommconf in use? "
2757 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2758 return;
2759 }
2760 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2761 return;
2762
2763 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2764 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2765 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2766 }
2767
2768 /*
2769 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2770 * when the PCI-E Completion packets are aligned on an 8-byte
2771 * boundary. Some PCI-E chip sets always align Completion packets; on
2772 * the ones that do not, the alignment can be enforced by enabling
2773 * ECRC generation (if supported).
2774 *
2775 * When PCI-E Completion packets are not aligned, it is actually more
2776 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2777 *
2778 * If the driver can neither enable ECRC nor verify that it has
2779 * already been enabled, then it must use a firmware image which works
2780 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2781 * should also ensure that it never gives the device a Read-DMA which is
2782 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
2783 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2784 * firmware image, and set tx_boundary to 4KB.
2785 */
2786
2787 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
2788 {
2789 struct pci_dev *pdev = mgp->pdev;
2790 struct device *dev = &pdev->dev;
2791 int status;
2792
2793 mgp->tx_boundary = 4096;
2794 /*
2795 * Verify the max read request size was set to 4KB
2796 * before trying the test with 4KB.
2797 */
2798 status = pcie_get_readrq(pdev);
2799 if (status < 0) {
2800 dev_err(dev, "Couldn't read max read req size: %d\n", status);
2801 goto abort;
2802 }
2803 if (status != 4096) {
2804 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
2805 mgp->tx_boundary = 2048;
2806 }
2807 /*
2808 * load the optimized firmware (which assumes aligned PCIe
2809 * completions) in order to see if it works on this host.
2810 */
2811 mgp->fw_name = myri10ge_fw_aligned;
2812 status = myri10ge_load_firmware(mgp);
2813 if (status != 0) {
2814 goto abort;
2815 }
2816
2817 /*
2818 * Enable ECRC if possible
2819 */
2820 myri10ge_enable_ecrc(mgp);
2821
2822 /*
2823 * Run a DMA test which watches for unaligned completions and
2824 * aborts on the first one seen.
2825 */
2826
2827 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
2828 if (status == 0)
2829 return; /* keep the aligned firmware */
2830
2831 if (status != -E2BIG)
2832 dev_warn(dev, "DMA test failed: %d\n", status);
2833 if (status == -ENOSYS)
2834 dev_warn(dev, "Falling back to ethp! "
2835 "Please install up to date fw\n");
2836 abort:
2837 /* fall back to using the unaligned firmware */
2838 mgp->tx_boundary = 2048;
2839 mgp->fw_name = myri10ge_fw_unaligned;
2840
2841 }
2842
2843 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2844 {
2845 if (myri10ge_force_firmware == 0) {
2846 int link_width, exp_cap;
2847 u16 lnk;
2848
2849 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2850 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2851 link_width = (lnk >> 4) & 0x3f;
2852
2853 /* Check to see if Link is less than 8 or if the
2854 * upstream bridge is known to provide aligned
2855 * completions */
2856 if (link_width < 8) {
2857 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2858 link_width);
2859 mgp->tx_boundary = 4096;
2860 mgp->fw_name = myri10ge_fw_aligned;
2861 } else {
2862 myri10ge_firmware_probe(mgp);
2863 }
2864 } else {
2865 if (myri10ge_force_firmware == 1) {
2866 dev_info(&mgp->pdev->dev,
2867 "Assuming aligned completions (forced)\n");
2868 mgp->tx_boundary = 4096;
2869 mgp->fw_name = myri10ge_fw_aligned;
2870 } else {
2871 dev_info(&mgp->pdev->dev,
2872 "Assuming unaligned completions (forced)\n");
2873 mgp->tx_boundary = 2048;
2874 mgp->fw_name = myri10ge_fw_unaligned;
2875 }
2876 }
2877 if (myri10ge_fw_name != NULL) {
2878 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2879 myri10ge_fw_name);
2880 mgp->fw_name = myri10ge_fw_name;
2881 }
2882 }
2883
2884 #ifdef CONFIG_PM
2885 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2886 {
2887 struct myri10ge_priv *mgp;
2888 struct net_device *netdev;
2889
2890 mgp = pci_get_drvdata(pdev);
2891 if (mgp == NULL)
2892 return -EINVAL;
2893 netdev = mgp->dev;
2894
2895 netif_device_detach(netdev);
2896 if (netif_running(netdev)) {
2897 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2898 rtnl_lock();
2899 myri10ge_close(netdev);
2900 rtnl_unlock();
2901 }
2902 myri10ge_dummy_rdma(mgp, 0);
2903 pci_save_state(pdev);
2904 pci_disable_device(pdev);
2905
2906 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
2907 }
2908
2909 static int myri10ge_resume(struct pci_dev *pdev)
2910 {
2911 struct myri10ge_priv *mgp;
2912 struct net_device *netdev;
2913 int status;
2914 u16 vendor;
2915
2916 mgp = pci_get_drvdata(pdev);
2917 if (mgp == NULL)
2918 return -EINVAL;
2919 netdev = mgp->dev;
2920 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2921 msleep(5); /* give card time to respond */
2922 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2923 if (vendor == 0xffff) {
2924 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2925 mgp->dev->name);
2926 return -EIO;
2927 }
2928
2929 status = pci_restore_state(pdev);
2930 if (status)
2931 return status;
2932
2933 status = pci_enable_device(pdev);
2934 if (status) {
2935 dev_err(&pdev->dev, "failed to enable device\n");
2936 return status;
2937 }
2938
2939 pci_set_master(pdev);
2940
2941 myri10ge_reset(mgp);
2942 myri10ge_dummy_rdma(mgp, 1);
2943
2944 /* Save configuration space to be restored if the
2945 * nic resets due to a parity error */
2946 pci_save_state(pdev);
2947
2948 if (netif_running(netdev)) {
2949 rtnl_lock();
2950 status = myri10ge_open(netdev);
2951 rtnl_unlock();
2952 if (status != 0)
2953 goto abort_with_enabled;
2954
2955 }
2956 netif_device_attach(netdev);
2957
2958 return 0;
2959
2960 abort_with_enabled:
2961 pci_disable_device(pdev);
2962 return -EIO;
2963
2964 }
2965 #endif /* CONFIG_PM */
2966
2967 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2968 {
2969 struct pci_dev *pdev = mgp->pdev;
2970 int vs = mgp->vendor_specific_offset;
2971 u32 reboot;
2972
2973 /*enter read32 mode */
2974 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2975
2976 /*read REBOOT_STATUS (0xfffffff0) */
2977 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2978 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2979 return reboot;
2980 }
2981
2982 /*
2983 * This watchdog is used to check whether the board has suffered
2984 * from a parity error and needs to be recovered.
2985 */
2986 static void myri10ge_watchdog(struct work_struct *work)
2987 {
2988 struct myri10ge_priv *mgp =
2989 container_of(work, struct myri10ge_priv, watchdog_work);
2990 struct myri10ge_tx_buf *tx;
2991 u32 reboot;
2992 int status;
2993 u16 cmd, vendor;
2994
2995 mgp->watchdog_resets++;
2996 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2997 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2998 /* Bus master DMA disabled? Check to see
2999 * if the card rebooted due to a parity error
3000 * For now, just report it */
3001 reboot = myri10ge_read_reboot(mgp);
3002 printk(KERN_ERR
3003 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3004 mgp->dev->name, reboot,
3005 myri10ge_reset_recover ? " " : " not");
3006 if (myri10ge_reset_recover == 0)
3007 return;
3008
3009 myri10ge_reset_recover--;
3010
3011 /*
3012 * A rebooted nic will come back with config space as
3013 * it was after power was applied to PCIe bus.
3014 * Attempt to restore config space which was saved
3015 * when the driver was loaded, or the last time the
3016 * nic was resumed from power saving mode.
3017 */
3018 pci_restore_state(mgp->pdev);
3019
3020 /* save state again for accounting reasons */
3021 pci_save_state(mgp->pdev);
3022
3023 } else {
3024 /* if we get back -1's from our slot, perhaps somebody
3025 * powered off our card. Don't try to reset it in
3026 * this case */
3027 if (cmd == 0xffff) {
3028 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3029 if (vendor == 0xffff) {
3030 printk(KERN_ERR
3031 "myri10ge: %s: device disappeared!\n",
3032 mgp->dev->name);
3033 return;
3034 }
3035 }
3036 /* Perhaps it is a software error. Try to reset */
3037
3038 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3039 mgp->dev->name);
3040 tx = &mgp->ss.tx;
3041 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
3042 mgp->dev->name, tx->req, tx->done,
3043 tx->pkt_start, tx->pkt_done,
3044 (int)ntohl(mgp->ss.fw_stats->send_done_count));
3045 msleep(2000);
3046 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
3047 mgp->dev->name, tx->req, tx->done,
3048 tx->pkt_start, tx->pkt_done,
3049 (int)ntohl(mgp->ss.fw_stats->send_done_count));
3050 }
3051 rtnl_lock();
3052 myri10ge_close(mgp->dev);
3053 status = myri10ge_load_firmware(mgp);
3054 if (status != 0)
3055 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3056 mgp->dev->name);
3057 else
3058 myri10ge_open(mgp->dev);
3059 rtnl_unlock();
3060 }
3061
3062 /*
3063 * We use our own timer routine rather than relying upon
3064 * netdev->tx_timeout because we have a very large hardware transmit
3065 * queue. Due to the large queue, the netdev->tx_timeout function
3066 * cannot detect a NIC with a parity error in a timely fashion if the
3067 * NIC is lightly loaded.
3068 */
3069 static void myri10ge_watchdog_timer(unsigned long arg)
3070 {
3071 struct myri10ge_priv *mgp;
3072 struct myri10ge_slice_state *ss;
3073 u32 rx_pause_cnt;
3074
3075 mgp = (struct myri10ge_priv *)arg;
3076
3077 rx_pause_cnt = ntohl(mgp->ss.fw_stats->dropped_pause);
3078
3079 ss = &mgp->ss;
3080 if (ss->rx_small.watchdog_needed) {
3081 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3082 mgp->small_bytes + MXGEFW_PAD, 1);
3083 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3084 myri10ge_fill_thresh)
3085 ss->rx_small.watchdog_needed = 0;
3086 }
3087 if (ss->rx_big.watchdog_needed) {
3088 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 1);
3089 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3090 myri10ge_fill_thresh)
3091 ss->rx_big.watchdog_needed = 0;
3092 }
3093
3094 if (ss->tx.req != ss->tx.done &&
3095 ss->tx.done == ss->watchdog_tx_done &&
3096 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3097 /* nic seems like it might be stuck.. */
3098 if (rx_pause_cnt != mgp->watchdog_pause) {
3099 if (net_ratelimit())
3100 printk(KERN_WARNING "myri10ge %s:"
3101 "TX paused, check link partner\n",
3102 mgp->dev->name);
3103 } else {
3104 schedule_work(&mgp->watchdog_work);
3105 return;
3106 }
3107 }
3108 /* rearm timer */
3109 mod_timer(&mgp->watchdog_timer,
3110 jiffies + myri10ge_watchdog_timeout * HZ);
3111 ss->watchdog_tx_done = ss->tx.done;
3112 ss->watchdog_tx_req = ss->tx.req;
3113 mgp->watchdog_pause = rx_pause_cnt;
3114 }
3115
3116 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3117 {
3118 struct net_device *netdev;
3119 struct myri10ge_priv *mgp;
3120 struct device *dev = &pdev->dev;
3121 size_t bytes;
3122 int i;
3123 int status = -ENXIO;
3124 int dac_enabled;
3125
3126 netdev = alloc_etherdev(sizeof(*mgp));
3127 if (netdev == NULL) {
3128 dev_err(dev, "Could not allocate ethernet device\n");
3129 return -ENOMEM;
3130 }
3131
3132 SET_NETDEV_DEV(netdev, &pdev->dev);
3133
3134 mgp = netdev_priv(netdev);
3135 mgp->dev = netdev;
3136 netif_napi_add(netdev, &mgp->ss.napi, myri10ge_poll, myri10ge_napi_weight);
3137 mgp->pdev = pdev;
3138 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3139 mgp->pause = myri10ge_flow_control;
3140 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3141 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3142 init_waitqueue_head(&mgp->down_wq);
3143
3144 if (pci_enable_device(pdev)) {
3145 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3146 status = -ENODEV;
3147 goto abort_with_netdev;
3148 }
3149
3150 /* Find the vendor-specific cap so we can check
3151 * the reboot register later on */
3152 mgp->vendor_specific_offset
3153 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3154
3155 /* Set our max read request to 4KB */
3156 status = pcie_set_readrq(pdev, 4096);
3157 if (status != 0) {
3158 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3159 status);
3160 goto abort_with_netdev;
3161 }
3162
3163 pci_set_master(pdev);
3164 dac_enabled = 1;
3165 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3166 if (status != 0) {
3167 dac_enabled = 0;
3168 dev_err(&pdev->dev,
3169 "64-bit pci address mask was refused, "
3170 "trying 32-bit\n");
3171 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3172 }
3173 if (status != 0) {
3174 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3175 goto abort_with_netdev;
3176 }
3177 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3178 &mgp->cmd_bus, GFP_KERNEL);
3179 if (mgp->cmd == NULL)
3180 goto abort_with_netdev;
3181
3182 mgp->ss.fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->ss.fw_stats),
3183 &mgp->ss.fw_stats_bus, GFP_KERNEL);
3184 if (mgp->ss.fw_stats == NULL)
3185 goto abort_with_cmd;
3186
3187 mgp->board_span = pci_resource_len(pdev, 0);
3188 mgp->iomem_base = pci_resource_start(pdev, 0);
3189 mgp->mtrr = -1;
3190 mgp->wc_enabled = 0;
3191 #ifdef CONFIG_MTRR
3192 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3193 MTRR_TYPE_WRCOMB, 1);
3194 if (mgp->mtrr >= 0)
3195 mgp->wc_enabled = 1;
3196 #endif
3197 /* Hack. need to get rid of these magic numbers */
3198 mgp->sram_size =
3199 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3200 if (mgp->sram_size > mgp->board_span) {
3201 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3202 mgp->board_span);
3203 goto abort_with_wc;
3204 }
3205 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
3206 if (mgp->sram == NULL) {
3207 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3208 mgp->board_span, mgp->iomem_base);
3209 status = -ENXIO;
3210 goto abort_with_wc;
3211 }
3212 memcpy_fromio(mgp->eeprom_strings,
3213 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3214 MYRI10GE_EEPROM_STRINGS_SIZE);
3215 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3216 status = myri10ge_read_mac_addr(mgp);
3217 if (status)
3218 goto abort_with_ioremap;
3219
3220 for (i = 0; i < ETH_ALEN; i++)
3221 netdev->dev_addr[i] = mgp->mac_addr[i];
3222
3223 /* allocate rx done ring */
3224 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
3225 mgp->ss.rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3226 &mgp->ss.rx_done.bus, GFP_KERNEL);
3227 if (mgp->ss.rx_done.entry == NULL)
3228 goto abort_with_ioremap;
3229 memset(mgp->ss.rx_done.entry, 0, bytes);
3230
3231 myri10ge_select_firmware(mgp);
3232
3233 status = myri10ge_load_firmware(mgp);
3234 if (status != 0) {
3235 dev_err(&pdev->dev, "failed to load firmware\n");
3236 goto abort_with_rx_done;
3237 }
3238
3239 status = myri10ge_reset(mgp);
3240 if (status != 0) {
3241 dev_err(&pdev->dev, "failed reset\n");
3242 goto abort_with_firmware;
3243 }
3244
3245 pci_set_drvdata(pdev, mgp);
3246 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3247 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3248 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3249 myri10ge_initial_mtu = 68;
3250 netdev->mtu = myri10ge_initial_mtu;
3251 netdev->open = myri10ge_open;
3252 netdev->stop = myri10ge_close;
3253 netdev->hard_start_xmit = myri10ge_xmit;
3254 netdev->get_stats = myri10ge_get_stats;
3255 netdev->base_addr = mgp->iomem_base;
3256 netdev->change_mtu = myri10ge_change_mtu;
3257 netdev->set_multicast_list = myri10ge_set_multicast_list;
3258 netdev->set_mac_address = myri10ge_set_mac_address;
3259 netdev->features = mgp->features;
3260 if (dac_enabled)
3261 netdev->features |= NETIF_F_HIGHDMA;
3262
3263 /* make sure we can get an irq, and that MSI can be
3264 * setup (if available). Also ensure netdev->irq
3265 * is set to correct value if MSI is enabled */
3266 status = myri10ge_request_irq(mgp);
3267 if (status != 0)
3268 goto abort_with_firmware;
3269 netdev->irq = pdev->irq;
3270 myri10ge_free_irq(mgp);
3271
3272 /* Save configuration space to be restored if the
3273 * nic resets due to a parity error */
3274 pci_save_state(pdev);
3275
3276 /* Setup the watchdog timer */
3277 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3278 (unsigned long)mgp);
3279
3280 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3281 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3282 status = register_netdev(netdev);
3283 if (status != 0) {
3284 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3285 goto abort_with_state;
3286 }
3287 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3288 (mgp->msi_enabled ? "MSI" : "xPIC"),
3289 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3290 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3291
3292 return 0;
3293
3294 abort_with_state:
3295 pci_restore_state(pdev);
3296
3297 abort_with_firmware:
3298 myri10ge_dummy_rdma(mgp, 0);
3299
3300 abort_with_rx_done:
3301 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
3302 dma_free_coherent(&pdev->dev, bytes,
3303 mgp->ss.rx_done.entry, mgp->ss.rx_done.bus);
3304
3305 abort_with_ioremap:
3306 iounmap(mgp->sram);
3307
3308 abort_with_wc:
3309 #ifdef CONFIG_MTRR
3310 if (mgp->mtrr >= 0)
3311 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3312 #endif
3313 dma_free_coherent(&pdev->dev, sizeof(*mgp->ss.fw_stats),
3314 mgp->ss.fw_stats, mgp->ss.fw_stats_bus);
3315
3316 abort_with_cmd:
3317 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3318 mgp->cmd, mgp->cmd_bus);
3319
3320 abort_with_netdev:
3321
3322 free_netdev(netdev);
3323 return status;
3324 }
3325
3326 /*
3327 * myri10ge_remove
3328 *
3329 * Does what is necessary to shutdown one Myrinet device. Called
3330 * once for each Myrinet card by the kernel when a module is
3331 * unloaded.
3332 */
3333 static void myri10ge_remove(struct pci_dev *pdev)
3334 {
3335 struct myri10ge_priv *mgp;
3336 struct net_device *netdev;
3337 size_t bytes;
3338
3339 mgp = pci_get_drvdata(pdev);
3340 if (mgp == NULL)
3341 return;
3342
3343 flush_scheduled_work();
3344 netdev = mgp->dev;
3345 unregister_netdev(netdev);
3346
3347 myri10ge_dummy_rdma(mgp, 0);
3348
3349 /* avoid a memory leak */
3350 pci_restore_state(pdev);
3351
3352 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
3353 dma_free_coherent(&pdev->dev, bytes,
3354 mgp->ss.rx_done.entry, mgp->ss.rx_done.bus);
3355
3356 iounmap(mgp->sram);
3357
3358 #ifdef CONFIG_MTRR
3359 if (mgp->mtrr >= 0)
3360 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3361 #endif
3362 dma_free_coherent(&pdev->dev, sizeof(*mgp->ss.fw_stats),
3363 mgp->ss.fw_stats, mgp->ss.fw_stats_bus);
3364
3365 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3366 mgp->cmd, mgp->cmd_bus);
3367
3368 free_netdev(netdev);
3369 pci_set_drvdata(pdev, NULL);
3370 }
3371
3372 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
3373 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
3374
3375 static struct pci_device_id myri10ge_pci_tbl[] = {
3376 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
3377 {PCI_DEVICE
3378 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
3379 {0},
3380 };
3381
3382 static struct pci_driver myri10ge_driver = {
3383 .name = "myri10ge",
3384 .probe = myri10ge_probe,
3385 .remove = myri10ge_remove,
3386 .id_table = myri10ge_pci_tbl,
3387 #ifdef CONFIG_PM
3388 .suspend = myri10ge_suspend,
3389 .resume = myri10ge_resume,
3390 #endif
3391 };
3392
3393 static __init int myri10ge_init_module(void)
3394 {
3395 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3396 MYRI10GE_VERSION_STR);
3397 return pci_register_driver(&myri10ge_driver);
3398 }
3399
3400 module_init(myri10ge_init_module);
3401
3402 static __exit void myri10ge_cleanup_module(void)
3403 {
3404 pci_unregister_driver(&myri10ge_driver);
3405 }
3406
3407 module_exit(myri10ge_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)