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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / myri10ge / myri10ge.c
1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005 - 2007 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/ip.h>
52 #include <linux/inet.h>
53 #include <linux/in.h>
54 #include <linux/ethtool.h>
55 #include <linux/firmware.h>
56 #include <linux/delay.h>
57 #include <linux/version.h>
58 #include <linux/timer.h>
59 #include <linux/vmalloc.h>
60 #include <linux/crc32.h>
61 #include <linux/moduleparam.h>
62 #include <linux/io.h>
63 #include <linux/log2.h>
64 #include <net/checksum.h>
65 #include <asm/byteorder.h>
66 #include <asm/io.h>
67 #include <asm/processor.h>
68 #ifdef CONFIG_MTRR
69 #include <asm/mtrr.h>
70 #endif
71
72 #include "myri10ge_mcp.h"
73 #include "myri10ge_mcp_gen_header.h"
74
75 #define MYRI10GE_VERSION_STR "1.3.2-1.269"
76
77 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
78 MODULE_AUTHOR("Maintainer: help@myri.com");
79 MODULE_VERSION(MYRI10GE_VERSION_STR);
80 MODULE_LICENSE("Dual BSD/GPL");
81
82 #define MYRI10GE_MAX_ETHER_MTU 9014
83
84 #define MYRI10GE_ETH_STOPPED 0
85 #define MYRI10GE_ETH_STOPPING 1
86 #define MYRI10GE_ETH_STARTING 2
87 #define MYRI10GE_ETH_RUNNING 3
88 #define MYRI10GE_ETH_OPEN_FAILED 4
89
90 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
91 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
92
93 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
94 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
95
96 #define MYRI10GE_ALLOC_ORDER 0
97 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
98 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
99
100 struct myri10ge_rx_buffer_state {
101 struct page *page;
102 int page_offset;
103 DECLARE_PCI_UNMAP_ADDR(bus)
104 DECLARE_PCI_UNMAP_LEN(len)
105 };
106
107 struct myri10ge_tx_buffer_state {
108 struct sk_buff *skb;
109 int last;
110 DECLARE_PCI_UNMAP_ADDR(bus)
111 DECLARE_PCI_UNMAP_LEN(len)
112 };
113
114 struct myri10ge_cmd {
115 u32 data0;
116 u32 data1;
117 u32 data2;
118 };
119
120 struct myri10ge_rx_buf {
121 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
122 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
123 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
124 struct myri10ge_rx_buffer_state *info;
125 struct page *page;
126 dma_addr_t bus;
127 int page_offset;
128 int cnt;
129 int fill_cnt;
130 int alloc_fail;
131 int mask; /* number of rx slots -1 */
132 int watchdog_needed;
133 };
134
135 struct myri10ge_tx_buf {
136 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
137 u8 __iomem *wc_fifo; /* w/c send fifo address */
138 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
139 char *req_bytes;
140 struct myri10ge_tx_buffer_state *info;
141 int mask; /* number of transmit slots -1 */
142 int boundary; /* boundary transmits cannot cross */
143 int req ____cacheline_aligned; /* transmit slots submitted */
144 int pkt_start; /* packets started */
145 int done ____cacheline_aligned; /* transmit slots completed */
146 int pkt_done; /* packets completed */
147 };
148
149 struct myri10ge_rx_done {
150 struct mcp_slot *entry;
151 dma_addr_t bus;
152 int cnt;
153 int idx;
154 };
155
156 struct myri10ge_priv {
157 int running; /* running? */
158 int csum_flag; /* rx_csums? */
159 struct myri10ge_tx_buf tx; /* transmit ring */
160 struct myri10ge_rx_buf rx_small;
161 struct myri10ge_rx_buf rx_big;
162 struct myri10ge_rx_done rx_done;
163 int small_bytes;
164 int big_bytes;
165 struct net_device *dev;
166 struct net_device_stats stats;
167 u8 __iomem *sram;
168 int sram_size;
169 unsigned long board_span;
170 unsigned long iomem_base;
171 __be32 __iomem *irq_claim;
172 __be32 __iomem *irq_deassert;
173 char *mac_addr_string;
174 struct mcp_cmd_response *cmd;
175 dma_addr_t cmd_bus;
176 struct mcp_irq_data *fw_stats;
177 dma_addr_t fw_stats_bus;
178 struct pci_dev *pdev;
179 int msi_enabled;
180 __be32 link_state;
181 unsigned int rdma_tags_available;
182 int intr_coal_delay;
183 __be32 __iomem *intr_coal_delay_ptr;
184 int mtrr;
185 int wc_enabled;
186 int wake_queue;
187 int stop_queue;
188 int down_cnt;
189 wait_queue_head_t down_wq;
190 struct work_struct watchdog_work;
191 struct timer_list watchdog_timer;
192 int watchdog_tx_done;
193 int watchdog_tx_req;
194 int watchdog_pause;
195 int watchdog_resets;
196 int tx_linearized;
197 int pause;
198 char *fw_name;
199 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
200 char fw_version[128];
201 int fw_ver_major;
202 int fw_ver_minor;
203 int fw_ver_tiny;
204 int adopted_rx_filter_bug;
205 u8 mac_addr[6]; /* eeprom mac address */
206 unsigned long serial_number;
207 int vendor_specific_offset;
208 int fw_multicast_support;
209 u32 read_dma;
210 u32 write_dma;
211 u32 read_write_dma;
212 u32 link_changes;
213 u32 msg_enable;
214 };
215
216 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
217 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
218
219 static char *myri10ge_fw_name = NULL;
220 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
221 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
222
223 static int myri10ge_ecrc_enable = 1;
224 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
225 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
226
227 static int myri10ge_max_intr_slots = 1024;
228 module_param(myri10ge_max_intr_slots, int, S_IRUGO);
229 MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
230
231 static int myri10ge_small_bytes = -1; /* -1 == auto */
232 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
233 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
234
235 static int myri10ge_msi = 1; /* enable msi by default */
236 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
237 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
238
239 static int myri10ge_intr_coal_delay = 75;
240 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
241 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
242
243 static int myri10ge_flow_control = 1;
244 module_param(myri10ge_flow_control, int, S_IRUGO);
245 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
246
247 static int myri10ge_deassert_wait = 1;
248 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
249 MODULE_PARM_DESC(myri10ge_deassert_wait,
250 "Wait when deasserting legacy interrupts\n");
251
252 static int myri10ge_force_firmware = 0;
253 module_param(myri10ge_force_firmware, int, S_IRUGO);
254 MODULE_PARM_DESC(myri10ge_force_firmware,
255 "Force firmware to assume aligned completions\n");
256
257 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
258 module_param(myri10ge_initial_mtu, int, S_IRUGO);
259 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
260
261 static int myri10ge_napi_weight = 64;
262 module_param(myri10ge_napi_weight, int, S_IRUGO);
263 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
264
265 static int myri10ge_watchdog_timeout = 1;
266 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
267 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
268
269 static int myri10ge_max_irq_loops = 1048576;
270 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
271 MODULE_PARM_DESC(myri10ge_max_irq_loops,
272 "Set stuck legacy IRQ detection threshold\n");
273
274 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
275
276 static int myri10ge_debug = -1; /* defaults above */
277 module_param(myri10ge_debug, int, 0);
278 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
279
280 static int myri10ge_fill_thresh = 256;
281 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
282 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
283
284 static int myri10ge_reset_recover = 1;
285
286 static int myri10ge_wcfifo = 0;
287 module_param(myri10ge_wcfifo, int, S_IRUGO);
288 MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
289
290 #define MYRI10GE_FW_OFFSET 1024*1024
291 #define MYRI10GE_HIGHPART_TO_U32(X) \
292 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
293 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
294
295 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
296
297 static void myri10ge_set_multicast_list(struct net_device *dev);
298
299 static inline void put_be32(__be32 val, __be32 __iomem * p)
300 {
301 __raw_writel((__force __u32) val, (__force void __iomem *)p);
302 }
303
304 static int
305 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
306 struct myri10ge_cmd *data, int atomic)
307 {
308 struct mcp_cmd *buf;
309 char buf_bytes[sizeof(*buf) + 8];
310 struct mcp_cmd_response *response = mgp->cmd;
311 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
312 u32 dma_low, dma_high, result, value;
313 int sleep_total = 0;
314
315 /* ensure buf is aligned to 8 bytes */
316 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
317
318 buf->data0 = htonl(data->data0);
319 buf->data1 = htonl(data->data1);
320 buf->data2 = htonl(data->data2);
321 buf->cmd = htonl(cmd);
322 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
323 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
324
325 buf->response_addr.low = htonl(dma_low);
326 buf->response_addr.high = htonl(dma_high);
327 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
328 mb();
329 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
330
331 /* wait up to 15ms. Longest command is the DMA benchmark,
332 * which is capped at 5ms, but runs from a timeout handler
333 * that runs every 7.8ms. So a 15ms timeout leaves us with
334 * a 2.2ms margin
335 */
336 if (atomic) {
337 /* if atomic is set, do not sleep,
338 * and try to get the completion quickly
339 * (1ms will be enough for those commands) */
340 for (sleep_total = 0;
341 sleep_total < 1000
342 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
343 sleep_total += 10)
344 udelay(10);
345 } else {
346 /* use msleep for most command */
347 for (sleep_total = 0;
348 sleep_total < 15
349 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
350 sleep_total++)
351 msleep(1);
352 }
353
354 result = ntohl(response->result);
355 value = ntohl(response->data);
356 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
357 if (result == 0) {
358 data->data0 = value;
359 return 0;
360 } else if (result == MXGEFW_CMD_UNKNOWN) {
361 return -ENOSYS;
362 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
363 return -E2BIG;
364 } else {
365 dev_err(&mgp->pdev->dev,
366 "command %d failed, result = %d\n",
367 cmd, result);
368 return -ENXIO;
369 }
370 }
371
372 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
373 cmd, result);
374 return -EAGAIN;
375 }
376
377 /*
378 * The eeprom strings on the lanaiX have the format
379 * SN=x\0
380 * MAC=x:x:x:x:x:x\0
381 * PT:ddd mmm xx xx:xx:xx xx\0
382 * PV:ddd mmm xx xx:xx:xx xx\0
383 */
384 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
385 {
386 char *ptr, *limit;
387 int i;
388
389 ptr = mgp->eeprom_strings;
390 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
391
392 while (*ptr != '\0' && ptr < limit) {
393 if (memcmp(ptr, "MAC=", 4) == 0) {
394 ptr += 4;
395 mgp->mac_addr_string = ptr;
396 for (i = 0; i < 6; i++) {
397 if ((ptr + 2) > limit)
398 goto abort;
399 mgp->mac_addr[i] =
400 simple_strtoul(ptr, &ptr, 16);
401 ptr += 1;
402 }
403 }
404 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
405 ptr += 3;
406 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
407 }
408 while (ptr < limit && *ptr++) ;
409 }
410
411 return 0;
412
413 abort:
414 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
415 return -ENXIO;
416 }
417
418 /*
419 * Enable or disable periodic RDMAs from the host to make certain
420 * chipsets resend dropped PCIe messages
421 */
422
423 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
424 {
425 char __iomem *submit;
426 __be32 buf[16];
427 u32 dma_low, dma_high;
428 int i;
429
430 /* clear confirmation addr */
431 mgp->cmd->data = 0;
432 mb();
433
434 /* send a rdma command to the PCIe engine, and wait for the
435 * response in the confirmation address. The firmware should
436 * write a -1 there to indicate it is alive and well
437 */
438 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
439 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
440
441 buf[0] = htonl(dma_high); /* confirm addr MSW */
442 buf[1] = htonl(dma_low); /* confirm addr LSW */
443 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
444 buf[3] = htonl(dma_high); /* dummy addr MSW */
445 buf[4] = htonl(dma_low); /* dummy addr LSW */
446 buf[5] = htonl(enable); /* enable? */
447
448 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
449
450 myri10ge_pio_copy(submit, &buf, sizeof(buf));
451 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
452 msleep(1);
453 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
454 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
455 (enable ? "enable" : "disable"));
456 }
457
458 static int
459 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
460 struct mcp_gen_header *hdr)
461 {
462 struct device *dev = &mgp->pdev->dev;
463
464 /* check firmware type */
465 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
466 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
467 return -EINVAL;
468 }
469
470 /* save firmware version for ethtool */
471 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
472
473 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
474 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
475
476 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
477 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
478 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
479 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
480 MXGEFW_VERSION_MINOR);
481 return -EINVAL;
482 }
483 return 0;
484 }
485
486 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
487 {
488 unsigned crc, reread_crc;
489 const struct firmware *fw;
490 struct device *dev = &mgp->pdev->dev;
491 struct mcp_gen_header *hdr;
492 size_t hdr_offset;
493 int status;
494 unsigned i;
495
496 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
497 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
498 mgp->fw_name);
499 status = -EINVAL;
500 goto abort_with_nothing;
501 }
502
503 /* check size */
504
505 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
506 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
507 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
508 status = -EINVAL;
509 goto abort_with_fw;
510 }
511
512 /* check id */
513 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
514 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
515 dev_err(dev, "Bad firmware file\n");
516 status = -EINVAL;
517 goto abort_with_fw;
518 }
519 hdr = (void *)(fw->data + hdr_offset);
520
521 status = myri10ge_validate_firmware(mgp, hdr);
522 if (status != 0)
523 goto abort_with_fw;
524
525 crc = crc32(~0, fw->data, fw->size);
526 for (i = 0; i < fw->size; i += 256) {
527 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
528 fw->data + i,
529 min(256U, (unsigned)(fw->size - i)));
530 mb();
531 readb(mgp->sram);
532 }
533 /* corruption checking is good for parity recovery and buggy chipset */
534 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
535 reread_crc = crc32(~0, fw->data, fw->size);
536 if (crc != reread_crc) {
537 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
538 (unsigned)fw->size, reread_crc, crc);
539 status = -EIO;
540 goto abort_with_fw;
541 }
542 *size = (u32) fw->size;
543
544 abort_with_fw:
545 release_firmware(fw);
546
547 abort_with_nothing:
548 return status;
549 }
550
551 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
552 {
553 struct mcp_gen_header *hdr;
554 struct device *dev = &mgp->pdev->dev;
555 const size_t bytes = sizeof(struct mcp_gen_header);
556 size_t hdr_offset;
557 int status;
558
559 /* find running firmware header */
560 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
561
562 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
563 dev_err(dev, "Running firmware has bad header offset (%d)\n",
564 (int)hdr_offset);
565 return -EIO;
566 }
567
568 /* copy header of running firmware from SRAM to host memory to
569 * validate firmware */
570 hdr = kmalloc(bytes, GFP_KERNEL);
571 if (hdr == NULL) {
572 dev_err(dev, "could not malloc firmware hdr\n");
573 return -ENOMEM;
574 }
575 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
576 status = myri10ge_validate_firmware(mgp, hdr);
577 kfree(hdr);
578
579 /* check to see if adopted firmware has bug where adopting
580 * it will cause broadcasts to be filtered unless the NIC
581 * is kept in ALLMULTI mode */
582 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
583 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
584 mgp->adopted_rx_filter_bug = 1;
585 dev_warn(dev, "Adopting fw %d.%d.%d: "
586 "working around rx filter bug\n",
587 mgp->fw_ver_major, mgp->fw_ver_minor,
588 mgp->fw_ver_tiny);
589 }
590 return status;
591 }
592
593 static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
594 {
595 char __iomem *submit;
596 __be32 buf[16];
597 u32 dma_low, dma_high, size;
598 int status, i;
599
600 size = 0;
601 status = myri10ge_load_hotplug_firmware(mgp, &size);
602 if (status) {
603 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
604
605 /* Do not attempt to adopt firmware if there
606 * was a bad crc */
607 if (status == -EIO)
608 return status;
609
610 status = myri10ge_adopt_running_firmware(mgp);
611 if (status != 0) {
612 dev_err(&mgp->pdev->dev,
613 "failed to adopt running firmware\n");
614 return status;
615 }
616 dev_info(&mgp->pdev->dev,
617 "Successfully adopted running firmware\n");
618 if (mgp->tx.boundary == 4096) {
619 dev_warn(&mgp->pdev->dev,
620 "Using firmware currently running on NIC"
621 ". For optimal\n");
622 dev_warn(&mgp->pdev->dev,
623 "performance consider loading optimized "
624 "firmware\n");
625 dev_warn(&mgp->pdev->dev, "via hotplug\n");
626 }
627
628 mgp->fw_name = "adopted";
629 mgp->tx.boundary = 2048;
630 return status;
631 }
632
633 /* clear confirmation addr */
634 mgp->cmd->data = 0;
635 mb();
636
637 /* send a reload command to the bootstrap MCP, and wait for the
638 * response in the confirmation address. The firmware should
639 * write a -1 there to indicate it is alive and well
640 */
641 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
642 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
643
644 buf[0] = htonl(dma_high); /* confirm addr MSW */
645 buf[1] = htonl(dma_low); /* confirm addr LSW */
646 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
647
648 /* FIX: All newest firmware should un-protect the bottom of
649 * the sram before handoff. However, the very first interfaces
650 * do not. Therefore the handoff copy must skip the first 8 bytes
651 */
652 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
653 buf[4] = htonl(size - 8); /* length of code */
654 buf[5] = htonl(8); /* where to copy to */
655 buf[6] = htonl(0); /* where to jump to */
656
657 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
658
659 myri10ge_pio_copy(submit, &buf, sizeof(buf));
660 mb();
661 msleep(1);
662 mb();
663 i = 0;
664 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
665 msleep(1);
666 i++;
667 }
668 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
669 dev_err(&mgp->pdev->dev, "handoff failed\n");
670 return -ENXIO;
671 }
672 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
673 myri10ge_dummy_rdma(mgp, 1);
674
675 return 0;
676 }
677
678 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
679 {
680 struct myri10ge_cmd cmd;
681 int status;
682
683 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
684 | (addr[2] << 8) | addr[3]);
685
686 cmd.data1 = ((addr[4] << 8) | (addr[5]));
687
688 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
689 return status;
690 }
691
692 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
693 {
694 struct myri10ge_cmd cmd;
695 int status, ctl;
696
697 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
698 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
699
700 if (status) {
701 printk(KERN_ERR
702 "myri10ge: %s: Failed to set flow control mode\n",
703 mgp->dev->name);
704 return status;
705 }
706 mgp->pause = pause;
707 return 0;
708 }
709
710 static void
711 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
712 {
713 struct myri10ge_cmd cmd;
714 int status, ctl;
715
716 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
717 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
718 if (status)
719 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
720 mgp->dev->name);
721 }
722
723 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
724 {
725 struct myri10ge_cmd cmd;
726 int status;
727 u32 len;
728 struct page *dmatest_page;
729 dma_addr_t dmatest_bus;
730 char *test = " ";
731
732 dmatest_page = alloc_page(GFP_KERNEL);
733 if (!dmatest_page)
734 return -ENOMEM;
735 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
736 DMA_BIDIRECTIONAL);
737
738 /* Run a small DMA test.
739 * The magic multipliers to the length tell the firmware
740 * to do DMA read, write, or read+write tests. The
741 * results are returned in cmd.data0. The upper 16
742 * bits or the return is the number of transfers completed.
743 * The lower 16 bits is the time in 0.5us ticks that the
744 * transfers took to complete.
745 */
746
747 len = mgp->tx.boundary;
748
749 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
750 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
751 cmd.data2 = len * 0x10000;
752 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
753 if (status != 0) {
754 test = "read";
755 goto abort;
756 }
757 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
758 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
759 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
760 cmd.data2 = len * 0x1;
761 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
762 if (status != 0) {
763 test = "write";
764 goto abort;
765 }
766 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
767
768 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
769 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
770 cmd.data2 = len * 0x10001;
771 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
772 if (status != 0) {
773 test = "read/write";
774 goto abort;
775 }
776 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
777 (cmd.data0 & 0xffff);
778
779 abort:
780 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
781 put_page(dmatest_page);
782
783 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
784 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
785 test, status);
786
787 return status;
788 }
789
790 static int myri10ge_reset(struct myri10ge_priv *mgp)
791 {
792 struct myri10ge_cmd cmd;
793 int status;
794 size_t bytes;
795
796 /* try to send a reset command to the card to see if it
797 * is alive */
798 memset(&cmd, 0, sizeof(cmd));
799 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
800 if (status != 0) {
801 dev_err(&mgp->pdev->dev, "failed reset\n");
802 return -ENXIO;
803 }
804
805 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
806
807 /* Now exchange information about interrupts */
808
809 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
810 memset(mgp->rx_done.entry, 0, bytes);
811 cmd.data0 = (u32) bytes;
812 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
813 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
814 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
815 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
816
817 status |=
818 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
819 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
820 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
821 &cmd, 0);
822 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
823
824 status |= myri10ge_send_cmd
825 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
826 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
827 if (status != 0) {
828 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
829 return status;
830 }
831 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
832
833 memset(mgp->rx_done.entry, 0, bytes);
834
835 /* reset mcp/driver shared state back to 0 */
836 mgp->tx.req = 0;
837 mgp->tx.done = 0;
838 mgp->tx.pkt_start = 0;
839 mgp->tx.pkt_done = 0;
840 mgp->rx_big.cnt = 0;
841 mgp->rx_small.cnt = 0;
842 mgp->rx_done.idx = 0;
843 mgp->rx_done.cnt = 0;
844 mgp->link_changes = 0;
845 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
846 myri10ge_change_pause(mgp, mgp->pause);
847 myri10ge_set_multicast_list(mgp->dev);
848 return status;
849 }
850
851 static inline void
852 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
853 struct mcp_kreq_ether_recv *src)
854 {
855 __be32 low;
856
857 low = src->addr_low;
858 src->addr_low = htonl(DMA_32BIT_MASK);
859 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
860 mb();
861 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
862 mb();
863 src->addr_low = low;
864 put_be32(low, &dst->addr_low);
865 mb();
866 }
867
868 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
869 {
870 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
871
872 if ((skb->protocol == htons(ETH_P_8021Q)) &&
873 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
874 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
875 skb->csum = hw_csum;
876 skb->ip_summed = CHECKSUM_COMPLETE;
877 }
878 }
879
880 static inline void
881 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
882 struct skb_frag_struct *rx_frags, int len, int hlen)
883 {
884 struct skb_frag_struct *skb_frags;
885
886 skb->len = skb->data_len = len;
887 skb->truesize = len + sizeof(struct sk_buff);
888 /* attach the page(s) */
889
890 skb_frags = skb_shinfo(skb)->frags;
891 while (len > 0) {
892 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
893 len -= rx_frags->size;
894 skb_frags++;
895 rx_frags++;
896 skb_shinfo(skb)->nr_frags++;
897 }
898
899 /* pskb_may_pull is not available in irq context, but
900 * skb_pull() (for ether_pad and eth_type_trans()) requires
901 * the beginning of the packet in skb_headlen(), move it
902 * manually */
903 skb_copy_to_linear_data(skb, va, hlen);
904 skb_shinfo(skb)->frags[0].page_offset += hlen;
905 skb_shinfo(skb)->frags[0].size -= hlen;
906 skb->data_len -= hlen;
907 skb->tail += hlen;
908 skb_pull(skb, MXGEFW_PAD);
909 }
910
911 static void
912 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
913 int bytes, int watchdog)
914 {
915 struct page *page;
916 int idx;
917
918 if (unlikely(rx->watchdog_needed && !watchdog))
919 return;
920
921 /* try to refill entire ring */
922 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
923 idx = rx->fill_cnt & rx->mask;
924 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
925 /* we can use part of previous page */
926 get_page(rx->page);
927 } else {
928 /* we need a new page */
929 page =
930 alloc_pages(GFP_ATOMIC | __GFP_COMP,
931 MYRI10GE_ALLOC_ORDER);
932 if (unlikely(page == NULL)) {
933 if (rx->fill_cnt - rx->cnt < 16)
934 rx->watchdog_needed = 1;
935 return;
936 }
937 rx->page = page;
938 rx->page_offset = 0;
939 rx->bus = pci_map_page(mgp->pdev, page, 0,
940 MYRI10GE_ALLOC_SIZE,
941 PCI_DMA_FROMDEVICE);
942 }
943 rx->info[idx].page = rx->page;
944 rx->info[idx].page_offset = rx->page_offset;
945 /* note that this is the address of the start of the
946 * page */
947 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
948 rx->shadow[idx].addr_low =
949 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
950 rx->shadow[idx].addr_high =
951 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
952
953 /* start next packet on a cacheline boundary */
954 rx->page_offset += SKB_DATA_ALIGN(bytes);
955
956 #if MYRI10GE_ALLOC_SIZE > 4096
957 /* don't cross a 4KB boundary */
958 if ((rx->page_offset >> 12) !=
959 ((rx->page_offset + bytes - 1) >> 12))
960 rx->page_offset = (rx->page_offset + 4096) & ~4095;
961 #endif
962 rx->fill_cnt++;
963
964 /* copy 8 descriptors to the firmware at a time */
965 if ((idx & 7) == 7) {
966 if (rx->wc_fifo == NULL)
967 myri10ge_submit_8rx(&rx->lanai[idx - 7],
968 &rx->shadow[idx - 7]);
969 else {
970 mb();
971 myri10ge_pio_copy(rx->wc_fifo,
972 &rx->shadow[idx - 7], 64);
973 }
974 }
975 }
976 }
977
978 static inline void
979 myri10ge_unmap_rx_page(struct pci_dev *pdev,
980 struct myri10ge_rx_buffer_state *info, int bytes)
981 {
982 /* unmap the recvd page if we're the only or last user of it */
983 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
984 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
985 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
986 & ~(MYRI10GE_ALLOC_SIZE - 1)),
987 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
988 }
989 }
990
991 #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
992 * page into an skb */
993
994 static inline int
995 myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
996 int bytes, int len, __wsum csum)
997 {
998 struct sk_buff *skb;
999 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1000 int i, idx, hlen, remainder;
1001 struct pci_dev *pdev = mgp->pdev;
1002 struct net_device *dev = mgp->dev;
1003 u8 *va;
1004
1005 len += MXGEFW_PAD;
1006 idx = rx->cnt & rx->mask;
1007 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1008 prefetch(va);
1009 /* Fill skb_frag_struct(s) with data from our receive */
1010 for (i = 0, remainder = len; remainder > 0; i++) {
1011 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1012 rx_frags[i].page = rx->info[idx].page;
1013 rx_frags[i].page_offset = rx->info[idx].page_offset;
1014 if (remainder < MYRI10GE_ALLOC_SIZE)
1015 rx_frags[i].size = remainder;
1016 else
1017 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1018 rx->cnt++;
1019 idx = rx->cnt & rx->mask;
1020 remainder -= MYRI10GE_ALLOC_SIZE;
1021 }
1022
1023 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1024
1025 /* allocate an skb to attach the page(s) to. */
1026
1027 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1028 if (unlikely(skb == NULL)) {
1029 mgp->stats.rx_dropped++;
1030 do {
1031 i--;
1032 put_page(rx_frags[i].page);
1033 } while (i != 0);
1034 return 0;
1035 }
1036
1037 /* Attach the pages to the skb, and trim off any padding */
1038 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1039 if (skb_shinfo(skb)->frags[0].size <= 0) {
1040 put_page(skb_shinfo(skb)->frags[0].page);
1041 skb_shinfo(skb)->nr_frags = 0;
1042 }
1043 skb->protocol = eth_type_trans(skb, dev);
1044
1045 if (mgp->csum_flag) {
1046 if ((skb->protocol == htons(ETH_P_IP)) ||
1047 (skb->protocol == htons(ETH_P_IPV6))) {
1048 skb->csum = csum;
1049 skb->ip_summed = CHECKSUM_COMPLETE;
1050 } else
1051 myri10ge_vlan_ip_csum(skb, csum);
1052 }
1053 netif_receive_skb(skb);
1054 dev->last_rx = jiffies;
1055 return 1;
1056 }
1057
1058 static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1059 {
1060 struct pci_dev *pdev = mgp->pdev;
1061 struct myri10ge_tx_buf *tx = &mgp->tx;
1062 struct sk_buff *skb;
1063 int idx, len;
1064
1065 while (tx->pkt_done != mcp_index) {
1066 idx = tx->done & tx->mask;
1067 skb = tx->info[idx].skb;
1068
1069 /* Mark as free */
1070 tx->info[idx].skb = NULL;
1071 if (tx->info[idx].last) {
1072 tx->pkt_done++;
1073 tx->info[idx].last = 0;
1074 }
1075 tx->done++;
1076 len = pci_unmap_len(&tx->info[idx], len);
1077 pci_unmap_len_set(&tx->info[idx], len, 0);
1078 if (skb) {
1079 mgp->stats.tx_bytes += skb->len;
1080 mgp->stats.tx_packets++;
1081 dev_kfree_skb_irq(skb);
1082 if (len)
1083 pci_unmap_single(pdev,
1084 pci_unmap_addr(&tx->info[idx],
1085 bus), len,
1086 PCI_DMA_TODEVICE);
1087 } else {
1088 if (len)
1089 pci_unmap_page(pdev,
1090 pci_unmap_addr(&tx->info[idx],
1091 bus), len,
1092 PCI_DMA_TODEVICE);
1093 }
1094 }
1095 /* start the queue if we've stopped it */
1096 if (netif_queue_stopped(mgp->dev)
1097 && tx->req - tx->done < (tx->mask >> 1)) {
1098 mgp->wake_queue++;
1099 netif_wake_queue(mgp->dev);
1100 }
1101 }
1102
1103 static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1104 {
1105 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1106 unsigned long rx_bytes = 0;
1107 unsigned long rx_packets = 0;
1108 unsigned long rx_ok;
1109
1110 int idx = rx_done->idx;
1111 int cnt = rx_done->cnt;
1112 u16 length;
1113 __wsum checksum;
1114
1115 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1116 length = ntohs(rx_done->entry[idx].length);
1117 rx_done->entry[idx].length = 0;
1118 checksum = csum_unfold(rx_done->entry[idx].checksum);
1119 if (length <= mgp->small_bytes)
1120 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1121 mgp->small_bytes,
1122 length, checksum);
1123 else
1124 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1125 mgp->big_bytes,
1126 length, checksum);
1127 rx_packets += rx_ok;
1128 rx_bytes += rx_ok * (unsigned long)length;
1129 cnt++;
1130 idx = cnt & (myri10ge_max_intr_slots - 1);
1131
1132 /* limit potential for livelock by only handling a
1133 * limited number of frames. */
1134 (*limit)--;
1135 }
1136 rx_done->idx = idx;
1137 rx_done->cnt = cnt;
1138 mgp->stats.rx_packets += rx_packets;
1139 mgp->stats.rx_bytes += rx_bytes;
1140
1141 /* restock receive rings if needed */
1142 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1143 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1144 mgp->small_bytes + MXGEFW_PAD, 0);
1145 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1146 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1147
1148 }
1149
1150 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1151 {
1152 struct mcp_irq_data *stats = mgp->fw_stats;
1153
1154 if (unlikely(stats->stats_updated)) {
1155 unsigned link_up = ntohl(stats->link_up);
1156 if (mgp->link_state != link_up) {
1157 mgp->link_state = link_up;
1158
1159 if (mgp->link_state == MXGEFW_LINK_UP) {
1160 if (netif_msg_link(mgp))
1161 printk(KERN_INFO
1162 "myri10ge: %s: link up\n",
1163 mgp->dev->name);
1164 netif_carrier_on(mgp->dev);
1165 mgp->link_changes++;
1166 } else {
1167 if (netif_msg_link(mgp))
1168 printk(KERN_INFO
1169 "myri10ge: %s: link %s\n",
1170 mgp->dev->name,
1171 (link_up == MXGEFW_LINK_MYRINET ?
1172 "mismatch (Myrinet detected)" :
1173 "down"));
1174 netif_carrier_off(mgp->dev);
1175 mgp->link_changes++;
1176 }
1177 }
1178 if (mgp->rdma_tags_available !=
1179 ntohl(mgp->fw_stats->rdma_tags_available)) {
1180 mgp->rdma_tags_available =
1181 ntohl(mgp->fw_stats->rdma_tags_available);
1182 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1183 "%d tags left\n", mgp->dev->name,
1184 mgp->rdma_tags_available);
1185 }
1186 mgp->down_cnt += stats->link_down;
1187 if (stats->link_down)
1188 wake_up(&mgp->down_wq);
1189 }
1190 }
1191
1192 static int myri10ge_poll(struct net_device *netdev, int *budget)
1193 {
1194 struct myri10ge_priv *mgp = netdev_priv(netdev);
1195 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1196 int limit, orig_limit, work_done;
1197
1198 /* process as many rx events as NAPI will allow */
1199 limit = min(*budget, netdev->quota);
1200 orig_limit = limit;
1201 myri10ge_clean_rx_done(mgp, &limit);
1202 work_done = orig_limit - limit;
1203 *budget -= work_done;
1204 netdev->quota -= work_done;
1205
1206 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1207 netif_rx_complete(netdev);
1208 put_be32(htonl(3), mgp->irq_claim);
1209 return 0;
1210 }
1211 return 1;
1212 }
1213
1214 static irqreturn_t myri10ge_intr(int irq, void *arg)
1215 {
1216 struct myri10ge_priv *mgp = arg;
1217 struct mcp_irq_data *stats = mgp->fw_stats;
1218 struct myri10ge_tx_buf *tx = &mgp->tx;
1219 u32 send_done_count;
1220 int i;
1221
1222 /* make sure it is our IRQ, and that the DMA has finished */
1223 if (unlikely(!stats->valid))
1224 return (IRQ_NONE);
1225
1226 /* low bit indicates receives are present, so schedule
1227 * napi poll handler */
1228 if (stats->valid & 1)
1229 netif_rx_schedule(mgp->dev);
1230
1231 if (!mgp->msi_enabled) {
1232 put_be32(0, mgp->irq_deassert);
1233 if (!myri10ge_deassert_wait)
1234 stats->valid = 0;
1235 mb();
1236 } else
1237 stats->valid = 0;
1238
1239 /* Wait for IRQ line to go low, if using INTx */
1240 i = 0;
1241 while (1) {
1242 i++;
1243 /* check for transmit completes and receives */
1244 send_done_count = ntohl(stats->send_done_count);
1245 if (send_done_count != tx->pkt_done)
1246 myri10ge_tx_done(mgp, (int)send_done_count);
1247 if (unlikely(i > myri10ge_max_irq_loops)) {
1248 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1249 mgp->dev->name);
1250 stats->valid = 0;
1251 schedule_work(&mgp->watchdog_work);
1252 }
1253 if (likely(stats->valid == 0))
1254 break;
1255 cpu_relax();
1256 barrier();
1257 }
1258
1259 myri10ge_check_statblock(mgp);
1260
1261 put_be32(htonl(3), mgp->irq_claim + 1);
1262 return (IRQ_HANDLED);
1263 }
1264
1265 static int
1266 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1267 {
1268 cmd->autoneg = AUTONEG_DISABLE;
1269 cmd->speed = SPEED_10000;
1270 cmd->duplex = DUPLEX_FULL;
1271 return 0;
1272 }
1273
1274 static void
1275 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1276 {
1277 struct myri10ge_priv *mgp = netdev_priv(netdev);
1278
1279 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1280 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1281 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1282 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1283 }
1284
1285 static int
1286 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1287 {
1288 struct myri10ge_priv *mgp = netdev_priv(netdev);
1289 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1290 return 0;
1291 }
1292
1293 static int
1294 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1295 {
1296 struct myri10ge_priv *mgp = netdev_priv(netdev);
1297
1298 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1299 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1300 return 0;
1301 }
1302
1303 static void
1304 myri10ge_get_pauseparam(struct net_device *netdev,
1305 struct ethtool_pauseparam *pause)
1306 {
1307 struct myri10ge_priv *mgp = netdev_priv(netdev);
1308
1309 pause->autoneg = 0;
1310 pause->rx_pause = mgp->pause;
1311 pause->tx_pause = mgp->pause;
1312 }
1313
1314 static int
1315 myri10ge_set_pauseparam(struct net_device *netdev,
1316 struct ethtool_pauseparam *pause)
1317 {
1318 struct myri10ge_priv *mgp = netdev_priv(netdev);
1319
1320 if (pause->tx_pause != mgp->pause)
1321 return myri10ge_change_pause(mgp, pause->tx_pause);
1322 if (pause->rx_pause != mgp->pause)
1323 return myri10ge_change_pause(mgp, pause->tx_pause);
1324 if (pause->autoneg != 0)
1325 return -EINVAL;
1326 return 0;
1327 }
1328
1329 static void
1330 myri10ge_get_ringparam(struct net_device *netdev,
1331 struct ethtool_ringparam *ring)
1332 {
1333 struct myri10ge_priv *mgp = netdev_priv(netdev);
1334
1335 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1336 ring->rx_max_pending = mgp->rx_big.mask + 1;
1337 ring->rx_jumbo_max_pending = 0;
1338 ring->tx_max_pending = mgp->rx_small.mask + 1;
1339 ring->rx_mini_pending = ring->rx_mini_max_pending;
1340 ring->rx_pending = ring->rx_max_pending;
1341 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1342 ring->tx_pending = ring->tx_max_pending;
1343 }
1344
1345 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1346 {
1347 struct myri10ge_priv *mgp = netdev_priv(netdev);
1348 if (mgp->csum_flag)
1349 return 1;
1350 else
1351 return 0;
1352 }
1353
1354 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1355 {
1356 struct myri10ge_priv *mgp = netdev_priv(netdev);
1357 if (csum_enabled)
1358 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1359 else
1360 mgp->csum_flag = 0;
1361 return 0;
1362 }
1363
1364 static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1365 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1366 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1367 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1368 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1369 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1370 "tx_heartbeat_errors", "tx_window_errors",
1371 /* device-specific stats */
1372 "tx_boundary", "WC", "irq", "MSI",
1373 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1374 "serial_number", "tx_pkt_start", "tx_pkt_done",
1375 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1376 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
1377 "link_changes", "link_up", "dropped_link_overflow",
1378 "dropped_link_error_or_filtered",
1379 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1380 "dropped_unicast_filtered", "dropped_multicast_filtered",
1381 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1382 "dropped_no_big_buffer"
1383 };
1384
1385 #define MYRI10GE_NET_STATS_LEN 21
1386 #define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1387
1388 static void
1389 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1390 {
1391 switch (stringset) {
1392 case ETH_SS_STATS:
1393 memcpy(data, *myri10ge_gstrings_stats,
1394 sizeof(myri10ge_gstrings_stats));
1395 break;
1396 }
1397 }
1398
1399 static int myri10ge_get_stats_count(struct net_device *netdev)
1400 {
1401 return MYRI10GE_STATS_LEN;
1402 }
1403
1404 static void
1405 myri10ge_get_ethtool_stats(struct net_device *netdev,
1406 struct ethtool_stats *stats, u64 * data)
1407 {
1408 struct myri10ge_priv *mgp = netdev_priv(netdev);
1409 int i;
1410
1411 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1412 data[i] = ((unsigned long *)&mgp->stats)[i];
1413
1414 data[i++] = (unsigned int)mgp->tx.boundary;
1415 data[i++] = (unsigned int)mgp->wc_enabled;
1416 data[i++] = (unsigned int)mgp->pdev->irq;
1417 data[i++] = (unsigned int)mgp->msi_enabled;
1418 data[i++] = (unsigned int)mgp->read_dma;
1419 data[i++] = (unsigned int)mgp->write_dma;
1420 data[i++] = (unsigned int)mgp->read_write_dma;
1421 data[i++] = (unsigned int)mgp->serial_number;
1422 data[i++] = (unsigned int)mgp->tx.pkt_start;
1423 data[i++] = (unsigned int)mgp->tx.pkt_done;
1424 data[i++] = (unsigned int)mgp->tx.req;
1425 data[i++] = (unsigned int)mgp->tx.done;
1426 data[i++] = (unsigned int)mgp->rx_small.cnt;
1427 data[i++] = (unsigned int)mgp->rx_big.cnt;
1428 data[i++] = (unsigned int)mgp->wake_queue;
1429 data[i++] = (unsigned int)mgp->stop_queue;
1430 data[i++] = (unsigned int)mgp->watchdog_resets;
1431 data[i++] = (unsigned int)mgp->tx_linearized;
1432 data[i++] = (unsigned int)mgp->link_changes;
1433 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1434 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1435 data[i++] =
1436 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
1437 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_pause);
1438 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_phy);
1439 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_crc32);
1440 data[i++] =
1441 (unsigned int)ntohl(mgp->fw_stats->dropped_unicast_filtered);
1442 data[i++] =
1443 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
1444 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1445 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1446 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1447 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1448 }
1449
1450 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1451 {
1452 struct myri10ge_priv *mgp = netdev_priv(netdev);
1453 mgp->msg_enable = value;
1454 }
1455
1456 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1457 {
1458 struct myri10ge_priv *mgp = netdev_priv(netdev);
1459 return mgp->msg_enable;
1460 }
1461
1462 static const struct ethtool_ops myri10ge_ethtool_ops = {
1463 .get_settings = myri10ge_get_settings,
1464 .get_drvinfo = myri10ge_get_drvinfo,
1465 .get_coalesce = myri10ge_get_coalesce,
1466 .set_coalesce = myri10ge_set_coalesce,
1467 .get_pauseparam = myri10ge_get_pauseparam,
1468 .set_pauseparam = myri10ge_set_pauseparam,
1469 .get_ringparam = myri10ge_get_ringparam,
1470 .get_rx_csum = myri10ge_get_rx_csum,
1471 .set_rx_csum = myri10ge_set_rx_csum,
1472 .get_tx_csum = ethtool_op_get_tx_csum,
1473 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1474 .get_sg = ethtool_op_get_sg,
1475 .set_sg = ethtool_op_set_sg,
1476 .get_tso = ethtool_op_get_tso,
1477 .set_tso = ethtool_op_set_tso,
1478 .get_link = ethtool_op_get_link,
1479 .get_strings = myri10ge_get_strings,
1480 .get_stats_count = myri10ge_get_stats_count,
1481 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1482 .set_msglevel = myri10ge_set_msglevel,
1483 .get_msglevel = myri10ge_get_msglevel
1484 };
1485
1486 static int myri10ge_allocate_rings(struct net_device *dev)
1487 {
1488 struct myri10ge_priv *mgp;
1489 struct myri10ge_cmd cmd;
1490 int tx_ring_size, rx_ring_size;
1491 int tx_ring_entries, rx_ring_entries;
1492 int i, status;
1493 size_t bytes;
1494
1495 mgp = netdev_priv(dev);
1496
1497 /* get ring sizes */
1498
1499 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1500 tx_ring_size = cmd.data0;
1501 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1502 if (status != 0)
1503 return status;
1504 rx_ring_size = cmd.data0;
1505
1506 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1507 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1508 mgp->tx.mask = tx_ring_entries - 1;
1509 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1510
1511 status = -ENOMEM;
1512
1513 /* allocate the host shadow rings */
1514
1515 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1516 * sizeof(*mgp->tx.req_list);
1517 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1518 if (mgp->tx.req_bytes == NULL)
1519 goto abort_with_nothing;
1520
1521 /* ensure req_list entries are aligned to 8 bytes */
1522 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1523 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1524
1525 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1526 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1527 if (mgp->rx_small.shadow == NULL)
1528 goto abort_with_tx_req_bytes;
1529
1530 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1531 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1532 if (mgp->rx_big.shadow == NULL)
1533 goto abort_with_rx_small_shadow;
1534
1535 /* allocate the host info rings */
1536
1537 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1538 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1539 if (mgp->tx.info == NULL)
1540 goto abort_with_rx_big_shadow;
1541
1542 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1543 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1544 if (mgp->rx_small.info == NULL)
1545 goto abort_with_tx_info;
1546
1547 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1548 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1549 if (mgp->rx_big.info == NULL)
1550 goto abort_with_rx_small_info;
1551
1552 /* Fill the receive rings */
1553 mgp->rx_big.cnt = 0;
1554 mgp->rx_small.cnt = 0;
1555 mgp->rx_big.fill_cnt = 0;
1556 mgp->rx_small.fill_cnt = 0;
1557 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1558 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1559 mgp->rx_small.watchdog_needed = 0;
1560 mgp->rx_big.watchdog_needed = 0;
1561 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1562 mgp->small_bytes + MXGEFW_PAD, 0);
1563
1564 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1565 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1566 dev->name, mgp->rx_small.fill_cnt);
1567 goto abort_with_rx_small_ring;
1568 }
1569
1570 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1571 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1572 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1573 dev->name, mgp->rx_big.fill_cnt);
1574 goto abort_with_rx_big_ring;
1575 }
1576
1577 return 0;
1578
1579 abort_with_rx_big_ring:
1580 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1581 int idx = i & mgp->rx_big.mask;
1582 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1583 mgp->big_bytes);
1584 put_page(mgp->rx_big.info[idx].page);
1585 }
1586
1587 abort_with_rx_small_ring:
1588 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1589 int idx = i & mgp->rx_small.mask;
1590 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1591 mgp->small_bytes + MXGEFW_PAD);
1592 put_page(mgp->rx_small.info[idx].page);
1593 }
1594
1595 kfree(mgp->rx_big.info);
1596
1597 abort_with_rx_small_info:
1598 kfree(mgp->rx_small.info);
1599
1600 abort_with_tx_info:
1601 kfree(mgp->tx.info);
1602
1603 abort_with_rx_big_shadow:
1604 kfree(mgp->rx_big.shadow);
1605
1606 abort_with_rx_small_shadow:
1607 kfree(mgp->rx_small.shadow);
1608
1609 abort_with_tx_req_bytes:
1610 kfree(mgp->tx.req_bytes);
1611 mgp->tx.req_bytes = NULL;
1612 mgp->tx.req_list = NULL;
1613
1614 abort_with_nothing:
1615 return status;
1616 }
1617
1618 static void myri10ge_free_rings(struct net_device *dev)
1619 {
1620 struct myri10ge_priv *mgp;
1621 struct sk_buff *skb;
1622 struct myri10ge_tx_buf *tx;
1623 int i, len, idx;
1624
1625 mgp = netdev_priv(dev);
1626
1627 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1628 idx = i & mgp->rx_big.mask;
1629 if (i == mgp->rx_big.fill_cnt - 1)
1630 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1631 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1632 mgp->big_bytes);
1633 put_page(mgp->rx_big.info[idx].page);
1634 }
1635
1636 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1637 idx = i & mgp->rx_small.mask;
1638 if (i == mgp->rx_small.fill_cnt - 1)
1639 mgp->rx_small.info[idx].page_offset =
1640 MYRI10GE_ALLOC_SIZE;
1641 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1642 mgp->small_bytes + MXGEFW_PAD);
1643 put_page(mgp->rx_small.info[idx].page);
1644 }
1645 tx = &mgp->tx;
1646 while (tx->done != tx->req) {
1647 idx = tx->done & tx->mask;
1648 skb = tx->info[idx].skb;
1649
1650 /* Mark as free */
1651 tx->info[idx].skb = NULL;
1652 tx->done++;
1653 len = pci_unmap_len(&tx->info[idx], len);
1654 pci_unmap_len_set(&tx->info[idx], len, 0);
1655 if (skb) {
1656 mgp->stats.tx_dropped++;
1657 dev_kfree_skb_any(skb);
1658 if (len)
1659 pci_unmap_single(mgp->pdev,
1660 pci_unmap_addr(&tx->info[idx],
1661 bus), len,
1662 PCI_DMA_TODEVICE);
1663 } else {
1664 if (len)
1665 pci_unmap_page(mgp->pdev,
1666 pci_unmap_addr(&tx->info[idx],
1667 bus), len,
1668 PCI_DMA_TODEVICE);
1669 }
1670 }
1671 kfree(mgp->rx_big.info);
1672
1673 kfree(mgp->rx_small.info);
1674
1675 kfree(mgp->tx.info);
1676
1677 kfree(mgp->rx_big.shadow);
1678
1679 kfree(mgp->rx_small.shadow);
1680
1681 kfree(mgp->tx.req_bytes);
1682 mgp->tx.req_bytes = NULL;
1683 mgp->tx.req_list = NULL;
1684 }
1685
1686 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1687 {
1688 struct pci_dev *pdev = mgp->pdev;
1689 int status;
1690
1691 if (myri10ge_msi) {
1692 status = pci_enable_msi(pdev);
1693 if (status != 0)
1694 dev_err(&pdev->dev,
1695 "Error %d setting up MSI; falling back to xPIC\n",
1696 status);
1697 else
1698 mgp->msi_enabled = 1;
1699 } else {
1700 mgp->msi_enabled = 0;
1701 }
1702 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1703 mgp->dev->name, mgp);
1704 if (status != 0) {
1705 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1706 if (mgp->msi_enabled)
1707 pci_disable_msi(pdev);
1708 }
1709 return status;
1710 }
1711
1712 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1713 {
1714 struct pci_dev *pdev = mgp->pdev;
1715
1716 free_irq(pdev->irq, mgp);
1717 if (mgp->msi_enabled)
1718 pci_disable_msi(pdev);
1719 }
1720
1721 static int myri10ge_open(struct net_device *dev)
1722 {
1723 struct myri10ge_priv *mgp;
1724 struct myri10ge_cmd cmd;
1725 int status, big_pow2;
1726
1727 mgp = netdev_priv(dev);
1728
1729 if (mgp->running != MYRI10GE_ETH_STOPPED)
1730 return -EBUSY;
1731
1732 mgp->running = MYRI10GE_ETH_STARTING;
1733 status = myri10ge_reset(mgp);
1734 if (status != 0) {
1735 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
1736 goto abort_with_nothing;
1737 }
1738
1739 status = myri10ge_request_irq(mgp);
1740 if (status != 0)
1741 goto abort_with_nothing;
1742
1743 /* decide what small buffer size to use. For good TCP rx
1744 * performance, it is important to not receive 1514 byte
1745 * frames into jumbo buffers, as it confuses the socket buffer
1746 * accounting code, leading to drops and erratic performance.
1747 */
1748
1749 if (dev->mtu <= ETH_DATA_LEN)
1750 /* enough for a TCP header */
1751 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1752 ? (128 - MXGEFW_PAD)
1753 : (SMP_CACHE_BYTES - MXGEFW_PAD);
1754 else
1755 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1756 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
1757
1758 /* Override the small buffer size? */
1759 if (myri10ge_small_bytes > 0)
1760 mgp->small_bytes = myri10ge_small_bytes;
1761
1762 /* get the lanai pointers to the send and receive rings */
1763
1764 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1765 mgp->tx.lanai =
1766 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1767
1768 status |=
1769 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1770 mgp->rx_small.lanai =
1771 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1772
1773 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1774 mgp->rx_big.lanai =
1775 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1776
1777 if (status != 0) {
1778 printk(KERN_ERR
1779 "myri10ge: %s: failed to get ring sizes or locations\n",
1780 dev->name);
1781 mgp->running = MYRI10GE_ETH_STOPPED;
1782 goto abort_with_irq;
1783 }
1784
1785 if (myri10ge_wcfifo && mgp->wc_enabled) {
1786 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1787 mgp->rx_small.wc_fifo =
1788 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1789 mgp->rx_big.wc_fifo =
1790 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
1791 } else {
1792 mgp->tx.wc_fifo = NULL;
1793 mgp->rx_small.wc_fifo = NULL;
1794 mgp->rx_big.wc_fifo = NULL;
1795 }
1796
1797 /* Firmware needs the big buff size as a power of 2. Lie and
1798 * tell him the buffer is larger, because we only use 1
1799 * buffer/pkt, and the mtu will prevent overruns.
1800 */
1801 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
1802 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
1803 while (!is_power_of_2(big_pow2))
1804 big_pow2++;
1805 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
1806 } else {
1807 big_pow2 = MYRI10GE_ALLOC_SIZE;
1808 mgp->big_bytes = big_pow2;
1809 }
1810
1811 status = myri10ge_allocate_rings(dev);
1812 if (status != 0)
1813 goto abort_with_irq;
1814
1815 /* now give firmware buffers sizes, and MTU */
1816 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1817 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1818 cmd.data0 = mgp->small_bytes;
1819 status |=
1820 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1821 cmd.data0 = big_pow2;
1822 status |=
1823 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1824 if (status) {
1825 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1826 dev->name);
1827 goto abort_with_rings;
1828 }
1829
1830 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1831 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
1832 cmd.data2 = sizeof(struct mcp_irq_data);
1833 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1834 if (status == -ENOSYS) {
1835 dma_addr_t bus = mgp->fw_stats_bus;
1836 bus += offsetof(struct mcp_irq_data, send_done_count);
1837 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1838 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1839 status = myri10ge_send_cmd(mgp,
1840 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1841 &cmd, 0);
1842 /* Firmware cannot support multicast without STATS_DMA_V2 */
1843 mgp->fw_multicast_support = 0;
1844 } else {
1845 mgp->fw_multicast_support = 1;
1846 }
1847 if (status) {
1848 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1849 dev->name);
1850 goto abort_with_rings;
1851 }
1852
1853 mgp->link_state = htonl(~0U);
1854 mgp->rdma_tags_available = 15;
1855
1856 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1857
1858 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1859 if (status) {
1860 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1861 dev->name);
1862 goto abort_with_rings;
1863 }
1864
1865 mgp->wake_queue = 0;
1866 mgp->stop_queue = 0;
1867 mgp->running = MYRI10GE_ETH_RUNNING;
1868 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1869 add_timer(&mgp->watchdog_timer);
1870 netif_wake_queue(dev);
1871 return 0;
1872
1873 abort_with_rings:
1874 myri10ge_free_rings(dev);
1875
1876 abort_with_irq:
1877 myri10ge_free_irq(mgp);
1878
1879 abort_with_nothing:
1880 mgp->running = MYRI10GE_ETH_STOPPED;
1881 return -ENOMEM;
1882 }
1883
1884 static int myri10ge_close(struct net_device *dev)
1885 {
1886 struct myri10ge_priv *mgp;
1887 struct myri10ge_cmd cmd;
1888 int status, old_down_cnt;
1889
1890 mgp = netdev_priv(dev);
1891
1892 if (mgp->running != MYRI10GE_ETH_RUNNING)
1893 return 0;
1894
1895 if (mgp->tx.req_bytes == NULL)
1896 return 0;
1897
1898 del_timer_sync(&mgp->watchdog_timer);
1899 mgp->running = MYRI10GE_ETH_STOPPING;
1900 netif_poll_disable(mgp->dev);
1901 netif_carrier_off(dev);
1902 netif_stop_queue(dev);
1903 old_down_cnt = mgp->down_cnt;
1904 mb();
1905 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1906 if (status)
1907 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1908 dev->name);
1909
1910 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1911 if (old_down_cnt == mgp->down_cnt)
1912 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1913
1914 netif_tx_disable(dev);
1915 myri10ge_free_irq(mgp);
1916 myri10ge_free_rings(dev);
1917
1918 mgp->running = MYRI10GE_ETH_STOPPED;
1919 return 0;
1920 }
1921
1922 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1923 * backwards one at a time and handle ring wraps */
1924
1925 static inline void
1926 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1927 struct mcp_kreq_ether_send *src, int cnt)
1928 {
1929 int idx, starting_slot;
1930 starting_slot = tx->req;
1931 while (cnt > 1) {
1932 cnt--;
1933 idx = (starting_slot + cnt) & tx->mask;
1934 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1935 mb();
1936 }
1937 }
1938
1939 /*
1940 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1941 * at most 32 bytes at a time, so as to avoid involving the software
1942 * pio handler in the nic. We re-write the first segment's flags
1943 * to mark them valid only after writing the entire chain.
1944 */
1945
1946 static inline void
1947 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1948 int cnt)
1949 {
1950 int idx, i;
1951 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1952 struct mcp_kreq_ether_send *srcp;
1953 u8 last_flags;
1954
1955 idx = tx->req & tx->mask;
1956
1957 last_flags = src->flags;
1958 src->flags = 0;
1959 mb();
1960 dst = dstp = &tx->lanai[idx];
1961 srcp = src;
1962
1963 if ((idx + cnt) < tx->mask) {
1964 for (i = 0; i < (cnt - 1); i += 2) {
1965 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1966 mb(); /* force write every 32 bytes */
1967 srcp += 2;
1968 dstp += 2;
1969 }
1970 } else {
1971 /* submit all but the first request, and ensure
1972 * that it is submitted below */
1973 myri10ge_submit_req_backwards(tx, src, cnt);
1974 i = 0;
1975 }
1976 if (i < cnt) {
1977 /* submit the first request */
1978 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1979 mb(); /* barrier before setting valid flag */
1980 }
1981
1982 /* re-write the last 32-bits with the valid flags */
1983 src->flags = last_flags;
1984 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
1985 tx->req += cnt;
1986 mb();
1987 }
1988
1989 static inline void
1990 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1991 struct mcp_kreq_ether_send *src, int cnt)
1992 {
1993 tx->req += cnt;
1994 mb();
1995 while (cnt >= 4) {
1996 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1997 mb();
1998 src += 4;
1999 cnt -= 4;
2000 }
2001 if (cnt > 0) {
2002 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2003 * needs to be so that we don't overrun it */
2004 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2005 src, 64);
2006 mb();
2007 }
2008 }
2009
2010 /*
2011 * Transmit a packet. We need to split the packet so that a single
2012 * segment does not cross myri10ge->tx.boundary, so this makes segment
2013 * counting tricky. So rather than try to count segments up front, we
2014 * just give up if there are too few segments to hold a reasonably
2015 * fragmented packet currently available. If we run
2016 * out of segments while preparing a packet for DMA, we just linearize
2017 * it and try again.
2018 */
2019
2020 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2021 {
2022 struct myri10ge_priv *mgp = netdev_priv(dev);
2023 struct mcp_kreq_ether_send *req;
2024 struct myri10ge_tx_buf *tx = &mgp->tx;
2025 struct skb_frag_struct *frag;
2026 dma_addr_t bus;
2027 u32 low;
2028 __be32 high_swapped;
2029 unsigned int len;
2030 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2031 u16 pseudo_hdr_offset, cksum_offset;
2032 int cum_len, seglen, boundary, rdma_count;
2033 u8 flags, odd_flag;
2034
2035 again:
2036 req = tx->req_list;
2037 avail = tx->mask - 1 - (tx->req - tx->done);
2038
2039 mss = 0;
2040 max_segments = MXGEFW_MAX_SEND_DESC;
2041
2042 if (skb_is_gso(skb)) {
2043 mss = skb_shinfo(skb)->gso_size;
2044 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2045 }
2046
2047 if ((unlikely(avail < max_segments))) {
2048 /* we are out of transmit resources */
2049 mgp->stop_queue++;
2050 netif_stop_queue(dev);
2051 return 1;
2052 }
2053
2054 /* Setup checksum offloading, if needed */
2055 cksum_offset = 0;
2056 pseudo_hdr_offset = 0;
2057 odd_flag = 0;
2058 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2059 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2060 cksum_offset = skb_transport_offset(skb);
2061 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2062 /* If the headers are excessively large, then we must
2063 * fall back to a software checksum */
2064 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
2065 if (skb_checksum_help(skb))
2066 goto drop;
2067 cksum_offset = 0;
2068 pseudo_hdr_offset = 0;
2069 } else {
2070 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2071 flags |= MXGEFW_FLAGS_CKSUM;
2072 }
2073 }
2074
2075 cum_len = 0;
2076
2077 if (mss) { /* TSO */
2078 /* this removes any CKSUM flag from before */
2079 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2080
2081 /* negative cum_len signifies to the
2082 * send loop that we are still in the
2083 * header portion of the TSO packet.
2084 * TSO header must be at most 134 bytes long */
2085 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2086
2087 /* for TSO, pseudo_hdr_offset holds mss.
2088 * The firmware figures out where to put
2089 * the checksum by parsing the header. */
2090 pseudo_hdr_offset = mss;
2091 } else
2092 /* Mark small packets, and pad out tiny packets */
2093 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2094 flags |= MXGEFW_FLAGS_SMALL;
2095
2096 /* pad frames to at least ETH_ZLEN bytes */
2097 if (unlikely(skb->len < ETH_ZLEN)) {
2098 if (skb_padto(skb, ETH_ZLEN)) {
2099 /* The packet is gone, so we must
2100 * return 0 */
2101 mgp->stats.tx_dropped += 1;
2102 return 0;
2103 }
2104 /* adjust the len to account for the zero pad
2105 * so that the nic can know how long it is */
2106 skb->len = ETH_ZLEN;
2107 }
2108 }
2109
2110 /* map the skb for DMA */
2111 len = skb->len - skb->data_len;
2112 idx = tx->req & tx->mask;
2113 tx->info[idx].skb = skb;
2114 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2115 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2116 pci_unmap_len_set(&tx->info[idx], len, len);
2117
2118 frag_cnt = skb_shinfo(skb)->nr_frags;
2119 frag_idx = 0;
2120 count = 0;
2121 rdma_count = 0;
2122
2123 /* "rdma_count" is the number of RDMAs belonging to the
2124 * current packet BEFORE the current send request. For
2125 * non-TSO packets, this is equal to "count".
2126 * For TSO packets, rdma_count needs to be reset
2127 * to 0 after a segment cut.
2128 *
2129 * The rdma_count field of the send request is
2130 * the number of RDMAs of the packet starting at
2131 * that request. For TSO send requests with one ore more cuts
2132 * in the middle, this is the number of RDMAs starting
2133 * after the last cut in the request. All previous
2134 * segments before the last cut implicitly have 1 RDMA.
2135 *
2136 * Since the number of RDMAs is not known beforehand,
2137 * it must be filled-in retroactively - after each
2138 * segmentation cut or at the end of the entire packet.
2139 */
2140
2141 while (1) {
2142 /* Break the SKB or Fragment up into pieces which
2143 * do not cross mgp->tx.boundary */
2144 low = MYRI10GE_LOWPART_TO_U32(bus);
2145 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2146 while (len) {
2147 u8 flags_next;
2148 int cum_len_next;
2149
2150 if (unlikely(count == max_segments))
2151 goto abort_linearize;
2152
2153 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2154 seglen = boundary - low;
2155 if (seglen > len)
2156 seglen = len;
2157 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2158 cum_len_next = cum_len + seglen;
2159 if (mss) { /* TSO */
2160 (req - rdma_count)->rdma_count = rdma_count + 1;
2161
2162 if (likely(cum_len >= 0)) { /* payload */
2163 int next_is_first, chop;
2164
2165 chop = (cum_len_next > mss);
2166 cum_len_next = cum_len_next % mss;
2167 next_is_first = (cum_len_next == 0);
2168 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2169 flags_next |= next_is_first *
2170 MXGEFW_FLAGS_FIRST;
2171 rdma_count |= -(chop | next_is_first);
2172 rdma_count += chop & !next_is_first;
2173 } else if (likely(cum_len_next >= 0)) { /* header ends */
2174 int small;
2175
2176 rdma_count = -1;
2177 cum_len_next = 0;
2178 seglen = -cum_len;
2179 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2180 flags_next = MXGEFW_FLAGS_TSO_PLD |
2181 MXGEFW_FLAGS_FIRST |
2182 (small * MXGEFW_FLAGS_SMALL);
2183 }
2184 }
2185 req->addr_high = high_swapped;
2186 req->addr_low = htonl(low);
2187 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2188 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2189 req->rdma_count = 1;
2190 req->length = htons(seglen);
2191 req->cksum_offset = cksum_offset;
2192 req->flags = flags | ((cum_len & 1) * odd_flag);
2193
2194 low += seglen;
2195 len -= seglen;
2196 cum_len = cum_len_next;
2197 flags = flags_next;
2198 req++;
2199 count++;
2200 rdma_count++;
2201 if (unlikely(cksum_offset > seglen))
2202 cksum_offset -= seglen;
2203 else
2204 cksum_offset = 0;
2205 }
2206 if (frag_idx == frag_cnt)
2207 break;
2208
2209 /* map next fragment for DMA */
2210 idx = (count + tx->req) & tx->mask;
2211 frag = &skb_shinfo(skb)->frags[frag_idx];
2212 frag_idx++;
2213 len = frag->size;
2214 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2215 len, PCI_DMA_TODEVICE);
2216 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2217 pci_unmap_len_set(&tx->info[idx], len, len);
2218 }
2219
2220 (req - rdma_count)->rdma_count = rdma_count;
2221 if (mss)
2222 do {
2223 req--;
2224 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2225 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2226 MXGEFW_FLAGS_FIRST)));
2227 idx = ((count - 1) + tx->req) & tx->mask;
2228 tx->info[idx].last = 1;
2229 if (tx->wc_fifo == NULL)
2230 myri10ge_submit_req(tx, tx->req_list, count);
2231 else
2232 myri10ge_submit_req_wc(tx, tx->req_list, count);
2233 tx->pkt_start++;
2234 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2235 mgp->stop_queue++;
2236 netif_stop_queue(dev);
2237 }
2238 dev->trans_start = jiffies;
2239 return 0;
2240
2241 abort_linearize:
2242 /* Free any DMA resources we've alloced and clear out the skb
2243 * slot so as to not trip up assertions, and to avoid a
2244 * double-free if linearizing fails */
2245
2246 last_idx = (idx + 1) & tx->mask;
2247 idx = tx->req & tx->mask;
2248 tx->info[idx].skb = NULL;
2249 do {
2250 len = pci_unmap_len(&tx->info[idx], len);
2251 if (len) {
2252 if (tx->info[idx].skb != NULL)
2253 pci_unmap_single(mgp->pdev,
2254 pci_unmap_addr(&tx->info[idx],
2255 bus), len,
2256 PCI_DMA_TODEVICE);
2257 else
2258 pci_unmap_page(mgp->pdev,
2259 pci_unmap_addr(&tx->info[idx],
2260 bus), len,
2261 PCI_DMA_TODEVICE);
2262 pci_unmap_len_set(&tx->info[idx], len, 0);
2263 tx->info[idx].skb = NULL;
2264 }
2265 idx = (idx + 1) & tx->mask;
2266 } while (idx != last_idx);
2267 if (skb_is_gso(skb)) {
2268 printk(KERN_ERR
2269 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2270 mgp->dev->name);
2271 goto drop;
2272 }
2273
2274 if (skb_linearize(skb))
2275 goto drop;
2276
2277 mgp->tx_linearized++;
2278 goto again;
2279
2280 drop:
2281 dev_kfree_skb_any(skb);
2282 mgp->stats.tx_dropped += 1;
2283 return 0;
2284
2285 }
2286
2287 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2288 {
2289 struct myri10ge_priv *mgp = netdev_priv(dev);
2290 return &mgp->stats;
2291 }
2292
2293 static void myri10ge_set_multicast_list(struct net_device *dev)
2294 {
2295 struct myri10ge_cmd cmd;
2296 struct myri10ge_priv *mgp;
2297 struct dev_mc_list *mc_list;
2298 __be32 data[2] = { 0, 0 };
2299 int err;
2300
2301 mgp = netdev_priv(dev);
2302 /* can be called from atomic contexts,
2303 * pass 1 to force atomicity in myri10ge_send_cmd() */
2304 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2305
2306 /* This firmware is known to not support multicast */
2307 if (!mgp->fw_multicast_support)
2308 return;
2309
2310 /* Disable multicast filtering */
2311
2312 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2313 if (err != 0) {
2314 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2315 " error status: %d\n", dev->name, err);
2316 goto abort;
2317 }
2318
2319 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
2320 /* request to disable multicast filtering, so quit here */
2321 return;
2322 }
2323
2324 /* Flush the filters */
2325
2326 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2327 &cmd, 1);
2328 if (err != 0) {
2329 printk(KERN_ERR
2330 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2331 ", error status: %d\n", dev->name, err);
2332 goto abort;
2333 }
2334
2335 /* Walk the multicast list, and add each address */
2336 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
2337 memcpy(data, &mc_list->dmi_addr, 6);
2338 cmd.data0 = ntohl(data[0]);
2339 cmd.data1 = ntohl(data[1]);
2340 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2341 &cmd, 1);
2342
2343 if (err != 0) {
2344 printk(KERN_ERR "myri10ge: %s: Failed "
2345 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2346 "%d\t", dev->name, err);
2347 printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
2348 ((unsigned char *)&mc_list->dmi_addr)[0],
2349 ((unsigned char *)&mc_list->dmi_addr)[1],
2350 ((unsigned char *)&mc_list->dmi_addr)[2],
2351 ((unsigned char *)&mc_list->dmi_addr)[3],
2352 ((unsigned char *)&mc_list->dmi_addr)[4],
2353 ((unsigned char *)&mc_list->dmi_addr)[5]
2354 );
2355 goto abort;
2356 }
2357 }
2358 /* Enable multicast filtering */
2359 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2360 if (err != 0) {
2361 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2362 "error status: %d\n", dev->name, err);
2363 goto abort;
2364 }
2365
2366 return;
2367
2368 abort:
2369 return;
2370 }
2371
2372 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2373 {
2374 struct sockaddr *sa = addr;
2375 struct myri10ge_priv *mgp = netdev_priv(dev);
2376 int status;
2377
2378 if (!is_valid_ether_addr(sa->sa_data))
2379 return -EADDRNOTAVAIL;
2380
2381 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2382 if (status != 0) {
2383 printk(KERN_ERR
2384 "myri10ge: %s: changing mac address failed with %d\n",
2385 dev->name, status);
2386 return status;
2387 }
2388
2389 /* change the dev structure */
2390 memcpy(dev->dev_addr, sa->sa_data, 6);
2391 return 0;
2392 }
2393
2394 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2395 {
2396 struct myri10ge_priv *mgp = netdev_priv(dev);
2397 int error = 0;
2398
2399 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2400 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2401 dev->name, new_mtu);
2402 return -EINVAL;
2403 }
2404 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2405 dev->name, dev->mtu, new_mtu);
2406 if (mgp->running) {
2407 /* if we change the mtu on an active device, we must
2408 * reset the device so the firmware sees the change */
2409 myri10ge_close(dev);
2410 dev->mtu = new_mtu;
2411 myri10ge_open(dev);
2412 } else
2413 dev->mtu = new_mtu;
2414
2415 return error;
2416 }
2417
2418 /*
2419 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2420 * Only do it if the bridge is a root port since we don't want to disturb
2421 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2422 */
2423
2424 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2425 {
2426 struct pci_dev *bridge = mgp->pdev->bus->self;
2427 struct device *dev = &mgp->pdev->dev;
2428 unsigned cap;
2429 unsigned err_cap;
2430 u16 val;
2431 u8 ext_type;
2432 int ret;
2433
2434 if (!myri10ge_ecrc_enable || !bridge)
2435 return;
2436
2437 /* check that the bridge is a root port */
2438 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2439 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2440 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2441 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2442 if (myri10ge_ecrc_enable > 1) {
2443 struct pci_dev *old_bridge = bridge;
2444
2445 /* Walk the hierarchy up to the root port
2446 * where ECRC has to be enabled */
2447 do {
2448 bridge = bridge->bus->self;
2449 if (!bridge) {
2450 dev_err(dev,
2451 "Failed to find root port"
2452 " to force ECRC\n");
2453 return;
2454 }
2455 cap =
2456 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2457 pci_read_config_word(bridge,
2458 cap + PCI_CAP_FLAGS, &val);
2459 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2460 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2461
2462 dev_info(dev,
2463 "Forcing ECRC on non-root port %s"
2464 " (enabling on root port %s)\n",
2465 pci_name(old_bridge), pci_name(bridge));
2466 } else {
2467 dev_err(dev,
2468 "Not enabling ECRC on non-root port %s\n",
2469 pci_name(bridge));
2470 return;
2471 }
2472 }
2473
2474 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
2475 if (!cap)
2476 return;
2477
2478 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2479 if (ret) {
2480 dev_err(dev, "failed reading ext-conf-space of %s\n",
2481 pci_name(bridge));
2482 dev_err(dev, "\t pci=nommconf in use? "
2483 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2484 return;
2485 }
2486 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2487 return;
2488
2489 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2490 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2491 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2492 }
2493
2494 /*
2495 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2496 * when the PCI-E Completion packets are aligned on an 8-byte
2497 * boundary. Some PCI-E chip sets always align Completion packets; on
2498 * the ones that do not, the alignment can be enforced by enabling
2499 * ECRC generation (if supported).
2500 *
2501 * When PCI-E Completion packets are not aligned, it is actually more
2502 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2503 *
2504 * If the driver can neither enable ECRC nor verify that it has
2505 * already been enabled, then it must use a firmware image which works
2506 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2507 * should also ensure that it never gives the device a Read-DMA which is
2508 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2509 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2510 * firmware image, and set tx.boundary to 4KB.
2511 */
2512
2513 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
2514 {
2515 struct pci_dev *pdev = mgp->pdev;
2516 struct device *dev = &pdev->dev;
2517 int status;
2518
2519 mgp->tx.boundary = 4096;
2520 /*
2521 * Verify the max read request size was set to 4KB
2522 * before trying the test with 4KB.
2523 */
2524 status = pcie_get_readrq(pdev);
2525 if (status < 0) {
2526 dev_err(dev, "Couldn't read max read req size: %d\n", status);
2527 goto abort;
2528 }
2529 if (status != 4096) {
2530 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
2531 mgp->tx.boundary = 2048;
2532 }
2533 /*
2534 * load the optimized firmware (which assumes aligned PCIe
2535 * completions) in order to see if it works on this host.
2536 */
2537 mgp->fw_name = myri10ge_fw_aligned;
2538 status = myri10ge_load_firmware(mgp);
2539 if (status != 0) {
2540 goto abort;
2541 }
2542
2543 /*
2544 * Enable ECRC if possible
2545 */
2546 myri10ge_enable_ecrc(mgp);
2547
2548 /*
2549 * Run a DMA test which watches for unaligned completions and
2550 * aborts on the first one seen.
2551 */
2552
2553 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
2554 if (status == 0)
2555 return; /* keep the aligned firmware */
2556
2557 if (status != -E2BIG)
2558 dev_warn(dev, "DMA test failed: %d\n", status);
2559 if (status == -ENOSYS)
2560 dev_warn(dev, "Falling back to ethp! "
2561 "Please install up to date fw\n");
2562 abort:
2563 /* fall back to using the unaligned firmware */
2564 mgp->tx.boundary = 2048;
2565 mgp->fw_name = myri10ge_fw_unaligned;
2566
2567 }
2568
2569 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2570 {
2571 if (myri10ge_force_firmware == 0) {
2572 int link_width, exp_cap;
2573 u16 lnk;
2574
2575 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2576 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2577 link_width = (lnk >> 4) & 0x3f;
2578
2579 /* Check to see if Link is less than 8 or if the
2580 * upstream bridge is known to provide aligned
2581 * completions */
2582 if (link_width < 8) {
2583 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2584 link_width);
2585 mgp->tx.boundary = 4096;
2586 mgp->fw_name = myri10ge_fw_aligned;
2587 } else {
2588 myri10ge_firmware_probe(mgp);
2589 }
2590 } else {
2591 if (myri10ge_force_firmware == 1) {
2592 dev_info(&mgp->pdev->dev,
2593 "Assuming aligned completions (forced)\n");
2594 mgp->tx.boundary = 4096;
2595 mgp->fw_name = myri10ge_fw_aligned;
2596 } else {
2597 dev_info(&mgp->pdev->dev,
2598 "Assuming unaligned completions (forced)\n");
2599 mgp->tx.boundary = 2048;
2600 mgp->fw_name = myri10ge_fw_unaligned;
2601 }
2602 }
2603 if (myri10ge_fw_name != NULL) {
2604 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2605 myri10ge_fw_name);
2606 mgp->fw_name = myri10ge_fw_name;
2607 }
2608 }
2609
2610 #ifdef CONFIG_PM
2611
2612 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2613 {
2614 struct myri10ge_priv *mgp;
2615 struct net_device *netdev;
2616
2617 mgp = pci_get_drvdata(pdev);
2618 if (mgp == NULL)
2619 return -EINVAL;
2620 netdev = mgp->dev;
2621
2622 netif_device_detach(netdev);
2623 if (netif_running(netdev)) {
2624 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2625 rtnl_lock();
2626 myri10ge_close(netdev);
2627 rtnl_unlock();
2628 }
2629 myri10ge_dummy_rdma(mgp, 0);
2630 pci_save_state(pdev);
2631 pci_disable_device(pdev);
2632
2633 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
2634 }
2635
2636 static int myri10ge_resume(struct pci_dev *pdev)
2637 {
2638 struct myri10ge_priv *mgp;
2639 struct net_device *netdev;
2640 int status;
2641 u16 vendor;
2642
2643 mgp = pci_get_drvdata(pdev);
2644 if (mgp == NULL)
2645 return -EINVAL;
2646 netdev = mgp->dev;
2647 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2648 msleep(5); /* give card time to respond */
2649 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2650 if (vendor == 0xffff) {
2651 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2652 mgp->dev->name);
2653 return -EIO;
2654 }
2655
2656 status = pci_restore_state(pdev);
2657 if (status)
2658 return status;
2659
2660 status = pci_enable_device(pdev);
2661 if (status) {
2662 dev_err(&pdev->dev, "failed to enable device\n");
2663 return status;
2664 }
2665
2666 pci_set_master(pdev);
2667
2668 myri10ge_reset(mgp);
2669 myri10ge_dummy_rdma(mgp, 1);
2670
2671 /* Save configuration space to be restored if the
2672 * nic resets due to a parity error */
2673 pci_save_state(pdev);
2674
2675 if (netif_running(netdev)) {
2676 rtnl_lock();
2677 status = myri10ge_open(netdev);
2678 rtnl_unlock();
2679 if (status != 0)
2680 goto abort_with_enabled;
2681
2682 }
2683 netif_device_attach(netdev);
2684
2685 return 0;
2686
2687 abort_with_enabled:
2688 pci_disable_device(pdev);
2689 return -EIO;
2690
2691 }
2692
2693 #endif /* CONFIG_PM */
2694
2695 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2696 {
2697 struct pci_dev *pdev = mgp->pdev;
2698 int vs = mgp->vendor_specific_offset;
2699 u32 reboot;
2700
2701 /*enter read32 mode */
2702 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2703
2704 /*read REBOOT_STATUS (0xfffffff0) */
2705 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2706 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2707 return reboot;
2708 }
2709
2710 /*
2711 * This watchdog is used to check whether the board has suffered
2712 * from a parity error and needs to be recovered.
2713 */
2714 static void myri10ge_watchdog(struct work_struct *work)
2715 {
2716 struct myri10ge_priv *mgp =
2717 container_of(work, struct myri10ge_priv, watchdog_work);
2718 u32 reboot;
2719 int status;
2720 u16 cmd, vendor;
2721
2722 mgp->watchdog_resets++;
2723 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2724 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2725 /* Bus master DMA disabled? Check to see
2726 * if the card rebooted due to a parity error
2727 * For now, just report it */
2728 reboot = myri10ge_read_reboot(mgp);
2729 printk(KERN_ERR
2730 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
2731 mgp->dev->name, reboot,
2732 myri10ge_reset_recover ? " " : " not");
2733 if (myri10ge_reset_recover == 0)
2734 return;
2735
2736 myri10ge_reset_recover--;
2737
2738 /*
2739 * A rebooted nic will come back with config space as
2740 * it was after power was applied to PCIe bus.
2741 * Attempt to restore config space which was saved
2742 * when the driver was loaded, or the last time the
2743 * nic was resumed from power saving mode.
2744 */
2745 pci_restore_state(mgp->pdev);
2746
2747 /* save state again for accounting reasons */
2748 pci_save_state(mgp->pdev);
2749
2750 } else {
2751 /* if we get back -1's from our slot, perhaps somebody
2752 * powered off our card. Don't try to reset it in
2753 * this case */
2754 if (cmd == 0xffff) {
2755 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2756 if (vendor == 0xffff) {
2757 printk(KERN_ERR
2758 "myri10ge: %s: device disappeared!\n",
2759 mgp->dev->name);
2760 return;
2761 }
2762 }
2763 /* Perhaps it is a software error. Try to reset */
2764
2765 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2766 mgp->dev->name);
2767 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2768 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2769 mgp->tx.pkt_start, mgp->tx.pkt_done,
2770 (int)ntohl(mgp->fw_stats->send_done_count));
2771 msleep(2000);
2772 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2773 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2774 mgp->tx.pkt_start, mgp->tx.pkt_done,
2775 (int)ntohl(mgp->fw_stats->send_done_count));
2776 }
2777 rtnl_lock();
2778 myri10ge_close(mgp->dev);
2779 status = myri10ge_load_firmware(mgp);
2780 if (status != 0)
2781 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2782 mgp->dev->name);
2783 else
2784 myri10ge_open(mgp->dev);
2785 rtnl_unlock();
2786 }
2787
2788 /*
2789 * We use our own timer routine rather than relying upon
2790 * netdev->tx_timeout because we have a very large hardware transmit
2791 * queue. Due to the large queue, the netdev->tx_timeout function
2792 * cannot detect a NIC with a parity error in a timely fashion if the
2793 * NIC is lightly loaded.
2794 */
2795 static void myri10ge_watchdog_timer(unsigned long arg)
2796 {
2797 struct myri10ge_priv *mgp;
2798 u32 rx_pause_cnt;
2799
2800 mgp = (struct myri10ge_priv *)arg;
2801
2802 if (mgp->rx_small.watchdog_needed) {
2803 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2804 mgp->small_bytes + MXGEFW_PAD, 1);
2805 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2806 myri10ge_fill_thresh)
2807 mgp->rx_small.watchdog_needed = 0;
2808 }
2809 if (mgp->rx_big.watchdog_needed) {
2810 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2811 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2812 myri10ge_fill_thresh)
2813 mgp->rx_big.watchdog_needed = 0;
2814 }
2815 rx_pause_cnt = ntohl(mgp->fw_stats->dropped_pause);
2816
2817 if (mgp->tx.req != mgp->tx.done &&
2818 mgp->tx.done == mgp->watchdog_tx_done &&
2819 mgp->watchdog_tx_req != mgp->watchdog_tx_done) {
2820 /* nic seems like it might be stuck.. */
2821 if (rx_pause_cnt != mgp->watchdog_pause) {
2822 if (net_ratelimit())
2823 printk(KERN_WARNING "myri10ge %s:"
2824 "TX paused, check link partner\n",
2825 mgp->dev->name);
2826 } else {
2827 schedule_work(&mgp->watchdog_work);
2828 return;
2829 }
2830 }
2831 /* rearm timer */
2832 mod_timer(&mgp->watchdog_timer,
2833 jiffies + myri10ge_watchdog_timeout * HZ);
2834 mgp->watchdog_tx_done = mgp->tx.done;
2835 mgp->watchdog_tx_req = mgp->tx.req;
2836 mgp->watchdog_pause = rx_pause_cnt;
2837 }
2838
2839 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2840 {
2841 struct net_device *netdev;
2842 struct myri10ge_priv *mgp;
2843 struct device *dev = &pdev->dev;
2844 size_t bytes;
2845 int i;
2846 int status = -ENXIO;
2847 int dac_enabled;
2848
2849 netdev = alloc_etherdev(sizeof(*mgp));
2850 if (netdev == NULL) {
2851 dev_err(dev, "Could not allocate ethernet device\n");
2852 return -ENOMEM;
2853 }
2854
2855 SET_NETDEV_DEV(netdev, &pdev->dev);
2856
2857 mgp = netdev_priv(netdev);
2858 memset(mgp, 0, sizeof(*mgp));
2859 mgp->dev = netdev;
2860 mgp->pdev = pdev;
2861 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2862 mgp->pause = myri10ge_flow_control;
2863 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
2864 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2865 init_waitqueue_head(&mgp->down_wq);
2866
2867 if (pci_enable_device(pdev)) {
2868 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2869 status = -ENODEV;
2870 goto abort_with_netdev;
2871 }
2872
2873 /* Find the vendor-specific cap so we can check
2874 * the reboot register later on */
2875 mgp->vendor_specific_offset
2876 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2877
2878 /* Set our max read request to 4KB */
2879 status = pcie_set_readrq(pdev, 4096);
2880 if (status != 0) {
2881 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2882 status);
2883 goto abort_with_netdev;
2884 }
2885
2886 pci_set_master(pdev);
2887 dac_enabled = 1;
2888 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2889 if (status != 0) {
2890 dac_enabled = 0;
2891 dev_err(&pdev->dev,
2892 "64-bit pci address mask was refused, trying 32-bit");
2893 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2894 }
2895 if (status != 0) {
2896 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2897 goto abort_with_netdev;
2898 }
2899 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2900 &mgp->cmd_bus, GFP_KERNEL);
2901 if (mgp->cmd == NULL)
2902 goto abort_with_netdev;
2903
2904 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2905 &mgp->fw_stats_bus, GFP_KERNEL);
2906 if (mgp->fw_stats == NULL)
2907 goto abort_with_cmd;
2908
2909 mgp->board_span = pci_resource_len(pdev, 0);
2910 mgp->iomem_base = pci_resource_start(pdev, 0);
2911 mgp->mtrr = -1;
2912 mgp->wc_enabled = 0;
2913 #ifdef CONFIG_MTRR
2914 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2915 MTRR_TYPE_WRCOMB, 1);
2916 if (mgp->mtrr >= 0)
2917 mgp->wc_enabled = 1;
2918 #endif
2919 /* Hack. need to get rid of these magic numbers */
2920 mgp->sram_size =
2921 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2922 if (mgp->sram_size > mgp->board_span) {
2923 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2924 mgp->board_span);
2925 goto abort_with_wc;
2926 }
2927 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2928 if (mgp->sram == NULL) {
2929 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2930 mgp->board_span, mgp->iomem_base);
2931 status = -ENXIO;
2932 goto abort_with_wc;
2933 }
2934 memcpy_fromio(mgp->eeprom_strings,
2935 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2936 MYRI10GE_EEPROM_STRINGS_SIZE);
2937 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2938 status = myri10ge_read_mac_addr(mgp);
2939 if (status)
2940 goto abort_with_ioremap;
2941
2942 for (i = 0; i < ETH_ALEN; i++)
2943 netdev->dev_addr[i] = mgp->mac_addr[i];
2944
2945 /* allocate rx done ring */
2946 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2947 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2948 &mgp->rx_done.bus, GFP_KERNEL);
2949 if (mgp->rx_done.entry == NULL)
2950 goto abort_with_ioremap;
2951 memset(mgp->rx_done.entry, 0, bytes);
2952
2953 myri10ge_select_firmware(mgp);
2954
2955 status = myri10ge_load_firmware(mgp);
2956 if (status != 0) {
2957 dev_err(&pdev->dev, "failed to load firmware\n");
2958 goto abort_with_rx_done;
2959 }
2960
2961 status = myri10ge_reset(mgp);
2962 if (status != 0) {
2963 dev_err(&pdev->dev, "failed reset\n");
2964 goto abort_with_firmware;
2965 }
2966
2967 pci_set_drvdata(pdev, mgp);
2968 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2969 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2970 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2971 myri10ge_initial_mtu = 68;
2972 netdev->mtu = myri10ge_initial_mtu;
2973 netdev->open = myri10ge_open;
2974 netdev->stop = myri10ge_close;
2975 netdev->hard_start_xmit = myri10ge_xmit;
2976 netdev->get_stats = myri10ge_get_stats;
2977 netdev->base_addr = mgp->iomem_base;
2978 netdev->change_mtu = myri10ge_change_mtu;
2979 netdev->set_multicast_list = myri10ge_set_multicast_list;
2980 netdev->set_mac_address = myri10ge_set_mac_address;
2981 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2982 if (dac_enabled)
2983 netdev->features |= NETIF_F_HIGHDMA;
2984 netdev->poll = myri10ge_poll;
2985 netdev->weight = myri10ge_napi_weight;
2986
2987 /* make sure we can get an irq, and that MSI can be
2988 * setup (if available). Also ensure netdev->irq
2989 * is set to correct value if MSI is enabled */
2990 status = myri10ge_request_irq(mgp);
2991 if (status != 0)
2992 goto abort_with_firmware;
2993 netdev->irq = pdev->irq;
2994 myri10ge_free_irq(mgp);
2995
2996 /* Save configuration space to be restored if the
2997 * nic resets due to a parity error */
2998 pci_save_state(pdev);
2999
3000 /* Setup the watchdog timer */
3001 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3002 (unsigned long)mgp);
3003
3004 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3005 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3006 status = register_netdev(netdev);
3007 if (status != 0) {
3008 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3009 goto abort_with_state;
3010 }
3011 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3012 (mgp->msi_enabled ? "MSI" : "xPIC"),
3013 netdev->irq, mgp->tx.boundary, mgp->fw_name,
3014 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3015
3016 return 0;
3017
3018 abort_with_state:
3019 pci_restore_state(pdev);
3020
3021 abort_with_firmware:
3022 myri10ge_dummy_rdma(mgp, 0);
3023
3024 abort_with_rx_done:
3025 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
3026 dma_free_coherent(&pdev->dev, bytes,
3027 mgp->rx_done.entry, mgp->rx_done.bus);
3028
3029 abort_with_ioremap:
3030 iounmap(mgp->sram);
3031
3032 abort_with_wc:
3033 #ifdef CONFIG_MTRR
3034 if (mgp->mtrr >= 0)
3035 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3036 #endif
3037 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3038 mgp->fw_stats, mgp->fw_stats_bus);
3039
3040 abort_with_cmd:
3041 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3042 mgp->cmd, mgp->cmd_bus);
3043
3044 abort_with_netdev:
3045
3046 free_netdev(netdev);
3047 return status;
3048 }
3049
3050 /*
3051 * myri10ge_remove
3052 *
3053 * Does what is necessary to shutdown one Myrinet device. Called
3054 * once for each Myrinet card by the kernel when a module is
3055 * unloaded.
3056 */
3057 static void myri10ge_remove(struct pci_dev *pdev)
3058 {
3059 struct myri10ge_priv *mgp;
3060 struct net_device *netdev;
3061 size_t bytes;
3062
3063 mgp = pci_get_drvdata(pdev);
3064 if (mgp == NULL)
3065 return;
3066
3067 flush_scheduled_work();
3068 netdev = mgp->dev;
3069 unregister_netdev(netdev);
3070
3071 myri10ge_dummy_rdma(mgp, 0);
3072
3073 /* avoid a memory leak */
3074 pci_restore_state(pdev);
3075
3076 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
3077 dma_free_coherent(&pdev->dev, bytes,
3078 mgp->rx_done.entry, mgp->rx_done.bus);
3079
3080 iounmap(mgp->sram);
3081
3082 #ifdef CONFIG_MTRR
3083 if (mgp->mtrr >= 0)
3084 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3085 #endif
3086 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3087 mgp->fw_stats, mgp->fw_stats_bus);
3088
3089 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3090 mgp->cmd, mgp->cmd_bus);
3091
3092 free_netdev(netdev);
3093 pci_set_drvdata(pdev, NULL);
3094 }
3095
3096 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
3097
3098 static struct pci_device_id myri10ge_pci_tbl[] = {
3099 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
3100 {0},
3101 };
3102
3103 static struct pci_driver myri10ge_driver = {
3104 .name = "myri10ge",
3105 .probe = myri10ge_probe,
3106 .remove = myri10ge_remove,
3107 .id_table = myri10ge_pci_tbl,
3108 #ifdef CONFIG_PM
3109 .suspend = myri10ge_suspend,
3110 .resume = myri10ge_resume,
3111 #endif
3112 };
3113
3114 static __init int myri10ge_init_module(void)
3115 {
3116 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3117 MYRI10GE_VERSION_STR);
3118 return pci_register_driver(&myri10ge_driver);
3119 }
3120
3121 module_init(myri10ge_init_module);
3122
3123 static __exit void myri10ge_cleanup_module(void)
3124 {
3125 pci_unregister_driver(&myri10ge_driver);
3126 }
3127
3128 module_exit(myri10ge_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)