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mv643xx_eth: require contiguous receive and transmit queue numbering
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / mv643xx_eth.c
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
37
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/in.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
53 #include <asm/io.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
56
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.3";
59
60 #define MV643XX_ETH_TX_FAST_REFILL
61
62 /*
63 * Registers shared between all ports.
64 */
65 #define PHY_ADDR 0x0000
66 #define SMI_REG 0x0004
67 #define SMI_BUSY 0x10000000
68 #define SMI_READ_VALID 0x08000000
69 #define SMI_OPCODE_READ 0x04000000
70 #define SMI_OPCODE_WRITE 0x00000000
71 #define ERR_INT_CAUSE 0x0080
72 #define ERR_INT_SMI_DONE 0x00000010
73 #define ERR_INT_MASK 0x0084
74 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77 #define WINDOW_BAR_ENABLE 0x0290
78 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
79
80 /*
81 * Per-port registers.
82 */
83 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
84 #define UNICAST_PROMISCUOUS_MODE 0x00000001
85 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
86 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
87 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
88 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
89 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
90 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
91 #define TX_FIFO_EMPTY 0x00000400
92 #define TX_IN_PROGRESS 0x00000080
93 #define PORT_SPEED_MASK 0x00000030
94 #define PORT_SPEED_1000 0x00000010
95 #define PORT_SPEED_100 0x00000020
96 #define PORT_SPEED_10 0x00000000
97 #define FLOW_CONTROL_ENABLED 0x00000008
98 #define FULL_DUPLEX 0x00000004
99 #define LINK_UP 0x00000002
100 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
101 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
102 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
103 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
104 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
105 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
106 #define INT_TX_END_0 0x00080000
107 #define INT_TX_END 0x07f80000
108 #define INT_RX 0x0007fbfc
109 #define INT_EXT 0x00000002
110 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
111 #define INT_EXT_LINK 0x00100000
112 #define INT_EXT_PHY 0x00010000
113 #define INT_EXT_TX_ERROR_0 0x00000100
114 #define INT_EXT_TX_0 0x00000001
115 #define INT_EXT_TX 0x0000ffff
116 #define INT_MASK(p) (0x0468 + ((p) << 10))
117 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
118 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
119 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
120 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
121 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
122 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
123 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
124 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
125 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
126 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
127 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
128 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
129 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
130 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
131 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
132 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
133
134
135 /*
136 * SDMA configuration register.
137 */
138 #define RX_BURST_SIZE_16_64BIT (4 << 1)
139 #define BLM_RX_NO_SWAP (1 << 4)
140 #define BLM_TX_NO_SWAP (1 << 5)
141 #define TX_BURST_SIZE_16_64BIT (4 << 22)
142
143 #if defined(__BIG_ENDIAN)
144 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
145 RX_BURST_SIZE_16_64BIT | \
146 TX_BURST_SIZE_16_64BIT
147 #elif defined(__LITTLE_ENDIAN)
148 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
149 RX_BURST_SIZE_16_64BIT | \
150 BLM_RX_NO_SWAP | \
151 BLM_TX_NO_SWAP | \
152 TX_BURST_SIZE_16_64BIT
153 #else
154 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
155 #endif
156
157
158 /*
159 * Port serial control register.
160 */
161 #define SET_MII_SPEED_TO_100 (1 << 24)
162 #define SET_GMII_SPEED_TO_1000 (1 << 23)
163 #define SET_FULL_DUPLEX_MODE (1 << 21)
164 #define MAX_RX_PACKET_9700BYTE (5 << 17)
165 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
166 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
167 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
168 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
169 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
170 #define FORCE_LINK_PASS (1 << 1)
171 #define SERIAL_PORT_ENABLE (1 << 0)
172
173 #define DEFAULT_RX_QUEUE_SIZE 400
174 #define DEFAULT_TX_QUEUE_SIZE 800
175
176
177 /*
178 * RX/TX descriptors.
179 */
180 #if defined(__BIG_ENDIAN)
181 struct rx_desc {
182 u16 byte_cnt; /* Descriptor buffer byte count */
183 u16 buf_size; /* Buffer size */
184 u32 cmd_sts; /* Descriptor command status */
185 u32 next_desc_ptr; /* Next descriptor pointer */
186 u32 buf_ptr; /* Descriptor buffer pointer */
187 };
188
189 struct tx_desc {
190 u16 byte_cnt; /* buffer byte count */
191 u16 l4i_chk; /* CPU provided TCP checksum */
192 u32 cmd_sts; /* Command/status field */
193 u32 next_desc_ptr; /* Pointer to next descriptor */
194 u32 buf_ptr; /* pointer to buffer for this descriptor*/
195 };
196 #elif defined(__LITTLE_ENDIAN)
197 struct rx_desc {
198 u32 cmd_sts; /* Descriptor command status */
199 u16 buf_size; /* Buffer size */
200 u16 byte_cnt; /* Descriptor buffer byte count */
201 u32 buf_ptr; /* Descriptor buffer pointer */
202 u32 next_desc_ptr; /* Next descriptor pointer */
203 };
204
205 struct tx_desc {
206 u32 cmd_sts; /* Command/status field */
207 u16 l4i_chk; /* CPU provided TCP checksum */
208 u16 byte_cnt; /* buffer byte count */
209 u32 buf_ptr; /* pointer to buffer for this descriptor*/
210 u32 next_desc_ptr; /* Pointer to next descriptor */
211 };
212 #else
213 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
214 #endif
215
216 /* RX & TX descriptor command */
217 #define BUFFER_OWNED_BY_DMA 0x80000000
218
219 /* RX & TX descriptor status */
220 #define ERROR_SUMMARY 0x00000001
221
222 /* RX descriptor status */
223 #define LAYER_4_CHECKSUM_OK 0x40000000
224 #define RX_ENABLE_INTERRUPT 0x20000000
225 #define RX_FIRST_DESC 0x08000000
226 #define RX_LAST_DESC 0x04000000
227
228 /* TX descriptor command */
229 #define TX_ENABLE_INTERRUPT 0x00800000
230 #define GEN_CRC 0x00400000
231 #define TX_FIRST_DESC 0x00200000
232 #define TX_LAST_DESC 0x00100000
233 #define ZERO_PADDING 0x00080000
234 #define GEN_IP_V4_CHECKSUM 0x00040000
235 #define GEN_TCP_UDP_CHECKSUM 0x00020000
236 #define UDP_FRAME 0x00010000
237 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
238 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
239
240 #define TX_IHL_SHIFT 11
241
242
243 /* global *******************************************************************/
244 struct mv643xx_eth_shared_private {
245 /*
246 * Ethernet controller base address.
247 */
248 void __iomem *base;
249
250 /*
251 * Protects access to SMI_REG, which is shared between ports.
252 */
253 struct mutex phy_lock;
254
255 /*
256 * If we have access to the error interrupt pin (which is
257 * somewhat misnamed as it not only reflects internal errors
258 * but also reflects SMI completion), use that to wait for
259 * SMI access completion instead of polling the SMI busy bit.
260 */
261 int err_interrupt;
262 wait_queue_head_t smi_busy_wait;
263
264 /*
265 * Per-port MBUS window access register value.
266 */
267 u32 win_protect;
268
269 /*
270 * Hardware-specific parameters.
271 */
272 unsigned int t_clk;
273 int extended_rx_coal_limit;
274 int tx_bw_control_moved;
275 };
276
277
278 /* per-port *****************************************************************/
279 struct mib_counters {
280 u64 good_octets_received;
281 u32 bad_octets_received;
282 u32 internal_mac_transmit_err;
283 u32 good_frames_received;
284 u32 bad_frames_received;
285 u32 broadcast_frames_received;
286 u32 multicast_frames_received;
287 u32 frames_64_octets;
288 u32 frames_65_to_127_octets;
289 u32 frames_128_to_255_octets;
290 u32 frames_256_to_511_octets;
291 u32 frames_512_to_1023_octets;
292 u32 frames_1024_to_max_octets;
293 u64 good_octets_sent;
294 u32 good_frames_sent;
295 u32 excessive_collision;
296 u32 multicast_frames_sent;
297 u32 broadcast_frames_sent;
298 u32 unrec_mac_control_received;
299 u32 fc_sent;
300 u32 good_fc_received;
301 u32 bad_fc_received;
302 u32 undersize_received;
303 u32 fragments_received;
304 u32 oversize_received;
305 u32 jabber_received;
306 u32 mac_receive_error;
307 u32 bad_crc_event;
308 u32 collision;
309 u32 late_collision;
310 };
311
312 struct rx_queue {
313 int index;
314
315 int rx_ring_size;
316
317 int rx_desc_count;
318 int rx_curr_desc;
319 int rx_used_desc;
320
321 struct rx_desc *rx_desc_area;
322 dma_addr_t rx_desc_dma;
323 int rx_desc_area_size;
324 struct sk_buff **rx_skb;
325 };
326
327 struct tx_queue {
328 int index;
329
330 int tx_ring_size;
331
332 int tx_desc_count;
333 int tx_curr_desc;
334 int tx_used_desc;
335
336 struct tx_desc *tx_desc_area;
337 dma_addr_t tx_desc_dma;
338 int tx_desc_area_size;
339 struct sk_buff **tx_skb;
340 };
341
342 struct mv643xx_eth_private {
343 struct mv643xx_eth_shared_private *shared;
344 int port_num;
345
346 struct net_device *dev;
347
348 struct mv643xx_eth_shared_private *shared_smi;
349 int phy_addr;
350
351 spinlock_t lock;
352
353 struct mib_counters mib_counters;
354 struct work_struct tx_timeout_task;
355 struct mii_if_info mii;
356
357 /*
358 * RX state.
359 */
360 int default_rx_ring_size;
361 unsigned long rx_desc_sram_addr;
362 int rx_desc_sram_size;
363 int rxq_count;
364 struct napi_struct napi;
365 struct timer_list rx_oom;
366 struct rx_queue rxq[8];
367
368 /*
369 * TX state.
370 */
371 int default_tx_ring_size;
372 unsigned long tx_desc_sram_addr;
373 int tx_desc_sram_size;
374 int txq_count;
375 struct tx_queue txq[8];
376 #ifdef MV643XX_ETH_TX_FAST_REFILL
377 int tx_clean_threshold;
378 #endif
379 };
380
381
382 /* port register accessors **************************************************/
383 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
384 {
385 return readl(mp->shared->base + offset);
386 }
387
388 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
389 {
390 writel(data, mp->shared->base + offset);
391 }
392
393
394 /* rxq/txq helper functions *************************************************/
395 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
396 {
397 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
398 }
399
400 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
401 {
402 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
403 }
404
405 static void rxq_enable(struct rx_queue *rxq)
406 {
407 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
408 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
409 }
410
411 static void rxq_disable(struct rx_queue *rxq)
412 {
413 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
414 u8 mask = 1 << rxq->index;
415
416 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
417 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
418 udelay(10);
419 }
420
421 static void txq_reset_hw_ptr(struct tx_queue *txq)
422 {
423 struct mv643xx_eth_private *mp = txq_to_mp(txq);
424 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
425 u32 addr;
426
427 addr = (u32)txq->tx_desc_dma;
428 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
429 wrl(mp, off, addr);
430 }
431
432 static void txq_enable(struct tx_queue *txq)
433 {
434 struct mv643xx_eth_private *mp = txq_to_mp(txq);
435 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
436 }
437
438 static void txq_disable(struct tx_queue *txq)
439 {
440 struct mv643xx_eth_private *mp = txq_to_mp(txq);
441 u8 mask = 1 << txq->index;
442
443 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
444 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
445 udelay(10);
446 }
447
448 static void __txq_maybe_wake(struct tx_queue *txq)
449 {
450 struct mv643xx_eth_private *mp = txq_to_mp(txq);
451
452 /*
453 * netif_{stop,wake}_queue() flow control only applies to
454 * the primary queue.
455 */
456 BUG_ON(txq->index != 0);
457
458 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
459 netif_wake_queue(mp->dev);
460 }
461
462
463 /* rx ***********************************************************************/
464 static void txq_reclaim(struct tx_queue *txq, int force);
465
466 static int rxq_refill(struct rx_queue *rxq, int budget, int *oom)
467 {
468 int skb_size;
469 int refilled;
470
471 /*
472 * Reserve 2+14 bytes for an ethernet header (the hardware
473 * automatically prepends 2 bytes of dummy data to each
474 * received packet), 16 bytes for up to four VLAN tags, and
475 * 4 bytes for the trailing FCS -- 36 bytes total.
476 */
477 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
478
479 /*
480 * Make sure that the skb size is a multiple of 8 bytes, as
481 * the lower three bits of the receive descriptor's buffer
482 * size field are ignored by the hardware.
483 */
484 skb_size = (skb_size + 7) & ~7;
485
486 refilled = 0;
487 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
488 struct sk_buff *skb;
489 int unaligned;
490 int rx;
491
492 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
493 if (skb == NULL) {
494 *oom = 1;
495 break;
496 }
497
498 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
499 if (unaligned)
500 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
501
502 refilled++;
503 rxq->rx_desc_count++;
504
505 rx = rxq->rx_used_desc++;
506 if (rxq->rx_used_desc == rxq->rx_ring_size)
507 rxq->rx_used_desc = 0;
508
509 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
510 skb_size, DMA_FROM_DEVICE);
511 rxq->rx_desc_area[rx].buf_size = skb_size;
512 rxq->rx_skb[rx] = skb;
513 wmb();
514 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
515 RX_ENABLE_INTERRUPT;
516 wmb();
517
518 /*
519 * The hardware automatically prepends 2 bytes of
520 * dummy data to each received packet, so that the
521 * IP header ends up 16-byte aligned.
522 */
523 skb_reserve(skb, 2);
524 }
525
526 return refilled;
527 }
528
529 static int rxq_process(struct rx_queue *rxq, int budget)
530 {
531 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
532 struct net_device_stats *stats = &mp->dev->stats;
533 int rx;
534
535 rx = 0;
536 while (rx < budget && rxq->rx_desc_count) {
537 struct rx_desc *rx_desc;
538 unsigned int cmd_sts;
539 struct sk_buff *skb;
540
541 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
542
543 cmd_sts = rx_desc->cmd_sts;
544 if (cmd_sts & BUFFER_OWNED_BY_DMA)
545 break;
546 rmb();
547
548 skb = rxq->rx_skb[rxq->rx_curr_desc];
549 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
550
551 rxq->rx_curr_desc++;
552 if (rxq->rx_curr_desc == rxq->rx_ring_size)
553 rxq->rx_curr_desc = 0;
554
555 dma_unmap_single(NULL, rx_desc->buf_ptr,
556 rx_desc->buf_size, DMA_FROM_DEVICE);
557 rxq->rx_desc_count--;
558 rx++;
559
560 /*
561 * Update statistics.
562 *
563 * Note that the descriptor byte count includes 2 dummy
564 * bytes automatically inserted by the hardware at the
565 * start of the packet (which we don't count), and a 4
566 * byte CRC at the end of the packet (which we do count).
567 */
568 stats->rx_packets++;
569 stats->rx_bytes += rx_desc->byte_cnt - 2;
570
571 /*
572 * In case we received a packet without first / last bits
573 * on, or the error summary bit is set, the packet needs
574 * to be dropped.
575 */
576 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
577 (RX_FIRST_DESC | RX_LAST_DESC))
578 || (cmd_sts & ERROR_SUMMARY)) {
579 stats->rx_dropped++;
580
581 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
582 (RX_FIRST_DESC | RX_LAST_DESC)) {
583 if (net_ratelimit())
584 dev_printk(KERN_ERR, &mp->dev->dev,
585 "received packet spanning "
586 "multiple descriptors\n");
587 }
588
589 if (cmd_sts & ERROR_SUMMARY)
590 stats->rx_errors++;
591
592 dev_kfree_skb(skb);
593 } else {
594 /*
595 * The -4 is for the CRC in the trailer of the
596 * received packet
597 */
598 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
599
600 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
601 skb->ip_summed = CHECKSUM_UNNECESSARY;
602 skb->csum = htons(
603 (cmd_sts & 0x0007fff8) >> 3);
604 }
605 skb->protocol = eth_type_trans(skb, mp->dev);
606 netif_receive_skb(skb);
607 }
608
609 mp->dev->last_rx = jiffies;
610 }
611
612 return rx;
613 }
614
615 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
616 {
617 struct mv643xx_eth_private *mp;
618 int work_done;
619 int oom;
620 int i;
621
622 mp = container_of(napi, struct mv643xx_eth_private, napi);
623
624 #ifdef MV643XX_ETH_TX_FAST_REFILL
625 if (++mp->tx_clean_threshold > 5) {
626 mp->tx_clean_threshold = 0;
627 for (i = 0; i < mp->txq_count; i++)
628 txq_reclaim(mp->txq + i, 0);
629
630 if (netif_carrier_ok(mp->dev)) {
631 spin_lock_irq(&mp->lock);
632 __txq_maybe_wake(mp->txq);
633 spin_unlock_irq(&mp->lock);
634 }
635 }
636 #endif
637
638 work_done = 0;
639 oom = 0;
640 for (i = mp->rxq_count - 1; work_done < budget && i >= 0; i--) {
641 struct rx_queue *rxq = mp->rxq + i;
642
643 work_done += rxq_process(rxq, budget - work_done);
644 work_done += rxq_refill(rxq, budget - work_done, &oom);
645 }
646
647 if (work_done < budget) {
648 if (oom)
649 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
650 netif_rx_complete(mp->dev, napi);
651 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
652 }
653
654 return work_done;
655 }
656
657 static inline void oom_timer_wrapper(unsigned long data)
658 {
659 struct mv643xx_eth_private *mp = (void *)data;
660
661 napi_schedule(&mp->napi);
662 }
663
664
665 /* tx ***********************************************************************/
666 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
667 {
668 int frag;
669
670 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
671 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
672 if (fragp->size <= 8 && fragp->page_offset & 7)
673 return 1;
674 }
675
676 return 0;
677 }
678
679 static int txq_alloc_desc_index(struct tx_queue *txq)
680 {
681 int tx_desc_curr;
682
683 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
684
685 tx_desc_curr = txq->tx_curr_desc++;
686 if (txq->tx_curr_desc == txq->tx_ring_size)
687 txq->tx_curr_desc = 0;
688
689 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
690
691 return tx_desc_curr;
692 }
693
694 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
695 {
696 int nr_frags = skb_shinfo(skb)->nr_frags;
697 int frag;
698
699 for (frag = 0; frag < nr_frags; frag++) {
700 skb_frag_t *this_frag;
701 int tx_index;
702 struct tx_desc *desc;
703
704 this_frag = &skb_shinfo(skb)->frags[frag];
705 tx_index = txq_alloc_desc_index(txq);
706 desc = &txq->tx_desc_area[tx_index];
707
708 /*
709 * The last fragment will generate an interrupt
710 * which will free the skb on TX completion.
711 */
712 if (frag == nr_frags - 1) {
713 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
714 ZERO_PADDING | TX_LAST_DESC |
715 TX_ENABLE_INTERRUPT;
716 txq->tx_skb[tx_index] = skb;
717 } else {
718 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
719 txq->tx_skb[tx_index] = NULL;
720 }
721
722 desc->l4i_chk = 0;
723 desc->byte_cnt = this_frag->size;
724 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
725 this_frag->page_offset,
726 this_frag->size,
727 DMA_TO_DEVICE);
728 }
729 }
730
731 static inline __be16 sum16_as_be(__sum16 sum)
732 {
733 return (__force __be16)sum;
734 }
735
736 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
737 {
738 struct mv643xx_eth_private *mp = txq_to_mp(txq);
739 int nr_frags = skb_shinfo(skb)->nr_frags;
740 int tx_index;
741 struct tx_desc *desc;
742 u32 cmd_sts;
743 int length;
744
745 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
746
747 tx_index = txq_alloc_desc_index(txq);
748 desc = &txq->tx_desc_area[tx_index];
749
750 if (nr_frags) {
751 txq_submit_frag_skb(txq, skb);
752
753 length = skb_headlen(skb);
754 txq->tx_skb[tx_index] = NULL;
755 } else {
756 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
757 length = skb->len;
758 txq->tx_skb[tx_index] = skb;
759 }
760
761 desc->byte_cnt = length;
762 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
763
764 if (skb->ip_summed == CHECKSUM_PARTIAL) {
765 int mac_hdr_len;
766
767 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
768 skb->protocol != htons(ETH_P_8021Q));
769
770 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
771 GEN_IP_V4_CHECKSUM |
772 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
773
774 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
775 switch (mac_hdr_len - ETH_HLEN) {
776 case 0:
777 break;
778 case 4:
779 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
780 break;
781 case 8:
782 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
783 break;
784 case 12:
785 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
786 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
787 break;
788 default:
789 if (net_ratelimit())
790 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
791 "mac header length is %d?!\n", mac_hdr_len);
792 break;
793 }
794
795 switch (ip_hdr(skb)->protocol) {
796 case IPPROTO_UDP:
797 cmd_sts |= UDP_FRAME;
798 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
799 break;
800 case IPPROTO_TCP:
801 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
802 break;
803 default:
804 BUG();
805 }
806 } else {
807 /* Errata BTS #50, IHL must be 5 if no HW checksum */
808 cmd_sts |= 5 << TX_IHL_SHIFT;
809 desc->l4i_chk = 0;
810 }
811
812 /* ensure all other descriptors are written before first cmd_sts */
813 wmb();
814 desc->cmd_sts = cmd_sts;
815
816 /* clear TX_END interrupt status */
817 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
818 rdl(mp, INT_CAUSE(mp->port_num));
819
820 /* ensure all descriptors are written before poking hardware */
821 wmb();
822 txq_enable(txq);
823
824 txq->tx_desc_count += nr_frags + 1;
825 }
826
827 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
828 {
829 struct mv643xx_eth_private *mp = netdev_priv(dev);
830 struct net_device_stats *stats = &dev->stats;
831 struct tx_queue *txq;
832 unsigned long flags;
833
834 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
835 stats->tx_dropped++;
836 dev_printk(KERN_DEBUG, &dev->dev,
837 "failed to linearize skb with tiny "
838 "unaligned fragment\n");
839 return NETDEV_TX_BUSY;
840 }
841
842 spin_lock_irqsave(&mp->lock, flags);
843
844 txq = mp->txq;
845
846 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
847 spin_unlock_irqrestore(&mp->lock, flags);
848 if (txq->index == 0 && net_ratelimit())
849 dev_printk(KERN_ERR, &dev->dev,
850 "primary tx queue full?!\n");
851 kfree_skb(skb);
852 return NETDEV_TX_OK;
853 }
854
855 txq_submit_skb(txq, skb);
856 stats->tx_bytes += skb->len;
857 stats->tx_packets++;
858 dev->trans_start = jiffies;
859
860 if (txq->index == 0) {
861 int entries_left;
862
863 entries_left = txq->tx_ring_size - txq->tx_desc_count;
864 if (entries_left < MAX_SKB_FRAGS + 1)
865 netif_stop_queue(dev);
866 }
867
868 spin_unlock_irqrestore(&mp->lock, flags);
869
870 return NETDEV_TX_OK;
871 }
872
873
874 /* tx rate control **********************************************************/
875 /*
876 * Set total maximum TX rate (shared by all TX queues for this port)
877 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
878 */
879 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
880 {
881 int token_rate;
882 int mtu;
883 int bucket_size;
884
885 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
886 if (token_rate > 1023)
887 token_rate = 1023;
888
889 mtu = (mp->dev->mtu + 255) >> 8;
890 if (mtu > 63)
891 mtu = 63;
892
893 bucket_size = (burst + 255) >> 8;
894 if (bucket_size > 65535)
895 bucket_size = 65535;
896
897 if (mp->shared->tx_bw_control_moved) {
898 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
899 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
900 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
901 } else {
902 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
903 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
904 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
905 }
906 }
907
908 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
909 {
910 struct mv643xx_eth_private *mp = txq_to_mp(txq);
911 int token_rate;
912 int bucket_size;
913
914 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
915 if (token_rate > 1023)
916 token_rate = 1023;
917
918 bucket_size = (burst + 255) >> 8;
919 if (bucket_size > 65535)
920 bucket_size = 65535;
921
922 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
923 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
924 (bucket_size << 10) | token_rate);
925 }
926
927 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
928 {
929 struct mv643xx_eth_private *mp = txq_to_mp(txq);
930 int off;
931 u32 val;
932
933 /*
934 * Turn on fixed priority mode.
935 */
936 if (mp->shared->tx_bw_control_moved)
937 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
938 else
939 off = TXQ_FIX_PRIO_CONF(mp->port_num);
940
941 val = rdl(mp, off);
942 val |= 1 << txq->index;
943 wrl(mp, off, val);
944 }
945
946 static void txq_set_wrr(struct tx_queue *txq, int weight)
947 {
948 struct mv643xx_eth_private *mp = txq_to_mp(txq);
949 int off;
950 u32 val;
951
952 /*
953 * Turn off fixed priority mode.
954 */
955 if (mp->shared->tx_bw_control_moved)
956 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
957 else
958 off = TXQ_FIX_PRIO_CONF(mp->port_num);
959
960 val = rdl(mp, off);
961 val &= ~(1 << txq->index);
962 wrl(mp, off, val);
963
964 /*
965 * Configure WRR weight for this queue.
966 */
967 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
968
969 val = rdl(mp, off);
970 val = (val & ~0xff) | (weight & 0xff);
971 wrl(mp, off, val);
972 }
973
974
975 /* mii management interface *************************************************/
976 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
977 {
978 struct mv643xx_eth_shared_private *msp = dev_id;
979
980 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
981 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
982 wake_up(&msp->smi_busy_wait);
983 return IRQ_HANDLED;
984 }
985
986 return IRQ_NONE;
987 }
988
989 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
990 {
991 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
992 }
993
994 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
995 {
996 if (msp->err_interrupt == NO_IRQ) {
997 int i;
998
999 for (i = 0; !smi_is_done(msp); i++) {
1000 if (i == 10)
1001 return -ETIMEDOUT;
1002 msleep(10);
1003 }
1004
1005 return 0;
1006 }
1007
1008 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1009 msecs_to_jiffies(100)))
1010 return -ETIMEDOUT;
1011
1012 return 0;
1013 }
1014
1015 static int smi_reg_read(struct mv643xx_eth_private *mp,
1016 unsigned int addr, unsigned int reg)
1017 {
1018 struct mv643xx_eth_shared_private *msp = mp->shared_smi;
1019 void __iomem *smi_reg = msp->base + SMI_REG;
1020 int ret;
1021
1022 mutex_lock(&msp->phy_lock);
1023
1024 if (smi_wait_ready(msp)) {
1025 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1026 ret = -ETIMEDOUT;
1027 goto out;
1028 }
1029
1030 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1031
1032 if (smi_wait_ready(msp)) {
1033 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1034 ret = -ETIMEDOUT;
1035 goto out;
1036 }
1037
1038 ret = readl(smi_reg);
1039 if (!(ret & SMI_READ_VALID)) {
1040 printk("%s: SMI bus read not valid\n", mp->dev->name);
1041 ret = -ENODEV;
1042 goto out;
1043 }
1044
1045 ret &= 0xffff;
1046
1047 out:
1048 mutex_unlock(&msp->phy_lock);
1049
1050 return ret;
1051 }
1052
1053 static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1054 unsigned int reg, unsigned int value)
1055 {
1056 struct mv643xx_eth_shared_private *msp = mp->shared_smi;
1057 void __iomem *smi_reg = msp->base + SMI_REG;
1058
1059 mutex_lock(&msp->phy_lock);
1060
1061 if (smi_wait_ready(msp)) {
1062 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1063 mutex_unlock(&msp->phy_lock);
1064 return -ETIMEDOUT;
1065 }
1066
1067 writel(SMI_OPCODE_WRITE | (reg << 21) |
1068 (addr << 16) | (value & 0xffff), smi_reg);
1069
1070 mutex_unlock(&msp->phy_lock);
1071
1072 return 0;
1073 }
1074
1075
1076 /* mib counters *************************************************************/
1077 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1078 {
1079 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1080 }
1081
1082 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1083 {
1084 int i;
1085
1086 for (i = 0; i < 0x80; i += 4)
1087 mib_read(mp, i);
1088 }
1089
1090 static void mib_counters_update(struct mv643xx_eth_private *mp)
1091 {
1092 struct mib_counters *p = &mp->mib_counters;
1093
1094 p->good_octets_received += mib_read(mp, 0x00);
1095 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1096 p->bad_octets_received += mib_read(mp, 0x08);
1097 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1098 p->good_frames_received += mib_read(mp, 0x10);
1099 p->bad_frames_received += mib_read(mp, 0x14);
1100 p->broadcast_frames_received += mib_read(mp, 0x18);
1101 p->multicast_frames_received += mib_read(mp, 0x1c);
1102 p->frames_64_octets += mib_read(mp, 0x20);
1103 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1104 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1105 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1106 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1107 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1108 p->good_octets_sent += mib_read(mp, 0x38);
1109 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1110 p->good_frames_sent += mib_read(mp, 0x40);
1111 p->excessive_collision += mib_read(mp, 0x44);
1112 p->multicast_frames_sent += mib_read(mp, 0x48);
1113 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1114 p->unrec_mac_control_received += mib_read(mp, 0x50);
1115 p->fc_sent += mib_read(mp, 0x54);
1116 p->good_fc_received += mib_read(mp, 0x58);
1117 p->bad_fc_received += mib_read(mp, 0x5c);
1118 p->undersize_received += mib_read(mp, 0x60);
1119 p->fragments_received += mib_read(mp, 0x64);
1120 p->oversize_received += mib_read(mp, 0x68);
1121 p->jabber_received += mib_read(mp, 0x6c);
1122 p->mac_receive_error += mib_read(mp, 0x70);
1123 p->bad_crc_event += mib_read(mp, 0x74);
1124 p->collision += mib_read(mp, 0x78);
1125 p->late_collision += mib_read(mp, 0x7c);
1126 }
1127
1128
1129 /* ethtool ******************************************************************/
1130 struct mv643xx_eth_stats {
1131 char stat_string[ETH_GSTRING_LEN];
1132 int sizeof_stat;
1133 int netdev_off;
1134 int mp_off;
1135 };
1136
1137 #define SSTAT(m) \
1138 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1139 offsetof(struct net_device, stats.m), -1 }
1140
1141 #define MIBSTAT(m) \
1142 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1143 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1144
1145 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1146 SSTAT(rx_packets),
1147 SSTAT(tx_packets),
1148 SSTAT(rx_bytes),
1149 SSTAT(tx_bytes),
1150 SSTAT(rx_errors),
1151 SSTAT(tx_errors),
1152 SSTAT(rx_dropped),
1153 SSTAT(tx_dropped),
1154 MIBSTAT(good_octets_received),
1155 MIBSTAT(bad_octets_received),
1156 MIBSTAT(internal_mac_transmit_err),
1157 MIBSTAT(good_frames_received),
1158 MIBSTAT(bad_frames_received),
1159 MIBSTAT(broadcast_frames_received),
1160 MIBSTAT(multicast_frames_received),
1161 MIBSTAT(frames_64_octets),
1162 MIBSTAT(frames_65_to_127_octets),
1163 MIBSTAT(frames_128_to_255_octets),
1164 MIBSTAT(frames_256_to_511_octets),
1165 MIBSTAT(frames_512_to_1023_octets),
1166 MIBSTAT(frames_1024_to_max_octets),
1167 MIBSTAT(good_octets_sent),
1168 MIBSTAT(good_frames_sent),
1169 MIBSTAT(excessive_collision),
1170 MIBSTAT(multicast_frames_sent),
1171 MIBSTAT(broadcast_frames_sent),
1172 MIBSTAT(unrec_mac_control_received),
1173 MIBSTAT(fc_sent),
1174 MIBSTAT(good_fc_received),
1175 MIBSTAT(bad_fc_received),
1176 MIBSTAT(undersize_received),
1177 MIBSTAT(fragments_received),
1178 MIBSTAT(oversize_received),
1179 MIBSTAT(jabber_received),
1180 MIBSTAT(mac_receive_error),
1181 MIBSTAT(bad_crc_event),
1182 MIBSTAT(collision),
1183 MIBSTAT(late_collision),
1184 };
1185
1186 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1187 {
1188 struct mv643xx_eth_private *mp = netdev_priv(dev);
1189 int err;
1190
1191 err = mii_ethtool_gset(&mp->mii, cmd);
1192
1193 /*
1194 * The MAC does not support 1000baseT_Half.
1195 */
1196 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1197 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1198
1199 return err;
1200 }
1201
1202 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1203 {
1204 struct mv643xx_eth_private *mp = netdev_priv(dev);
1205 u32 port_status;
1206
1207 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1208
1209 cmd->supported = SUPPORTED_MII;
1210 cmd->advertising = ADVERTISED_MII;
1211 switch (port_status & PORT_SPEED_MASK) {
1212 case PORT_SPEED_10:
1213 cmd->speed = SPEED_10;
1214 break;
1215 case PORT_SPEED_100:
1216 cmd->speed = SPEED_100;
1217 break;
1218 case PORT_SPEED_1000:
1219 cmd->speed = SPEED_1000;
1220 break;
1221 default:
1222 cmd->speed = -1;
1223 break;
1224 }
1225 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1226 cmd->port = PORT_MII;
1227 cmd->phy_address = 0;
1228 cmd->transceiver = XCVR_INTERNAL;
1229 cmd->autoneg = AUTONEG_DISABLE;
1230 cmd->maxtxpkt = 1;
1231 cmd->maxrxpkt = 1;
1232
1233 return 0;
1234 }
1235
1236 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1237 {
1238 struct mv643xx_eth_private *mp = netdev_priv(dev);
1239
1240 /*
1241 * The MAC does not support 1000baseT_Half.
1242 */
1243 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1244
1245 return mii_ethtool_sset(&mp->mii, cmd);
1246 }
1247
1248 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1249 {
1250 return -EINVAL;
1251 }
1252
1253 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1254 struct ethtool_drvinfo *drvinfo)
1255 {
1256 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1257 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1258 strncpy(drvinfo->fw_version, "N/A", 32);
1259 strncpy(drvinfo->bus_info, "platform", 32);
1260 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1261 }
1262
1263 static int mv643xx_eth_nway_reset(struct net_device *dev)
1264 {
1265 struct mv643xx_eth_private *mp = netdev_priv(dev);
1266
1267 return mii_nway_restart(&mp->mii);
1268 }
1269
1270 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1271 {
1272 return -EINVAL;
1273 }
1274
1275 static u32 mv643xx_eth_get_link(struct net_device *dev)
1276 {
1277 struct mv643xx_eth_private *mp = netdev_priv(dev);
1278
1279 return mii_link_ok(&mp->mii);
1280 }
1281
1282 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1283 {
1284 return 1;
1285 }
1286
1287 static void mv643xx_eth_get_strings(struct net_device *dev,
1288 uint32_t stringset, uint8_t *data)
1289 {
1290 int i;
1291
1292 if (stringset == ETH_SS_STATS) {
1293 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1294 memcpy(data + i * ETH_GSTRING_LEN,
1295 mv643xx_eth_stats[i].stat_string,
1296 ETH_GSTRING_LEN);
1297 }
1298 }
1299 }
1300
1301 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1302 struct ethtool_stats *stats,
1303 uint64_t *data)
1304 {
1305 struct mv643xx_eth_private *mp = netdev_priv(dev);
1306 int i;
1307
1308 mib_counters_update(mp);
1309
1310 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1311 const struct mv643xx_eth_stats *stat;
1312 void *p;
1313
1314 stat = mv643xx_eth_stats + i;
1315
1316 if (stat->netdev_off >= 0)
1317 p = ((void *)mp->dev) + stat->netdev_off;
1318 else
1319 p = ((void *)mp) + stat->mp_off;
1320
1321 data[i] = (stat->sizeof_stat == 8) ?
1322 *(uint64_t *)p : *(uint32_t *)p;
1323 }
1324 }
1325
1326 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1327 {
1328 if (sset == ETH_SS_STATS)
1329 return ARRAY_SIZE(mv643xx_eth_stats);
1330
1331 return -EOPNOTSUPP;
1332 }
1333
1334 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1335 .get_settings = mv643xx_eth_get_settings,
1336 .set_settings = mv643xx_eth_set_settings,
1337 .get_drvinfo = mv643xx_eth_get_drvinfo,
1338 .nway_reset = mv643xx_eth_nway_reset,
1339 .get_link = mv643xx_eth_get_link,
1340 .set_sg = ethtool_op_set_sg,
1341 .get_strings = mv643xx_eth_get_strings,
1342 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1343 .get_sset_count = mv643xx_eth_get_sset_count,
1344 };
1345
1346 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1347 .get_settings = mv643xx_eth_get_settings_phyless,
1348 .set_settings = mv643xx_eth_set_settings_phyless,
1349 .get_drvinfo = mv643xx_eth_get_drvinfo,
1350 .nway_reset = mv643xx_eth_nway_reset_phyless,
1351 .get_link = mv643xx_eth_get_link_phyless,
1352 .set_sg = ethtool_op_set_sg,
1353 .get_strings = mv643xx_eth_get_strings,
1354 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1355 .get_sset_count = mv643xx_eth_get_sset_count,
1356 };
1357
1358
1359 /* address handling *********************************************************/
1360 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1361 {
1362 unsigned int mac_h;
1363 unsigned int mac_l;
1364
1365 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1366 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1367
1368 addr[0] = (mac_h >> 24) & 0xff;
1369 addr[1] = (mac_h >> 16) & 0xff;
1370 addr[2] = (mac_h >> 8) & 0xff;
1371 addr[3] = mac_h & 0xff;
1372 addr[4] = (mac_l >> 8) & 0xff;
1373 addr[5] = mac_l & 0xff;
1374 }
1375
1376 static void init_mac_tables(struct mv643xx_eth_private *mp)
1377 {
1378 int i;
1379
1380 for (i = 0; i < 0x100; i += 4) {
1381 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1382 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1383 }
1384
1385 for (i = 0; i < 0x10; i += 4)
1386 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1387 }
1388
1389 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1390 int table, unsigned char entry)
1391 {
1392 unsigned int table_reg;
1393
1394 /* Set "accepts frame bit" at specified table entry */
1395 table_reg = rdl(mp, table + (entry & 0xfc));
1396 table_reg |= 0x01 << (8 * (entry & 3));
1397 wrl(mp, table + (entry & 0xfc), table_reg);
1398 }
1399
1400 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1401 {
1402 unsigned int mac_h;
1403 unsigned int mac_l;
1404 int table;
1405
1406 mac_l = (addr[4] << 8) | addr[5];
1407 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1408
1409 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1410 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1411
1412 table = UNICAST_TABLE(mp->port_num);
1413 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1414 }
1415
1416 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1417 {
1418 struct mv643xx_eth_private *mp = netdev_priv(dev);
1419
1420 /* +2 is for the offset of the HW addr type */
1421 memcpy(dev->dev_addr, addr + 2, 6);
1422
1423 init_mac_tables(mp);
1424 uc_addr_set(mp, dev->dev_addr);
1425
1426 return 0;
1427 }
1428
1429 static int addr_crc(unsigned char *addr)
1430 {
1431 int crc = 0;
1432 int i;
1433
1434 for (i = 0; i < 6; i++) {
1435 int j;
1436
1437 crc = (crc ^ addr[i]) << 8;
1438 for (j = 7; j >= 0; j--) {
1439 if (crc & (0x100 << j))
1440 crc ^= 0x107 << j;
1441 }
1442 }
1443
1444 return crc;
1445 }
1446
1447 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1448 {
1449 struct mv643xx_eth_private *mp = netdev_priv(dev);
1450 u32 port_config;
1451 struct dev_addr_list *addr;
1452 int i;
1453
1454 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1455 if (dev->flags & IFF_PROMISC)
1456 port_config |= UNICAST_PROMISCUOUS_MODE;
1457 else
1458 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1459 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1460
1461 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1462 int port_num = mp->port_num;
1463 u32 accept = 0x01010101;
1464
1465 for (i = 0; i < 0x100; i += 4) {
1466 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1467 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1468 }
1469 return;
1470 }
1471
1472 for (i = 0; i < 0x100; i += 4) {
1473 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1474 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1475 }
1476
1477 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1478 u8 *a = addr->da_addr;
1479 int table;
1480
1481 if (addr->da_addrlen != 6)
1482 continue;
1483
1484 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1485 table = SPECIAL_MCAST_TABLE(mp->port_num);
1486 set_filter_table_entry(mp, table, a[5]);
1487 } else {
1488 int crc = addr_crc(a);
1489
1490 table = OTHER_MCAST_TABLE(mp->port_num);
1491 set_filter_table_entry(mp, table, crc);
1492 }
1493 }
1494 }
1495
1496
1497 /* rx/tx queue initialisation ***********************************************/
1498 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1499 {
1500 struct rx_queue *rxq = mp->rxq + index;
1501 struct rx_desc *rx_desc;
1502 int size;
1503 int i;
1504
1505 rxq->index = index;
1506
1507 rxq->rx_ring_size = mp->default_rx_ring_size;
1508
1509 rxq->rx_desc_count = 0;
1510 rxq->rx_curr_desc = 0;
1511 rxq->rx_used_desc = 0;
1512
1513 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1514
1515 if (index == 0 && size <= mp->rx_desc_sram_size) {
1516 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1517 mp->rx_desc_sram_size);
1518 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1519 } else {
1520 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1521 &rxq->rx_desc_dma,
1522 GFP_KERNEL);
1523 }
1524
1525 if (rxq->rx_desc_area == NULL) {
1526 dev_printk(KERN_ERR, &mp->dev->dev,
1527 "can't allocate rx ring (%d bytes)\n", size);
1528 goto out;
1529 }
1530 memset(rxq->rx_desc_area, 0, size);
1531
1532 rxq->rx_desc_area_size = size;
1533 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1534 GFP_KERNEL);
1535 if (rxq->rx_skb == NULL) {
1536 dev_printk(KERN_ERR, &mp->dev->dev,
1537 "can't allocate rx skb ring\n");
1538 goto out_free;
1539 }
1540
1541 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1542 for (i = 0; i < rxq->rx_ring_size; i++) {
1543 int nexti;
1544
1545 nexti = i + 1;
1546 if (nexti == rxq->rx_ring_size)
1547 nexti = 0;
1548
1549 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1550 nexti * sizeof(struct rx_desc);
1551 }
1552
1553 return 0;
1554
1555
1556 out_free:
1557 if (index == 0 && size <= mp->rx_desc_sram_size)
1558 iounmap(rxq->rx_desc_area);
1559 else
1560 dma_free_coherent(NULL, size,
1561 rxq->rx_desc_area,
1562 rxq->rx_desc_dma);
1563
1564 out:
1565 return -ENOMEM;
1566 }
1567
1568 static void rxq_deinit(struct rx_queue *rxq)
1569 {
1570 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1571 int i;
1572
1573 rxq_disable(rxq);
1574
1575 for (i = 0; i < rxq->rx_ring_size; i++) {
1576 if (rxq->rx_skb[i]) {
1577 dev_kfree_skb(rxq->rx_skb[i]);
1578 rxq->rx_desc_count--;
1579 }
1580 }
1581
1582 if (rxq->rx_desc_count) {
1583 dev_printk(KERN_ERR, &mp->dev->dev,
1584 "error freeing rx ring -- %d skbs stuck\n",
1585 rxq->rx_desc_count);
1586 }
1587
1588 if (rxq->index == 0 &&
1589 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1590 iounmap(rxq->rx_desc_area);
1591 else
1592 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1593 rxq->rx_desc_area, rxq->rx_desc_dma);
1594
1595 kfree(rxq->rx_skb);
1596 }
1597
1598 static int txq_init(struct mv643xx_eth_private *mp, int index)
1599 {
1600 struct tx_queue *txq = mp->txq + index;
1601 struct tx_desc *tx_desc;
1602 int size;
1603 int i;
1604
1605 txq->index = index;
1606
1607 txq->tx_ring_size = mp->default_tx_ring_size;
1608
1609 txq->tx_desc_count = 0;
1610 txq->tx_curr_desc = 0;
1611 txq->tx_used_desc = 0;
1612
1613 size = txq->tx_ring_size * sizeof(struct tx_desc);
1614
1615 if (index == 0 && size <= mp->tx_desc_sram_size) {
1616 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1617 mp->tx_desc_sram_size);
1618 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1619 } else {
1620 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1621 &txq->tx_desc_dma,
1622 GFP_KERNEL);
1623 }
1624
1625 if (txq->tx_desc_area == NULL) {
1626 dev_printk(KERN_ERR, &mp->dev->dev,
1627 "can't allocate tx ring (%d bytes)\n", size);
1628 goto out;
1629 }
1630 memset(txq->tx_desc_area, 0, size);
1631
1632 txq->tx_desc_area_size = size;
1633 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1634 GFP_KERNEL);
1635 if (txq->tx_skb == NULL) {
1636 dev_printk(KERN_ERR, &mp->dev->dev,
1637 "can't allocate tx skb ring\n");
1638 goto out_free;
1639 }
1640
1641 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1642 for (i = 0; i < txq->tx_ring_size; i++) {
1643 struct tx_desc *txd = tx_desc + i;
1644 int nexti;
1645
1646 nexti = i + 1;
1647 if (nexti == txq->tx_ring_size)
1648 nexti = 0;
1649
1650 txd->cmd_sts = 0;
1651 txd->next_desc_ptr = txq->tx_desc_dma +
1652 nexti * sizeof(struct tx_desc);
1653 }
1654
1655 return 0;
1656
1657
1658 out_free:
1659 if (index == 0 && size <= mp->tx_desc_sram_size)
1660 iounmap(txq->tx_desc_area);
1661 else
1662 dma_free_coherent(NULL, size,
1663 txq->tx_desc_area,
1664 txq->tx_desc_dma);
1665
1666 out:
1667 return -ENOMEM;
1668 }
1669
1670 static void txq_reclaim(struct tx_queue *txq, int force)
1671 {
1672 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1673 unsigned long flags;
1674
1675 spin_lock_irqsave(&mp->lock, flags);
1676 while (txq->tx_desc_count > 0) {
1677 int tx_index;
1678 struct tx_desc *desc;
1679 u32 cmd_sts;
1680 struct sk_buff *skb;
1681 dma_addr_t addr;
1682 int count;
1683
1684 tx_index = txq->tx_used_desc;
1685 desc = &txq->tx_desc_area[tx_index];
1686 cmd_sts = desc->cmd_sts;
1687
1688 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1689 if (!force)
1690 break;
1691 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1692 }
1693
1694 txq->tx_used_desc = tx_index + 1;
1695 if (txq->tx_used_desc == txq->tx_ring_size)
1696 txq->tx_used_desc = 0;
1697 txq->tx_desc_count--;
1698
1699 addr = desc->buf_ptr;
1700 count = desc->byte_cnt;
1701 skb = txq->tx_skb[tx_index];
1702 txq->tx_skb[tx_index] = NULL;
1703
1704 if (cmd_sts & ERROR_SUMMARY) {
1705 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1706 mp->dev->stats.tx_errors++;
1707 }
1708
1709 /*
1710 * Drop mp->lock while we free the skb.
1711 */
1712 spin_unlock_irqrestore(&mp->lock, flags);
1713
1714 if (cmd_sts & TX_FIRST_DESC)
1715 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1716 else
1717 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1718
1719 if (skb)
1720 dev_kfree_skb_irq(skb);
1721
1722 spin_lock_irqsave(&mp->lock, flags);
1723 }
1724 spin_unlock_irqrestore(&mp->lock, flags);
1725 }
1726
1727 static void txq_deinit(struct tx_queue *txq)
1728 {
1729 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1730
1731 txq_disable(txq);
1732 txq_reclaim(txq, 1);
1733
1734 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1735
1736 if (txq->index == 0 &&
1737 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1738 iounmap(txq->tx_desc_area);
1739 else
1740 dma_free_coherent(NULL, txq->tx_desc_area_size,
1741 txq->tx_desc_area, txq->tx_desc_dma);
1742
1743 kfree(txq->tx_skb);
1744 }
1745
1746
1747 /* netdev ops and related ***************************************************/
1748 static void handle_link_event(struct mv643xx_eth_private *mp)
1749 {
1750 struct net_device *dev = mp->dev;
1751 u32 port_status;
1752 int speed;
1753 int duplex;
1754 int fc;
1755
1756 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1757 if (!(port_status & LINK_UP)) {
1758 if (netif_carrier_ok(dev)) {
1759 int i;
1760
1761 printk(KERN_INFO "%s: link down\n", dev->name);
1762
1763 netif_carrier_off(dev);
1764 netif_stop_queue(dev);
1765
1766 for (i = 0; i < mp->txq_count; i++) {
1767 struct tx_queue *txq = mp->txq + i;
1768
1769 txq_reclaim(txq, 1);
1770 txq_reset_hw_ptr(txq);
1771 }
1772 }
1773 return;
1774 }
1775
1776 switch (port_status & PORT_SPEED_MASK) {
1777 case PORT_SPEED_10:
1778 speed = 10;
1779 break;
1780 case PORT_SPEED_100:
1781 speed = 100;
1782 break;
1783 case PORT_SPEED_1000:
1784 speed = 1000;
1785 break;
1786 default:
1787 speed = -1;
1788 break;
1789 }
1790 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1791 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1792
1793 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1794 "flow control %sabled\n", dev->name,
1795 speed, duplex ? "full" : "half",
1796 fc ? "en" : "dis");
1797
1798 if (!netif_carrier_ok(dev)) {
1799 netif_carrier_on(dev);
1800 netif_wake_queue(dev);
1801 }
1802 }
1803
1804 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1805 {
1806 struct net_device *dev = (struct net_device *)dev_id;
1807 struct mv643xx_eth_private *mp = netdev_priv(dev);
1808 u32 int_cause;
1809 u32 int_cause_ext;
1810
1811 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1812 (INT_TX_END | INT_RX | INT_EXT);
1813 if (int_cause == 0)
1814 return IRQ_NONE;
1815
1816 int_cause_ext = 0;
1817 if (int_cause & INT_EXT) {
1818 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1819 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1820 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1821 }
1822
1823 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK))
1824 handle_link_event(mp);
1825
1826 /*
1827 * RxBuffer or RxError set for any of the 8 queues?
1828 */
1829 if (int_cause & INT_RX) {
1830 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_RX));
1831 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1832 rdl(mp, INT_MASK(mp->port_num));
1833
1834 napi_schedule(&mp->napi);
1835 }
1836
1837 /*
1838 * TxBuffer or TxError set for any of the 8 queues?
1839 */
1840 if (int_cause_ext & INT_EXT_TX) {
1841 int i;
1842
1843 for (i = 0; i < mp->txq_count; i++)
1844 txq_reclaim(mp->txq + i, 0);
1845
1846 /*
1847 * Enough space again in the primary TX queue for a
1848 * full packet?
1849 */
1850 if (netif_carrier_ok(dev)) {
1851 spin_lock(&mp->lock);
1852 __txq_maybe_wake(mp->txq);
1853 spin_unlock(&mp->lock);
1854 }
1855 }
1856
1857 /*
1858 * Any TxEnd interrupts?
1859 */
1860 if (int_cause & INT_TX_END) {
1861 int i;
1862
1863 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1864
1865 spin_lock(&mp->lock);
1866 for (i = 0; i < 8; i++) {
1867 struct tx_queue *txq = mp->txq + i;
1868 u32 hw_desc_ptr;
1869 u32 expected_ptr;
1870
1871 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1872 continue;
1873
1874 hw_desc_ptr =
1875 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1876 expected_ptr = (u32)txq->tx_desc_dma +
1877 txq->tx_curr_desc * sizeof(struct tx_desc);
1878
1879 if (hw_desc_ptr != expected_ptr)
1880 txq_enable(txq);
1881 }
1882 spin_unlock(&mp->lock);
1883 }
1884
1885 return IRQ_HANDLED;
1886 }
1887
1888 static void phy_reset(struct mv643xx_eth_private *mp)
1889 {
1890 int data;
1891
1892 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1893 if (data < 0)
1894 return;
1895
1896 data |= BMCR_RESET;
1897 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1898 return;
1899
1900 do {
1901 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1902 } while (data >= 0 && data & BMCR_RESET);
1903 }
1904
1905 static void port_start(struct mv643xx_eth_private *mp)
1906 {
1907 u32 pscr;
1908 int i;
1909
1910 /*
1911 * Perform PHY reset, if there is a PHY.
1912 */
1913 if (mp->phy_addr != -1) {
1914 struct ethtool_cmd cmd;
1915
1916 mv643xx_eth_get_settings(mp->dev, &cmd);
1917 phy_reset(mp);
1918 mv643xx_eth_set_settings(mp->dev, &cmd);
1919 }
1920
1921 /*
1922 * Configure basic link parameters.
1923 */
1924 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1925
1926 pscr |= SERIAL_PORT_ENABLE;
1927 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1928
1929 pscr |= DO_NOT_FORCE_LINK_FAIL;
1930 if (mp->phy_addr == -1)
1931 pscr |= FORCE_LINK_PASS;
1932 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1933
1934 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1935
1936 /*
1937 * Configure TX path and queues.
1938 */
1939 tx_set_rate(mp, 1000000000, 16777216);
1940 for (i = 0; i < mp->txq_count; i++) {
1941 struct tx_queue *txq = mp->txq + i;
1942
1943 txq_reset_hw_ptr(txq);
1944 txq_set_rate(txq, 1000000000, 16777216);
1945 txq_set_fixed_prio_mode(txq);
1946 }
1947
1948 /*
1949 * Add configured unicast address to address filter table.
1950 */
1951 uc_addr_set(mp, mp->dev->dev_addr);
1952
1953 /*
1954 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1955 * frames to RX queue #0.
1956 */
1957 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1958
1959 /*
1960 * Treat BPDUs as normal multicasts, and disable partition mode.
1961 */
1962 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1963
1964 /*
1965 * Enable the receive queues.
1966 */
1967 for (i = 0; i < mp->rxq_count; i++) {
1968 struct rx_queue *rxq = mp->rxq + i;
1969 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1970 u32 addr;
1971
1972 addr = (u32)rxq->rx_desc_dma;
1973 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1974 wrl(mp, off, addr);
1975
1976 rxq_enable(rxq);
1977 }
1978 }
1979
1980 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1981 {
1982 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1983 u32 val;
1984
1985 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1986 if (mp->shared->extended_rx_coal_limit) {
1987 if (coal > 0xffff)
1988 coal = 0xffff;
1989 val &= ~0x023fff80;
1990 val |= (coal & 0x8000) << 10;
1991 val |= (coal & 0x7fff) << 7;
1992 } else {
1993 if (coal > 0x3fff)
1994 coal = 0x3fff;
1995 val &= ~0x003fff00;
1996 val |= (coal & 0x3fff) << 8;
1997 }
1998 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1999 }
2000
2001 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2002 {
2003 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2004
2005 if (coal > 0x3fff)
2006 coal = 0x3fff;
2007 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2008 }
2009
2010 static int mv643xx_eth_open(struct net_device *dev)
2011 {
2012 struct mv643xx_eth_private *mp = netdev_priv(dev);
2013 int err;
2014 int oom;
2015 int i;
2016
2017 wrl(mp, INT_CAUSE(mp->port_num), 0);
2018 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2019 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2020
2021 err = request_irq(dev->irq, mv643xx_eth_irq,
2022 IRQF_SHARED, dev->name, dev);
2023 if (err) {
2024 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2025 return -EAGAIN;
2026 }
2027
2028 init_mac_tables(mp);
2029
2030 napi_enable(&mp->napi);
2031
2032 oom = 0;
2033 for (i = 0; i < mp->rxq_count; i++) {
2034 err = rxq_init(mp, i);
2035 if (err) {
2036 while (--i >= 0)
2037 rxq_deinit(mp->rxq + i);
2038 goto out;
2039 }
2040
2041 rxq_refill(mp->rxq + i, INT_MAX, &oom);
2042 }
2043
2044 if (oom) {
2045 mp->rx_oom.expires = jiffies + (HZ / 10);
2046 add_timer(&mp->rx_oom);
2047 }
2048
2049 for (i = 0; i < mp->txq_count; i++) {
2050 err = txq_init(mp, i);
2051 if (err) {
2052 while (--i >= 0)
2053 txq_deinit(mp->txq + i);
2054 goto out_free;
2055 }
2056 }
2057
2058 netif_carrier_off(dev);
2059 netif_stop_queue(dev);
2060
2061 port_start(mp);
2062
2063 set_rx_coal(mp, 0);
2064 set_tx_coal(mp, 0);
2065
2066 wrl(mp, INT_MASK_EXT(mp->port_num),
2067 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2068
2069 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2070
2071 return 0;
2072
2073
2074 out_free:
2075 for (i = 0; i < mp->rxq_count; i++)
2076 rxq_deinit(mp->rxq + i);
2077 out:
2078 free_irq(dev->irq, dev);
2079
2080 return err;
2081 }
2082
2083 static void port_reset(struct mv643xx_eth_private *mp)
2084 {
2085 unsigned int data;
2086 int i;
2087
2088 for (i = 0; i < mp->rxq_count; i++)
2089 rxq_disable(mp->rxq + i);
2090 for (i = 0; i < mp->txq_count; i++)
2091 txq_disable(mp->txq + i);
2092
2093 while (1) {
2094 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2095
2096 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2097 break;
2098 udelay(10);
2099 }
2100
2101 /* Reset the Enable bit in the Configuration Register */
2102 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2103 data &= ~(SERIAL_PORT_ENABLE |
2104 DO_NOT_FORCE_LINK_FAIL |
2105 FORCE_LINK_PASS);
2106 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2107 }
2108
2109 static int mv643xx_eth_stop(struct net_device *dev)
2110 {
2111 struct mv643xx_eth_private *mp = netdev_priv(dev);
2112 int i;
2113
2114 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2115 rdl(mp, INT_MASK(mp->port_num));
2116
2117 napi_disable(&mp->napi);
2118
2119 del_timer_sync(&mp->rx_oom);
2120
2121 netif_carrier_off(dev);
2122 netif_stop_queue(dev);
2123
2124 free_irq(dev->irq, dev);
2125
2126 port_reset(mp);
2127 mib_counters_update(mp);
2128
2129 for (i = 0; i < mp->rxq_count; i++)
2130 rxq_deinit(mp->rxq + i);
2131 for (i = 0; i < mp->txq_count; i++)
2132 txq_deinit(mp->txq + i);
2133
2134 return 0;
2135 }
2136
2137 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2138 {
2139 struct mv643xx_eth_private *mp = netdev_priv(dev);
2140
2141 if (mp->phy_addr != -1)
2142 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2143
2144 return -EOPNOTSUPP;
2145 }
2146
2147 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2148 {
2149 struct mv643xx_eth_private *mp = netdev_priv(dev);
2150
2151 if (new_mtu < 64 || new_mtu > 9500)
2152 return -EINVAL;
2153
2154 dev->mtu = new_mtu;
2155 tx_set_rate(mp, 1000000000, 16777216);
2156
2157 if (!netif_running(dev))
2158 return 0;
2159
2160 /*
2161 * Stop and then re-open the interface. This will allocate RX
2162 * skbs of the new MTU.
2163 * There is a possible danger that the open will not succeed,
2164 * due to memory being full.
2165 */
2166 mv643xx_eth_stop(dev);
2167 if (mv643xx_eth_open(dev)) {
2168 dev_printk(KERN_ERR, &dev->dev,
2169 "fatal error on re-opening device after "
2170 "MTU change\n");
2171 }
2172
2173 return 0;
2174 }
2175
2176 static void tx_timeout_task(struct work_struct *ugly)
2177 {
2178 struct mv643xx_eth_private *mp;
2179
2180 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2181 if (netif_running(mp->dev)) {
2182 netif_stop_queue(mp->dev);
2183
2184 port_reset(mp);
2185 port_start(mp);
2186
2187 __txq_maybe_wake(mp->txq);
2188 }
2189 }
2190
2191 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2192 {
2193 struct mv643xx_eth_private *mp = netdev_priv(dev);
2194
2195 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2196
2197 schedule_work(&mp->tx_timeout_task);
2198 }
2199
2200 #ifdef CONFIG_NET_POLL_CONTROLLER
2201 static void mv643xx_eth_netpoll(struct net_device *dev)
2202 {
2203 struct mv643xx_eth_private *mp = netdev_priv(dev);
2204
2205 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2206 rdl(mp, INT_MASK(mp->port_num));
2207
2208 mv643xx_eth_irq(dev->irq, dev);
2209
2210 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2211 }
2212 #endif
2213
2214 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2215 {
2216 struct mv643xx_eth_private *mp = netdev_priv(dev);
2217 return smi_reg_read(mp, addr, reg);
2218 }
2219
2220 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2221 {
2222 struct mv643xx_eth_private *mp = netdev_priv(dev);
2223 smi_reg_write(mp, addr, reg, val);
2224 }
2225
2226
2227 /* platform glue ************************************************************/
2228 static void
2229 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2230 struct mbus_dram_target_info *dram)
2231 {
2232 void __iomem *base = msp->base;
2233 u32 win_enable;
2234 u32 win_protect;
2235 int i;
2236
2237 for (i = 0; i < 6; i++) {
2238 writel(0, base + WINDOW_BASE(i));
2239 writel(0, base + WINDOW_SIZE(i));
2240 if (i < 4)
2241 writel(0, base + WINDOW_REMAP_HIGH(i));
2242 }
2243
2244 win_enable = 0x3f;
2245 win_protect = 0;
2246
2247 for (i = 0; i < dram->num_cs; i++) {
2248 struct mbus_dram_window *cs = dram->cs + i;
2249
2250 writel((cs->base & 0xffff0000) |
2251 (cs->mbus_attr << 8) |
2252 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2253 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2254
2255 win_enable &= ~(1 << i);
2256 win_protect |= 3 << (2 * i);
2257 }
2258
2259 writel(win_enable, base + WINDOW_BAR_ENABLE);
2260 msp->win_protect = win_protect;
2261 }
2262
2263 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2264 {
2265 /*
2266 * Check whether we have a 14-bit coal limit field in bits
2267 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2268 * SDMA config register.
2269 */
2270 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2271 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2272 msp->extended_rx_coal_limit = 1;
2273 else
2274 msp->extended_rx_coal_limit = 0;
2275
2276 /*
2277 * Check whether the TX rate control registers are in the
2278 * old or the new place.
2279 */
2280 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2281 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2282 msp->tx_bw_control_moved = 1;
2283 else
2284 msp->tx_bw_control_moved = 0;
2285 }
2286
2287 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2288 {
2289 static int mv643xx_eth_version_printed = 0;
2290 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2291 struct mv643xx_eth_shared_private *msp;
2292 struct resource *res;
2293 int ret;
2294
2295 if (!mv643xx_eth_version_printed++)
2296 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2297 "driver version %s\n", mv643xx_eth_driver_version);
2298
2299 ret = -EINVAL;
2300 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2301 if (res == NULL)
2302 goto out;
2303
2304 ret = -ENOMEM;
2305 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2306 if (msp == NULL)
2307 goto out;
2308 memset(msp, 0, sizeof(*msp));
2309
2310 msp->base = ioremap(res->start, res->end - res->start + 1);
2311 if (msp->base == NULL)
2312 goto out_free;
2313
2314 mutex_init(&msp->phy_lock);
2315
2316 msp->err_interrupt = NO_IRQ;
2317 init_waitqueue_head(&msp->smi_busy_wait);
2318
2319 /*
2320 * Check whether the error interrupt is hooked up.
2321 */
2322 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2323 if (res != NULL) {
2324 int err;
2325
2326 err = request_irq(res->start, mv643xx_eth_err_irq,
2327 IRQF_SHARED, "mv643xx_eth", msp);
2328 if (!err) {
2329 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2330 msp->err_interrupt = res->start;
2331 }
2332 }
2333
2334 /*
2335 * (Re-)program MBUS remapping windows if we are asked to.
2336 */
2337 if (pd != NULL && pd->dram != NULL)
2338 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2339
2340 /*
2341 * Detect hardware parameters.
2342 */
2343 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2344 infer_hw_params(msp);
2345
2346 platform_set_drvdata(pdev, msp);
2347
2348 return 0;
2349
2350 out_free:
2351 kfree(msp);
2352 out:
2353 return ret;
2354 }
2355
2356 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2357 {
2358 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2359
2360 if (msp->err_interrupt != NO_IRQ)
2361 free_irq(msp->err_interrupt, msp);
2362 iounmap(msp->base);
2363 kfree(msp);
2364
2365 return 0;
2366 }
2367
2368 static struct platform_driver mv643xx_eth_shared_driver = {
2369 .probe = mv643xx_eth_shared_probe,
2370 .remove = mv643xx_eth_shared_remove,
2371 .driver = {
2372 .name = MV643XX_ETH_SHARED_NAME,
2373 .owner = THIS_MODULE,
2374 },
2375 };
2376
2377 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2378 {
2379 int addr_shift = 5 * mp->port_num;
2380 u32 data;
2381
2382 data = rdl(mp, PHY_ADDR);
2383 data &= ~(0x1f << addr_shift);
2384 data |= (phy_addr & 0x1f) << addr_shift;
2385 wrl(mp, PHY_ADDR, data);
2386 }
2387
2388 static int phy_addr_get(struct mv643xx_eth_private *mp)
2389 {
2390 unsigned int data;
2391
2392 data = rdl(mp, PHY_ADDR);
2393
2394 return (data >> (5 * mp->port_num)) & 0x1f;
2395 }
2396
2397 static void set_params(struct mv643xx_eth_private *mp,
2398 struct mv643xx_eth_platform_data *pd)
2399 {
2400 struct net_device *dev = mp->dev;
2401
2402 if (is_valid_ether_addr(pd->mac_addr))
2403 memcpy(dev->dev_addr, pd->mac_addr, 6);
2404 else
2405 uc_addr_get(mp, dev->dev_addr);
2406
2407 if (pd->phy_addr == -1) {
2408 mp->shared_smi = NULL;
2409 mp->phy_addr = -1;
2410 } else {
2411 mp->shared_smi = mp->shared;
2412 if (pd->shared_smi != NULL)
2413 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2414
2415 if (pd->force_phy_addr || pd->phy_addr) {
2416 mp->phy_addr = pd->phy_addr & 0x3f;
2417 phy_addr_set(mp, mp->phy_addr);
2418 } else {
2419 mp->phy_addr = phy_addr_get(mp);
2420 }
2421 }
2422
2423 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2424 if (pd->rx_queue_size)
2425 mp->default_rx_ring_size = pd->rx_queue_size;
2426 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2427 mp->rx_desc_sram_size = pd->rx_sram_size;
2428
2429 mp->rxq_count = pd->rx_queue_count ? : 1;
2430
2431 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2432 if (pd->tx_queue_size)
2433 mp->default_tx_ring_size = pd->tx_queue_size;
2434 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2435 mp->tx_desc_sram_size = pd->tx_sram_size;
2436
2437 mp->txq_count = pd->tx_queue_count ? : 1;
2438 }
2439
2440 static int phy_detect(struct mv643xx_eth_private *mp)
2441 {
2442 int data;
2443 int data2;
2444
2445 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2446 if (data < 0)
2447 return -ENODEV;
2448
2449 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2450 return -ENODEV;
2451
2452 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2453 if (data2 < 0)
2454 return -ENODEV;
2455
2456 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2457 return -ENODEV;
2458
2459 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2460
2461 return 0;
2462 }
2463
2464 static int phy_init(struct mv643xx_eth_private *mp,
2465 struct mv643xx_eth_platform_data *pd)
2466 {
2467 struct ethtool_cmd cmd;
2468 int err;
2469
2470 err = phy_detect(mp);
2471 if (err) {
2472 dev_printk(KERN_INFO, &mp->dev->dev,
2473 "no PHY detected at addr %d\n", mp->phy_addr);
2474 return err;
2475 }
2476 phy_reset(mp);
2477
2478 mp->mii.phy_id = mp->phy_addr;
2479 mp->mii.phy_id_mask = 0x3f;
2480 mp->mii.reg_num_mask = 0x1f;
2481 mp->mii.dev = mp->dev;
2482 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2483 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2484
2485 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2486
2487 memset(&cmd, 0, sizeof(cmd));
2488
2489 cmd.port = PORT_MII;
2490 cmd.transceiver = XCVR_INTERNAL;
2491 cmd.phy_address = mp->phy_addr;
2492 if (pd->speed == 0) {
2493 cmd.autoneg = AUTONEG_ENABLE;
2494 cmd.speed = SPEED_100;
2495 cmd.advertising = ADVERTISED_10baseT_Half |
2496 ADVERTISED_10baseT_Full |
2497 ADVERTISED_100baseT_Half |
2498 ADVERTISED_100baseT_Full;
2499 if (mp->mii.supports_gmii)
2500 cmd.advertising |= ADVERTISED_1000baseT_Full;
2501 } else {
2502 cmd.autoneg = AUTONEG_DISABLE;
2503 cmd.speed = pd->speed;
2504 cmd.duplex = pd->duplex;
2505 }
2506
2507 mv643xx_eth_set_settings(mp->dev, &cmd);
2508
2509 return 0;
2510 }
2511
2512 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2513 {
2514 u32 pscr;
2515
2516 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2517 if (pscr & SERIAL_PORT_ENABLE) {
2518 pscr &= ~SERIAL_PORT_ENABLE;
2519 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2520 }
2521
2522 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2523 if (mp->phy_addr == -1) {
2524 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2525 if (speed == SPEED_1000)
2526 pscr |= SET_GMII_SPEED_TO_1000;
2527 else if (speed == SPEED_100)
2528 pscr |= SET_MII_SPEED_TO_100;
2529
2530 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2531
2532 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2533 if (duplex == DUPLEX_FULL)
2534 pscr |= SET_FULL_DUPLEX_MODE;
2535 }
2536
2537 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2538 }
2539
2540 static int mv643xx_eth_probe(struct platform_device *pdev)
2541 {
2542 struct mv643xx_eth_platform_data *pd;
2543 struct mv643xx_eth_private *mp;
2544 struct net_device *dev;
2545 struct resource *res;
2546 DECLARE_MAC_BUF(mac);
2547 int err;
2548
2549 pd = pdev->dev.platform_data;
2550 if (pd == NULL) {
2551 dev_printk(KERN_ERR, &pdev->dev,
2552 "no mv643xx_eth_platform_data\n");
2553 return -ENODEV;
2554 }
2555
2556 if (pd->shared == NULL) {
2557 dev_printk(KERN_ERR, &pdev->dev,
2558 "no mv643xx_eth_platform_data->shared\n");
2559 return -ENODEV;
2560 }
2561
2562 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2563 if (!dev)
2564 return -ENOMEM;
2565
2566 mp = netdev_priv(dev);
2567 platform_set_drvdata(pdev, mp);
2568
2569 mp->shared = platform_get_drvdata(pd->shared);
2570 mp->port_num = pd->port_number;
2571
2572 mp->dev = dev;
2573
2574 set_params(mp, pd);
2575
2576 spin_lock_init(&mp->lock);
2577
2578 mib_counters_clear(mp);
2579 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2580
2581 if (mp->phy_addr != -1) {
2582 err = phy_init(mp, pd);
2583 if (err)
2584 goto out;
2585
2586 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2587 } else {
2588 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2589 }
2590 init_pscr(mp, pd->speed, pd->duplex);
2591
2592 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2593
2594 init_timer(&mp->rx_oom);
2595 mp->rx_oom.data = (unsigned long)mp;
2596 mp->rx_oom.function = oom_timer_wrapper;
2597
2598
2599 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2600 BUG_ON(!res);
2601 dev->irq = res->start;
2602
2603 dev->hard_start_xmit = mv643xx_eth_xmit;
2604 dev->open = mv643xx_eth_open;
2605 dev->stop = mv643xx_eth_stop;
2606 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2607 dev->set_mac_address = mv643xx_eth_set_mac_address;
2608 dev->do_ioctl = mv643xx_eth_ioctl;
2609 dev->change_mtu = mv643xx_eth_change_mtu;
2610 dev->tx_timeout = mv643xx_eth_tx_timeout;
2611 #ifdef CONFIG_NET_POLL_CONTROLLER
2612 dev->poll_controller = mv643xx_eth_netpoll;
2613 #endif
2614 dev->watchdog_timeo = 2 * HZ;
2615 dev->base_addr = 0;
2616
2617 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2618 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2619
2620 SET_NETDEV_DEV(dev, &pdev->dev);
2621
2622 if (mp->shared->win_protect)
2623 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2624
2625 err = register_netdev(dev);
2626 if (err)
2627 goto out;
2628
2629 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2630 mp->port_num, print_mac(mac, dev->dev_addr));
2631
2632 if (mp->tx_desc_sram_size > 0)
2633 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2634
2635 return 0;
2636
2637 out:
2638 free_netdev(dev);
2639
2640 return err;
2641 }
2642
2643 static int mv643xx_eth_remove(struct platform_device *pdev)
2644 {
2645 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2646
2647 unregister_netdev(mp->dev);
2648 flush_scheduled_work();
2649 free_netdev(mp->dev);
2650
2651 platform_set_drvdata(pdev, NULL);
2652
2653 return 0;
2654 }
2655
2656 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2657 {
2658 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2659
2660 /* Mask all interrupts on ethernet port */
2661 wrl(mp, INT_MASK(mp->port_num), 0);
2662 rdl(mp, INT_MASK(mp->port_num));
2663
2664 if (netif_running(mp->dev))
2665 port_reset(mp);
2666 }
2667
2668 static struct platform_driver mv643xx_eth_driver = {
2669 .probe = mv643xx_eth_probe,
2670 .remove = mv643xx_eth_remove,
2671 .shutdown = mv643xx_eth_shutdown,
2672 .driver = {
2673 .name = MV643XX_ETH_NAME,
2674 .owner = THIS_MODULE,
2675 },
2676 };
2677
2678 static int __init mv643xx_eth_init_module(void)
2679 {
2680 int rc;
2681
2682 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2683 if (!rc) {
2684 rc = platform_driver_register(&mv643xx_eth_driver);
2685 if (rc)
2686 platform_driver_unregister(&mv643xx_eth_shared_driver);
2687 }
2688
2689 return rc;
2690 }
2691 module_init(mv643xx_eth_init_module);
2692
2693 static void __exit mv643xx_eth_cleanup_module(void)
2694 {
2695 platform_driver_unregister(&mv643xx_eth_driver);
2696 platform_driver_unregister(&mv643xx_eth_shared_driver);
2697 }
2698 module_exit(mv643xx_eth_cleanup_module);
2699
2700 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2701 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2702 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2703 MODULE_LICENSE("GPL");
2704 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2705 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
kernel source for telekom puls (alcatel/mediatek)