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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / mv643xx_eth.c
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
37
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/in.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
53 #include <asm/io.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
56
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.3";
59
60 #define MV643XX_ETH_TX_FAST_REFILL
61
62 /*
63 * Registers shared between all ports.
64 */
65 #define PHY_ADDR 0x0000
66 #define SMI_REG 0x0004
67 #define SMI_BUSY 0x10000000
68 #define SMI_READ_VALID 0x08000000
69 #define SMI_OPCODE_READ 0x04000000
70 #define SMI_OPCODE_WRITE 0x00000000
71 #define ERR_INT_CAUSE 0x0080
72 #define ERR_INT_SMI_DONE 0x00000010
73 #define ERR_INT_MASK 0x0084
74 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77 #define WINDOW_BAR_ENABLE 0x0290
78 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
79
80 /*
81 * Per-port registers.
82 */
83 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
84 #define UNICAST_PROMISCUOUS_MODE 0x00000001
85 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
86 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
87 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
88 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
89 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
90 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
91 #define TX_FIFO_EMPTY 0x00000400
92 #define TX_IN_PROGRESS 0x00000080
93 #define PORT_SPEED_MASK 0x00000030
94 #define PORT_SPEED_1000 0x00000010
95 #define PORT_SPEED_100 0x00000020
96 #define PORT_SPEED_10 0x00000000
97 #define FLOW_CONTROL_ENABLED 0x00000008
98 #define FULL_DUPLEX 0x00000004
99 #define LINK_UP 0x00000002
100 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
101 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
102 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
103 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
104 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
105 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
106 #define INT_TX_END_0 0x00080000
107 #define INT_TX_END 0x07f80000
108 #define INT_RX 0x0007fbfc
109 #define INT_EXT 0x00000002
110 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
111 #define INT_EXT_LINK 0x00100000
112 #define INT_EXT_PHY 0x00010000
113 #define INT_EXT_TX_ERROR_0 0x00000100
114 #define INT_EXT_TX_0 0x00000001
115 #define INT_EXT_TX 0x0000ffff
116 #define INT_MASK(p) (0x0468 + ((p) << 10))
117 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
118 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
119 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
120 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
121 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
122 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
123 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
124 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
125 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
126 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
127 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
128 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
129 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
130 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
131 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
132 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
133
134
135 /*
136 * SDMA configuration register.
137 */
138 #define RX_BURST_SIZE_16_64BIT (4 << 1)
139 #define BLM_RX_NO_SWAP (1 << 4)
140 #define BLM_TX_NO_SWAP (1 << 5)
141 #define TX_BURST_SIZE_16_64BIT (4 << 22)
142
143 #if defined(__BIG_ENDIAN)
144 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
145 RX_BURST_SIZE_16_64BIT | \
146 TX_BURST_SIZE_16_64BIT
147 #elif defined(__LITTLE_ENDIAN)
148 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
149 RX_BURST_SIZE_16_64BIT | \
150 BLM_RX_NO_SWAP | \
151 BLM_TX_NO_SWAP | \
152 TX_BURST_SIZE_16_64BIT
153 #else
154 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
155 #endif
156
157
158 /*
159 * Port serial control register.
160 */
161 #define SET_MII_SPEED_TO_100 (1 << 24)
162 #define SET_GMII_SPEED_TO_1000 (1 << 23)
163 #define SET_FULL_DUPLEX_MODE (1 << 21)
164 #define MAX_RX_PACKET_9700BYTE (5 << 17)
165 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
166 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
167 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
168 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
169 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
170 #define FORCE_LINK_PASS (1 << 1)
171 #define SERIAL_PORT_ENABLE (1 << 0)
172
173 #define DEFAULT_RX_QUEUE_SIZE 400
174 #define DEFAULT_TX_QUEUE_SIZE 800
175
176
177 /*
178 * RX/TX descriptors.
179 */
180 #if defined(__BIG_ENDIAN)
181 struct rx_desc {
182 u16 byte_cnt; /* Descriptor buffer byte count */
183 u16 buf_size; /* Buffer size */
184 u32 cmd_sts; /* Descriptor command status */
185 u32 next_desc_ptr; /* Next descriptor pointer */
186 u32 buf_ptr; /* Descriptor buffer pointer */
187 };
188
189 struct tx_desc {
190 u16 byte_cnt; /* buffer byte count */
191 u16 l4i_chk; /* CPU provided TCP checksum */
192 u32 cmd_sts; /* Command/status field */
193 u32 next_desc_ptr; /* Pointer to next descriptor */
194 u32 buf_ptr; /* pointer to buffer for this descriptor*/
195 };
196 #elif defined(__LITTLE_ENDIAN)
197 struct rx_desc {
198 u32 cmd_sts; /* Descriptor command status */
199 u16 buf_size; /* Buffer size */
200 u16 byte_cnt; /* Descriptor buffer byte count */
201 u32 buf_ptr; /* Descriptor buffer pointer */
202 u32 next_desc_ptr; /* Next descriptor pointer */
203 };
204
205 struct tx_desc {
206 u32 cmd_sts; /* Command/status field */
207 u16 l4i_chk; /* CPU provided TCP checksum */
208 u16 byte_cnt; /* buffer byte count */
209 u32 buf_ptr; /* pointer to buffer for this descriptor*/
210 u32 next_desc_ptr; /* Pointer to next descriptor */
211 };
212 #else
213 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
214 #endif
215
216 /* RX & TX descriptor command */
217 #define BUFFER_OWNED_BY_DMA 0x80000000
218
219 /* RX & TX descriptor status */
220 #define ERROR_SUMMARY 0x00000001
221
222 /* RX descriptor status */
223 #define LAYER_4_CHECKSUM_OK 0x40000000
224 #define RX_ENABLE_INTERRUPT 0x20000000
225 #define RX_FIRST_DESC 0x08000000
226 #define RX_LAST_DESC 0x04000000
227
228 /* TX descriptor command */
229 #define TX_ENABLE_INTERRUPT 0x00800000
230 #define GEN_CRC 0x00400000
231 #define TX_FIRST_DESC 0x00200000
232 #define TX_LAST_DESC 0x00100000
233 #define ZERO_PADDING 0x00080000
234 #define GEN_IP_V4_CHECKSUM 0x00040000
235 #define GEN_TCP_UDP_CHECKSUM 0x00020000
236 #define UDP_FRAME 0x00010000
237 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
238 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
239
240 #define TX_IHL_SHIFT 11
241
242
243 /* global *******************************************************************/
244 struct mv643xx_eth_shared_private {
245 /*
246 * Ethernet controller base address.
247 */
248 void __iomem *base;
249
250 /*
251 * Protects access to SMI_REG, which is shared between ports.
252 */
253 struct mutex phy_lock;
254
255 /*
256 * If we have access to the error interrupt pin (which is
257 * somewhat misnamed as it not only reflects internal errors
258 * but also reflects SMI completion), use that to wait for
259 * SMI access completion instead of polling the SMI busy bit.
260 */
261 int err_interrupt;
262 wait_queue_head_t smi_busy_wait;
263
264 /*
265 * Per-port MBUS window access register value.
266 */
267 u32 win_protect;
268
269 /*
270 * Hardware-specific parameters.
271 */
272 unsigned int t_clk;
273 int extended_rx_coal_limit;
274 int tx_bw_control_moved;
275 };
276
277
278 /* per-port *****************************************************************/
279 struct mib_counters {
280 u64 good_octets_received;
281 u32 bad_octets_received;
282 u32 internal_mac_transmit_err;
283 u32 good_frames_received;
284 u32 bad_frames_received;
285 u32 broadcast_frames_received;
286 u32 multicast_frames_received;
287 u32 frames_64_octets;
288 u32 frames_65_to_127_octets;
289 u32 frames_128_to_255_octets;
290 u32 frames_256_to_511_octets;
291 u32 frames_512_to_1023_octets;
292 u32 frames_1024_to_max_octets;
293 u64 good_octets_sent;
294 u32 good_frames_sent;
295 u32 excessive_collision;
296 u32 multicast_frames_sent;
297 u32 broadcast_frames_sent;
298 u32 unrec_mac_control_received;
299 u32 fc_sent;
300 u32 good_fc_received;
301 u32 bad_fc_received;
302 u32 undersize_received;
303 u32 fragments_received;
304 u32 oversize_received;
305 u32 jabber_received;
306 u32 mac_receive_error;
307 u32 bad_crc_event;
308 u32 collision;
309 u32 late_collision;
310 };
311
312 struct rx_queue {
313 int index;
314
315 int rx_ring_size;
316
317 int rx_desc_count;
318 int rx_curr_desc;
319 int rx_used_desc;
320
321 struct rx_desc *rx_desc_area;
322 dma_addr_t rx_desc_dma;
323 int rx_desc_area_size;
324 struct sk_buff **rx_skb;
325 };
326
327 struct tx_queue {
328 int index;
329
330 int tx_ring_size;
331
332 int tx_desc_count;
333 int tx_curr_desc;
334 int tx_used_desc;
335
336 struct tx_desc *tx_desc_area;
337 dma_addr_t tx_desc_dma;
338 int tx_desc_area_size;
339 struct sk_buff **tx_skb;
340 };
341
342 struct mv643xx_eth_private {
343 struct mv643xx_eth_shared_private *shared;
344 int port_num;
345
346 struct net_device *dev;
347
348 struct mv643xx_eth_shared_private *shared_smi;
349 int phy_addr;
350
351 spinlock_t lock;
352
353 struct mib_counters mib_counters;
354 struct work_struct tx_timeout_task;
355 struct mii_if_info mii;
356
357 /*
358 * RX state.
359 */
360 int default_rx_ring_size;
361 unsigned long rx_desc_sram_addr;
362 int rx_desc_sram_size;
363 u8 rxq_mask;
364 int rxq_primary;
365 struct napi_struct napi;
366 struct timer_list rx_oom;
367 struct rx_queue rxq[8];
368
369 /*
370 * TX state.
371 */
372 int default_tx_ring_size;
373 unsigned long tx_desc_sram_addr;
374 int tx_desc_sram_size;
375 u8 txq_mask;
376 int txq_primary;
377 struct tx_queue txq[8];
378 #ifdef MV643XX_ETH_TX_FAST_REFILL
379 int tx_clean_threshold;
380 #endif
381 };
382
383
384 /* port register accessors **************************************************/
385 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
386 {
387 return readl(mp->shared->base + offset);
388 }
389
390 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
391 {
392 writel(data, mp->shared->base + offset);
393 }
394
395
396 /* rxq/txq helper functions *************************************************/
397 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
398 {
399 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
400 }
401
402 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
403 {
404 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
405 }
406
407 static void rxq_enable(struct rx_queue *rxq)
408 {
409 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
410 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
411 }
412
413 static void rxq_disable(struct rx_queue *rxq)
414 {
415 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
416 u8 mask = 1 << rxq->index;
417
418 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
419 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
420 udelay(10);
421 }
422
423 static void txq_reset_hw_ptr(struct tx_queue *txq)
424 {
425 struct mv643xx_eth_private *mp = txq_to_mp(txq);
426 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
427 u32 addr;
428
429 addr = (u32)txq->tx_desc_dma;
430 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
431 wrl(mp, off, addr);
432 }
433
434 static void txq_enable(struct tx_queue *txq)
435 {
436 struct mv643xx_eth_private *mp = txq_to_mp(txq);
437 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
438 }
439
440 static void txq_disable(struct tx_queue *txq)
441 {
442 struct mv643xx_eth_private *mp = txq_to_mp(txq);
443 u8 mask = 1 << txq->index;
444
445 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
446 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
447 udelay(10);
448 }
449
450 static void __txq_maybe_wake(struct tx_queue *txq)
451 {
452 struct mv643xx_eth_private *mp = txq_to_mp(txq);
453
454 /*
455 * netif_{stop,wake}_queue() flow control only applies to
456 * the primary queue.
457 */
458 BUG_ON(txq->index != mp->txq_primary);
459
460 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
461 netif_wake_queue(mp->dev);
462 }
463
464
465 /* rx ***********************************************************************/
466 static void txq_reclaim(struct tx_queue *txq, int force);
467
468 static int rxq_refill(struct rx_queue *rxq, int budget, int *oom)
469 {
470 int skb_size;
471 int refilled;
472
473 /*
474 * Reserve 2+14 bytes for an ethernet header (the hardware
475 * automatically prepends 2 bytes of dummy data to each
476 * received packet), 16 bytes for up to four VLAN tags, and
477 * 4 bytes for the trailing FCS -- 36 bytes total.
478 */
479 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
480
481 /*
482 * Make sure that the skb size is a multiple of 8 bytes, as
483 * the lower three bits of the receive descriptor's buffer
484 * size field are ignored by the hardware.
485 */
486 skb_size = (skb_size + 7) & ~7;
487
488 refilled = 0;
489 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
490 struct sk_buff *skb;
491 int unaligned;
492 int rx;
493
494 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
495 if (skb == NULL) {
496 *oom = 1;
497 break;
498 }
499
500 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
501 if (unaligned)
502 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
503
504 refilled++;
505 rxq->rx_desc_count++;
506
507 rx = rxq->rx_used_desc++;
508 if (rxq->rx_used_desc == rxq->rx_ring_size)
509 rxq->rx_used_desc = 0;
510
511 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
512 skb_size, DMA_FROM_DEVICE);
513 rxq->rx_desc_area[rx].buf_size = skb_size;
514 rxq->rx_skb[rx] = skb;
515 wmb();
516 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
517 RX_ENABLE_INTERRUPT;
518 wmb();
519
520 /*
521 * The hardware automatically prepends 2 bytes of
522 * dummy data to each received packet, so that the
523 * IP header ends up 16-byte aligned.
524 */
525 skb_reserve(skb, 2);
526 }
527
528 return refilled;
529 }
530
531 static int rxq_process(struct rx_queue *rxq, int budget)
532 {
533 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
534 struct net_device_stats *stats = &mp->dev->stats;
535 int rx;
536
537 rx = 0;
538 while (rx < budget && rxq->rx_desc_count) {
539 struct rx_desc *rx_desc;
540 unsigned int cmd_sts;
541 struct sk_buff *skb;
542
543 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
544
545 cmd_sts = rx_desc->cmd_sts;
546 if (cmd_sts & BUFFER_OWNED_BY_DMA)
547 break;
548 rmb();
549
550 skb = rxq->rx_skb[rxq->rx_curr_desc];
551 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
552
553 rxq->rx_curr_desc++;
554 if (rxq->rx_curr_desc == rxq->rx_ring_size)
555 rxq->rx_curr_desc = 0;
556
557 dma_unmap_single(NULL, rx_desc->buf_ptr,
558 rx_desc->buf_size, DMA_FROM_DEVICE);
559 rxq->rx_desc_count--;
560 rx++;
561
562 /*
563 * Update statistics.
564 *
565 * Note that the descriptor byte count includes 2 dummy
566 * bytes automatically inserted by the hardware at the
567 * start of the packet (which we don't count), and a 4
568 * byte CRC at the end of the packet (which we do count).
569 */
570 stats->rx_packets++;
571 stats->rx_bytes += rx_desc->byte_cnt - 2;
572
573 /*
574 * In case we received a packet without first / last bits
575 * on, or the error summary bit is set, the packet needs
576 * to be dropped.
577 */
578 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
579 (RX_FIRST_DESC | RX_LAST_DESC))
580 || (cmd_sts & ERROR_SUMMARY)) {
581 stats->rx_dropped++;
582
583 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
584 (RX_FIRST_DESC | RX_LAST_DESC)) {
585 if (net_ratelimit())
586 dev_printk(KERN_ERR, &mp->dev->dev,
587 "received packet spanning "
588 "multiple descriptors\n");
589 }
590
591 if (cmd_sts & ERROR_SUMMARY)
592 stats->rx_errors++;
593
594 dev_kfree_skb(skb);
595 } else {
596 /*
597 * The -4 is for the CRC in the trailer of the
598 * received packet
599 */
600 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
601
602 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
603 skb->ip_summed = CHECKSUM_UNNECESSARY;
604 skb->csum = htons(
605 (cmd_sts & 0x0007fff8) >> 3);
606 }
607 skb->protocol = eth_type_trans(skb, mp->dev);
608 netif_receive_skb(skb);
609 }
610
611 mp->dev->last_rx = jiffies;
612 }
613
614 return rx;
615 }
616
617 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
618 {
619 struct mv643xx_eth_private *mp;
620 int work_done;
621 int oom;
622 int i;
623
624 mp = container_of(napi, struct mv643xx_eth_private, napi);
625
626 #ifdef MV643XX_ETH_TX_FAST_REFILL
627 if (++mp->tx_clean_threshold > 5) {
628 mp->tx_clean_threshold = 0;
629 for (i = 0; i < 8; i++)
630 if (mp->txq_mask & (1 << i))
631 txq_reclaim(mp->txq + i, 0);
632
633 if (netif_carrier_ok(mp->dev)) {
634 spin_lock_irq(&mp->lock);
635 __txq_maybe_wake(mp->txq + mp->txq_primary);
636 spin_unlock_irq(&mp->lock);
637 }
638 }
639 #endif
640
641 work_done = 0;
642 oom = 0;
643 for (i = 7; work_done < budget && i >= 0; i--) {
644 if (mp->rxq_mask & (1 << i)) {
645 struct rx_queue *rxq = mp->rxq + i;
646
647 work_done += rxq_process(rxq, budget - work_done);
648 work_done += rxq_refill(rxq, budget - work_done, &oom);
649 }
650 }
651
652 if (work_done < budget) {
653 if (oom)
654 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
655 netif_rx_complete(mp->dev, napi);
656 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
657 }
658
659 return work_done;
660 }
661
662 static inline void oom_timer_wrapper(unsigned long data)
663 {
664 struct mv643xx_eth_private *mp = (void *)data;
665
666 napi_schedule(&mp->napi);
667 }
668
669
670 /* tx ***********************************************************************/
671 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
672 {
673 int frag;
674
675 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
676 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
677 if (fragp->size <= 8 && fragp->page_offset & 7)
678 return 1;
679 }
680
681 return 0;
682 }
683
684 static int txq_alloc_desc_index(struct tx_queue *txq)
685 {
686 int tx_desc_curr;
687
688 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
689
690 tx_desc_curr = txq->tx_curr_desc++;
691 if (txq->tx_curr_desc == txq->tx_ring_size)
692 txq->tx_curr_desc = 0;
693
694 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
695
696 return tx_desc_curr;
697 }
698
699 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
700 {
701 int nr_frags = skb_shinfo(skb)->nr_frags;
702 int frag;
703
704 for (frag = 0; frag < nr_frags; frag++) {
705 skb_frag_t *this_frag;
706 int tx_index;
707 struct tx_desc *desc;
708
709 this_frag = &skb_shinfo(skb)->frags[frag];
710 tx_index = txq_alloc_desc_index(txq);
711 desc = &txq->tx_desc_area[tx_index];
712
713 /*
714 * The last fragment will generate an interrupt
715 * which will free the skb on TX completion.
716 */
717 if (frag == nr_frags - 1) {
718 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
719 ZERO_PADDING | TX_LAST_DESC |
720 TX_ENABLE_INTERRUPT;
721 txq->tx_skb[tx_index] = skb;
722 } else {
723 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
724 txq->tx_skb[tx_index] = NULL;
725 }
726
727 desc->l4i_chk = 0;
728 desc->byte_cnt = this_frag->size;
729 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
730 this_frag->page_offset,
731 this_frag->size,
732 DMA_TO_DEVICE);
733 }
734 }
735
736 static inline __be16 sum16_as_be(__sum16 sum)
737 {
738 return (__force __be16)sum;
739 }
740
741 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
742 {
743 struct mv643xx_eth_private *mp = txq_to_mp(txq);
744 int nr_frags = skb_shinfo(skb)->nr_frags;
745 int tx_index;
746 struct tx_desc *desc;
747 u32 cmd_sts;
748 int length;
749
750 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
751
752 tx_index = txq_alloc_desc_index(txq);
753 desc = &txq->tx_desc_area[tx_index];
754
755 if (nr_frags) {
756 txq_submit_frag_skb(txq, skb);
757
758 length = skb_headlen(skb);
759 txq->tx_skb[tx_index] = NULL;
760 } else {
761 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
762 length = skb->len;
763 txq->tx_skb[tx_index] = skb;
764 }
765
766 desc->byte_cnt = length;
767 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
768
769 if (skb->ip_summed == CHECKSUM_PARTIAL) {
770 int mac_hdr_len;
771
772 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
773 skb->protocol != htons(ETH_P_8021Q));
774
775 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
776 GEN_IP_V4_CHECKSUM |
777 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
778
779 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
780 switch (mac_hdr_len - ETH_HLEN) {
781 case 0:
782 break;
783 case 4:
784 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
785 break;
786 case 8:
787 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
788 break;
789 case 12:
790 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
791 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
792 break;
793 default:
794 if (net_ratelimit())
795 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
796 "mac header length is %d?!\n", mac_hdr_len);
797 break;
798 }
799
800 switch (ip_hdr(skb)->protocol) {
801 case IPPROTO_UDP:
802 cmd_sts |= UDP_FRAME;
803 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
804 break;
805 case IPPROTO_TCP:
806 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
807 break;
808 default:
809 BUG();
810 }
811 } else {
812 /* Errata BTS #50, IHL must be 5 if no HW checksum */
813 cmd_sts |= 5 << TX_IHL_SHIFT;
814 desc->l4i_chk = 0;
815 }
816
817 /* ensure all other descriptors are written before first cmd_sts */
818 wmb();
819 desc->cmd_sts = cmd_sts;
820
821 /* clear TX_END interrupt status */
822 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
823 rdl(mp, INT_CAUSE(mp->port_num));
824
825 /* ensure all descriptors are written before poking hardware */
826 wmb();
827 txq_enable(txq);
828
829 txq->tx_desc_count += nr_frags + 1;
830 }
831
832 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
833 {
834 struct mv643xx_eth_private *mp = netdev_priv(dev);
835 struct net_device_stats *stats = &dev->stats;
836 struct tx_queue *txq;
837 unsigned long flags;
838
839 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
840 stats->tx_dropped++;
841 dev_printk(KERN_DEBUG, &dev->dev,
842 "failed to linearize skb with tiny "
843 "unaligned fragment\n");
844 return NETDEV_TX_BUSY;
845 }
846
847 spin_lock_irqsave(&mp->lock, flags);
848
849 txq = mp->txq + mp->txq_primary;
850
851 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
852 spin_unlock_irqrestore(&mp->lock, flags);
853 if (txq->index == mp->txq_primary && net_ratelimit())
854 dev_printk(KERN_ERR, &dev->dev,
855 "primary tx queue full?!\n");
856 kfree_skb(skb);
857 return NETDEV_TX_OK;
858 }
859
860 txq_submit_skb(txq, skb);
861 stats->tx_bytes += skb->len;
862 stats->tx_packets++;
863 dev->trans_start = jiffies;
864
865 if (txq->index == mp->txq_primary) {
866 int entries_left;
867
868 entries_left = txq->tx_ring_size - txq->tx_desc_count;
869 if (entries_left < MAX_SKB_FRAGS + 1)
870 netif_stop_queue(dev);
871 }
872
873 spin_unlock_irqrestore(&mp->lock, flags);
874
875 return NETDEV_TX_OK;
876 }
877
878
879 /* tx rate control **********************************************************/
880 /*
881 * Set total maximum TX rate (shared by all TX queues for this port)
882 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
883 */
884 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
885 {
886 int token_rate;
887 int mtu;
888 int bucket_size;
889
890 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
891 if (token_rate > 1023)
892 token_rate = 1023;
893
894 mtu = (mp->dev->mtu + 255) >> 8;
895 if (mtu > 63)
896 mtu = 63;
897
898 bucket_size = (burst + 255) >> 8;
899 if (bucket_size > 65535)
900 bucket_size = 65535;
901
902 if (mp->shared->tx_bw_control_moved) {
903 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
904 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
905 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
906 } else {
907 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
908 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
909 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
910 }
911 }
912
913 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
914 {
915 struct mv643xx_eth_private *mp = txq_to_mp(txq);
916 int token_rate;
917 int bucket_size;
918
919 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
920 if (token_rate > 1023)
921 token_rate = 1023;
922
923 bucket_size = (burst + 255) >> 8;
924 if (bucket_size > 65535)
925 bucket_size = 65535;
926
927 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
928 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
929 (bucket_size << 10) | token_rate);
930 }
931
932 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
933 {
934 struct mv643xx_eth_private *mp = txq_to_mp(txq);
935 int off;
936 u32 val;
937
938 /*
939 * Turn on fixed priority mode.
940 */
941 if (mp->shared->tx_bw_control_moved)
942 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
943 else
944 off = TXQ_FIX_PRIO_CONF(mp->port_num);
945
946 val = rdl(mp, off);
947 val |= 1 << txq->index;
948 wrl(mp, off, val);
949 }
950
951 static void txq_set_wrr(struct tx_queue *txq, int weight)
952 {
953 struct mv643xx_eth_private *mp = txq_to_mp(txq);
954 int off;
955 u32 val;
956
957 /*
958 * Turn off fixed priority mode.
959 */
960 if (mp->shared->tx_bw_control_moved)
961 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
962 else
963 off = TXQ_FIX_PRIO_CONF(mp->port_num);
964
965 val = rdl(mp, off);
966 val &= ~(1 << txq->index);
967 wrl(mp, off, val);
968
969 /*
970 * Configure WRR weight for this queue.
971 */
972 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
973
974 val = rdl(mp, off);
975 val = (val & ~0xff) | (weight & 0xff);
976 wrl(mp, off, val);
977 }
978
979
980 /* mii management interface *************************************************/
981 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
982 {
983 struct mv643xx_eth_shared_private *msp = dev_id;
984
985 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
986 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
987 wake_up(&msp->smi_busy_wait);
988 return IRQ_HANDLED;
989 }
990
991 return IRQ_NONE;
992 }
993
994 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
995 {
996 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
997 }
998
999 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1000 {
1001 if (msp->err_interrupt == NO_IRQ) {
1002 int i;
1003
1004 for (i = 0; !smi_is_done(msp); i++) {
1005 if (i == 10)
1006 return -ETIMEDOUT;
1007 msleep(10);
1008 }
1009
1010 return 0;
1011 }
1012
1013 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1014 msecs_to_jiffies(100)))
1015 return -ETIMEDOUT;
1016
1017 return 0;
1018 }
1019
1020 static int smi_reg_read(struct mv643xx_eth_private *mp,
1021 unsigned int addr, unsigned int reg)
1022 {
1023 struct mv643xx_eth_shared_private *msp = mp->shared_smi;
1024 void __iomem *smi_reg = msp->base + SMI_REG;
1025 int ret;
1026
1027 mutex_lock(&msp->phy_lock);
1028
1029 if (smi_wait_ready(msp)) {
1030 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1031 ret = -ETIMEDOUT;
1032 goto out;
1033 }
1034
1035 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1036
1037 if (smi_wait_ready(msp)) {
1038 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1039 ret = -ETIMEDOUT;
1040 goto out;
1041 }
1042
1043 ret = readl(smi_reg);
1044 if (!(ret & SMI_READ_VALID)) {
1045 printk("%s: SMI bus read not valid\n", mp->dev->name);
1046 ret = -ENODEV;
1047 goto out;
1048 }
1049
1050 ret &= 0xffff;
1051
1052 out:
1053 mutex_unlock(&msp->phy_lock);
1054
1055 return ret;
1056 }
1057
1058 static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1059 unsigned int reg, unsigned int value)
1060 {
1061 struct mv643xx_eth_shared_private *msp = mp->shared_smi;
1062 void __iomem *smi_reg = msp->base + SMI_REG;
1063
1064 mutex_lock(&msp->phy_lock);
1065
1066 if (smi_wait_ready(msp)) {
1067 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1068 mutex_unlock(&msp->phy_lock);
1069 return -ETIMEDOUT;
1070 }
1071
1072 writel(SMI_OPCODE_WRITE | (reg << 21) |
1073 (addr << 16) | (value & 0xffff), smi_reg);
1074
1075 mutex_unlock(&msp->phy_lock);
1076
1077 return 0;
1078 }
1079
1080
1081 /* mib counters *************************************************************/
1082 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1083 {
1084 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1085 }
1086
1087 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1088 {
1089 int i;
1090
1091 for (i = 0; i < 0x80; i += 4)
1092 mib_read(mp, i);
1093 }
1094
1095 static void mib_counters_update(struct mv643xx_eth_private *mp)
1096 {
1097 struct mib_counters *p = &mp->mib_counters;
1098
1099 p->good_octets_received += mib_read(mp, 0x00);
1100 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1101 p->bad_octets_received += mib_read(mp, 0x08);
1102 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1103 p->good_frames_received += mib_read(mp, 0x10);
1104 p->bad_frames_received += mib_read(mp, 0x14);
1105 p->broadcast_frames_received += mib_read(mp, 0x18);
1106 p->multicast_frames_received += mib_read(mp, 0x1c);
1107 p->frames_64_octets += mib_read(mp, 0x20);
1108 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1109 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1110 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1111 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1112 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1113 p->good_octets_sent += mib_read(mp, 0x38);
1114 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1115 p->good_frames_sent += mib_read(mp, 0x40);
1116 p->excessive_collision += mib_read(mp, 0x44);
1117 p->multicast_frames_sent += mib_read(mp, 0x48);
1118 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1119 p->unrec_mac_control_received += mib_read(mp, 0x50);
1120 p->fc_sent += mib_read(mp, 0x54);
1121 p->good_fc_received += mib_read(mp, 0x58);
1122 p->bad_fc_received += mib_read(mp, 0x5c);
1123 p->undersize_received += mib_read(mp, 0x60);
1124 p->fragments_received += mib_read(mp, 0x64);
1125 p->oversize_received += mib_read(mp, 0x68);
1126 p->jabber_received += mib_read(mp, 0x6c);
1127 p->mac_receive_error += mib_read(mp, 0x70);
1128 p->bad_crc_event += mib_read(mp, 0x74);
1129 p->collision += mib_read(mp, 0x78);
1130 p->late_collision += mib_read(mp, 0x7c);
1131 }
1132
1133
1134 /* ethtool ******************************************************************/
1135 struct mv643xx_eth_stats {
1136 char stat_string[ETH_GSTRING_LEN];
1137 int sizeof_stat;
1138 int netdev_off;
1139 int mp_off;
1140 };
1141
1142 #define SSTAT(m) \
1143 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1144 offsetof(struct net_device, stats.m), -1 }
1145
1146 #define MIBSTAT(m) \
1147 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1148 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1149
1150 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1151 SSTAT(rx_packets),
1152 SSTAT(tx_packets),
1153 SSTAT(rx_bytes),
1154 SSTAT(tx_bytes),
1155 SSTAT(rx_errors),
1156 SSTAT(tx_errors),
1157 SSTAT(rx_dropped),
1158 SSTAT(tx_dropped),
1159 MIBSTAT(good_octets_received),
1160 MIBSTAT(bad_octets_received),
1161 MIBSTAT(internal_mac_transmit_err),
1162 MIBSTAT(good_frames_received),
1163 MIBSTAT(bad_frames_received),
1164 MIBSTAT(broadcast_frames_received),
1165 MIBSTAT(multicast_frames_received),
1166 MIBSTAT(frames_64_octets),
1167 MIBSTAT(frames_65_to_127_octets),
1168 MIBSTAT(frames_128_to_255_octets),
1169 MIBSTAT(frames_256_to_511_octets),
1170 MIBSTAT(frames_512_to_1023_octets),
1171 MIBSTAT(frames_1024_to_max_octets),
1172 MIBSTAT(good_octets_sent),
1173 MIBSTAT(good_frames_sent),
1174 MIBSTAT(excessive_collision),
1175 MIBSTAT(multicast_frames_sent),
1176 MIBSTAT(broadcast_frames_sent),
1177 MIBSTAT(unrec_mac_control_received),
1178 MIBSTAT(fc_sent),
1179 MIBSTAT(good_fc_received),
1180 MIBSTAT(bad_fc_received),
1181 MIBSTAT(undersize_received),
1182 MIBSTAT(fragments_received),
1183 MIBSTAT(oversize_received),
1184 MIBSTAT(jabber_received),
1185 MIBSTAT(mac_receive_error),
1186 MIBSTAT(bad_crc_event),
1187 MIBSTAT(collision),
1188 MIBSTAT(late_collision),
1189 };
1190
1191 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1192 {
1193 struct mv643xx_eth_private *mp = netdev_priv(dev);
1194 int err;
1195
1196 err = mii_ethtool_gset(&mp->mii, cmd);
1197
1198 /*
1199 * The MAC does not support 1000baseT_Half.
1200 */
1201 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1202 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1203
1204 return err;
1205 }
1206
1207 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1208 {
1209 struct mv643xx_eth_private *mp = netdev_priv(dev);
1210 u32 port_status;
1211
1212 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1213
1214 cmd->supported = SUPPORTED_MII;
1215 cmd->advertising = ADVERTISED_MII;
1216 switch (port_status & PORT_SPEED_MASK) {
1217 case PORT_SPEED_10:
1218 cmd->speed = SPEED_10;
1219 break;
1220 case PORT_SPEED_100:
1221 cmd->speed = SPEED_100;
1222 break;
1223 case PORT_SPEED_1000:
1224 cmd->speed = SPEED_1000;
1225 break;
1226 default:
1227 cmd->speed = -1;
1228 break;
1229 }
1230 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1231 cmd->port = PORT_MII;
1232 cmd->phy_address = 0;
1233 cmd->transceiver = XCVR_INTERNAL;
1234 cmd->autoneg = AUTONEG_DISABLE;
1235 cmd->maxtxpkt = 1;
1236 cmd->maxrxpkt = 1;
1237
1238 return 0;
1239 }
1240
1241 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1242 {
1243 struct mv643xx_eth_private *mp = netdev_priv(dev);
1244
1245 /*
1246 * The MAC does not support 1000baseT_Half.
1247 */
1248 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1249
1250 return mii_ethtool_sset(&mp->mii, cmd);
1251 }
1252
1253 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1254 {
1255 return -EINVAL;
1256 }
1257
1258 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1259 struct ethtool_drvinfo *drvinfo)
1260 {
1261 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1262 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1263 strncpy(drvinfo->fw_version, "N/A", 32);
1264 strncpy(drvinfo->bus_info, "platform", 32);
1265 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1266 }
1267
1268 static int mv643xx_eth_nway_reset(struct net_device *dev)
1269 {
1270 struct mv643xx_eth_private *mp = netdev_priv(dev);
1271
1272 return mii_nway_restart(&mp->mii);
1273 }
1274
1275 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1276 {
1277 return -EINVAL;
1278 }
1279
1280 static u32 mv643xx_eth_get_link(struct net_device *dev)
1281 {
1282 struct mv643xx_eth_private *mp = netdev_priv(dev);
1283
1284 return mii_link_ok(&mp->mii);
1285 }
1286
1287 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1288 {
1289 return 1;
1290 }
1291
1292 static void mv643xx_eth_get_strings(struct net_device *dev,
1293 uint32_t stringset, uint8_t *data)
1294 {
1295 int i;
1296
1297 if (stringset == ETH_SS_STATS) {
1298 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1299 memcpy(data + i * ETH_GSTRING_LEN,
1300 mv643xx_eth_stats[i].stat_string,
1301 ETH_GSTRING_LEN);
1302 }
1303 }
1304 }
1305
1306 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1307 struct ethtool_stats *stats,
1308 uint64_t *data)
1309 {
1310 struct mv643xx_eth_private *mp = netdev_priv(dev);
1311 int i;
1312
1313 mib_counters_update(mp);
1314
1315 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1316 const struct mv643xx_eth_stats *stat;
1317 void *p;
1318
1319 stat = mv643xx_eth_stats + i;
1320
1321 if (stat->netdev_off >= 0)
1322 p = ((void *)mp->dev) + stat->netdev_off;
1323 else
1324 p = ((void *)mp) + stat->mp_off;
1325
1326 data[i] = (stat->sizeof_stat == 8) ?
1327 *(uint64_t *)p : *(uint32_t *)p;
1328 }
1329 }
1330
1331 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1332 {
1333 if (sset == ETH_SS_STATS)
1334 return ARRAY_SIZE(mv643xx_eth_stats);
1335
1336 return -EOPNOTSUPP;
1337 }
1338
1339 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1340 .get_settings = mv643xx_eth_get_settings,
1341 .set_settings = mv643xx_eth_set_settings,
1342 .get_drvinfo = mv643xx_eth_get_drvinfo,
1343 .nway_reset = mv643xx_eth_nway_reset,
1344 .get_link = mv643xx_eth_get_link,
1345 .set_sg = ethtool_op_set_sg,
1346 .get_strings = mv643xx_eth_get_strings,
1347 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1348 .get_sset_count = mv643xx_eth_get_sset_count,
1349 };
1350
1351 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1352 .get_settings = mv643xx_eth_get_settings_phyless,
1353 .set_settings = mv643xx_eth_set_settings_phyless,
1354 .get_drvinfo = mv643xx_eth_get_drvinfo,
1355 .nway_reset = mv643xx_eth_nway_reset_phyless,
1356 .get_link = mv643xx_eth_get_link_phyless,
1357 .set_sg = ethtool_op_set_sg,
1358 .get_strings = mv643xx_eth_get_strings,
1359 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1360 .get_sset_count = mv643xx_eth_get_sset_count,
1361 };
1362
1363
1364 /* address handling *********************************************************/
1365 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1366 {
1367 unsigned int mac_h;
1368 unsigned int mac_l;
1369
1370 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1371 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1372
1373 addr[0] = (mac_h >> 24) & 0xff;
1374 addr[1] = (mac_h >> 16) & 0xff;
1375 addr[2] = (mac_h >> 8) & 0xff;
1376 addr[3] = mac_h & 0xff;
1377 addr[4] = (mac_l >> 8) & 0xff;
1378 addr[5] = mac_l & 0xff;
1379 }
1380
1381 static void init_mac_tables(struct mv643xx_eth_private *mp)
1382 {
1383 int i;
1384
1385 for (i = 0; i < 0x100; i += 4) {
1386 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1387 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1388 }
1389
1390 for (i = 0; i < 0x10; i += 4)
1391 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1392 }
1393
1394 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1395 int table, unsigned char entry)
1396 {
1397 unsigned int table_reg;
1398
1399 /* Set "accepts frame bit" at specified table entry */
1400 table_reg = rdl(mp, table + (entry & 0xfc));
1401 table_reg |= 0x01 << (8 * (entry & 3));
1402 wrl(mp, table + (entry & 0xfc), table_reg);
1403 }
1404
1405 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1406 {
1407 unsigned int mac_h;
1408 unsigned int mac_l;
1409 int table;
1410
1411 mac_l = (addr[4] << 8) | addr[5];
1412 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1413
1414 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1415 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1416
1417 table = UNICAST_TABLE(mp->port_num);
1418 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1419 }
1420
1421 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1422 {
1423 struct mv643xx_eth_private *mp = netdev_priv(dev);
1424
1425 /* +2 is for the offset of the HW addr type */
1426 memcpy(dev->dev_addr, addr + 2, 6);
1427
1428 init_mac_tables(mp);
1429 uc_addr_set(mp, dev->dev_addr);
1430
1431 return 0;
1432 }
1433
1434 static int addr_crc(unsigned char *addr)
1435 {
1436 int crc = 0;
1437 int i;
1438
1439 for (i = 0; i < 6; i++) {
1440 int j;
1441
1442 crc = (crc ^ addr[i]) << 8;
1443 for (j = 7; j >= 0; j--) {
1444 if (crc & (0x100 << j))
1445 crc ^= 0x107 << j;
1446 }
1447 }
1448
1449 return crc;
1450 }
1451
1452 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1453 {
1454 struct mv643xx_eth_private *mp = netdev_priv(dev);
1455 u32 port_config;
1456 struct dev_addr_list *addr;
1457 int i;
1458
1459 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1460 if (dev->flags & IFF_PROMISC)
1461 port_config |= UNICAST_PROMISCUOUS_MODE;
1462 else
1463 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1464 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1465
1466 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1467 int port_num = mp->port_num;
1468 u32 accept = 0x01010101;
1469
1470 for (i = 0; i < 0x100; i += 4) {
1471 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1472 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1473 }
1474 return;
1475 }
1476
1477 for (i = 0; i < 0x100; i += 4) {
1478 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1479 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1480 }
1481
1482 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1483 u8 *a = addr->da_addr;
1484 int table;
1485
1486 if (addr->da_addrlen != 6)
1487 continue;
1488
1489 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1490 table = SPECIAL_MCAST_TABLE(mp->port_num);
1491 set_filter_table_entry(mp, table, a[5]);
1492 } else {
1493 int crc = addr_crc(a);
1494
1495 table = OTHER_MCAST_TABLE(mp->port_num);
1496 set_filter_table_entry(mp, table, crc);
1497 }
1498 }
1499 }
1500
1501
1502 /* rx/tx queue initialisation ***********************************************/
1503 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1504 {
1505 struct rx_queue *rxq = mp->rxq + index;
1506 struct rx_desc *rx_desc;
1507 int size;
1508 int i;
1509
1510 rxq->index = index;
1511
1512 rxq->rx_ring_size = mp->default_rx_ring_size;
1513
1514 rxq->rx_desc_count = 0;
1515 rxq->rx_curr_desc = 0;
1516 rxq->rx_used_desc = 0;
1517
1518 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1519
1520 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1521 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1522 mp->rx_desc_sram_size);
1523 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1524 } else {
1525 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1526 &rxq->rx_desc_dma,
1527 GFP_KERNEL);
1528 }
1529
1530 if (rxq->rx_desc_area == NULL) {
1531 dev_printk(KERN_ERR, &mp->dev->dev,
1532 "can't allocate rx ring (%d bytes)\n", size);
1533 goto out;
1534 }
1535 memset(rxq->rx_desc_area, 0, size);
1536
1537 rxq->rx_desc_area_size = size;
1538 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1539 GFP_KERNEL);
1540 if (rxq->rx_skb == NULL) {
1541 dev_printk(KERN_ERR, &mp->dev->dev,
1542 "can't allocate rx skb ring\n");
1543 goto out_free;
1544 }
1545
1546 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1547 for (i = 0; i < rxq->rx_ring_size; i++) {
1548 int nexti;
1549
1550 nexti = i + 1;
1551 if (nexti == rxq->rx_ring_size)
1552 nexti = 0;
1553
1554 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1555 nexti * sizeof(struct rx_desc);
1556 }
1557
1558 return 0;
1559
1560
1561 out_free:
1562 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1563 iounmap(rxq->rx_desc_area);
1564 else
1565 dma_free_coherent(NULL, size,
1566 rxq->rx_desc_area,
1567 rxq->rx_desc_dma);
1568
1569 out:
1570 return -ENOMEM;
1571 }
1572
1573 static void rxq_deinit(struct rx_queue *rxq)
1574 {
1575 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1576 int i;
1577
1578 rxq_disable(rxq);
1579
1580 for (i = 0; i < rxq->rx_ring_size; i++) {
1581 if (rxq->rx_skb[i]) {
1582 dev_kfree_skb(rxq->rx_skb[i]);
1583 rxq->rx_desc_count--;
1584 }
1585 }
1586
1587 if (rxq->rx_desc_count) {
1588 dev_printk(KERN_ERR, &mp->dev->dev,
1589 "error freeing rx ring -- %d skbs stuck\n",
1590 rxq->rx_desc_count);
1591 }
1592
1593 if (rxq->index == mp->rxq_primary &&
1594 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1595 iounmap(rxq->rx_desc_area);
1596 else
1597 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1598 rxq->rx_desc_area, rxq->rx_desc_dma);
1599
1600 kfree(rxq->rx_skb);
1601 }
1602
1603 static int txq_init(struct mv643xx_eth_private *mp, int index)
1604 {
1605 struct tx_queue *txq = mp->txq + index;
1606 struct tx_desc *tx_desc;
1607 int size;
1608 int i;
1609
1610 txq->index = index;
1611
1612 txq->tx_ring_size = mp->default_tx_ring_size;
1613
1614 txq->tx_desc_count = 0;
1615 txq->tx_curr_desc = 0;
1616 txq->tx_used_desc = 0;
1617
1618 size = txq->tx_ring_size * sizeof(struct tx_desc);
1619
1620 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1621 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1622 mp->tx_desc_sram_size);
1623 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1624 } else {
1625 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1626 &txq->tx_desc_dma,
1627 GFP_KERNEL);
1628 }
1629
1630 if (txq->tx_desc_area == NULL) {
1631 dev_printk(KERN_ERR, &mp->dev->dev,
1632 "can't allocate tx ring (%d bytes)\n", size);
1633 goto out;
1634 }
1635 memset(txq->tx_desc_area, 0, size);
1636
1637 txq->tx_desc_area_size = size;
1638 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1639 GFP_KERNEL);
1640 if (txq->tx_skb == NULL) {
1641 dev_printk(KERN_ERR, &mp->dev->dev,
1642 "can't allocate tx skb ring\n");
1643 goto out_free;
1644 }
1645
1646 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1647 for (i = 0; i < txq->tx_ring_size; i++) {
1648 struct tx_desc *txd = tx_desc + i;
1649 int nexti;
1650
1651 nexti = i + 1;
1652 if (nexti == txq->tx_ring_size)
1653 nexti = 0;
1654
1655 txd->cmd_sts = 0;
1656 txd->next_desc_ptr = txq->tx_desc_dma +
1657 nexti * sizeof(struct tx_desc);
1658 }
1659
1660 return 0;
1661
1662
1663 out_free:
1664 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1665 iounmap(txq->tx_desc_area);
1666 else
1667 dma_free_coherent(NULL, size,
1668 txq->tx_desc_area,
1669 txq->tx_desc_dma);
1670
1671 out:
1672 return -ENOMEM;
1673 }
1674
1675 static void txq_reclaim(struct tx_queue *txq, int force)
1676 {
1677 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1678 unsigned long flags;
1679
1680 spin_lock_irqsave(&mp->lock, flags);
1681 while (txq->tx_desc_count > 0) {
1682 int tx_index;
1683 struct tx_desc *desc;
1684 u32 cmd_sts;
1685 struct sk_buff *skb;
1686 dma_addr_t addr;
1687 int count;
1688
1689 tx_index = txq->tx_used_desc;
1690 desc = &txq->tx_desc_area[tx_index];
1691 cmd_sts = desc->cmd_sts;
1692
1693 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1694 if (!force)
1695 break;
1696 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1697 }
1698
1699 txq->tx_used_desc = tx_index + 1;
1700 if (txq->tx_used_desc == txq->tx_ring_size)
1701 txq->tx_used_desc = 0;
1702 txq->tx_desc_count--;
1703
1704 addr = desc->buf_ptr;
1705 count = desc->byte_cnt;
1706 skb = txq->tx_skb[tx_index];
1707 txq->tx_skb[tx_index] = NULL;
1708
1709 if (cmd_sts & ERROR_SUMMARY) {
1710 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1711 mp->dev->stats.tx_errors++;
1712 }
1713
1714 /*
1715 * Drop mp->lock while we free the skb.
1716 */
1717 spin_unlock_irqrestore(&mp->lock, flags);
1718
1719 if (cmd_sts & TX_FIRST_DESC)
1720 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1721 else
1722 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1723
1724 if (skb)
1725 dev_kfree_skb_irq(skb);
1726
1727 spin_lock_irqsave(&mp->lock, flags);
1728 }
1729 spin_unlock_irqrestore(&mp->lock, flags);
1730 }
1731
1732 static void txq_deinit(struct tx_queue *txq)
1733 {
1734 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1735
1736 txq_disable(txq);
1737 txq_reclaim(txq, 1);
1738
1739 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1740
1741 if (txq->index == mp->txq_primary &&
1742 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1743 iounmap(txq->tx_desc_area);
1744 else
1745 dma_free_coherent(NULL, txq->tx_desc_area_size,
1746 txq->tx_desc_area, txq->tx_desc_dma);
1747
1748 kfree(txq->tx_skb);
1749 }
1750
1751
1752 /* netdev ops and related ***************************************************/
1753 static void handle_link_event(struct mv643xx_eth_private *mp)
1754 {
1755 struct net_device *dev = mp->dev;
1756 u32 port_status;
1757 int speed;
1758 int duplex;
1759 int fc;
1760
1761 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1762 if (!(port_status & LINK_UP)) {
1763 if (netif_carrier_ok(dev)) {
1764 int i;
1765
1766 printk(KERN_INFO "%s: link down\n", dev->name);
1767
1768 netif_carrier_off(dev);
1769 netif_stop_queue(dev);
1770
1771 for (i = 0; i < 8; i++) {
1772 struct tx_queue *txq = mp->txq + i;
1773
1774 if (mp->txq_mask & (1 << i)) {
1775 txq_reclaim(txq, 1);
1776 txq_reset_hw_ptr(txq);
1777 }
1778 }
1779 }
1780 return;
1781 }
1782
1783 switch (port_status & PORT_SPEED_MASK) {
1784 case PORT_SPEED_10:
1785 speed = 10;
1786 break;
1787 case PORT_SPEED_100:
1788 speed = 100;
1789 break;
1790 case PORT_SPEED_1000:
1791 speed = 1000;
1792 break;
1793 default:
1794 speed = -1;
1795 break;
1796 }
1797 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1798 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1799
1800 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1801 "flow control %sabled\n", dev->name,
1802 speed, duplex ? "full" : "half",
1803 fc ? "en" : "dis");
1804
1805 if (!netif_carrier_ok(dev)) {
1806 netif_carrier_on(dev);
1807 netif_wake_queue(dev);
1808 }
1809 }
1810
1811 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1812 {
1813 struct net_device *dev = (struct net_device *)dev_id;
1814 struct mv643xx_eth_private *mp = netdev_priv(dev);
1815 u32 int_cause;
1816 u32 int_cause_ext;
1817
1818 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1819 (INT_TX_END | INT_RX | INT_EXT);
1820 if (int_cause == 0)
1821 return IRQ_NONE;
1822
1823 int_cause_ext = 0;
1824 if (int_cause & INT_EXT) {
1825 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1826 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1827 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1828 }
1829
1830 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK))
1831 handle_link_event(mp);
1832
1833 /*
1834 * RxBuffer or RxError set for any of the 8 queues?
1835 */
1836 if (int_cause & INT_RX) {
1837 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_RX));
1838 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1839 rdl(mp, INT_MASK(mp->port_num));
1840
1841 napi_schedule(&mp->napi);
1842 }
1843
1844 /*
1845 * TxBuffer or TxError set for any of the 8 queues?
1846 */
1847 if (int_cause_ext & INT_EXT_TX) {
1848 int i;
1849
1850 for (i = 0; i < 8; i++)
1851 if (mp->txq_mask & (1 << i))
1852 txq_reclaim(mp->txq + i, 0);
1853
1854 /*
1855 * Enough space again in the primary TX queue for a
1856 * full packet?
1857 */
1858 if (netif_carrier_ok(dev)) {
1859 spin_lock(&mp->lock);
1860 __txq_maybe_wake(mp->txq + mp->txq_primary);
1861 spin_unlock(&mp->lock);
1862 }
1863 }
1864
1865 /*
1866 * Any TxEnd interrupts?
1867 */
1868 if (int_cause & INT_TX_END) {
1869 int i;
1870
1871 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1872
1873 spin_lock(&mp->lock);
1874 for (i = 0; i < 8; i++) {
1875 struct tx_queue *txq = mp->txq + i;
1876 u32 hw_desc_ptr;
1877 u32 expected_ptr;
1878
1879 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1880 continue;
1881
1882 hw_desc_ptr =
1883 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1884 expected_ptr = (u32)txq->tx_desc_dma +
1885 txq->tx_curr_desc * sizeof(struct tx_desc);
1886
1887 if (hw_desc_ptr != expected_ptr)
1888 txq_enable(txq);
1889 }
1890 spin_unlock(&mp->lock);
1891 }
1892
1893 return IRQ_HANDLED;
1894 }
1895
1896 static void phy_reset(struct mv643xx_eth_private *mp)
1897 {
1898 int data;
1899
1900 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1901 if (data < 0)
1902 return;
1903
1904 data |= BMCR_RESET;
1905 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1906 return;
1907
1908 do {
1909 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1910 } while (data >= 0 && data & BMCR_RESET);
1911 }
1912
1913 static void port_start(struct mv643xx_eth_private *mp)
1914 {
1915 u32 pscr;
1916 int i;
1917
1918 /*
1919 * Perform PHY reset, if there is a PHY.
1920 */
1921 if (mp->phy_addr != -1) {
1922 struct ethtool_cmd cmd;
1923
1924 mv643xx_eth_get_settings(mp->dev, &cmd);
1925 phy_reset(mp);
1926 mv643xx_eth_set_settings(mp->dev, &cmd);
1927 }
1928
1929 /*
1930 * Configure basic link parameters.
1931 */
1932 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1933
1934 pscr |= SERIAL_PORT_ENABLE;
1935 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1936
1937 pscr |= DO_NOT_FORCE_LINK_FAIL;
1938 if (mp->phy_addr == -1)
1939 pscr |= FORCE_LINK_PASS;
1940 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1941
1942 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1943
1944 /*
1945 * Configure TX path and queues.
1946 */
1947 tx_set_rate(mp, 1000000000, 16777216);
1948 for (i = 0; i < 8; i++) {
1949 struct tx_queue *txq = mp->txq + i;
1950
1951 if ((mp->txq_mask & (1 << i)) == 0)
1952 continue;
1953
1954 txq_reset_hw_ptr(txq);
1955 txq_set_rate(txq, 1000000000, 16777216);
1956 txq_set_fixed_prio_mode(txq);
1957 }
1958
1959 /*
1960 * Add configured unicast address to address filter table.
1961 */
1962 uc_addr_set(mp, mp->dev->dev_addr);
1963
1964 /*
1965 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1966 * frames to RX queue #0.
1967 */
1968 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1969
1970 /*
1971 * Treat BPDUs as normal multicasts, and disable partition mode.
1972 */
1973 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1974
1975 /*
1976 * Enable the receive queues.
1977 */
1978 for (i = 0; i < 8; i++) {
1979 struct rx_queue *rxq = mp->rxq + i;
1980 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1981 u32 addr;
1982
1983 if ((mp->rxq_mask & (1 << i)) == 0)
1984 continue;
1985
1986 addr = (u32)rxq->rx_desc_dma;
1987 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1988 wrl(mp, off, addr);
1989
1990 rxq_enable(rxq);
1991 }
1992 }
1993
1994 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1995 {
1996 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1997 u32 val;
1998
1999 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2000 if (mp->shared->extended_rx_coal_limit) {
2001 if (coal > 0xffff)
2002 coal = 0xffff;
2003 val &= ~0x023fff80;
2004 val |= (coal & 0x8000) << 10;
2005 val |= (coal & 0x7fff) << 7;
2006 } else {
2007 if (coal > 0x3fff)
2008 coal = 0x3fff;
2009 val &= ~0x003fff00;
2010 val |= (coal & 0x3fff) << 8;
2011 }
2012 wrl(mp, SDMA_CONFIG(mp->port_num), val);
2013 }
2014
2015 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2016 {
2017 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2018
2019 if (coal > 0x3fff)
2020 coal = 0x3fff;
2021 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2022 }
2023
2024 static int mv643xx_eth_open(struct net_device *dev)
2025 {
2026 struct mv643xx_eth_private *mp = netdev_priv(dev);
2027 int err;
2028 int oom;
2029 int i;
2030
2031 wrl(mp, INT_CAUSE(mp->port_num), 0);
2032 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2033 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2034
2035 err = request_irq(dev->irq, mv643xx_eth_irq,
2036 IRQF_SHARED, dev->name, dev);
2037 if (err) {
2038 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2039 return -EAGAIN;
2040 }
2041
2042 init_mac_tables(mp);
2043
2044 napi_enable(&mp->napi);
2045
2046 oom = 0;
2047 for (i = 0; i < 8; i++) {
2048 if ((mp->rxq_mask & (1 << i)) == 0)
2049 continue;
2050
2051 err = rxq_init(mp, i);
2052 if (err) {
2053 while (--i >= 0)
2054 if (mp->rxq_mask & (1 << i))
2055 rxq_deinit(mp->rxq + i);
2056 goto out;
2057 }
2058
2059 rxq_refill(mp->rxq + i, INT_MAX, &oom);
2060 }
2061
2062 if (oom) {
2063 mp->rx_oom.expires = jiffies + (HZ / 10);
2064 add_timer(&mp->rx_oom);
2065 }
2066
2067 for (i = 0; i < 8; i++) {
2068 if ((mp->txq_mask & (1 << i)) == 0)
2069 continue;
2070
2071 err = txq_init(mp, i);
2072 if (err) {
2073 while (--i >= 0)
2074 if (mp->txq_mask & (1 << i))
2075 txq_deinit(mp->txq + i);
2076 goto out_free;
2077 }
2078 }
2079
2080 netif_carrier_off(dev);
2081 netif_stop_queue(dev);
2082
2083 port_start(mp);
2084
2085 set_rx_coal(mp, 0);
2086 set_tx_coal(mp, 0);
2087
2088 wrl(mp, INT_MASK_EXT(mp->port_num),
2089 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2090
2091 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2092
2093 return 0;
2094
2095
2096 out_free:
2097 for (i = 0; i < 8; i++)
2098 if (mp->rxq_mask & (1 << i))
2099 rxq_deinit(mp->rxq + i);
2100 out:
2101 free_irq(dev->irq, dev);
2102
2103 return err;
2104 }
2105
2106 static void port_reset(struct mv643xx_eth_private *mp)
2107 {
2108 unsigned int data;
2109 int i;
2110
2111 for (i = 0; i < 8; i++) {
2112 if (mp->rxq_mask & (1 << i))
2113 rxq_disable(mp->rxq + i);
2114 if (mp->txq_mask & (1 << i))
2115 txq_disable(mp->txq + i);
2116 }
2117
2118 while (1) {
2119 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2120
2121 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2122 break;
2123 udelay(10);
2124 }
2125
2126 /* Reset the Enable bit in the Configuration Register */
2127 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2128 data &= ~(SERIAL_PORT_ENABLE |
2129 DO_NOT_FORCE_LINK_FAIL |
2130 FORCE_LINK_PASS);
2131 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2132 }
2133
2134 static int mv643xx_eth_stop(struct net_device *dev)
2135 {
2136 struct mv643xx_eth_private *mp = netdev_priv(dev);
2137 int i;
2138
2139 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2140 rdl(mp, INT_MASK(mp->port_num));
2141
2142 napi_disable(&mp->napi);
2143
2144 del_timer_sync(&mp->rx_oom);
2145
2146 netif_carrier_off(dev);
2147 netif_stop_queue(dev);
2148
2149 free_irq(dev->irq, dev);
2150
2151 port_reset(mp);
2152 mib_counters_update(mp);
2153
2154 for (i = 0; i < 8; i++) {
2155 if (mp->rxq_mask & (1 << i))
2156 rxq_deinit(mp->rxq + i);
2157 if (mp->txq_mask & (1 << i))
2158 txq_deinit(mp->txq + i);
2159 }
2160
2161 return 0;
2162 }
2163
2164 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2165 {
2166 struct mv643xx_eth_private *mp = netdev_priv(dev);
2167
2168 if (mp->phy_addr != -1)
2169 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2170
2171 return -EOPNOTSUPP;
2172 }
2173
2174 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2175 {
2176 struct mv643xx_eth_private *mp = netdev_priv(dev);
2177
2178 if (new_mtu < 64 || new_mtu > 9500)
2179 return -EINVAL;
2180
2181 dev->mtu = new_mtu;
2182 tx_set_rate(mp, 1000000000, 16777216);
2183
2184 if (!netif_running(dev))
2185 return 0;
2186
2187 /*
2188 * Stop and then re-open the interface. This will allocate RX
2189 * skbs of the new MTU.
2190 * There is a possible danger that the open will not succeed,
2191 * due to memory being full.
2192 */
2193 mv643xx_eth_stop(dev);
2194 if (mv643xx_eth_open(dev)) {
2195 dev_printk(KERN_ERR, &dev->dev,
2196 "fatal error on re-opening device after "
2197 "MTU change\n");
2198 }
2199
2200 return 0;
2201 }
2202
2203 static void tx_timeout_task(struct work_struct *ugly)
2204 {
2205 struct mv643xx_eth_private *mp;
2206
2207 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2208 if (netif_running(mp->dev)) {
2209 netif_stop_queue(mp->dev);
2210
2211 port_reset(mp);
2212 port_start(mp);
2213
2214 __txq_maybe_wake(mp->txq + mp->txq_primary);
2215 }
2216 }
2217
2218 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2219 {
2220 struct mv643xx_eth_private *mp = netdev_priv(dev);
2221
2222 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2223
2224 schedule_work(&mp->tx_timeout_task);
2225 }
2226
2227 #ifdef CONFIG_NET_POLL_CONTROLLER
2228 static void mv643xx_eth_netpoll(struct net_device *dev)
2229 {
2230 struct mv643xx_eth_private *mp = netdev_priv(dev);
2231
2232 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2233 rdl(mp, INT_MASK(mp->port_num));
2234
2235 mv643xx_eth_irq(dev->irq, dev);
2236
2237 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2238 }
2239 #endif
2240
2241 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2242 {
2243 struct mv643xx_eth_private *mp = netdev_priv(dev);
2244 return smi_reg_read(mp, addr, reg);
2245 }
2246
2247 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2248 {
2249 struct mv643xx_eth_private *mp = netdev_priv(dev);
2250 smi_reg_write(mp, addr, reg, val);
2251 }
2252
2253
2254 /* platform glue ************************************************************/
2255 static void
2256 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2257 struct mbus_dram_target_info *dram)
2258 {
2259 void __iomem *base = msp->base;
2260 u32 win_enable;
2261 u32 win_protect;
2262 int i;
2263
2264 for (i = 0; i < 6; i++) {
2265 writel(0, base + WINDOW_BASE(i));
2266 writel(0, base + WINDOW_SIZE(i));
2267 if (i < 4)
2268 writel(0, base + WINDOW_REMAP_HIGH(i));
2269 }
2270
2271 win_enable = 0x3f;
2272 win_protect = 0;
2273
2274 for (i = 0; i < dram->num_cs; i++) {
2275 struct mbus_dram_window *cs = dram->cs + i;
2276
2277 writel((cs->base & 0xffff0000) |
2278 (cs->mbus_attr << 8) |
2279 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2280 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2281
2282 win_enable &= ~(1 << i);
2283 win_protect |= 3 << (2 * i);
2284 }
2285
2286 writel(win_enable, base + WINDOW_BAR_ENABLE);
2287 msp->win_protect = win_protect;
2288 }
2289
2290 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2291 {
2292 /*
2293 * Check whether we have a 14-bit coal limit field in bits
2294 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2295 * SDMA config register.
2296 */
2297 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2298 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2299 msp->extended_rx_coal_limit = 1;
2300 else
2301 msp->extended_rx_coal_limit = 0;
2302
2303 /*
2304 * Check whether the TX rate control registers are in the
2305 * old or the new place.
2306 */
2307 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2308 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2309 msp->tx_bw_control_moved = 1;
2310 else
2311 msp->tx_bw_control_moved = 0;
2312 }
2313
2314 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2315 {
2316 static int mv643xx_eth_version_printed = 0;
2317 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2318 struct mv643xx_eth_shared_private *msp;
2319 struct resource *res;
2320 int ret;
2321
2322 if (!mv643xx_eth_version_printed++)
2323 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2324 "driver version %s\n", mv643xx_eth_driver_version);
2325
2326 ret = -EINVAL;
2327 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2328 if (res == NULL)
2329 goto out;
2330
2331 ret = -ENOMEM;
2332 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2333 if (msp == NULL)
2334 goto out;
2335 memset(msp, 0, sizeof(*msp));
2336
2337 msp->base = ioremap(res->start, res->end - res->start + 1);
2338 if (msp->base == NULL)
2339 goto out_free;
2340
2341 mutex_init(&msp->phy_lock);
2342
2343 msp->err_interrupt = NO_IRQ;
2344 init_waitqueue_head(&msp->smi_busy_wait);
2345
2346 /*
2347 * Check whether the error interrupt is hooked up.
2348 */
2349 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2350 if (res != NULL) {
2351 int err;
2352
2353 err = request_irq(res->start, mv643xx_eth_err_irq,
2354 IRQF_SHARED, "mv643xx_eth", msp);
2355 if (!err) {
2356 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2357 msp->err_interrupt = res->start;
2358 }
2359 }
2360
2361 /*
2362 * (Re-)program MBUS remapping windows if we are asked to.
2363 */
2364 if (pd != NULL && pd->dram != NULL)
2365 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2366
2367 /*
2368 * Detect hardware parameters.
2369 */
2370 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2371 infer_hw_params(msp);
2372
2373 platform_set_drvdata(pdev, msp);
2374
2375 return 0;
2376
2377 out_free:
2378 kfree(msp);
2379 out:
2380 return ret;
2381 }
2382
2383 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2384 {
2385 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2386
2387 if (msp->err_interrupt != NO_IRQ)
2388 free_irq(msp->err_interrupt, msp);
2389 iounmap(msp->base);
2390 kfree(msp);
2391
2392 return 0;
2393 }
2394
2395 static struct platform_driver mv643xx_eth_shared_driver = {
2396 .probe = mv643xx_eth_shared_probe,
2397 .remove = mv643xx_eth_shared_remove,
2398 .driver = {
2399 .name = MV643XX_ETH_SHARED_NAME,
2400 .owner = THIS_MODULE,
2401 },
2402 };
2403
2404 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2405 {
2406 int addr_shift = 5 * mp->port_num;
2407 u32 data;
2408
2409 data = rdl(mp, PHY_ADDR);
2410 data &= ~(0x1f << addr_shift);
2411 data |= (phy_addr & 0x1f) << addr_shift;
2412 wrl(mp, PHY_ADDR, data);
2413 }
2414
2415 static int phy_addr_get(struct mv643xx_eth_private *mp)
2416 {
2417 unsigned int data;
2418
2419 data = rdl(mp, PHY_ADDR);
2420
2421 return (data >> (5 * mp->port_num)) & 0x1f;
2422 }
2423
2424 static void set_params(struct mv643xx_eth_private *mp,
2425 struct mv643xx_eth_platform_data *pd)
2426 {
2427 struct net_device *dev = mp->dev;
2428
2429 if (is_valid_ether_addr(pd->mac_addr))
2430 memcpy(dev->dev_addr, pd->mac_addr, 6);
2431 else
2432 uc_addr_get(mp, dev->dev_addr);
2433
2434 if (pd->phy_addr == -1) {
2435 mp->shared_smi = NULL;
2436 mp->phy_addr = -1;
2437 } else {
2438 mp->shared_smi = mp->shared;
2439 if (pd->shared_smi != NULL)
2440 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2441
2442 if (pd->force_phy_addr || pd->phy_addr) {
2443 mp->phy_addr = pd->phy_addr & 0x3f;
2444 phy_addr_set(mp, mp->phy_addr);
2445 } else {
2446 mp->phy_addr = phy_addr_get(mp);
2447 }
2448 }
2449
2450 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2451 if (pd->rx_queue_size)
2452 mp->default_rx_ring_size = pd->rx_queue_size;
2453 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2454 mp->rx_desc_sram_size = pd->rx_sram_size;
2455
2456 if (pd->rx_queue_mask)
2457 mp->rxq_mask = pd->rx_queue_mask;
2458 else
2459 mp->rxq_mask = 0x01;
2460 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2461
2462 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2463 if (pd->tx_queue_size)
2464 mp->default_tx_ring_size = pd->tx_queue_size;
2465 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2466 mp->tx_desc_sram_size = pd->tx_sram_size;
2467
2468 if (pd->tx_queue_mask)
2469 mp->txq_mask = pd->tx_queue_mask;
2470 else
2471 mp->txq_mask = 0x01;
2472 mp->txq_primary = fls(mp->txq_mask) - 1;
2473 }
2474
2475 static int phy_detect(struct mv643xx_eth_private *mp)
2476 {
2477 int data;
2478 int data2;
2479
2480 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2481 if (data < 0)
2482 return -ENODEV;
2483
2484 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2485 return -ENODEV;
2486
2487 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2488 if (data2 < 0)
2489 return -ENODEV;
2490
2491 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2492 return -ENODEV;
2493
2494 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2495
2496 return 0;
2497 }
2498
2499 static int phy_init(struct mv643xx_eth_private *mp,
2500 struct mv643xx_eth_platform_data *pd)
2501 {
2502 struct ethtool_cmd cmd;
2503 int err;
2504
2505 err = phy_detect(mp);
2506 if (err) {
2507 dev_printk(KERN_INFO, &mp->dev->dev,
2508 "no PHY detected at addr %d\n", mp->phy_addr);
2509 return err;
2510 }
2511 phy_reset(mp);
2512
2513 mp->mii.phy_id = mp->phy_addr;
2514 mp->mii.phy_id_mask = 0x3f;
2515 mp->mii.reg_num_mask = 0x1f;
2516 mp->mii.dev = mp->dev;
2517 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2518 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2519
2520 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2521
2522 memset(&cmd, 0, sizeof(cmd));
2523
2524 cmd.port = PORT_MII;
2525 cmd.transceiver = XCVR_INTERNAL;
2526 cmd.phy_address = mp->phy_addr;
2527 if (pd->speed == 0) {
2528 cmd.autoneg = AUTONEG_ENABLE;
2529 cmd.speed = SPEED_100;
2530 cmd.advertising = ADVERTISED_10baseT_Half |
2531 ADVERTISED_10baseT_Full |
2532 ADVERTISED_100baseT_Half |
2533 ADVERTISED_100baseT_Full;
2534 if (mp->mii.supports_gmii)
2535 cmd.advertising |= ADVERTISED_1000baseT_Full;
2536 } else {
2537 cmd.autoneg = AUTONEG_DISABLE;
2538 cmd.speed = pd->speed;
2539 cmd.duplex = pd->duplex;
2540 }
2541
2542 mv643xx_eth_set_settings(mp->dev, &cmd);
2543
2544 return 0;
2545 }
2546
2547 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2548 {
2549 u32 pscr;
2550
2551 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2552 if (pscr & SERIAL_PORT_ENABLE) {
2553 pscr &= ~SERIAL_PORT_ENABLE;
2554 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2555 }
2556
2557 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2558 if (mp->phy_addr == -1) {
2559 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2560 if (speed == SPEED_1000)
2561 pscr |= SET_GMII_SPEED_TO_1000;
2562 else if (speed == SPEED_100)
2563 pscr |= SET_MII_SPEED_TO_100;
2564
2565 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2566
2567 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2568 if (duplex == DUPLEX_FULL)
2569 pscr |= SET_FULL_DUPLEX_MODE;
2570 }
2571
2572 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2573 }
2574
2575 static int mv643xx_eth_probe(struct platform_device *pdev)
2576 {
2577 struct mv643xx_eth_platform_data *pd;
2578 struct mv643xx_eth_private *mp;
2579 struct net_device *dev;
2580 struct resource *res;
2581 DECLARE_MAC_BUF(mac);
2582 int err;
2583
2584 pd = pdev->dev.platform_data;
2585 if (pd == NULL) {
2586 dev_printk(KERN_ERR, &pdev->dev,
2587 "no mv643xx_eth_platform_data\n");
2588 return -ENODEV;
2589 }
2590
2591 if (pd->shared == NULL) {
2592 dev_printk(KERN_ERR, &pdev->dev,
2593 "no mv643xx_eth_platform_data->shared\n");
2594 return -ENODEV;
2595 }
2596
2597 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2598 if (!dev)
2599 return -ENOMEM;
2600
2601 mp = netdev_priv(dev);
2602 platform_set_drvdata(pdev, mp);
2603
2604 mp->shared = platform_get_drvdata(pd->shared);
2605 mp->port_num = pd->port_number;
2606
2607 mp->dev = dev;
2608
2609 set_params(mp, pd);
2610
2611 spin_lock_init(&mp->lock);
2612
2613 mib_counters_clear(mp);
2614 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2615
2616 if (mp->phy_addr != -1) {
2617 err = phy_init(mp, pd);
2618 if (err)
2619 goto out;
2620
2621 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2622 } else {
2623 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2624 }
2625 init_pscr(mp, pd->speed, pd->duplex);
2626
2627 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2628
2629 init_timer(&mp->rx_oom);
2630 mp->rx_oom.data = (unsigned long)mp;
2631 mp->rx_oom.function = oom_timer_wrapper;
2632
2633
2634 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2635 BUG_ON(!res);
2636 dev->irq = res->start;
2637
2638 dev->hard_start_xmit = mv643xx_eth_xmit;
2639 dev->open = mv643xx_eth_open;
2640 dev->stop = mv643xx_eth_stop;
2641 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2642 dev->set_mac_address = mv643xx_eth_set_mac_address;
2643 dev->do_ioctl = mv643xx_eth_ioctl;
2644 dev->change_mtu = mv643xx_eth_change_mtu;
2645 dev->tx_timeout = mv643xx_eth_tx_timeout;
2646 #ifdef CONFIG_NET_POLL_CONTROLLER
2647 dev->poll_controller = mv643xx_eth_netpoll;
2648 #endif
2649 dev->watchdog_timeo = 2 * HZ;
2650 dev->base_addr = 0;
2651
2652 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2653 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2654
2655 SET_NETDEV_DEV(dev, &pdev->dev);
2656
2657 if (mp->shared->win_protect)
2658 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2659
2660 err = register_netdev(dev);
2661 if (err)
2662 goto out;
2663
2664 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2665 mp->port_num, print_mac(mac, dev->dev_addr));
2666
2667 if (mp->tx_desc_sram_size > 0)
2668 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2669
2670 return 0;
2671
2672 out:
2673 free_netdev(dev);
2674
2675 return err;
2676 }
2677
2678 static int mv643xx_eth_remove(struct platform_device *pdev)
2679 {
2680 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2681
2682 unregister_netdev(mp->dev);
2683 flush_scheduled_work();
2684 free_netdev(mp->dev);
2685
2686 platform_set_drvdata(pdev, NULL);
2687
2688 return 0;
2689 }
2690
2691 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2692 {
2693 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2694
2695 /* Mask all interrupts on ethernet port */
2696 wrl(mp, INT_MASK(mp->port_num), 0);
2697 rdl(mp, INT_MASK(mp->port_num));
2698
2699 if (netif_running(mp->dev))
2700 port_reset(mp);
2701 }
2702
2703 static struct platform_driver mv643xx_eth_driver = {
2704 .probe = mv643xx_eth_probe,
2705 .remove = mv643xx_eth_remove,
2706 .shutdown = mv643xx_eth_shutdown,
2707 .driver = {
2708 .name = MV643XX_ETH_NAME,
2709 .owner = THIS_MODULE,
2710 },
2711 };
2712
2713 static int __init mv643xx_eth_init_module(void)
2714 {
2715 int rc;
2716
2717 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2718 if (!rc) {
2719 rc = platform_driver_register(&mv643xx_eth_driver);
2720 if (rc)
2721 platform_driver_unregister(&mv643xx_eth_shared_driver);
2722 }
2723
2724 return rc;
2725 }
2726 module_init(mv643xx_eth_init_module);
2727
2728 static void __exit mv643xx_eth_cleanup_module(void)
2729 {
2730 platform_driver_unregister(&mv643xx_eth_driver);
2731 platform_driver_unregister(&mv643xx_eth_shared_driver);
2732 }
2733 module_exit(mv643xx_eth_cleanup_module);
2734
2735 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2736 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2737 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2738 MODULE_LICENSE("GPL");
2739 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2740 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
kernel source for telekom puls (alcatel/mediatek)