2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/etherdevice.h>
45 #include <linux/delay.h>
46 #include <linux/ethtool.h>
47 #include <linux/platform_device.h>
48 #include <linux/module.h>
49 #include <linux/kernel.h>
50 #include <linux/spinlock.h>
51 #include <linux/workqueue.h>
52 #include <linux/phy.h>
53 #include <linux/mv643xx_eth.h>
55 #include <linux/types.h>
56 #include <linux/inet_lro.h>
57 #include <asm/system.h>
59 static char mv643xx_eth_driver_name
[] = "mv643xx_eth";
60 static char mv643xx_eth_driver_version
[] = "1.4";
64 * Registers shared between all ports.
66 #define PHY_ADDR 0x0000
67 #define SMI_REG 0x0004
68 #define SMI_BUSY 0x10000000
69 #define SMI_READ_VALID 0x08000000
70 #define SMI_OPCODE_READ 0x04000000
71 #define SMI_OPCODE_WRITE 0x00000000
72 #define ERR_INT_CAUSE 0x0080
73 #define ERR_INT_SMI_DONE 0x00000010
74 #define ERR_INT_MASK 0x0084
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
82 * Main per-port registers. These live at offset 0x0400 for
83 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
85 #define PORT_CONFIG 0x0000
86 #define UNICAST_PROMISCUOUS_MODE 0x00000001
87 #define PORT_CONFIG_EXT 0x0004
88 #define MAC_ADDR_LOW 0x0014
89 #define MAC_ADDR_HIGH 0x0018
90 #define SDMA_CONFIG 0x001c
91 #define PORT_SERIAL_CONTROL 0x003c
92 #define PORT_STATUS 0x0044
93 #define TX_FIFO_EMPTY 0x00000400
94 #define TX_IN_PROGRESS 0x00000080
95 #define PORT_SPEED_MASK 0x00000030
96 #define PORT_SPEED_1000 0x00000010
97 #define PORT_SPEED_100 0x00000020
98 #define PORT_SPEED_10 0x00000000
99 #define FLOW_CONTROL_ENABLED 0x00000008
100 #define FULL_DUPLEX 0x00000004
101 #define LINK_UP 0x00000002
102 #define TXQ_COMMAND 0x0048
103 #define TXQ_FIX_PRIO_CONF 0x004c
104 #define TX_BW_RATE 0x0050
105 #define TX_BW_MTU 0x0058
106 #define TX_BW_BURST 0x005c
107 #define INT_CAUSE 0x0060
108 #define INT_TX_END 0x07f80000
109 #define INT_RX 0x000003fc
110 #define INT_EXT 0x00000002
111 #define INT_CAUSE_EXT 0x0064
112 #define INT_EXT_LINK_PHY 0x00110000
113 #define INT_EXT_TX 0x000000ff
114 #define INT_MASK 0x0068
115 #define INT_MASK_EXT 0x006c
116 #define TX_FIFO_URGENT_THRESHOLD 0x0074
117 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
118 #define TX_BW_RATE_MOVED 0x00e0
119 #define TX_BW_MTU_MOVED 0x00e8
120 #define TX_BW_BURST_MOVED 0x00ec
121 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
122 #define RXQ_COMMAND 0x0280
123 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
124 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
125 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
126 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
129 * Misc per-port registers.
131 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
132 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
133 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
134 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
138 * SDMA configuration register.
140 #define RX_BURST_SIZE_4_64BIT (2 << 1)
141 #define RX_BURST_SIZE_16_64BIT (4 << 1)
142 #define BLM_RX_NO_SWAP (1 << 4)
143 #define BLM_TX_NO_SWAP (1 << 5)
144 #define TX_BURST_SIZE_4_64BIT (2 << 22)
145 #define TX_BURST_SIZE_16_64BIT (4 << 22)
147 #if defined(__BIG_ENDIAN)
148 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
149 (RX_BURST_SIZE_4_64BIT | \
150 TX_BURST_SIZE_4_64BIT)
151 #elif defined(__LITTLE_ENDIAN)
152 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
153 (RX_BURST_SIZE_4_64BIT | \
156 TX_BURST_SIZE_4_64BIT)
158 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
163 * Port serial control register.
165 #define SET_MII_SPEED_TO_100 (1 << 24)
166 #define SET_GMII_SPEED_TO_1000 (1 << 23)
167 #define SET_FULL_DUPLEX_MODE (1 << 21)
168 #define MAX_RX_PACKET_9700BYTE (5 << 17)
169 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
170 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
171 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
172 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
173 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
174 #define FORCE_LINK_PASS (1 << 1)
175 #define SERIAL_PORT_ENABLE (1 << 0)
177 #define DEFAULT_RX_QUEUE_SIZE 128
178 #define DEFAULT_TX_QUEUE_SIZE 256
184 #if defined(__BIG_ENDIAN)
186 u16 byte_cnt
; /* Descriptor buffer byte count */
187 u16 buf_size
; /* Buffer size */
188 u32 cmd_sts
; /* Descriptor command status */
189 u32 next_desc_ptr
; /* Next descriptor pointer */
190 u32 buf_ptr
; /* Descriptor buffer pointer */
194 u16 byte_cnt
; /* buffer byte count */
195 u16 l4i_chk
; /* CPU provided TCP checksum */
196 u32 cmd_sts
; /* Command/status field */
197 u32 next_desc_ptr
; /* Pointer to next descriptor */
198 u32 buf_ptr
; /* pointer to buffer for this descriptor*/
200 #elif defined(__LITTLE_ENDIAN)
202 u32 cmd_sts
; /* Descriptor command status */
203 u16 buf_size
; /* Buffer size */
204 u16 byte_cnt
; /* Descriptor buffer byte count */
205 u32 buf_ptr
; /* Descriptor buffer pointer */
206 u32 next_desc_ptr
; /* Next descriptor pointer */
210 u32 cmd_sts
; /* Command/status field */
211 u16 l4i_chk
; /* CPU provided TCP checksum */
212 u16 byte_cnt
; /* buffer byte count */
213 u32 buf_ptr
; /* pointer to buffer for this descriptor*/
214 u32 next_desc_ptr
; /* Pointer to next descriptor */
217 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
220 /* RX & TX descriptor command */
221 #define BUFFER_OWNED_BY_DMA 0x80000000
223 /* RX & TX descriptor status */
224 #define ERROR_SUMMARY 0x00000001
226 /* RX descriptor status */
227 #define LAYER_4_CHECKSUM_OK 0x40000000
228 #define RX_ENABLE_INTERRUPT 0x20000000
229 #define RX_FIRST_DESC 0x08000000
230 #define RX_LAST_DESC 0x04000000
231 #define RX_IP_HDR_OK 0x02000000
232 #define RX_PKT_IS_IPV4 0x01000000
233 #define RX_PKT_IS_ETHERNETV2 0x00800000
234 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
235 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
236 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
238 /* TX descriptor command */
239 #define TX_ENABLE_INTERRUPT 0x00800000
240 #define GEN_CRC 0x00400000
241 #define TX_FIRST_DESC 0x00200000
242 #define TX_LAST_DESC 0x00100000
243 #define ZERO_PADDING 0x00080000
244 #define GEN_IP_V4_CHECKSUM 0x00040000
245 #define GEN_TCP_UDP_CHECKSUM 0x00020000
246 #define UDP_FRAME 0x00010000
247 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
248 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
250 #define TX_IHL_SHIFT 11
253 /* global *******************************************************************/
254 struct mv643xx_eth_shared_private
{
256 * Ethernet controller base address.
261 * Points at the right SMI instance to use.
263 struct mv643xx_eth_shared_private
*smi
;
266 * Provides access to local SMI interface.
268 struct mii_bus
*smi_bus
;
271 * If we have access to the error interrupt pin (which is
272 * somewhat misnamed as it not only reflects internal errors
273 * but also reflects SMI completion), use that to wait for
274 * SMI access completion instead of polling the SMI busy bit.
277 wait_queue_head_t smi_busy_wait
;
280 * Per-port MBUS window access register value.
285 * Hardware-specific parameters.
288 int extended_rx_coal_limit
;
292 #define TX_BW_CONTROL_ABSENT 0
293 #define TX_BW_CONTROL_OLD_LAYOUT 1
294 #define TX_BW_CONTROL_NEW_LAYOUT 2
296 static int mv643xx_eth_open(struct net_device
*dev
);
297 static int mv643xx_eth_stop(struct net_device
*dev
);
300 /* per-port *****************************************************************/
301 struct mib_counters
{
302 u64 good_octets_received
;
303 u32 bad_octets_received
;
304 u32 internal_mac_transmit_err
;
305 u32 good_frames_received
;
306 u32 bad_frames_received
;
307 u32 broadcast_frames_received
;
308 u32 multicast_frames_received
;
309 u32 frames_64_octets
;
310 u32 frames_65_to_127_octets
;
311 u32 frames_128_to_255_octets
;
312 u32 frames_256_to_511_octets
;
313 u32 frames_512_to_1023_octets
;
314 u32 frames_1024_to_max_octets
;
315 u64 good_octets_sent
;
316 u32 good_frames_sent
;
317 u32 excessive_collision
;
318 u32 multicast_frames_sent
;
319 u32 broadcast_frames_sent
;
320 u32 unrec_mac_control_received
;
322 u32 good_fc_received
;
324 u32 undersize_received
;
325 u32 fragments_received
;
326 u32 oversize_received
;
328 u32 mac_receive_error
;
334 struct lro_counters
{
349 struct rx_desc
*rx_desc_area
;
350 dma_addr_t rx_desc_dma
;
351 int rx_desc_area_size
;
352 struct sk_buff
**rx_skb
;
354 struct net_lro_mgr lro_mgr
;
355 struct net_lro_desc lro_arr
[8];
367 struct tx_desc
*tx_desc_area
;
368 dma_addr_t tx_desc_dma
;
369 int tx_desc_area_size
;
371 struct sk_buff_head tx_skb
;
373 unsigned long tx_packets
;
374 unsigned long tx_bytes
;
375 unsigned long tx_dropped
;
378 struct mv643xx_eth_private
{
379 struct mv643xx_eth_shared_private
*shared
;
383 struct net_device
*dev
;
385 struct phy_device
*phy
;
387 struct timer_list mib_counters_timer
;
388 spinlock_t mib_counters_lock
;
389 struct mib_counters mib_counters
;
391 struct lro_counters lro_counters
;
393 struct work_struct tx_timeout_task
;
395 struct napi_struct napi
;
404 struct sk_buff_head rx_recycle
;
410 unsigned long rx_desc_sram_addr
;
411 int rx_desc_sram_size
;
413 struct timer_list rx_oom
;
414 struct rx_queue rxq
[8];
420 unsigned long tx_desc_sram_addr
;
421 int tx_desc_sram_size
;
423 struct tx_queue txq
[8];
427 /* port register accessors **************************************************/
428 static inline u32
rdl(struct mv643xx_eth_private
*mp
, int offset
)
430 return readl(mp
->shared
->base
+ offset
);
433 static inline u32
rdlp(struct mv643xx_eth_private
*mp
, int offset
)
435 return readl(mp
->base
+ offset
);
438 static inline void wrl(struct mv643xx_eth_private
*mp
, int offset
, u32 data
)
440 writel(data
, mp
->shared
->base
+ offset
);
443 static inline void wrlp(struct mv643xx_eth_private
*mp
, int offset
, u32 data
)
445 writel(data
, mp
->base
+ offset
);
449 /* rxq/txq helper functions *************************************************/
450 static struct mv643xx_eth_private
*rxq_to_mp(struct rx_queue
*rxq
)
452 return container_of(rxq
, struct mv643xx_eth_private
, rxq
[rxq
->index
]);
455 static struct mv643xx_eth_private
*txq_to_mp(struct tx_queue
*txq
)
457 return container_of(txq
, struct mv643xx_eth_private
, txq
[txq
->index
]);
460 static void rxq_enable(struct rx_queue
*rxq
)
462 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
463 wrlp(mp
, RXQ_COMMAND
, 1 << rxq
->index
);
466 static void rxq_disable(struct rx_queue
*rxq
)
468 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
469 u8 mask
= 1 << rxq
->index
;
471 wrlp(mp
, RXQ_COMMAND
, mask
<< 8);
472 while (rdlp(mp
, RXQ_COMMAND
) & mask
)
476 static void txq_reset_hw_ptr(struct tx_queue
*txq
)
478 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
481 addr
= (u32
)txq
->tx_desc_dma
;
482 addr
+= txq
->tx_curr_desc
* sizeof(struct tx_desc
);
483 wrlp(mp
, TXQ_CURRENT_DESC_PTR(txq
->index
), addr
);
486 static void txq_enable(struct tx_queue
*txq
)
488 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
489 wrlp(mp
, TXQ_COMMAND
, 1 << txq
->index
);
492 static void txq_disable(struct tx_queue
*txq
)
494 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
495 u8 mask
= 1 << txq
->index
;
497 wrlp(mp
, TXQ_COMMAND
, mask
<< 8);
498 while (rdlp(mp
, TXQ_COMMAND
) & mask
)
502 static void txq_maybe_wake(struct tx_queue
*txq
)
504 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
505 struct netdev_queue
*nq
= netdev_get_tx_queue(mp
->dev
, txq
->index
);
507 if (netif_tx_queue_stopped(nq
)) {
508 __netif_tx_lock(nq
, smp_processor_id());
509 if (txq
->tx_ring_size
- txq
->tx_desc_count
>= MAX_SKB_FRAGS
+ 1)
510 netif_tx_wake_queue(nq
);
511 __netif_tx_unlock(nq
);
516 /* rx napi ******************************************************************/
518 mv643xx_get_skb_header(struct sk_buff
*skb
, void **iphdr
, void **tcph
,
519 u64
*hdr_flags
, void *priv
)
521 unsigned long cmd_sts
= (unsigned long)priv
;
524 * Make sure that this packet is Ethernet II, is not VLAN
525 * tagged, is IPv4, has a valid IP header, and is TCP.
527 if ((cmd_sts
& (RX_IP_HDR_OK
| RX_PKT_IS_IPV4
|
528 RX_PKT_IS_ETHERNETV2
| RX_PKT_LAYER4_TYPE_MASK
|
529 RX_PKT_IS_VLAN_TAGGED
)) !=
530 (RX_IP_HDR_OK
| RX_PKT_IS_IPV4
|
531 RX_PKT_IS_ETHERNETV2
| RX_PKT_LAYER4_TYPE_TCP_IPV4
))
534 skb_reset_network_header(skb
);
535 skb_set_transport_header(skb
, ip_hdrlen(skb
));
536 *iphdr
= ip_hdr(skb
);
537 *tcph
= tcp_hdr(skb
);
538 *hdr_flags
= LRO_IPV4
| LRO_TCP
;
543 static int rxq_process(struct rx_queue
*rxq
, int budget
)
545 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
546 struct net_device_stats
*stats
= &mp
->dev
->stats
;
547 int lro_flush_needed
;
550 lro_flush_needed
= 0;
552 while (rx
< budget
&& rxq
->rx_desc_count
) {
553 struct rx_desc
*rx_desc
;
554 unsigned int cmd_sts
;
558 rx_desc
= &rxq
->rx_desc_area
[rxq
->rx_curr_desc
];
560 cmd_sts
= rx_desc
->cmd_sts
;
561 if (cmd_sts
& BUFFER_OWNED_BY_DMA
)
565 skb
= rxq
->rx_skb
[rxq
->rx_curr_desc
];
566 rxq
->rx_skb
[rxq
->rx_curr_desc
] = NULL
;
569 if (rxq
->rx_curr_desc
== rxq
->rx_ring_size
)
570 rxq
->rx_curr_desc
= 0;
572 dma_unmap_single(NULL
, rx_desc
->buf_ptr
,
573 rx_desc
->buf_size
, DMA_FROM_DEVICE
);
574 rxq
->rx_desc_count
--;
577 mp
->work_rx_refill
|= 1 << rxq
->index
;
579 byte_cnt
= rx_desc
->byte_cnt
;
584 * Note that the descriptor byte count includes 2 dummy
585 * bytes automatically inserted by the hardware at the
586 * start of the packet (which we don't count), and a 4
587 * byte CRC at the end of the packet (which we do count).
590 stats
->rx_bytes
+= byte_cnt
- 2;
593 * In case we received a packet without first / last bits
594 * on, or the error summary bit is set, the packet needs
597 if ((cmd_sts
& (RX_FIRST_DESC
| RX_LAST_DESC
| ERROR_SUMMARY
))
598 != (RX_FIRST_DESC
| RX_LAST_DESC
))
602 * The -4 is for the CRC in the trailer of the
605 skb_put(skb
, byte_cnt
- 2 - 4);
607 if (cmd_sts
& LAYER_4_CHECKSUM_OK
)
608 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
609 skb
->protocol
= eth_type_trans(skb
, mp
->dev
);
611 if (skb
->dev
->features
& NETIF_F_LRO
&&
612 skb
->ip_summed
== CHECKSUM_UNNECESSARY
) {
613 lro_receive_skb(&rxq
->lro_mgr
, skb
, (void *)cmd_sts
);
614 lro_flush_needed
= 1;
616 netif_receive_skb(skb
);
623 if ((cmd_sts
& (RX_FIRST_DESC
| RX_LAST_DESC
)) !=
624 (RX_FIRST_DESC
| RX_LAST_DESC
)) {
626 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
627 "received packet spanning "
628 "multiple descriptors\n");
631 if (cmd_sts
& ERROR_SUMMARY
)
637 if (lro_flush_needed
)
638 lro_flush_all(&rxq
->lro_mgr
);
641 mp
->work_rx
&= ~(1 << rxq
->index
);
646 static int rxq_refill(struct rx_queue
*rxq
, int budget
)
648 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
652 while (refilled
< budget
&& rxq
->rx_desc_count
< rxq
->rx_ring_size
) {
656 struct rx_desc
*rx_desc
;
658 skb
= __skb_dequeue(&mp
->rx_recycle
);
660 skb
= dev_alloc_skb(mp
->skb_size
+
661 dma_get_cache_alignment() - 1);
668 unaligned
= (u32
)skb
->data
& (dma_get_cache_alignment() - 1);
670 skb_reserve(skb
, dma_get_cache_alignment() - unaligned
);
673 rxq
->rx_desc_count
++;
675 rx
= rxq
->rx_used_desc
++;
676 if (rxq
->rx_used_desc
== rxq
->rx_ring_size
)
677 rxq
->rx_used_desc
= 0;
679 rx_desc
= rxq
->rx_desc_area
+ rx
;
681 rx_desc
->buf_ptr
= dma_map_single(NULL
, skb
->data
,
682 mp
->skb_size
, DMA_FROM_DEVICE
);
683 rx_desc
->buf_size
= mp
->skb_size
;
684 rxq
->rx_skb
[rx
] = skb
;
686 rx_desc
->cmd_sts
= BUFFER_OWNED_BY_DMA
| RX_ENABLE_INTERRUPT
;
690 * The hardware automatically prepends 2 bytes of
691 * dummy data to each received packet, so that the
692 * IP header ends up 16-byte aligned.
697 if (refilled
< budget
)
698 mp
->work_rx_refill
&= ~(1 << rxq
->index
);
705 /* tx ***********************************************************************/
706 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff
*skb
)
710 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
711 skb_frag_t
*fragp
= &skb_shinfo(skb
)->frags
[frag
];
712 if (fragp
->size
<= 8 && fragp
->page_offset
& 7)
719 static void txq_submit_frag_skb(struct tx_queue
*txq
, struct sk_buff
*skb
)
721 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
724 for (frag
= 0; frag
< nr_frags
; frag
++) {
725 skb_frag_t
*this_frag
;
727 struct tx_desc
*desc
;
729 this_frag
= &skb_shinfo(skb
)->frags
[frag
];
730 tx_index
= txq
->tx_curr_desc
++;
731 if (txq
->tx_curr_desc
== txq
->tx_ring_size
)
732 txq
->tx_curr_desc
= 0;
733 desc
= &txq
->tx_desc_area
[tx_index
];
736 * The last fragment will generate an interrupt
737 * which will free the skb on TX completion.
739 if (frag
== nr_frags
- 1) {
740 desc
->cmd_sts
= BUFFER_OWNED_BY_DMA
|
741 ZERO_PADDING
| TX_LAST_DESC
|
744 desc
->cmd_sts
= BUFFER_OWNED_BY_DMA
;
748 desc
->byte_cnt
= this_frag
->size
;
749 desc
->buf_ptr
= dma_map_page(NULL
, this_frag
->page
,
750 this_frag
->page_offset
,
756 static inline __be16
sum16_as_be(__sum16 sum
)
758 return (__force __be16
)sum
;
761 static int txq_submit_skb(struct tx_queue
*txq
, struct sk_buff
*skb
)
763 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
764 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
766 struct tx_desc
*desc
;
771 cmd_sts
= TX_FIRST_DESC
| GEN_CRC
| BUFFER_OWNED_BY_DMA
;
774 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
777 BUG_ON(skb
->protocol
!= htons(ETH_P_IP
) &&
778 skb
->protocol
!= htons(ETH_P_8021Q
));
780 tag_bytes
= (void *)ip_hdr(skb
) - (void *)skb
->data
- ETH_HLEN
;
781 if (unlikely(tag_bytes
& ~12)) {
782 if (skb_checksum_help(skb
) == 0)
789 cmd_sts
|= MAC_HDR_EXTRA_4_BYTES
;
791 cmd_sts
|= MAC_HDR_EXTRA_8_BYTES
;
793 cmd_sts
|= GEN_TCP_UDP_CHECKSUM
|
795 ip_hdr(skb
)->ihl
<< TX_IHL_SHIFT
;
797 switch (ip_hdr(skb
)->protocol
) {
799 cmd_sts
|= UDP_FRAME
;
800 l4i_chk
= ntohs(sum16_as_be(udp_hdr(skb
)->check
));
803 l4i_chk
= ntohs(sum16_as_be(tcp_hdr(skb
)->check
));
810 /* Errata BTS #50, IHL must be 5 if no HW checksum */
811 cmd_sts
|= 5 << TX_IHL_SHIFT
;
814 tx_index
= txq
->tx_curr_desc
++;
815 if (txq
->tx_curr_desc
== txq
->tx_ring_size
)
816 txq
->tx_curr_desc
= 0;
817 desc
= &txq
->tx_desc_area
[tx_index
];
820 txq_submit_frag_skb(txq
, skb
);
821 length
= skb_headlen(skb
);
823 cmd_sts
|= ZERO_PADDING
| TX_LAST_DESC
| TX_ENABLE_INTERRUPT
;
827 desc
->l4i_chk
= l4i_chk
;
828 desc
->byte_cnt
= length
;
829 desc
->buf_ptr
= dma_map_single(NULL
, skb
->data
, length
, DMA_TO_DEVICE
);
831 __skb_queue_tail(&txq
->tx_skb
, skb
);
833 /* ensure all other descriptors are written before first cmd_sts */
835 desc
->cmd_sts
= cmd_sts
;
837 /* clear TX_END status */
838 mp
->work_tx_end
&= ~(1 << txq
->index
);
840 /* ensure all descriptors are written before poking hardware */
844 txq
->tx_desc_count
+= nr_frags
+ 1;
849 static int mv643xx_eth_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
851 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
853 struct tx_queue
*txq
;
854 struct netdev_queue
*nq
;
856 queue
= skb_get_queue_mapping(skb
);
857 txq
= mp
->txq
+ queue
;
858 nq
= netdev_get_tx_queue(dev
, queue
);
860 if (has_tiny_unaligned_frags(skb
) && __skb_linearize(skb
)) {
862 dev_printk(KERN_DEBUG
, &dev
->dev
,
863 "failed to linearize skb with tiny "
864 "unaligned fragment\n");
865 return NETDEV_TX_BUSY
;
868 if (txq
->tx_ring_size
- txq
->tx_desc_count
< MAX_SKB_FRAGS
+ 1) {
870 dev_printk(KERN_ERR
, &dev
->dev
, "tx queue full?!\n");
875 if (!txq_submit_skb(txq
, skb
)) {
878 txq
->tx_bytes
+= skb
->len
;
880 dev
->trans_start
= jiffies
;
882 entries_left
= txq
->tx_ring_size
- txq
->tx_desc_count
;
883 if (entries_left
< MAX_SKB_FRAGS
+ 1)
884 netif_tx_stop_queue(nq
);
891 /* tx napi ******************************************************************/
892 static void txq_kick(struct tx_queue
*txq
)
894 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
895 struct netdev_queue
*nq
= netdev_get_tx_queue(mp
->dev
, txq
->index
);
899 __netif_tx_lock(nq
, smp_processor_id());
901 if (rdlp(mp
, TXQ_COMMAND
) & (1 << txq
->index
))
904 hw_desc_ptr
= rdlp(mp
, TXQ_CURRENT_DESC_PTR(txq
->index
));
905 expected_ptr
= (u32
)txq
->tx_desc_dma
+
906 txq
->tx_curr_desc
* sizeof(struct tx_desc
);
908 if (hw_desc_ptr
!= expected_ptr
)
912 __netif_tx_unlock(nq
);
914 mp
->work_tx_end
&= ~(1 << txq
->index
);
917 static int txq_reclaim(struct tx_queue
*txq
, int budget
, int force
)
919 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
920 struct netdev_queue
*nq
= netdev_get_tx_queue(mp
->dev
, txq
->index
);
923 __netif_tx_lock(nq
, smp_processor_id());
926 while (reclaimed
< budget
&& txq
->tx_desc_count
> 0) {
928 struct tx_desc
*desc
;
932 tx_index
= txq
->tx_used_desc
;
933 desc
= &txq
->tx_desc_area
[tx_index
];
934 cmd_sts
= desc
->cmd_sts
;
936 if (cmd_sts
& BUFFER_OWNED_BY_DMA
) {
939 desc
->cmd_sts
= cmd_sts
& ~BUFFER_OWNED_BY_DMA
;
942 txq
->tx_used_desc
= tx_index
+ 1;
943 if (txq
->tx_used_desc
== txq
->tx_ring_size
)
944 txq
->tx_used_desc
= 0;
947 txq
->tx_desc_count
--;
950 if (cmd_sts
& TX_LAST_DESC
)
951 skb
= __skb_dequeue(&txq
->tx_skb
);
953 if (cmd_sts
& ERROR_SUMMARY
) {
954 dev_printk(KERN_INFO
, &mp
->dev
->dev
, "tx error\n");
955 mp
->dev
->stats
.tx_errors
++;
958 if (cmd_sts
& TX_FIRST_DESC
) {
959 dma_unmap_single(NULL
, desc
->buf_ptr
,
960 desc
->byte_cnt
, DMA_TO_DEVICE
);
962 dma_unmap_page(NULL
, desc
->buf_ptr
,
963 desc
->byte_cnt
, DMA_TO_DEVICE
);
967 if (skb_queue_len(&mp
->rx_recycle
) <
969 skb_recycle_check(skb
, mp
->skb_size
+
970 dma_get_cache_alignment() - 1))
971 __skb_queue_head(&mp
->rx_recycle
, skb
);
977 __netif_tx_unlock(nq
);
979 if (reclaimed
< budget
)
980 mp
->work_tx
&= ~(1 << txq
->index
);
986 /* tx rate control **********************************************************/
988 * Set total maximum TX rate (shared by all TX queues for this port)
989 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
991 static void tx_set_rate(struct mv643xx_eth_private
*mp
, int rate
, int burst
)
997 token_rate
= ((rate
/ 1000) * 64) / (mp
->shared
->t_clk
/ 1000);
998 if (token_rate
> 1023)
1001 mtu
= (mp
->dev
->mtu
+ 255) >> 8;
1005 bucket_size
= (burst
+ 255) >> 8;
1006 if (bucket_size
> 65535)
1007 bucket_size
= 65535;
1009 switch (mp
->shared
->tx_bw_control
) {
1010 case TX_BW_CONTROL_OLD_LAYOUT
:
1011 wrlp(mp
, TX_BW_RATE
, token_rate
);
1012 wrlp(mp
, TX_BW_MTU
, mtu
);
1013 wrlp(mp
, TX_BW_BURST
, bucket_size
);
1015 case TX_BW_CONTROL_NEW_LAYOUT
:
1016 wrlp(mp
, TX_BW_RATE_MOVED
, token_rate
);
1017 wrlp(mp
, TX_BW_MTU_MOVED
, mtu
);
1018 wrlp(mp
, TX_BW_BURST_MOVED
, bucket_size
);
1023 static void txq_set_rate(struct tx_queue
*txq
, int rate
, int burst
)
1025 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
1029 token_rate
= ((rate
/ 1000) * 64) / (mp
->shared
->t_clk
/ 1000);
1030 if (token_rate
> 1023)
1033 bucket_size
= (burst
+ 255) >> 8;
1034 if (bucket_size
> 65535)
1035 bucket_size
= 65535;
1037 wrlp(mp
, TXQ_BW_TOKENS(txq
->index
), token_rate
<< 14);
1038 wrlp(mp
, TXQ_BW_CONF(txq
->index
), (bucket_size
<< 10) | token_rate
);
1041 static void txq_set_fixed_prio_mode(struct tx_queue
*txq
)
1043 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
1048 * Turn on fixed priority mode.
1051 switch (mp
->shared
->tx_bw_control
) {
1052 case TX_BW_CONTROL_OLD_LAYOUT
:
1053 off
= TXQ_FIX_PRIO_CONF
;
1055 case TX_BW_CONTROL_NEW_LAYOUT
:
1056 off
= TXQ_FIX_PRIO_CONF_MOVED
;
1061 val
= rdlp(mp
, off
);
1062 val
|= 1 << txq
->index
;
1067 static void txq_set_wrr(struct tx_queue
*txq
, int weight
)
1069 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
1074 * Turn off fixed priority mode.
1077 switch (mp
->shared
->tx_bw_control
) {
1078 case TX_BW_CONTROL_OLD_LAYOUT
:
1079 off
= TXQ_FIX_PRIO_CONF
;
1081 case TX_BW_CONTROL_NEW_LAYOUT
:
1082 off
= TXQ_FIX_PRIO_CONF_MOVED
;
1087 val
= rdlp(mp
, off
);
1088 val
&= ~(1 << txq
->index
);
1092 * Configure WRR weight for this queue.
1095 val
= rdlp(mp
, off
);
1096 val
= (val
& ~0xff) | (weight
& 0xff);
1097 wrlp(mp
, TXQ_BW_WRR_CONF(txq
->index
), val
);
1102 /* mii management interface *************************************************/
1103 static irqreturn_t
mv643xx_eth_err_irq(int irq
, void *dev_id
)
1105 struct mv643xx_eth_shared_private
*msp
= dev_id
;
1107 if (readl(msp
->base
+ ERR_INT_CAUSE
) & ERR_INT_SMI_DONE
) {
1108 writel(~ERR_INT_SMI_DONE
, msp
->base
+ ERR_INT_CAUSE
);
1109 wake_up(&msp
->smi_busy_wait
);
1116 static int smi_is_done(struct mv643xx_eth_shared_private
*msp
)
1118 return !(readl(msp
->base
+ SMI_REG
) & SMI_BUSY
);
1121 static int smi_wait_ready(struct mv643xx_eth_shared_private
*msp
)
1123 if (msp
->err_interrupt
== NO_IRQ
) {
1126 for (i
= 0; !smi_is_done(msp
); i
++) {
1135 if (!smi_is_done(msp
)) {
1136 wait_event_timeout(msp
->smi_busy_wait
, smi_is_done(msp
),
1137 msecs_to_jiffies(100));
1138 if (!smi_is_done(msp
))
1145 static int smi_bus_read(struct mii_bus
*bus
, int addr
, int reg
)
1147 struct mv643xx_eth_shared_private
*msp
= bus
->priv
;
1148 void __iomem
*smi_reg
= msp
->base
+ SMI_REG
;
1151 if (smi_wait_ready(msp
)) {
1152 printk(KERN_WARNING
"mv643xx_eth: SMI bus busy timeout\n");
1156 writel(SMI_OPCODE_READ
| (reg
<< 21) | (addr
<< 16), smi_reg
);
1158 if (smi_wait_ready(msp
)) {
1159 printk(KERN_WARNING
"mv643xx_eth: SMI bus busy timeout\n");
1163 ret
= readl(smi_reg
);
1164 if (!(ret
& SMI_READ_VALID
)) {
1165 printk(KERN_WARNING
"mv643xx_eth: SMI bus read not valid\n");
1169 return ret
& 0xffff;
1172 static int smi_bus_write(struct mii_bus
*bus
, int addr
, int reg
, u16 val
)
1174 struct mv643xx_eth_shared_private
*msp
= bus
->priv
;
1175 void __iomem
*smi_reg
= msp
->base
+ SMI_REG
;
1177 if (smi_wait_ready(msp
)) {
1178 printk(KERN_WARNING
"mv643xx_eth: SMI bus busy timeout\n");
1182 writel(SMI_OPCODE_WRITE
| (reg
<< 21) |
1183 (addr
<< 16) | (val
& 0xffff), smi_reg
);
1185 if (smi_wait_ready(msp
)) {
1186 printk(KERN_WARNING
"mv643xx_eth: SMI bus busy timeout\n");
1194 /* statistics ***************************************************************/
1195 static struct net_device_stats
*mv643xx_eth_get_stats(struct net_device
*dev
)
1197 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1198 struct net_device_stats
*stats
= &dev
->stats
;
1199 unsigned long tx_packets
= 0;
1200 unsigned long tx_bytes
= 0;
1201 unsigned long tx_dropped
= 0;
1204 for (i
= 0; i
< mp
->txq_count
; i
++) {
1205 struct tx_queue
*txq
= mp
->txq
+ i
;
1207 tx_packets
+= txq
->tx_packets
;
1208 tx_bytes
+= txq
->tx_bytes
;
1209 tx_dropped
+= txq
->tx_dropped
;
1212 stats
->tx_packets
= tx_packets
;
1213 stats
->tx_bytes
= tx_bytes
;
1214 stats
->tx_dropped
= tx_dropped
;
1219 static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private
*mp
)
1221 u32 lro_aggregated
= 0;
1222 u32 lro_flushed
= 0;
1223 u32 lro_no_desc
= 0;
1226 for (i
= 0; i
< mp
->rxq_count
; i
++) {
1227 struct rx_queue
*rxq
= mp
->rxq
+ i
;
1229 lro_aggregated
+= rxq
->lro_mgr
.stats
.aggregated
;
1230 lro_flushed
+= rxq
->lro_mgr
.stats
.flushed
;
1231 lro_no_desc
+= rxq
->lro_mgr
.stats
.no_desc
;
1234 mp
->lro_counters
.lro_aggregated
= lro_aggregated
;
1235 mp
->lro_counters
.lro_flushed
= lro_flushed
;
1236 mp
->lro_counters
.lro_no_desc
= lro_no_desc
;
1239 static inline u32
mib_read(struct mv643xx_eth_private
*mp
, int offset
)
1241 return rdl(mp
, MIB_COUNTERS(mp
->port_num
) + offset
);
1244 static void mib_counters_clear(struct mv643xx_eth_private
*mp
)
1248 for (i
= 0; i
< 0x80; i
+= 4)
1252 static void mib_counters_update(struct mv643xx_eth_private
*mp
)
1254 struct mib_counters
*p
= &mp
->mib_counters
;
1256 spin_lock_bh(&mp
->mib_counters_lock
);
1257 p
->good_octets_received
+= mib_read(mp
, 0x00);
1258 p
->bad_octets_received
+= mib_read(mp
, 0x08);
1259 p
->internal_mac_transmit_err
+= mib_read(mp
, 0x0c);
1260 p
->good_frames_received
+= mib_read(mp
, 0x10);
1261 p
->bad_frames_received
+= mib_read(mp
, 0x14);
1262 p
->broadcast_frames_received
+= mib_read(mp
, 0x18);
1263 p
->multicast_frames_received
+= mib_read(mp
, 0x1c);
1264 p
->frames_64_octets
+= mib_read(mp
, 0x20);
1265 p
->frames_65_to_127_octets
+= mib_read(mp
, 0x24);
1266 p
->frames_128_to_255_octets
+= mib_read(mp
, 0x28);
1267 p
->frames_256_to_511_octets
+= mib_read(mp
, 0x2c);
1268 p
->frames_512_to_1023_octets
+= mib_read(mp
, 0x30);
1269 p
->frames_1024_to_max_octets
+= mib_read(mp
, 0x34);
1270 p
->good_octets_sent
+= mib_read(mp
, 0x38);
1271 p
->good_frames_sent
+= mib_read(mp
, 0x40);
1272 p
->excessive_collision
+= mib_read(mp
, 0x44);
1273 p
->multicast_frames_sent
+= mib_read(mp
, 0x48);
1274 p
->broadcast_frames_sent
+= mib_read(mp
, 0x4c);
1275 p
->unrec_mac_control_received
+= mib_read(mp
, 0x50);
1276 p
->fc_sent
+= mib_read(mp
, 0x54);
1277 p
->good_fc_received
+= mib_read(mp
, 0x58);
1278 p
->bad_fc_received
+= mib_read(mp
, 0x5c);
1279 p
->undersize_received
+= mib_read(mp
, 0x60);
1280 p
->fragments_received
+= mib_read(mp
, 0x64);
1281 p
->oversize_received
+= mib_read(mp
, 0x68);
1282 p
->jabber_received
+= mib_read(mp
, 0x6c);
1283 p
->mac_receive_error
+= mib_read(mp
, 0x70);
1284 p
->bad_crc_event
+= mib_read(mp
, 0x74);
1285 p
->collision
+= mib_read(mp
, 0x78);
1286 p
->late_collision
+= mib_read(mp
, 0x7c);
1287 spin_unlock_bh(&mp
->mib_counters_lock
);
1289 mod_timer(&mp
->mib_counters_timer
, jiffies
+ 30 * HZ
);
1292 static void mib_counters_timer_wrapper(unsigned long _mp
)
1294 struct mv643xx_eth_private
*mp
= (void *)_mp
;
1296 mib_counters_update(mp
);
1300 /* interrupt coalescing *****************************************************/
1302 * Hardware coalescing parameters are set in units of 64 t_clk
1305 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1307 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1309 * In the ->set*() methods, we round the computed register value
1310 * to the nearest integer.
1312 static unsigned int get_rx_coal(struct mv643xx_eth_private
*mp
)
1314 u32 val
= rdlp(mp
, SDMA_CONFIG
);
1317 if (mp
->shared
->extended_rx_coal_limit
)
1318 temp
= ((val
& 0x02000000) >> 10) | ((val
& 0x003fff80) >> 7);
1320 temp
= (val
& 0x003fff00) >> 8;
1323 do_div(temp
, mp
->shared
->t_clk
);
1325 return (unsigned int)temp
;
1328 static void set_rx_coal(struct mv643xx_eth_private
*mp
, unsigned int usec
)
1333 temp
= (u64
)usec
* mp
->shared
->t_clk
;
1335 do_div(temp
, 64000000);
1337 val
= rdlp(mp
, SDMA_CONFIG
);
1338 if (mp
->shared
->extended_rx_coal_limit
) {
1342 val
|= (temp
& 0x8000) << 10;
1343 val
|= (temp
& 0x7fff) << 7;
1348 val
|= (temp
& 0x3fff) << 8;
1350 wrlp(mp
, SDMA_CONFIG
, val
);
1353 static unsigned int get_tx_coal(struct mv643xx_eth_private
*mp
)
1357 temp
= (rdlp(mp
, TX_FIFO_URGENT_THRESHOLD
) & 0x3fff0) >> 4;
1359 do_div(temp
, mp
->shared
->t_clk
);
1361 return (unsigned int)temp
;
1364 static void set_tx_coal(struct mv643xx_eth_private
*mp
, unsigned int usec
)
1368 temp
= (u64
)usec
* mp
->shared
->t_clk
;
1370 do_div(temp
, 64000000);
1375 wrlp(mp
, TX_FIFO_URGENT_THRESHOLD
, temp
<< 4);
1379 /* ethtool ******************************************************************/
1380 struct mv643xx_eth_stats
{
1381 char stat_string
[ETH_GSTRING_LEN
];
1388 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1389 offsetof(struct net_device, stats.m), -1 }
1391 #define MIBSTAT(m) \
1392 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1393 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1395 #define LROSTAT(m) \
1396 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1397 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1399 static const struct mv643xx_eth_stats mv643xx_eth_stats
[] = {
1408 MIBSTAT(good_octets_received
),
1409 MIBSTAT(bad_octets_received
),
1410 MIBSTAT(internal_mac_transmit_err
),
1411 MIBSTAT(good_frames_received
),
1412 MIBSTAT(bad_frames_received
),
1413 MIBSTAT(broadcast_frames_received
),
1414 MIBSTAT(multicast_frames_received
),
1415 MIBSTAT(frames_64_octets
),
1416 MIBSTAT(frames_65_to_127_octets
),
1417 MIBSTAT(frames_128_to_255_octets
),
1418 MIBSTAT(frames_256_to_511_octets
),
1419 MIBSTAT(frames_512_to_1023_octets
),
1420 MIBSTAT(frames_1024_to_max_octets
),
1421 MIBSTAT(good_octets_sent
),
1422 MIBSTAT(good_frames_sent
),
1423 MIBSTAT(excessive_collision
),
1424 MIBSTAT(multicast_frames_sent
),
1425 MIBSTAT(broadcast_frames_sent
),
1426 MIBSTAT(unrec_mac_control_received
),
1428 MIBSTAT(good_fc_received
),
1429 MIBSTAT(bad_fc_received
),
1430 MIBSTAT(undersize_received
),
1431 MIBSTAT(fragments_received
),
1432 MIBSTAT(oversize_received
),
1433 MIBSTAT(jabber_received
),
1434 MIBSTAT(mac_receive_error
),
1435 MIBSTAT(bad_crc_event
),
1437 MIBSTAT(late_collision
),
1438 LROSTAT(lro_aggregated
),
1439 LROSTAT(lro_flushed
),
1440 LROSTAT(lro_no_desc
),
1444 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private
*mp
,
1445 struct ethtool_cmd
*cmd
)
1449 err
= phy_read_status(mp
->phy
);
1451 err
= phy_ethtool_gset(mp
->phy
, cmd
);
1454 * The MAC does not support 1000baseT_Half.
1456 cmd
->supported
&= ~SUPPORTED_1000baseT_Half
;
1457 cmd
->advertising
&= ~ADVERTISED_1000baseT_Half
;
1463 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private
*mp
,
1464 struct ethtool_cmd
*cmd
)
1468 port_status
= rdlp(mp
, PORT_STATUS
);
1470 cmd
->supported
= SUPPORTED_MII
;
1471 cmd
->advertising
= ADVERTISED_MII
;
1472 switch (port_status
& PORT_SPEED_MASK
) {
1474 cmd
->speed
= SPEED_10
;
1476 case PORT_SPEED_100
:
1477 cmd
->speed
= SPEED_100
;
1479 case PORT_SPEED_1000
:
1480 cmd
->speed
= SPEED_1000
;
1486 cmd
->duplex
= (port_status
& FULL_DUPLEX
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1487 cmd
->port
= PORT_MII
;
1488 cmd
->phy_address
= 0;
1489 cmd
->transceiver
= XCVR_INTERNAL
;
1490 cmd
->autoneg
= AUTONEG_DISABLE
;
1498 mv643xx_eth_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1500 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1502 if (mp
->phy
!= NULL
)
1503 return mv643xx_eth_get_settings_phy(mp
, cmd
);
1505 return mv643xx_eth_get_settings_phyless(mp
, cmd
);
1509 mv643xx_eth_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1511 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1513 if (mp
->phy
== NULL
)
1517 * The MAC does not support 1000baseT_Half.
1519 cmd
->advertising
&= ~ADVERTISED_1000baseT_Half
;
1521 return phy_ethtool_sset(mp
->phy
, cmd
);
1524 static void mv643xx_eth_get_drvinfo(struct net_device
*dev
,
1525 struct ethtool_drvinfo
*drvinfo
)
1527 strncpy(drvinfo
->driver
, mv643xx_eth_driver_name
, 32);
1528 strncpy(drvinfo
->version
, mv643xx_eth_driver_version
, 32);
1529 strncpy(drvinfo
->fw_version
, "N/A", 32);
1530 strncpy(drvinfo
->bus_info
, "platform", 32);
1531 drvinfo
->n_stats
= ARRAY_SIZE(mv643xx_eth_stats
);
1534 static int mv643xx_eth_nway_reset(struct net_device
*dev
)
1536 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1538 if (mp
->phy
== NULL
)
1541 return genphy_restart_aneg(mp
->phy
);
1544 static u32
mv643xx_eth_get_link(struct net_device
*dev
)
1546 return !!netif_carrier_ok(dev
);
1550 mv643xx_eth_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
1552 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1554 ec
->rx_coalesce_usecs
= get_rx_coal(mp
);
1555 ec
->tx_coalesce_usecs
= get_tx_coal(mp
);
1561 mv643xx_eth_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
1563 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1565 set_rx_coal(mp
, ec
->rx_coalesce_usecs
);
1566 set_tx_coal(mp
, ec
->tx_coalesce_usecs
);
1572 mv643xx_eth_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*er
)
1574 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1576 er
->rx_max_pending
= 4096;
1577 er
->tx_max_pending
= 4096;
1578 er
->rx_mini_max_pending
= 0;
1579 er
->rx_jumbo_max_pending
= 0;
1581 er
->rx_pending
= mp
->rx_ring_size
;
1582 er
->tx_pending
= mp
->tx_ring_size
;
1583 er
->rx_mini_pending
= 0;
1584 er
->rx_jumbo_pending
= 0;
1588 mv643xx_eth_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*er
)
1590 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1592 if (er
->rx_mini_pending
|| er
->rx_jumbo_pending
)
1595 mp
->rx_ring_size
= er
->rx_pending
< 4096 ? er
->rx_pending
: 4096;
1596 mp
->tx_ring_size
= er
->tx_pending
< 4096 ? er
->tx_pending
: 4096;
1598 if (netif_running(dev
)) {
1599 mv643xx_eth_stop(dev
);
1600 if (mv643xx_eth_open(dev
)) {
1601 dev_printk(KERN_ERR
, &dev
->dev
,
1602 "fatal error on re-opening device after "
1603 "ring param change\n");
1612 mv643xx_eth_get_rx_csum(struct net_device
*dev
)
1614 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1616 return !!(rdlp(mp
, PORT_CONFIG
) & 0x02000000);
1620 mv643xx_eth_set_rx_csum(struct net_device
*dev
, u32 rx_csum
)
1622 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1624 wrlp(mp
, PORT_CONFIG
, rx_csum
? 0x02000000 : 0x00000000);
1629 static void mv643xx_eth_get_strings(struct net_device
*dev
,
1630 uint32_t stringset
, uint8_t *data
)
1634 if (stringset
== ETH_SS_STATS
) {
1635 for (i
= 0; i
< ARRAY_SIZE(mv643xx_eth_stats
); i
++) {
1636 memcpy(data
+ i
* ETH_GSTRING_LEN
,
1637 mv643xx_eth_stats
[i
].stat_string
,
1643 static void mv643xx_eth_get_ethtool_stats(struct net_device
*dev
,
1644 struct ethtool_stats
*stats
,
1647 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1650 mv643xx_eth_get_stats(dev
);
1651 mib_counters_update(mp
);
1652 mv643xx_eth_grab_lro_stats(mp
);
1654 for (i
= 0; i
< ARRAY_SIZE(mv643xx_eth_stats
); i
++) {
1655 const struct mv643xx_eth_stats
*stat
;
1658 stat
= mv643xx_eth_stats
+ i
;
1660 if (stat
->netdev_off
>= 0)
1661 p
= ((void *)mp
->dev
) + stat
->netdev_off
;
1663 p
= ((void *)mp
) + stat
->mp_off
;
1665 data
[i
] = (stat
->sizeof_stat
== 8) ?
1666 *(uint64_t *)p
: *(uint32_t *)p
;
1670 static int mv643xx_eth_get_sset_count(struct net_device
*dev
, int sset
)
1672 if (sset
== ETH_SS_STATS
)
1673 return ARRAY_SIZE(mv643xx_eth_stats
);
1678 static const struct ethtool_ops mv643xx_eth_ethtool_ops
= {
1679 .get_settings
= mv643xx_eth_get_settings
,
1680 .set_settings
= mv643xx_eth_set_settings
,
1681 .get_drvinfo
= mv643xx_eth_get_drvinfo
,
1682 .nway_reset
= mv643xx_eth_nway_reset
,
1683 .get_link
= mv643xx_eth_get_link
,
1684 .get_coalesce
= mv643xx_eth_get_coalesce
,
1685 .set_coalesce
= mv643xx_eth_set_coalesce
,
1686 .get_ringparam
= mv643xx_eth_get_ringparam
,
1687 .set_ringparam
= mv643xx_eth_set_ringparam
,
1688 .get_rx_csum
= mv643xx_eth_get_rx_csum
,
1689 .set_rx_csum
= mv643xx_eth_set_rx_csum
,
1690 .set_tx_csum
= ethtool_op_set_tx_csum
,
1691 .set_sg
= ethtool_op_set_sg
,
1692 .get_strings
= mv643xx_eth_get_strings
,
1693 .get_ethtool_stats
= mv643xx_eth_get_ethtool_stats
,
1694 .get_flags
= ethtool_op_get_flags
,
1695 .set_flags
= ethtool_op_set_flags
,
1696 .get_sset_count
= mv643xx_eth_get_sset_count
,
1700 /* address handling *********************************************************/
1701 static void uc_addr_get(struct mv643xx_eth_private
*mp
, unsigned char *addr
)
1703 unsigned int mac_h
= rdlp(mp
, MAC_ADDR_HIGH
);
1704 unsigned int mac_l
= rdlp(mp
, MAC_ADDR_LOW
);
1706 addr
[0] = (mac_h
>> 24) & 0xff;
1707 addr
[1] = (mac_h
>> 16) & 0xff;
1708 addr
[2] = (mac_h
>> 8) & 0xff;
1709 addr
[3] = mac_h
& 0xff;
1710 addr
[4] = (mac_l
>> 8) & 0xff;
1711 addr
[5] = mac_l
& 0xff;
1714 static void uc_addr_set(struct mv643xx_eth_private
*mp
, unsigned char *addr
)
1716 wrlp(mp
, MAC_ADDR_HIGH
,
1717 (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3]);
1718 wrlp(mp
, MAC_ADDR_LOW
, (addr
[4] << 8) | addr
[5]);
1721 static u32
uc_addr_filter_mask(struct net_device
*dev
)
1723 struct dev_addr_list
*uc_ptr
;
1726 if (dev
->flags
& IFF_PROMISC
)
1729 nibbles
= 1 << (dev
->dev_addr
[5] & 0x0f);
1730 for (uc_ptr
= dev
->uc_list
; uc_ptr
!= NULL
; uc_ptr
= uc_ptr
->next
) {
1731 if (memcmp(dev
->dev_addr
, uc_ptr
->da_addr
, 5))
1733 if ((dev
->dev_addr
[5] ^ uc_ptr
->da_addr
[5]) & 0xf0)
1736 nibbles
|= 1 << (uc_ptr
->da_addr
[5] & 0x0f);
1742 static void mv643xx_eth_program_unicast_filter(struct net_device
*dev
)
1744 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1749 uc_addr_set(mp
, dev
->dev_addr
);
1751 port_config
= rdlp(mp
, PORT_CONFIG
);
1752 nibbles
= uc_addr_filter_mask(dev
);
1754 port_config
|= UNICAST_PROMISCUOUS_MODE
;
1755 wrlp(mp
, PORT_CONFIG
, port_config
);
1759 for (i
= 0; i
< 16; i
+= 4) {
1760 int off
= UNICAST_TABLE(mp
->port_num
) + i
;
1777 port_config
&= ~UNICAST_PROMISCUOUS_MODE
;
1778 wrlp(mp
, PORT_CONFIG
, port_config
);
1781 static int addr_crc(unsigned char *addr
)
1786 for (i
= 0; i
< 6; i
++) {
1789 crc
= (crc
^ addr
[i
]) << 8;
1790 for (j
= 7; j
>= 0; j
--) {
1791 if (crc
& (0x100 << j
))
1799 static void mv643xx_eth_program_multicast_filter(struct net_device
*dev
)
1801 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1804 struct dev_addr_list
*addr
;
1807 if (dev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
)) {
1812 port_num
= mp
->port_num
;
1813 accept
= 0x01010101;
1814 for (i
= 0; i
< 0x100; i
+= 4) {
1815 wrl(mp
, SPECIAL_MCAST_TABLE(port_num
) + i
, accept
);
1816 wrl(mp
, OTHER_MCAST_TABLE(port_num
) + i
, accept
);
1821 mc_spec
= kmalloc(0x200, GFP_ATOMIC
);
1822 if (mc_spec
== NULL
)
1824 mc_other
= mc_spec
+ (0x100 >> 2);
1826 memset(mc_spec
, 0, 0x100);
1827 memset(mc_other
, 0, 0x100);
1829 for (addr
= dev
->mc_list
; addr
!= NULL
; addr
= addr
->next
) {
1830 u8
*a
= addr
->da_addr
;
1834 if (memcmp(a
, "\x01\x00\x5e\x00\x00", 5) == 0) {
1839 entry
= addr_crc(a
);
1842 table
[entry
>> 2] |= 1 << (8 * (entry
& 3));
1845 for (i
= 0; i
< 0x100; i
+= 4) {
1846 wrl(mp
, SPECIAL_MCAST_TABLE(mp
->port_num
) + i
, mc_spec
[i
>> 2]);
1847 wrl(mp
, OTHER_MCAST_TABLE(mp
->port_num
) + i
, mc_other
[i
>> 2]);
1853 static void mv643xx_eth_set_rx_mode(struct net_device
*dev
)
1855 mv643xx_eth_program_unicast_filter(dev
);
1856 mv643xx_eth_program_multicast_filter(dev
);
1859 static int mv643xx_eth_set_mac_address(struct net_device
*dev
, void *addr
)
1861 struct sockaddr
*sa
= addr
;
1863 memcpy(dev
->dev_addr
, sa
->sa_data
, ETH_ALEN
);
1865 netif_addr_lock_bh(dev
);
1866 mv643xx_eth_program_unicast_filter(dev
);
1867 netif_addr_unlock_bh(dev
);
1873 /* rx/tx queue initialisation ***********************************************/
1874 static int rxq_init(struct mv643xx_eth_private
*mp
, int index
)
1876 struct rx_queue
*rxq
= mp
->rxq
+ index
;
1877 struct rx_desc
*rx_desc
;
1883 rxq
->rx_ring_size
= mp
->rx_ring_size
;
1885 rxq
->rx_desc_count
= 0;
1886 rxq
->rx_curr_desc
= 0;
1887 rxq
->rx_used_desc
= 0;
1889 size
= rxq
->rx_ring_size
* sizeof(struct rx_desc
);
1891 if (index
== 0 && size
<= mp
->rx_desc_sram_size
) {
1892 rxq
->rx_desc_area
= ioremap(mp
->rx_desc_sram_addr
,
1893 mp
->rx_desc_sram_size
);
1894 rxq
->rx_desc_dma
= mp
->rx_desc_sram_addr
;
1896 rxq
->rx_desc_area
= dma_alloc_coherent(NULL
, size
,
1901 if (rxq
->rx_desc_area
== NULL
) {
1902 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1903 "can't allocate rx ring (%d bytes)\n", size
);
1906 memset(rxq
->rx_desc_area
, 0, size
);
1908 rxq
->rx_desc_area_size
= size
;
1909 rxq
->rx_skb
= kmalloc(rxq
->rx_ring_size
* sizeof(*rxq
->rx_skb
),
1911 if (rxq
->rx_skb
== NULL
) {
1912 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1913 "can't allocate rx skb ring\n");
1917 rx_desc
= (struct rx_desc
*)rxq
->rx_desc_area
;
1918 for (i
= 0; i
< rxq
->rx_ring_size
; i
++) {
1922 if (nexti
== rxq
->rx_ring_size
)
1925 rx_desc
[i
].next_desc_ptr
= rxq
->rx_desc_dma
+
1926 nexti
* sizeof(struct rx_desc
);
1929 rxq
->lro_mgr
.dev
= mp
->dev
;
1930 memset(&rxq
->lro_mgr
.stats
, 0, sizeof(rxq
->lro_mgr
.stats
));
1931 rxq
->lro_mgr
.features
= LRO_F_NAPI
;
1932 rxq
->lro_mgr
.ip_summed
= CHECKSUM_UNNECESSARY
;
1933 rxq
->lro_mgr
.ip_summed_aggr
= CHECKSUM_UNNECESSARY
;
1934 rxq
->lro_mgr
.max_desc
= ARRAY_SIZE(rxq
->lro_arr
);
1935 rxq
->lro_mgr
.max_aggr
= 32;
1936 rxq
->lro_mgr
.frag_align_pad
= 0;
1937 rxq
->lro_mgr
.lro_arr
= rxq
->lro_arr
;
1938 rxq
->lro_mgr
.get_skb_header
= mv643xx_get_skb_header
;
1940 memset(&rxq
->lro_arr
, 0, sizeof(rxq
->lro_arr
));
1946 if (index
== 0 && size
<= mp
->rx_desc_sram_size
)
1947 iounmap(rxq
->rx_desc_area
);
1949 dma_free_coherent(NULL
, size
,
1957 static void rxq_deinit(struct rx_queue
*rxq
)
1959 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
1964 for (i
= 0; i
< rxq
->rx_ring_size
; i
++) {
1965 if (rxq
->rx_skb
[i
]) {
1966 dev_kfree_skb(rxq
->rx_skb
[i
]);
1967 rxq
->rx_desc_count
--;
1971 if (rxq
->rx_desc_count
) {
1972 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1973 "error freeing rx ring -- %d skbs stuck\n",
1974 rxq
->rx_desc_count
);
1977 if (rxq
->index
== 0 &&
1978 rxq
->rx_desc_area_size
<= mp
->rx_desc_sram_size
)
1979 iounmap(rxq
->rx_desc_area
);
1981 dma_free_coherent(NULL
, rxq
->rx_desc_area_size
,
1982 rxq
->rx_desc_area
, rxq
->rx_desc_dma
);
1987 static int txq_init(struct mv643xx_eth_private
*mp
, int index
)
1989 struct tx_queue
*txq
= mp
->txq
+ index
;
1990 struct tx_desc
*tx_desc
;
1996 txq
->tx_ring_size
= mp
->tx_ring_size
;
1998 txq
->tx_desc_count
= 0;
1999 txq
->tx_curr_desc
= 0;
2000 txq
->tx_used_desc
= 0;
2002 size
= txq
->tx_ring_size
* sizeof(struct tx_desc
);
2004 if (index
== 0 && size
<= mp
->tx_desc_sram_size
) {
2005 txq
->tx_desc_area
= ioremap(mp
->tx_desc_sram_addr
,
2006 mp
->tx_desc_sram_size
);
2007 txq
->tx_desc_dma
= mp
->tx_desc_sram_addr
;
2009 txq
->tx_desc_area
= dma_alloc_coherent(NULL
, size
,
2014 if (txq
->tx_desc_area
== NULL
) {
2015 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
2016 "can't allocate tx ring (%d bytes)\n", size
);
2019 memset(txq
->tx_desc_area
, 0, size
);
2021 txq
->tx_desc_area_size
= size
;
2023 tx_desc
= (struct tx_desc
*)txq
->tx_desc_area
;
2024 for (i
= 0; i
< txq
->tx_ring_size
; i
++) {
2025 struct tx_desc
*txd
= tx_desc
+ i
;
2029 if (nexti
== txq
->tx_ring_size
)
2033 txd
->next_desc_ptr
= txq
->tx_desc_dma
+
2034 nexti
* sizeof(struct tx_desc
);
2037 skb_queue_head_init(&txq
->tx_skb
);
2042 static void txq_deinit(struct tx_queue
*txq
)
2044 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
2047 txq_reclaim(txq
, txq
->tx_ring_size
, 1);
2049 BUG_ON(txq
->tx_used_desc
!= txq
->tx_curr_desc
);
2051 if (txq
->index
== 0 &&
2052 txq
->tx_desc_area_size
<= mp
->tx_desc_sram_size
)
2053 iounmap(txq
->tx_desc_area
);
2055 dma_free_coherent(NULL
, txq
->tx_desc_area_size
,
2056 txq
->tx_desc_area
, txq
->tx_desc_dma
);
2060 /* netdev ops and related ***************************************************/
2061 static int mv643xx_eth_collect_events(struct mv643xx_eth_private
*mp
)
2066 int_cause
= rdlp(mp
, INT_CAUSE
) & (INT_TX_END
| INT_RX
| INT_EXT
);
2071 if (int_cause
& INT_EXT
)
2072 int_cause_ext
= rdlp(mp
, INT_CAUSE_EXT
);
2074 int_cause
&= INT_TX_END
| INT_RX
;
2076 wrlp(mp
, INT_CAUSE
, ~int_cause
);
2077 mp
->work_tx_end
|= ((int_cause
& INT_TX_END
) >> 19) &
2078 ~(rdlp(mp
, TXQ_COMMAND
) & 0xff);
2079 mp
->work_rx
|= (int_cause
& INT_RX
) >> 2;
2082 int_cause_ext
&= INT_EXT_LINK_PHY
| INT_EXT_TX
;
2083 if (int_cause_ext
) {
2084 wrlp(mp
, INT_CAUSE_EXT
, ~int_cause_ext
);
2085 if (int_cause_ext
& INT_EXT_LINK_PHY
)
2087 mp
->work_tx
|= int_cause_ext
& INT_EXT_TX
;
2093 static irqreturn_t
mv643xx_eth_irq(int irq
, void *dev_id
)
2095 struct net_device
*dev
= (struct net_device
*)dev_id
;
2096 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2098 if (unlikely(!mv643xx_eth_collect_events(mp
)))
2101 wrlp(mp
, INT_MASK
, 0);
2102 napi_schedule(&mp
->napi
);
2107 static void handle_link_event(struct mv643xx_eth_private
*mp
)
2109 struct net_device
*dev
= mp
->dev
;
2115 port_status
= rdlp(mp
, PORT_STATUS
);
2116 if (!(port_status
& LINK_UP
)) {
2117 if (netif_carrier_ok(dev
)) {
2120 printk(KERN_INFO
"%s: link down\n", dev
->name
);
2122 netif_carrier_off(dev
);
2124 for (i
= 0; i
< mp
->txq_count
; i
++) {
2125 struct tx_queue
*txq
= mp
->txq
+ i
;
2127 txq_reclaim(txq
, txq
->tx_ring_size
, 1);
2128 txq_reset_hw_ptr(txq
);
2134 switch (port_status
& PORT_SPEED_MASK
) {
2138 case PORT_SPEED_100
:
2141 case PORT_SPEED_1000
:
2148 duplex
= (port_status
& FULL_DUPLEX
) ? 1 : 0;
2149 fc
= (port_status
& FLOW_CONTROL_ENABLED
) ? 1 : 0;
2151 printk(KERN_INFO
"%s: link up, %d Mb/s, %s duplex, "
2152 "flow control %sabled\n", dev
->name
,
2153 speed
, duplex
? "full" : "half",
2156 if (!netif_carrier_ok(dev
))
2157 netif_carrier_on(dev
);
2160 static int mv643xx_eth_poll(struct napi_struct
*napi
, int budget
)
2162 struct mv643xx_eth_private
*mp
;
2165 mp
= container_of(napi
, struct mv643xx_eth_private
, napi
);
2167 if (unlikely(mp
->oom
)) {
2169 del_timer(&mp
->rx_oom
);
2173 while (work_done
< budget
) {
2178 if (mp
->work_link
) {
2180 handle_link_event(mp
);
2184 queue_mask
= mp
->work_tx
| mp
->work_tx_end
| mp
->work_rx
;
2185 if (likely(!mp
->oom
))
2186 queue_mask
|= mp
->work_rx_refill
;
2189 if (mv643xx_eth_collect_events(mp
))
2194 queue
= fls(queue_mask
) - 1;
2195 queue_mask
= 1 << queue
;
2197 work_tbd
= budget
- work_done
;
2201 if (mp
->work_tx_end
& queue_mask
) {
2202 txq_kick(mp
->txq
+ queue
);
2203 } else if (mp
->work_tx
& queue_mask
) {
2204 work_done
+= txq_reclaim(mp
->txq
+ queue
, work_tbd
, 0);
2205 txq_maybe_wake(mp
->txq
+ queue
);
2206 } else if (mp
->work_rx
& queue_mask
) {
2207 work_done
+= rxq_process(mp
->rxq
+ queue
, work_tbd
);
2208 } else if (!mp
->oom
&& (mp
->work_rx_refill
& queue_mask
)) {
2209 work_done
+= rxq_refill(mp
->rxq
+ queue
, work_tbd
);
2215 if (work_done
< budget
) {
2217 mod_timer(&mp
->rx_oom
, jiffies
+ (HZ
/ 10));
2218 napi_complete(napi
);
2219 wrlp(mp
, INT_MASK
, INT_TX_END
| INT_RX
| INT_EXT
);
2225 static inline void oom_timer_wrapper(unsigned long data
)
2227 struct mv643xx_eth_private
*mp
= (void *)data
;
2229 napi_schedule(&mp
->napi
);
2232 static void phy_reset(struct mv643xx_eth_private
*mp
)
2236 data
= phy_read(mp
->phy
, MII_BMCR
);
2241 if (phy_write(mp
->phy
, MII_BMCR
, data
) < 0)
2245 data
= phy_read(mp
->phy
, MII_BMCR
);
2246 } while (data
>= 0 && data
& BMCR_RESET
);
2249 static void port_start(struct mv643xx_eth_private
*mp
)
2255 * Perform PHY reset, if there is a PHY.
2257 if (mp
->phy
!= NULL
) {
2258 struct ethtool_cmd cmd
;
2260 mv643xx_eth_get_settings(mp
->dev
, &cmd
);
2262 mv643xx_eth_set_settings(mp
->dev
, &cmd
);
2266 * Configure basic link parameters.
2268 pscr
= rdlp(mp
, PORT_SERIAL_CONTROL
);
2270 pscr
|= SERIAL_PORT_ENABLE
;
2271 wrlp(mp
, PORT_SERIAL_CONTROL
, pscr
);
2273 pscr
|= DO_NOT_FORCE_LINK_FAIL
;
2274 if (mp
->phy
== NULL
)
2275 pscr
|= FORCE_LINK_PASS
;
2276 wrlp(mp
, PORT_SERIAL_CONTROL
, pscr
);
2279 * Configure TX path and queues.
2281 tx_set_rate(mp
, 1000000000, 16777216);
2282 for (i
= 0; i
< mp
->txq_count
; i
++) {
2283 struct tx_queue
*txq
= mp
->txq
+ i
;
2285 txq_reset_hw_ptr(txq
);
2286 txq_set_rate(txq
, 1000000000, 16777216);
2287 txq_set_fixed_prio_mode(txq
);
2291 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2292 * frames to RX queue #0, and include the pseudo-header when
2293 * calculating receive checksums.
2295 wrlp(mp
, PORT_CONFIG
, 0x02000000);
2298 * Treat BPDUs as normal multicasts, and disable partition mode.
2300 wrlp(mp
, PORT_CONFIG_EXT
, 0x00000000);
2303 * Add configured unicast addresses to address filter table.
2305 mv643xx_eth_program_unicast_filter(mp
->dev
);
2308 * Enable the receive queues.
2310 for (i
= 0; i
< mp
->rxq_count
; i
++) {
2311 struct rx_queue
*rxq
= mp
->rxq
+ i
;
2314 addr
= (u32
)rxq
->rx_desc_dma
;
2315 addr
+= rxq
->rx_curr_desc
* sizeof(struct rx_desc
);
2316 wrlp(mp
, RXQ_CURRENT_DESC_PTR(i
), addr
);
2322 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private
*mp
)
2327 * Reserve 2+14 bytes for an ethernet header (the hardware
2328 * automatically prepends 2 bytes of dummy data to each
2329 * received packet), 16 bytes for up to four VLAN tags, and
2330 * 4 bytes for the trailing FCS -- 36 bytes total.
2332 skb_size
= mp
->dev
->mtu
+ 36;
2335 * Make sure that the skb size is a multiple of 8 bytes, as
2336 * the lower three bits of the receive descriptor's buffer
2337 * size field are ignored by the hardware.
2339 mp
->skb_size
= (skb_size
+ 7) & ~7;
2342 static int mv643xx_eth_open(struct net_device
*dev
)
2344 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2348 wrlp(mp
, INT_CAUSE
, 0);
2349 wrlp(mp
, INT_CAUSE_EXT
, 0);
2350 rdlp(mp
, INT_CAUSE_EXT
);
2352 err
= request_irq(dev
->irq
, mv643xx_eth_irq
,
2353 IRQF_SHARED
, dev
->name
, dev
);
2355 dev_printk(KERN_ERR
, &dev
->dev
, "can't assign irq\n");
2359 mv643xx_eth_recalc_skb_size(mp
);
2361 napi_enable(&mp
->napi
);
2363 skb_queue_head_init(&mp
->rx_recycle
);
2365 for (i
= 0; i
< mp
->rxq_count
; i
++) {
2366 err
= rxq_init(mp
, i
);
2369 rxq_deinit(mp
->rxq
+ i
);
2373 rxq_refill(mp
->rxq
+ i
, INT_MAX
);
2377 mp
->rx_oom
.expires
= jiffies
+ (HZ
/ 10);
2378 add_timer(&mp
->rx_oom
);
2381 for (i
= 0; i
< mp
->txq_count
; i
++) {
2382 err
= txq_init(mp
, i
);
2385 txq_deinit(mp
->txq
+ i
);
2392 wrlp(mp
, INT_MASK_EXT
, INT_EXT_LINK_PHY
| INT_EXT_TX
);
2393 wrlp(mp
, INT_MASK
, INT_TX_END
| INT_RX
| INT_EXT
);
2399 for (i
= 0; i
< mp
->rxq_count
; i
++)
2400 rxq_deinit(mp
->rxq
+ i
);
2402 free_irq(dev
->irq
, dev
);
2407 static void port_reset(struct mv643xx_eth_private
*mp
)
2412 for (i
= 0; i
< mp
->rxq_count
; i
++)
2413 rxq_disable(mp
->rxq
+ i
);
2414 for (i
= 0; i
< mp
->txq_count
; i
++)
2415 txq_disable(mp
->txq
+ i
);
2418 u32 ps
= rdlp(mp
, PORT_STATUS
);
2420 if ((ps
& (TX_IN_PROGRESS
| TX_FIFO_EMPTY
)) == TX_FIFO_EMPTY
)
2425 /* Reset the Enable bit in the Configuration Register */
2426 data
= rdlp(mp
, PORT_SERIAL_CONTROL
);
2427 data
&= ~(SERIAL_PORT_ENABLE
|
2428 DO_NOT_FORCE_LINK_FAIL
|
2430 wrlp(mp
, PORT_SERIAL_CONTROL
, data
);
2433 static int mv643xx_eth_stop(struct net_device
*dev
)
2435 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2438 wrlp(mp
, INT_MASK_EXT
, 0x00000000);
2439 wrlp(mp
, INT_MASK
, 0x00000000);
2442 napi_disable(&mp
->napi
);
2444 del_timer_sync(&mp
->rx_oom
);
2446 netif_carrier_off(dev
);
2448 free_irq(dev
->irq
, dev
);
2451 mv643xx_eth_get_stats(dev
);
2452 mib_counters_update(mp
);
2453 del_timer_sync(&mp
->mib_counters_timer
);
2455 skb_queue_purge(&mp
->rx_recycle
);
2457 for (i
= 0; i
< mp
->rxq_count
; i
++)
2458 rxq_deinit(mp
->rxq
+ i
);
2459 for (i
= 0; i
< mp
->txq_count
; i
++)
2460 txq_deinit(mp
->txq
+ i
);
2465 static int mv643xx_eth_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2467 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2469 if (mp
->phy
!= NULL
)
2470 return phy_mii_ioctl(mp
->phy
, if_mii(ifr
), cmd
);
2475 static int mv643xx_eth_change_mtu(struct net_device
*dev
, int new_mtu
)
2477 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2479 if (new_mtu
< 64 || new_mtu
> 9500)
2483 mv643xx_eth_recalc_skb_size(mp
);
2484 tx_set_rate(mp
, 1000000000, 16777216);
2486 if (!netif_running(dev
))
2490 * Stop and then re-open the interface. This will allocate RX
2491 * skbs of the new MTU.
2492 * There is a possible danger that the open will not succeed,
2493 * due to memory being full.
2495 mv643xx_eth_stop(dev
);
2496 if (mv643xx_eth_open(dev
)) {
2497 dev_printk(KERN_ERR
, &dev
->dev
,
2498 "fatal error on re-opening device after "
2505 static void tx_timeout_task(struct work_struct
*ugly
)
2507 struct mv643xx_eth_private
*mp
;
2509 mp
= container_of(ugly
, struct mv643xx_eth_private
, tx_timeout_task
);
2510 if (netif_running(mp
->dev
)) {
2511 netif_tx_stop_all_queues(mp
->dev
);
2514 netif_tx_wake_all_queues(mp
->dev
);
2518 static void mv643xx_eth_tx_timeout(struct net_device
*dev
)
2520 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2522 dev_printk(KERN_INFO
, &dev
->dev
, "tx timeout\n");
2524 schedule_work(&mp
->tx_timeout_task
);
2527 #ifdef CONFIG_NET_POLL_CONTROLLER
2528 static void mv643xx_eth_netpoll(struct net_device
*dev
)
2530 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2532 wrlp(mp
, INT_MASK
, 0x00000000);
2535 mv643xx_eth_irq(dev
->irq
, dev
);
2537 wrlp(mp
, INT_MASK
, INT_TX_END
| INT_RX
| INT_EXT
);
2542 /* platform glue ************************************************************/
2544 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private
*msp
,
2545 struct mbus_dram_target_info
*dram
)
2547 void __iomem
*base
= msp
->base
;
2552 for (i
= 0; i
< 6; i
++) {
2553 writel(0, base
+ WINDOW_BASE(i
));
2554 writel(0, base
+ WINDOW_SIZE(i
));
2556 writel(0, base
+ WINDOW_REMAP_HIGH(i
));
2562 for (i
= 0; i
< dram
->num_cs
; i
++) {
2563 struct mbus_dram_window
*cs
= dram
->cs
+ i
;
2565 writel((cs
->base
& 0xffff0000) |
2566 (cs
->mbus_attr
<< 8) |
2567 dram
->mbus_dram_target_id
, base
+ WINDOW_BASE(i
));
2568 writel((cs
->size
- 1) & 0xffff0000, base
+ WINDOW_SIZE(i
));
2570 win_enable
&= ~(1 << i
);
2571 win_protect
|= 3 << (2 * i
);
2574 writel(win_enable
, base
+ WINDOW_BAR_ENABLE
);
2575 msp
->win_protect
= win_protect
;
2578 static void infer_hw_params(struct mv643xx_eth_shared_private
*msp
)
2581 * Check whether we have a 14-bit coal limit field in bits
2582 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2583 * SDMA config register.
2585 writel(0x02000000, msp
->base
+ 0x0400 + SDMA_CONFIG
);
2586 if (readl(msp
->base
+ 0x0400 + SDMA_CONFIG
) & 0x02000000)
2587 msp
->extended_rx_coal_limit
= 1;
2589 msp
->extended_rx_coal_limit
= 0;
2592 * Check whether the MAC supports TX rate control, and if
2593 * yes, whether its associated registers are in the old or
2596 writel(1, msp
->base
+ 0x0400 + TX_BW_MTU_MOVED
);
2597 if (readl(msp
->base
+ 0x0400 + TX_BW_MTU_MOVED
) & 1) {
2598 msp
->tx_bw_control
= TX_BW_CONTROL_NEW_LAYOUT
;
2600 writel(7, msp
->base
+ 0x0400 + TX_BW_RATE
);
2601 if (readl(msp
->base
+ 0x0400 + TX_BW_RATE
) & 7)
2602 msp
->tx_bw_control
= TX_BW_CONTROL_OLD_LAYOUT
;
2604 msp
->tx_bw_control
= TX_BW_CONTROL_ABSENT
;
2608 static int mv643xx_eth_shared_probe(struct platform_device
*pdev
)
2610 static int mv643xx_eth_version_printed
;
2611 struct mv643xx_eth_shared_platform_data
*pd
= pdev
->dev
.platform_data
;
2612 struct mv643xx_eth_shared_private
*msp
;
2613 struct resource
*res
;
2616 if (!mv643xx_eth_version_printed
++)
2617 printk(KERN_NOTICE
"MV-643xx 10/100/1000 ethernet "
2618 "driver version %s\n", mv643xx_eth_driver_version
);
2621 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2626 msp
= kmalloc(sizeof(*msp
), GFP_KERNEL
);
2629 memset(msp
, 0, sizeof(*msp
));
2631 msp
->base
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
2632 if (msp
->base
== NULL
)
2636 * Set up and register SMI bus.
2638 if (pd
== NULL
|| pd
->shared_smi
== NULL
) {
2639 msp
->smi_bus
= mdiobus_alloc();
2640 if (msp
->smi_bus
== NULL
)
2643 msp
->smi_bus
->priv
= msp
;
2644 msp
->smi_bus
->name
= "mv643xx_eth smi";
2645 msp
->smi_bus
->read
= smi_bus_read
;
2646 msp
->smi_bus
->write
= smi_bus_write
,
2647 snprintf(msp
->smi_bus
->id
, MII_BUS_ID_SIZE
, "%d", pdev
->id
);
2648 msp
->smi_bus
->parent
= &pdev
->dev
;
2649 msp
->smi_bus
->phy_mask
= 0xffffffff;
2650 if (mdiobus_register(msp
->smi_bus
) < 0)
2651 goto out_free_mii_bus
;
2654 msp
->smi
= platform_get_drvdata(pd
->shared_smi
);
2657 msp
->err_interrupt
= NO_IRQ
;
2658 init_waitqueue_head(&msp
->smi_busy_wait
);
2661 * Check whether the error interrupt is hooked up.
2663 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
2667 err
= request_irq(res
->start
, mv643xx_eth_err_irq
,
2668 IRQF_SHARED
, "mv643xx_eth", msp
);
2670 writel(ERR_INT_SMI_DONE
, msp
->base
+ ERR_INT_MASK
);
2671 msp
->err_interrupt
= res
->start
;
2676 * (Re-)program MBUS remapping windows if we are asked to.
2678 if (pd
!= NULL
&& pd
->dram
!= NULL
)
2679 mv643xx_eth_conf_mbus_windows(msp
, pd
->dram
);
2682 * Detect hardware parameters.
2684 msp
->t_clk
= (pd
!= NULL
&& pd
->t_clk
!= 0) ? pd
->t_clk
: 133000000;
2685 infer_hw_params(msp
);
2687 platform_set_drvdata(pdev
, msp
);
2692 mdiobus_free(msp
->smi_bus
);
2701 static int mv643xx_eth_shared_remove(struct platform_device
*pdev
)
2703 struct mv643xx_eth_shared_private
*msp
= platform_get_drvdata(pdev
);
2704 struct mv643xx_eth_shared_platform_data
*pd
= pdev
->dev
.platform_data
;
2706 if (pd
== NULL
|| pd
->shared_smi
== NULL
) {
2707 mdiobus_unregister(msp
->smi_bus
);
2708 mdiobus_free(msp
->smi_bus
);
2710 if (msp
->err_interrupt
!= NO_IRQ
)
2711 free_irq(msp
->err_interrupt
, msp
);
2718 static struct platform_driver mv643xx_eth_shared_driver
= {
2719 .probe
= mv643xx_eth_shared_probe
,
2720 .remove
= mv643xx_eth_shared_remove
,
2722 .name
= MV643XX_ETH_SHARED_NAME
,
2723 .owner
= THIS_MODULE
,
2727 static void phy_addr_set(struct mv643xx_eth_private
*mp
, int phy_addr
)
2729 int addr_shift
= 5 * mp
->port_num
;
2732 data
= rdl(mp
, PHY_ADDR
);
2733 data
&= ~(0x1f << addr_shift
);
2734 data
|= (phy_addr
& 0x1f) << addr_shift
;
2735 wrl(mp
, PHY_ADDR
, data
);
2738 static int phy_addr_get(struct mv643xx_eth_private
*mp
)
2742 data
= rdl(mp
, PHY_ADDR
);
2744 return (data
>> (5 * mp
->port_num
)) & 0x1f;
2747 static void set_params(struct mv643xx_eth_private
*mp
,
2748 struct mv643xx_eth_platform_data
*pd
)
2750 struct net_device
*dev
= mp
->dev
;
2752 if (is_valid_ether_addr(pd
->mac_addr
))
2753 memcpy(dev
->dev_addr
, pd
->mac_addr
, 6);
2755 uc_addr_get(mp
, dev
->dev_addr
);
2757 mp
->rx_ring_size
= DEFAULT_RX_QUEUE_SIZE
;
2758 if (pd
->rx_queue_size
)
2759 mp
->rx_ring_size
= pd
->rx_queue_size
;
2760 mp
->rx_desc_sram_addr
= pd
->rx_sram_addr
;
2761 mp
->rx_desc_sram_size
= pd
->rx_sram_size
;
2763 mp
->rxq_count
= pd
->rx_queue_count
? : 1;
2765 mp
->tx_ring_size
= DEFAULT_TX_QUEUE_SIZE
;
2766 if (pd
->tx_queue_size
)
2767 mp
->tx_ring_size
= pd
->tx_queue_size
;
2768 mp
->tx_desc_sram_addr
= pd
->tx_sram_addr
;
2769 mp
->tx_desc_sram_size
= pd
->tx_sram_size
;
2771 mp
->txq_count
= pd
->tx_queue_count
? : 1;
2774 static struct phy_device
*phy_scan(struct mv643xx_eth_private
*mp
,
2777 struct mii_bus
*bus
= mp
->shared
->smi
->smi_bus
;
2778 struct phy_device
*phydev
;
2783 if (phy_addr
== MV643XX_ETH_PHY_ADDR_DEFAULT
) {
2784 start
= phy_addr_get(mp
) & 0x1f;
2787 start
= phy_addr
& 0x1f;
2792 for (i
= 0; i
< num
; i
++) {
2793 int addr
= (start
+ i
) & 0x1f;
2795 if (bus
->phy_map
[addr
] == NULL
)
2796 mdiobus_scan(bus
, addr
);
2798 if (phydev
== NULL
) {
2799 phydev
= bus
->phy_map
[addr
];
2801 phy_addr_set(mp
, addr
);
2808 static void phy_init(struct mv643xx_eth_private
*mp
, int speed
, int duplex
)
2810 struct phy_device
*phy
= mp
->phy
;
2814 phy_attach(mp
->dev
, dev_name(&phy
->dev
), 0, PHY_INTERFACE_MODE_GMII
);
2817 phy
->autoneg
= AUTONEG_ENABLE
;
2820 phy
->advertising
= phy
->supported
| ADVERTISED_Autoneg
;
2822 phy
->autoneg
= AUTONEG_DISABLE
;
2823 phy
->advertising
= 0;
2825 phy
->duplex
= duplex
;
2827 phy_start_aneg(phy
);
2830 static void init_pscr(struct mv643xx_eth_private
*mp
, int speed
, int duplex
)
2834 pscr
= rdlp(mp
, PORT_SERIAL_CONTROL
);
2835 if (pscr
& SERIAL_PORT_ENABLE
) {
2836 pscr
&= ~SERIAL_PORT_ENABLE
;
2837 wrlp(mp
, PORT_SERIAL_CONTROL
, pscr
);
2840 pscr
= MAX_RX_PACKET_9700BYTE
| SERIAL_PORT_CONTROL_RESERVED
;
2841 if (mp
->phy
== NULL
) {
2842 pscr
|= DISABLE_AUTO_NEG_SPEED_GMII
;
2843 if (speed
== SPEED_1000
)
2844 pscr
|= SET_GMII_SPEED_TO_1000
;
2845 else if (speed
== SPEED_100
)
2846 pscr
|= SET_MII_SPEED_TO_100
;
2848 pscr
|= DISABLE_AUTO_NEG_FOR_FLOW_CTRL
;
2850 pscr
|= DISABLE_AUTO_NEG_FOR_DUPLEX
;
2851 if (duplex
== DUPLEX_FULL
)
2852 pscr
|= SET_FULL_DUPLEX_MODE
;
2855 wrlp(mp
, PORT_SERIAL_CONTROL
, pscr
);
2858 static const struct net_device_ops mv643xx_eth_netdev_ops
= {
2859 .ndo_open
= mv643xx_eth_open
,
2860 .ndo_stop
= mv643xx_eth_stop
,
2861 .ndo_start_xmit
= mv643xx_eth_xmit
,
2862 .ndo_set_rx_mode
= mv643xx_eth_set_rx_mode
,
2863 .ndo_set_mac_address
= mv643xx_eth_set_mac_address
,
2864 .ndo_do_ioctl
= mv643xx_eth_ioctl
,
2865 .ndo_change_mtu
= mv643xx_eth_change_mtu
,
2866 .ndo_tx_timeout
= mv643xx_eth_tx_timeout
,
2867 .ndo_get_stats
= mv643xx_eth_get_stats
,
2868 #ifdef CONFIG_NET_POLL_CONTROLLER
2869 .ndo_poll_controller
= mv643xx_eth_netpoll
,
2873 static int mv643xx_eth_probe(struct platform_device
*pdev
)
2875 struct mv643xx_eth_platform_data
*pd
;
2876 struct mv643xx_eth_private
*mp
;
2877 struct net_device
*dev
;
2878 struct resource
*res
;
2881 pd
= pdev
->dev
.platform_data
;
2883 dev_printk(KERN_ERR
, &pdev
->dev
,
2884 "no mv643xx_eth_platform_data\n");
2888 if (pd
->shared
== NULL
) {
2889 dev_printk(KERN_ERR
, &pdev
->dev
,
2890 "no mv643xx_eth_platform_data->shared\n");
2894 dev
= alloc_etherdev_mq(sizeof(struct mv643xx_eth_private
), 8);
2898 mp
= netdev_priv(dev
);
2899 platform_set_drvdata(pdev
, mp
);
2901 mp
->shared
= platform_get_drvdata(pd
->shared
);
2902 mp
->base
= mp
->shared
->base
+ 0x0400 + (pd
->port_number
<< 10);
2903 mp
->port_num
= pd
->port_number
;
2908 dev
->real_num_tx_queues
= mp
->txq_count
;
2910 if (pd
->phy_addr
!= MV643XX_ETH_PHY_NONE
)
2911 mp
->phy
= phy_scan(mp
, pd
->phy_addr
);
2913 if (mp
->phy
!= NULL
)
2914 phy_init(mp
, pd
->speed
, pd
->duplex
);
2916 SET_ETHTOOL_OPS(dev
, &mv643xx_eth_ethtool_ops
);
2918 init_pscr(mp
, pd
->speed
, pd
->duplex
);
2921 mib_counters_clear(mp
);
2923 init_timer(&mp
->mib_counters_timer
);
2924 mp
->mib_counters_timer
.data
= (unsigned long)mp
;
2925 mp
->mib_counters_timer
.function
= mib_counters_timer_wrapper
;
2926 mp
->mib_counters_timer
.expires
= jiffies
+ 30 * HZ
;
2927 add_timer(&mp
->mib_counters_timer
);
2929 spin_lock_init(&mp
->mib_counters_lock
);
2931 INIT_WORK(&mp
->tx_timeout_task
, tx_timeout_task
);
2933 netif_napi_add(dev
, &mp
->napi
, mv643xx_eth_poll
, 128);
2935 init_timer(&mp
->rx_oom
);
2936 mp
->rx_oom
.data
= (unsigned long)mp
;
2937 mp
->rx_oom
.function
= oom_timer_wrapper
;
2940 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
2942 dev
->irq
= res
->start
;
2944 dev
->netdev_ops
= &mv643xx_eth_netdev_ops
;
2946 dev
->watchdog_timeo
= 2 * HZ
;
2949 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
;
2950 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
;
2952 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2954 if (mp
->shared
->win_protect
)
2955 wrl(mp
, WINDOW_PROTECT(mp
->port_num
), mp
->shared
->win_protect
);
2957 netif_carrier_off(dev
);
2959 wrlp(mp
, SDMA_CONFIG
, PORT_SDMA_CONFIG_DEFAULT_VALUE
);
2961 set_rx_coal(mp
, 250);
2964 err
= register_netdev(dev
);
2968 dev_printk(KERN_NOTICE
, &dev
->dev
, "port %d with MAC address %pM\n",
2969 mp
->port_num
, dev
->dev_addr
);
2971 if (mp
->tx_desc_sram_size
> 0)
2972 dev_printk(KERN_NOTICE
, &dev
->dev
, "configured with sram\n");
2982 static int mv643xx_eth_remove(struct platform_device
*pdev
)
2984 struct mv643xx_eth_private
*mp
= platform_get_drvdata(pdev
);
2986 unregister_netdev(mp
->dev
);
2987 if (mp
->phy
!= NULL
)
2988 phy_detach(mp
->phy
);
2989 flush_scheduled_work();
2990 free_netdev(mp
->dev
);
2992 platform_set_drvdata(pdev
, NULL
);
2997 static void mv643xx_eth_shutdown(struct platform_device
*pdev
)
2999 struct mv643xx_eth_private
*mp
= platform_get_drvdata(pdev
);
3001 /* Mask all interrupts on ethernet port */
3002 wrlp(mp
, INT_MASK
, 0);
3005 if (netif_running(mp
->dev
))
3009 static struct platform_driver mv643xx_eth_driver
= {
3010 .probe
= mv643xx_eth_probe
,
3011 .remove
= mv643xx_eth_remove
,
3012 .shutdown
= mv643xx_eth_shutdown
,
3014 .name
= MV643XX_ETH_NAME
,
3015 .owner
= THIS_MODULE
,
3019 static int __init
mv643xx_eth_init_module(void)
3023 rc
= platform_driver_register(&mv643xx_eth_shared_driver
);
3025 rc
= platform_driver_register(&mv643xx_eth_driver
);
3027 platform_driver_unregister(&mv643xx_eth_shared_driver
);
3032 module_init(mv643xx_eth_init_module
);
3034 static void __exit
mv643xx_eth_cleanup_module(void)
3036 platform_driver_unregister(&mv643xx_eth_driver
);
3037 platform_driver_unregister(&mv643xx_eth_shared_driver
);
3039 module_exit(mv643xx_eth_cleanup_module
);
3041 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3042 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3043 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3044 MODULE_LICENSE("GPL");
3045 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME
);
3046 MODULE_ALIAS("platform:" MV643XX_ETH_NAME
);