2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #ifndef __JME_H_INCLUDED__
25 #define __JME_H_INCLUDED__
27 #define DRV_NAME "jme"
28 #define DRV_VERSION "1.0.4"
29 #define PFX DRV_NAME ": "
31 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
32 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
35 * Message related definitions
37 #define JME_DEF_MSG_ENABLE \
44 #define jeprintk(pdev, fmt, args...) \
45 printk(KERN_ERR PFX fmt, ## args)
48 #define tx_dbg(priv, fmt, args...) \
49 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ## args)
51 #define tx_dbg(priv, fmt, args...)
54 #define jme_msg(msglvl, type, priv, fmt, args...) \
55 if (netif_msg_##type(priv)) \
56 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
58 #define msg_probe(priv, fmt, args...) \
59 jme_msg(KERN_INFO, probe, priv, fmt, ## args)
61 #define msg_link(priv, fmt, args...) \
62 jme_msg(KERN_INFO, link, priv, fmt, ## args)
64 #define msg_intr(priv, fmt, args...) \
65 jme_msg(KERN_INFO, intr, priv, fmt, ## args)
67 #define msg_rx_err(priv, fmt, args...) \
68 jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
70 #define msg_rx_status(priv, fmt, args...) \
71 jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
73 #define msg_tx_err(priv, fmt, args...) \
74 jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
76 #define msg_tx_done(priv, fmt, args...) \
77 jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
79 #define msg_tx_queued(priv, fmt, args...) \
80 jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
82 #define msg_hw(priv, fmt, args...) \
83 jme_msg(KERN_ERR, hw, priv, fmt, ## args)
86 * Extra PCI Configuration space interface
88 #define PCI_DCSR_MRRS 0x59
89 #define PCI_DCSR_MRRS_MASK 0x70
91 enum pci_dcsr_mrrs_vals
{
113 __u8 wn
; /* Number of write actions */
114 __u8 rn
; /* Number of read actions */
115 __u8 bitn
; /* Number of bits per action */
116 __u8 spd
; /* The maxim acceptable speed of controller, in MHz.*/
117 __u8 mode
; /* CPOL, CPHA, and Duplex mode of SPI */
119 /* Internal use only */
123 u16 halfclk
; /* Half of clock cycle calculated from spd, in ns */
126 enum jme_spi_op_bits
{
127 SPI_MODE_CPHA
= 0x01,
128 SPI_MODE_CPOL
= 0x02,
132 #define HALF_US 500 /* 500 ns */
133 #define JMESPIIOCTL SIOCDEVPRIVATE
136 * Dynamic(adaptive)/Static PCC values
138 enum dynamic_pcc_values
{
155 unsigned long last_bytes
;
156 unsigned long last_pkts
;
157 unsigned long intr_cnt
;
159 unsigned char attempt
;
162 #define PCC_INTERVAL_US 100000
163 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
164 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
165 #define PCC_P2_THRESHOLD 800
166 #define PCC_INTR_THRESHOLD 800
167 #define PCC_TX_TO 1000
173 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
175 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
176 #define TX_DESC_SIZE 16
178 #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
238 enum jme_txdesc_flags_bits
{
249 #define TXDESC_MSS_SHIFT 2
250 enum jme_txwbdesc_flags_bits
{
253 TXWBFLAG_TMOUT
= 0x20,
254 TXWBFLAG_TRYOUT
= 0x10,
257 TXWBFLAG_ALLERR
= TXWBFLAG_TMOUT
|
262 #define RX_DESC_SIZE 16
264 #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
265 #define RX_BUF_DMA_ALIGN 8
266 #define RX_PREPAD_SIZE 10
267 #define ETH_CRC_LEN 2
268 #define RX_VLANHDR_LEN 2
269 #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
316 enum jme_rxdesc_flags_bits
{
322 enum jme_rxwbdesc_flags_bits
{
323 RXWBFLAG_OWN
= 0x8000,
324 RXWBFLAG_INT
= 0x4000,
325 RXWBFLAG_MF
= 0x2000,
326 RXWBFLAG_64BIT
= 0x2000,
327 RXWBFLAG_TCPON
= 0x1000,
328 RXWBFLAG_UDPON
= 0x0800,
329 RXWBFLAG_IPCS
= 0x0400,
330 RXWBFLAG_TCPCS
= 0x0200,
331 RXWBFLAG_UDPCS
= 0x0100,
332 RXWBFLAG_TAGON
= 0x0080,
333 RXWBFLAG_IPV4
= 0x0040,
334 RXWBFLAG_IPV6
= 0x0020,
335 RXWBFLAG_PAUSE
= 0x0010,
336 RXWBFLAG_MAGIC
= 0x0008,
337 RXWBFLAG_WAKEUP
= 0x0004,
338 RXWBFLAG_DEST
= 0x0003,
339 RXWBFLAG_DEST_UNI
= 0x0001,
340 RXWBFLAG_DEST_MUL
= 0x0002,
341 RXWBFLAG_DEST_BRO
= 0x0003,
344 enum jme_rxwbdesc_desccnt_mask
{
345 RXWBDCNT_WBCPL
= 0x80,
346 RXWBDCNT_DCNT
= 0x7F,
349 enum jme_rxwbdesc_errstat_bits
{
350 RXWBERR_LIMIT
= 0x80,
351 RXWBERR_MIIER
= 0x40,
352 RXWBERR_NIBON
= 0x20,
353 RXWBERR_COLON
= 0x10,
354 RXWBERR_ABORT
= 0x08,
355 RXWBERR_SHORT
= 0x04,
356 RXWBERR_OVERUN
= 0x02,
357 RXWBERR_CRCERR
= 0x01,
358 RXWBERR_ALLERR
= 0xFF,
362 * Buffer information corresponding to ring descriptors.
364 struct jme_buffer_info
{
369 unsigned long start_xmit
;
373 * The structure holding buffer information and ring descriptors all together.
376 void *alloc
; /* pointer to allocated memory */
377 void *desc
; /* pointer to ring memory */
378 dma_addr_t dmaalloc
; /* phys address of ring alloc */
379 dma_addr_t dma
; /* phys address for ring dma */
381 /* Buffer information corresponding to each descriptor */
382 struct jme_buffer_info
*bufinf
;
385 atomic_t next_to_clean
;
389 #define NET_STAT(priv) (priv->dev->stats)
390 #define NETDEV_GET_STATS(netdev, fun_ptr)
391 #define DECLARE_NET_DEVICE_STATS
393 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
394 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
395 netif_napi_add(dev, napis, pollfn, q);
396 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
397 #define JME_NAPI_WEIGHT(w) int w
398 #define JME_NAPI_WEIGHT_VAL(w) w
399 #define JME_NAPI_WEIGHT_SET(w, r)
400 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
401 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
402 #define JME_NAPI_DISABLE(priv) \
403 if (!napi_disable_pending(&priv->napi)) \
404 napi_disable(&priv->napi);
405 #define JME_RX_SCHEDULE_PREP(priv) \
406 napi_schedule_prep(&priv->napi)
407 #define JME_RX_SCHEDULE(priv) \
408 __napi_schedule(&priv->napi);
411 * Jmac Adapter Private data
413 #define SHADOW_REG_NR 8
415 struct pci_dev
*pdev
;
416 struct net_device
*dev
;
418 dma_addr_t shadow_dma
;
420 struct mii_if_info mii_if
;
421 struct jme_ring rxring
[RX_RING_NR
];
422 struct jme_ring txring
[TX_RING_NR
];
424 spinlock_t macaddr_lock
;
425 spinlock_t rxmcs_lock
;
426 struct tasklet_struct rxempty_task
;
427 struct tasklet_struct rxclean_task
;
428 struct tasklet_struct txclean_task
;
429 struct tasklet_struct linkch_task
;
430 struct tasklet_struct pcc_task
;
441 u32 tx_wake_threshold
;
445 unsigned int fpgaver
;
446 unsigned int chiprev
;
449 struct ethtool_cmd old_ecmd
;
450 unsigned int old_mtu
;
451 struct vlan_group
*vlgrp
;
452 struct dynpcc_info dpi
;
454 atomic_t link_changing
;
455 atomic_t tx_cleaning
;
456 atomic_t rx_cleaning
;
458 int (*jme_rx
)(struct sk_buff
*skb
);
459 int (*jme_vlan_rx
)(struct sk_buff
*skb
,
460 struct vlan_group
*grp
,
461 unsigned short vlan_tag
);
463 DECLARE_NET_DEVICE_STATS
466 enum shadow_reg_val
{
470 enum jme_flags_bits
{
476 JME_FLAG_SHUTDOWN
= 6,
479 #define TX_TIMEOUT (5 * HZ)
480 #define JME_REG_LEN 0x500
481 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
483 static inline struct jme_adapter
*
484 jme_napi_priv(struct napi_struct
*napi
)
486 struct jme_adapter
*jme
;
487 jme
= container_of(napi
, struct jme_adapter
, napi
);
494 enum jme_iomap_offsets
{
501 enum jme_iomap_lens
{
508 enum jme_iomap_regs
{
509 JME_TXCS
= JME_MAC
| 0x00, /* Transmit Control and Status */
510 JME_TXDBA_LO
= JME_MAC
| 0x04, /* Transmit Queue Desc Base Addr */
511 JME_TXDBA_HI
= JME_MAC
| 0x08, /* Transmit Queue Desc Base Addr */
512 JME_TXQDC
= JME_MAC
| 0x0C, /* Transmit Queue Desc Count */
513 JME_TXNDA
= JME_MAC
| 0x10, /* Transmit Queue Next Desc Addr */
514 JME_TXMCS
= JME_MAC
| 0x14, /* Transmit MAC Control Status */
515 JME_TXPFC
= JME_MAC
| 0x18, /* Transmit Pause Frame Control */
516 JME_TXTRHD
= JME_MAC
| 0x1C, /* Transmit Timer/Retry@Half-Dup */
518 JME_RXCS
= JME_MAC
| 0x20, /* Receive Control and Status */
519 JME_RXDBA_LO
= JME_MAC
| 0x24, /* Receive Queue Desc Base Addr */
520 JME_RXDBA_HI
= JME_MAC
| 0x28, /* Receive Queue Desc Base Addr */
521 JME_RXQDC
= JME_MAC
| 0x2C, /* Receive Queue Desc Count */
522 JME_RXNDA
= JME_MAC
| 0x30, /* Receive Queue Next Desc Addr */
523 JME_RXMCS
= JME_MAC
| 0x34, /* Receive MAC Control Status */
524 JME_RXUMA_LO
= JME_MAC
| 0x38, /* Receive Unicast MAC Address */
525 JME_RXUMA_HI
= JME_MAC
| 0x3C, /* Receive Unicast MAC Address */
526 JME_RXMCHT_LO
= JME_MAC
| 0x40, /* Recv Multicast Addr HashTable */
527 JME_RXMCHT_HI
= JME_MAC
| 0x44, /* Recv Multicast Addr HashTable */
528 JME_WFODP
= JME_MAC
| 0x48, /* Wakeup Frame Output Data Port */
529 JME_WFOI
= JME_MAC
| 0x4C, /* Wakeup Frame Output Interface */
531 JME_SMI
= JME_MAC
| 0x50, /* Station Management Interface */
532 JME_GHC
= JME_MAC
| 0x54, /* Global Host Control */
533 JME_PMCS
= JME_MAC
| 0x60, /* Power Management Control/Stat */
536 JME_PHY_CS
= JME_PHY
| 0x28, /* PHY Ctrl and Status Register */
537 JME_PHY_LINK
= JME_PHY
| 0x30, /* PHY Link Status Register */
538 JME_SMBCSR
= JME_PHY
| 0x40, /* SMB Control and Status */
539 JME_SMBINTF
= JME_PHY
| 0x44, /* SMB Interface */
542 JME_TMCSR
= JME_MISC
| 0x00, /* Timer Control/Status Register */
543 JME_GPREG0
= JME_MISC
| 0x08, /* General purpose REG-0 */
544 JME_GPREG1
= JME_MISC
| 0x0C, /* General purpose REG-1 */
545 JME_IEVE
= JME_MISC
| 0x20, /* Interrupt Event Status */
546 JME_IREQ
= JME_MISC
| 0x24, /* Intr Req Status(For Debug) */
547 JME_IENS
= JME_MISC
| 0x28, /* Intr Enable - Setting Port */
548 JME_IENC
= JME_MISC
| 0x2C, /* Interrupt Enable - Clear Port */
549 JME_PCCRX0
= JME_MISC
| 0x30, /* PCC Control for RX Queue 0 */
550 JME_PCCTX
= JME_MISC
| 0x40, /* PCC Control for TX Queues */
551 JME_CHIPMODE
= JME_MISC
| 0x44, /* Identify FPGA Version */
552 JME_SHBA_HI
= JME_MISC
| 0x48, /* Shadow Register Base HI */
553 JME_SHBA_LO
= JME_MISC
| 0x4C, /* Shadow Register Base LO */
554 JME_TIMER1
= JME_MISC
| 0x70, /* Timer1 */
555 JME_TIMER2
= JME_MISC
| 0x74, /* Timer2 */
556 JME_APMC
= JME_MISC
| 0x7C, /* Aggressive Power Mode Control */
557 JME_PCCSRX0
= JME_MISC
| 0x80, /* PCC Status of RX0 */
561 * TX Control/Status Bits
564 TXCS_QUEUE7S
= 0x00008000,
565 TXCS_QUEUE6S
= 0x00004000,
566 TXCS_QUEUE5S
= 0x00002000,
567 TXCS_QUEUE4S
= 0x00001000,
568 TXCS_QUEUE3S
= 0x00000800,
569 TXCS_QUEUE2S
= 0x00000400,
570 TXCS_QUEUE1S
= 0x00000200,
571 TXCS_QUEUE0S
= 0x00000100,
572 TXCS_FIFOTH
= 0x000000C0,
573 TXCS_DMASIZE
= 0x00000030,
574 TXCS_BURST
= 0x00000004,
575 TXCS_ENABLE
= 0x00000001,
578 enum jme_txcs_value
{
579 TXCS_FIFOTH_16QW
= 0x000000C0,
580 TXCS_FIFOTH_12QW
= 0x00000080,
581 TXCS_FIFOTH_8QW
= 0x00000040,
582 TXCS_FIFOTH_4QW
= 0x00000000,
584 TXCS_DMASIZE_64B
= 0x00000000,
585 TXCS_DMASIZE_128B
= 0x00000010,
586 TXCS_DMASIZE_256B
= 0x00000020,
587 TXCS_DMASIZE_512B
= 0x00000030,
589 TXCS_SELECT_QUEUE0
= 0x00000000,
590 TXCS_SELECT_QUEUE1
= 0x00010000,
591 TXCS_SELECT_QUEUE2
= 0x00020000,
592 TXCS_SELECT_QUEUE3
= 0x00030000,
593 TXCS_SELECT_QUEUE4
= 0x00040000,
594 TXCS_SELECT_QUEUE5
= 0x00050000,
595 TXCS_SELECT_QUEUE6
= 0x00060000,
596 TXCS_SELECT_QUEUE7
= 0x00070000,
598 TXCS_DEFAULT
= TXCS_FIFOTH_4QW
|
602 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
605 * TX MAC Control/Status Bits
607 enum jme_txmcs_bit_masks
{
608 TXMCS_IFG2
= 0xC0000000,
609 TXMCS_IFG1
= 0x30000000,
610 TXMCS_TTHOLD
= 0x00000300,
611 TXMCS_FBURST
= 0x00000080,
612 TXMCS_CARRIEREXT
= 0x00000040,
613 TXMCS_DEFER
= 0x00000020,
614 TXMCS_BACKOFF
= 0x00000010,
615 TXMCS_CARRIERSENSE
= 0x00000008,
616 TXMCS_COLLISION
= 0x00000004,
617 TXMCS_CRC
= 0x00000002,
618 TXMCS_PADDING
= 0x00000001,
621 enum jme_txmcs_values
{
622 TXMCS_IFG2_6_4
= 0x00000000,
623 TXMCS_IFG2_8_5
= 0x40000000,
624 TXMCS_IFG2_10_6
= 0x80000000,
625 TXMCS_IFG2_12_7
= 0xC0000000,
627 TXMCS_IFG1_8_4
= 0x00000000,
628 TXMCS_IFG1_12_6
= 0x10000000,
629 TXMCS_IFG1_16_8
= 0x20000000,
630 TXMCS_IFG1_20_10
= 0x30000000,
632 TXMCS_TTHOLD_1_8
= 0x00000000,
633 TXMCS_TTHOLD_1_4
= 0x00000100,
634 TXMCS_TTHOLD_1_2
= 0x00000200,
635 TXMCS_TTHOLD_FULL
= 0x00000300,
637 TXMCS_DEFAULT
= TXMCS_IFG2_8_5
|
645 enum jme_txpfc_bits_masks
{
646 TXPFC_VLAN_TAG
= 0xFFFF0000,
647 TXPFC_VLAN_EN
= 0x00008000,
648 TXPFC_PF_EN
= 0x00000001,
651 enum jme_txtrhd_bits_masks
{
652 TXTRHD_TXPEN
= 0x80000000,
653 TXTRHD_TXP
= 0x7FFFFF00,
654 TXTRHD_TXREN
= 0x00000080,
655 TXTRHD_TXRL
= 0x0000007F,
658 enum jme_txtrhd_shifts
{
659 TXTRHD_TXP_SHIFT
= 8,
660 TXTRHD_TXRL_SHIFT
= 0,
664 * RX Control/Status Bits
666 enum jme_rxcs_bit_masks
{
667 /* FIFO full threshold for transmitting Tx Pause Packet */
668 RXCS_FIFOTHTP
= 0x30000000,
669 /* FIFO threshold for processing next packet */
670 RXCS_FIFOTHNP
= 0x0C000000,
671 RXCS_DMAREQSZ
= 0x03000000, /* DMA Request Size */
672 RXCS_QUEUESEL
= 0x00030000, /* Queue selection */
673 RXCS_RETRYGAP
= 0x0000F000, /* RX Desc full retry gap */
674 RXCS_RETRYCNT
= 0x00000F00, /* RX Desc full retry counter */
675 RXCS_WAKEUP
= 0x00000040, /* Enable receive wakeup packet */
676 RXCS_MAGIC
= 0x00000020, /* Enable receive magic packet */
677 RXCS_SHORT
= 0x00000010, /* Enable receive short packet */
678 RXCS_ABORT
= 0x00000008, /* Enable receive errorr packet */
679 RXCS_QST
= 0x00000004, /* Receive queue start */
680 RXCS_SUSPEND
= 0x00000002,
681 RXCS_ENABLE
= 0x00000001,
684 enum jme_rxcs_values
{
685 RXCS_FIFOTHTP_16T
= 0x00000000,
686 RXCS_FIFOTHTP_32T
= 0x10000000,
687 RXCS_FIFOTHTP_64T
= 0x20000000,
688 RXCS_FIFOTHTP_128T
= 0x30000000,
690 RXCS_FIFOTHNP_16QW
= 0x00000000,
691 RXCS_FIFOTHNP_32QW
= 0x04000000,
692 RXCS_FIFOTHNP_64QW
= 0x08000000,
693 RXCS_FIFOTHNP_128QW
= 0x0C000000,
695 RXCS_DMAREQSZ_16B
= 0x00000000,
696 RXCS_DMAREQSZ_32B
= 0x01000000,
697 RXCS_DMAREQSZ_64B
= 0x02000000,
698 RXCS_DMAREQSZ_128B
= 0x03000000,
700 RXCS_QUEUESEL_Q0
= 0x00000000,
701 RXCS_QUEUESEL_Q1
= 0x00010000,
702 RXCS_QUEUESEL_Q2
= 0x00020000,
703 RXCS_QUEUESEL_Q3
= 0x00030000,
705 RXCS_RETRYGAP_256ns
= 0x00000000,
706 RXCS_RETRYGAP_512ns
= 0x00001000,
707 RXCS_RETRYGAP_1024ns
= 0x00002000,
708 RXCS_RETRYGAP_2048ns
= 0x00003000,
709 RXCS_RETRYGAP_4096ns
= 0x00004000,
710 RXCS_RETRYGAP_8192ns
= 0x00005000,
711 RXCS_RETRYGAP_16384ns
= 0x00006000,
712 RXCS_RETRYGAP_32768ns
= 0x00007000,
714 RXCS_RETRYCNT_0
= 0x00000000,
715 RXCS_RETRYCNT_4
= 0x00000100,
716 RXCS_RETRYCNT_8
= 0x00000200,
717 RXCS_RETRYCNT_12
= 0x00000300,
718 RXCS_RETRYCNT_16
= 0x00000400,
719 RXCS_RETRYCNT_20
= 0x00000500,
720 RXCS_RETRYCNT_24
= 0x00000600,
721 RXCS_RETRYCNT_28
= 0x00000700,
722 RXCS_RETRYCNT_32
= 0x00000800,
723 RXCS_RETRYCNT_36
= 0x00000900,
724 RXCS_RETRYCNT_40
= 0x00000A00,
725 RXCS_RETRYCNT_44
= 0x00000B00,
726 RXCS_RETRYCNT_48
= 0x00000C00,
727 RXCS_RETRYCNT_52
= 0x00000D00,
728 RXCS_RETRYCNT_56
= 0x00000E00,
729 RXCS_RETRYCNT_60
= 0x00000F00,
731 RXCS_DEFAULT
= RXCS_FIFOTHTP_128T
|
732 RXCS_FIFOTHNP_128QW
|
734 RXCS_RETRYGAP_256ns
|
738 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
741 * RX MAC Control/Status Bits
743 enum jme_rxmcs_bits
{
744 RXMCS_ALLFRAME
= 0x00000800,
745 RXMCS_BRDFRAME
= 0x00000400,
746 RXMCS_MULFRAME
= 0x00000200,
747 RXMCS_UNIFRAME
= 0x00000100,
748 RXMCS_ALLMULFRAME
= 0x00000080,
749 RXMCS_MULFILTERED
= 0x00000040,
750 RXMCS_RXCOLLDEC
= 0x00000020,
751 RXMCS_FLOWCTRL
= 0x00000008,
752 RXMCS_VTAGRM
= 0x00000004,
753 RXMCS_PREPAD
= 0x00000002,
754 RXMCS_CHECKSUM
= 0x00000001,
756 RXMCS_DEFAULT
= RXMCS_VTAGRM
|
763 * Wakeup Frame setup interface registers
765 #define WAKEUP_FRAME_NR 8
766 #define WAKEUP_FRAME_MASK_DWNR 4
768 enum jme_wfoi_bit_masks
{
769 WFOI_MASK_SEL
= 0x00000070,
770 WFOI_CRC_SEL
= 0x00000008,
771 WFOI_FRAME_SEL
= 0x00000007,
774 enum jme_wfoi_shifts
{
779 * SMI Related definitions
781 enum jme_smi_bit_mask
{
782 SMI_DATA_MASK
= 0xFFFF0000,
783 SMI_REG_ADDR_MASK
= 0x0000F800,
784 SMI_PHY_ADDR_MASK
= 0x000007C0,
785 SMI_OP_WRITE
= 0x00000020,
786 /* Set to 1, after req done it'll be cleared to 0 */
787 SMI_OP_REQ
= 0x00000010,
788 SMI_OP_MDIO
= 0x00000008, /* Software assess In/Out */
789 SMI_OP_MDOE
= 0x00000004, /* Software Output Enable */
790 SMI_OP_MDC
= 0x00000002, /* Software CLK Control */
791 SMI_OP_MDEN
= 0x00000001, /* Software access Enable */
794 enum jme_smi_bit_shift
{
796 SMI_REG_ADDR_SHIFT
= 11,
797 SMI_PHY_ADDR_SHIFT
= 6,
800 static inline u32
smi_reg_addr(int x
)
802 return (x
<< SMI_REG_ADDR_SHIFT
) & SMI_REG_ADDR_MASK
;
805 static inline u32
smi_phy_addr(int x
)
807 return (x
<< SMI_PHY_ADDR_SHIFT
) & SMI_PHY_ADDR_MASK
;
810 #define JME_PHY_TIMEOUT 100 /* 100 msec */
811 #define JME_PHY_REG_NR 32
814 * Global Host Control
816 enum jme_ghc_bit_mask
{
817 GHC_SWRST
= 0x40000000,
818 GHC_DPX
= 0x00000040,
819 GHC_SPEED
= 0x00000030,
820 GHC_LINK_POLL
= 0x00000001,
823 enum jme_ghc_speed_val
{
824 GHC_SPEED_10M
= 0x00000010,
825 GHC_SPEED_100M
= 0x00000020,
826 GHC_SPEED_1000M
= 0x00000030,
829 enum jme_ghc_to_clk
{
830 GHC_TO_CLK_OFF
= 0x00000000,
831 GHC_TO_CLK_GPHY
= 0x00400000,
832 GHC_TO_CLK_PCIE
= 0x00800000,
833 GHC_TO_CLK_INVALID
= 0x00C00000,
836 enum jme_ghc_txmac_clk
{
837 GHC_TXMAC_CLK_OFF
= 0x00000000,
838 GHC_TXMAC_CLK_GPHY
= 0x00100000,
839 GHC_TXMAC_CLK_PCIE
= 0x00200000,
840 GHC_TXMAC_CLK_INVALID
= 0x00300000,
844 * Power management control and status register
846 enum jme_pmcs_bit_masks
{
847 PMCS_WF7DET
= 0x80000000,
848 PMCS_WF6DET
= 0x40000000,
849 PMCS_WF5DET
= 0x20000000,
850 PMCS_WF4DET
= 0x10000000,
851 PMCS_WF3DET
= 0x08000000,
852 PMCS_WF2DET
= 0x04000000,
853 PMCS_WF1DET
= 0x02000000,
854 PMCS_WF0DET
= 0x01000000,
855 PMCS_LFDET
= 0x00040000,
856 PMCS_LRDET
= 0x00020000,
857 PMCS_MFDET
= 0x00010000,
858 PMCS_WF7EN
= 0x00008000,
859 PMCS_WF6EN
= 0x00004000,
860 PMCS_WF5EN
= 0x00002000,
861 PMCS_WF4EN
= 0x00001000,
862 PMCS_WF3EN
= 0x00000800,
863 PMCS_WF2EN
= 0x00000400,
864 PMCS_WF1EN
= 0x00000200,
865 PMCS_WF0EN
= 0x00000100,
866 PMCS_LFEN
= 0x00000004,
867 PMCS_LREN
= 0x00000002,
868 PMCS_MFEN
= 0x00000001,
872 * Giga PHY Status Registers
874 enum jme_phy_link_bit_mask
{
875 PHY_LINK_SPEED_MASK
= 0x0000C000,
876 PHY_LINK_DUPLEX
= 0x00002000,
877 PHY_LINK_SPEEDDPU_RESOLVED
= 0x00000800,
878 PHY_LINK_UP
= 0x00000400,
879 PHY_LINK_AUTONEG_COMPLETE
= 0x00000200,
880 PHY_LINK_MDI_STAT
= 0x00000040,
883 enum jme_phy_link_speed_val
{
884 PHY_LINK_SPEED_10M
= 0x00000000,
885 PHY_LINK_SPEED_100M
= 0x00004000,
886 PHY_LINK_SPEED_1000M
= 0x00008000,
889 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
892 * SMB Control and Status
894 enum jme_smbcsr_bit_mask
{
895 SMBCSR_CNACK
= 0x00020000,
896 SMBCSR_RELOAD
= 0x00010000,
897 SMBCSR_EEPROMD
= 0x00000020,
898 SMBCSR_INITDONE
= 0x00000010,
899 SMBCSR_BUSY
= 0x0000000F,
902 enum jme_smbintf_bit_mask
{
903 SMBINTF_HWDATR
= 0xFF000000,
904 SMBINTF_HWDATW
= 0x00FF0000,
905 SMBINTF_HWADDR
= 0x0000FF00,
906 SMBINTF_HWRWN
= 0x00000020,
907 SMBINTF_HWCMD
= 0x00000010,
908 SMBINTF_FASTM
= 0x00000008,
909 SMBINTF_GPIOSCL
= 0x00000004,
910 SMBINTF_GPIOSDA
= 0x00000002,
911 SMBINTF_GPIOEN
= 0x00000001,
914 enum jme_smbintf_vals
{
915 SMBINTF_HWRWN_READ
= 0x00000020,
916 SMBINTF_HWRWN_WRITE
= 0x00000000,
919 enum jme_smbintf_shifts
{
920 SMBINTF_HWDATR_SHIFT
= 24,
921 SMBINTF_HWDATW_SHIFT
= 16,
922 SMBINTF_HWADDR_SHIFT
= 8,
925 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
926 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
927 #define JME_SMB_LEN 256
928 #define JME_EEPROM_MAGIC 0x250
931 * Timer Control/Status Register
933 enum jme_tmcsr_bit_masks
{
934 TMCSR_SWIT
= 0x80000000,
935 TMCSR_EN
= 0x01000000,
936 TMCSR_CNT
= 0x00FFFFFF,
940 * General Purpose REG-0
942 enum jme_gpreg0_masks
{
943 GPREG0_DISSH
= 0xFF000000,
944 GPREG0_PCIRLMT
= 0x00300000,
945 GPREG0_PCCNOMUTCLR
= 0x00040000,
946 GPREG0_LNKINTPOLL
= 0x00001000,
947 GPREG0_PCCTMR
= 0x00000300,
948 GPREG0_PHYADDR
= 0x0000001F,
951 enum jme_gpreg0_vals
{
952 GPREG0_DISSH_DW7
= 0x80000000,
953 GPREG0_DISSH_DW6
= 0x40000000,
954 GPREG0_DISSH_DW5
= 0x20000000,
955 GPREG0_DISSH_DW4
= 0x10000000,
956 GPREG0_DISSH_DW3
= 0x08000000,
957 GPREG0_DISSH_DW2
= 0x04000000,
958 GPREG0_DISSH_DW1
= 0x02000000,
959 GPREG0_DISSH_DW0
= 0x01000000,
960 GPREG0_DISSH_ALL
= 0xFF000000,
962 GPREG0_PCIRLMT_8
= 0x00000000,
963 GPREG0_PCIRLMT_6
= 0x00100000,
964 GPREG0_PCIRLMT_5
= 0x00200000,
965 GPREG0_PCIRLMT_4
= 0x00300000,
967 GPREG0_PCCTMR_16ns
= 0x00000000,
968 GPREG0_PCCTMR_256ns
= 0x00000100,
969 GPREG0_PCCTMR_1us
= 0x00000200,
970 GPREG0_PCCTMR_1ms
= 0x00000300,
972 GPREG0_PHYADDR_1
= 0x00000001,
974 GPREG0_DEFAULT
= GPREG0_PCIRLMT_4
|
980 * General Purpose REG-1
981 * Note: All theses bits defined here are for
982 * Chip mode revision 0x11 only
984 enum jme_gpreg1_masks
{
985 GPREG1_INTRDELAYUNIT
= 0x00000018,
986 GPREG1_INTRDELAYENABLE
= 0x00000007,
989 enum jme_gpreg1_vals
{
990 GPREG1_RSSPATCH
= 0x00000040,
991 GPREG1_HALFMODEPATCH
= 0x00000020,
993 GPREG1_INTDLYUNIT_16NS
= 0x00000000,
994 GPREG1_INTDLYUNIT_256NS
= 0x00000008,
995 GPREG1_INTDLYUNIT_1US
= 0x00000010,
996 GPREG1_INTDLYUNIT_16US
= 0x00000018,
998 GPREG1_INTDLYEN_1U
= 0x00000001,
999 GPREG1_INTDLYEN_2U
= 0x00000002,
1000 GPREG1_INTDLYEN_3U
= 0x00000003,
1001 GPREG1_INTDLYEN_4U
= 0x00000004,
1002 GPREG1_INTDLYEN_5U
= 0x00000005,
1003 GPREG1_INTDLYEN_6U
= 0x00000006,
1004 GPREG1_INTDLYEN_7U
= 0x00000007,
1006 GPREG1_DEFAULT
= 0x00000000,
1010 * Interrupt Status Bits
1012 enum jme_interrupt_bits
{
1013 INTR_SWINTR
= 0x80000000,
1014 INTR_TMINTR
= 0x40000000,
1015 INTR_LINKCH
= 0x20000000,
1016 INTR_PAUSERCV
= 0x10000000,
1017 INTR_MAGICRCV
= 0x08000000,
1018 INTR_WAKERCV
= 0x04000000,
1019 INTR_PCCRX0TO
= 0x02000000,
1020 INTR_PCCRX1TO
= 0x01000000,
1021 INTR_PCCRX2TO
= 0x00800000,
1022 INTR_PCCRX3TO
= 0x00400000,
1023 INTR_PCCTXTO
= 0x00200000,
1024 INTR_PCCRX0
= 0x00100000,
1025 INTR_PCCRX1
= 0x00080000,
1026 INTR_PCCRX2
= 0x00040000,
1027 INTR_PCCRX3
= 0x00020000,
1028 INTR_PCCTX
= 0x00010000,
1029 INTR_RX3EMP
= 0x00008000,
1030 INTR_RX2EMP
= 0x00004000,
1031 INTR_RX1EMP
= 0x00002000,
1032 INTR_RX0EMP
= 0x00001000,
1033 INTR_RX3
= 0x00000800,
1034 INTR_RX2
= 0x00000400,
1035 INTR_RX1
= 0x00000200,
1036 INTR_RX0
= 0x00000100,
1037 INTR_TX7
= 0x00000080,
1038 INTR_TX6
= 0x00000040,
1039 INTR_TX5
= 0x00000020,
1040 INTR_TX4
= 0x00000010,
1041 INTR_TX3
= 0x00000008,
1042 INTR_TX2
= 0x00000004,
1043 INTR_TX1
= 0x00000002,
1044 INTR_TX0
= 0x00000001,
1047 static const u32 INTR_ENABLE
= INTR_SWINTR
|
1057 * PCC Control Registers
1059 enum jme_pccrx_masks
{
1060 PCCRXTO_MASK
= 0xFFFF0000,
1061 PCCRX_MASK
= 0x0000FF00,
1064 enum jme_pcctx_masks
{
1065 PCCTXTO_MASK
= 0xFFFF0000,
1066 PCCTX_MASK
= 0x0000FF00,
1067 PCCTX_QS_MASK
= 0x000000FF,
1070 enum jme_pccrx_shifts
{
1075 enum jme_pcctx_shifts
{
1080 enum jme_pcctx_bits
{
1081 PCCTXQ0_EN
= 0x00000001,
1082 PCCTXQ1_EN
= 0x00000002,
1083 PCCTXQ2_EN
= 0x00000004,
1084 PCCTXQ3_EN
= 0x00000008,
1085 PCCTXQ4_EN
= 0x00000010,
1086 PCCTXQ5_EN
= 0x00000020,
1087 PCCTXQ6_EN
= 0x00000040,
1088 PCCTXQ7_EN
= 0x00000080,
1092 * Chip Mode Register
1094 enum jme_chipmode_bit_masks
{
1095 CM_FPGAVER_MASK
= 0xFFFF0000,
1096 CM_CHIPREV_MASK
= 0x0000FF00,
1097 CM_CHIPMODE_MASK
= 0x0000000F,
1100 enum jme_chipmode_shifts
{
1101 CM_FPGAVER_SHIFT
= 16,
1102 CM_CHIPREV_SHIFT
= 8,
1106 * Shadow base address register bits
1108 enum jme_shadow_base_address_bits
{
1113 * Aggressive Power Mode Control
1115 enum jme_apmc_bits
{
1116 JME_APMC_PCIE_SD_EN
= 0x40000000,
1117 JME_APMC_PSEUDO_HP_EN
= 0x20000000,
1118 JME_APMC_EPIEN
= 0x04000000,
1119 JME_APMC_EPIEN_CTRL
= 0x03000000,
1122 enum jme_apmc_values
{
1123 JME_APMC_EPIEN_CTRL_EN
= 0x02000000,
1124 JME_APMC_EPIEN_CTRL_DIS
= 0x01000000,
1127 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1130 static char *MAC_REG_NAME
[] = {
1131 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1132 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1133 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1134 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1135 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1136 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1139 static char *PE_REG_NAME
[] = {
1140 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1141 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1142 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1143 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1144 "JME_SMBCSR", "JME_SMBINTF"};
1146 static char *MISC_REG_NAME
[] = {
1147 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1148 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1149 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1150 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1151 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1152 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1153 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1154 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1157 static inline void reg_dbg(const struct jme_adapter
*jme
,
1158 const char *msg
, u32 val
, u32 reg
)
1160 const char *regname
;
1161 switch (reg
& 0xF00) {
1163 regname
= MAC_REG_NAME
[(reg
& 0xFF) >> 2];
1166 regname
= PE_REG_NAME
[(reg
& 0xFF) >> 2];
1169 regname
= MISC_REG_NAME
[(reg
& 0xFF) >> 2];
1172 regname
= PE_REG_NAME
[0];
1174 printk(KERN_DEBUG
"%s: %-20s %08x@%s\n", jme
->dev
->name
,
1178 static inline void reg_dbg(const struct jme_adapter
*jme
,
1179 const char *msg
, u32 val
, u32 reg
) {}
1183 * Read/Write MMaped I/O Registers
1185 static inline u32
jread32(struct jme_adapter
*jme
, u32 reg
)
1187 return readl(jme
->regs
+ reg
);
1190 static inline void jwrite32(struct jme_adapter
*jme
, u32 reg
, u32 val
)
1192 reg_dbg(jme
, "REG WRITE", val
, reg
);
1193 writel(val
, jme
->regs
+ reg
);
1194 reg_dbg(jme
, "VAL AFTER WRITE", readl(jme
->regs
+ reg
), reg
);
1197 static inline void jwrite32f(struct jme_adapter
*jme
, u32 reg
, u32 val
)
1200 * Read after write should cause flush
1202 reg_dbg(jme
, "REG WRITE FLUSH", val
, reg
);
1203 writel(val
, jme
->regs
+ reg
);
1204 readl(jme
->regs
+ reg
);
1205 reg_dbg(jme
, "VAL AFTER WRITE", readl(jme
->regs
+ reg
), reg
);
1211 enum jme_phy_reg17_bit_masks
{
1212 PREG17_SPEED
= 0xC000,
1213 PREG17_DUPLEX
= 0x2000,
1214 PREG17_SPDRSV
= 0x0800,
1215 PREG17_LNKUP
= 0x0400,
1216 PREG17_MDI
= 0x0040,
1219 enum jme_phy_reg17_vals
{
1220 PREG17_SPEED_10M
= 0x0000,
1221 PREG17_SPEED_100M
= 0x4000,
1222 PREG17_SPEED_1000M
= 0x8000,
1225 #define BMSR_ANCOMP 0x0020
1230 static inline int is_buggy250(unsigned short device
, unsigned int chiprev
)
1232 return device
== PCI_DEVICE_ID_JMICRON_JMC250
&& chiprev
== 0x11;
1236 * Function prototypes
1238 static int jme_set_settings(struct net_device
*netdev
,
1239 struct ethtool_cmd
*ecmd
);
1240 static void jme_set_multi(struct net_device
*netdev
);