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ixgbe: add support for 82599 based Express Module X520-P2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <scsi/fc/fc_fcoe.h>
44
45 #include "ixgbe.h"
46 #include "ixgbe_common.h"
47
48 char ixgbe_driver_name[] = "ixgbe";
49 static const char ixgbe_driver_string[] =
50 "Intel(R) 10 Gigabit PCI Express Network Driver";
51
52 #define DRV_VERSION "2.0.44-k2"
53 const char ixgbe_driver_version[] = DRV_VERSION;
54 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
55
56 static const struct ixgbe_info *ixgbe_info_tbl[] = {
57 [board_82598] = &ixgbe_82598_info,
58 [board_82599] = &ixgbe_82599_info,
59 };
60
61 /* ixgbe_pci_tbl - PCI Device ID Table
62 *
63 * Wildcard entries (PCI_ANY_ID) should come last
64 * Last entry must be all 0s
65 *
66 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67 * Class, Class Mask, private data (not used) }
68 */
69 static struct pci_device_id ixgbe_pci_tbl[] = {
70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
71 board_82598 },
72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
73 board_82598 },
74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
75 board_82598 },
76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
77 board_82598 },
78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
79 board_82598 },
80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
83 board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
85 board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
87 board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
89 board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
91 board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
93 board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
95 board_82599 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
97 board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
99 board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
101 board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
103 board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
105 board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
107 board_82599 },
108
109 /* required last entry */
110 {0, }
111 };
112 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
113
114 #ifdef CONFIG_IXGBE_DCA
115 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
116 void *p);
117 static struct notifier_block dca_notifier = {
118 .notifier_call = ixgbe_notify_dca,
119 .next = NULL,
120 .priority = 0
121 };
122 #endif
123
124 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
125 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
126 MODULE_LICENSE("GPL");
127 MODULE_VERSION(DRV_VERSION);
128
129 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
130
131 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
132 {
133 u32 ctrl_ext;
134
135 /* Let firmware take over control of h/w */
136 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
137 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
138 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
139 }
140
141 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
142 {
143 u32 ctrl_ext;
144
145 /* Let firmware know the driver has taken over */
146 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
147 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
148 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
149 }
150
151 /*
152 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
153 * @adapter: pointer to adapter struct
154 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
155 * @queue: queue to map the corresponding interrupt to
156 * @msix_vector: the vector to map to the corresponding queue
157 *
158 */
159 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
160 u8 queue, u8 msix_vector)
161 {
162 u32 ivar, index;
163 struct ixgbe_hw *hw = &adapter->hw;
164 switch (hw->mac.type) {
165 case ixgbe_mac_82598EB:
166 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
167 if (direction == -1)
168 direction = 0;
169 index = (((direction * 64) + queue) >> 2) & 0x1F;
170 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
171 ivar &= ~(0xFF << (8 * (queue & 0x3)));
172 ivar |= (msix_vector << (8 * (queue & 0x3)));
173 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
174 break;
175 case ixgbe_mac_82599EB:
176 if (direction == -1) {
177 /* other causes */
178 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
179 index = ((queue & 1) * 8);
180 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
181 ivar &= ~(0xFF << index);
182 ivar |= (msix_vector << index);
183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
184 break;
185 } else {
186 /* tx or rx causes */
187 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
188 index = ((16 * (queue & 1)) + (8 * direction));
189 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
190 ivar &= ~(0xFF << index);
191 ivar |= (msix_vector << index);
192 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
193 break;
194 }
195 default:
196 break;
197 }
198 }
199
200 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
201 u64 qmask)
202 {
203 u32 mask;
204
205 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
206 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
207 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
208 } else {
209 mask = (qmask & 0xFFFFFFFF);
210 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
211 mask = (qmask >> 32);
212 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
213 }
214 }
215
216 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
217 struct ixgbe_tx_buffer
218 *tx_buffer_info)
219 {
220 tx_buffer_info->dma = 0;
221 if (tx_buffer_info->skb) {
222 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
223 DMA_TO_DEVICE);
224 dev_kfree_skb_any(tx_buffer_info->skb);
225 tx_buffer_info->skb = NULL;
226 }
227 tx_buffer_info->time_stamp = 0;
228 /* tx_buffer_info must be completely set up in the transmit path */
229 }
230
231 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
232 struct ixgbe_ring *tx_ring,
233 unsigned int eop)
234 {
235 struct ixgbe_hw *hw = &adapter->hw;
236
237 /* Detect a transmit hang in hardware, this serializes the
238 * check with the clearing of time_stamp and movement of eop */
239 adapter->detect_tx_hung = false;
240 if (tx_ring->tx_buffer_info[eop].time_stamp &&
241 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
242 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
243 /* detected Tx unit hang */
244 union ixgbe_adv_tx_desc *tx_desc;
245 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
246 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
247 " Tx Queue <%d>\n"
248 " TDH, TDT <%x>, <%x>\n"
249 " next_to_use <%x>\n"
250 " next_to_clean <%x>\n"
251 "tx_buffer_info[next_to_clean]\n"
252 " time_stamp <%lx>\n"
253 " jiffies <%lx>\n",
254 tx_ring->queue_index,
255 IXGBE_READ_REG(hw, tx_ring->head),
256 IXGBE_READ_REG(hw, tx_ring->tail),
257 tx_ring->next_to_use, eop,
258 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
259 return true;
260 }
261
262 return false;
263 }
264
265 #define IXGBE_MAX_TXD_PWR 14
266 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
267
268 /* Tx Descriptors needed, worst case */
269 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
270 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
271 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
272 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
273
274 static void ixgbe_tx_timeout(struct net_device *netdev);
275
276 /**
277 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
278 * @q_vector: structure containing interrupt and ring information
279 * @tx_ring: tx ring to clean
280 **/
281 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
282 struct ixgbe_ring *tx_ring)
283 {
284 struct ixgbe_adapter *adapter = q_vector->adapter;
285 struct net_device *netdev = adapter->netdev;
286 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
287 struct ixgbe_tx_buffer *tx_buffer_info;
288 unsigned int i, eop, count = 0;
289 unsigned int total_bytes = 0, total_packets = 0;
290
291 i = tx_ring->next_to_clean;
292 eop = tx_ring->tx_buffer_info[i].next_to_watch;
293 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
294
295 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
296 (count < tx_ring->work_limit)) {
297 bool cleaned = false;
298 for ( ; !cleaned; count++) {
299 struct sk_buff *skb;
300 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
301 tx_buffer_info = &tx_ring->tx_buffer_info[i];
302 cleaned = (i == eop);
303 skb = tx_buffer_info->skb;
304
305 if (cleaned && skb) {
306 unsigned int segs, bytecount;
307 unsigned int hlen = skb_headlen(skb);
308
309 /* gso_segs is currently only valid for tcp */
310 segs = skb_shinfo(skb)->gso_segs ?: 1;
311 #ifdef IXGBE_FCOE
312 /* adjust for FCoE Sequence Offload */
313 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
314 && (skb->protocol == htons(ETH_P_FCOE)) &&
315 skb_is_gso(skb)) {
316 hlen = skb_transport_offset(skb) +
317 sizeof(struct fc_frame_header) +
318 sizeof(struct fcoe_crc_eof);
319 segs = DIV_ROUND_UP(skb->len - hlen,
320 skb_shinfo(skb)->gso_size);
321 }
322 #endif /* IXGBE_FCOE */
323 /* multiply data chunks by size of headers */
324 bytecount = ((segs - 1) * hlen) + skb->len;
325 total_packets += segs;
326 total_bytes += bytecount;
327 }
328
329 ixgbe_unmap_and_free_tx_resource(adapter,
330 tx_buffer_info);
331
332 tx_desc->wb.status = 0;
333
334 i++;
335 if (i == tx_ring->count)
336 i = 0;
337 }
338
339 eop = tx_ring->tx_buffer_info[i].next_to_watch;
340 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
341 }
342
343 tx_ring->next_to_clean = i;
344
345 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
346 if (unlikely(count && netif_carrier_ok(netdev) &&
347 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
348 /* Make sure that anybody stopping the queue after this
349 * sees the new next_to_clean.
350 */
351 smp_mb();
352 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
353 !test_bit(__IXGBE_DOWN, &adapter->state)) {
354 netif_wake_subqueue(netdev, tx_ring->queue_index);
355 ++adapter->restart_queue;
356 }
357 }
358
359 if (adapter->detect_tx_hung) {
360 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
361 /* schedule immediate reset if we believe we hung */
362 DPRINTK(PROBE, INFO,
363 "tx hang %d detected, resetting adapter\n",
364 adapter->tx_timeout_count + 1);
365 ixgbe_tx_timeout(adapter->netdev);
366 }
367 }
368
369 /* re-arm the interrupt */
370 if (count >= tx_ring->work_limit)
371 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
372
373 tx_ring->total_bytes += total_bytes;
374 tx_ring->total_packets += total_packets;
375 tx_ring->stats.packets += total_packets;
376 tx_ring->stats.bytes += total_bytes;
377 netdev->stats.tx_bytes += total_bytes;
378 netdev->stats.tx_packets += total_packets;
379 return (count < tx_ring->work_limit);
380 }
381
382 #ifdef CONFIG_IXGBE_DCA
383 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
384 struct ixgbe_ring *rx_ring)
385 {
386 u32 rxctrl;
387 int cpu = get_cpu();
388 int q = rx_ring - adapter->rx_ring;
389
390 if (rx_ring->cpu != cpu) {
391 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
392 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
393 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
394 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
395 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
396 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
397 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
398 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
399 }
400 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
401 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
402 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
403 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
404 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
405 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
406 rx_ring->cpu = cpu;
407 }
408 put_cpu();
409 }
410
411 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
412 struct ixgbe_ring *tx_ring)
413 {
414 u32 txctrl;
415 int cpu = get_cpu();
416 int q = tx_ring - adapter->tx_ring;
417
418 if (tx_ring->cpu != cpu) {
419 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
420 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
421 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
422 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
423 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
424 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
425 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
426 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
427 }
428 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
429 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
430 tx_ring->cpu = cpu;
431 }
432 put_cpu();
433 }
434
435 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
436 {
437 int i;
438
439 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
440 return;
441
442 /* always use CB2 mode, difference is masked in the CB driver */
443 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
444
445 for (i = 0; i < adapter->num_tx_queues; i++) {
446 adapter->tx_ring[i].cpu = -1;
447 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
448 }
449 for (i = 0; i < adapter->num_rx_queues; i++) {
450 adapter->rx_ring[i].cpu = -1;
451 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
452 }
453 }
454
455 static int __ixgbe_notify_dca(struct device *dev, void *data)
456 {
457 struct net_device *netdev = dev_get_drvdata(dev);
458 struct ixgbe_adapter *adapter = netdev_priv(netdev);
459 unsigned long event = *(unsigned long *)data;
460
461 switch (event) {
462 case DCA_PROVIDER_ADD:
463 /* if we're already enabled, don't do it again */
464 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
465 break;
466 if (dca_add_requester(dev) == 0) {
467 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
468 ixgbe_setup_dca(adapter);
469 break;
470 }
471 /* Fall Through since DCA is disabled. */
472 case DCA_PROVIDER_REMOVE:
473 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
474 dca_remove_requester(dev);
475 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
476 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
477 }
478 break;
479 }
480
481 return 0;
482 }
483
484 #endif /* CONFIG_IXGBE_DCA */
485 /**
486 * ixgbe_receive_skb - Send a completed packet up the stack
487 * @adapter: board private structure
488 * @skb: packet to send up
489 * @status: hardware indication of status of receive
490 * @rx_ring: rx descriptor ring (for a specific queue) to setup
491 * @rx_desc: rx descriptor
492 **/
493 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
494 struct sk_buff *skb, u8 status,
495 struct ixgbe_ring *ring,
496 union ixgbe_adv_rx_desc *rx_desc)
497 {
498 struct ixgbe_adapter *adapter = q_vector->adapter;
499 struct napi_struct *napi = &q_vector->napi;
500 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
501 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
502
503 skb_record_rx_queue(skb, ring->queue_index);
504 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
505 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
506 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
507 else
508 napi_gro_receive(napi, skb);
509 } else {
510 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
511 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
512 else
513 netif_rx(skb);
514 }
515 }
516
517 /**
518 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
519 * @adapter: address of board private structure
520 * @status_err: hardware indication of status of receive
521 * @skb: skb currently being received and modified
522 **/
523 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
524 union ixgbe_adv_rx_desc *rx_desc,
525 struct sk_buff *skb)
526 {
527 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
528
529 skb->ip_summed = CHECKSUM_NONE;
530
531 /* Rx csum disabled */
532 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
533 return;
534
535 /* if IP and error */
536 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
537 (status_err & IXGBE_RXDADV_ERR_IPE)) {
538 adapter->hw_csum_rx_error++;
539 return;
540 }
541
542 if (!(status_err & IXGBE_RXD_STAT_L4CS))
543 return;
544
545 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
546 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
547
548 /*
549 * 82599 errata, UDP frames with a 0 checksum can be marked as
550 * checksum errors.
551 */
552 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
553 (adapter->hw.mac.type == ixgbe_mac_82599EB))
554 return;
555
556 adapter->hw_csum_rx_error++;
557 return;
558 }
559
560 /* It must be a TCP or UDP packet with a valid checksum */
561 skb->ip_summed = CHECKSUM_UNNECESSARY;
562 adapter->hw_csum_rx_good++;
563 }
564
565 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
566 struct ixgbe_ring *rx_ring, u32 val)
567 {
568 /*
569 * Force memory writes to complete before letting h/w
570 * know there are new descriptors to fetch. (Only
571 * applicable for weak-ordered memory model archs,
572 * such as IA-64).
573 */
574 wmb();
575 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
576 }
577
578 /**
579 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
580 * @adapter: address of board private structure
581 **/
582 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
583 struct ixgbe_ring *rx_ring,
584 int cleaned_count)
585 {
586 struct pci_dev *pdev = adapter->pdev;
587 union ixgbe_adv_rx_desc *rx_desc;
588 struct ixgbe_rx_buffer *bi;
589 unsigned int i;
590
591 i = rx_ring->next_to_use;
592 bi = &rx_ring->rx_buffer_info[i];
593
594 while (cleaned_count--) {
595 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
596
597 if (!bi->page_dma &&
598 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
599 if (!bi->page) {
600 bi->page = alloc_page(GFP_ATOMIC);
601 if (!bi->page) {
602 adapter->alloc_rx_page_failed++;
603 goto no_buffers;
604 }
605 bi->page_offset = 0;
606 } else {
607 /* use a half page if we're re-using */
608 bi->page_offset ^= (PAGE_SIZE / 2);
609 }
610
611 bi->page_dma = pci_map_page(pdev, bi->page,
612 bi->page_offset,
613 (PAGE_SIZE / 2),
614 PCI_DMA_FROMDEVICE);
615 }
616
617 if (!bi->skb) {
618 struct sk_buff *skb;
619 skb = netdev_alloc_skb(adapter->netdev,
620 (rx_ring->rx_buf_len +
621 NET_IP_ALIGN));
622
623 if (!skb) {
624 adapter->alloc_rx_buff_failed++;
625 goto no_buffers;
626 }
627
628 /*
629 * Make buffer alignment 2 beyond a 16 byte boundary
630 * this will result in a 16 byte aligned IP header after
631 * the 14 byte MAC header is removed
632 */
633 skb_reserve(skb, NET_IP_ALIGN);
634
635 bi->skb = skb;
636 bi->dma = pci_map_single(pdev, skb->data,
637 rx_ring->rx_buf_len,
638 PCI_DMA_FROMDEVICE);
639 }
640 /* Refresh the desc even if buffer_addrs didn't change because
641 * each write-back erases this info. */
642 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
643 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
644 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
645 } else {
646 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
647 }
648
649 i++;
650 if (i == rx_ring->count)
651 i = 0;
652 bi = &rx_ring->rx_buffer_info[i];
653 }
654
655 no_buffers:
656 if (rx_ring->next_to_use != i) {
657 rx_ring->next_to_use = i;
658 if (i-- == 0)
659 i = (rx_ring->count - 1);
660
661 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
662 }
663 }
664
665 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
666 {
667 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
668 }
669
670 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
671 {
672 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
673 }
674
675 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
676 {
677 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
678 IXGBE_RXDADV_RSCCNT_MASK) >>
679 IXGBE_RXDADV_RSCCNT_SHIFT;
680 }
681
682 /**
683 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
684 * @skb: pointer to the last skb in the rsc queue
685 *
686 * This function changes a queue full of hw rsc buffers into a completed
687 * packet. It uses the ->prev pointers to find the first packet and then
688 * turns it into the frag list owner.
689 **/
690 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
691 {
692 unsigned int frag_list_size = 0;
693
694 while (skb->prev) {
695 struct sk_buff *prev = skb->prev;
696 frag_list_size += skb->len;
697 skb->prev = NULL;
698 skb = prev;
699 }
700
701 skb_shinfo(skb)->frag_list = skb->next;
702 skb->next = NULL;
703 skb->len += frag_list_size;
704 skb->data_len += frag_list_size;
705 skb->truesize += frag_list_size;
706 return skb;
707 }
708
709 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
710 struct ixgbe_ring *rx_ring,
711 int *work_done, int work_to_do)
712 {
713 struct ixgbe_adapter *adapter = q_vector->adapter;
714 struct net_device *netdev = adapter->netdev;
715 struct pci_dev *pdev = adapter->pdev;
716 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
717 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
718 struct sk_buff *skb;
719 unsigned int i, rsc_count = 0;
720 u32 len, staterr;
721 u16 hdr_info;
722 bool cleaned = false;
723 int cleaned_count = 0;
724 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
725 #ifdef IXGBE_FCOE
726 int ddp_bytes = 0;
727 #endif /* IXGBE_FCOE */
728
729 i = rx_ring->next_to_clean;
730 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
731 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
732 rx_buffer_info = &rx_ring->rx_buffer_info[i];
733
734 while (staterr & IXGBE_RXD_STAT_DD) {
735 u32 upper_len = 0;
736 if (*work_done >= work_to_do)
737 break;
738 (*work_done)++;
739
740 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
741 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
742 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
743 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
744 if (hdr_info & IXGBE_RXDADV_SPH)
745 adapter->rx_hdr_split++;
746 if (len > IXGBE_RX_HDR_SIZE)
747 len = IXGBE_RX_HDR_SIZE;
748 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
749 } else {
750 len = le16_to_cpu(rx_desc->wb.upper.length);
751 }
752
753 cleaned = true;
754 skb = rx_buffer_info->skb;
755 prefetch(skb->data - NET_IP_ALIGN);
756 rx_buffer_info->skb = NULL;
757
758 if (rx_buffer_info->dma) {
759 pci_unmap_single(pdev, rx_buffer_info->dma,
760 rx_ring->rx_buf_len,
761 PCI_DMA_FROMDEVICE);
762 rx_buffer_info->dma = 0;
763 skb_put(skb, len);
764 }
765
766 if (upper_len) {
767 pci_unmap_page(pdev, rx_buffer_info->page_dma,
768 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
769 rx_buffer_info->page_dma = 0;
770 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
771 rx_buffer_info->page,
772 rx_buffer_info->page_offset,
773 upper_len);
774
775 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
776 (page_count(rx_buffer_info->page) != 1))
777 rx_buffer_info->page = NULL;
778 else
779 get_page(rx_buffer_info->page);
780
781 skb->len += upper_len;
782 skb->data_len += upper_len;
783 skb->truesize += upper_len;
784 }
785
786 i++;
787 if (i == rx_ring->count)
788 i = 0;
789
790 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
791 prefetch(next_rxd);
792 cleaned_count++;
793
794 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
795 rsc_count = ixgbe_get_rsc_count(rx_desc);
796
797 if (rsc_count) {
798 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
799 IXGBE_RXDADV_NEXTP_SHIFT;
800 next_buffer = &rx_ring->rx_buffer_info[nextp];
801 rx_ring->rsc_count += (rsc_count - 1);
802 } else {
803 next_buffer = &rx_ring->rx_buffer_info[i];
804 }
805
806 if (staterr & IXGBE_RXD_STAT_EOP) {
807 if (skb->prev)
808 skb = ixgbe_transform_rsc_queue(skb);
809 rx_ring->stats.packets++;
810 rx_ring->stats.bytes += skb->len;
811 } else {
812 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
813 rx_buffer_info->skb = next_buffer->skb;
814 rx_buffer_info->dma = next_buffer->dma;
815 next_buffer->skb = skb;
816 next_buffer->dma = 0;
817 } else {
818 skb->next = next_buffer->skb;
819 skb->next->prev = skb;
820 }
821 adapter->non_eop_descs++;
822 goto next_desc;
823 }
824
825 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
826 dev_kfree_skb_irq(skb);
827 goto next_desc;
828 }
829
830 ixgbe_rx_checksum(adapter, rx_desc, skb);
831
832 /* probably a little skewed due to removing CRC */
833 total_rx_bytes += skb->len;
834 total_rx_packets++;
835
836 skb->protocol = eth_type_trans(skb, adapter->netdev);
837 #ifdef IXGBE_FCOE
838 /* if ddp, not passing to ULD unless for FCP_RSP or error */
839 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
840 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
841 if (!ddp_bytes)
842 goto next_desc;
843 }
844 #endif /* IXGBE_FCOE */
845 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
846
847 next_desc:
848 rx_desc->wb.upper.status_error = 0;
849
850 /* return some buffers to hardware, one at a time is too slow */
851 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
852 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
853 cleaned_count = 0;
854 }
855
856 /* use prefetched values */
857 rx_desc = next_rxd;
858 rx_buffer_info = &rx_ring->rx_buffer_info[i];
859
860 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
861 }
862
863 rx_ring->next_to_clean = i;
864 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
865
866 if (cleaned_count)
867 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
868
869 #ifdef IXGBE_FCOE
870 /* include DDPed FCoE data */
871 if (ddp_bytes > 0) {
872 unsigned int mss;
873
874 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
875 sizeof(struct fc_frame_header) -
876 sizeof(struct fcoe_crc_eof);
877 if (mss > 512)
878 mss &= ~511;
879 total_rx_bytes += ddp_bytes;
880 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
881 }
882 #endif /* IXGBE_FCOE */
883
884 rx_ring->total_packets += total_rx_packets;
885 rx_ring->total_bytes += total_rx_bytes;
886 netdev->stats.rx_bytes += total_rx_bytes;
887 netdev->stats.rx_packets += total_rx_packets;
888
889 return cleaned;
890 }
891
892 static int ixgbe_clean_rxonly(struct napi_struct *, int);
893 /**
894 * ixgbe_configure_msix - Configure MSI-X hardware
895 * @adapter: board private structure
896 *
897 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
898 * interrupts.
899 **/
900 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
901 {
902 struct ixgbe_q_vector *q_vector;
903 int i, j, q_vectors, v_idx, r_idx;
904 u32 mask;
905
906 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
907
908 /*
909 * Populate the IVAR table and set the ITR values to the
910 * corresponding register.
911 */
912 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
913 q_vector = adapter->q_vector[v_idx];
914 /* XXX for_each_bit(...) */
915 r_idx = find_first_bit(q_vector->rxr_idx,
916 adapter->num_rx_queues);
917
918 for (i = 0; i < q_vector->rxr_count; i++) {
919 j = adapter->rx_ring[r_idx].reg_idx;
920 ixgbe_set_ivar(adapter, 0, j, v_idx);
921 r_idx = find_next_bit(q_vector->rxr_idx,
922 adapter->num_rx_queues,
923 r_idx + 1);
924 }
925 r_idx = find_first_bit(q_vector->txr_idx,
926 adapter->num_tx_queues);
927
928 for (i = 0; i < q_vector->txr_count; i++) {
929 j = adapter->tx_ring[r_idx].reg_idx;
930 ixgbe_set_ivar(adapter, 1, j, v_idx);
931 r_idx = find_next_bit(q_vector->txr_idx,
932 adapter->num_tx_queues,
933 r_idx + 1);
934 }
935
936 if (q_vector->txr_count && !q_vector->rxr_count)
937 /* tx only */
938 q_vector->eitr = adapter->tx_eitr_param;
939 else if (q_vector->rxr_count)
940 /* rx or mixed */
941 q_vector->eitr = adapter->rx_eitr_param;
942
943 ixgbe_write_eitr(q_vector);
944 }
945
946 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
947 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
948 v_idx);
949 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
950 ixgbe_set_ivar(adapter, -1, 1, v_idx);
951 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
952
953 /* set up to autoclear timer, and the vectors */
954 mask = IXGBE_EIMS_ENABLE_MASK;
955 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
956 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
957 }
958
959 enum latency_range {
960 lowest_latency = 0,
961 low_latency = 1,
962 bulk_latency = 2,
963 latency_invalid = 255
964 };
965
966 /**
967 * ixgbe_update_itr - update the dynamic ITR value based on statistics
968 * @adapter: pointer to adapter
969 * @eitr: eitr setting (ints per sec) to give last timeslice
970 * @itr_setting: current throttle rate in ints/second
971 * @packets: the number of packets during this measurement interval
972 * @bytes: the number of bytes during this measurement interval
973 *
974 * Stores a new ITR value based on packets and byte
975 * counts during the last interrupt. The advantage of per interrupt
976 * computation is faster updates and more accurate ITR for the current
977 * traffic pattern. Constants in this function were computed
978 * based on theoretical maximum wire speed and thresholds were set based
979 * on testing data as well as attempting to minimize response time
980 * while increasing bulk throughput.
981 * this functionality is controlled by the InterruptThrottleRate module
982 * parameter (see ixgbe_param.c)
983 **/
984 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
985 u32 eitr, u8 itr_setting,
986 int packets, int bytes)
987 {
988 unsigned int retval = itr_setting;
989 u32 timepassed_us;
990 u64 bytes_perint;
991
992 if (packets == 0)
993 goto update_itr_done;
994
995
996 /* simple throttlerate management
997 * 0-20MB/s lowest (100000 ints/s)
998 * 20-100MB/s low (20000 ints/s)
999 * 100-1249MB/s bulk (8000 ints/s)
1000 */
1001 /* what was last interrupt timeslice? */
1002 timepassed_us = 1000000/eitr;
1003 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1004
1005 switch (itr_setting) {
1006 case lowest_latency:
1007 if (bytes_perint > adapter->eitr_low)
1008 retval = low_latency;
1009 break;
1010 case low_latency:
1011 if (bytes_perint > adapter->eitr_high)
1012 retval = bulk_latency;
1013 else if (bytes_perint <= adapter->eitr_low)
1014 retval = lowest_latency;
1015 break;
1016 case bulk_latency:
1017 if (bytes_perint <= adapter->eitr_high)
1018 retval = low_latency;
1019 break;
1020 }
1021
1022 update_itr_done:
1023 return retval;
1024 }
1025
1026 /**
1027 * ixgbe_write_eitr - write EITR register in hardware specific way
1028 * @q_vector: structure containing interrupt and ring information
1029 *
1030 * This function is made to be called by ethtool and by the driver
1031 * when it needs to update EITR registers at runtime. Hardware
1032 * specific quirks/differences are taken care of here.
1033 */
1034 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1035 {
1036 struct ixgbe_adapter *adapter = q_vector->adapter;
1037 struct ixgbe_hw *hw = &adapter->hw;
1038 int v_idx = q_vector->v_idx;
1039 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1040
1041 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1042 /* must write high and low 16 bits to reset counter */
1043 itr_reg |= (itr_reg << 16);
1044 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1045 /*
1046 * set the WDIS bit to not clear the timer bits and cause an
1047 * immediate assertion of the interrupt
1048 */
1049 itr_reg |= IXGBE_EITR_CNT_WDIS;
1050 }
1051 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1052 }
1053
1054 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1055 {
1056 struct ixgbe_adapter *adapter = q_vector->adapter;
1057 u32 new_itr;
1058 u8 current_itr, ret_itr;
1059 int i, r_idx;
1060 struct ixgbe_ring *rx_ring, *tx_ring;
1061
1062 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1063 for (i = 0; i < q_vector->txr_count; i++) {
1064 tx_ring = &(adapter->tx_ring[r_idx]);
1065 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1066 q_vector->tx_itr,
1067 tx_ring->total_packets,
1068 tx_ring->total_bytes);
1069 /* if the result for this queue would decrease interrupt
1070 * rate for this vector then use that result */
1071 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1072 q_vector->tx_itr - 1 : ret_itr);
1073 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1074 r_idx + 1);
1075 }
1076
1077 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1078 for (i = 0; i < q_vector->rxr_count; i++) {
1079 rx_ring = &(adapter->rx_ring[r_idx]);
1080 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1081 q_vector->rx_itr,
1082 rx_ring->total_packets,
1083 rx_ring->total_bytes);
1084 /* if the result for this queue would decrease interrupt
1085 * rate for this vector then use that result */
1086 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1087 q_vector->rx_itr - 1 : ret_itr);
1088 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1089 r_idx + 1);
1090 }
1091
1092 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1093
1094 switch (current_itr) {
1095 /* counts and packets in update_itr are dependent on these numbers */
1096 case lowest_latency:
1097 new_itr = 100000;
1098 break;
1099 case low_latency:
1100 new_itr = 20000; /* aka hwitr = ~200 */
1101 break;
1102 case bulk_latency:
1103 default:
1104 new_itr = 8000;
1105 break;
1106 }
1107
1108 if (new_itr != q_vector->eitr) {
1109 /* do an exponential smoothing */
1110 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1111
1112 /* save the algorithm value here, not the smoothed one */
1113 q_vector->eitr = new_itr;
1114
1115 ixgbe_write_eitr(q_vector);
1116 }
1117
1118 return;
1119 }
1120
1121 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1122 {
1123 struct ixgbe_hw *hw = &adapter->hw;
1124
1125 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1126 (eicr & IXGBE_EICR_GPI_SDP1)) {
1127 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1128 /* write to clear the interrupt */
1129 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1130 }
1131 }
1132
1133 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1134 {
1135 struct ixgbe_hw *hw = &adapter->hw;
1136
1137 if (eicr & IXGBE_EICR_GPI_SDP1) {
1138 /* Clear the interrupt */
1139 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1140 schedule_work(&adapter->multispeed_fiber_task);
1141 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1142 /* Clear the interrupt */
1143 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1144 schedule_work(&adapter->sfp_config_module_task);
1145 } else {
1146 /* Interrupt isn't for us... */
1147 return;
1148 }
1149 }
1150
1151 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1152 {
1153 struct ixgbe_hw *hw = &adapter->hw;
1154
1155 adapter->lsc_int++;
1156 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1157 adapter->link_check_timeout = jiffies;
1158 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1159 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1160 schedule_work(&adapter->watchdog_task);
1161 }
1162 }
1163
1164 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1165 {
1166 struct net_device *netdev = data;
1167 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1168 struct ixgbe_hw *hw = &adapter->hw;
1169 u32 eicr;
1170
1171 /*
1172 * Workaround for Silicon errata. Use clear-by-write instead
1173 * of clear-by-read. Reading with EICS will return the
1174 * interrupt causes without clearing, which later be done
1175 * with the write to EICR.
1176 */
1177 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1178 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1179
1180 if (eicr & IXGBE_EICR_LSC)
1181 ixgbe_check_lsc(adapter);
1182
1183 if (hw->mac.type == ixgbe_mac_82598EB)
1184 ixgbe_check_fan_failure(adapter, eicr);
1185
1186 if (hw->mac.type == ixgbe_mac_82599EB) {
1187 ixgbe_check_sfp_event(adapter, eicr);
1188
1189 /* Handle Flow Director Full threshold interrupt */
1190 if (eicr & IXGBE_EICR_FLOW_DIR) {
1191 int i;
1192 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1193 /* Disable transmits before FDIR Re-initialization */
1194 netif_tx_stop_all_queues(netdev);
1195 for (i = 0; i < adapter->num_tx_queues; i++) {
1196 struct ixgbe_ring *tx_ring =
1197 &adapter->tx_ring[i];
1198 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1199 &tx_ring->reinit_state))
1200 schedule_work(&adapter->fdir_reinit_task);
1201 }
1202 }
1203 }
1204 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1205 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1206
1207 return IRQ_HANDLED;
1208 }
1209
1210 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1211 u64 qmask)
1212 {
1213 u32 mask;
1214
1215 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1216 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1217 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1218 } else {
1219 mask = (qmask & 0xFFFFFFFF);
1220 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1221 mask = (qmask >> 32);
1222 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1223 }
1224 /* skip the flush */
1225 }
1226
1227 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1228 u64 qmask)
1229 {
1230 u32 mask;
1231
1232 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1233 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1234 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1235 } else {
1236 mask = (qmask & 0xFFFFFFFF);
1237 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1238 mask = (qmask >> 32);
1239 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1240 }
1241 /* skip the flush */
1242 }
1243
1244 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1245 {
1246 struct ixgbe_q_vector *q_vector = data;
1247 struct ixgbe_adapter *adapter = q_vector->adapter;
1248 struct ixgbe_ring *tx_ring;
1249 int i, r_idx;
1250
1251 if (!q_vector->txr_count)
1252 return IRQ_HANDLED;
1253
1254 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1255 for (i = 0; i < q_vector->txr_count; i++) {
1256 tx_ring = &(adapter->tx_ring[r_idx]);
1257 tx_ring->total_bytes = 0;
1258 tx_ring->total_packets = 0;
1259 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1260 r_idx + 1);
1261 }
1262
1263 /* disable interrupts on this vector only */
1264 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1265 napi_schedule(&q_vector->napi);
1266
1267 return IRQ_HANDLED;
1268 }
1269
1270 /**
1271 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1272 * @irq: unused
1273 * @data: pointer to our q_vector struct for this interrupt vector
1274 **/
1275 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1276 {
1277 struct ixgbe_q_vector *q_vector = data;
1278 struct ixgbe_adapter *adapter = q_vector->adapter;
1279 struct ixgbe_ring *rx_ring;
1280 int r_idx;
1281 int i;
1282
1283 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1284 for (i = 0; i < q_vector->rxr_count; i++) {
1285 rx_ring = &(adapter->rx_ring[r_idx]);
1286 rx_ring->total_bytes = 0;
1287 rx_ring->total_packets = 0;
1288 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1289 r_idx + 1);
1290 }
1291
1292 if (!q_vector->rxr_count)
1293 return IRQ_HANDLED;
1294
1295 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1296 rx_ring = &(adapter->rx_ring[r_idx]);
1297 /* disable interrupts on this vector only */
1298 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1299 napi_schedule(&q_vector->napi);
1300
1301 return IRQ_HANDLED;
1302 }
1303
1304 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1305 {
1306 struct ixgbe_q_vector *q_vector = data;
1307 struct ixgbe_adapter *adapter = q_vector->adapter;
1308 struct ixgbe_ring *ring;
1309 int r_idx;
1310 int i;
1311
1312 if (!q_vector->txr_count && !q_vector->rxr_count)
1313 return IRQ_HANDLED;
1314
1315 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1316 for (i = 0; i < q_vector->txr_count; i++) {
1317 ring = &(adapter->tx_ring[r_idx]);
1318 ring->total_bytes = 0;
1319 ring->total_packets = 0;
1320 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1321 r_idx + 1);
1322 }
1323
1324 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1325 for (i = 0; i < q_vector->rxr_count; i++) {
1326 ring = &(adapter->rx_ring[r_idx]);
1327 ring->total_bytes = 0;
1328 ring->total_packets = 0;
1329 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1330 r_idx + 1);
1331 }
1332
1333 /* disable interrupts on this vector only */
1334 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1335 napi_schedule(&q_vector->napi);
1336
1337 return IRQ_HANDLED;
1338 }
1339
1340 /**
1341 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1342 * @napi: napi struct with our devices info in it
1343 * @budget: amount of work driver is allowed to do this pass, in packets
1344 *
1345 * This function is optimized for cleaning one queue only on a single
1346 * q_vector!!!
1347 **/
1348 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1349 {
1350 struct ixgbe_q_vector *q_vector =
1351 container_of(napi, struct ixgbe_q_vector, napi);
1352 struct ixgbe_adapter *adapter = q_vector->adapter;
1353 struct ixgbe_ring *rx_ring = NULL;
1354 int work_done = 0;
1355 long r_idx;
1356
1357 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1358 rx_ring = &(adapter->rx_ring[r_idx]);
1359 #ifdef CONFIG_IXGBE_DCA
1360 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1361 ixgbe_update_rx_dca(adapter, rx_ring);
1362 #endif
1363
1364 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1365
1366 /* If all Rx work done, exit the polling mode */
1367 if (work_done < budget) {
1368 napi_complete(napi);
1369 if (adapter->rx_itr_setting & 1)
1370 ixgbe_set_itr_msix(q_vector);
1371 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1372 ixgbe_irq_enable_queues(adapter,
1373 ((u64)1 << q_vector->v_idx));
1374 }
1375
1376 return work_done;
1377 }
1378
1379 /**
1380 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1381 * @napi: napi struct with our devices info in it
1382 * @budget: amount of work driver is allowed to do this pass, in packets
1383 *
1384 * This function will clean more than one rx queue associated with a
1385 * q_vector.
1386 **/
1387 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1388 {
1389 struct ixgbe_q_vector *q_vector =
1390 container_of(napi, struct ixgbe_q_vector, napi);
1391 struct ixgbe_adapter *adapter = q_vector->adapter;
1392 struct ixgbe_ring *ring = NULL;
1393 int work_done = 0, i;
1394 long r_idx;
1395 bool tx_clean_complete = true;
1396
1397 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1398 for (i = 0; i < q_vector->txr_count; i++) {
1399 ring = &(adapter->tx_ring[r_idx]);
1400 #ifdef CONFIG_IXGBE_DCA
1401 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1402 ixgbe_update_tx_dca(adapter, ring);
1403 #endif
1404 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1405 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1406 r_idx + 1);
1407 }
1408
1409 /* attempt to distribute budget to each queue fairly, but don't allow
1410 * the budget to go below 1 because we'll exit polling */
1411 budget /= (q_vector->rxr_count ?: 1);
1412 budget = max(budget, 1);
1413 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1414 for (i = 0; i < q_vector->rxr_count; i++) {
1415 ring = &(adapter->rx_ring[r_idx]);
1416 #ifdef CONFIG_IXGBE_DCA
1417 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1418 ixgbe_update_rx_dca(adapter, ring);
1419 #endif
1420 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1421 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1422 r_idx + 1);
1423 }
1424
1425 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1426 ring = &(adapter->rx_ring[r_idx]);
1427 /* If all Rx work done, exit the polling mode */
1428 if (work_done < budget) {
1429 napi_complete(napi);
1430 if (adapter->rx_itr_setting & 1)
1431 ixgbe_set_itr_msix(q_vector);
1432 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1433 ixgbe_irq_enable_queues(adapter,
1434 ((u64)1 << q_vector->v_idx));
1435 return 0;
1436 }
1437
1438 return work_done;
1439 }
1440
1441 /**
1442 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1443 * @napi: napi struct with our devices info in it
1444 * @budget: amount of work driver is allowed to do this pass, in packets
1445 *
1446 * This function is optimized for cleaning one queue only on a single
1447 * q_vector!!!
1448 **/
1449 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1450 {
1451 struct ixgbe_q_vector *q_vector =
1452 container_of(napi, struct ixgbe_q_vector, napi);
1453 struct ixgbe_adapter *adapter = q_vector->adapter;
1454 struct ixgbe_ring *tx_ring = NULL;
1455 int work_done = 0;
1456 long r_idx;
1457
1458 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1459 tx_ring = &(adapter->tx_ring[r_idx]);
1460 #ifdef CONFIG_IXGBE_DCA
1461 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1462 ixgbe_update_tx_dca(adapter, tx_ring);
1463 #endif
1464
1465 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1466 work_done = budget;
1467
1468 /* If all Tx work done, exit the polling mode */
1469 if (work_done < budget) {
1470 napi_complete(napi);
1471 if (adapter->tx_itr_setting & 1)
1472 ixgbe_set_itr_msix(q_vector);
1473 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1474 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1475 }
1476
1477 return work_done;
1478 }
1479
1480 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1481 int r_idx)
1482 {
1483 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1484
1485 set_bit(r_idx, q_vector->rxr_idx);
1486 q_vector->rxr_count++;
1487 }
1488
1489 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1490 int t_idx)
1491 {
1492 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1493
1494 set_bit(t_idx, q_vector->txr_idx);
1495 q_vector->txr_count++;
1496 }
1497
1498 /**
1499 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1500 * @adapter: board private structure to initialize
1501 * @vectors: allotted vector count for descriptor rings
1502 *
1503 * This function maps descriptor rings to the queue-specific vectors
1504 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1505 * one vector per ring/queue, but on a constrained vector budget, we
1506 * group the rings as "efficiently" as possible. You would add new
1507 * mapping configurations in here.
1508 **/
1509 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1510 int vectors)
1511 {
1512 int v_start = 0;
1513 int rxr_idx = 0, txr_idx = 0;
1514 int rxr_remaining = adapter->num_rx_queues;
1515 int txr_remaining = adapter->num_tx_queues;
1516 int i, j;
1517 int rqpv, tqpv;
1518 int err = 0;
1519
1520 /* No mapping required if MSI-X is disabled. */
1521 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1522 goto out;
1523
1524 /*
1525 * The ideal configuration...
1526 * We have enough vectors to map one per queue.
1527 */
1528 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1529 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1530 map_vector_to_rxq(adapter, v_start, rxr_idx);
1531
1532 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1533 map_vector_to_txq(adapter, v_start, txr_idx);
1534
1535 goto out;
1536 }
1537
1538 /*
1539 * If we don't have enough vectors for a 1-to-1
1540 * mapping, we'll have to group them so there are
1541 * multiple queues per vector.
1542 */
1543 /* Re-adjusting *qpv takes care of the remainder. */
1544 for (i = v_start; i < vectors; i++) {
1545 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1546 for (j = 0; j < rqpv; j++) {
1547 map_vector_to_rxq(adapter, i, rxr_idx);
1548 rxr_idx++;
1549 rxr_remaining--;
1550 }
1551 }
1552 for (i = v_start; i < vectors; i++) {
1553 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1554 for (j = 0; j < tqpv; j++) {
1555 map_vector_to_txq(adapter, i, txr_idx);
1556 txr_idx++;
1557 txr_remaining--;
1558 }
1559 }
1560
1561 out:
1562 return err;
1563 }
1564
1565 /**
1566 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1567 * @adapter: board private structure
1568 *
1569 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1570 * interrupts from the kernel.
1571 **/
1572 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1573 {
1574 struct net_device *netdev = adapter->netdev;
1575 irqreturn_t (*handler)(int, void *);
1576 int i, vector, q_vectors, err;
1577 int ri=0, ti=0;
1578
1579 /* Decrement for Other and TCP Timer vectors */
1580 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1581
1582 /* Map the Tx/Rx rings to the vectors we were allotted. */
1583 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1584 if (err)
1585 goto out;
1586
1587 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1588 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1589 &ixgbe_msix_clean_many)
1590 for (vector = 0; vector < q_vectors; vector++) {
1591 handler = SET_HANDLER(adapter->q_vector[vector]);
1592
1593 if(handler == &ixgbe_msix_clean_rx) {
1594 sprintf(adapter->name[vector], "%s-%s-%d",
1595 netdev->name, "rx", ri++);
1596 }
1597 else if(handler == &ixgbe_msix_clean_tx) {
1598 sprintf(adapter->name[vector], "%s-%s-%d",
1599 netdev->name, "tx", ti++);
1600 }
1601 else
1602 sprintf(adapter->name[vector], "%s-%s-%d",
1603 netdev->name, "TxRx", vector);
1604
1605 err = request_irq(adapter->msix_entries[vector].vector,
1606 handler, 0, adapter->name[vector],
1607 adapter->q_vector[vector]);
1608 if (err) {
1609 DPRINTK(PROBE, ERR,
1610 "request_irq failed for MSIX interrupt "
1611 "Error: %d\n", err);
1612 goto free_queue_irqs;
1613 }
1614 }
1615
1616 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1617 err = request_irq(adapter->msix_entries[vector].vector,
1618 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1619 if (err) {
1620 DPRINTK(PROBE, ERR,
1621 "request_irq for msix_lsc failed: %d\n", err);
1622 goto free_queue_irqs;
1623 }
1624
1625 return 0;
1626
1627 free_queue_irqs:
1628 for (i = vector - 1; i >= 0; i--)
1629 free_irq(adapter->msix_entries[--vector].vector,
1630 adapter->q_vector[i]);
1631 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1632 pci_disable_msix(adapter->pdev);
1633 kfree(adapter->msix_entries);
1634 adapter->msix_entries = NULL;
1635 out:
1636 return err;
1637 }
1638
1639 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1640 {
1641 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1642 u8 current_itr;
1643 u32 new_itr = q_vector->eitr;
1644 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1645 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1646
1647 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1648 q_vector->tx_itr,
1649 tx_ring->total_packets,
1650 tx_ring->total_bytes);
1651 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1652 q_vector->rx_itr,
1653 rx_ring->total_packets,
1654 rx_ring->total_bytes);
1655
1656 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1657
1658 switch (current_itr) {
1659 /* counts and packets in update_itr are dependent on these numbers */
1660 case lowest_latency:
1661 new_itr = 100000;
1662 break;
1663 case low_latency:
1664 new_itr = 20000; /* aka hwitr = ~200 */
1665 break;
1666 case bulk_latency:
1667 new_itr = 8000;
1668 break;
1669 default:
1670 break;
1671 }
1672
1673 if (new_itr != q_vector->eitr) {
1674 /* do an exponential smoothing */
1675 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1676
1677 /* save the algorithm value here, not the smoothed one */
1678 q_vector->eitr = new_itr;
1679
1680 ixgbe_write_eitr(q_vector);
1681 }
1682
1683 return;
1684 }
1685
1686 /**
1687 * ixgbe_irq_enable - Enable default interrupt generation settings
1688 * @adapter: board private structure
1689 **/
1690 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1691 {
1692 u32 mask;
1693
1694 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1695 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1696 mask |= IXGBE_EIMS_GPI_SDP1;
1697 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1698 mask |= IXGBE_EIMS_ECC;
1699 mask |= IXGBE_EIMS_GPI_SDP1;
1700 mask |= IXGBE_EIMS_GPI_SDP2;
1701 }
1702 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1703 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1704 mask |= IXGBE_EIMS_FLOW_DIR;
1705
1706 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1707 ixgbe_irq_enable_queues(adapter, ~0);
1708 IXGBE_WRITE_FLUSH(&adapter->hw);
1709 }
1710
1711 /**
1712 * ixgbe_intr - legacy mode Interrupt Handler
1713 * @irq: interrupt number
1714 * @data: pointer to a network interface device structure
1715 **/
1716 static irqreturn_t ixgbe_intr(int irq, void *data)
1717 {
1718 struct net_device *netdev = data;
1719 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1720 struct ixgbe_hw *hw = &adapter->hw;
1721 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1722 u32 eicr;
1723
1724 /*
1725 * Workaround for silicon errata. Mask the interrupts
1726 * before the read of EICR.
1727 */
1728 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1729
1730 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1731 * therefore no explict interrupt disable is necessary */
1732 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1733 if (!eicr) {
1734 /* shared interrupt alert!
1735 * make sure interrupts are enabled because the read will
1736 * have disabled interrupts due to EIAM */
1737 ixgbe_irq_enable(adapter);
1738 return IRQ_NONE; /* Not our interrupt */
1739 }
1740
1741 if (eicr & IXGBE_EICR_LSC)
1742 ixgbe_check_lsc(adapter);
1743
1744 if (hw->mac.type == ixgbe_mac_82599EB)
1745 ixgbe_check_sfp_event(adapter, eicr);
1746
1747 ixgbe_check_fan_failure(adapter, eicr);
1748
1749 if (napi_schedule_prep(&(q_vector->napi))) {
1750 adapter->tx_ring[0].total_packets = 0;
1751 adapter->tx_ring[0].total_bytes = 0;
1752 adapter->rx_ring[0].total_packets = 0;
1753 adapter->rx_ring[0].total_bytes = 0;
1754 /* would disable interrupts here but EIAM disabled it */
1755 __napi_schedule(&(q_vector->napi));
1756 }
1757
1758 return IRQ_HANDLED;
1759 }
1760
1761 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1762 {
1763 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1764
1765 for (i = 0; i < q_vectors; i++) {
1766 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1767 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1768 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1769 q_vector->rxr_count = 0;
1770 q_vector->txr_count = 0;
1771 }
1772 }
1773
1774 /**
1775 * ixgbe_request_irq - initialize interrupts
1776 * @adapter: board private structure
1777 *
1778 * Attempts to configure interrupts using the best available
1779 * capabilities of the hardware and kernel.
1780 **/
1781 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1782 {
1783 struct net_device *netdev = adapter->netdev;
1784 int err;
1785
1786 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1787 err = ixgbe_request_msix_irqs(adapter);
1788 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1789 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1790 netdev->name, netdev);
1791 } else {
1792 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1793 netdev->name, netdev);
1794 }
1795
1796 if (err)
1797 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1798
1799 return err;
1800 }
1801
1802 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1803 {
1804 struct net_device *netdev = adapter->netdev;
1805
1806 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1807 int i, q_vectors;
1808
1809 q_vectors = adapter->num_msix_vectors;
1810
1811 i = q_vectors - 1;
1812 free_irq(adapter->msix_entries[i].vector, netdev);
1813
1814 i--;
1815 for (; i >= 0; i--) {
1816 free_irq(adapter->msix_entries[i].vector,
1817 adapter->q_vector[i]);
1818 }
1819
1820 ixgbe_reset_q_vectors(adapter);
1821 } else {
1822 free_irq(adapter->pdev->irq, netdev);
1823 }
1824 }
1825
1826 /**
1827 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1828 * @adapter: board private structure
1829 **/
1830 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1831 {
1832 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1833 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1834 } else {
1835 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1836 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1838 }
1839 IXGBE_WRITE_FLUSH(&adapter->hw);
1840 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1841 int i;
1842 for (i = 0; i < adapter->num_msix_vectors; i++)
1843 synchronize_irq(adapter->msix_entries[i].vector);
1844 } else {
1845 synchronize_irq(adapter->pdev->irq);
1846 }
1847 }
1848
1849 /**
1850 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1851 *
1852 **/
1853 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1854 {
1855 struct ixgbe_hw *hw = &adapter->hw;
1856
1857 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1858 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1859
1860 ixgbe_set_ivar(adapter, 0, 0, 0);
1861 ixgbe_set_ivar(adapter, 1, 0, 0);
1862
1863 map_vector_to_rxq(adapter, 0, 0);
1864 map_vector_to_txq(adapter, 0, 0);
1865
1866 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1867 }
1868
1869 /**
1870 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1871 * @adapter: board private structure
1872 *
1873 * Configure the Tx unit of the MAC after a reset.
1874 **/
1875 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1876 {
1877 u64 tdba;
1878 struct ixgbe_hw *hw = &adapter->hw;
1879 u32 i, j, tdlen, txctrl;
1880
1881 /* Setup the HW Tx Head and Tail descriptor pointers */
1882 for (i = 0; i < adapter->num_tx_queues; i++) {
1883 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1884 j = ring->reg_idx;
1885 tdba = ring->dma;
1886 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1887 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1888 (tdba & DMA_BIT_MASK(32)));
1889 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1890 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1891 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1892 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1893 adapter->tx_ring[i].head = IXGBE_TDH(j);
1894 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1895 /*
1896 * Disable Tx Head Writeback RO bit, since this hoses
1897 * bookkeeping if things aren't delivered in order.
1898 */
1899 switch (hw->mac.type) {
1900 case ixgbe_mac_82598EB:
1901 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1902 break;
1903 case ixgbe_mac_82599EB:
1904 default:
1905 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1906 break;
1907 }
1908 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1909 switch (hw->mac.type) {
1910 case ixgbe_mac_82598EB:
1911 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1912 break;
1913 case ixgbe_mac_82599EB:
1914 default:
1915 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1916 break;
1917 }
1918 }
1919 if (hw->mac.type == ixgbe_mac_82599EB) {
1920 /* We enable 8 traffic classes, DCB only */
1921 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1922 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1923 IXGBE_MTQC_8TC_8TQ));
1924 }
1925 }
1926
1927 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1928
1929 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1930 struct ixgbe_ring *rx_ring)
1931 {
1932 u32 srrctl;
1933 int index;
1934 struct ixgbe_ring_feature *feature = adapter->ring_feature;
1935
1936 index = rx_ring->reg_idx;
1937 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1938 unsigned long mask;
1939 mask = (unsigned long) feature[RING_F_RSS].mask;
1940 index = index & mask;
1941 }
1942 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1943
1944 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1945 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1946
1947 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1948 IXGBE_SRRCTL_BSIZEHDR_MASK;
1949
1950 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1951 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1952 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1953 #else
1954 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1955 #endif
1956 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1957 } else {
1958 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1959 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1960 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1961 }
1962
1963 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1964 }
1965
1966 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1967 {
1968 u32 mrqc = 0;
1969 int mask;
1970
1971 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1972 return mrqc;
1973
1974 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1975 #ifdef CONFIG_IXGBE_DCB
1976 | IXGBE_FLAG_DCB_ENABLED
1977 #endif
1978 );
1979
1980 switch (mask) {
1981 case (IXGBE_FLAG_RSS_ENABLED):
1982 mrqc = IXGBE_MRQC_RSSEN;
1983 break;
1984 #ifdef CONFIG_IXGBE_DCB
1985 case (IXGBE_FLAG_DCB_ENABLED):
1986 mrqc = IXGBE_MRQC_RT8TCEN;
1987 break;
1988 #endif /* CONFIG_IXGBE_DCB */
1989 default:
1990 break;
1991 }
1992
1993 return mrqc;
1994 }
1995
1996 /**
1997 * ixgbe_configure_rscctl - enable RSC for the indicated ring
1998 * @adapter: address of board private structure
1999 * @index: index of ring to set
2000 * @rx_buf_len: rx buffer length
2001 **/
2002 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index,
2003 int rx_buf_len)
2004 {
2005 struct ixgbe_ring *rx_ring;
2006 struct ixgbe_hw *hw = &adapter->hw;
2007 int j;
2008 u32 rscctrl;
2009
2010 rx_ring = &adapter->rx_ring[index];
2011 j = rx_ring->reg_idx;
2012 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2013 rscctrl |= IXGBE_RSCCTL_RSCEN;
2014 /*
2015 * we must limit the number of descriptors so that the
2016 * total size of max desc * buf_len is not greater
2017 * than 65535
2018 */
2019 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2020 #if (MAX_SKB_FRAGS > 16)
2021 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2022 #elif (MAX_SKB_FRAGS > 8)
2023 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2024 #elif (MAX_SKB_FRAGS > 4)
2025 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2026 #else
2027 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2028 #endif
2029 } else {
2030 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2031 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2032 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2033 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2034 else
2035 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2036 }
2037 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2038 }
2039
2040 /**
2041 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2042 * @adapter: board private structure
2043 *
2044 * Configure the Rx unit of the MAC after a reset.
2045 **/
2046 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2047 {
2048 u64 rdba;
2049 struct ixgbe_hw *hw = &adapter->hw;
2050 struct ixgbe_ring *rx_ring;
2051 struct net_device *netdev = adapter->netdev;
2052 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2053 int i, j;
2054 u32 rdlen, rxctrl, rxcsum;
2055 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2056 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2057 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2058 u32 fctrl, hlreg0;
2059 u32 reta = 0, mrqc = 0;
2060 u32 rdrxctl;
2061 int rx_buf_len;
2062
2063 /* Decide whether to use packet split mode or not */
2064 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2065
2066 /* Set the RX buffer length according to the mode */
2067 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2068 rx_buf_len = IXGBE_RX_HDR_SIZE;
2069 if (hw->mac.type == ixgbe_mac_82599EB) {
2070 /* PSRTYPE must be initialized in 82599 */
2071 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2072 IXGBE_PSRTYPE_UDPHDR |
2073 IXGBE_PSRTYPE_IPV4HDR |
2074 IXGBE_PSRTYPE_IPV6HDR |
2075 IXGBE_PSRTYPE_L2HDR;
2076 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2077 }
2078 } else {
2079 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2080 (netdev->mtu <= ETH_DATA_LEN))
2081 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2082 else
2083 rx_buf_len = ALIGN(max_frame, 1024);
2084 }
2085
2086 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2087 fctrl |= IXGBE_FCTRL_BAM;
2088 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2089 fctrl |= IXGBE_FCTRL_PMCF;
2090 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2091
2092 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2093 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2094 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2095 else
2096 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2097 #ifdef IXGBE_FCOE
2098 if (netdev->features & NETIF_F_FCOE_MTU)
2099 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2100 #endif
2101 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2102
2103 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2104 /* disable receives while setting up the descriptors */
2105 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2106 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2107
2108 /*
2109 * Setup the HW Rx Head and Tail Descriptor Pointers and
2110 * the Base and Length of the Rx Descriptor Ring
2111 */
2112 for (i = 0; i < adapter->num_rx_queues; i++) {
2113 rx_ring = &adapter->rx_ring[i];
2114 rdba = rx_ring->dma;
2115 j = rx_ring->reg_idx;
2116 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2117 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2118 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2119 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2120 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2121 rx_ring->head = IXGBE_RDH(j);
2122 rx_ring->tail = IXGBE_RDT(j);
2123 rx_ring->rx_buf_len = rx_buf_len;
2124
2125 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2126 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2127 else
2128 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2129
2130 #ifdef IXGBE_FCOE
2131 if (netdev->features & NETIF_F_FCOE_MTU) {
2132 struct ixgbe_ring_feature *f;
2133 f = &adapter->ring_feature[RING_F_FCOE];
2134 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2135 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2136 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2137 rx_ring->rx_buf_len =
2138 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2139 }
2140 }
2141
2142 #endif /* IXGBE_FCOE */
2143 ixgbe_configure_srrctl(adapter, rx_ring);
2144 }
2145
2146 if (hw->mac.type == ixgbe_mac_82598EB) {
2147 /*
2148 * For VMDq support of different descriptor types or
2149 * buffer sizes through the use of multiple SRRCTL
2150 * registers, RDRXCTL.MVMEN must be set to 1
2151 *
2152 * also, the manual doesn't mention it clearly but DCA hints
2153 * will only use queue 0's tags unless this bit is set. Side
2154 * effects of setting this bit are only that SRRCTL must be
2155 * fully programmed [0..15]
2156 */
2157 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2158 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2159 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2160 }
2161
2162 /* Program MRQC for the distribution of queues */
2163 mrqc = ixgbe_setup_mrqc(adapter);
2164
2165 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2166 /* Fill out redirection table */
2167 for (i = 0, j = 0; i < 128; i++, j++) {
2168 if (j == adapter->ring_feature[RING_F_RSS].indices)
2169 j = 0;
2170 /* reta = 4-byte sliding window of
2171 * 0x00..(indices-1)(indices-1)00..etc. */
2172 reta = (reta << 8) | (j * 0x11);
2173 if ((i & 3) == 3)
2174 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2175 }
2176
2177 /* Fill out hash function seeds */
2178 for (i = 0; i < 10; i++)
2179 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2180
2181 if (hw->mac.type == ixgbe_mac_82598EB)
2182 mrqc |= IXGBE_MRQC_RSSEN;
2183 /* Perform hash on these packet types */
2184 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2185 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2186 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2187 | IXGBE_MRQC_RSS_FIELD_IPV6
2188 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2189 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2190 }
2191 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2192
2193 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2194
2195 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2196 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2197 /* Disable indicating checksum in descriptor, enables
2198 * RSS hash */
2199 rxcsum |= IXGBE_RXCSUM_PCSD;
2200 }
2201 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2202 /* Enable IPv4 payload checksum for UDP fragments
2203 * if PCSD is not set */
2204 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2205 }
2206
2207 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2208
2209 if (hw->mac.type == ixgbe_mac_82599EB) {
2210 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2211 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2212 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2213 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2214 }
2215
2216 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2217 /* Enable 82599 HW-RSC */
2218 for (i = 0; i < adapter->num_rx_queues; i++)
2219 ixgbe_configure_rscctl(adapter, i, rx_buf_len);
2220
2221 /* Disable RSC for ACK packets */
2222 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2223 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2224 }
2225 }
2226
2227 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2228 {
2229 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2230 struct ixgbe_hw *hw = &adapter->hw;
2231
2232 /* add VID to filter table */
2233 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2234 }
2235
2236 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2237 {
2238 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2239 struct ixgbe_hw *hw = &adapter->hw;
2240
2241 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2242 ixgbe_irq_disable(adapter);
2243
2244 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2245
2246 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2247 ixgbe_irq_enable(adapter);
2248
2249 /* remove VID from filter table */
2250 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2251 }
2252
2253 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2254 struct vlan_group *grp)
2255 {
2256 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2257 u32 ctrl;
2258 int i, j;
2259
2260 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2261 ixgbe_irq_disable(adapter);
2262 adapter->vlgrp = grp;
2263
2264 /*
2265 * For a DCB driver, always enable VLAN tag stripping so we can
2266 * still receive traffic from a DCB-enabled host even if we're
2267 * not in DCB mode.
2268 */
2269 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2270 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2271 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2272 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2273 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2274 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2275 ctrl |= IXGBE_VLNCTRL_VFE;
2276 /* enable VLAN tag insert/strip */
2277 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2278 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2279 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2280 for (i = 0; i < adapter->num_rx_queues; i++) {
2281 j = adapter->rx_ring[i].reg_idx;
2282 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2283 ctrl |= IXGBE_RXDCTL_VME;
2284 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2285 }
2286 }
2287 ixgbe_vlan_rx_add_vid(netdev, 0);
2288
2289 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2290 ixgbe_irq_enable(adapter);
2291 }
2292
2293 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2294 {
2295 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2296
2297 if (adapter->vlgrp) {
2298 u16 vid;
2299 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2300 if (!vlan_group_get_device(adapter->vlgrp, vid))
2301 continue;
2302 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2303 }
2304 }
2305 }
2306
2307 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2308 {
2309 struct dev_mc_list *mc_ptr;
2310 u8 *addr = *mc_addr_ptr;
2311 *vmdq = 0;
2312
2313 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2314 if (mc_ptr->next)
2315 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2316 else
2317 *mc_addr_ptr = NULL;
2318
2319 return addr;
2320 }
2321
2322 /**
2323 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2324 * @netdev: network interface device structure
2325 *
2326 * The set_rx_method entry point is called whenever the unicast/multicast
2327 * address list or the network interface flags are updated. This routine is
2328 * responsible for configuring the hardware for proper unicast, multicast and
2329 * promiscuous mode.
2330 **/
2331 static void ixgbe_set_rx_mode(struct net_device *netdev)
2332 {
2333 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2334 struct ixgbe_hw *hw = &adapter->hw;
2335 u32 fctrl, vlnctrl;
2336 u8 *addr_list = NULL;
2337 int addr_count = 0;
2338
2339 /* Check for Promiscuous and All Multicast modes */
2340
2341 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2342 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2343
2344 if (netdev->flags & IFF_PROMISC) {
2345 hw->addr_ctrl.user_set_promisc = 1;
2346 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2347 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2348 } else {
2349 if (netdev->flags & IFF_ALLMULTI) {
2350 fctrl |= IXGBE_FCTRL_MPE;
2351 fctrl &= ~IXGBE_FCTRL_UPE;
2352 } else {
2353 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2354 }
2355 vlnctrl |= IXGBE_VLNCTRL_VFE;
2356 hw->addr_ctrl.user_set_promisc = 0;
2357 }
2358
2359 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2360 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2361
2362 /* reprogram secondary unicast list */
2363 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2364
2365 /* reprogram multicast list */
2366 addr_count = netdev->mc_count;
2367 if (addr_count)
2368 addr_list = netdev->mc_list->dmi_addr;
2369 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2370 ixgbe_addr_list_itr);
2371 }
2372
2373 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2374 {
2375 int q_idx;
2376 struct ixgbe_q_vector *q_vector;
2377 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2378
2379 /* legacy and MSI only use one vector */
2380 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2381 q_vectors = 1;
2382
2383 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2384 struct napi_struct *napi;
2385 q_vector = adapter->q_vector[q_idx];
2386 napi = &q_vector->napi;
2387 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2388 if (!q_vector->rxr_count || !q_vector->txr_count) {
2389 if (q_vector->txr_count == 1)
2390 napi->poll = &ixgbe_clean_txonly;
2391 else if (q_vector->rxr_count == 1)
2392 napi->poll = &ixgbe_clean_rxonly;
2393 }
2394 }
2395
2396 napi_enable(napi);
2397 }
2398 }
2399
2400 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2401 {
2402 int q_idx;
2403 struct ixgbe_q_vector *q_vector;
2404 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2405
2406 /* legacy and MSI only use one vector */
2407 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2408 q_vectors = 1;
2409
2410 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2411 q_vector = adapter->q_vector[q_idx];
2412 napi_disable(&q_vector->napi);
2413 }
2414 }
2415
2416 #ifdef CONFIG_IXGBE_DCB
2417 /*
2418 * ixgbe_configure_dcb - Configure DCB hardware
2419 * @adapter: ixgbe adapter struct
2420 *
2421 * This is called by the driver on open to configure the DCB hardware.
2422 * This is also called by the gennetlink interface when reconfiguring
2423 * the DCB state.
2424 */
2425 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2426 {
2427 struct ixgbe_hw *hw = &adapter->hw;
2428 u32 txdctl, vlnctrl;
2429 int i, j;
2430
2431 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2432 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2433 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2434
2435 /* reconfigure the hardware */
2436 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2437
2438 for (i = 0; i < adapter->num_tx_queues; i++) {
2439 j = adapter->tx_ring[i].reg_idx;
2440 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2441 /* PThresh workaround for Tx hang with DFP enabled. */
2442 txdctl |= 32;
2443 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2444 }
2445 /* Enable VLAN tag insert/strip */
2446 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2447 if (hw->mac.type == ixgbe_mac_82598EB) {
2448 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2449 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2450 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2451 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2452 vlnctrl |= IXGBE_VLNCTRL_VFE;
2453 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2454 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2455 for (i = 0; i < adapter->num_rx_queues; i++) {
2456 j = adapter->rx_ring[i].reg_idx;
2457 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2458 vlnctrl |= IXGBE_RXDCTL_VME;
2459 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2460 }
2461 }
2462 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2463 }
2464
2465 #endif
2466 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2467 {
2468 struct net_device *netdev = adapter->netdev;
2469 struct ixgbe_hw *hw = &adapter->hw;
2470 int i;
2471
2472 ixgbe_set_rx_mode(netdev);
2473
2474 ixgbe_restore_vlan(adapter);
2475 #ifdef CONFIG_IXGBE_DCB
2476 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2477 netif_set_gso_max_size(netdev, 32768);
2478 ixgbe_configure_dcb(adapter);
2479 } else {
2480 netif_set_gso_max_size(netdev, 65536);
2481 }
2482 #else
2483 netif_set_gso_max_size(netdev, 65536);
2484 #endif
2485
2486 #ifdef IXGBE_FCOE
2487 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2488 ixgbe_configure_fcoe(adapter);
2489
2490 #endif /* IXGBE_FCOE */
2491 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2492 for (i = 0; i < adapter->num_tx_queues; i++)
2493 adapter->tx_ring[i].atr_sample_rate =
2494 adapter->atr_sample_rate;
2495 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2496 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2497 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2498 }
2499
2500 ixgbe_configure_tx(adapter);
2501 ixgbe_configure_rx(adapter);
2502 for (i = 0; i < adapter->num_rx_queues; i++)
2503 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2504 (adapter->rx_ring[i].count - 1));
2505 }
2506
2507 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2508 {
2509 switch (hw->phy.type) {
2510 case ixgbe_phy_sfp_avago:
2511 case ixgbe_phy_sfp_ftl:
2512 case ixgbe_phy_sfp_intel:
2513 case ixgbe_phy_sfp_unknown:
2514 case ixgbe_phy_tw_tyco:
2515 case ixgbe_phy_tw_unknown:
2516 return true;
2517 default:
2518 return false;
2519 }
2520 }
2521
2522 /**
2523 * ixgbe_sfp_link_config - set up SFP+ link
2524 * @adapter: pointer to private adapter struct
2525 **/
2526 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2527 {
2528 struct ixgbe_hw *hw = &adapter->hw;
2529
2530 if (hw->phy.multispeed_fiber) {
2531 /*
2532 * In multispeed fiber setups, the device may not have
2533 * had a physical connection when the driver loaded.
2534 * If that's the case, the initial link configuration
2535 * couldn't get the MAC into 10G or 1G mode, so we'll
2536 * never have a link status change interrupt fire.
2537 * We need to try and force an autonegotiation
2538 * session, then bring up link.
2539 */
2540 hw->mac.ops.setup_sfp(hw);
2541 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2542 schedule_work(&adapter->multispeed_fiber_task);
2543 } else {
2544 /*
2545 * Direct Attach Cu and non-multispeed fiber modules
2546 * still need to be configured properly prior to
2547 * attempting link.
2548 */
2549 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2550 schedule_work(&adapter->sfp_config_module_task);
2551 }
2552 }
2553
2554 /**
2555 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2556 * @hw: pointer to private hardware struct
2557 *
2558 * Returns 0 on success, negative on failure
2559 **/
2560 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2561 {
2562 u32 autoneg;
2563 bool negotiation, link_up = false;
2564 u32 ret = IXGBE_ERR_LINK_SETUP;
2565
2566 if (hw->mac.ops.check_link)
2567 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2568
2569 if (ret)
2570 goto link_cfg_out;
2571
2572 if (hw->mac.ops.get_link_capabilities)
2573 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2574 if (ret)
2575 goto link_cfg_out;
2576
2577 if (hw->mac.ops.setup_link)
2578 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2579 link_cfg_out:
2580 return ret;
2581 }
2582
2583 #define IXGBE_MAX_RX_DESC_POLL 10
2584 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2585 int rxr)
2586 {
2587 int j = adapter->rx_ring[rxr].reg_idx;
2588 int k;
2589
2590 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2591 if (IXGBE_READ_REG(&adapter->hw,
2592 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2593 break;
2594 else
2595 msleep(1);
2596 }
2597 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2598 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2599 "not set within the polling period\n", rxr);
2600 }
2601 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2602 (adapter->rx_ring[rxr].count - 1));
2603 }
2604
2605 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2606 {
2607 struct net_device *netdev = adapter->netdev;
2608 struct ixgbe_hw *hw = &adapter->hw;
2609 int i, j = 0;
2610 int num_rx_rings = adapter->num_rx_queues;
2611 int err;
2612 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2613 u32 txdctl, rxdctl, mhadd;
2614 u32 dmatxctl;
2615 u32 gpie;
2616
2617 ixgbe_get_hw_control(adapter);
2618
2619 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2620 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2621 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2622 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2623 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2624 } else {
2625 /* MSI only */
2626 gpie = 0;
2627 }
2628 /* XXX: to interrupt immediately for EICS writes, enable this */
2629 /* gpie |= IXGBE_GPIE_EIMEN; */
2630 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2631 }
2632
2633 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2634 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2635 * specifically only auto mask tx and rx interrupts */
2636 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2637 }
2638
2639 /* Enable fan failure interrupt if media type is copper */
2640 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2641 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2642 gpie |= IXGBE_SDP1_GPIEN;
2643 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2644 }
2645
2646 if (hw->mac.type == ixgbe_mac_82599EB) {
2647 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2648 gpie |= IXGBE_SDP1_GPIEN;
2649 gpie |= IXGBE_SDP2_GPIEN;
2650 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2651 }
2652
2653 #ifdef IXGBE_FCOE
2654 /* adjust max frame to be able to do baby jumbo for FCoE */
2655 if ((netdev->features & NETIF_F_FCOE_MTU) &&
2656 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2657 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2658
2659 #endif /* IXGBE_FCOE */
2660 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2661 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2662 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2663 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2664
2665 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2666 }
2667
2668 for (i = 0; i < adapter->num_tx_queues; i++) {
2669 j = adapter->tx_ring[i].reg_idx;
2670 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2671 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2672 txdctl |= (8 << 16);
2673 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2674 }
2675
2676 if (hw->mac.type == ixgbe_mac_82599EB) {
2677 /* DMATXCTL.EN must be set after all Tx queue config is done */
2678 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2679 dmatxctl |= IXGBE_DMATXCTL_TE;
2680 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2681 }
2682 for (i = 0; i < adapter->num_tx_queues; i++) {
2683 j = adapter->tx_ring[i].reg_idx;
2684 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2685 txdctl |= IXGBE_TXDCTL_ENABLE;
2686 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2687 }
2688
2689 for (i = 0; i < num_rx_rings; i++) {
2690 j = adapter->rx_ring[i].reg_idx;
2691 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2692 /* enable PTHRESH=32 descriptors (half the internal cache)
2693 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2694 * this also removes a pesky rx_no_buffer_count increment */
2695 rxdctl |= 0x0020;
2696 rxdctl |= IXGBE_RXDCTL_ENABLE;
2697 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2698 if (hw->mac.type == ixgbe_mac_82599EB)
2699 ixgbe_rx_desc_queue_enable(adapter, i);
2700 }
2701 /* enable all receives */
2702 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2703 if (hw->mac.type == ixgbe_mac_82598EB)
2704 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2705 else
2706 rxdctl |= IXGBE_RXCTRL_RXEN;
2707 hw->mac.ops.enable_rx_dma(hw, rxdctl);
2708
2709 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2710 ixgbe_configure_msix(adapter);
2711 else
2712 ixgbe_configure_msi_and_legacy(adapter);
2713
2714 clear_bit(__IXGBE_DOWN, &adapter->state);
2715 ixgbe_napi_enable_all(adapter);
2716
2717 /* clear any pending interrupts, may auto mask */
2718 IXGBE_READ_REG(hw, IXGBE_EICR);
2719
2720 ixgbe_irq_enable(adapter);
2721
2722 /*
2723 * If this adapter has a fan, check to see if we had a failure
2724 * before we enabled the interrupt.
2725 */
2726 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2727 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2728 if (esdp & IXGBE_ESDP_SDP1)
2729 DPRINTK(DRV, CRIT,
2730 "Fan has stopped, replace the adapter\n");
2731 }
2732
2733 /*
2734 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2735 * arrived before interrupts were enabled but after probe. Such
2736 * devices wouldn't have their type identified yet. We need to
2737 * kick off the SFP+ module setup first, then try to bring up link.
2738 * If we're not hot-pluggable SFP+, we just need to configure link
2739 * and bring it up.
2740 */
2741 if (hw->phy.type == ixgbe_phy_unknown) {
2742 err = hw->phy.ops.identify(hw);
2743 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2744 /*
2745 * Take the device down and schedule the sfp tasklet
2746 * which will unregister_netdev and log it.
2747 */
2748 ixgbe_down(adapter);
2749 schedule_work(&adapter->sfp_config_module_task);
2750 return err;
2751 }
2752 }
2753
2754 if (ixgbe_is_sfp(hw)) {
2755 ixgbe_sfp_link_config(adapter);
2756 } else {
2757 err = ixgbe_non_sfp_link_config(hw);
2758 if (err)
2759 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2760 }
2761
2762 for (i = 0; i < adapter->num_tx_queues; i++)
2763 set_bit(__IXGBE_FDIR_INIT_DONE,
2764 &(adapter->tx_ring[i].reinit_state));
2765
2766 /* enable transmits */
2767 netif_tx_start_all_queues(netdev);
2768
2769 /* bring the link up in the watchdog, this could race with our first
2770 * link up interrupt but shouldn't be a problem */
2771 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2772 adapter->link_check_timeout = jiffies;
2773 mod_timer(&adapter->watchdog_timer, jiffies);
2774 return 0;
2775 }
2776
2777 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2778 {
2779 WARN_ON(in_interrupt());
2780 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2781 msleep(1);
2782 ixgbe_down(adapter);
2783 ixgbe_up(adapter);
2784 clear_bit(__IXGBE_RESETTING, &adapter->state);
2785 }
2786
2787 int ixgbe_up(struct ixgbe_adapter *adapter)
2788 {
2789 /* hardware has been reset, we need to reload some things */
2790 ixgbe_configure(adapter);
2791
2792 return ixgbe_up_complete(adapter);
2793 }
2794
2795 void ixgbe_reset(struct ixgbe_adapter *adapter)
2796 {
2797 struct ixgbe_hw *hw = &adapter->hw;
2798 int err;
2799
2800 err = hw->mac.ops.init_hw(hw);
2801 switch (err) {
2802 case 0:
2803 case IXGBE_ERR_SFP_NOT_PRESENT:
2804 break;
2805 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2806 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2807 break;
2808 case IXGBE_ERR_EEPROM_VERSION:
2809 /* We are running on a pre-production device, log a warning */
2810 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2811 "adapter/LOM. Please be aware there may be issues "
2812 "associated with your hardware. If you are "
2813 "experiencing problems please contact your Intel or "
2814 "hardware representative who provided you with this "
2815 "hardware.\n");
2816 break;
2817 default:
2818 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2819 }
2820
2821 /* reprogram the RAR[0] in case user changed it. */
2822 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2823 }
2824
2825 /**
2826 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2827 * @adapter: board private structure
2828 * @rx_ring: ring to free buffers from
2829 **/
2830 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2831 struct ixgbe_ring *rx_ring)
2832 {
2833 struct pci_dev *pdev = adapter->pdev;
2834 unsigned long size;
2835 unsigned int i;
2836
2837 /* Free all the Rx ring sk_buffs */
2838
2839 for (i = 0; i < rx_ring->count; i++) {
2840 struct ixgbe_rx_buffer *rx_buffer_info;
2841
2842 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2843 if (rx_buffer_info->dma) {
2844 pci_unmap_single(pdev, rx_buffer_info->dma,
2845 rx_ring->rx_buf_len,
2846 PCI_DMA_FROMDEVICE);
2847 rx_buffer_info->dma = 0;
2848 }
2849 if (rx_buffer_info->skb) {
2850 struct sk_buff *skb = rx_buffer_info->skb;
2851 rx_buffer_info->skb = NULL;
2852 do {
2853 struct sk_buff *this = skb;
2854 skb = skb->prev;
2855 dev_kfree_skb(this);
2856 } while (skb);
2857 }
2858 if (!rx_buffer_info->page)
2859 continue;
2860 if (rx_buffer_info->page_dma) {
2861 pci_unmap_page(pdev, rx_buffer_info->page_dma,
2862 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2863 rx_buffer_info->page_dma = 0;
2864 }
2865 put_page(rx_buffer_info->page);
2866 rx_buffer_info->page = NULL;
2867 rx_buffer_info->page_offset = 0;
2868 }
2869
2870 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2871 memset(rx_ring->rx_buffer_info, 0, size);
2872
2873 /* Zero out the descriptor ring */
2874 memset(rx_ring->desc, 0, rx_ring->size);
2875
2876 rx_ring->next_to_clean = 0;
2877 rx_ring->next_to_use = 0;
2878
2879 if (rx_ring->head)
2880 writel(0, adapter->hw.hw_addr + rx_ring->head);
2881 if (rx_ring->tail)
2882 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2883 }
2884
2885 /**
2886 * ixgbe_clean_tx_ring - Free Tx Buffers
2887 * @adapter: board private structure
2888 * @tx_ring: ring to be cleaned
2889 **/
2890 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2891 struct ixgbe_ring *tx_ring)
2892 {
2893 struct ixgbe_tx_buffer *tx_buffer_info;
2894 unsigned long size;
2895 unsigned int i;
2896
2897 /* Free all the Tx ring sk_buffs */
2898
2899 for (i = 0; i < tx_ring->count; i++) {
2900 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2901 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2902 }
2903
2904 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2905 memset(tx_ring->tx_buffer_info, 0, size);
2906
2907 /* Zero out the descriptor ring */
2908 memset(tx_ring->desc, 0, tx_ring->size);
2909
2910 tx_ring->next_to_use = 0;
2911 tx_ring->next_to_clean = 0;
2912
2913 if (tx_ring->head)
2914 writel(0, adapter->hw.hw_addr + tx_ring->head);
2915 if (tx_ring->tail)
2916 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2917 }
2918
2919 /**
2920 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2921 * @adapter: board private structure
2922 **/
2923 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2924 {
2925 int i;
2926
2927 for (i = 0; i < adapter->num_rx_queues; i++)
2928 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2929 }
2930
2931 /**
2932 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2933 * @adapter: board private structure
2934 **/
2935 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2936 {
2937 int i;
2938
2939 for (i = 0; i < adapter->num_tx_queues; i++)
2940 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2941 }
2942
2943 void ixgbe_down(struct ixgbe_adapter *adapter)
2944 {
2945 struct net_device *netdev = adapter->netdev;
2946 struct ixgbe_hw *hw = &adapter->hw;
2947 u32 rxctrl;
2948 u32 txdctl;
2949 int i, j;
2950
2951 /* signal that we are down to the interrupt handler */
2952 set_bit(__IXGBE_DOWN, &adapter->state);
2953
2954 /* disable receives */
2955 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2956 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2957
2958 netif_tx_disable(netdev);
2959
2960 IXGBE_WRITE_FLUSH(hw);
2961 msleep(10);
2962
2963 netif_tx_stop_all_queues(netdev);
2964
2965 ixgbe_irq_disable(adapter);
2966
2967 ixgbe_napi_disable_all(adapter);
2968
2969 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2970 del_timer_sync(&adapter->sfp_timer);
2971 del_timer_sync(&adapter->watchdog_timer);
2972 cancel_work_sync(&adapter->watchdog_task);
2973
2974 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2975 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2976 cancel_work_sync(&adapter->fdir_reinit_task);
2977
2978 /* disable transmits in the hardware now that interrupts are off */
2979 for (i = 0; i < adapter->num_tx_queues; i++) {
2980 j = adapter->tx_ring[i].reg_idx;
2981 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2982 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2983 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2984 }
2985 /* Disable the Tx DMA engine on 82599 */
2986 if (hw->mac.type == ixgbe_mac_82599EB)
2987 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2988 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2989 ~IXGBE_DMATXCTL_TE));
2990
2991 netif_carrier_off(netdev);
2992
2993 if (!pci_channel_offline(adapter->pdev))
2994 ixgbe_reset(adapter);
2995 ixgbe_clean_all_tx_rings(adapter);
2996 ixgbe_clean_all_rx_rings(adapter);
2997
2998 #ifdef CONFIG_IXGBE_DCA
2999 /* since we reset the hardware DCA settings were cleared */
3000 ixgbe_setup_dca(adapter);
3001 #endif
3002 }
3003
3004 /**
3005 * ixgbe_poll - NAPI Rx polling callback
3006 * @napi: structure for representing this polling device
3007 * @budget: how many packets driver is allowed to clean
3008 *
3009 * This function is used for legacy and MSI, NAPI mode
3010 **/
3011 static int ixgbe_poll(struct napi_struct *napi, int budget)
3012 {
3013 struct ixgbe_q_vector *q_vector =
3014 container_of(napi, struct ixgbe_q_vector, napi);
3015 struct ixgbe_adapter *adapter = q_vector->adapter;
3016 int tx_clean_complete, work_done = 0;
3017
3018 #ifdef CONFIG_IXGBE_DCA
3019 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3020 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3021 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3022 }
3023 #endif
3024
3025 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3026 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3027
3028 if (!tx_clean_complete)
3029 work_done = budget;
3030
3031 /* If budget not fully consumed, exit the polling mode */
3032 if (work_done < budget) {
3033 napi_complete(napi);
3034 if (adapter->rx_itr_setting & 1)
3035 ixgbe_set_itr(adapter);
3036 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3037 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3038 }
3039 return work_done;
3040 }
3041
3042 /**
3043 * ixgbe_tx_timeout - Respond to a Tx Hang
3044 * @netdev: network interface device structure
3045 **/
3046 static void ixgbe_tx_timeout(struct net_device *netdev)
3047 {
3048 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3049
3050 /* Do the reset outside of interrupt context */
3051 schedule_work(&adapter->reset_task);
3052 }
3053
3054 static void ixgbe_reset_task(struct work_struct *work)
3055 {
3056 struct ixgbe_adapter *adapter;
3057 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3058
3059 /* If we're already down or resetting, just bail */
3060 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3061 test_bit(__IXGBE_RESETTING, &adapter->state))
3062 return;
3063
3064 adapter->tx_timeout_count++;
3065
3066 ixgbe_reinit_locked(adapter);
3067 }
3068
3069 #ifdef CONFIG_IXGBE_DCB
3070 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3071 {
3072 bool ret = false;
3073 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3074
3075 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3076 return ret;
3077
3078 f->mask = 0x7 << 3;
3079 adapter->num_rx_queues = f->indices;
3080 adapter->num_tx_queues = f->indices;
3081 ret = true;
3082
3083 return ret;
3084 }
3085 #endif
3086
3087 /**
3088 * ixgbe_set_rss_queues: Allocate queues for RSS
3089 * @adapter: board private structure to initialize
3090 *
3091 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3092 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3093 *
3094 **/
3095 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3096 {
3097 bool ret = false;
3098 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3099
3100 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3101 f->mask = 0xF;
3102 adapter->num_rx_queues = f->indices;
3103 adapter->num_tx_queues = f->indices;
3104 ret = true;
3105 } else {
3106 ret = false;
3107 }
3108
3109 return ret;
3110 }
3111
3112 /**
3113 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3114 * @adapter: board private structure to initialize
3115 *
3116 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3117 * to the original CPU that initiated the Tx session. This runs in addition
3118 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3119 * Rx load across CPUs using RSS.
3120 *
3121 **/
3122 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3123 {
3124 bool ret = false;
3125 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3126
3127 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3128 f_fdir->mask = 0;
3129
3130 /* Flow Director must have RSS enabled */
3131 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3132 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3133 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3134 adapter->num_tx_queues = f_fdir->indices;
3135 adapter->num_rx_queues = f_fdir->indices;
3136 ret = true;
3137 } else {
3138 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3139 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3140 }
3141 return ret;
3142 }
3143
3144 #ifdef IXGBE_FCOE
3145 /**
3146 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3147 * @adapter: board private structure to initialize
3148 *
3149 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3150 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3151 * rx queues out of the max number of rx queues, instead, it is used as the
3152 * index of the first rx queue used by FCoE.
3153 *
3154 **/
3155 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3156 {
3157 bool ret = false;
3158 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3159
3160 f->indices = min((int)num_online_cpus(), f->indices);
3161 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3162 adapter->num_rx_queues = 1;
3163 adapter->num_tx_queues = 1;
3164 #ifdef CONFIG_IXGBE_DCB
3165 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3166 DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3167 ixgbe_set_dcb_queues(adapter);
3168 }
3169 #endif
3170 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3171 DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3172 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3173 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3174 ixgbe_set_fdir_queues(adapter);
3175 else
3176 ixgbe_set_rss_queues(adapter);
3177 }
3178 /* adding FCoE rx rings to the end */
3179 f->mask = adapter->num_rx_queues;
3180 adapter->num_rx_queues += f->indices;
3181 adapter->num_tx_queues += f->indices;
3182
3183 ret = true;
3184 }
3185
3186 return ret;
3187 }
3188
3189 #endif /* IXGBE_FCOE */
3190 /*
3191 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3192 * @adapter: board private structure to initialize
3193 *
3194 * This is the top level queue allocation routine. The order here is very
3195 * important, starting with the "most" number of features turned on at once,
3196 * and ending with the smallest set of features. This way large combinations
3197 * can be allocated if they're turned on, and smaller combinations are the
3198 * fallthrough conditions.
3199 *
3200 **/
3201 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3202 {
3203 #ifdef IXGBE_FCOE
3204 if (ixgbe_set_fcoe_queues(adapter))
3205 goto done;
3206
3207 #endif /* IXGBE_FCOE */
3208 #ifdef CONFIG_IXGBE_DCB
3209 if (ixgbe_set_dcb_queues(adapter))
3210 goto done;
3211
3212 #endif
3213 if (ixgbe_set_fdir_queues(adapter))
3214 goto done;
3215
3216 if (ixgbe_set_rss_queues(adapter))
3217 goto done;
3218
3219 /* fallback to base case */
3220 adapter->num_rx_queues = 1;
3221 adapter->num_tx_queues = 1;
3222
3223 done:
3224 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3225 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3226 }
3227
3228 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3229 int vectors)
3230 {
3231 int err, vector_threshold;
3232
3233 /* We'll want at least 3 (vector_threshold):
3234 * 1) TxQ[0] Cleanup
3235 * 2) RxQ[0] Cleanup
3236 * 3) Other (Link Status Change, etc.)
3237 * 4) TCP Timer (optional)
3238 */
3239 vector_threshold = MIN_MSIX_COUNT;
3240
3241 /* The more we get, the more we will assign to Tx/Rx Cleanup
3242 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3243 * Right now, we simply care about how many we'll get; we'll
3244 * set them up later while requesting irq's.
3245 */
3246 while (vectors >= vector_threshold) {
3247 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3248 vectors);
3249 if (!err) /* Success in acquiring all requested vectors. */
3250 break;
3251 else if (err < 0)
3252 vectors = 0; /* Nasty failure, quit now */
3253 else /* err == number of vectors we should try again with */
3254 vectors = err;
3255 }
3256
3257 if (vectors < vector_threshold) {
3258 /* Can't allocate enough MSI-X interrupts? Oh well.
3259 * This just means we'll go with either a single MSI
3260 * vector or fall back to legacy interrupts.
3261 */
3262 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3263 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3264 kfree(adapter->msix_entries);
3265 adapter->msix_entries = NULL;
3266 } else {
3267 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3268 /*
3269 * Adjust for only the vectors we'll use, which is minimum
3270 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3271 * vectors we were allocated.
3272 */
3273 adapter->num_msix_vectors = min(vectors,
3274 adapter->max_msix_q_vectors + NON_Q_VECTORS);
3275 }
3276 }
3277
3278 /**
3279 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3280 * @adapter: board private structure to initialize
3281 *
3282 * Cache the descriptor ring offsets for RSS to the assigned rings.
3283 *
3284 **/
3285 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3286 {
3287 int i;
3288 bool ret = false;
3289
3290 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3291 for (i = 0; i < adapter->num_rx_queues; i++)
3292 adapter->rx_ring[i].reg_idx = i;
3293 for (i = 0; i < adapter->num_tx_queues; i++)
3294 adapter->tx_ring[i].reg_idx = i;
3295 ret = true;
3296 } else {
3297 ret = false;
3298 }
3299
3300 return ret;
3301 }
3302
3303 #ifdef CONFIG_IXGBE_DCB
3304 /**
3305 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3306 * @adapter: board private structure to initialize
3307 *
3308 * Cache the descriptor ring offsets for DCB to the assigned rings.
3309 *
3310 **/
3311 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3312 {
3313 int i;
3314 bool ret = false;
3315 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3316
3317 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3318 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3319 /* the number of queues is assumed to be symmetric */
3320 for (i = 0; i < dcb_i; i++) {
3321 adapter->rx_ring[i].reg_idx = i << 3;
3322 adapter->tx_ring[i].reg_idx = i << 2;
3323 }
3324 ret = true;
3325 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3326 if (dcb_i == 8) {
3327 /*
3328 * Tx TC0 starts at: descriptor queue 0
3329 * Tx TC1 starts at: descriptor queue 32
3330 * Tx TC2 starts at: descriptor queue 64
3331 * Tx TC3 starts at: descriptor queue 80
3332 * Tx TC4 starts at: descriptor queue 96
3333 * Tx TC5 starts at: descriptor queue 104
3334 * Tx TC6 starts at: descriptor queue 112
3335 * Tx TC7 starts at: descriptor queue 120
3336 *
3337 * Rx TC0-TC7 are offset by 16 queues each
3338 */
3339 for (i = 0; i < 3; i++) {
3340 adapter->tx_ring[i].reg_idx = i << 5;
3341 adapter->rx_ring[i].reg_idx = i << 4;
3342 }
3343 for ( ; i < 5; i++) {
3344 adapter->tx_ring[i].reg_idx =
3345 ((i + 2) << 4);
3346 adapter->rx_ring[i].reg_idx = i << 4;
3347 }
3348 for ( ; i < dcb_i; i++) {
3349 adapter->tx_ring[i].reg_idx =
3350 ((i + 8) << 3);
3351 adapter->rx_ring[i].reg_idx = i << 4;
3352 }
3353
3354 ret = true;
3355 } else if (dcb_i == 4) {
3356 /*
3357 * Tx TC0 starts at: descriptor queue 0
3358 * Tx TC1 starts at: descriptor queue 64
3359 * Tx TC2 starts at: descriptor queue 96
3360 * Tx TC3 starts at: descriptor queue 112
3361 *
3362 * Rx TC0-TC3 are offset by 32 queues each
3363 */
3364 adapter->tx_ring[0].reg_idx = 0;
3365 adapter->tx_ring[1].reg_idx = 64;
3366 adapter->tx_ring[2].reg_idx = 96;
3367 adapter->tx_ring[3].reg_idx = 112;
3368 for (i = 0 ; i < dcb_i; i++)
3369 adapter->rx_ring[i].reg_idx = i << 5;
3370
3371 ret = true;
3372 } else {
3373 ret = false;
3374 }
3375 } else {
3376 ret = false;
3377 }
3378 } else {
3379 ret = false;
3380 }
3381
3382 return ret;
3383 }
3384 #endif
3385
3386 /**
3387 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3388 * @adapter: board private structure to initialize
3389 *
3390 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3391 *
3392 **/
3393 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3394 {
3395 int i;
3396 bool ret = false;
3397
3398 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3399 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3400 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3401 for (i = 0; i < adapter->num_rx_queues; i++)
3402 adapter->rx_ring[i].reg_idx = i;
3403 for (i = 0; i < adapter->num_tx_queues; i++)
3404 adapter->tx_ring[i].reg_idx = i;
3405 ret = true;
3406 }
3407
3408 return ret;
3409 }
3410
3411 #ifdef IXGBE_FCOE
3412 /**
3413 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3414 * @adapter: board private structure to initialize
3415 *
3416 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3417 *
3418 */
3419 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3420 {
3421 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3422 bool ret = false;
3423 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3424
3425 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3426 #ifdef CONFIG_IXGBE_DCB
3427 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3428 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3429
3430 ixgbe_cache_ring_dcb(adapter);
3431 /* find out queues in TC for FCoE */
3432 fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3433 fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3434 /*
3435 * In 82599, the number of Tx queues for each traffic
3436 * class for both 8-TC and 4-TC modes are:
3437 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3438 * 8 TCs: 32 32 16 16 8 8 8 8
3439 * 4 TCs: 64 64 32 32
3440 * We have max 8 queues for FCoE, where 8 the is
3441 * FCoE redirection table size. If TC for FCoE is
3442 * less than or equal to TC3, we have enough queues
3443 * to add max of 8 queues for FCoE, so we start FCoE
3444 * tx descriptor from the next one, i.e., reg_idx + 1.
3445 * If TC for FCoE is above TC3, implying 8 TC mode,
3446 * and we need 8 for FCoE, we have to take all queues
3447 * in that traffic class for FCoE.
3448 */
3449 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3450 fcoe_tx_i--;
3451 }
3452 #endif /* CONFIG_IXGBE_DCB */
3453 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3454 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3455 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3456 ixgbe_cache_ring_fdir(adapter);
3457 else
3458 ixgbe_cache_ring_rss(adapter);
3459
3460 fcoe_rx_i = f->mask;
3461 fcoe_tx_i = f->mask;
3462 }
3463 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3464 adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3465 adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3466 }
3467 ret = true;
3468 }
3469 return ret;
3470 }
3471
3472 #endif /* IXGBE_FCOE */
3473 /**
3474 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3475 * @adapter: board private structure to initialize
3476 *
3477 * Once we know the feature-set enabled for the device, we'll cache
3478 * the register offset the descriptor ring is assigned to.
3479 *
3480 * Note, the order the various feature calls is important. It must start with
3481 * the "most" features enabled at the same time, then trickle down to the
3482 * least amount of features turned on at once.
3483 **/
3484 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3485 {
3486 /* start with default case */
3487 adapter->rx_ring[0].reg_idx = 0;
3488 adapter->tx_ring[0].reg_idx = 0;
3489
3490 #ifdef IXGBE_FCOE
3491 if (ixgbe_cache_ring_fcoe(adapter))
3492 return;
3493
3494 #endif /* IXGBE_FCOE */
3495 #ifdef CONFIG_IXGBE_DCB
3496 if (ixgbe_cache_ring_dcb(adapter))
3497 return;
3498
3499 #endif
3500 if (ixgbe_cache_ring_fdir(adapter))
3501 return;
3502
3503 if (ixgbe_cache_ring_rss(adapter))
3504 return;
3505 }
3506
3507 /**
3508 * ixgbe_alloc_queues - Allocate memory for all rings
3509 * @adapter: board private structure to initialize
3510 *
3511 * We allocate one ring per queue at run-time since we don't know the
3512 * number of queues at compile-time. The polling_netdev array is
3513 * intended for Multiqueue, but should work fine with a single queue.
3514 **/
3515 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3516 {
3517 int i;
3518
3519 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3520 sizeof(struct ixgbe_ring), GFP_KERNEL);
3521 if (!adapter->tx_ring)
3522 goto err_tx_ring_allocation;
3523
3524 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3525 sizeof(struct ixgbe_ring), GFP_KERNEL);
3526 if (!adapter->rx_ring)
3527 goto err_rx_ring_allocation;
3528
3529 for (i = 0; i < adapter->num_tx_queues; i++) {
3530 adapter->tx_ring[i].count = adapter->tx_ring_count;
3531 adapter->tx_ring[i].queue_index = i;
3532 }
3533
3534 for (i = 0; i < adapter->num_rx_queues; i++) {
3535 adapter->rx_ring[i].count = adapter->rx_ring_count;
3536 adapter->rx_ring[i].queue_index = i;
3537 }
3538
3539 ixgbe_cache_ring_register(adapter);
3540
3541 return 0;
3542
3543 err_rx_ring_allocation:
3544 kfree(adapter->tx_ring);
3545 err_tx_ring_allocation:
3546 return -ENOMEM;
3547 }
3548
3549 /**
3550 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3551 * @adapter: board private structure to initialize
3552 *
3553 * Attempt to configure the interrupts using the best available
3554 * capabilities of the hardware and the kernel.
3555 **/
3556 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3557 {
3558 struct ixgbe_hw *hw = &adapter->hw;
3559 int err = 0;
3560 int vector, v_budget;
3561
3562 /*
3563 * It's easy to be greedy for MSI-X vectors, but it really
3564 * doesn't do us much good if we have a lot more vectors
3565 * than CPU's. So let's be conservative and only ask for
3566 * (roughly) twice the number of vectors as there are CPU's.
3567 */
3568 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3569 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3570
3571 /*
3572 * At the same time, hardware can only support a maximum of
3573 * hw.mac->max_msix_vectors vectors. With features
3574 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3575 * descriptor queues supported by our device. Thus, we cap it off in
3576 * those rare cases where the cpu count also exceeds our vector limit.
3577 */
3578 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3579
3580 /* A failure in MSI-X entry allocation isn't fatal, but it does
3581 * mean we disable MSI-X capabilities of the adapter. */
3582 adapter->msix_entries = kcalloc(v_budget,
3583 sizeof(struct msix_entry), GFP_KERNEL);
3584 if (adapter->msix_entries) {
3585 for (vector = 0; vector < v_budget; vector++)
3586 adapter->msix_entries[vector].entry = vector;
3587
3588 ixgbe_acquire_msix_vectors(adapter, v_budget);
3589
3590 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3591 goto out;
3592 }
3593
3594 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3595 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3596 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3597 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3598 adapter->atr_sample_rate = 0;
3599 ixgbe_set_num_queues(adapter);
3600
3601 err = pci_enable_msi(adapter->pdev);
3602 if (!err) {
3603 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3604 } else {
3605 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3606 "falling back to legacy. Error: %d\n", err);
3607 /* reset err */
3608 err = 0;
3609 }
3610
3611 out:
3612 return err;
3613 }
3614
3615 /**
3616 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3617 * @adapter: board private structure to initialize
3618 *
3619 * We allocate one q_vector per queue interrupt. If allocation fails we
3620 * return -ENOMEM.
3621 **/
3622 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3623 {
3624 int q_idx, num_q_vectors;
3625 struct ixgbe_q_vector *q_vector;
3626 int napi_vectors;
3627 int (*poll)(struct napi_struct *, int);
3628
3629 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3630 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3631 napi_vectors = adapter->num_rx_queues;
3632 poll = &ixgbe_clean_rxtx_many;
3633 } else {
3634 num_q_vectors = 1;
3635 napi_vectors = 1;
3636 poll = &ixgbe_poll;
3637 }
3638
3639 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3640 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3641 if (!q_vector)
3642 goto err_out;
3643 q_vector->adapter = adapter;
3644 if (q_vector->txr_count && !q_vector->rxr_count)
3645 q_vector->eitr = adapter->tx_eitr_param;
3646 else
3647 q_vector->eitr = adapter->rx_eitr_param;
3648 q_vector->v_idx = q_idx;
3649 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3650 adapter->q_vector[q_idx] = q_vector;
3651 }
3652
3653 return 0;
3654
3655 err_out:
3656 while (q_idx) {
3657 q_idx--;
3658 q_vector = adapter->q_vector[q_idx];
3659 netif_napi_del(&q_vector->napi);
3660 kfree(q_vector);
3661 adapter->q_vector[q_idx] = NULL;
3662 }
3663 return -ENOMEM;
3664 }
3665
3666 /**
3667 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3668 * @adapter: board private structure to initialize
3669 *
3670 * This function frees the memory allocated to the q_vectors. In addition if
3671 * NAPI is enabled it will delete any references to the NAPI struct prior
3672 * to freeing the q_vector.
3673 **/
3674 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3675 {
3676 int q_idx, num_q_vectors;
3677
3678 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3679 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3680 else
3681 num_q_vectors = 1;
3682
3683 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3684 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3685 adapter->q_vector[q_idx] = NULL;
3686 netif_napi_del(&q_vector->napi);
3687 kfree(q_vector);
3688 }
3689 }
3690
3691 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3692 {
3693 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3694 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3695 pci_disable_msix(adapter->pdev);
3696 kfree(adapter->msix_entries);
3697 adapter->msix_entries = NULL;
3698 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3699 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3700 pci_disable_msi(adapter->pdev);
3701 }
3702 return;
3703 }
3704
3705 /**
3706 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3707 * @adapter: board private structure to initialize
3708 *
3709 * We determine which interrupt scheme to use based on...
3710 * - Kernel support (MSI, MSI-X)
3711 * - which can be user-defined (via MODULE_PARAM)
3712 * - Hardware queue count (num_*_queues)
3713 * - defined by miscellaneous hardware support/features (RSS, etc.)
3714 **/
3715 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3716 {
3717 int err;
3718
3719 /* Number of supported queues */
3720 ixgbe_set_num_queues(adapter);
3721
3722 err = ixgbe_set_interrupt_capability(adapter);
3723 if (err) {
3724 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3725 goto err_set_interrupt;
3726 }
3727
3728 err = ixgbe_alloc_q_vectors(adapter);
3729 if (err) {
3730 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3731 "vectors\n");
3732 goto err_alloc_q_vectors;
3733 }
3734
3735 err = ixgbe_alloc_queues(adapter);
3736 if (err) {
3737 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3738 goto err_alloc_queues;
3739 }
3740
3741 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3742 "Tx Queue count = %u\n",
3743 (adapter->num_rx_queues > 1) ? "Enabled" :
3744 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3745
3746 set_bit(__IXGBE_DOWN, &adapter->state);
3747
3748 return 0;
3749
3750 err_alloc_queues:
3751 ixgbe_free_q_vectors(adapter);
3752 err_alloc_q_vectors:
3753 ixgbe_reset_interrupt_capability(adapter);
3754 err_set_interrupt:
3755 return err;
3756 }
3757
3758 /**
3759 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3760 * @adapter: board private structure to clear interrupt scheme on
3761 *
3762 * We go through and clear interrupt specific resources and reset the structure
3763 * to pre-load conditions
3764 **/
3765 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3766 {
3767 kfree(adapter->tx_ring);
3768 kfree(adapter->rx_ring);
3769 adapter->tx_ring = NULL;
3770 adapter->rx_ring = NULL;
3771
3772 ixgbe_free_q_vectors(adapter);
3773 ixgbe_reset_interrupt_capability(adapter);
3774 }
3775
3776 /**
3777 * ixgbe_sfp_timer - worker thread to find a missing module
3778 * @data: pointer to our adapter struct
3779 **/
3780 static void ixgbe_sfp_timer(unsigned long data)
3781 {
3782 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3783
3784 /*
3785 * Do the sfp_timer outside of interrupt context due to the
3786 * delays that sfp+ detection requires
3787 */
3788 schedule_work(&adapter->sfp_task);
3789 }
3790
3791 /**
3792 * ixgbe_sfp_task - worker thread to find a missing module
3793 * @work: pointer to work_struct containing our data
3794 **/
3795 static void ixgbe_sfp_task(struct work_struct *work)
3796 {
3797 struct ixgbe_adapter *adapter = container_of(work,
3798 struct ixgbe_adapter,
3799 sfp_task);
3800 struct ixgbe_hw *hw = &adapter->hw;
3801
3802 if ((hw->phy.type == ixgbe_phy_nl) &&
3803 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3804 s32 ret = hw->phy.ops.identify_sfp(hw);
3805 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3806 goto reschedule;
3807 ret = hw->phy.ops.reset(hw);
3808 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3809 dev_err(&adapter->pdev->dev, "failed to initialize "
3810 "because an unsupported SFP+ module type "
3811 "was detected.\n"
3812 "Reload the driver after installing a "
3813 "supported module.\n");
3814 unregister_netdev(adapter->netdev);
3815 } else {
3816 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3817 hw->phy.sfp_type);
3818 }
3819 /* don't need this routine any more */
3820 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3821 }
3822 return;
3823 reschedule:
3824 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3825 mod_timer(&adapter->sfp_timer,
3826 round_jiffies(jiffies + (2 * HZ)));
3827 }
3828
3829 /**
3830 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3831 * @adapter: board private structure to initialize
3832 *
3833 * ixgbe_sw_init initializes the Adapter private data structure.
3834 * Fields are initialized based on PCI device information and
3835 * OS network device settings (MTU size).
3836 **/
3837 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3838 {
3839 struct ixgbe_hw *hw = &adapter->hw;
3840 struct pci_dev *pdev = adapter->pdev;
3841 unsigned int rss;
3842 #ifdef CONFIG_IXGBE_DCB
3843 int j;
3844 struct tc_configuration *tc;
3845 #endif
3846
3847 /* PCI config space info */
3848
3849 hw->vendor_id = pdev->vendor;
3850 hw->device_id = pdev->device;
3851 hw->revision_id = pdev->revision;
3852 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3853 hw->subsystem_device_id = pdev->subsystem_device;
3854
3855 /* Set capability flags */
3856 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3857 adapter->ring_feature[RING_F_RSS].indices = rss;
3858 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3859 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3860 if (hw->mac.type == ixgbe_mac_82598EB) {
3861 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3862 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3863 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3864 } else if (hw->mac.type == ixgbe_mac_82599EB) {
3865 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3866 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3867 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3868 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3869 adapter->ring_feature[RING_F_FDIR].indices =
3870 IXGBE_MAX_FDIR_INDICES;
3871 adapter->atr_sample_rate = 20;
3872 adapter->fdir_pballoc = 0;
3873 #ifdef IXGBE_FCOE
3874 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3875 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3876 adapter->ring_feature[RING_F_FCOE].indices = 0;
3877 /* Default traffic class to use for FCoE */
3878 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3879 #endif /* IXGBE_FCOE */
3880 }
3881
3882 #ifdef CONFIG_IXGBE_DCB
3883 /* Configure DCB traffic classes */
3884 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3885 tc = &adapter->dcb_cfg.tc_config[j];
3886 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3887 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3888 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3889 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3890 tc->dcb_pfc = pfc_disabled;
3891 }
3892 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3893 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3894 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3895 adapter->dcb_cfg.pfc_mode_enable = false;
3896 adapter->dcb_cfg.round_robin_enable = false;
3897 adapter->dcb_set_bitmap = 0x00;
3898 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3899 adapter->ring_feature[RING_F_DCB].indices);
3900
3901 #endif
3902
3903 /* default flow control settings */
3904 hw->fc.requested_mode = ixgbe_fc_full;
3905 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
3906 #ifdef CONFIG_DCB
3907 adapter->last_lfc_mode = hw->fc.current_mode;
3908 #endif
3909 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3910 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3911 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3912 hw->fc.send_xon = true;
3913 hw->fc.disable_fc_autoneg = false;
3914
3915 /* enable itr by default in dynamic mode */
3916 adapter->rx_itr_setting = 1;
3917 adapter->rx_eitr_param = 20000;
3918 adapter->tx_itr_setting = 1;
3919 adapter->tx_eitr_param = 10000;
3920
3921 /* set defaults for eitr in MegaBytes */
3922 adapter->eitr_low = 10;
3923 adapter->eitr_high = 20;
3924
3925 /* set default ring sizes */
3926 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3927 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3928
3929 /* initialize eeprom parameters */
3930 if (ixgbe_init_eeprom_params_generic(hw)) {
3931 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3932 return -EIO;
3933 }
3934
3935 /* enable rx csum by default */
3936 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3937
3938 set_bit(__IXGBE_DOWN, &adapter->state);
3939
3940 return 0;
3941 }
3942
3943 /**
3944 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3945 * @adapter: board private structure
3946 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3947 *
3948 * Return 0 on success, negative on failure
3949 **/
3950 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3951 struct ixgbe_ring *tx_ring)
3952 {
3953 struct pci_dev *pdev = adapter->pdev;
3954 int size;
3955
3956 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3957 tx_ring->tx_buffer_info = vmalloc(size);
3958 if (!tx_ring->tx_buffer_info)
3959 goto err;
3960 memset(tx_ring->tx_buffer_info, 0, size);
3961
3962 /* round up to nearest 4K */
3963 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3964 tx_ring->size = ALIGN(tx_ring->size, 4096);
3965
3966 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3967 &tx_ring->dma);
3968 if (!tx_ring->desc)
3969 goto err;
3970
3971 tx_ring->next_to_use = 0;
3972 tx_ring->next_to_clean = 0;
3973 tx_ring->work_limit = tx_ring->count;
3974 return 0;
3975
3976 err:
3977 vfree(tx_ring->tx_buffer_info);
3978 tx_ring->tx_buffer_info = NULL;
3979 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3980 "descriptor ring\n");
3981 return -ENOMEM;
3982 }
3983
3984 /**
3985 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3986 * @adapter: board private structure
3987 *
3988 * If this function returns with an error, then it's possible one or
3989 * more of the rings is populated (while the rest are not). It is the
3990 * callers duty to clean those orphaned rings.
3991 *
3992 * Return 0 on success, negative on failure
3993 **/
3994 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3995 {
3996 int i, err = 0;
3997
3998 for (i = 0; i < adapter->num_tx_queues; i++) {
3999 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4000 if (!err)
4001 continue;
4002 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4003 break;
4004 }
4005
4006 return err;
4007 }
4008
4009 /**
4010 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4011 * @adapter: board private structure
4012 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4013 *
4014 * Returns 0 on success, negative on failure
4015 **/
4016 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4017 struct ixgbe_ring *rx_ring)
4018 {
4019 struct pci_dev *pdev = adapter->pdev;
4020 int size;
4021
4022 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4023 rx_ring->rx_buffer_info = vmalloc(size);
4024 if (!rx_ring->rx_buffer_info) {
4025 DPRINTK(PROBE, ERR,
4026 "vmalloc allocation failed for the rx desc ring\n");
4027 goto alloc_failed;
4028 }
4029 memset(rx_ring->rx_buffer_info, 0, size);
4030
4031 /* Round up to nearest 4K */
4032 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4033 rx_ring->size = ALIGN(rx_ring->size, 4096);
4034
4035 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4036
4037 if (!rx_ring->desc) {
4038 DPRINTK(PROBE, ERR,
4039 "Memory allocation failed for the rx desc ring\n");
4040 vfree(rx_ring->rx_buffer_info);
4041 goto alloc_failed;
4042 }
4043
4044 rx_ring->next_to_clean = 0;
4045 rx_ring->next_to_use = 0;
4046
4047 return 0;
4048
4049 alloc_failed:
4050 return -ENOMEM;
4051 }
4052
4053 /**
4054 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4055 * @adapter: board private structure
4056 *
4057 * If this function returns with an error, then it's possible one or
4058 * more of the rings is populated (while the rest are not). It is the
4059 * callers duty to clean those orphaned rings.
4060 *
4061 * Return 0 on success, negative on failure
4062 **/
4063
4064 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4065 {
4066 int i, err = 0;
4067
4068 for (i = 0; i < adapter->num_rx_queues; i++) {
4069 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4070 if (!err)
4071 continue;
4072 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4073 break;
4074 }
4075
4076 return err;
4077 }
4078
4079 /**
4080 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4081 * @adapter: board private structure
4082 * @tx_ring: Tx descriptor ring for a specific queue
4083 *
4084 * Free all transmit software resources
4085 **/
4086 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4087 struct ixgbe_ring *tx_ring)
4088 {
4089 struct pci_dev *pdev = adapter->pdev;
4090
4091 ixgbe_clean_tx_ring(adapter, tx_ring);
4092
4093 vfree(tx_ring->tx_buffer_info);
4094 tx_ring->tx_buffer_info = NULL;
4095
4096 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4097
4098 tx_ring->desc = NULL;
4099 }
4100
4101 /**
4102 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4103 * @adapter: board private structure
4104 *
4105 * Free all transmit software resources
4106 **/
4107 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4108 {
4109 int i;
4110
4111 for (i = 0; i < adapter->num_tx_queues; i++)
4112 if (adapter->tx_ring[i].desc)
4113 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4114 }
4115
4116 /**
4117 * ixgbe_free_rx_resources - Free Rx Resources
4118 * @adapter: board private structure
4119 * @rx_ring: ring to clean the resources from
4120 *
4121 * Free all receive software resources
4122 **/
4123 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4124 struct ixgbe_ring *rx_ring)
4125 {
4126 struct pci_dev *pdev = adapter->pdev;
4127
4128 ixgbe_clean_rx_ring(adapter, rx_ring);
4129
4130 vfree(rx_ring->rx_buffer_info);
4131 rx_ring->rx_buffer_info = NULL;
4132
4133 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4134
4135 rx_ring->desc = NULL;
4136 }
4137
4138 /**
4139 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4140 * @adapter: board private structure
4141 *
4142 * Free all receive software resources
4143 **/
4144 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4145 {
4146 int i;
4147
4148 for (i = 0; i < adapter->num_rx_queues; i++)
4149 if (adapter->rx_ring[i].desc)
4150 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4151 }
4152
4153 /**
4154 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4155 * @netdev: network interface device structure
4156 * @new_mtu: new value for maximum frame size
4157 *
4158 * Returns 0 on success, negative on failure
4159 **/
4160 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4161 {
4162 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4163 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4164
4165 /* MTU < 68 is an error and causes problems on some kernels */
4166 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4167 return -EINVAL;
4168
4169 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4170 netdev->mtu, new_mtu);
4171 /* must set new MTU before calling down or up */
4172 netdev->mtu = new_mtu;
4173
4174 if (netif_running(netdev))
4175 ixgbe_reinit_locked(adapter);
4176
4177 return 0;
4178 }
4179
4180 /**
4181 * ixgbe_open - Called when a network interface is made active
4182 * @netdev: network interface device structure
4183 *
4184 * Returns 0 on success, negative value on failure
4185 *
4186 * The open entry point is called when a network interface is made
4187 * active by the system (IFF_UP). At this point all resources needed
4188 * for transmit and receive operations are allocated, the interrupt
4189 * handler is registered with the OS, the watchdog timer is started,
4190 * and the stack is notified that the interface is ready.
4191 **/
4192 static int ixgbe_open(struct net_device *netdev)
4193 {
4194 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4195 int err;
4196
4197 /* disallow open during test */
4198 if (test_bit(__IXGBE_TESTING, &adapter->state))
4199 return -EBUSY;
4200
4201 netif_carrier_off(netdev);
4202
4203 /* allocate transmit descriptors */
4204 err = ixgbe_setup_all_tx_resources(adapter);
4205 if (err)
4206 goto err_setup_tx;
4207
4208 /* allocate receive descriptors */
4209 err = ixgbe_setup_all_rx_resources(adapter);
4210 if (err)
4211 goto err_setup_rx;
4212
4213 ixgbe_configure(adapter);
4214
4215 err = ixgbe_request_irq(adapter);
4216 if (err)
4217 goto err_req_irq;
4218
4219 err = ixgbe_up_complete(adapter);
4220 if (err)
4221 goto err_up;
4222
4223 netif_tx_start_all_queues(netdev);
4224
4225 return 0;
4226
4227 err_up:
4228 ixgbe_release_hw_control(adapter);
4229 ixgbe_free_irq(adapter);
4230 err_req_irq:
4231 err_setup_rx:
4232 ixgbe_free_all_rx_resources(adapter);
4233 err_setup_tx:
4234 ixgbe_free_all_tx_resources(adapter);
4235 ixgbe_reset(adapter);
4236
4237 return err;
4238 }
4239
4240 /**
4241 * ixgbe_close - Disables a network interface
4242 * @netdev: network interface device structure
4243 *
4244 * Returns 0, this is not allowed to fail
4245 *
4246 * The close entry point is called when an interface is de-activated
4247 * by the OS. The hardware is still under the drivers control, but
4248 * needs to be disabled. A global MAC reset is issued to stop the
4249 * hardware, and all transmit and receive resources are freed.
4250 **/
4251 static int ixgbe_close(struct net_device *netdev)
4252 {
4253 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4254
4255 ixgbe_down(adapter);
4256 ixgbe_free_irq(adapter);
4257
4258 ixgbe_free_all_tx_resources(adapter);
4259 ixgbe_free_all_rx_resources(adapter);
4260
4261 ixgbe_release_hw_control(adapter);
4262
4263 return 0;
4264 }
4265
4266 #ifdef CONFIG_PM
4267 static int ixgbe_resume(struct pci_dev *pdev)
4268 {
4269 struct net_device *netdev = pci_get_drvdata(pdev);
4270 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4271 u32 err;
4272
4273 pci_set_power_state(pdev, PCI_D0);
4274 pci_restore_state(pdev);
4275
4276 err = pci_enable_device_mem(pdev);
4277 if (err) {
4278 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4279 "suspend\n");
4280 return err;
4281 }
4282 pci_set_master(pdev);
4283
4284 pci_wake_from_d3(pdev, false);
4285
4286 err = ixgbe_init_interrupt_scheme(adapter);
4287 if (err) {
4288 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4289 "device\n");
4290 return err;
4291 }
4292
4293 ixgbe_reset(adapter);
4294
4295 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4296
4297 if (netif_running(netdev)) {
4298 err = ixgbe_open(adapter->netdev);
4299 if (err)
4300 return err;
4301 }
4302
4303 netif_device_attach(netdev);
4304
4305 return 0;
4306 }
4307 #endif /* CONFIG_PM */
4308
4309 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4310 {
4311 struct net_device *netdev = pci_get_drvdata(pdev);
4312 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4313 struct ixgbe_hw *hw = &adapter->hw;
4314 u32 ctrl, fctrl;
4315 u32 wufc = adapter->wol;
4316 #ifdef CONFIG_PM
4317 int retval = 0;
4318 #endif
4319
4320 netif_device_detach(netdev);
4321
4322 if (netif_running(netdev)) {
4323 ixgbe_down(adapter);
4324 ixgbe_free_irq(adapter);
4325 ixgbe_free_all_tx_resources(adapter);
4326 ixgbe_free_all_rx_resources(adapter);
4327 }
4328 ixgbe_clear_interrupt_scheme(adapter);
4329
4330 #ifdef CONFIG_PM
4331 retval = pci_save_state(pdev);
4332 if (retval)
4333 return retval;
4334
4335 #endif
4336 if (wufc) {
4337 ixgbe_set_rx_mode(netdev);
4338
4339 /* turn on all-multi mode if wake on multicast is enabled */
4340 if (wufc & IXGBE_WUFC_MC) {
4341 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4342 fctrl |= IXGBE_FCTRL_MPE;
4343 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4344 }
4345
4346 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4347 ctrl |= IXGBE_CTRL_GIO_DIS;
4348 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4349
4350 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4351 } else {
4352 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4353 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4354 }
4355
4356 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4357 pci_wake_from_d3(pdev, true);
4358 else
4359 pci_wake_from_d3(pdev, false);
4360
4361 *enable_wake = !!wufc;
4362
4363 ixgbe_release_hw_control(adapter);
4364
4365 pci_disable_device(pdev);
4366
4367 return 0;
4368 }
4369
4370 #ifdef CONFIG_PM
4371 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4372 {
4373 int retval;
4374 bool wake;
4375
4376 retval = __ixgbe_shutdown(pdev, &wake);
4377 if (retval)
4378 return retval;
4379
4380 if (wake) {
4381 pci_prepare_to_sleep(pdev);
4382 } else {
4383 pci_wake_from_d3(pdev, false);
4384 pci_set_power_state(pdev, PCI_D3hot);
4385 }
4386
4387 return 0;
4388 }
4389 #endif /* CONFIG_PM */
4390
4391 static void ixgbe_shutdown(struct pci_dev *pdev)
4392 {
4393 bool wake;
4394
4395 __ixgbe_shutdown(pdev, &wake);
4396
4397 if (system_state == SYSTEM_POWER_OFF) {
4398 pci_wake_from_d3(pdev, wake);
4399 pci_set_power_state(pdev, PCI_D3hot);
4400 }
4401 }
4402
4403 /**
4404 * ixgbe_update_stats - Update the board statistics counters.
4405 * @adapter: board private structure
4406 **/
4407 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4408 {
4409 struct net_device *netdev = adapter->netdev;
4410 struct ixgbe_hw *hw = &adapter->hw;
4411 u64 total_mpc = 0;
4412 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4413
4414 if (hw->mac.type == ixgbe_mac_82599EB) {
4415 u64 rsc_count = 0;
4416 for (i = 0; i < 16; i++)
4417 adapter->hw_rx_no_dma_resources +=
4418 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4419 for (i = 0; i < adapter->num_rx_queues; i++)
4420 rsc_count += adapter->rx_ring[i].rsc_count;
4421 adapter->rsc_count = rsc_count;
4422 }
4423
4424 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4425 for (i = 0; i < 8; i++) {
4426 /* for packet buffers not used, the register should read 0 */
4427 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4428 missed_rx += mpc;
4429 adapter->stats.mpc[i] += mpc;
4430 total_mpc += adapter->stats.mpc[i];
4431 if (hw->mac.type == ixgbe_mac_82598EB)
4432 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4433 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4434 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4435 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4436 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4437 if (hw->mac.type == ixgbe_mac_82599EB) {
4438 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4439 IXGBE_PXONRXCNT(i));
4440 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4441 IXGBE_PXOFFRXCNT(i));
4442 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4443 } else {
4444 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4445 IXGBE_PXONRXC(i));
4446 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4447 IXGBE_PXOFFRXC(i));
4448 }
4449 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4450 IXGBE_PXONTXC(i));
4451 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4452 IXGBE_PXOFFTXC(i));
4453 }
4454 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4455 /* work around hardware counting issue */
4456 adapter->stats.gprc -= missed_rx;
4457
4458 /* 82598 hardware only has a 32 bit counter in the high register */
4459 if (hw->mac.type == ixgbe_mac_82599EB) {
4460 u64 tmp;
4461 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4462 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4463 adapter->stats.gorc += (tmp << 32);
4464 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4465 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4466 adapter->stats.gotc += (tmp << 32);
4467 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4468 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4469 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4470 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4471 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4472 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4473 #ifdef IXGBE_FCOE
4474 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4475 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4476 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4477 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4478 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4479 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4480 #endif /* IXGBE_FCOE */
4481 } else {
4482 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4483 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4484 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4485 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4486 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4487 }
4488 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4489 adapter->stats.bprc += bprc;
4490 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4491 if (hw->mac.type == ixgbe_mac_82598EB)
4492 adapter->stats.mprc -= bprc;
4493 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4494 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4495 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4496 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4497 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4498 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4499 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4500 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4501 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4502 adapter->stats.lxontxc += lxon;
4503 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4504 adapter->stats.lxofftxc += lxoff;
4505 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4506 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4507 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4508 /*
4509 * 82598 errata - tx of flow control packets is included in tx counters
4510 */
4511 xon_off_tot = lxon + lxoff;
4512 adapter->stats.gptc -= xon_off_tot;
4513 adapter->stats.mptc -= xon_off_tot;
4514 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4515 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4516 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4517 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4518 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4519 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4520 adapter->stats.ptc64 -= xon_off_tot;
4521 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4522 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4523 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4524 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4525 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4526 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4527
4528 /* Fill out the OS statistics structure */
4529 netdev->stats.multicast = adapter->stats.mprc;
4530
4531 /* Rx Errors */
4532 netdev->stats.rx_errors = adapter->stats.crcerrs +
4533 adapter->stats.rlec;
4534 netdev->stats.rx_dropped = 0;
4535 netdev->stats.rx_length_errors = adapter->stats.rlec;
4536 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4537 netdev->stats.rx_missed_errors = total_mpc;
4538 }
4539
4540 /**
4541 * ixgbe_watchdog - Timer Call-back
4542 * @data: pointer to adapter cast into an unsigned long
4543 **/
4544 static void ixgbe_watchdog(unsigned long data)
4545 {
4546 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4547 struct ixgbe_hw *hw = &adapter->hw;
4548 u64 eics = 0;
4549 int i;
4550
4551 /*
4552 * Do the watchdog outside of interrupt context due to the lovely
4553 * delays that some of the newer hardware requires
4554 */
4555
4556 if (test_bit(__IXGBE_DOWN, &adapter->state))
4557 goto watchdog_short_circuit;
4558
4559 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4560 /*
4561 * for legacy and MSI interrupts don't set any bits
4562 * that are enabled for EIAM, because this operation
4563 * would set *both* EIMS and EICS for any bit in EIAM
4564 */
4565 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4566 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4567 goto watchdog_reschedule;
4568 }
4569
4570 /* get one bit for every active tx/rx interrupt vector */
4571 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4572 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4573 if (qv->rxr_count || qv->txr_count)
4574 eics |= ((u64)1 << i);
4575 }
4576
4577 /* Cause software interrupt to ensure rx rings are cleaned */
4578 ixgbe_irq_rearm_queues(adapter, eics);
4579
4580 watchdog_reschedule:
4581 /* Reset the timer */
4582 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4583
4584 watchdog_short_circuit:
4585 schedule_work(&adapter->watchdog_task);
4586 }
4587
4588 /**
4589 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4590 * @work: pointer to work_struct containing our data
4591 **/
4592 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4593 {
4594 struct ixgbe_adapter *adapter = container_of(work,
4595 struct ixgbe_adapter,
4596 multispeed_fiber_task);
4597 struct ixgbe_hw *hw = &adapter->hw;
4598 u32 autoneg;
4599 bool negotiation;
4600
4601 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4602 autoneg = hw->phy.autoneg_advertised;
4603 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4604 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4605 if (hw->mac.ops.setup_link)
4606 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4607 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4608 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4609 }
4610
4611 /**
4612 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4613 * @work: pointer to work_struct containing our data
4614 **/
4615 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4616 {
4617 struct ixgbe_adapter *adapter = container_of(work,
4618 struct ixgbe_adapter,
4619 sfp_config_module_task);
4620 struct ixgbe_hw *hw = &adapter->hw;
4621 u32 err;
4622
4623 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4624
4625 /* Time for electrical oscillations to settle down */
4626 msleep(100);
4627 err = hw->phy.ops.identify_sfp(hw);
4628
4629 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4630 dev_err(&adapter->pdev->dev, "failed to initialize because "
4631 "an unsupported SFP+ module type was detected.\n"
4632 "Reload the driver after installing a supported "
4633 "module.\n");
4634 unregister_netdev(adapter->netdev);
4635 return;
4636 }
4637 hw->mac.ops.setup_sfp(hw);
4638
4639 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4640 /* This will also work for DA Twinax connections */
4641 schedule_work(&adapter->multispeed_fiber_task);
4642 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4643 }
4644
4645 /**
4646 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4647 * @work: pointer to work_struct containing our data
4648 **/
4649 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4650 {
4651 struct ixgbe_adapter *adapter = container_of(work,
4652 struct ixgbe_adapter,
4653 fdir_reinit_task);
4654 struct ixgbe_hw *hw = &adapter->hw;
4655 int i;
4656
4657 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4658 for (i = 0; i < adapter->num_tx_queues; i++)
4659 set_bit(__IXGBE_FDIR_INIT_DONE,
4660 &(adapter->tx_ring[i].reinit_state));
4661 } else {
4662 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4663 "ignored adding FDIR ATR filters \n");
4664 }
4665 /* Done FDIR Re-initialization, enable transmits */
4666 netif_tx_start_all_queues(adapter->netdev);
4667 }
4668
4669 /**
4670 * ixgbe_watchdog_task - worker thread to bring link up
4671 * @work: pointer to work_struct containing our data
4672 **/
4673 static void ixgbe_watchdog_task(struct work_struct *work)
4674 {
4675 struct ixgbe_adapter *adapter = container_of(work,
4676 struct ixgbe_adapter,
4677 watchdog_task);
4678 struct net_device *netdev = adapter->netdev;
4679 struct ixgbe_hw *hw = &adapter->hw;
4680 u32 link_speed = adapter->link_speed;
4681 bool link_up = adapter->link_up;
4682 int i;
4683 struct ixgbe_ring *tx_ring;
4684 int some_tx_pending = 0;
4685
4686 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4687
4688 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4689 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4690 if (link_up) {
4691 #ifdef CONFIG_DCB
4692 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4693 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4694 hw->mac.ops.fc_enable(hw, i);
4695 } else {
4696 hw->mac.ops.fc_enable(hw, 0);
4697 }
4698 #else
4699 hw->mac.ops.fc_enable(hw, 0);
4700 #endif
4701 }
4702
4703 if (link_up ||
4704 time_after(jiffies, (adapter->link_check_timeout +
4705 IXGBE_TRY_LINK_TIMEOUT))) {
4706 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4707 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4708 }
4709 adapter->link_up = link_up;
4710 adapter->link_speed = link_speed;
4711 }
4712
4713 if (link_up) {
4714 if (!netif_carrier_ok(netdev)) {
4715 bool flow_rx, flow_tx;
4716
4717 if (hw->mac.type == ixgbe_mac_82599EB) {
4718 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4719 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4720 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4721 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4722 } else {
4723 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4724 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4725 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4726 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4727 }
4728
4729 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4730 "Flow Control: %s\n",
4731 netdev->name,
4732 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4733 "10 Gbps" :
4734 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4735 "1 Gbps" : "unknown speed")),
4736 ((flow_rx && flow_tx) ? "RX/TX" :
4737 (flow_rx ? "RX" :
4738 (flow_tx ? "TX" : "None"))));
4739
4740 netif_carrier_on(netdev);
4741 } else {
4742 /* Force detection of hung controller */
4743 adapter->detect_tx_hung = true;
4744 }
4745 } else {
4746 adapter->link_up = false;
4747 adapter->link_speed = 0;
4748 if (netif_carrier_ok(netdev)) {
4749 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4750 netdev->name);
4751 netif_carrier_off(netdev);
4752 }
4753 }
4754
4755 if (!netif_carrier_ok(netdev)) {
4756 for (i = 0; i < adapter->num_tx_queues; i++) {
4757 tx_ring = &adapter->tx_ring[i];
4758 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4759 some_tx_pending = 1;
4760 break;
4761 }
4762 }
4763
4764 if (some_tx_pending) {
4765 /* We've lost link, so the controller stops DMA,
4766 * but we've got queued Tx work that's never going
4767 * to get done, so reset controller to flush Tx.
4768 * (Do the reset outside of interrupt context).
4769 */
4770 schedule_work(&adapter->reset_task);
4771 }
4772 }
4773
4774 ixgbe_update_stats(adapter);
4775 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4776 }
4777
4778 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4779 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4780 u32 tx_flags, u8 *hdr_len)
4781 {
4782 struct ixgbe_adv_tx_context_desc *context_desc;
4783 unsigned int i;
4784 int err;
4785 struct ixgbe_tx_buffer *tx_buffer_info;
4786 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4787 u32 mss_l4len_idx, l4len;
4788
4789 if (skb_is_gso(skb)) {
4790 if (skb_header_cloned(skb)) {
4791 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4792 if (err)
4793 return err;
4794 }
4795 l4len = tcp_hdrlen(skb);
4796 *hdr_len += l4len;
4797
4798 if (skb->protocol == htons(ETH_P_IP)) {
4799 struct iphdr *iph = ip_hdr(skb);
4800 iph->tot_len = 0;
4801 iph->check = 0;
4802 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4803 iph->daddr, 0,
4804 IPPROTO_TCP,
4805 0);
4806 adapter->hw_tso_ctxt++;
4807 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4808 ipv6_hdr(skb)->payload_len = 0;
4809 tcp_hdr(skb)->check =
4810 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4811 &ipv6_hdr(skb)->daddr,
4812 0, IPPROTO_TCP, 0);
4813 adapter->hw_tso6_ctxt++;
4814 }
4815
4816 i = tx_ring->next_to_use;
4817
4818 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4819 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4820
4821 /* VLAN MACLEN IPLEN */
4822 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4823 vlan_macip_lens |=
4824 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4825 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4826 IXGBE_ADVTXD_MACLEN_SHIFT);
4827 *hdr_len += skb_network_offset(skb);
4828 vlan_macip_lens |=
4829 (skb_transport_header(skb) - skb_network_header(skb));
4830 *hdr_len +=
4831 (skb_transport_header(skb) - skb_network_header(skb));
4832 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4833 context_desc->seqnum_seed = 0;
4834
4835 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4836 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4837 IXGBE_ADVTXD_DTYP_CTXT);
4838
4839 if (skb->protocol == htons(ETH_P_IP))
4840 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4841 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4842 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4843
4844 /* MSS L4LEN IDX */
4845 mss_l4len_idx =
4846 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4847 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4848 /* use index 1 for TSO */
4849 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4850 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4851
4852 tx_buffer_info->time_stamp = jiffies;
4853 tx_buffer_info->next_to_watch = i;
4854
4855 i++;
4856 if (i == tx_ring->count)
4857 i = 0;
4858 tx_ring->next_to_use = i;
4859
4860 return true;
4861 }
4862 return false;
4863 }
4864
4865 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4866 struct ixgbe_ring *tx_ring,
4867 struct sk_buff *skb, u32 tx_flags)
4868 {
4869 struct ixgbe_adv_tx_context_desc *context_desc;
4870 unsigned int i;
4871 struct ixgbe_tx_buffer *tx_buffer_info;
4872 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4873
4874 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4875 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4876 i = tx_ring->next_to_use;
4877 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4878 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4879
4880 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4881 vlan_macip_lens |=
4882 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4883 vlan_macip_lens |= (skb_network_offset(skb) <<
4884 IXGBE_ADVTXD_MACLEN_SHIFT);
4885 if (skb->ip_summed == CHECKSUM_PARTIAL)
4886 vlan_macip_lens |= (skb_transport_header(skb) -
4887 skb_network_header(skb));
4888
4889 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4890 context_desc->seqnum_seed = 0;
4891
4892 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4893 IXGBE_ADVTXD_DTYP_CTXT);
4894
4895 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4896 switch (skb->protocol) {
4897 case cpu_to_be16(ETH_P_IP):
4898 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4899 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4900 type_tucmd_mlhl |=
4901 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4902 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4903 type_tucmd_mlhl |=
4904 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4905 break;
4906 case cpu_to_be16(ETH_P_IPV6):
4907 /* XXX what about other V6 headers?? */
4908 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4909 type_tucmd_mlhl |=
4910 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4911 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4912 type_tucmd_mlhl |=
4913 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4914 break;
4915 default:
4916 if (unlikely(net_ratelimit())) {
4917 DPRINTK(PROBE, WARNING,
4918 "partial checksum but proto=%x!\n",
4919 skb->protocol);
4920 }
4921 break;
4922 }
4923 }
4924
4925 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4926 /* use index zero for tx checksum offload */
4927 context_desc->mss_l4len_idx = 0;
4928
4929 tx_buffer_info->time_stamp = jiffies;
4930 tx_buffer_info->next_to_watch = i;
4931
4932 adapter->hw_csum_tx_good++;
4933 i++;
4934 if (i == tx_ring->count)
4935 i = 0;
4936 tx_ring->next_to_use = i;
4937
4938 return true;
4939 }
4940
4941 return false;
4942 }
4943
4944 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4945 struct ixgbe_ring *tx_ring,
4946 struct sk_buff *skb, u32 tx_flags,
4947 unsigned int first)
4948 {
4949 struct ixgbe_tx_buffer *tx_buffer_info;
4950 unsigned int len;
4951 unsigned int total = skb->len;
4952 unsigned int offset = 0, size, count = 0, i;
4953 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4954 unsigned int f;
4955 dma_addr_t *map;
4956
4957 i = tx_ring->next_to_use;
4958
4959 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4960 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4961 return 0;
4962 }
4963
4964 map = skb_shinfo(skb)->dma_maps;
4965
4966 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4967 /* excluding fcoe_crc_eof for FCoE */
4968 total -= sizeof(struct fcoe_crc_eof);
4969
4970 len = min(skb_headlen(skb), total);
4971 while (len) {
4972 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4973 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4974
4975 tx_buffer_info->length = size;
4976 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
4977 tx_buffer_info->time_stamp = jiffies;
4978 tx_buffer_info->next_to_watch = i;
4979
4980 len -= size;
4981 total -= size;
4982 offset += size;
4983 count++;
4984
4985 if (len) {
4986 i++;
4987 if (i == tx_ring->count)
4988 i = 0;
4989 }
4990 }
4991
4992 for (f = 0; f < nr_frags; f++) {
4993 struct skb_frag_struct *frag;
4994
4995 frag = &skb_shinfo(skb)->frags[f];
4996 len = min((unsigned int)frag->size, total);
4997 offset = 0;
4998
4999 while (len) {
5000 i++;
5001 if (i == tx_ring->count)
5002 i = 0;
5003
5004 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5005 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5006
5007 tx_buffer_info->length = size;
5008 tx_buffer_info->dma = map[f] + offset;
5009 tx_buffer_info->time_stamp = jiffies;
5010 tx_buffer_info->next_to_watch = i;
5011
5012 len -= size;
5013 total -= size;
5014 offset += size;
5015 count++;
5016 }
5017 if (total == 0)
5018 break;
5019 }
5020
5021 tx_ring->tx_buffer_info[i].skb = skb;
5022 tx_ring->tx_buffer_info[first].next_to_watch = i;
5023
5024 return count;
5025 }
5026
5027 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5028 struct ixgbe_ring *tx_ring,
5029 int tx_flags, int count, u32 paylen, u8 hdr_len)
5030 {
5031 union ixgbe_adv_tx_desc *tx_desc = NULL;
5032 struct ixgbe_tx_buffer *tx_buffer_info;
5033 u32 olinfo_status = 0, cmd_type_len = 0;
5034 unsigned int i;
5035 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5036
5037 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5038
5039 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5040
5041 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5042 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5043
5044 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5045 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5046
5047 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5048 IXGBE_ADVTXD_POPTS_SHIFT;
5049
5050 /* use index 1 context for tso */
5051 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5052 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5053 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5054 IXGBE_ADVTXD_POPTS_SHIFT;
5055
5056 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5057 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5058 IXGBE_ADVTXD_POPTS_SHIFT;
5059
5060 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5061 olinfo_status |= IXGBE_ADVTXD_CC;
5062 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5063 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5064 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5065 }
5066
5067 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5068
5069 i = tx_ring->next_to_use;
5070 while (count--) {
5071 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5072 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5073 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5074 tx_desc->read.cmd_type_len =
5075 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5076 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5077 i++;
5078 if (i == tx_ring->count)
5079 i = 0;
5080 }
5081
5082 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5083
5084 /*
5085 * Force memory writes to complete before letting h/w
5086 * know there are new descriptors to fetch. (Only
5087 * applicable for weak-ordered memory model archs,
5088 * such as IA-64).
5089 */
5090 wmb();
5091
5092 tx_ring->next_to_use = i;
5093 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5094 }
5095
5096 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5097 int queue, u32 tx_flags)
5098 {
5099 /* Right now, we support IPv4 only */
5100 struct ixgbe_atr_input atr_input;
5101 struct tcphdr *th;
5102 struct iphdr *iph = ip_hdr(skb);
5103 struct ethhdr *eth = (struct ethhdr *)skb->data;
5104 u16 vlan_id, src_port, dst_port, flex_bytes;
5105 u32 src_ipv4_addr, dst_ipv4_addr;
5106 u8 l4type = 0;
5107
5108 /* check if we're UDP or TCP */
5109 if (iph->protocol == IPPROTO_TCP) {
5110 th = tcp_hdr(skb);
5111 src_port = th->source;
5112 dst_port = th->dest;
5113 l4type |= IXGBE_ATR_L4TYPE_TCP;
5114 /* l4type IPv4 type is 0, no need to assign */
5115 } else {
5116 /* Unsupported L4 header, just bail here */
5117 return;
5118 }
5119
5120 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5121
5122 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5123 IXGBE_TX_FLAGS_VLAN_SHIFT;
5124 src_ipv4_addr = iph->saddr;
5125 dst_ipv4_addr = iph->daddr;
5126 flex_bytes = eth->h_proto;
5127
5128 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5129 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5130 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5131 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5132 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5133 /* src and dst are inverted, think how the receiver sees them */
5134 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5135 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5136
5137 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5138 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5139 }
5140
5141 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5142 struct ixgbe_ring *tx_ring, int size)
5143 {
5144 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5145
5146 netif_stop_subqueue(netdev, tx_ring->queue_index);
5147 /* Herbert's original patch had:
5148 * smp_mb__after_netif_stop_queue();
5149 * but since that doesn't exist yet, just open code it. */
5150 smp_mb();
5151
5152 /* We need to check again in a case another CPU has just
5153 * made room available. */
5154 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5155 return -EBUSY;
5156
5157 /* A reprieve! - use start_queue because it doesn't call schedule */
5158 netif_start_subqueue(netdev, tx_ring->queue_index);
5159 ++adapter->restart_queue;
5160 return 0;
5161 }
5162
5163 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5164 struct ixgbe_ring *tx_ring, int size)
5165 {
5166 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5167 return 0;
5168 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5169 }
5170
5171 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5172 {
5173 struct ixgbe_adapter *adapter = netdev_priv(dev);
5174
5175 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5176 return smp_processor_id();
5177
5178 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5179 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5180
5181 return skb_tx_hash(dev, skb);
5182 }
5183
5184 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5185 struct net_device *netdev)
5186 {
5187 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5188 struct ixgbe_ring *tx_ring;
5189 unsigned int first;
5190 unsigned int tx_flags = 0;
5191 u8 hdr_len = 0;
5192 int r_idx = 0, tso;
5193 int count = 0;
5194 unsigned int f;
5195
5196 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5197 tx_flags |= vlan_tx_tag_get(skb);
5198 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5199 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5200 tx_flags |= (skb->queue_mapping << 13);
5201 }
5202 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5203 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5204 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5205 if (skb->priority != TC_PRIO_CONTROL) {
5206 tx_flags |= (skb->queue_mapping << 13);
5207 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5208 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5209 } else {
5210 skb->queue_mapping =
5211 adapter->ring_feature[RING_F_DCB].indices-1;
5212 }
5213 }
5214
5215 r_idx = skb->queue_mapping;
5216 tx_ring = &adapter->tx_ring[r_idx];
5217
5218 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5219 (skb->protocol == htons(ETH_P_FCOE))) {
5220 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5221 #ifdef IXGBE_FCOE
5222 r_idx = smp_processor_id();
5223 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5224 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5225 tx_ring = &adapter->tx_ring[r_idx];
5226 #endif
5227 }
5228 /* four things can cause us to need a context descriptor */
5229 if (skb_is_gso(skb) ||
5230 (skb->ip_summed == CHECKSUM_PARTIAL) ||
5231 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5232 (tx_flags & IXGBE_TX_FLAGS_FCOE))
5233 count++;
5234
5235 count += TXD_USE_COUNT(skb_headlen(skb));
5236 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5237 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5238
5239 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5240 adapter->tx_busy++;
5241 return NETDEV_TX_BUSY;
5242 }
5243
5244 first = tx_ring->next_to_use;
5245 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5246 #ifdef IXGBE_FCOE
5247 /* setup tx offload for FCoE */
5248 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5249 if (tso < 0) {
5250 dev_kfree_skb_any(skb);
5251 return NETDEV_TX_OK;
5252 }
5253 if (tso)
5254 tx_flags |= IXGBE_TX_FLAGS_FSO;
5255 #endif /* IXGBE_FCOE */
5256 } else {
5257 if (skb->protocol == htons(ETH_P_IP))
5258 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5259 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5260 if (tso < 0) {
5261 dev_kfree_skb_any(skb);
5262 return NETDEV_TX_OK;
5263 }
5264
5265 if (tso)
5266 tx_flags |= IXGBE_TX_FLAGS_TSO;
5267 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5268 (skb->ip_summed == CHECKSUM_PARTIAL))
5269 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5270 }
5271
5272 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5273 if (count) {
5274 /* add the ATR filter if ATR is on */
5275 if (tx_ring->atr_sample_rate) {
5276 ++tx_ring->atr_count;
5277 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5278 test_bit(__IXGBE_FDIR_INIT_DONE,
5279 &tx_ring->reinit_state)) {
5280 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5281 tx_flags);
5282 tx_ring->atr_count = 0;
5283 }
5284 }
5285 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5286 hdr_len);
5287 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5288
5289 } else {
5290 dev_kfree_skb_any(skb);
5291 tx_ring->tx_buffer_info[first].time_stamp = 0;
5292 tx_ring->next_to_use = first;
5293 }
5294
5295 return NETDEV_TX_OK;
5296 }
5297
5298 /**
5299 * ixgbe_get_stats - Get System Network Statistics
5300 * @netdev: network interface device structure
5301 *
5302 * Returns the address of the device statistics structure.
5303 * The statistics are actually updated from the timer callback.
5304 **/
5305 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5306 {
5307 /* only return the current stats */
5308 return &netdev->stats;
5309 }
5310
5311 /**
5312 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5313 * @netdev: network interface device structure
5314 * @p: pointer to an address structure
5315 *
5316 * Returns 0 on success, negative on failure
5317 **/
5318 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5319 {
5320 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5321 struct ixgbe_hw *hw = &adapter->hw;
5322 struct sockaddr *addr = p;
5323
5324 if (!is_valid_ether_addr(addr->sa_data))
5325 return -EADDRNOTAVAIL;
5326
5327 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5328 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5329
5330 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5331
5332 return 0;
5333 }
5334
5335 static int
5336 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5337 {
5338 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5339 struct ixgbe_hw *hw = &adapter->hw;
5340 u16 value;
5341 int rc;
5342
5343 if (prtad != hw->phy.mdio.prtad)
5344 return -EINVAL;
5345 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5346 if (!rc)
5347 rc = value;
5348 return rc;
5349 }
5350
5351 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5352 u16 addr, u16 value)
5353 {
5354 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5355 struct ixgbe_hw *hw = &adapter->hw;
5356
5357 if (prtad != hw->phy.mdio.prtad)
5358 return -EINVAL;
5359 return hw->phy.ops.write_reg(hw, addr, devad, value);
5360 }
5361
5362 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5363 {
5364 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5365
5366 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5367 }
5368
5369 /**
5370 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5371 * netdev->dev_addrs
5372 * @netdev: network interface device structure
5373 *
5374 * Returns non-zero on failure
5375 **/
5376 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5377 {
5378 int err = 0;
5379 struct ixgbe_adapter *adapter = netdev_priv(dev);
5380 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5381
5382 if (is_valid_ether_addr(mac->san_addr)) {
5383 rtnl_lock();
5384 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5385 rtnl_unlock();
5386 }
5387 return err;
5388 }
5389
5390 /**
5391 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5392 * netdev->dev_addrs
5393 * @netdev: network interface device structure
5394 *
5395 * Returns non-zero on failure
5396 **/
5397 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5398 {
5399 int err = 0;
5400 struct ixgbe_adapter *adapter = netdev_priv(dev);
5401 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5402
5403 if (is_valid_ether_addr(mac->san_addr)) {
5404 rtnl_lock();
5405 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5406 rtnl_unlock();
5407 }
5408 return err;
5409 }
5410
5411 #ifdef CONFIG_NET_POLL_CONTROLLER
5412 /*
5413 * Polling 'interrupt' - used by things like netconsole to send skbs
5414 * without having to re-enable interrupts. It's not called while
5415 * the interrupt routine is executing.
5416 */
5417 static void ixgbe_netpoll(struct net_device *netdev)
5418 {
5419 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5420 int i;
5421
5422 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5423 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5424 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5425 for (i = 0; i < num_q_vectors; i++) {
5426 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5427 ixgbe_msix_clean_many(0, q_vector);
5428 }
5429 } else {
5430 ixgbe_intr(adapter->pdev->irq, netdev);
5431 }
5432 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5433 }
5434 #endif
5435
5436 static const struct net_device_ops ixgbe_netdev_ops = {
5437 .ndo_open = ixgbe_open,
5438 .ndo_stop = ixgbe_close,
5439 .ndo_start_xmit = ixgbe_xmit_frame,
5440 .ndo_select_queue = ixgbe_select_queue,
5441 .ndo_get_stats = ixgbe_get_stats,
5442 .ndo_set_rx_mode = ixgbe_set_rx_mode,
5443 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5444 .ndo_validate_addr = eth_validate_addr,
5445 .ndo_set_mac_address = ixgbe_set_mac,
5446 .ndo_change_mtu = ixgbe_change_mtu,
5447 .ndo_tx_timeout = ixgbe_tx_timeout,
5448 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5449 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5450 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
5451 .ndo_do_ioctl = ixgbe_ioctl,
5452 #ifdef CONFIG_NET_POLL_CONTROLLER
5453 .ndo_poll_controller = ixgbe_netpoll,
5454 #endif
5455 #ifdef IXGBE_FCOE
5456 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5457 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5458 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5459 .ndo_fcoe_disable = ixgbe_fcoe_disable,
5460 #endif /* IXGBE_FCOE */
5461 };
5462
5463 /**
5464 * ixgbe_probe - Device Initialization Routine
5465 * @pdev: PCI device information struct
5466 * @ent: entry in ixgbe_pci_tbl
5467 *
5468 * Returns 0 on success, negative on failure
5469 *
5470 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5471 * The OS initialization, configuring of the adapter private structure,
5472 * and a hardware reset occur.
5473 **/
5474 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5475 const struct pci_device_id *ent)
5476 {
5477 struct net_device *netdev;
5478 struct ixgbe_adapter *adapter = NULL;
5479 struct ixgbe_hw *hw;
5480 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5481 static int cards_found;
5482 int i, err, pci_using_dac;
5483 #ifdef IXGBE_FCOE
5484 u16 device_caps;
5485 #endif
5486 u32 part_num, eec;
5487
5488 err = pci_enable_device_mem(pdev);
5489 if (err)
5490 return err;
5491
5492 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5493 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5494 pci_using_dac = 1;
5495 } else {
5496 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5497 if (err) {
5498 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5499 if (err) {
5500 dev_err(&pdev->dev, "No usable DMA "
5501 "configuration, aborting\n");
5502 goto err_dma;
5503 }
5504 }
5505 pci_using_dac = 0;
5506 }
5507
5508 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5509 IORESOURCE_MEM), ixgbe_driver_name);
5510 if (err) {
5511 dev_err(&pdev->dev,
5512 "pci_request_selected_regions failed 0x%x\n", err);
5513 goto err_pci_reg;
5514 }
5515
5516 pci_enable_pcie_error_reporting(pdev);
5517
5518 pci_set_master(pdev);
5519 pci_save_state(pdev);
5520
5521 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5522 if (!netdev) {
5523 err = -ENOMEM;
5524 goto err_alloc_etherdev;
5525 }
5526
5527 SET_NETDEV_DEV(netdev, &pdev->dev);
5528
5529 pci_set_drvdata(pdev, netdev);
5530 adapter = netdev_priv(netdev);
5531
5532 adapter->netdev = netdev;
5533 adapter->pdev = pdev;
5534 hw = &adapter->hw;
5535 hw->back = adapter;
5536 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5537
5538 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5539 pci_resource_len(pdev, 0));
5540 if (!hw->hw_addr) {
5541 err = -EIO;
5542 goto err_ioremap;
5543 }
5544
5545 for (i = 1; i <= 5; i++) {
5546 if (pci_resource_len(pdev, i) == 0)
5547 continue;
5548 }
5549
5550 netdev->netdev_ops = &ixgbe_netdev_ops;
5551 ixgbe_set_ethtool_ops(netdev);
5552 netdev->watchdog_timeo = 5 * HZ;
5553 strcpy(netdev->name, pci_name(pdev));
5554
5555 adapter->bd_number = cards_found;
5556
5557 /* Setup hw api */
5558 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5559 hw->mac.type = ii->mac;
5560
5561 /* EEPROM */
5562 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5563 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5564 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5565 if (!(eec & (1 << 8)))
5566 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5567
5568 /* PHY */
5569 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5570 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5571 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5572 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5573 hw->phy.mdio.mmds = 0;
5574 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5575 hw->phy.mdio.dev = netdev;
5576 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5577 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5578
5579 /* set up this timer and work struct before calling get_invariants
5580 * which might start the timer
5581 */
5582 init_timer(&adapter->sfp_timer);
5583 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5584 adapter->sfp_timer.data = (unsigned long) adapter;
5585
5586 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5587
5588 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5589 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5590
5591 /* a new SFP+ module arrival, called from GPI SDP2 context */
5592 INIT_WORK(&adapter->sfp_config_module_task,
5593 ixgbe_sfp_config_module_task);
5594
5595 ii->get_invariants(hw);
5596
5597 /* setup the private structure */
5598 err = ixgbe_sw_init(adapter);
5599 if (err)
5600 goto err_sw_init;
5601
5602 /*
5603 * If there is a fan on this device and it has failed log the
5604 * failure.
5605 */
5606 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5607 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5608 if (esdp & IXGBE_ESDP_SDP1)
5609 DPRINTK(PROBE, CRIT,
5610 "Fan has stopped, replace the adapter\n");
5611 }
5612
5613 /* reset_hw fills in the perm_addr as well */
5614 err = hw->mac.ops.reset_hw(hw);
5615 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5616 hw->mac.type == ixgbe_mac_82598EB) {
5617 /*
5618 * Start a kernel thread to watch for a module to arrive.
5619 * Only do this for 82598, since 82599 will generate
5620 * interrupts on module arrival.
5621 */
5622 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5623 mod_timer(&adapter->sfp_timer,
5624 round_jiffies(jiffies + (2 * HZ)));
5625 err = 0;
5626 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5627 dev_err(&adapter->pdev->dev, "failed to initialize because "
5628 "an unsupported SFP+ module type was detected.\n"
5629 "Reload the driver after installing a supported "
5630 "module.\n");
5631 goto err_sw_init;
5632 } else if (err) {
5633 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5634 goto err_sw_init;
5635 }
5636
5637 netdev->features = NETIF_F_SG |
5638 NETIF_F_IP_CSUM |
5639 NETIF_F_HW_VLAN_TX |
5640 NETIF_F_HW_VLAN_RX |
5641 NETIF_F_HW_VLAN_FILTER;
5642
5643 netdev->features |= NETIF_F_IPV6_CSUM;
5644 netdev->features |= NETIF_F_TSO;
5645 netdev->features |= NETIF_F_TSO6;
5646 netdev->features |= NETIF_F_GRO;
5647
5648 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5649 netdev->features |= NETIF_F_SCTP_CSUM;
5650
5651 netdev->vlan_features |= NETIF_F_TSO;
5652 netdev->vlan_features |= NETIF_F_TSO6;
5653 netdev->vlan_features |= NETIF_F_IP_CSUM;
5654 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5655 netdev->vlan_features |= NETIF_F_SG;
5656
5657 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5658 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5659
5660 #ifdef CONFIG_IXGBE_DCB
5661 netdev->dcbnl_ops = &dcbnl_ops;
5662 #endif
5663
5664 #ifdef IXGBE_FCOE
5665 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5666 if (hw->mac.ops.get_device_caps) {
5667 hw->mac.ops.get_device_caps(hw, &device_caps);
5668 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5669 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5670 }
5671 }
5672 #endif /* IXGBE_FCOE */
5673 if (pci_using_dac)
5674 netdev->features |= NETIF_F_HIGHDMA;
5675
5676 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5677 netdev->features |= NETIF_F_LRO;
5678
5679 /* make sure the EEPROM is good */
5680 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5681 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5682 err = -EIO;
5683 goto err_eeprom;
5684 }
5685
5686 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5687 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5688
5689 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5690 dev_err(&pdev->dev, "invalid MAC address\n");
5691 err = -EIO;
5692 goto err_eeprom;
5693 }
5694
5695 init_timer(&adapter->watchdog_timer);
5696 adapter->watchdog_timer.function = &ixgbe_watchdog;
5697 adapter->watchdog_timer.data = (unsigned long)adapter;
5698
5699 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5700 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5701
5702 err = ixgbe_init_interrupt_scheme(adapter);
5703 if (err)
5704 goto err_sw_init;
5705
5706 switch (pdev->device) {
5707 case IXGBE_DEV_ID_82599_KX4:
5708 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5709 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5710 /* Enable ACPI wakeup in GRC */
5711 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5712 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5713 break;
5714 default:
5715 adapter->wol = 0;
5716 break;
5717 }
5718 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5719
5720 /* pick up the PCI bus settings for reporting later */
5721 hw->mac.ops.get_bus_info(hw);
5722
5723 /* print bus type/speed/width info */
5724 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5725 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5726 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5727 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5728 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5729 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5730 "Unknown"),
5731 netdev->dev_addr);
5732 ixgbe_read_pba_num_generic(hw, &part_num);
5733 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5734 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5735 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5736 (part_num >> 8), (part_num & 0xff));
5737 else
5738 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5739 hw->mac.type, hw->phy.type,
5740 (part_num >> 8), (part_num & 0xff));
5741
5742 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5743 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5744 "this card is not sufficient for optimal "
5745 "performance.\n");
5746 dev_warn(&pdev->dev, "For optimal performance a x8 "
5747 "PCI-Express slot is required.\n");
5748 }
5749
5750 /* save off EEPROM version number */
5751 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5752
5753 /* reset the hardware with the new settings */
5754 err = hw->mac.ops.start_hw(hw);
5755
5756 if (err == IXGBE_ERR_EEPROM_VERSION) {
5757 /* We are running on a pre-production device, log a warning */
5758 dev_warn(&pdev->dev, "This device is a pre-production "
5759 "adapter/LOM. Please be aware there may be issues "
5760 "associated with your hardware. If you are "
5761 "experiencing problems please contact your Intel or "
5762 "hardware representative who provided you with this "
5763 "hardware.\n");
5764 }
5765 strcpy(netdev->name, "eth%d");
5766 err = register_netdev(netdev);
5767 if (err)
5768 goto err_register;
5769
5770 /* carrier off reporting is important to ethtool even BEFORE open */
5771 netif_carrier_off(netdev);
5772
5773 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5774 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5775 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5776
5777 #ifdef CONFIG_IXGBE_DCA
5778 if (dca_add_requester(&pdev->dev) == 0) {
5779 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5780 ixgbe_setup_dca(adapter);
5781 }
5782 #endif
5783 /* add san mac addr to netdev */
5784 ixgbe_add_sanmac_netdev(netdev);
5785
5786 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5787 cards_found++;
5788 return 0;
5789
5790 err_register:
5791 ixgbe_release_hw_control(adapter);
5792 ixgbe_clear_interrupt_scheme(adapter);
5793 err_sw_init:
5794 err_eeprom:
5795 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5796 del_timer_sync(&adapter->sfp_timer);
5797 cancel_work_sync(&adapter->sfp_task);
5798 cancel_work_sync(&adapter->multispeed_fiber_task);
5799 cancel_work_sync(&adapter->sfp_config_module_task);
5800 iounmap(hw->hw_addr);
5801 err_ioremap:
5802 free_netdev(netdev);
5803 err_alloc_etherdev:
5804 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5805 IORESOURCE_MEM));
5806 err_pci_reg:
5807 err_dma:
5808 pci_disable_device(pdev);
5809 return err;
5810 }
5811
5812 /**
5813 * ixgbe_remove - Device Removal Routine
5814 * @pdev: PCI device information struct
5815 *
5816 * ixgbe_remove is called by the PCI subsystem to alert the driver
5817 * that it should release a PCI device. The could be caused by a
5818 * Hot-Plug event, or because the driver is going to be removed from
5819 * memory.
5820 **/
5821 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5822 {
5823 struct net_device *netdev = pci_get_drvdata(pdev);
5824 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5825
5826 set_bit(__IXGBE_DOWN, &adapter->state);
5827 /* clear the module not found bit to make sure the worker won't
5828 * reschedule
5829 */
5830 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5831 del_timer_sync(&adapter->watchdog_timer);
5832
5833 del_timer_sync(&adapter->sfp_timer);
5834 cancel_work_sync(&adapter->watchdog_task);
5835 cancel_work_sync(&adapter->sfp_task);
5836 cancel_work_sync(&adapter->multispeed_fiber_task);
5837 cancel_work_sync(&adapter->sfp_config_module_task);
5838 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5839 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5840 cancel_work_sync(&adapter->fdir_reinit_task);
5841 flush_scheduled_work();
5842
5843 #ifdef CONFIG_IXGBE_DCA
5844 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5845 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5846 dca_remove_requester(&pdev->dev);
5847 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5848 }
5849
5850 #endif
5851 #ifdef IXGBE_FCOE
5852 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5853 ixgbe_cleanup_fcoe(adapter);
5854
5855 #endif /* IXGBE_FCOE */
5856
5857 /* remove the added san mac */
5858 ixgbe_del_sanmac_netdev(netdev);
5859
5860 if (netdev->reg_state == NETREG_REGISTERED)
5861 unregister_netdev(netdev);
5862
5863 ixgbe_clear_interrupt_scheme(adapter);
5864
5865 ixgbe_release_hw_control(adapter);
5866
5867 iounmap(adapter->hw.hw_addr);
5868 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5869 IORESOURCE_MEM));
5870
5871 DPRINTK(PROBE, INFO, "complete\n");
5872
5873 free_netdev(netdev);
5874
5875 pci_disable_pcie_error_reporting(pdev);
5876
5877 pci_disable_device(pdev);
5878 }
5879
5880 /**
5881 * ixgbe_io_error_detected - called when PCI error is detected
5882 * @pdev: Pointer to PCI device
5883 * @state: The current pci connection state
5884 *
5885 * This function is called after a PCI bus error affecting
5886 * this device has been detected.
5887 */
5888 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5889 pci_channel_state_t state)
5890 {
5891 struct net_device *netdev = pci_get_drvdata(pdev);
5892 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5893
5894 netif_device_detach(netdev);
5895
5896 if (state == pci_channel_io_perm_failure)
5897 return PCI_ERS_RESULT_DISCONNECT;
5898
5899 if (netif_running(netdev))
5900 ixgbe_down(adapter);
5901 pci_disable_device(pdev);
5902
5903 /* Request a slot reset. */
5904 return PCI_ERS_RESULT_NEED_RESET;
5905 }
5906
5907 /**
5908 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5909 * @pdev: Pointer to PCI device
5910 *
5911 * Restart the card from scratch, as if from a cold-boot.
5912 */
5913 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5914 {
5915 struct net_device *netdev = pci_get_drvdata(pdev);
5916 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5917 pci_ers_result_t result;
5918 int err;
5919
5920 if (pci_enable_device_mem(pdev)) {
5921 DPRINTK(PROBE, ERR,
5922 "Cannot re-enable PCI device after reset.\n");
5923 result = PCI_ERS_RESULT_DISCONNECT;
5924 } else {
5925 pci_set_master(pdev);
5926 pci_restore_state(pdev);
5927
5928 pci_wake_from_d3(pdev, false);
5929
5930 ixgbe_reset(adapter);
5931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5932 result = PCI_ERS_RESULT_RECOVERED;
5933 }
5934
5935 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5936 if (err) {
5937 dev_err(&pdev->dev,
5938 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5939 /* non-fatal, continue */
5940 }
5941
5942 return result;
5943 }
5944
5945 /**
5946 * ixgbe_io_resume - called when traffic can start flowing again.
5947 * @pdev: Pointer to PCI device
5948 *
5949 * This callback is called when the error recovery driver tells us that
5950 * its OK to resume normal operation.
5951 */
5952 static void ixgbe_io_resume(struct pci_dev *pdev)
5953 {
5954 struct net_device *netdev = pci_get_drvdata(pdev);
5955 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5956
5957 if (netif_running(netdev)) {
5958 if (ixgbe_up(adapter)) {
5959 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5960 return;
5961 }
5962 }
5963
5964 netif_device_attach(netdev);
5965 }
5966
5967 static struct pci_error_handlers ixgbe_err_handler = {
5968 .error_detected = ixgbe_io_error_detected,
5969 .slot_reset = ixgbe_io_slot_reset,
5970 .resume = ixgbe_io_resume,
5971 };
5972
5973 static struct pci_driver ixgbe_driver = {
5974 .name = ixgbe_driver_name,
5975 .id_table = ixgbe_pci_tbl,
5976 .probe = ixgbe_probe,
5977 .remove = __devexit_p(ixgbe_remove),
5978 #ifdef CONFIG_PM
5979 .suspend = ixgbe_suspend,
5980 .resume = ixgbe_resume,
5981 #endif
5982 .shutdown = ixgbe_shutdown,
5983 .err_handler = &ixgbe_err_handler
5984 };
5985
5986 /**
5987 * ixgbe_init_module - Driver Registration Routine
5988 *
5989 * ixgbe_init_module is the first routine called when the driver is
5990 * loaded. All it does is register with the PCI subsystem.
5991 **/
5992 static int __init ixgbe_init_module(void)
5993 {
5994 int ret;
5995 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5996 ixgbe_driver_string, ixgbe_driver_version);
5997
5998 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5999
6000 #ifdef CONFIG_IXGBE_DCA
6001 dca_register_notify(&dca_notifier);
6002 #endif
6003
6004 ret = pci_register_driver(&ixgbe_driver);
6005 return ret;
6006 }
6007
6008 module_init(ixgbe_init_module);
6009
6010 /**
6011 * ixgbe_exit_module - Driver Exit Cleanup Routine
6012 *
6013 * ixgbe_exit_module is called just before the driver is removed
6014 * from memory.
6015 **/
6016 static void __exit ixgbe_exit_module(void)
6017 {
6018 #ifdef CONFIG_IXGBE_DCA
6019 dca_unregister_notify(&dca_notifier);
6020 #endif
6021 pci_unregister_driver(&ixgbe_driver);
6022 }
6023
6024 #ifdef CONFIG_IXGBE_DCA
6025 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6026 void *p)
6027 {
6028 int ret_val;
6029
6030 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6031 __ixgbe_notify_dca);
6032
6033 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6034 }
6035
6036 #endif /* CONFIG_IXGBE_DCA */
6037 #ifdef DEBUG
6038 /**
6039 * ixgbe_get_hw_dev_name - return device name string
6040 * used by hardware layer to print debugging information
6041 **/
6042 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6043 {
6044 struct ixgbe_adapter *adapter = hw->back;
6045 return adapter->netdev->name;
6046 }
6047
6048 #endif
6049 module_exit(ixgbe_exit_module);
6050
6051 /* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)