1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
51 char ixgbe_driver_name
[] = "ixgbe";
52 static const char ixgbe_driver_string
[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #define DRV_VERSION "2.0.62-k2"
56 const char ixgbe_driver_version
[] = DRV_VERSION
;
57 static char ixgbe_copyright
[] = "Copyright (c) 1999-2010 Intel Corporation.";
59 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
60 [board_82598
] = &ixgbe_82598_info
,
61 [board_82599
] = &ixgbe_82599_info
,
64 /* ixgbe_pci_tbl - PCI Device ID Table
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
73 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
75 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
77 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
79 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
97 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
99 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
101 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
103 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
105 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
107 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
109 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
111 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
114 /* required last entry */
117 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
119 #ifdef CONFIG_IXGBE_DCA
120 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
122 static struct notifier_block dca_notifier
= {
123 .notifier_call
= ixgbe_notify_dca
,
129 #ifdef CONFIG_PCI_IOV
130 static unsigned int max_vfs
;
131 module_param(max_vfs
, uint
, 0);
132 MODULE_PARM_DESC(max_vfs
, "Maximum number of virtual functions to allocate "
133 "per physical function");
134 #endif /* CONFIG_PCI_IOV */
136 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
137 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
138 MODULE_LICENSE("GPL");
139 MODULE_VERSION(DRV_VERSION
);
141 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
143 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
145 struct ixgbe_hw
*hw
= &adapter
->hw
;
150 #ifdef CONFIG_PCI_IOV
151 /* disable iov and allow time for transactions to clear */
152 pci_disable_sriov(adapter
->pdev
);
155 /* turn off device IOV mode */
156 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
157 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
158 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
159 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
160 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
161 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
163 /* set default pool back to 0 */
164 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
165 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
166 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
168 /* take a breather then clean up driver data */
171 kfree(adapter
->vfinfo
);
172 adapter
->vfinfo
= NULL
;
174 adapter
->num_vfs
= 0;
175 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
178 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
182 /* Let firmware take over control of h/w */
183 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
184 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
185 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
188 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
192 /* Let firmware know the driver has taken over */
193 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
194 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
195 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
199 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
200 * @adapter: pointer to adapter struct
201 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
202 * @queue: queue to map the corresponding interrupt to
203 * @msix_vector: the vector to map to the corresponding queue
206 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
207 u8 queue
, u8 msix_vector
)
210 struct ixgbe_hw
*hw
= &adapter
->hw
;
211 switch (hw
->mac
.type
) {
212 case ixgbe_mac_82598EB
:
213 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
216 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
217 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
218 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
219 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
220 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
222 case ixgbe_mac_82599EB
:
223 if (direction
== -1) {
225 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
226 index
= ((queue
& 1) * 8);
227 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
228 ivar
&= ~(0xFF << index
);
229 ivar
|= (msix_vector
<< index
);
230 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
233 /* tx or rx causes */
234 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
235 index
= ((16 * (queue
& 1)) + (8 * direction
));
236 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
237 ivar
&= ~(0xFF << index
);
238 ivar
|= (msix_vector
<< index
);
239 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
247 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
252 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
253 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
254 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
256 mask
= (qmask
& 0xFFFFFFFF);
257 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
258 mask
= (qmask
>> 32);
259 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
263 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter
*adapter
,
264 struct ixgbe_tx_buffer
267 if (tx_buffer_info
->dma
) {
268 if (tx_buffer_info
->mapped_as_page
)
269 dma_unmap_page(&adapter
->pdev
->dev
,
271 tx_buffer_info
->length
,
274 dma_unmap_single(&adapter
->pdev
->dev
,
276 tx_buffer_info
->length
,
278 tx_buffer_info
->dma
= 0;
280 if (tx_buffer_info
->skb
) {
281 dev_kfree_skb_any(tx_buffer_info
->skb
);
282 tx_buffer_info
->skb
= NULL
;
284 tx_buffer_info
->time_stamp
= 0;
285 /* tx_buffer_info must be completely set up in the transmit path */
289 * ixgbe_tx_is_paused - check if the tx ring is paused
290 * @adapter: the ixgbe adapter
291 * @tx_ring: the corresponding tx_ring
293 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
294 * corresponding TC of this tx_ring when checking TFCS.
296 * Returns : true if paused
298 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter
*adapter
,
299 struct ixgbe_ring
*tx_ring
)
301 u32 txoff
= IXGBE_TFCS_TXOFF
;
303 #ifdef CONFIG_IXGBE_DCB
304 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
306 int reg_idx
= tx_ring
->reg_idx
;
307 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
309 switch (adapter
->hw
.mac
.type
) {
310 case ixgbe_mac_82598EB
:
312 txoff
= IXGBE_TFCS_TXOFF0
;
314 case ixgbe_mac_82599EB
:
316 txoff
= IXGBE_TFCS_TXOFF
;
320 if (tc
== 2) /* TC2, TC3 */
321 tc
+= (reg_idx
- 64) >> 4;
322 else if (tc
== 3) /* TC4, TC5, TC6, TC7 */
323 tc
+= 1 + ((reg_idx
- 96) >> 3);
324 } else if (dcb_i
== 4) {
328 tc
+= (reg_idx
- 64) >> 5;
329 if (tc
== 2) /* TC2, TC3 */
330 tc
+= (reg_idx
- 96) >> 4;
340 return IXGBE_READ_REG(&adapter
->hw
, IXGBE_TFCS
) & txoff
;
343 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter
*adapter
,
344 struct ixgbe_ring
*tx_ring
,
347 struct ixgbe_hw
*hw
= &adapter
->hw
;
349 /* Detect a transmit hang in hardware, this serializes the
350 * check with the clearing of time_stamp and movement of eop */
351 adapter
->detect_tx_hung
= false;
352 if (tx_ring
->tx_buffer_info
[eop
].time_stamp
&&
353 time_after(jiffies
, tx_ring
->tx_buffer_info
[eop
].time_stamp
+ HZ
) &&
354 !ixgbe_tx_is_paused(adapter
, tx_ring
)) {
355 /* detected Tx unit hang */
356 union ixgbe_adv_tx_desc
*tx_desc
;
357 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
358 DPRINTK(DRV
, ERR
, "Detected Tx Unit Hang\n"
360 " TDH, TDT <%x>, <%x>\n"
361 " next_to_use <%x>\n"
362 " next_to_clean <%x>\n"
363 "tx_buffer_info[next_to_clean]\n"
364 " time_stamp <%lx>\n"
366 tx_ring
->queue_index
,
367 IXGBE_READ_REG(hw
, tx_ring
->head
),
368 IXGBE_READ_REG(hw
, tx_ring
->tail
),
369 tx_ring
->next_to_use
, eop
,
370 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
377 #define IXGBE_MAX_TXD_PWR 14
378 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
380 /* Tx Descriptors needed, worst case */
381 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
382 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
383 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
384 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
386 static void ixgbe_tx_timeout(struct net_device
*netdev
);
389 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
390 * @q_vector: structure containing interrupt and ring information
391 * @tx_ring: tx ring to clean
393 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
394 struct ixgbe_ring
*tx_ring
)
396 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
397 struct net_device
*netdev
= adapter
->netdev
;
398 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
399 struct ixgbe_tx_buffer
*tx_buffer_info
;
400 unsigned int i
, eop
, count
= 0;
401 unsigned int total_bytes
= 0, total_packets
= 0;
403 i
= tx_ring
->next_to_clean
;
404 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
405 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
407 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
408 (count
< tx_ring
->work_limit
)) {
409 bool cleaned
= false;
410 for ( ; !cleaned
; count
++) {
412 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
413 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
414 cleaned
= (i
== eop
);
415 skb
= tx_buffer_info
->skb
;
417 if (cleaned
&& skb
) {
418 unsigned int segs
, bytecount
;
419 unsigned int hlen
= skb_headlen(skb
);
421 /* gso_segs is currently only valid for tcp */
422 segs
= skb_shinfo(skb
)->gso_segs
?: 1;
424 /* adjust for FCoE Sequence Offload */
425 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
426 && (skb
->protocol
== htons(ETH_P_FCOE
)) &&
428 hlen
= skb_transport_offset(skb
) +
429 sizeof(struct fc_frame_header
) +
430 sizeof(struct fcoe_crc_eof
);
431 segs
= DIV_ROUND_UP(skb
->len
- hlen
,
432 skb_shinfo(skb
)->gso_size
);
434 #endif /* IXGBE_FCOE */
435 /* multiply data chunks by size of headers */
436 bytecount
= ((segs
- 1) * hlen
) + skb
->len
;
437 total_packets
+= segs
;
438 total_bytes
+= bytecount
;
441 ixgbe_unmap_and_free_tx_resource(adapter
,
444 tx_desc
->wb
.status
= 0;
447 if (i
== tx_ring
->count
)
451 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
452 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
455 tx_ring
->next_to_clean
= i
;
457 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
458 if (unlikely(count
&& netif_carrier_ok(netdev
) &&
459 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
460 /* Make sure that anybody stopping the queue after this
461 * sees the new next_to_clean.
464 if (__netif_subqueue_stopped(netdev
, tx_ring
->queue_index
) &&
465 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
466 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
467 ++tx_ring
->restart_queue
;
471 if (adapter
->detect_tx_hung
) {
472 if (ixgbe_check_tx_hang(adapter
, tx_ring
, i
)) {
473 /* schedule immediate reset if we believe we hung */
475 "tx hang %d detected, resetting adapter\n",
476 adapter
->tx_timeout_count
+ 1);
477 ixgbe_tx_timeout(adapter
->netdev
);
481 /* re-arm the interrupt */
482 if (count
>= tx_ring
->work_limit
)
483 ixgbe_irq_rearm_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
485 tx_ring
->total_bytes
+= total_bytes
;
486 tx_ring
->total_packets
+= total_packets
;
487 tx_ring
->stats
.packets
+= total_packets
;
488 tx_ring
->stats
.bytes
+= total_bytes
;
489 return (count
< tx_ring
->work_limit
);
492 #ifdef CONFIG_IXGBE_DCA
493 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
494 struct ixgbe_ring
*rx_ring
)
498 int q
= rx_ring
->reg_idx
;
500 if (rx_ring
->cpu
!= cpu
) {
501 rxctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
));
502 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
503 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
504 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
505 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
506 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
507 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
508 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
510 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
511 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
512 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
513 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
514 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
515 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
), rxctrl
);
521 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
522 struct ixgbe_ring
*tx_ring
)
526 int q
= tx_ring
->reg_idx
;
527 struct ixgbe_hw
*hw
= &adapter
->hw
;
529 if (tx_ring
->cpu
!= cpu
) {
530 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
531 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(q
));
532 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
533 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
534 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
535 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(q
), txctrl
);
536 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
537 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
));
538 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
539 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
540 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
541 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
542 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
), txctrl
);
549 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
553 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
556 /* always use CB2 mode, difference is masked in the CB driver */
557 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
559 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
560 adapter
->tx_ring
[i
]->cpu
= -1;
561 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[i
]);
563 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
564 adapter
->rx_ring
[i
]->cpu
= -1;
565 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[i
]);
569 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
571 struct net_device
*netdev
= dev_get_drvdata(dev
);
572 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
573 unsigned long event
= *(unsigned long *)data
;
576 case DCA_PROVIDER_ADD
:
577 /* if we're already enabled, don't do it again */
578 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
580 if (dca_add_requester(dev
) == 0) {
581 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
582 ixgbe_setup_dca(adapter
);
585 /* Fall Through since DCA is disabled. */
586 case DCA_PROVIDER_REMOVE
:
587 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
588 dca_remove_requester(dev
);
589 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
590 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
598 #endif /* CONFIG_IXGBE_DCA */
600 * ixgbe_receive_skb - Send a completed packet up the stack
601 * @adapter: board private structure
602 * @skb: packet to send up
603 * @status: hardware indication of status of receive
604 * @rx_ring: rx descriptor ring (for a specific queue) to setup
605 * @rx_desc: rx descriptor
607 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
608 struct sk_buff
*skb
, u8 status
,
609 struct ixgbe_ring
*ring
,
610 union ixgbe_adv_rx_desc
*rx_desc
)
612 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
613 struct napi_struct
*napi
= &q_vector
->napi
;
614 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
615 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
617 skb_record_rx_queue(skb
, ring
->queue_index
);
618 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
)) {
619 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
620 vlan_gro_receive(napi
, adapter
->vlgrp
, tag
, skb
);
622 napi_gro_receive(napi
, skb
);
624 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
625 vlan_hwaccel_rx(skb
, adapter
->vlgrp
, tag
);
632 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
633 * @adapter: address of board private structure
634 * @status_err: hardware indication of status of receive
635 * @skb: skb currently being received and modified
637 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
638 union ixgbe_adv_rx_desc
*rx_desc
,
641 u32 status_err
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
643 skb
->ip_summed
= CHECKSUM_NONE
;
645 /* Rx csum disabled */
646 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
649 /* if IP and error */
650 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
651 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
652 adapter
->hw_csum_rx_error
++;
656 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
659 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
660 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
663 * 82599 errata, UDP frames with a 0 checksum can be marked as
666 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
667 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
670 adapter
->hw_csum_rx_error
++;
674 /* It must be a TCP or UDP packet with a valid checksum */
675 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
678 static inline void ixgbe_release_rx_desc(struct ixgbe_hw
*hw
,
679 struct ixgbe_ring
*rx_ring
, u32 val
)
682 * Force memory writes to complete before letting h/w
683 * know there are new descriptors to fetch. (Only
684 * applicable for weak-ordered memory model archs,
688 IXGBE_WRITE_REG(hw
, IXGBE_RDT(rx_ring
->reg_idx
), val
);
692 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
693 * @adapter: address of board private structure
695 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter
*adapter
,
696 struct ixgbe_ring
*rx_ring
,
699 struct pci_dev
*pdev
= adapter
->pdev
;
700 union ixgbe_adv_rx_desc
*rx_desc
;
701 struct ixgbe_rx_buffer
*bi
;
704 i
= rx_ring
->next_to_use
;
705 bi
= &rx_ring
->rx_buffer_info
[i
];
707 while (cleaned_count
--) {
708 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
711 (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)) {
713 bi
->page
= alloc_page(GFP_ATOMIC
);
715 adapter
->alloc_rx_page_failed
++;
720 /* use a half page if we're re-using */
721 bi
->page_offset
^= (PAGE_SIZE
/ 2);
724 bi
->page_dma
= dma_map_page(&pdev
->dev
, bi
->page
,
732 /* netdev_alloc_skb reserves 32 bytes up front!! */
733 uint bufsz
= rx_ring
->rx_buf_len
+ SMP_CACHE_BYTES
;
734 skb
= netdev_alloc_skb(adapter
->netdev
, bufsz
);
737 adapter
->alloc_rx_buff_failed
++;
741 /* advance the data pointer to the next cache line */
742 skb_reserve(skb
, (PTR_ALIGN(skb
->data
, SMP_CACHE_BYTES
)
746 bi
->dma
= dma_map_single(&pdev
->dev
, skb
->data
,
750 /* Refresh the desc even if buffer_addrs didn't change because
751 * each write-back erases this info. */
752 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
753 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
754 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
756 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
760 if (i
== rx_ring
->count
)
762 bi
= &rx_ring
->rx_buffer_info
[i
];
766 if (rx_ring
->next_to_use
!= i
) {
767 rx_ring
->next_to_use
= i
;
769 i
= (rx_ring
->count
- 1);
771 ixgbe_release_rx_desc(&adapter
->hw
, rx_ring
, i
);
775 static inline u16
ixgbe_get_hdr_info(union ixgbe_adv_rx_desc
*rx_desc
)
777 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
;
780 static inline u16
ixgbe_get_pkt_info(union ixgbe_adv_rx_desc
*rx_desc
)
782 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
785 static inline u32
ixgbe_get_rsc_count(union ixgbe_adv_rx_desc
*rx_desc
)
787 return (le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
788 IXGBE_RXDADV_RSCCNT_MASK
) >>
789 IXGBE_RXDADV_RSCCNT_SHIFT
;
793 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
794 * @skb: pointer to the last skb in the rsc queue
795 * @count: pointer to number of packets coalesced in this context
797 * This function changes a queue full of hw rsc buffers into a completed
798 * packet. It uses the ->prev pointers to find the first packet and then
799 * turns it into the frag list owner.
801 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
,
804 unsigned int frag_list_size
= 0;
807 struct sk_buff
*prev
= skb
->prev
;
808 frag_list_size
+= skb
->len
;
814 skb_shinfo(skb
)->frag_list
= skb
->next
;
816 skb
->len
+= frag_list_size
;
817 skb
->data_len
+= frag_list_size
;
818 skb
->truesize
+= frag_list_size
;
822 struct ixgbe_rsc_cb
{
826 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
828 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
829 struct ixgbe_ring
*rx_ring
,
830 int *work_done
, int work_to_do
)
832 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
833 struct net_device
*netdev
= adapter
->netdev
;
834 struct pci_dev
*pdev
= adapter
->pdev
;
835 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
836 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
838 unsigned int i
, rsc_count
= 0;
841 bool cleaned
= false;
842 int cleaned_count
= 0;
843 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
846 #endif /* IXGBE_FCOE */
848 i
= rx_ring
->next_to_clean
;
849 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
850 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
851 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
853 while (staterr
& IXGBE_RXD_STAT_DD
) {
855 if (*work_done
>= work_to_do
)
859 rmb(); /* read descriptor and rx_buffer_info after status DD */
860 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
861 hdr_info
= le16_to_cpu(ixgbe_get_hdr_info(rx_desc
));
862 len
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
863 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
864 if (len
> IXGBE_RX_HDR_SIZE
)
865 len
= IXGBE_RX_HDR_SIZE
;
866 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
868 len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
872 skb
= rx_buffer_info
->skb
;
874 rx_buffer_info
->skb
= NULL
;
876 if (rx_buffer_info
->dma
) {
877 if ((adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
878 (!(staterr
& IXGBE_RXD_STAT_EOP
)) &&
881 * When HWRSC is enabled, delay unmapping
882 * of the first packet. It carries the
883 * header information, HW may still
884 * access the header after the writeback.
885 * Only unmap it when EOP is reached
887 IXGBE_RSC_CB(skb
)->dma
= rx_buffer_info
->dma
;
889 dma_unmap_single(&pdev
->dev
,
893 rx_buffer_info
->dma
= 0;
898 dma_unmap_page(&pdev
->dev
, rx_buffer_info
->page_dma
,
899 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
900 rx_buffer_info
->page_dma
= 0;
901 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
902 rx_buffer_info
->page
,
903 rx_buffer_info
->page_offset
,
906 if ((rx_ring
->rx_buf_len
> (PAGE_SIZE
/ 2)) ||
907 (page_count(rx_buffer_info
->page
) != 1))
908 rx_buffer_info
->page
= NULL
;
910 get_page(rx_buffer_info
->page
);
912 skb
->len
+= upper_len
;
913 skb
->data_len
+= upper_len
;
914 skb
->truesize
+= upper_len
;
918 if (i
== rx_ring
->count
)
921 next_rxd
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
925 if (adapter
->flags2
& IXGBE_FLAG2_RSC_CAPABLE
)
926 rsc_count
= ixgbe_get_rsc_count(rx_desc
);
929 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
930 IXGBE_RXDADV_NEXTP_SHIFT
;
931 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
933 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
936 if (staterr
& IXGBE_RXD_STAT_EOP
) {
938 skb
= ixgbe_transform_rsc_queue(skb
, &(rx_ring
->rsc_count
));
939 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
940 if (IXGBE_RSC_CB(skb
)->dma
) {
941 dma_unmap_single(&pdev
->dev
,
942 IXGBE_RSC_CB(skb
)->dma
,
945 IXGBE_RSC_CB(skb
)->dma
= 0;
947 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)
948 rx_ring
->rsc_count
+= skb_shinfo(skb
)->nr_frags
;
950 rx_ring
->rsc_count
++;
951 rx_ring
->rsc_flush
++;
953 rx_ring
->stats
.packets
++;
954 rx_ring
->stats
.bytes
+= skb
->len
;
956 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
957 rx_buffer_info
->skb
= next_buffer
->skb
;
958 rx_buffer_info
->dma
= next_buffer
->dma
;
959 next_buffer
->skb
= skb
;
960 next_buffer
->dma
= 0;
962 skb
->next
= next_buffer
->skb
;
963 skb
->next
->prev
= skb
;
965 rx_ring
->non_eop_descs
++;
969 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
970 dev_kfree_skb_irq(skb
);
974 ixgbe_rx_checksum(adapter
, rx_desc
, skb
);
976 /* probably a little skewed due to removing CRC */
977 total_rx_bytes
+= skb
->len
;
980 skb
->protocol
= eth_type_trans(skb
, adapter
->netdev
);
982 /* if ddp, not passing to ULD unless for FCP_RSP or error */
983 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
984 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
);
988 #endif /* IXGBE_FCOE */
989 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
992 rx_desc
->wb
.upper
.status_error
= 0;
994 /* return some buffers to hardware, one at a time is too slow */
995 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
996 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
1000 /* use prefetched values */
1002 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1004 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1007 rx_ring
->next_to_clean
= i
;
1008 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
1011 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
1014 /* include DDPed FCoE data */
1015 if (ddp_bytes
> 0) {
1018 mss
= adapter
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
1019 sizeof(struct fc_frame_header
) -
1020 sizeof(struct fcoe_crc_eof
);
1023 total_rx_bytes
+= ddp_bytes
;
1024 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
1026 #endif /* IXGBE_FCOE */
1028 rx_ring
->total_packets
+= total_rx_packets
;
1029 rx_ring
->total_bytes
+= total_rx_bytes
;
1030 netdev
->stats
.rx_bytes
+= total_rx_bytes
;
1031 netdev
->stats
.rx_packets
+= total_rx_packets
;
1036 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1038 * ixgbe_configure_msix - Configure MSI-X hardware
1039 * @adapter: board private structure
1041 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1044 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1046 struct ixgbe_q_vector
*q_vector
;
1047 int i
, j
, q_vectors
, v_idx
, r_idx
;
1050 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1053 * Populate the IVAR table and set the ITR values to the
1054 * corresponding register.
1056 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1057 q_vector
= adapter
->q_vector
[v_idx
];
1058 /* XXX for_each_set_bit(...) */
1059 r_idx
= find_first_bit(q_vector
->rxr_idx
,
1060 adapter
->num_rx_queues
);
1062 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1063 j
= adapter
->rx_ring
[r_idx
]->reg_idx
;
1064 ixgbe_set_ivar(adapter
, 0, j
, v_idx
);
1065 r_idx
= find_next_bit(q_vector
->rxr_idx
,
1066 adapter
->num_rx_queues
,
1069 r_idx
= find_first_bit(q_vector
->txr_idx
,
1070 adapter
->num_tx_queues
);
1072 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1073 j
= adapter
->tx_ring
[r_idx
]->reg_idx
;
1074 ixgbe_set_ivar(adapter
, 1, j
, v_idx
);
1075 r_idx
= find_next_bit(q_vector
->txr_idx
,
1076 adapter
->num_tx_queues
,
1080 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
1082 q_vector
->eitr
= adapter
->tx_eitr_param
;
1083 else if (q_vector
->rxr_count
)
1085 q_vector
->eitr
= adapter
->rx_eitr_param
;
1087 ixgbe_write_eitr(q_vector
);
1090 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
1091 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1093 else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
1094 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1095 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1097 /* set up to autoclear timer, and the vectors */
1098 mask
= IXGBE_EIMS_ENABLE_MASK
;
1099 if (adapter
->num_vfs
)
1100 mask
&= ~(IXGBE_EIMS_OTHER
|
1101 IXGBE_EIMS_MAILBOX
|
1104 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1105 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1108 enum latency_range
{
1112 latency_invalid
= 255
1116 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1117 * @adapter: pointer to adapter
1118 * @eitr: eitr setting (ints per sec) to give last timeslice
1119 * @itr_setting: current throttle rate in ints/second
1120 * @packets: the number of packets during this measurement interval
1121 * @bytes: the number of bytes during this measurement interval
1123 * Stores a new ITR value based on packets and byte
1124 * counts during the last interrupt. The advantage of per interrupt
1125 * computation is faster updates and more accurate ITR for the current
1126 * traffic pattern. Constants in this function were computed
1127 * based on theoretical maximum wire speed and thresholds were set based
1128 * on testing data as well as attempting to minimize response time
1129 * while increasing bulk throughput.
1130 * this functionality is controlled by the InterruptThrottleRate module
1131 * parameter (see ixgbe_param.c)
1133 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
1134 u32 eitr
, u8 itr_setting
,
1135 int packets
, int bytes
)
1137 unsigned int retval
= itr_setting
;
1142 goto update_itr_done
;
1145 /* simple throttlerate management
1146 * 0-20MB/s lowest (100000 ints/s)
1147 * 20-100MB/s low (20000 ints/s)
1148 * 100-1249MB/s bulk (8000 ints/s)
1150 /* what was last interrupt timeslice? */
1151 timepassed_us
= 1000000/eitr
;
1152 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1154 switch (itr_setting
) {
1155 case lowest_latency
:
1156 if (bytes_perint
> adapter
->eitr_low
)
1157 retval
= low_latency
;
1160 if (bytes_perint
> adapter
->eitr_high
)
1161 retval
= bulk_latency
;
1162 else if (bytes_perint
<= adapter
->eitr_low
)
1163 retval
= lowest_latency
;
1166 if (bytes_perint
<= adapter
->eitr_high
)
1167 retval
= low_latency
;
1176 * ixgbe_write_eitr - write EITR register in hardware specific way
1177 * @q_vector: structure containing interrupt and ring information
1179 * This function is made to be called by ethtool and by the driver
1180 * when it needs to update EITR registers at runtime. Hardware
1181 * specific quirks/differences are taken care of here.
1183 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1185 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1186 struct ixgbe_hw
*hw
= &adapter
->hw
;
1187 int v_idx
= q_vector
->v_idx
;
1188 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1190 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1191 /* must write high and low 16 bits to reset counter */
1192 itr_reg
|= (itr_reg
<< 16);
1193 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1195 * 82599 can support a value of zero, so allow it for
1196 * max interrupt rate, but there is an errata where it can
1197 * not be zero with RSC
1200 !(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
))
1204 * set the WDIS bit to not clear the timer bits and cause an
1205 * immediate assertion of the interrupt
1207 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1209 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1212 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
1214 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1216 u8 current_itr
, ret_itr
;
1218 struct ixgbe_ring
*rx_ring
, *tx_ring
;
1220 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1221 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1222 tx_ring
= adapter
->tx_ring
[r_idx
];
1223 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1225 tx_ring
->total_packets
,
1226 tx_ring
->total_bytes
);
1227 /* if the result for this queue would decrease interrupt
1228 * rate for this vector then use that result */
1229 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1230 q_vector
->tx_itr
- 1 : ret_itr
);
1231 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1235 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1236 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1237 rx_ring
= adapter
->rx_ring
[r_idx
];
1238 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1240 rx_ring
->total_packets
,
1241 rx_ring
->total_bytes
);
1242 /* if the result for this queue would decrease interrupt
1243 * rate for this vector then use that result */
1244 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1245 q_vector
->rx_itr
- 1 : ret_itr
);
1246 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1250 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1252 switch (current_itr
) {
1253 /* counts and packets in update_itr are dependent on these numbers */
1254 case lowest_latency
:
1258 new_itr
= 20000; /* aka hwitr = ~200 */
1266 if (new_itr
!= q_vector
->eitr
) {
1267 /* do an exponential smoothing */
1268 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1270 /* save the algorithm value here, not the smoothed one */
1271 q_vector
->eitr
= new_itr
;
1273 ixgbe_write_eitr(q_vector
);
1279 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1281 struct ixgbe_hw
*hw
= &adapter
->hw
;
1283 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1284 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1285 DPRINTK(PROBE
, CRIT
, "Fan has stopped, replace the adapter\n");
1286 /* write to clear the interrupt */
1287 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1291 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1293 struct ixgbe_hw
*hw
= &adapter
->hw
;
1295 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1296 /* Clear the interrupt */
1297 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1298 schedule_work(&adapter
->multispeed_fiber_task
);
1299 } else if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1300 /* Clear the interrupt */
1301 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1302 schedule_work(&adapter
->sfp_config_module_task
);
1304 /* Interrupt isn't for us... */
1309 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1311 struct ixgbe_hw
*hw
= &adapter
->hw
;
1314 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1315 adapter
->link_check_timeout
= jiffies
;
1316 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1317 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1318 IXGBE_WRITE_FLUSH(hw
);
1319 schedule_work(&adapter
->watchdog_task
);
1323 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1325 struct net_device
*netdev
= data
;
1326 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1327 struct ixgbe_hw
*hw
= &adapter
->hw
;
1331 * Workaround for Silicon errata. Use clear-by-write instead
1332 * of clear-by-read. Reading with EICS will return the
1333 * interrupt causes without clearing, which later be done
1334 * with the write to EICR.
1336 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1337 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1339 if (eicr
& IXGBE_EICR_LSC
)
1340 ixgbe_check_lsc(adapter
);
1342 if (eicr
& IXGBE_EICR_MAILBOX
)
1343 ixgbe_msg_task(adapter
);
1345 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
1346 ixgbe_check_fan_failure(adapter
, eicr
);
1348 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1349 ixgbe_check_sfp_event(adapter
, eicr
);
1351 /* Handle Flow Director Full threshold interrupt */
1352 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1354 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_FLOW_DIR
);
1355 /* Disable transmits before FDIR Re-initialization */
1356 netif_tx_stop_all_queues(netdev
);
1357 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1358 struct ixgbe_ring
*tx_ring
=
1359 adapter
->tx_ring
[i
];
1360 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE
,
1361 &tx_ring
->reinit_state
))
1362 schedule_work(&adapter
->fdir_reinit_task
);
1366 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1367 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_OTHER
);
1372 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1377 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1378 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1379 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1381 mask
= (qmask
& 0xFFFFFFFF);
1382 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(0), mask
);
1383 mask
= (qmask
>> 32);
1384 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(1), mask
);
1386 /* skip the flush */
1389 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1394 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1395 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1396 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, mask
);
1398 mask
= (qmask
& 0xFFFFFFFF);
1399 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), mask
);
1400 mask
= (qmask
>> 32);
1401 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), mask
);
1403 /* skip the flush */
1406 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1408 struct ixgbe_q_vector
*q_vector
= data
;
1409 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1410 struct ixgbe_ring
*tx_ring
;
1413 if (!q_vector
->txr_count
)
1416 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1417 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1418 tx_ring
= adapter
->tx_ring
[r_idx
];
1419 tx_ring
->total_bytes
= 0;
1420 tx_ring
->total_packets
= 0;
1421 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1425 /* EIAM disabled interrupts (on this vector) for us */
1426 napi_schedule(&q_vector
->napi
);
1432 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1434 * @data: pointer to our q_vector struct for this interrupt vector
1436 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
1438 struct ixgbe_q_vector
*q_vector
= data
;
1439 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1440 struct ixgbe_ring
*rx_ring
;
1444 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1445 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1446 rx_ring
= adapter
->rx_ring
[r_idx
];
1447 rx_ring
->total_bytes
= 0;
1448 rx_ring
->total_packets
= 0;
1449 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1453 if (!q_vector
->rxr_count
)
1456 /* disable interrupts on this vector only */
1457 /* EIAM disabled interrupts (on this vector) for us */
1458 napi_schedule(&q_vector
->napi
);
1463 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
1465 struct ixgbe_q_vector
*q_vector
= data
;
1466 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1467 struct ixgbe_ring
*ring
;
1471 if (!q_vector
->txr_count
&& !q_vector
->rxr_count
)
1474 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1475 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1476 ring
= adapter
->tx_ring
[r_idx
];
1477 ring
->total_bytes
= 0;
1478 ring
->total_packets
= 0;
1479 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1483 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1484 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1485 ring
= adapter
->rx_ring
[r_idx
];
1486 ring
->total_bytes
= 0;
1487 ring
->total_packets
= 0;
1488 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1492 /* EIAM disabled interrupts (on this vector) for us */
1493 napi_schedule(&q_vector
->napi
);
1499 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1500 * @napi: napi struct with our devices info in it
1501 * @budget: amount of work driver is allowed to do this pass, in packets
1503 * This function is optimized for cleaning one queue only on a single
1506 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
1508 struct ixgbe_q_vector
*q_vector
=
1509 container_of(napi
, struct ixgbe_q_vector
, napi
);
1510 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1511 struct ixgbe_ring
*rx_ring
= NULL
;
1515 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1516 rx_ring
= adapter
->rx_ring
[r_idx
];
1517 #ifdef CONFIG_IXGBE_DCA
1518 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1519 ixgbe_update_rx_dca(adapter
, rx_ring
);
1522 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
1524 /* If all Rx work done, exit the polling mode */
1525 if (work_done
< budget
) {
1526 napi_complete(napi
);
1527 if (adapter
->rx_itr_setting
& 1)
1528 ixgbe_set_itr_msix(q_vector
);
1529 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1530 ixgbe_irq_enable_queues(adapter
,
1531 ((u64
)1 << q_vector
->v_idx
));
1538 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1539 * @napi: napi struct with our devices info in it
1540 * @budget: amount of work driver is allowed to do this pass, in packets
1542 * This function will clean more than one rx queue associated with a
1545 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
1547 struct ixgbe_q_vector
*q_vector
=
1548 container_of(napi
, struct ixgbe_q_vector
, napi
);
1549 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1550 struct ixgbe_ring
*ring
= NULL
;
1551 int work_done
= 0, i
;
1553 bool tx_clean_complete
= true;
1555 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1556 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1557 ring
= adapter
->tx_ring
[r_idx
];
1558 #ifdef CONFIG_IXGBE_DCA
1559 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1560 ixgbe_update_tx_dca(adapter
, ring
);
1562 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
1563 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1567 /* attempt to distribute budget to each queue fairly, but don't allow
1568 * the budget to go below 1 because we'll exit polling */
1569 budget
/= (q_vector
->rxr_count
?: 1);
1570 budget
= max(budget
, 1);
1571 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1572 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1573 ring
= adapter
->rx_ring
[r_idx
];
1574 #ifdef CONFIG_IXGBE_DCA
1575 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1576 ixgbe_update_rx_dca(adapter
, ring
);
1578 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
1579 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1583 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1584 ring
= adapter
->rx_ring
[r_idx
];
1585 /* If all Rx work done, exit the polling mode */
1586 if (work_done
< budget
) {
1587 napi_complete(napi
);
1588 if (adapter
->rx_itr_setting
& 1)
1589 ixgbe_set_itr_msix(q_vector
);
1590 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1591 ixgbe_irq_enable_queues(adapter
,
1592 ((u64
)1 << q_vector
->v_idx
));
1600 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1601 * @napi: napi struct with our devices info in it
1602 * @budget: amount of work driver is allowed to do this pass, in packets
1604 * This function is optimized for cleaning one queue only on a single
1607 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
1609 struct ixgbe_q_vector
*q_vector
=
1610 container_of(napi
, struct ixgbe_q_vector
, napi
);
1611 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1612 struct ixgbe_ring
*tx_ring
= NULL
;
1616 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1617 tx_ring
= adapter
->tx_ring
[r_idx
];
1618 #ifdef CONFIG_IXGBE_DCA
1619 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1620 ixgbe_update_tx_dca(adapter
, tx_ring
);
1623 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
1626 /* If all Tx work done, exit the polling mode */
1627 if (work_done
< budget
) {
1628 napi_complete(napi
);
1629 if (adapter
->tx_itr_setting
& 1)
1630 ixgbe_set_itr_msix(q_vector
);
1631 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1632 ixgbe_irq_enable_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
1638 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
1641 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1643 set_bit(r_idx
, q_vector
->rxr_idx
);
1644 q_vector
->rxr_count
++;
1647 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
1650 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1652 set_bit(t_idx
, q_vector
->txr_idx
);
1653 q_vector
->txr_count
++;
1657 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1658 * @adapter: board private structure to initialize
1659 * @vectors: allotted vector count for descriptor rings
1661 * This function maps descriptor rings to the queue-specific vectors
1662 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1663 * one vector per ring/queue, but on a constrained vector budget, we
1664 * group the rings as "efficiently" as possible. You would add new
1665 * mapping configurations in here.
1667 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
,
1671 int rxr_idx
= 0, txr_idx
= 0;
1672 int rxr_remaining
= adapter
->num_rx_queues
;
1673 int txr_remaining
= adapter
->num_tx_queues
;
1678 /* No mapping required if MSI-X is disabled. */
1679 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
1683 * The ideal configuration...
1684 * We have enough vectors to map one per queue.
1686 if (vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
1687 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
1688 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
1690 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
1691 map_vector_to_txq(adapter
, v_start
, txr_idx
);
1697 * If we don't have enough vectors for a 1-to-1
1698 * mapping, we'll have to group them so there are
1699 * multiple queues per vector.
1701 /* Re-adjusting *qpv takes care of the remainder. */
1702 for (i
= v_start
; i
< vectors
; i
++) {
1703 rqpv
= DIV_ROUND_UP(rxr_remaining
, vectors
- i
);
1704 for (j
= 0; j
< rqpv
; j
++) {
1705 map_vector_to_rxq(adapter
, i
, rxr_idx
);
1710 for (i
= v_start
; i
< vectors
; i
++) {
1711 tqpv
= DIV_ROUND_UP(txr_remaining
, vectors
- i
);
1712 for (j
= 0; j
< tqpv
; j
++) {
1713 map_vector_to_txq(adapter
, i
, txr_idx
);
1724 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1725 * @adapter: board private structure
1727 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1728 * interrupts from the kernel.
1730 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
1732 struct net_device
*netdev
= adapter
->netdev
;
1733 irqreturn_t (*handler
)(int, void *);
1734 int i
, vector
, q_vectors
, err
;
1737 /* Decrement for Other and TCP Timer vectors */
1738 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1740 /* Map the Tx/Rx rings to the vectors we were allotted. */
1741 err
= ixgbe_map_rings_to_vectors(adapter
, q_vectors
);
1745 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1746 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1747 &ixgbe_msix_clean_many)
1748 for (vector
= 0; vector
< q_vectors
; vector
++) {
1749 handler
= SET_HANDLER(adapter
->q_vector
[vector
]);
1751 if(handler
== &ixgbe_msix_clean_rx
) {
1752 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1753 netdev
->name
, "rx", ri
++);
1755 else if(handler
== &ixgbe_msix_clean_tx
) {
1756 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1757 netdev
->name
, "tx", ti
++);
1760 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1761 netdev
->name
, "TxRx", vector
);
1763 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
1764 handler
, 0, adapter
->name
[vector
],
1765 adapter
->q_vector
[vector
]);
1768 "request_irq failed for MSIX interrupt "
1769 "Error: %d\n", err
);
1770 goto free_queue_irqs
;
1774 sprintf(adapter
->name
[vector
], "%s:lsc", netdev
->name
);
1775 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
1776 ixgbe_msix_lsc
, 0, adapter
->name
[vector
], netdev
);
1779 "request_irq for msix_lsc failed: %d\n", err
);
1780 goto free_queue_irqs
;
1786 for (i
= vector
- 1; i
>= 0; i
--)
1787 free_irq(adapter
->msix_entries
[--vector
].vector
,
1788 adapter
->q_vector
[i
]);
1789 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
1790 pci_disable_msix(adapter
->pdev
);
1791 kfree(adapter
->msix_entries
);
1792 adapter
->msix_entries
= NULL
;
1797 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
1799 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
1801 u32 new_itr
= q_vector
->eitr
;
1802 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[0];
1803 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[0];
1805 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
1807 tx_ring
->total_packets
,
1808 tx_ring
->total_bytes
);
1809 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
1811 rx_ring
->total_packets
,
1812 rx_ring
->total_bytes
);
1814 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1816 switch (current_itr
) {
1817 /* counts and packets in update_itr are dependent on these numbers */
1818 case lowest_latency
:
1822 new_itr
= 20000; /* aka hwitr = ~200 */
1831 if (new_itr
!= q_vector
->eitr
) {
1832 /* do an exponential smoothing */
1833 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1835 /* save the algorithm value here, not the smoothed one */
1836 q_vector
->eitr
= new_itr
;
1838 ixgbe_write_eitr(q_vector
);
1845 * ixgbe_irq_enable - Enable default interrupt generation settings
1846 * @adapter: board private structure
1848 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
)
1852 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
1853 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
1854 mask
|= IXGBE_EIMS_GPI_SDP1
;
1855 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1856 mask
|= IXGBE_EIMS_ECC
;
1857 mask
|= IXGBE_EIMS_GPI_SDP1
;
1858 mask
|= IXGBE_EIMS_GPI_SDP2
;
1859 if (adapter
->num_vfs
)
1860 mask
|= IXGBE_EIMS_MAILBOX
;
1862 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
1863 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
1864 mask
|= IXGBE_EIMS_FLOW_DIR
;
1866 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1867 ixgbe_irq_enable_queues(adapter
, ~0);
1868 IXGBE_WRITE_FLUSH(&adapter
->hw
);
1870 if (adapter
->num_vfs
> 32) {
1871 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
1872 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
1877 * ixgbe_intr - legacy mode Interrupt Handler
1878 * @irq: interrupt number
1879 * @data: pointer to a network interface device structure
1881 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
1883 struct net_device
*netdev
= data
;
1884 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1885 struct ixgbe_hw
*hw
= &adapter
->hw
;
1886 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
1890 * Workaround for silicon errata. Mask the interrupts
1891 * before the read of EICR.
1893 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
1895 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1896 * therefore no explict interrupt disable is necessary */
1897 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
1899 /* shared interrupt alert!
1900 * make sure interrupts are enabled because the read will
1901 * have disabled interrupts due to EIAM */
1902 ixgbe_irq_enable(adapter
);
1903 return IRQ_NONE
; /* Not our interrupt */
1906 if (eicr
& IXGBE_EICR_LSC
)
1907 ixgbe_check_lsc(adapter
);
1909 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
1910 ixgbe_check_sfp_event(adapter
, eicr
);
1912 ixgbe_check_fan_failure(adapter
, eicr
);
1914 if (napi_schedule_prep(&(q_vector
->napi
))) {
1915 adapter
->tx_ring
[0]->total_packets
= 0;
1916 adapter
->tx_ring
[0]->total_bytes
= 0;
1917 adapter
->rx_ring
[0]->total_packets
= 0;
1918 adapter
->rx_ring
[0]->total_bytes
= 0;
1919 /* would disable interrupts here but EIAM disabled it */
1920 __napi_schedule(&(q_vector
->napi
));
1926 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
1928 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1930 for (i
= 0; i
< q_vectors
; i
++) {
1931 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
1932 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
1933 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
1934 q_vector
->rxr_count
= 0;
1935 q_vector
->txr_count
= 0;
1940 * ixgbe_request_irq - initialize interrupts
1941 * @adapter: board private structure
1943 * Attempts to configure interrupts using the best available
1944 * capabilities of the hardware and kernel.
1946 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
1948 struct net_device
*netdev
= adapter
->netdev
;
1951 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1952 err
= ixgbe_request_msix_irqs(adapter
);
1953 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
1954 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
1955 netdev
->name
, netdev
);
1957 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
1958 netdev
->name
, netdev
);
1962 DPRINTK(PROBE
, ERR
, "request_irq failed, Error %d\n", err
);
1967 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
1969 struct net_device
*netdev
= adapter
->netdev
;
1971 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1974 q_vectors
= adapter
->num_msix_vectors
;
1977 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
1980 for (; i
>= 0; i
--) {
1981 free_irq(adapter
->msix_entries
[i
].vector
,
1982 adapter
->q_vector
[i
]);
1985 ixgbe_reset_q_vectors(adapter
);
1987 free_irq(adapter
->pdev
->irq
, netdev
);
1992 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1993 * @adapter: board private structure
1995 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
1997 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1998 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
2000 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
2001 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
2002 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
2003 if (adapter
->num_vfs
> 32)
2004 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
2006 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2007 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2009 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
2010 synchronize_irq(adapter
->msix_entries
[i
].vector
);
2012 synchronize_irq(adapter
->pdev
->irq
);
2017 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2020 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
2022 struct ixgbe_hw
*hw
= &adapter
->hw
;
2024 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
2025 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
2027 ixgbe_set_ivar(adapter
, 0, 0, 0);
2028 ixgbe_set_ivar(adapter
, 1, 0, 0);
2030 map_vector_to_rxq(adapter
, 0, 0);
2031 map_vector_to_txq(adapter
, 0, 0);
2033 DPRINTK(HW
, INFO
, "Legacy interrupt IVAR setup done\n");
2037 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2038 * @adapter: board private structure
2040 * Configure the Tx unit of the MAC after a reset.
2042 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2045 struct ixgbe_hw
*hw
= &adapter
->hw
;
2046 u32 i
, j
, tdlen
, txctrl
;
2048 /* Setup the HW Tx Head and Tail descriptor pointers */
2049 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2050 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
2053 tdlen
= ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
2054 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(j
),
2055 (tdba
& DMA_BIT_MASK(32)));
2056 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(j
), (tdba
>> 32));
2057 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(j
), tdlen
);
2058 IXGBE_WRITE_REG(hw
, IXGBE_TDH(j
), 0);
2059 IXGBE_WRITE_REG(hw
, IXGBE_TDT(j
), 0);
2060 adapter
->tx_ring
[i
]->head
= IXGBE_TDH(j
);
2061 adapter
->tx_ring
[i
]->tail
= IXGBE_TDT(j
);
2063 * Disable Tx Head Writeback RO bit, since this hoses
2064 * bookkeeping if things aren't delivered in order.
2066 switch (hw
->mac
.type
) {
2067 case ixgbe_mac_82598EB
:
2068 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(j
));
2070 case ixgbe_mac_82599EB
:
2072 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(j
));
2075 txctrl
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
2076 switch (hw
->mac
.type
) {
2077 case ixgbe_mac_82598EB
:
2078 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(j
), txctrl
);
2080 case ixgbe_mac_82599EB
:
2082 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(j
), txctrl
);
2087 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2091 /* disable the arbiter while setting MTQC */
2092 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2093 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2094 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2096 /* set transmit pool layout */
2097 mask
= (IXGBE_FLAG_SRIOV_ENABLED
| IXGBE_FLAG_DCB_ENABLED
);
2098 switch (adapter
->flags
& mask
) {
2100 case (IXGBE_FLAG_SRIOV_ENABLED
):
2101 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2102 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2105 case (IXGBE_FLAG_DCB_ENABLED
):
2106 /* We enable 8 traffic classes, DCB only */
2107 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2108 (IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
));
2112 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, IXGBE_MTQC_64Q_1PB
);
2116 /* re-eable the arbiter */
2117 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2118 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2122 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2124 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2125 struct ixgbe_ring
*rx_ring
)
2129 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2131 index
= rx_ring
->reg_idx
;
2132 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2134 mask
= (unsigned long) feature
[RING_F_RSS
].mask
;
2135 index
= index
& mask
;
2137 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(index
));
2139 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2140 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2142 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2143 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2145 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2146 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2147 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2149 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2151 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2153 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2154 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2155 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2158 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(index
), srrctl
);
2161 static u32
ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2166 if (!(adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
2169 mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2170 #ifdef CONFIG_IXGBE_DCB
2171 | IXGBE_FLAG_DCB_ENABLED
2173 | IXGBE_FLAG_SRIOV_ENABLED
2177 case (IXGBE_FLAG_RSS_ENABLED
):
2178 mrqc
= IXGBE_MRQC_RSSEN
;
2180 case (IXGBE_FLAG_SRIOV_ENABLED
):
2181 mrqc
= IXGBE_MRQC_VMDQEN
;
2183 #ifdef CONFIG_IXGBE_DCB
2184 case (IXGBE_FLAG_DCB_ENABLED
):
2185 mrqc
= IXGBE_MRQC_RT8TCEN
;
2187 #endif /* CONFIG_IXGBE_DCB */
2196 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2197 * @adapter: address of board private structure
2198 * @index: index of ring to set
2200 static void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
, int index
)
2202 struct ixgbe_ring
*rx_ring
;
2203 struct ixgbe_hw
*hw
= &adapter
->hw
;
2208 rx_ring
= adapter
->rx_ring
[index
];
2209 j
= rx_ring
->reg_idx
;
2210 rx_buf_len
= rx_ring
->rx_buf_len
;
2211 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(j
));
2212 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2214 * we must limit the number of descriptors so that the
2215 * total size of max desc * buf_len is not greater
2218 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2219 #if (MAX_SKB_FRAGS > 16)
2220 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2221 #elif (MAX_SKB_FRAGS > 8)
2222 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2223 #elif (MAX_SKB_FRAGS > 4)
2224 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2226 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2229 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2230 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2231 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2232 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2234 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2236 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(j
), rscctrl
);
2240 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2241 * @adapter: board private structure
2243 * Configure the Rx unit of the MAC after a reset.
2245 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
2248 struct ixgbe_hw
*hw
= &adapter
->hw
;
2249 struct ixgbe_ring
*rx_ring
;
2250 struct net_device
*netdev
= adapter
->netdev
;
2251 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2253 u32 rdlen
, rxctrl
, rxcsum
;
2254 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2255 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2256 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2258 u32 reta
= 0, mrqc
= 0;
2262 /* Decide whether to use packet split mode or not */
2263 /* Do not use packet split if we're in SR-IOV Mode */
2264 if (!adapter
->num_vfs
)
2265 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
2267 /* Set the RX buffer length according to the mode */
2268 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
2269 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
2270 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2271 /* PSRTYPE must be initialized in 82599 */
2272 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
2273 IXGBE_PSRTYPE_UDPHDR
|
2274 IXGBE_PSRTYPE_IPV4HDR
|
2275 IXGBE_PSRTYPE_IPV6HDR
|
2276 IXGBE_PSRTYPE_L2HDR
;
2278 IXGBE_PSRTYPE(adapter
->num_vfs
),
2282 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
2283 (netdev
->mtu
<= ETH_DATA_LEN
))
2284 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
2286 rx_buf_len
= ALIGN(max_frame
, 1024);
2289 fctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_FCTRL
);
2290 fctrl
|= IXGBE_FCTRL_BAM
;
2291 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
2292 fctrl
|= IXGBE_FCTRL_PMCF
;
2293 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_FCTRL
, fctrl
);
2295 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
2296 if (adapter
->netdev
->mtu
<= ETH_DATA_LEN
)
2297 hlreg0
&= ~IXGBE_HLREG0_JUMBOEN
;
2299 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2301 if (netdev
->features
& NETIF_F_FCOE_MTU
)
2302 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2304 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
2306 rdlen
= adapter
->rx_ring
[0]->count
* sizeof(union ixgbe_adv_rx_desc
);
2307 /* disable receives while setting up the descriptors */
2308 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2309 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
2312 * Setup the HW Rx Head and Tail Descriptor Pointers and
2313 * the Base and Length of the Rx Descriptor Ring
2315 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2316 rx_ring
= adapter
->rx_ring
[i
];
2317 rdba
= rx_ring
->dma
;
2318 j
= rx_ring
->reg_idx
;
2319 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(j
), (rdba
& DMA_BIT_MASK(32)));
2320 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(j
), (rdba
>> 32));
2321 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(j
), rdlen
);
2322 IXGBE_WRITE_REG(hw
, IXGBE_RDH(j
), 0);
2323 IXGBE_WRITE_REG(hw
, IXGBE_RDT(j
), 0);
2324 rx_ring
->head
= IXGBE_RDH(j
);
2325 rx_ring
->tail
= IXGBE_RDT(j
);
2326 rx_ring
->rx_buf_len
= rx_buf_len
;
2328 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
2329 rx_ring
->flags
|= IXGBE_RING_RX_PS_ENABLED
;
2331 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2334 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
2335 struct ixgbe_ring_feature
*f
;
2336 f
= &adapter
->ring_feature
[RING_F_FCOE
];
2337 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
2338 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2339 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
2340 rx_ring
->rx_buf_len
=
2341 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2345 #endif /* IXGBE_FCOE */
2346 ixgbe_configure_srrctl(adapter
, rx_ring
);
2349 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2351 * For VMDq support of different descriptor types or
2352 * buffer sizes through the use of multiple SRRCTL
2353 * registers, RDRXCTL.MVMEN must be set to 1
2355 * also, the manual doesn't mention it clearly but DCA hints
2356 * will only use queue 0's tags unless this bit is set. Side
2357 * effects of setting this bit are only that SRRCTL must be
2358 * fully programmed [0..15]
2360 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2361 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
2362 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2365 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2367 u32 reg_offset
, vf_shift
;
2368 u32 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2369 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
2370 | IXGBE_VT_CTL_REPLEN
;
2371 vt_reg_bits
|= (adapter
->num_vfs
<<
2372 IXGBE_VT_CTL_POOL_SHIFT
);
2373 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
2374 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, 0);
2376 vf_shift
= adapter
->num_vfs
% 32;
2377 reg_offset
= adapter
->num_vfs
/ 32;
2378 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(0), 0);
2379 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(1), 0);
2380 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(0), 0);
2381 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(1), 0);
2382 /* Enable only the PF's pool for Tx/Rx */
2383 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
2384 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
2385 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
2386 ixgbe_set_vmolr(hw
, adapter
->num_vfs
);
2389 /* Program MRQC for the distribution of queues */
2390 mrqc
= ixgbe_setup_mrqc(adapter
);
2392 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
2393 /* Fill out redirection table */
2394 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2395 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
2397 /* reta = 4-byte sliding window of
2398 * 0x00..(indices-1)(indices-1)00..etc. */
2399 reta
= (reta
<< 8) | (j
* 0x11);
2401 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2404 /* Fill out hash function seeds */
2405 for (i
= 0; i
< 10; i
++)
2406 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2408 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2409 mrqc
|= IXGBE_MRQC_RSSEN
;
2410 /* Perform hash on these packet types */
2411 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2412 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2413 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2414 | IXGBE_MRQC_RSS_FIELD_IPV6
2415 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2416 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
;
2418 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2420 if (adapter
->num_vfs
) {
2423 /* Map PF MAC address in RAR Entry 0 to first pool
2425 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
2427 /* Set up VF register offsets for selected VT Mode, i.e.
2428 * 64 VFs for SR-IOV */
2429 reg
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
2430 reg
|= IXGBE_GCR_EXT_SRIOV
;
2431 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, reg
);
2434 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2436 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
||
2437 adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
) {
2438 /* Disable indicating checksum in descriptor, enables
2440 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2442 if (!(rxcsum
& IXGBE_RXCSUM_PCSD
)) {
2443 /* Enable IPv4 payload checksum for UDP fragments
2444 * if PCSD is not set */
2445 rxcsum
|= IXGBE_RXCSUM_IPPCSE
;
2448 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2450 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2451 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2452 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
2453 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
2454 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2457 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
2458 /* Enable 82599 HW-RSC */
2459 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2460 ixgbe_configure_rscctl(adapter
, i
);
2462 /* Disable RSC for ACK packets */
2463 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
2464 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
2468 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
2470 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2471 struct ixgbe_hw
*hw
= &adapter
->hw
;
2472 int pool_ndx
= adapter
->num_vfs
;
2474 /* add VID to filter table */
2475 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
2478 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
2480 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2481 struct ixgbe_hw
*hw
= &adapter
->hw
;
2482 int pool_ndx
= adapter
->num_vfs
;
2484 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2485 ixgbe_irq_disable(adapter
);
2487 vlan_group_set_device(adapter
->vlgrp
, vid
, NULL
);
2489 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2490 ixgbe_irq_enable(adapter
);
2492 /* remove VID from filter table */
2493 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
2497 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2498 * @adapter: driver data
2500 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter
*adapter
)
2502 struct ixgbe_hw
*hw
= &adapter
->hw
;
2503 u32 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2506 switch (hw
->mac
.type
) {
2507 case ixgbe_mac_82598EB
:
2508 vlnctrl
&= ~(IXGBE_VLNCTRL_VME
| IXGBE_VLNCTRL_VFE
);
2509 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2510 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2512 case ixgbe_mac_82599EB
:
2513 vlnctrl
&= ~IXGBE_VLNCTRL_VFE
;
2514 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2515 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2516 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2517 j
= adapter
->rx_ring
[i
]->reg_idx
;
2518 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2519 vlnctrl
&= ~IXGBE_RXDCTL_VME
;
2520 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
2529 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2530 * @adapter: driver data
2532 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter
*adapter
)
2534 struct ixgbe_hw
*hw
= &adapter
->hw
;
2535 u32 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2538 switch (hw
->mac
.type
) {
2539 case ixgbe_mac_82598EB
:
2540 vlnctrl
|= IXGBE_VLNCTRL_VME
| IXGBE_VLNCTRL_VFE
;
2541 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2542 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2544 case ixgbe_mac_82599EB
:
2545 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2546 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2547 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2548 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2549 j
= adapter
->rx_ring
[i
]->reg_idx
;
2550 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2551 vlnctrl
|= IXGBE_RXDCTL_VME
;
2552 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
2560 static void ixgbe_vlan_rx_register(struct net_device
*netdev
,
2561 struct vlan_group
*grp
)
2563 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2565 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2566 ixgbe_irq_disable(adapter
);
2567 adapter
->vlgrp
= grp
;
2570 * For a DCB driver, always enable VLAN tag stripping so we can
2571 * still receive traffic from a DCB-enabled host even if we're
2574 ixgbe_vlan_filter_enable(adapter
);
2576 ixgbe_vlan_rx_add_vid(netdev
, 0);
2578 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2579 ixgbe_irq_enable(adapter
);
2582 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
2584 ixgbe_vlan_rx_register(adapter
->netdev
, adapter
->vlgrp
);
2586 if (adapter
->vlgrp
) {
2588 for (vid
= 0; vid
< VLAN_GROUP_ARRAY_LEN
; vid
++) {
2589 if (!vlan_group_get_device(adapter
->vlgrp
, vid
))
2591 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
2597 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2598 * @netdev: network interface device structure
2600 * The set_rx_method entry point is called whenever the unicast/multicast
2601 * address list or the network interface flags are updated. This routine is
2602 * responsible for configuring the hardware for proper unicast, multicast and
2605 void ixgbe_set_rx_mode(struct net_device
*netdev
)
2607 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2608 struct ixgbe_hw
*hw
= &adapter
->hw
;
2611 /* Check for Promiscuous and All Multicast modes */
2613 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
2615 if (netdev
->flags
& IFF_PROMISC
) {
2616 hw
->addr_ctrl
.user_set_promisc
= 1;
2617 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2618 /* don't hardware filter vlans in promisc mode */
2619 ixgbe_vlan_filter_disable(adapter
);
2621 if (netdev
->flags
& IFF_ALLMULTI
) {
2622 fctrl
|= IXGBE_FCTRL_MPE
;
2623 fctrl
&= ~IXGBE_FCTRL_UPE
;
2625 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2627 ixgbe_vlan_filter_enable(adapter
);
2628 hw
->addr_ctrl
.user_set_promisc
= 0;
2631 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
2633 /* reprogram secondary unicast list */
2634 hw
->mac
.ops
.update_uc_addr_list(hw
, netdev
);
2636 /* reprogram multicast list */
2637 hw
->mac
.ops
.update_mc_addr_list(hw
, netdev
);
2639 if (adapter
->num_vfs
)
2640 ixgbe_restore_vf_multicasts(adapter
);
2643 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
2646 struct ixgbe_q_vector
*q_vector
;
2647 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2649 /* legacy and MSI only use one vector */
2650 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2653 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
2654 struct napi_struct
*napi
;
2655 q_vector
= adapter
->q_vector
[q_idx
];
2656 napi
= &q_vector
->napi
;
2657 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2658 if (!q_vector
->rxr_count
|| !q_vector
->txr_count
) {
2659 if (q_vector
->txr_count
== 1)
2660 napi
->poll
= &ixgbe_clean_txonly
;
2661 else if (q_vector
->rxr_count
== 1)
2662 napi
->poll
= &ixgbe_clean_rxonly
;
2670 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
2673 struct ixgbe_q_vector
*q_vector
;
2674 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2676 /* legacy and MSI only use one vector */
2677 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2680 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
2681 q_vector
= adapter
->q_vector
[q_idx
];
2682 napi_disable(&q_vector
->napi
);
2686 #ifdef CONFIG_IXGBE_DCB
2688 * ixgbe_configure_dcb - Configure DCB hardware
2689 * @adapter: ixgbe adapter struct
2691 * This is called by the driver on open to configure the DCB hardware.
2692 * This is also called by the gennetlink interface when reconfiguring
2695 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
2697 struct ixgbe_hw
*hw
= &adapter
->hw
;
2701 ixgbe_dcb_check_config(&adapter
->dcb_cfg
);
2702 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_TX_CONFIG
);
2703 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_RX_CONFIG
);
2705 /* reconfigure the hardware */
2706 ixgbe_dcb_hw_config(&adapter
->hw
, &adapter
->dcb_cfg
);
2708 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2709 j
= adapter
->tx_ring
[i
]->reg_idx
;
2710 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2711 /* PThresh workaround for Tx hang with DFP enabled. */
2713 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2715 /* Enable VLAN tag insert/strip */
2716 ixgbe_vlan_filter_enable(adapter
);
2718 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
2722 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
2724 struct net_device
*netdev
= adapter
->netdev
;
2725 struct ixgbe_hw
*hw
= &adapter
->hw
;
2728 ixgbe_set_rx_mode(netdev
);
2730 ixgbe_restore_vlan(adapter
);
2731 #ifdef CONFIG_IXGBE_DCB
2732 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2733 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2734 netif_set_gso_max_size(netdev
, 32768);
2736 netif_set_gso_max_size(netdev
, 65536);
2737 ixgbe_configure_dcb(adapter
);
2739 netif_set_gso_max_size(netdev
, 65536);
2742 netif_set_gso_max_size(netdev
, 65536);
2746 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
2747 ixgbe_configure_fcoe(adapter
);
2749 #endif /* IXGBE_FCOE */
2750 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
2751 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2752 adapter
->tx_ring
[i
]->atr_sample_rate
=
2753 adapter
->atr_sample_rate
;
2754 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
2755 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
2756 ixgbe_init_fdir_perfect_82599(hw
, adapter
->fdir_pballoc
);
2759 ixgbe_configure_tx(adapter
);
2760 ixgbe_configure_rx(adapter
);
2761 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2762 ixgbe_alloc_rx_buffers(adapter
, adapter
->rx_ring
[i
],
2763 (adapter
->rx_ring
[i
]->count
- 1));
2766 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
2768 switch (hw
->phy
.type
) {
2769 case ixgbe_phy_sfp_avago
:
2770 case ixgbe_phy_sfp_ftl
:
2771 case ixgbe_phy_sfp_intel
:
2772 case ixgbe_phy_sfp_unknown
:
2773 case ixgbe_phy_tw_tyco
:
2774 case ixgbe_phy_tw_unknown
:
2782 * ixgbe_sfp_link_config - set up SFP+ link
2783 * @adapter: pointer to private adapter struct
2785 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
2787 struct ixgbe_hw
*hw
= &adapter
->hw
;
2789 if (hw
->phy
.multispeed_fiber
) {
2791 * In multispeed fiber setups, the device may not have
2792 * had a physical connection when the driver loaded.
2793 * If that's the case, the initial link configuration
2794 * couldn't get the MAC into 10G or 1G mode, so we'll
2795 * never have a link status change interrupt fire.
2796 * We need to try and force an autonegotiation
2797 * session, then bring up link.
2799 hw
->mac
.ops
.setup_sfp(hw
);
2800 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
2801 schedule_work(&adapter
->multispeed_fiber_task
);
2804 * Direct Attach Cu and non-multispeed fiber modules
2805 * still need to be configured properly prior to
2808 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_MOD_TASK
))
2809 schedule_work(&adapter
->sfp_config_module_task
);
2814 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2815 * @hw: pointer to private hardware struct
2817 * Returns 0 on success, negative on failure
2819 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
2822 bool negotiation
, link_up
= false;
2823 u32 ret
= IXGBE_ERR_LINK_SETUP
;
2825 if (hw
->mac
.ops
.check_link
)
2826 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
2831 if (hw
->mac
.ops
.get_link_capabilities
)
2832 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
2836 if (hw
->mac
.ops
.setup_link
)
2837 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
2842 #define IXGBE_MAX_RX_DESC_POLL 10
2843 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
2846 int j
= adapter
->rx_ring
[rxr
]->reg_idx
;
2849 for (k
= 0; k
< IXGBE_MAX_RX_DESC_POLL
; k
++) {
2850 if (IXGBE_READ_REG(&adapter
->hw
,
2851 IXGBE_RXDCTL(j
)) & IXGBE_RXDCTL_ENABLE
)
2856 if (k
>= IXGBE_MAX_RX_DESC_POLL
) {
2857 DPRINTK(DRV
, ERR
, "RXDCTL.ENABLE on Rx queue %d "
2858 "not set within the polling period\n", rxr
);
2860 ixgbe_release_rx_desc(&adapter
->hw
, adapter
->rx_ring
[rxr
],
2861 (adapter
->rx_ring
[rxr
]->count
- 1));
2864 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
2866 struct net_device
*netdev
= adapter
->netdev
;
2867 struct ixgbe_hw
*hw
= &adapter
->hw
;
2869 int num_rx_rings
= adapter
->num_rx_queues
;
2871 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2872 u32 txdctl
, rxdctl
, mhadd
;
2877 ixgbe_get_hw_control(adapter
);
2879 if ((adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) ||
2880 (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
)) {
2881 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2882 gpie
= (IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_EIAME
|
2883 IXGBE_GPIE_PBA_SUPPORT
| IXGBE_GPIE_OCD
);
2888 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2889 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
2890 gpie
|= IXGBE_GPIE_VTMODE_64
;
2892 /* XXX: to interrupt immediately for EICS writes, enable this */
2893 /* gpie |= IXGBE_GPIE_EIMEN; */
2894 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2897 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2899 * use EIAM to auto-mask when MSI-X interrupt is asserted
2900 * this saves a register write for every interrupt
2902 switch (hw
->mac
.type
) {
2903 case ixgbe_mac_82598EB
:
2904 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
2907 case ixgbe_mac_82599EB
:
2908 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2909 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2913 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2914 * specifically only auto mask tx and rx interrupts */
2915 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
2918 /* Enable fan failure interrupt if media type is copper */
2919 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
2920 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
2921 gpie
|= IXGBE_SDP1_GPIEN
;
2922 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2925 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2926 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
2927 gpie
|= IXGBE_SDP1_GPIEN
;
2928 gpie
|= IXGBE_SDP2_GPIEN
;
2929 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2933 /* adjust max frame to be able to do baby jumbo for FCoE */
2934 if ((netdev
->features
& NETIF_F_FCOE_MTU
) &&
2935 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
2936 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2938 #endif /* IXGBE_FCOE */
2939 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
2940 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
2941 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
2942 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
2944 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
2947 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2948 j
= adapter
->tx_ring
[i
]->reg_idx
;
2949 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2950 if (adapter
->rx_itr_setting
== 0) {
2951 /* cannot set wthresh when itr==0 */
2952 txdctl
&= ~0x007F0000;
2954 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2955 txdctl
|= (8 << 16);
2957 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2960 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2961 /* DMATXCTL.EN must be set after all Tx queue config is done */
2962 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2963 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2964 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2966 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2967 j
= adapter
->tx_ring
[i
]->reg_idx
;
2968 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2969 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2970 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2971 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2973 /* poll for Tx Enable ready */
2976 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2977 } while (--wait_loop
&&
2978 !(txdctl
& IXGBE_TXDCTL_ENABLE
));
2980 DPRINTK(DRV
, ERR
, "Could not enable "
2981 "Tx Queue %d\n", j
);
2985 for (i
= 0; i
< num_rx_rings
; i
++) {
2986 j
= adapter
->rx_ring
[i
]->reg_idx
;
2987 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2988 /* enable PTHRESH=32 descriptors (half the internal cache)
2989 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2990 * this also removes a pesky rx_no_buffer_count increment */
2992 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
2993 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), rxdctl
);
2994 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
2995 ixgbe_rx_desc_queue_enable(adapter
, i
);
2997 /* enable all receives */
2998 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2999 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3000 rxdctl
|= (IXGBE_RXCTRL_DMBYPS
| IXGBE_RXCTRL_RXEN
);
3002 rxdctl
|= IXGBE_RXCTRL_RXEN
;
3003 hw
->mac
.ops
.enable_rx_dma(hw
, rxdctl
);
3005 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3006 ixgbe_configure_msix(adapter
);
3008 ixgbe_configure_msi_and_legacy(adapter
);
3010 /* enable the optics */
3011 if (hw
->phy
.multispeed_fiber
)
3012 hw
->mac
.ops
.enable_tx_laser(hw
);
3014 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
3015 ixgbe_napi_enable_all(adapter
);
3017 /* clear any pending interrupts, may auto mask */
3018 IXGBE_READ_REG(hw
, IXGBE_EICR
);
3020 ixgbe_irq_enable(adapter
);
3023 * If this adapter has a fan, check to see if we had a failure
3024 * before we enabled the interrupt.
3026 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3027 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
3028 if (esdp
& IXGBE_ESDP_SDP1
)
3030 "Fan has stopped, replace the adapter\n");
3034 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3035 * arrived before interrupts were enabled but after probe. Such
3036 * devices wouldn't have their type identified yet. We need to
3037 * kick off the SFP+ module setup first, then try to bring up link.
3038 * If we're not hot-pluggable SFP+, we just need to configure link
3041 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
3042 err
= hw
->phy
.ops
.identify(hw
);
3043 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
3045 * Take the device down and schedule the sfp tasklet
3046 * which will unregister_netdev and log it.
3048 ixgbe_down(adapter
);
3049 schedule_work(&adapter
->sfp_config_module_task
);
3054 if (ixgbe_is_sfp(hw
)) {
3055 ixgbe_sfp_link_config(adapter
);
3057 err
= ixgbe_non_sfp_link_config(hw
);
3059 DPRINTK(PROBE
, ERR
, "link_config FAILED %d\n", err
);
3062 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3063 set_bit(__IXGBE_FDIR_INIT_DONE
,
3064 &(adapter
->tx_ring
[i
]->reinit_state
));
3066 /* enable transmits */
3067 netif_tx_start_all_queues(netdev
);
3069 /* bring the link up in the watchdog, this could race with our first
3070 * link up interrupt but shouldn't be a problem */
3071 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3072 adapter
->link_check_timeout
= jiffies
;
3073 mod_timer(&adapter
->watchdog_timer
, jiffies
);
3075 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3076 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
3077 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
3078 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
3083 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3085 WARN_ON(in_interrupt());
3086 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3088 ixgbe_down(adapter
);
3090 * If SR-IOV enabled then wait a bit before bringing the adapter
3091 * back up to give the VFs time to respond to the reset. The
3092 * two second wait is based upon the watchdog timer cycle in
3095 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3098 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3101 int ixgbe_up(struct ixgbe_adapter
*adapter
)
3103 /* hardware has been reset, we need to reload some things */
3104 ixgbe_configure(adapter
);
3106 return ixgbe_up_complete(adapter
);
3109 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3111 struct ixgbe_hw
*hw
= &adapter
->hw
;
3114 err
= hw
->mac
.ops
.init_hw(hw
);
3117 case IXGBE_ERR_SFP_NOT_PRESENT
:
3119 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
3120 dev_err(&adapter
->pdev
->dev
, "master disable timed out\n");
3122 case IXGBE_ERR_EEPROM_VERSION
:
3123 /* We are running on a pre-production device, log a warning */
3124 dev_warn(&adapter
->pdev
->dev
, "This device is a pre-production "
3125 "adapter/LOM. Please be aware there may be issues "
3126 "associated with your hardware. If you are "
3127 "experiencing problems please contact your Intel or "
3128 "hardware representative who provided you with this "
3132 dev_err(&adapter
->pdev
->dev
, "Hardware Error: %d\n", err
);
3135 /* reprogram the RAR[0] in case user changed it. */
3136 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
3141 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3142 * @adapter: board private structure
3143 * @rx_ring: ring to free buffers from
3145 static void ixgbe_clean_rx_ring(struct ixgbe_adapter
*adapter
,
3146 struct ixgbe_ring
*rx_ring
)
3148 struct pci_dev
*pdev
= adapter
->pdev
;
3152 /* Free all the Rx ring sk_buffs */
3154 for (i
= 0; i
< rx_ring
->count
; i
++) {
3155 struct ixgbe_rx_buffer
*rx_buffer_info
;
3157 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
3158 if (rx_buffer_info
->dma
) {
3159 dma_unmap_single(&pdev
->dev
, rx_buffer_info
->dma
,
3160 rx_ring
->rx_buf_len
,
3162 rx_buffer_info
->dma
= 0;
3164 if (rx_buffer_info
->skb
) {
3165 struct sk_buff
*skb
= rx_buffer_info
->skb
;
3166 rx_buffer_info
->skb
= NULL
;
3168 struct sk_buff
*this = skb
;
3169 if (IXGBE_RSC_CB(this)->dma
) {
3170 dma_unmap_single(&pdev
->dev
,
3171 IXGBE_RSC_CB(this)->dma
,
3172 rx_ring
->rx_buf_len
,
3174 IXGBE_RSC_CB(this)->dma
= 0;
3177 dev_kfree_skb(this);
3180 if (!rx_buffer_info
->page
)
3182 if (rx_buffer_info
->page_dma
) {
3183 dma_unmap_page(&pdev
->dev
, rx_buffer_info
->page_dma
,
3184 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
3185 rx_buffer_info
->page_dma
= 0;
3187 put_page(rx_buffer_info
->page
);
3188 rx_buffer_info
->page
= NULL
;
3189 rx_buffer_info
->page_offset
= 0;
3192 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
3193 memset(rx_ring
->rx_buffer_info
, 0, size
);
3195 /* Zero out the descriptor ring */
3196 memset(rx_ring
->desc
, 0, rx_ring
->size
);
3198 rx_ring
->next_to_clean
= 0;
3199 rx_ring
->next_to_use
= 0;
3202 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->head
);
3204 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->tail
);
3208 * ixgbe_clean_tx_ring - Free Tx Buffers
3209 * @adapter: board private structure
3210 * @tx_ring: ring to be cleaned
3212 static void ixgbe_clean_tx_ring(struct ixgbe_adapter
*adapter
,
3213 struct ixgbe_ring
*tx_ring
)
3215 struct ixgbe_tx_buffer
*tx_buffer_info
;
3219 /* Free all the Tx ring sk_buffs */
3221 for (i
= 0; i
< tx_ring
->count
; i
++) {
3222 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
3223 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
3226 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
3227 memset(tx_ring
->tx_buffer_info
, 0, size
);
3229 /* Zero out the descriptor ring */
3230 memset(tx_ring
->desc
, 0, tx_ring
->size
);
3232 tx_ring
->next_to_use
= 0;
3233 tx_ring
->next_to_clean
= 0;
3236 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->head
);
3238 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
3242 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3243 * @adapter: board private structure
3245 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
3249 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3250 ixgbe_clean_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3254 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3255 * @adapter: board private structure
3257 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
3261 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3262 ixgbe_clean_tx_ring(adapter
, adapter
->tx_ring
[i
]);
3265 void ixgbe_down(struct ixgbe_adapter
*adapter
)
3267 struct net_device
*netdev
= adapter
->netdev
;
3268 struct ixgbe_hw
*hw
= &adapter
->hw
;
3273 /* signal that we are down to the interrupt handler */
3274 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3276 /* power down the optics */
3277 if (hw
->phy
.multispeed_fiber
)
3278 hw
->mac
.ops
.disable_tx_laser(hw
);
3280 /* disable receive for all VFs and wait one second */
3281 if (adapter
->num_vfs
) {
3282 /* ping all the active vfs to let them know we are going down */
3283 ixgbe_ping_all_vfs(adapter
);
3285 /* Disable all VFTE/VFRE TX/RX */
3286 ixgbe_disable_tx_rx(adapter
);
3288 /* Mark all the VFs as inactive */
3289 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
3290 adapter
->vfinfo
[i
].clear_to_send
= 0;
3293 /* disable receives */
3294 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3295 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3297 IXGBE_WRITE_FLUSH(hw
);
3300 netif_tx_stop_all_queues(netdev
);
3302 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
3303 del_timer_sync(&adapter
->sfp_timer
);
3304 del_timer_sync(&adapter
->watchdog_timer
);
3305 cancel_work_sync(&adapter
->watchdog_task
);
3307 netif_carrier_off(netdev
);
3308 netif_tx_disable(netdev
);
3310 ixgbe_irq_disable(adapter
);
3312 ixgbe_napi_disable_all(adapter
);
3314 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3315 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3316 cancel_work_sync(&adapter
->fdir_reinit_task
);
3318 /* disable transmits in the hardware now that interrupts are off */
3319 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3320 j
= adapter
->tx_ring
[i
]->reg_idx
;
3321 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3322 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
),
3323 (txdctl
& ~IXGBE_TXDCTL_ENABLE
));
3325 /* Disable the Tx DMA engine on 82599 */
3326 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3327 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
3328 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
3329 ~IXGBE_DMATXCTL_TE
));
3331 /* clear n-tuple filters that are cached */
3332 ethtool_ntuple_flush(netdev
);
3334 if (!pci_channel_offline(adapter
->pdev
))
3335 ixgbe_reset(adapter
);
3336 ixgbe_clean_all_tx_rings(adapter
);
3337 ixgbe_clean_all_rx_rings(adapter
);
3339 #ifdef CONFIG_IXGBE_DCA
3340 /* since we reset the hardware DCA settings were cleared */
3341 ixgbe_setup_dca(adapter
);
3346 * ixgbe_poll - NAPI Rx polling callback
3347 * @napi: structure for representing this polling device
3348 * @budget: how many packets driver is allowed to clean
3350 * This function is used for legacy and MSI, NAPI mode
3352 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
3354 struct ixgbe_q_vector
*q_vector
=
3355 container_of(napi
, struct ixgbe_q_vector
, napi
);
3356 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
3357 int tx_clean_complete
, work_done
= 0;
3359 #ifdef CONFIG_IXGBE_DCA
3360 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
3361 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[0]);
3362 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[0]);
3366 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
[0]);
3367 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
[0], &work_done
, budget
);
3369 if (!tx_clean_complete
)
3372 /* If budget not fully consumed, exit the polling mode */
3373 if (work_done
< budget
) {
3374 napi_complete(napi
);
3375 if (adapter
->rx_itr_setting
& 1)
3376 ixgbe_set_itr(adapter
);
3377 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
3378 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
3384 * ixgbe_tx_timeout - Respond to a Tx Hang
3385 * @netdev: network interface device structure
3387 static void ixgbe_tx_timeout(struct net_device
*netdev
)
3389 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3391 /* Do the reset outside of interrupt context */
3392 schedule_work(&adapter
->reset_task
);
3395 static void ixgbe_reset_task(struct work_struct
*work
)
3397 struct ixgbe_adapter
*adapter
;
3398 adapter
= container_of(work
, struct ixgbe_adapter
, reset_task
);
3400 /* If we're already down or resetting, just bail */
3401 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
3402 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
3405 adapter
->tx_timeout_count
++;
3407 ixgbe_reinit_locked(adapter
);
3410 #ifdef CONFIG_IXGBE_DCB
3411 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
3414 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_DCB
];
3416 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
3420 adapter
->num_rx_queues
= f
->indices
;
3421 adapter
->num_tx_queues
= f
->indices
;
3429 * ixgbe_set_rss_queues: Allocate queues for RSS
3430 * @adapter: board private structure to initialize
3432 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3433 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3436 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
3439 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
3441 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3443 adapter
->num_rx_queues
= f
->indices
;
3444 adapter
->num_tx_queues
= f
->indices
;
3454 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3455 * @adapter: board private structure to initialize
3457 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3458 * to the original CPU that initiated the Tx session. This runs in addition
3459 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3460 * Rx load across CPUs using RSS.
3463 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
3466 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
3468 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
3471 /* Flow Director must have RSS enabled */
3472 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
3473 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3474 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)))) {
3475 adapter
->num_tx_queues
= f_fdir
->indices
;
3476 adapter
->num_rx_queues
= f_fdir
->indices
;
3479 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
3480 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
3487 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3488 * @adapter: board private structure to initialize
3490 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3491 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3492 * rx queues out of the max number of rx queues, instead, it is used as the
3493 * index of the first rx queue used by FCoE.
3496 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
3499 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
3501 f
->indices
= min((int)num_online_cpus(), f
->indices
);
3502 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
3503 adapter
->num_rx_queues
= 1;
3504 adapter
->num_tx_queues
= 1;
3505 #ifdef CONFIG_IXGBE_DCB
3506 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3507 DPRINTK(PROBE
, INFO
, "FCoE enabled with DCB\n");
3508 ixgbe_set_dcb_queues(adapter
);
3511 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3512 DPRINTK(PROBE
, INFO
, "FCoE enabled with RSS\n");
3513 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3514 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
3515 ixgbe_set_fdir_queues(adapter
);
3517 ixgbe_set_rss_queues(adapter
);
3519 /* adding FCoE rx rings to the end */
3520 f
->mask
= adapter
->num_rx_queues
;
3521 adapter
->num_rx_queues
+= f
->indices
;
3522 adapter
->num_tx_queues
+= f
->indices
;
3530 #endif /* IXGBE_FCOE */
3532 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3533 * @adapter: board private structure to initialize
3535 * IOV doesn't actually use anything, so just NAK the
3536 * request for now and let the other queue routines
3537 * figure out what to do.
3539 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
3545 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3546 * @adapter: board private structure to initialize
3548 * This is the top level queue allocation routine. The order here is very
3549 * important, starting with the "most" number of features turned on at once,
3550 * and ending with the smallest set of features. This way large combinations
3551 * can be allocated if they're turned on, and smaller combinations are the
3552 * fallthrough conditions.
3555 static void ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
3557 /* Start with base case */
3558 adapter
->num_rx_queues
= 1;
3559 adapter
->num_tx_queues
= 1;
3560 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
3561 adapter
->num_rx_queues_per_pool
= 1;
3563 if (ixgbe_set_sriov_queues(adapter
))
3567 if (ixgbe_set_fcoe_queues(adapter
))
3570 #endif /* IXGBE_FCOE */
3571 #ifdef CONFIG_IXGBE_DCB
3572 if (ixgbe_set_dcb_queues(adapter
))
3576 if (ixgbe_set_fdir_queues(adapter
))
3579 if (ixgbe_set_rss_queues(adapter
))
3582 /* fallback to base case */
3583 adapter
->num_rx_queues
= 1;
3584 adapter
->num_tx_queues
= 1;
3587 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3588 adapter
->netdev
->real_num_tx_queues
= adapter
->num_tx_queues
;
3591 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
3594 int err
, vector_threshold
;
3596 /* We'll want at least 3 (vector_threshold):
3599 * 3) Other (Link Status Change, etc.)
3600 * 4) TCP Timer (optional)
3602 vector_threshold
= MIN_MSIX_COUNT
;
3604 /* The more we get, the more we will assign to Tx/Rx Cleanup
3605 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3606 * Right now, we simply care about how many we'll get; we'll
3607 * set them up later while requesting irq's.
3609 while (vectors
>= vector_threshold
) {
3610 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
3612 if (!err
) /* Success in acquiring all requested vectors. */
3615 vectors
= 0; /* Nasty failure, quit now */
3616 else /* err == number of vectors we should try again with */
3620 if (vectors
< vector_threshold
) {
3621 /* Can't allocate enough MSI-X interrupts? Oh well.
3622 * This just means we'll go with either a single MSI
3623 * vector or fall back to legacy interrupts.
3625 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI-X interrupts\n");
3626 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
3627 kfree(adapter
->msix_entries
);
3628 adapter
->msix_entries
= NULL
;
3630 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
3632 * Adjust for only the vectors we'll use, which is minimum
3633 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3634 * vectors we were allocated.
3636 adapter
->num_msix_vectors
= min(vectors
,
3637 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
3642 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3643 * @adapter: board private structure to initialize
3645 * Cache the descriptor ring offsets for RSS to the assigned rings.
3648 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
3653 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3654 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3655 adapter
->rx_ring
[i
]->reg_idx
= i
;
3656 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3657 adapter
->tx_ring
[i
]->reg_idx
= i
;
3666 #ifdef CONFIG_IXGBE_DCB
3668 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3669 * @adapter: board private structure to initialize
3671 * Cache the descriptor ring offsets for DCB to the assigned rings.
3674 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
3678 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
3680 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3681 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
3682 /* the number of queues is assumed to be symmetric */
3683 for (i
= 0; i
< dcb_i
; i
++) {
3684 adapter
->rx_ring
[i
]->reg_idx
= i
<< 3;
3685 adapter
->tx_ring
[i
]->reg_idx
= i
<< 2;
3688 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
3691 * Tx TC0 starts at: descriptor queue 0
3692 * Tx TC1 starts at: descriptor queue 32
3693 * Tx TC2 starts at: descriptor queue 64
3694 * Tx TC3 starts at: descriptor queue 80
3695 * Tx TC4 starts at: descriptor queue 96
3696 * Tx TC5 starts at: descriptor queue 104
3697 * Tx TC6 starts at: descriptor queue 112
3698 * Tx TC7 starts at: descriptor queue 120
3700 * Rx TC0-TC7 are offset by 16 queues each
3702 for (i
= 0; i
< 3; i
++) {
3703 adapter
->tx_ring
[i
]->reg_idx
= i
<< 5;
3704 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
3706 for ( ; i
< 5; i
++) {
3707 adapter
->tx_ring
[i
]->reg_idx
=
3709 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
3711 for ( ; i
< dcb_i
; i
++) {
3712 adapter
->tx_ring
[i
]->reg_idx
=
3714 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
3718 } else if (dcb_i
== 4) {
3720 * Tx TC0 starts at: descriptor queue 0
3721 * Tx TC1 starts at: descriptor queue 64
3722 * Tx TC2 starts at: descriptor queue 96
3723 * Tx TC3 starts at: descriptor queue 112
3725 * Rx TC0-TC3 are offset by 32 queues each
3727 adapter
->tx_ring
[0]->reg_idx
= 0;
3728 adapter
->tx_ring
[1]->reg_idx
= 64;
3729 adapter
->tx_ring
[2]->reg_idx
= 96;
3730 adapter
->tx_ring
[3]->reg_idx
= 112;
3731 for (i
= 0 ; i
< dcb_i
; i
++)
3732 adapter
->rx_ring
[i
]->reg_idx
= i
<< 5;
3750 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3751 * @adapter: board private structure to initialize
3753 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3756 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
3761 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
3762 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3763 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))) {
3764 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3765 adapter
->rx_ring
[i
]->reg_idx
= i
;
3766 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3767 adapter
->tx_ring
[i
]->reg_idx
= i
;
3776 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3777 * @adapter: board private structure to initialize
3779 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3782 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
3784 int i
, fcoe_rx_i
= 0, fcoe_tx_i
= 0;
3786 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
3788 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
3789 #ifdef CONFIG_IXGBE_DCB
3790 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3791 struct ixgbe_fcoe
*fcoe
= &adapter
->fcoe
;
3793 ixgbe_cache_ring_dcb(adapter
);
3794 /* find out queues in TC for FCoE */
3795 fcoe_rx_i
= adapter
->rx_ring
[fcoe
->tc
]->reg_idx
+ 1;
3796 fcoe_tx_i
= adapter
->tx_ring
[fcoe
->tc
]->reg_idx
+ 1;
3798 * In 82599, the number of Tx queues for each traffic
3799 * class for both 8-TC and 4-TC modes are:
3800 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3801 * 8 TCs: 32 32 16 16 8 8 8 8
3802 * 4 TCs: 64 64 32 32
3803 * We have max 8 queues for FCoE, where 8 the is
3804 * FCoE redirection table size. If TC for FCoE is
3805 * less than or equal to TC3, we have enough queues
3806 * to add max of 8 queues for FCoE, so we start FCoE
3807 * tx descriptor from the next one, i.e., reg_idx + 1.
3808 * If TC for FCoE is above TC3, implying 8 TC mode,
3809 * and we need 8 for FCoE, we have to take all queues
3810 * in that traffic class for FCoE.
3812 if ((f
->indices
== IXGBE_FCRETA_SIZE
) && (fcoe
->tc
> 3))
3815 #endif /* CONFIG_IXGBE_DCB */
3816 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3817 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3818 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
3819 ixgbe_cache_ring_fdir(adapter
);
3821 ixgbe_cache_ring_rss(adapter
);
3823 fcoe_rx_i
= f
->mask
;
3824 fcoe_tx_i
= f
->mask
;
3826 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
3827 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
3828 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
3835 #endif /* IXGBE_FCOE */
3837 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3838 * @adapter: board private structure to initialize
3840 * SR-IOV doesn't use any descriptor rings but changes the default if
3841 * no other mapping is used.
3844 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
3846 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
3847 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
3848 if (adapter
->num_vfs
)
3855 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3856 * @adapter: board private structure to initialize
3858 * Once we know the feature-set enabled for the device, we'll cache
3859 * the register offset the descriptor ring is assigned to.
3861 * Note, the order the various feature calls is important. It must start with
3862 * the "most" features enabled at the same time, then trickle down to the
3863 * least amount of features turned on at once.
3865 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
3867 /* start with default case */
3868 adapter
->rx_ring
[0]->reg_idx
= 0;
3869 adapter
->tx_ring
[0]->reg_idx
= 0;
3871 if (ixgbe_cache_ring_sriov(adapter
))
3875 if (ixgbe_cache_ring_fcoe(adapter
))
3878 #endif /* IXGBE_FCOE */
3879 #ifdef CONFIG_IXGBE_DCB
3880 if (ixgbe_cache_ring_dcb(adapter
))
3884 if (ixgbe_cache_ring_fdir(adapter
))
3887 if (ixgbe_cache_ring_rss(adapter
))
3892 * ixgbe_alloc_queues - Allocate memory for all rings
3893 * @adapter: board private structure to initialize
3895 * We allocate one ring per queue at run-time since we don't know the
3896 * number of queues at compile-time. The polling_netdev array is
3897 * intended for Multiqueue, but should work fine with a single queue.
3899 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
3902 int orig_node
= adapter
->node
;
3904 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3905 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
3906 if (orig_node
== -1) {
3907 int cur_node
= next_online_node(adapter
->node
);
3908 if (cur_node
== MAX_NUMNODES
)
3909 cur_node
= first_online_node
;
3910 adapter
->node
= cur_node
;
3912 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
3915 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
3917 goto err_tx_ring_allocation
;
3918 ring
->count
= adapter
->tx_ring_count
;
3919 ring
->queue_index
= i
;
3920 ring
->numa_node
= adapter
->node
;
3922 adapter
->tx_ring
[i
] = ring
;
3925 /* Restore the adapter's original node */
3926 adapter
->node
= orig_node
;
3928 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3929 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
3930 if (orig_node
== -1) {
3931 int cur_node
= next_online_node(adapter
->node
);
3932 if (cur_node
== MAX_NUMNODES
)
3933 cur_node
= first_online_node
;
3934 adapter
->node
= cur_node
;
3936 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
3939 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
3941 goto err_rx_ring_allocation
;
3942 ring
->count
= adapter
->rx_ring_count
;
3943 ring
->queue_index
= i
;
3944 ring
->numa_node
= adapter
->node
;
3946 adapter
->rx_ring
[i
] = ring
;
3949 /* Restore the adapter's original node */
3950 adapter
->node
= orig_node
;
3952 ixgbe_cache_ring_register(adapter
);
3956 err_rx_ring_allocation
:
3957 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3958 kfree(adapter
->tx_ring
[i
]);
3959 err_tx_ring_allocation
:
3964 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3965 * @adapter: board private structure to initialize
3967 * Attempt to configure the interrupts using the best available
3968 * capabilities of the hardware and the kernel.
3970 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
3972 struct ixgbe_hw
*hw
= &adapter
->hw
;
3974 int vector
, v_budget
;
3977 * It's easy to be greedy for MSI-X vectors, but it really
3978 * doesn't do us much good if we have a lot more vectors
3979 * than CPU's. So let's be conservative and only ask for
3980 * (roughly) the same number of vectors as there are CPU's.
3982 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
3983 (int)num_online_cpus()) + NON_Q_VECTORS
;
3986 * At the same time, hardware can only support a maximum of
3987 * hw.mac->max_msix_vectors vectors. With features
3988 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3989 * descriptor queues supported by our device. Thus, we cap it off in
3990 * those rare cases where the cpu count also exceeds our vector limit.
3992 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
3994 /* A failure in MSI-X entry allocation isn't fatal, but it does
3995 * mean we disable MSI-X capabilities of the adapter. */
3996 adapter
->msix_entries
= kcalloc(v_budget
,
3997 sizeof(struct msix_entry
), GFP_KERNEL
);
3998 if (adapter
->msix_entries
) {
3999 for (vector
= 0; vector
< v_budget
; vector
++)
4000 adapter
->msix_entries
[vector
].entry
= vector
;
4002 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
4004 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4008 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
4009 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
4010 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4011 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4012 adapter
->atr_sample_rate
= 0;
4013 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
4014 ixgbe_disable_sriov(adapter
);
4016 ixgbe_set_num_queues(adapter
);
4018 err
= pci_enable_msi(adapter
->pdev
);
4020 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
4022 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI interrupt, "
4023 "falling back to legacy. Error: %d\n", err
);
4033 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4034 * @adapter: board private structure to initialize
4036 * We allocate one q_vector per queue interrupt. If allocation fails we
4039 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
4041 int q_idx
, num_q_vectors
;
4042 struct ixgbe_q_vector
*q_vector
;
4044 int (*poll
)(struct napi_struct
*, int);
4046 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4047 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4048 napi_vectors
= adapter
->num_rx_queues
;
4049 poll
= &ixgbe_clean_rxtx_many
;
4056 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4057 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
4058 GFP_KERNEL
, adapter
->node
);
4060 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
4064 q_vector
->adapter
= adapter
;
4065 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
4066 q_vector
->eitr
= adapter
->tx_eitr_param
;
4068 q_vector
->eitr
= adapter
->rx_eitr_param
;
4069 q_vector
->v_idx
= q_idx
;
4070 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
4071 adapter
->q_vector
[q_idx
] = q_vector
;
4079 q_vector
= adapter
->q_vector
[q_idx
];
4080 netif_napi_del(&q_vector
->napi
);
4082 adapter
->q_vector
[q_idx
] = NULL
;
4088 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4089 * @adapter: board private structure to initialize
4091 * This function frees the memory allocated to the q_vectors. In addition if
4092 * NAPI is enabled it will delete any references to the NAPI struct prior
4093 * to freeing the q_vector.
4095 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
4097 int q_idx
, num_q_vectors
;
4099 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4100 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4104 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4105 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
4106 adapter
->q_vector
[q_idx
] = NULL
;
4107 netif_napi_del(&q_vector
->napi
);
4112 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
4114 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4115 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4116 pci_disable_msix(adapter
->pdev
);
4117 kfree(adapter
->msix_entries
);
4118 adapter
->msix_entries
= NULL
;
4119 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
4120 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
4121 pci_disable_msi(adapter
->pdev
);
4127 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4128 * @adapter: board private structure to initialize
4130 * We determine which interrupt scheme to use based on...
4131 * - Kernel support (MSI, MSI-X)
4132 * - which can be user-defined (via MODULE_PARAM)
4133 * - Hardware queue count (num_*_queues)
4134 * - defined by miscellaneous hardware support/features (RSS, etc.)
4136 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4140 /* Number of supported queues */
4141 ixgbe_set_num_queues(adapter
);
4143 err
= ixgbe_set_interrupt_capability(adapter
);
4145 DPRINTK(PROBE
, ERR
, "Unable to setup interrupt capabilities\n");
4146 goto err_set_interrupt
;
4149 err
= ixgbe_alloc_q_vectors(adapter
);
4151 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queue "
4153 goto err_alloc_q_vectors
;
4156 err
= ixgbe_alloc_queues(adapter
);
4158 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queues\n");
4159 goto err_alloc_queues
;
4162 DPRINTK(DRV
, INFO
, "Multiqueue %s: Rx Queue count = %u, "
4163 "Tx Queue count = %u\n",
4164 (adapter
->num_rx_queues
> 1) ? "Enabled" :
4165 "Disabled", adapter
->num_rx_queues
, adapter
->num_tx_queues
);
4167 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4172 ixgbe_free_q_vectors(adapter
);
4173 err_alloc_q_vectors
:
4174 ixgbe_reset_interrupt_capability(adapter
);
4180 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4181 * @adapter: board private structure to clear interrupt scheme on
4183 * We go through and clear interrupt specific resources and reset the structure
4184 * to pre-load conditions
4186 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4190 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4191 kfree(adapter
->tx_ring
[i
]);
4192 adapter
->tx_ring
[i
] = NULL
;
4194 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4195 kfree(adapter
->rx_ring
[i
]);
4196 adapter
->rx_ring
[i
] = NULL
;
4199 ixgbe_free_q_vectors(adapter
);
4200 ixgbe_reset_interrupt_capability(adapter
);
4204 * ixgbe_sfp_timer - worker thread to find a missing module
4205 * @data: pointer to our adapter struct
4207 static void ixgbe_sfp_timer(unsigned long data
)
4209 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4212 * Do the sfp_timer outside of interrupt context due to the
4213 * delays that sfp+ detection requires
4215 schedule_work(&adapter
->sfp_task
);
4219 * ixgbe_sfp_task - worker thread to find a missing module
4220 * @work: pointer to work_struct containing our data
4222 static void ixgbe_sfp_task(struct work_struct
*work
)
4224 struct ixgbe_adapter
*adapter
= container_of(work
,
4225 struct ixgbe_adapter
,
4227 struct ixgbe_hw
*hw
= &adapter
->hw
;
4229 if ((hw
->phy
.type
== ixgbe_phy_nl
) &&
4230 (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)) {
4231 s32 ret
= hw
->phy
.ops
.identify_sfp(hw
);
4232 if (ret
== IXGBE_ERR_SFP_NOT_PRESENT
)
4234 ret
= hw
->phy
.ops
.reset(hw
);
4235 if (ret
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
4236 dev_err(&adapter
->pdev
->dev
, "failed to initialize "
4237 "because an unsupported SFP+ module type "
4239 "Reload the driver after installing a "
4240 "supported module.\n");
4241 unregister_netdev(adapter
->netdev
);
4243 DPRINTK(PROBE
, INFO
, "detected SFP+: %d\n",
4246 /* don't need this routine any more */
4247 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
4251 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
))
4252 mod_timer(&adapter
->sfp_timer
,
4253 round_jiffies(jiffies
+ (2 * HZ
)));
4257 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4258 * @adapter: board private structure to initialize
4260 * ixgbe_sw_init initializes the Adapter private data structure.
4261 * Fields are initialized based on PCI device information and
4262 * OS network device settings (MTU size).
4264 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
4266 struct ixgbe_hw
*hw
= &adapter
->hw
;
4267 struct pci_dev
*pdev
= adapter
->pdev
;
4268 struct net_device
*dev
= adapter
->netdev
;
4270 #ifdef CONFIG_IXGBE_DCB
4272 struct tc_configuration
*tc
;
4275 /* PCI config space info */
4277 hw
->vendor_id
= pdev
->vendor
;
4278 hw
->device_id
= pdev
->device
;
4279 hw
->revision_id
= pdev
->revision
;
4280 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
4281 hw
->subsystem_device_id
= pdev
->subsystem_device
;
4283 /* Set capability flags */
4284 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
4285 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
4286 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
4287 adapter
->ring_feature
[RING_F_DCB
].indices
= IXGBE_MAX_DCB_INDICES
;
4288 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
4289 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
4290 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
4291 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
4292 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4293 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
4294 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
4295 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
4296 if (dev
->features
& NETIF_F_NTUPLE
) {
4297 /* Flow Director perfect filter enabled */
4298 adapter
->flags
|= IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4299 adapter
->atr_sample_rate
= 0;
4300 spin_lock_init(&adapter
->fdir_perfect_lock
);
4302 /* Flow Director hash filters enabled */
4303 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4304 adapter
->atr_sample_rate
= 20;
4306 adapter
->ring_feature
[RING_F_FDIR
].indices
=
4307 IXGBE_MAX_FDIR_INDICES
;
4308 adapter
->fdir_pballoc
= 0;
4310 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
4311 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
4312 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
4313 #ifdef CONFIG_IXGBE_DCB
4314 /* Default traffic class to use for FCoE */
4315 adapter
->fcoe
.tc
= IXGBE_FCOE_DEFTC
;
4317 #endif /* IXGBE_FCOE */
4320 #ifdef CONFIG_IXGBE_DCB
4321 /* Configure DCB traffic classes */
4322 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
4323 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
4324 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
4325 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4326 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
4327 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4328 tc
->dcb_pfc
= pfc_disabled
;
4330 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
4331 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
4332 adapter
->dcb_cfg
.rx_pba_cfg
= pba_equal
;
4333 adapter
->dcb_cfg
.pfc_mode_enable
= false;
4334 adapter
->dcb_cfg
.round_robin_enable
= false;
4335 adapter
->dcb_set_bitmap
= 0x00;
4336 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
4337 adapter
->ring_feature
[RING_F_DCB
].indices
);
4341 /* default flow control settings */
4342 hw
->fc
.requested_mode
= ixgbe_fc_full
;
4343 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
4345 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
4347 hw
->fc
.high_water
= IXGBE_DEFAULT_FCRTH
;
4348 hw
->fc
.low_water
= IXGBE_DEFAULT_FCRTL
;
4349 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
4350 hw
->fc
.send_xon
= true;
4351 hw
->fc
.disable_fc_autoneg
= false;
4353 /* enable itr by default in dynamic mode */
4354 adapter
->rx_itr_setting
= 1;
4355 adapter
->rx_eitr_param
= 20000;
4356 adapter
->tx_itr_setting
= 1;
4357 adapter
->tx_eitr_param
= 10000;
4359 /* set defaults for eitr in MegaBytes */
4360 adapter
->eitr_low
= 10;
4361 adapter
->eitr_high
= 20;
4363 /* set default ring sizes */
4364 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
4365 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
4367 /* initialize eeprom parameters */
4368 if (ixgbe_init_eeprom_params_generic(hw
)) {
4369 dev_err(&pdev
->dev
, "EEPROM initialization failed\n");
4373 /* enable rx csum by default */
4374 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
4376 /* get assigned NUMA node */
4377 adapter
->node
= dev_to_node(&pdev
->dev
);
4379 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4385 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4386 * @adapter: board private structure
4387 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4389 * Return 0 on success, negative on failure
4391 int ixgbe_setup_tx_resources(struct ixgbe_adapter
*adapter
,
4392 struct ixgbe_ring
*tx_ring
)
4394 struct pci_dev
*pdev
= adapter
->pdev
;
4397 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
4398 tx_ring
->tx_buffer_info
= vmalloc_node(size
, tx_ring
->numa_node
);
4399 if (!tx_ring
->tx_buffer_info
)
4400 tx_ring
->tx_buffer_info
= vmalloc(size
);
4401 if (!tx_ring
->tx_buffer_info
)
4403 memset(tx_ring
->tx_buffer_info
, 0, size
);
4405 /* round up to nearest 4K */
4406 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
4407 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
4409 tx_ring
->desc
= dma_alloc_coherent(&pdev
->dev
, tx_ring
->size
,
4410 &tx_ring
->dma
, GFP_KERNEL
);
4414 tx_ring
->next_to_use
= 0;
4415 tx_ring
->next_to_clean
= 0;
4416 tx_ring
->work_limit
= tx_ring
->count
;
4420 vfree(tx_ring
->tx_buffer_info
);
4421 tx_ring
->tx_buffer_info
= NULL
;
4422 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for the transmit "
4423 "descriptor ring\n");
4428 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4429 * @adapter: board private structure
4431 * If this function returns with an error, then it's possible one or
4432 * more of the rings is populated (while the rest are not). It is the
4433 * callers duty to clean those orphaned rings.
4435 * Return 0 on success, negative on failure
4437 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
4441 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4442 err
= ixgbe_setup_tx_resources(adapter
, adapter
->tx_ring
[i
]);
4445 DPRINTK(PROBE
, ERR
, "Allocation for Tx Queue %u failed\n", i
);
4453 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4454 * @adapter: board private structure
4455 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4457 * Returns 0 on success, negative on failure
4459 int ixgbe_setup_rx_resources(struct ixgbe_adapter
*adapter
,
4460 struct ixgbe_ring
*rx_ring
)
4462 struct pci_dev
*pdev
= adapter
->pdev
;
4465 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
4466 rx_ring
->rx_buffer_info
= vmalloc_node(size
, adapter
->node
);
4467 if (!rx_ring
->rx_buffer_info
)
4468 rx_ring
->rx_buffer_info
= vmalloc(size
);
4469 if (!rx_ring
->rx_buffer_info
) {
4471 "vmalloc allocation failed for the rx desc ring\n");
4474 memset(rx_ring
->rx_buffer_info
, 0, size
);
4476 /* Round up to nearest 4K */
4477 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
4478 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
4480 rx_ring
->desc
= dma_alloc_coherent(&pdev
->dev
, rx_ring
->size
,
4481 &rx_ring
->dma
, GFP_KERNEL
);
4483 if (!rx_ring
->desc
) {
4485 "Memory allocation failed for the rx desc ring\n");
4486 vfree(rx_ring
->rx_buffer_info
);
4490 rx_ring
->next_to_clean
= 0;
4491 rx_ring
->next_to_use
= 0;
4500 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4501 * @adapter: board private structure
4503 * If this function returns with an error, then it's possible one or
4504 * more of the rings is populated (while the rest are not). It is the
4505 * callers duty to clean those orphaned rings.
4507 * Return 0 on success, negative on failure
4510 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
4514 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4515 err
= ixgbe_setup_rx_resources(adapter
, adapter
->rx_ring
[i
]);
4518 DPRINTK(PROBE
, ERR
, "Allocation for Rx Queue %u failed\n", i
);
4526 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4527 * @adapter: board private structure
4528 * @tx_ring: Tx descriptor ring for a specific queue
4530 * Free all transmit software resources
4532 void ixgbe_free_tx_resources(struct ixgbe_adapter
*adapter
,
4533 struct ixgbe_ring
*tx_ring
)
4535 struct pci_dev
*pdev
= adapter
->pdev
;
4537 ixgbe_clean_tx_ring(adapter
, tx_ring
);
4539 vfree(tx_ring
->tx_buffer_info
);
4540 tx_ring
->tx_buffer_info
= NULL
;
4542 dma_free_coherent(&pdev
->dev
, tx_ring
->size
, tx_ring
->desc
,
4545 tx_ring
->desc
= NULL
;
4549 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4550 * @adapter: board private structure
4552 * Free all transmit software resources
4554 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
4558 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4559 if (adapter
->tx_ring
[i
]->desc
)
4560 ixgbe_free_tx_resources(adapter
, adapter
->tx_ring
[i
]);
4564 * ixgbe_free_rx_resources - Free Rx Resources
4565 * @adapter: board private structure
4566 * @rx_ring: ring to clean the resources from
4568 * Free all receive software resources
4570 void ixgbe_free_rx_resources(struct ixgbe_adapter
*adapter
,
4571 struct ixgbe_ring
*rx_ring
)
4573 struct pci_dev
*pdev
= adapter
->pdev
;
4575 ixgbe_clean_rx_ring(adapter
, rx_ring
);
4577 vfree(rx_ring
->rx_buffer_info
);
4578 rx_ring
->rx_buffer_info
= NULL
;
4580 dma_free_coherent(&pdev
->dev
, rx_ring
->size
, rx_ring
->desc
,
4583 rx_ring
->desc
= NULL
;
4587 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4588 * @adapter: board private structure
4590 * Free all receive software resources
4592 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
4596 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4597 if (adapter
->rx_ring
[i
]->desc
)
4598 ixgbe_free_rx_resources(adapter
, adapter
->rx_ring
[i
]);
4602 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4603 * @netdev: network interface device structure
4604 * @new_mtu: new value for maximum frame size
4606 * Returns 0 on success, negative on failure
4608 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
4610 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4611 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
4613 /* MTU < 68 is an error and causes problems on some kernels */
4614 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
4617 DPRINTK(PROBE
, INFO
, "changing MTU from %d to %d\n",
4618 netdev
->mtu
, new_mtu
);
4619 /* must set new MTU before calling down or up */
4620 netdev
->mtu
= new_mtu
;
4622 if (netif_running(netdev
))
4623 ixgbe_reinit_locked(adapter
);
4629 * ixgbe_open - Called when a network interface is made active
4630 * @netdev: network interface device structure
4632 * Returns 0 on success, negative value on failure
4634 * The open entry point is called when a network interface is made
4635 * active by the system (IFF_UP). At this point all resources needed
4636 * for transmit and receive operations are allocated, the interrupt
4637 * handler is registered with the OS, the watchdog timer is started,
4638 * and the stack is notified that the interface is ready.
4640 static int ixgbe_open(struct net_device
*netdev
)
4642 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4645 /* disallow open during test */
4646 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
4649 netif_carrier_off(netdev
);
4651 /* allocate transmit descriptors */
4652 err
= ixgbe_setup_all_tx_resources(adapter
);
4656 /* allocate receive descriptors */
4657 err
= ixgbe_setup_all_rx_resources(adapter
);
4661 ixgbe_configure(adapter
);
4663 err
= ixgbe_request_irq(adapter
);
4667 err
= ixgbe_up_complete(adapter
);
4671 netif_tx_start_all_queues(netdev
);
4676 ixgbe_release_hw_control(adapter
);
4677 ixgbe_free_irq(adapter
);
4680 ixgbe_free_all_rx_resources(adapter
);
4682 ixgbe_free_all_tx_resources(adapter
);
4683 ixgbe_reset(adapter
);
4689 * ixgbe_close - Disables a network interface
4690 * @netdev: network interface device structure
4692 * Returns 0, this is not allowed to fail
4694 * The close entry point is called when an interface is de-activated
4695 * by the OS. The hardware is still under the drivers control, but
4696 * needs to be disabled. A global MAC reset is issued to stop the
4697 * hardware, and all transmit and receive resources are freed.
4699 static int ixgbe_close(struct net_device
*netdev
)
4701 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4703 ixgbe_down(adapter
);
4704 ixgbe_free_irq(adapter
);
4706 ixgbe_free_all_tx_resources(adapter
);
4707 ixgbe_free_all_rx_resources(adapter
);
4709 ixgbe_release_hw_control(adapter
);
4715 static int ixgbe_resume(struct pci_dev
*pdev
)
4717 struct net_device
*netdev
= pci_get_drvdata(pdev
);
4718 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4721 pci_set_power_state(pdev
, PCI_D0
);
4722 pci_restore_state(pdev
);
4724 * pci_restore_state clears dev->state_saved so call
4725 * pci_save_state to restore it.
4727 pci_save_state(pdev
);
4729 err
= pci_enable_device_mem(pdev
);
4731 printk(KERN_ERR
"ixgbe: Cannot enable PCI device from "
4735 pci_set_master(pdev
);
4737 pci_wake_from_d3(pdev
, false);
4739 err
= ixgbe_init_interrupt_scheme(adapter
);
4741 printk(KERN_ERR
"ixgbe: Cannot initialize interrupts for "
4746 ixgbe_reset(adapter
);
4748 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
4750 if (netif_running(netdev
)) {
4751 err
= ixgbe_open(adapter
->netdev
);
4756 netif_device_attach(netdev
);
4760 #endif /* CONFIG_PM */
4762 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
4764 struct net_device
*netdev
= pci_get_drvdata(pdev
);
4765 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4766 struct ixgbe_hw
*hw
= &adapter
->hw
;
4768 u32 wufc
= adapter
->wol
;
4773 netif_device_detach(netdev
);
4775 if (netif_running(netdev
)) {
4776 ixgbe_down(adapter
);
4777 ixgbe_free_irq(adapter
);
4778 ixgbe_free_all_tx_resources(adapter
);
4779 ixgbe_free_all_rx_resources(adapter
);
4781 ixgbe_clear_interrupt_scheme(adapter
);
4784 retval
= pci_save_state(pdev
);
4790 ixgbe_set_rx_mode(netdev
);
4792 /* turn on all-multi mode if wake on multicast is enabled */
4793 if (wufc
& IXGBE_WUFC_MC
) {
4794 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
4795 fctrl
|= IXGBE_FCTRL_MPE
;
4796 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
4799 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
4800 ctrl
|= IXGBE_CTRL_GIO_DIS
;
4801 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
4803 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
4805 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
4806 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
4809 if (wufc
&& hw
->mac
.type
== ixgbe_mac_82599EB
)
4810 pci_wake_from_d3(pdev
, true);
4812 pci_wake_from_d3(pdev
, false);
4814 *enable_wake
= !!wufc
;
4816 ixgbe_release_hw_control(adapter
);
4818 pci_disable_device(pdev
);
4824 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4829 retval
= __ixgbe_shutdown(pdev
, &wake
);
4834 pci_prepare_to_sleep(pdev
);
4836 pci_wake_from_d3(pdev
, false);
4837 pci_set_power_state(pdev
, PCI_D3hot
);
4842 #endif /* CONFIG_PM */
4844 static void ixgbe_shutdown(struct pci_dev
*pdev
)
4848 __ixgbe_shutdown(pdev
, &wake
);
4850 if (system_state
== SYSTEM_POWER_OFF
) {
4851 pci_wake_from_d3(pdev
, wake
);
4852 pci_set_power_state(pdev
, PCI_D3hot
);
4857 * ixgbe_update_stats - Update the board statistics counters.
4858 * @adapter: board private structure
4860 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
4862 struct net_device
*netdev
= adapter
->netdev
;
4863 struct ixgbe_hw
*hw
= &adapter
->hw
;
4865 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
4866 u64 non_eop_descs
= 0, restart_queue
= 0;
4868 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
4871 for (i
= 0; i
< 16; i
++)
4872 adapter
->hw_rx_no_dma_resources
+=
4873 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
4874 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4875 rsc_count
+= adapter
->rx_ring
[i
]->rsc_count
;
4876 rsc_flush
+= adapter
->rx_ring
[i
]->rsc_flush
;
4878 adapter
->rsc_total_count
= rsc_count
;
4879 adapter
->rsc_total_flush
= rsc_flush
;
4882 /* gather some stats to the adapter struct that are per queue */
4883 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4884 restart_queue
+= adapter
->tx_ring
[i
]->restart_queue
;
4885 adapter
->restart_queue
= restart_queue
;
4887 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4888 non_eop_descs
+= adapter
->rx_ring
[i
]->non_eop_descs
;
4889 adapter
->non_eop_descs
= non_eop_descs
;
4891 adapter
->stats
.crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
4892 for (i
= 0; i
< 8; i
++) {
4893 /* for packet buffers not used, the register should read 0 */
4894 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
4896 adapter
->stats
.mpc
[i
] += mpc
;
4897 total_mpc
+= adapter
->stats
.mpc
[i
];
4898 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
4899 adapter
->stats
.rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
4900 adapter
->stats
.qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
4901 adapter
->stats
.qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
4902 adapter
->stats
.qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
4903 adapter
->stats
.qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
4904 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4905 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
4906 IXGBE_PXONRXCNT(i
));
4907 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
4908 IXGBE_PXOFFRXCNT(i
));
4909 adapter
->stats
.qprdc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
4911 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
4913 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
4916 adapter
->stats
.pxontxc
[i
] += IXGBE_READ_REG(hw
,
4918 adapter
->stats
.pxofftxc
[i
] += IXGBE_READ_REG(hw
,
4921 adapter
->stats
.gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
4922 /* work around hardware counting issue */
4923 adapter
->stats
.gprc
-= missed_rx
;
4925 /* 82598 hardware only has a 32 bit counter in the high register */
4926 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4928 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
4929 tmp
= IXGBE_READ_REG(hw
, IXGBE_GORCH
) & 0xF; /* 4 high bits of GORC */
4930 adapter
->stats
.gorc
+= (tmp
<< 32);
4931 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
4932 tmp
= IXGBE_READ_REG(hw
, IXGBE_GOTCH
) & 0xF; /* 4 high bits of GOTC */
4933 adapter
->stats
.gotc
+= (tmp
<< 32);
4934 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
4935 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
4936 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
4937 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
4938 adapter
->stats
.fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
4939 adapter
->stats
.fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
4941 adapter
->stats
.fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
4942 adapter
->stats
.fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
4943 adapter
->stats
.fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
4944 adapter
->stats
.fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
4945 adapter
->stats
.fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
4946 adapter
->stats
.fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
4947 #endif /* IXGBE_FCOE */
4949 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
4950 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
4951 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
4952 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
4953 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
4955 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
4956 adapter
->stats
.bprc
+= bprc
;
4957 adapter
->stats
.mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
4958 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
4959 adapter
->stats
.mprc
-= bprc
;
4960 adapter
->stats
.roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
4961 adapter
->stats
.prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
4962 adapter
->stats
.prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
4963 adapter
->stats
.prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
4964 adapter
->stats
.prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
4965 adapter
->stats
.prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
4966 adapter
->stats
.prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
4967 adapter
->stats
.rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
4968 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
4969 adapter
->stats
.lxontxc
+= lxon
;
4970 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
4971 adapter
->stats
.lxofftxc
+= lxoff
;
4972 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
4973 adapter
->stats
.gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
4974 adapter
->stats
.mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
4976 * 82598 errata - tx of flow control packets is included in tx counters
4978 xon_off_tot
= lxon
+ lxoff
;
4979 adapter
->stats
.gptc
-= xon_off_tot
;
4980 adapter
->stats
.mptc
-= xon_off_tot
;
4981 adapter
->stats
.gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
4982 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
4983 adapter
->stats
.rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
4984 adapter
->stats
.rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
4985 adapter
->stats
.tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
4986 adapter
->stats
.ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
4987 adapter
->stats
.ptc64
-= xon_off_tot
;
4988 adapter
->stats
.ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
4989 adapter
->stats
.ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
4990 adapter
->stats
.ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
4991 adapter
->stats
.ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
4992 adapter
->stats
.ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
4993 adapter
->stats
.bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
4995 /* Fill out the OS statistics structure */
4996 netdev
->stats
.multicast
= adapter
->stats
.mprc
;
4999 netdev
->stats
.rx_errors
= adapter
->stats
.crcerrs
+
5000 adapter
->stats
.rlec
;
5001 netdev
->stats
.rx_dropped
= 0;
5002 netdev
->stats
.rx_length_errors
= adapter
->stats
.rlec
;
5003 netdev
->stats
.rx_crc_errors
= adapter
->stats
.crcerrs
;
5004 netdev
->stats
.rx_missed_errors
= total_mpc
;
5008 * ixgbe_watchdog - Timer Call-back
5009 * @data: pointer to adapter cast into an unsigned long
5011 static void ixgbe_watchdog(unsigned long data
)
5013 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
5014 struct ixgbe_hw
*hw
= &adapter
->hw
;
5019 * Do the watchdog outside of interrupt context due to the lovely
5020 * delays that some of the newer hardware requires
5023 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5024 goto watchdog_short_circuit
;
5026 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
5028 * for legacy and MSI interrupts don't set any bits
5029 * that are enabled for EIAM, because this operation
5030 * would set *both* EIMS and EICS for any bit in EIAM
5032 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
5033 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
5034 goto watchdog_reschedule
;
5037 /* get one bit for every active tx/rx interrupt vector */
5038 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
5039 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
5040 if (qv
->rxr_count
|| qv
->txr_count
)
5041 eics
|= ((u64
)1 << i
);
5044 /* Cause software interrupt to ensure rx rings are cleaned */
5045 ixgbe_irq_rearm_queues(adapter
, eics
);
5047 watchdog_reschedule
:
5048 /* Reset the timer */
5049 mod_timer(&adapter
->watchdog_timer
, round_jiffies(jiffies
+ 2 * HZ
));
5051 watchdog_short_circuit
:
5052 schedule_work(&adapter
->watchdog_task
);
5056 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5057 * @work: pointer to work_struct containing our data
5059 static void ixgbe_multispeed_fiber_task(struct work_struct
*work
)
5061 struct ixgbe_adapter
*adapter
= container_of(work
,
5062 struct ixgbe_adapter
,
5063 multispeed_fiber_task
);
5064 struct ixgbe_hw
*hw
= &adapter
->hw
;
5068 adapter
->flags
|= IXGBE_FLAG_IN_SFP_LINK_TASK
;
5069 autoneg
= hw
->phy
.autoneg_advertised
;
5070 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
5071 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
5072 hw
->mac
.autotry_restart
= false;
5073 if (hw
->mac
.ops
.setup_link
)
5074 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
5075 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
5076 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_LINK_TASK
;
5080 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5081 * @work: pointer to work_struct containing our data
5083 static void ixgbe_sfp_config_module_task(struct work_struct
*work
)
5085 struct ixgbe_adapter
*adapter
= container_of(work
,
5086 struct ixgbe_adapter
,
5087 sfp_config_module_task
);
5088 struct ixgbe_hw
*hw
= &adapter
->hw
;
5091 adapter
->flags
|= IXGBE_FLAG_IN_SFP_MOD_TASK
;
5093 /* Time for electrical oscillations to settle down */
5095 err
= hw
->phy
.ops
.identify_sfp(hw
);
5097 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5098 dev_err(&adapter
->pdev
->dev
, "failed to initialize because "
5099 "an unsupported SFP+ module type was detected.\n"
5100 "Reload the driver after installing a supported "
5102 unregister_netdev(adapter
->netdev
);
5105 hw
->mac
.ops
.setup_sfp(hw
);
5107 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
5108 /* This will also work for DA Twinax connections */
5109 schedule_work(&adapter
->multispeed_fiber_task
);
5110 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_MOD_TASK
;
5114 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5115 * @work: pointer to work_struct containing our data
5117 static void ixgbe_fdir_reinit_task(struct work_struct
*work
)
5119 struct ixgbe_adapter
*adapter
= container_of(work
,
5120 struct ixgbe_adapter
,
5122 struct ixgbe_hw
*hw
= &adapter
->hw
;
5125 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
5126 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5127 set_bit(__IXGBE_FDIR_INIT_DONE
,
5128 &(adapter
->tx_ring
[i
]->reinit_state
));
5130 DPRINTK(PROBE
, ERR
, "failed to finish FDIR re-initialization, "
5131 "ignored adding FDIR ATR filters\n");
5133 /* Done FDIR Re-initialization, enable transmits */
5134 netif_tx_start_all_queues(adapter
->netdev
);
5137 static DEFINE_MUTEX(ixgbe_watchdog_lock
);
5140 * ixgbe_watchdog_task - worker thread to bring link up
5141 * @work: pointer to work_struct containing our data
5143 static void ixgbe_watchdog_task(struct work_struct
*work
)
5145 struct ixgbe_adapter
*adapter
= container_of(work
,
5146 struct ixgbe_adapter
,
5148 struct net_device
*netdev
= adapter
->netdev
;
5149 struct ixgbe_hw
*hw
= &adapter
->hw
;
5153 struct ixgbe_ring
*tx_ring
;
5154 int some_tx_pending
= 0;
5156 mutex_lock(&ixgbe_watchdog_lock
);
5158 link_up
= adapter
->link_up
;
5159 link_speed
= adapter
->link_speed
;
5161 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
) {
5162 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
5165 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5166 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
5167 hw
->mac
.ops
.fc_enable(hw
, i
);
5169 hw
->mac
.ops
.fc_enable(hw
, 0);
5172 hw
->mac
.ops
.fc_enable(hw
, 0);
5177 time_after(jiffies
, (adapter
->link_check_timeout
+
5178 IXGBE_TRY_LINK_TIMEOUT
))) {
5179 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
5180 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
5182 adapter
->link_up
= link_up
;
5183 adapter
->link_speed
= link_speed
;
5187 if (!netif_carrier_ok(netdev
)) {
5188 bool flow_rx
, flow_tx
;
5190 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5191 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
5192 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
5193 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
5194 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
5196 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5197 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
5198 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
5199 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
5202 printk(KERN_INFO
"ixgbe: %s NIC Link is Up %s, "
5203 "Flow Control: %s\n",
5205 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
5207 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
5208 "1 Gbps" : "unknown speed")),
5209 ((flow_rx
&& flow_tx
) ? "RX/TX" :
5211 (flow_tx
? "TX" : "None"))));
5213 netif_carrier_on(netdev
);
5215 /* Force detection of hung controller */
5216 adapter
->detect_tx_hung
= true;
5219 adapter
->link_up
= false;
5220 adapter
->link_speed
= 0;
5221 if (netif_carrier_ok(netdev
)) {
5222 printk(KERN_INFO
"ixgbe: %s NIC Link is Down\n",
5224 netif_carrier_off(netdev
);
5228 if (!netif_carrier_ok(netdev
)) {
5229 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5230 tx_ring
= adapter
->tx_ring
[i
];
5231 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
5232 some_tx_pending
= 1;
5237 if (some_tx_pending
) {
5238 /* We've lost link, so the controller stops DMA,
5239 * but we've got queued Tx work that's never going
5240 * to get done, so reset controller to flush Tx.
5241 * (Do the reset outside of interrupt context).
5243 schedule_work(&adapter
->reset_task
);
5247 ixgbe_update_stats(adapter
);
5248 mutex_unlock(&ixgbe_watchdog_lock
);
5251 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
5252 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
5253 u32 tx_flags
, u8
*hdr_len
)
5255 struct ixgbe_adv_tx_context_desc
*context_desc
;
5258 struct ixgbe_tx_buffer
*tx_buffer_info
;
5259 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
5260 u32 mss_l4len_idx
, l4len
;
5262 if (skb_is_gso(skb
)) {
5263 if (skb_header_cloned(skb
)) {
5264 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
5268 l4len
= tcp_hdrlen(skb
);
5271 if (skb
->protocol
== htons(ETH_P_IP
)) {
5272 struct iphdr
*iph
= ip_hdr(skb
);
5275 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5279 } else if (skb_is_gso_v6(skb
)) {
5280 ipv6_hdr(skb
)->payload_len
= 0;
5281 tcp_hdr(skb
)->check
=
5282 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
5283 &ipv6_hdr(skb
)->daddr
,
5287 i
= tx_ring
->next_to_use
;
5289 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5290 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
5292 /* VLAN MACLEN IPLEN */
5293 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5295 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5296 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
5297 IXGBE_ADVTXD_MACLEN_SHIFT
);
5298 *hdr_len
+= skb_network_offset(skb
);
5300 (skb_transport_header(skb
) - skb_network_header(skb
));
5302 (skb_transport_header(skb
) - skb_network_header(skb
));
5303 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5304 context_desc
->seqnum_seed
= 0;
5306 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5307 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
5308 IXGBE_ADVTXD_DTYP_CTXT
);
5310 if (skb
->protocol
== htons(ETH_P_IP
))
5311 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5312 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5313 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5317 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
5318 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
5319 /* use index 1 for TSO */
5320 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5321 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
5323 tx_buffer_info
->time_stamp
= jiffies
;
5324 tx_buffer_info
->next_to_watch
= i
;
5327 if (i
== tx_ring
->count
)
5329 tx_ring
->next_to_use
= i
;
5336 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
5337 struct ixgbe_ring
*tx_ring
,
5338 struct sk_buff
*skb
, u32 tx_flags
)
5340 struct ixgbe_adv_tx_context_desc
*context_desc
;
5342 struct ixgbe_tx_buffer
*tx_buffer_info
;
5343 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
5345 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
5346 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
5347 i
= tx_ring
->next_to_use
;
5348 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5349 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
5351 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5353 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5354 vlan_macip_lens
|= (skb_network_offset(skb
) <<
5355 IXGBE_ADVTXD_MACLEN_SHIFT
);
5356 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5357 vlan_macip_lens
|= (skb_transport_header(skb
) -
5358 skb_network_header(skb
));
5360 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5361 context_desc
->seqnum_seed
= 0;
5363 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
5364 IXGBE_ADVTXD_DTYP_CTXT
);
5366 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5369 if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
)) {
5370 const struct vlan_ethhdr
*vhdr
=
5371 (const struct vlan_ethhdr
*)skb
->data
;
5373 protocol
= vhdr
->h_vlan_encapsulated_proto
;
5375 protocol
= skb
->protocol
;
5379 case cpu_to_be16(ETH_P_IP
):
5380 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5381 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
5383 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5384 else if (ip_hdr(skb
)->protocol
== IPPROTO_SCTP
)
5386 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5388 case cpu_to_be16(ETH_P_IPV6
):
5389 /* XXX what about other V6 headers?? */
5390 if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_TCP
)
5392 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5393 else if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_SCTP
)
5395 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5398 if (unlikely(net_ratelimit())) {
5399 DPRINTK(PROBE
, WARNING
,
5400 "partial checksum but proto=%x!\n",
5407 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5408 /* use index zero for tx checksum offload */
5409 context_desc
->mss_l4len_idx
= 0;
5411 tx_buffer_info
->time_stamp
= jiffies
;
5412 tx_buffer_info
->next_to_watch
= i
;
5415 if (i
== tx_ring
->count
)
5417 tx_ring
->next_to_use
= i
;
5425 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
5426 struct ixgbe_ring
*tx_ring
,
5427 struct sk_buff
*skb
, u32 tx_flags
,
5430 struct pci_dev
*pdev
= adapter
->pdev
;
5431 struct ixgbe_tx_buffer
*tx_buffer_info
;
5433 unsigned int total
= skb
->len
;
5434 unsigned int offset
= 0, size
, count
= 0, i
;
5435 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
5438 i
= tx_ring
->next_to_use
;
5440 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
5441 /* excluding fcoe_crc_eof for FCoE */
5442 total
-= sizeof(struct fcoe_crc_eof
);
5444 len
= min(skb_headlen(skb
), total
);
5446 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5447 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5449 tx_buffer_info
->length
= size
;
5450 tx_buffer_info
->mapped_as_page
= false;
5451 tx_buffer_info
->dma
= dma_map_single(&pdev
->dev
,
5453 size
, DMA_TO_DEVICE
);
5454 if (dma_mapping_error(&pdev
->dev
, tx_buffer_info
->dma
))
5456 tx_buffer_info
->time_stamp
= jiffies
;
5457 tx_buffer_info
->next_to_watch
= i
;
5466 if (i
== tx_ring
->count
)
5471 for (f
= 0; f
< nr_frags
; f
++) {
5472 struct skb_frag_struct
*frag
;
5474 frag
= &skb_shinfo(skb
)->frags
[f
];
5475 len
= min((unsigned int)frag
->size
, total
);
5476 offset
= frag
->page_offset
;
5480 if (i
== tx_ring
->count
)
5483 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5484 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5486 tx_buffer_info
->length
= size
;
5487 tx_buffer_info
->dma
= dma_map_page(&adapter
->pdev
->dev
,
5491 tx_buffer_info
->mapped_as_page
= true;
5492 if (dma_mapping_error(&pdev
->dev
, tx_buffer_info
->dma
))
5494 tx_buffer_info
->time_stamp
= jiffies
;
5495 tx_buffer_info
->next_to_watch
= i
;
5506 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
5507 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
5512 dev_err(&pdev
->dev
, "TX DMA map failed\n");
5514 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5515 tx_buffer_info
->dma
= 0;
5516 tx_buffer_info
->time_stamp
= 0;
5517 tx_buffer_info
->next_to_watch
= 0;
5521 /* clear timestamp and dma mappings for remaining portion of packet */
5524 i
+= tx_ring
->count
;
5526 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5527 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
5533 static void ixgbe_tx_queue(struct ixgbe_adapter
*adapter
,
5534 struct ixgbe_ring
*tx_ring
,
5535 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
5537 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
5538 struct ixgbe_tx_buffer
*tx_buffer_info
;
5539 u32 olinfo_status
= 0, cmd_type_len
= 0;
5541 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
5543 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
5545 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
5547 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5548 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
5550 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
5551 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
5553 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
5554 IXGBE_ADVTXD_POPTS_SHIFT
;
5556 /* use index 1 context for tso */
5557 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5558 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
5559 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
5560 IXGBE_ADVTXD_POPTS_SHIFT
;
5562 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
5563 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
5564 IXGBE_ADVTXD_POPTS_SHIFT
;
5566 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
5567 olinfo_status
|= IXGBE_ADVTXD_CC
;
5568 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5569 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
5570 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
5573 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
5575 i
= tx_ring
->next_to_use
;
5577 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5578 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
5579 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
5580 tx_desc
->read
.cmd_type_len
=
5581 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
5582 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
5584 if (i
== tx_ring
->count
)
5588 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
5591 * Force memory writes to complete before letting h/w
5592 * know there are new descriptors to fetch. (Only
5593 * applicable for weak-ordered memory model archs,
5598 tx_ring
->next_to_use
= i
;
5599 writel(i
, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
5602 static void ixgbe_atr(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
5603 int queue
, u32 tx_flags
)
5605 /* Right now, we support IPv4 only */
5606 struct ixgbe_atr_input atr_input
;
5608 struct iphdr
*iph
= ip_hdr(skb
);
5609 struct ethhdr
*eth
= (struct ethhdr
*)skb
->data
;
5610 u16 vlan_id
, src_port
, dst_port
, flex_bytes
;
5611 u32 src_ipv4_addr
, dst_ipv4_addr
;
5614 /* check if we're UDP or TCP */
5615 if (iph
->protocol
== IPPROTO_TCP
) {
5617 src_port
= th
->source
;
5618 dst_port
= th
->dest
;
5619 l4type
|= IXGBE_ATR_L4TYPE_TCP
;
5620 /* l4type IPv4 type is 0, no need to assign */
5622 /* Unsupported L4 header, just bail here */
5626 memset(&atr_input
, 0, sizeof(struct ixgbe_atr_input
));
5628 vlan_id
= (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
) >>
5629 IXGBE_TX_FLAGS_VLAN_SHIFT
;
5630 src_ipv4_addr
= iph
->saddr
;
5631 dst_ipv4_addr
= iph
->daddr
;
5632 flex_bytes
= eth
->h_proto
;
5634 ixgbe_atr_set_vlan_id_82599(&atr_input
, vlan_id
);
5635 ixgbe_atr_set_src_port_82599(&atr_input
, dst_port
);
5636 ixgbe_atr_set_dst_port_82599(&atr_input
, src_port
);
5637 ixgbe_atr_set_flex_byte_82599(&atr_input
, flex_bytes
);
5638 ixgbe_atr_set_l4type_82599(&atr_input
, l4type
);
5639 /* src and dst are inverted, think how the receiver sees them */
5640 ixgbe_atr_set_src_ipv4_82599(&atr_input
, dst_ipv4_addr
);
5641 ixgbe_atr_set_dst_ipv4_82599(&atr_input
, src_ipv4_addr
);
5643 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5644 ixgbe_fdir_add_signature_filter_82599(&adapter
->hw
, &atr_input
, queue
);
5647 static int __ixgbe_maybe_stop_tx(struct net_device
*netdev
,
5648 struct ixgbe_ring
*tx_ring
, int size
)
5650 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
5651 /* Herbert's original patch had:
5652 * smp_mb__after_netif_stop_queue();
5653 * but since that doesn't exist yet, just open code it. */
5656 /* We need to check again in a case another CPU has just
5657 * made room available. */
5658 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
5661 /* A reprieve! - use start_queue because it doesn't call schedule */
5662 netif_start_subqueue(netdev
, tx_ring
->queue_index
);
5663 ++tx_ring
->restart_queue
;
5667 static int ixgbe_maybe_stop_tx(struct net_device
*netdev
,
5668 struct ixgbe_ring
*tx_ring
, int size
)
5670 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
5672 return __ixgbe_maybe_stop_tx(netdev
, tx_ring
, size
);
5675 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
5677 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
5678 int txq
= smp_processor_id();
5680 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
5681 while (unlikely(txq
>= dev
->real_num_tx_queues
))
5682 txq
-= dev
->real_num_tx_queues
;
5687 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
5688 ((skb
->protocol
== htons(ETH_P_FCOE
)) ||
5689 (skb
->protocol
== htons(ETH_P_FIP
)))) {
5690 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
5691 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
5695 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5696 if (skb
->priority
== TC_PRIO_CONTROL
)
5697 txq
= adapter
->ring_feature
[RING_F_DCB
].indices
-1;
5699 txq
= (skb
->vlan_tci
& IXGBE_TX_FLAGS_VLAN_PRIO_MASK
)
5704 return skb_tx_hash(dev
, skb
);
5707 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
,
5708 struct net_device
*netdev
)
5710 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5711 struct ixgbe_ring
*tx_ring
;
5712 struct netdev_queue
*txq
;
5714 unsigned int tx_flags
= 0;
5720 if (adapter
->vlgrp
&& vlan_tx_tag_present(skb
)) {
5721 tx_flags
|= vlan_tx_tag_get(skb
);
5722 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5723 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
5724 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
5726 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
5727 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
5728 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5729 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
5730 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
5731 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
5734 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
5737 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
5738 #ifdef CONFIG_IXGBE_DCB
5739 /* for FCoE with DCB, we force the priority to what
5740 * was specified by the switch */
5741 if ((skb
->protocol
== htons(ETH_P_FCOE
)) ||
5742 (skb
->protocol
== htons(ETH_P_FIP
))) {
5743 tx_flags
&= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5744 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
5745 tx_flags
|= ((adapter
->fcoe
.up
<< 13)
5746 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
5749 /* flag for FCoE offloads */
5750 if (skb
->protocol
== htons(ETH_P_FCOE
))
5751 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
5755 /* four things can cause us to need a context descriptor */
5756 if (skb_is_gso(skb
) ||
5757 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
5758 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
5759 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
5762 count
+= TXD_USE_COUNT(skb_headlen(skb
));
5763 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
5764 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
5766 if (ixgbe_maybe_stop_tx(netdev
, tx_ring
, count
)) {
5768 return NETDEV_TX_BUSY
;
5771 first
= tx_ring
->next_to_use
;
5772 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
5774 /* setup tx offload for FCoE */
5775 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
5777 dev_kfree_skb_any(skb
);
5778 return NETDEV_TX_OK
;
5781 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
5782 #endif /* IXGBE_FCOE */
5784 if (skb
->protocol
== htons(ETH_P_IP
))
5785 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
5786 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
5788 dev_kfree_skb_any(skb
);
5789 return NETDEV_TX_OK
;
5793 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
5794 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
) &&
5795 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
5796 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
5799 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
);
5801 /* add the ATR filter if ATR is on */
5802 if (tx_ring
->atr_sample_rate
) {
5803 ++tx_ring
->atr_count
;
5804 if ((tx_ring
->atr_count
>= tx_ring
->atr_sample_rate
) &&
5805 test_bit(__IXGBE_FDIR_INIT_DONE
,
5806 &tx_ring
->reinit_state
)) {
5807 ixgbe_atr(adapter
, skb
, tx_ring
->queue_index
,
5809 tx_ring
->atr_count
= 0;
5812 txq
= netdev_get_tx_queue(netdev
, tx_ring
->queue_index
);
5813 txq
->tx_bytes
+= skb
->len
;
5815 ixgbe_tx_queue(adapter
, tx_ring
, tx_flags
, count
, skb
->len
,
5817 ixgbe_maybe_stop_tx(netdev
, tx_ring
, DESC_NEEDED
);
5820 dev_kfree_skb_any(skb
);
5821 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
5822 tx_ring
->next_to_use
= first
;
5825 return NETDEV_TX_OK
;
5829 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5830 * @netdev: network interface device structure
5831 * @p: pointer to an address structure
5833 * Returns 0 on success, negative on failure
5835 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
5837 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5838 struct ixgbe_hw
*hw
= &adapter
->hw
;
5839 struct sockaddr
*addr
= p
;
5841 if (!is_valid_ether_addr(addr
->sa_data
))
5842 return -EADDRNOTAVAIL
;
5844 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
5845 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
5847 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
5854 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
5856 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5857 struct ixgbe_hw
*hw
= &adapter
->hw
;
5861 if (prtad
!= hw
->phy
.mdio
.prtad
)
5863 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
5869 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
5870 u16 addr
, u16 value
)
5872 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5873 struct ixgbe_hw
*hw
= &adapter
->hw
;
5875 if (prtad
!= hw
->phy
.mdio
.prtad
)
5877 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
5880 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
5882 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5884 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
5888 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5890 * @netdev: network interface device structure
5892 * Returns non-zero on failure
5894 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
5897 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
5898 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
5900 if (is_valid_ether_addr(mac
->san_addr
)) {
5902 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
5909 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5911 * @netdev: network interface device structure
5913 * Returns non-zero on failure
5915 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
5918 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
5919 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
5921 if (is_valid_ether_addr(mac
->san_addr
)) {
5923 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
5929 #ifdef CONFIG_NET_POLL_CONTROLLER
5931 * Polling 'interrupt' - used by things like netconsole to send skbs
5932 * without having to re-enable interrupts. It's not called while
5933 * the interrupt routine is executing.
5935 static void ixgbe_netpoll(struct net_device
*netdev
)
5937 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5940 /* if interface is down do nothing */
5941 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5944 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
5945 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
5946 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
5947 for (i
= 0; i
< num_q_vectors
; i
++) {
5948 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
5949 ixgbe_msix_clean_many(0, q_vector
);
5952 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
5954 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
5958 static const struct net_device_ops ixgbe_netdev_ops
= {
5959 .ndo_open
= ixgbe_open
,
5960 .ndo_stop
= ixgbe_close
,
5961 .ndo_start_xmit
= ixgbe_xmit_frame
,
5962 .ndo_select_queue
= ixgbe_select_queue
,
5963 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
5964 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
5965 .ndo_validate_addr
= eth_validate_addr
,
5966 .ndo_set_mac_address
= ixgbe_set_mac
,
5967 .ndo_change_mtu
= ixgbe_change_mtu
,
5968 .ndo_tx_timeout
= ixgbe_tx_timeout
,
5969 .ndo_vlan_rx_register
= ixgbe_vlan_rx_register
,
5970 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
5971 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
5972 .ndo_do_ioctl
= ixgbe_ioctl
,
5973 #ifdef CONFIG_NET_POLL_CONTROLLER
5974 .ndo_poll_controller
= ixgbe_netpoll
,
5977 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
5978 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
5979 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
5980 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
5981 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
5982 #endif /* IXGBE_FCOE */
5985 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
5986 const struct ixgbe_info
*ii
)
5988 #ifdef CONFIG_PCI_IOV
5989 struct ixgbe_hw
*hw
= &adapter
->hw
;
5992 if (hw
->mac
.type
!= ixgbe_mac_82599EB
|| !max_vfs
)
5995 /* The 82599 supports up to 64 VFs per physical function
5996 * but this implementation limits allocation to 63 so that
5997 * basic networking resources are still available to the
6000 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
6001 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
6002 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
6005 "Failed to enable PCI sriov: %d\n", err
);
6008 /* If call to enable VFs succeeded then allocate memory
6009 * for per VF control structures.
6012 kcalloc(adapter
->num_vfs
,
6013 sizeof(struct vf_data_storage
), GFP_KERNEL
);
6014 if (adapter
->vfinfo
) {
6015 /* Now that we're sure SR-IOV is enabled
6016 * and memory allocated set up the mailbox parameters
6018 ixgbe_init_mbx_params_pf(hw
);
6019 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
6020 sizeof(hw
->mbx
.ops
));
6022 /* Disable RSC when in SR-IOV mode */
6023 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
6024 IXGBE_FLAG2_RSC_ENABLED
);
6030 "Unable to allocate memory for VF "
6031 "Data Storage - SRIOV disabled\n");
6032 pci_disable_sriov(adapter
->pdev
);
6035 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
6036 adapter
->num_vfs
= 0;
6037 #endif /* CONFIG_PCI_IOV */
6041 * ixgbe_probe - Device Initialization Routine
6042 * @pdev: PCI device information struct
6043 * @ent: entry in ixgbe_pci_tbl
6045 * Returns 0 on success, negative on failure
6047 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6048 * The OS initialization, configuring of the adapter private structure,
6049 * and a hardware reset occur.
6051 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
6052 const struct pci_device_id
*ent
)
6054 struct net_device
*netdev
;
6055 struct ixgbe_adapter
*adapter
= NULL
;
6056 struct ixgbe_hw
*hw
;
6057 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
6058 static int cards_found
;
6059 int i
, err
, pci_using_dac
;
6060 unsigned int indices
= num_possible_cpus();
6066 err
= pci_enable_device_mem(pdev
);
6070 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
6071 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
6074 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
6076 err
= dma_set_coherent_mask(&pdev
->dev
,
6079 dev_err(&pdev
->dev
, "No usable DMA "
6080 "configuration, aborting\n");
6087 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
6088 IORESOURCE_MEM
), ixgbe_driver_name
);
6091 "pci_request_selected_regions failed 0x%x\n", err
);
6095 pci_enable_pcie_error_reporting(pdev
);
6097 pci_set_master(pdev
);
6098 pci_save_state(pdev
);
6100 if (ii
->mac
== ixgbe_mac_82598EB
)
6101 indices
= min_t(unsigned int, indices
, IXGBE_MAX_RSS_INDICES
);
6103 indices
= min_t(unsigned int, indices
, IXGBE_MAX_FDIR_INDICES
);
6105 indices
= max_t(unsigned int, indices
, IXGBE_MAX_DCB_INDICES
);
6107 indices
+= min_t(unsigned int, num_possible_cpus(),
6108 IXGBE_MAX_FCOE_INDICES
);
6110 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), indices
);
6113 goto err_alloc_etherdev
;
6116 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
6118 pci_set_drvdata(pdev
, netdev
);
6119 adapter
= netdev_priv(netdev
);
6121 adapter
->netdev
= netdev
;
6122 adapter
->pdev
= pdev
;
6125 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
6127 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
6128 pci_resource_len(pdev
, 0));
6134 for (i
= 1; i
<= 5; i
++) {
6135 if (pci_resource_len(pdev
, i
) == 0)
6139 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
6140 ixgbe_set_ethtool_ops(netdev
);
6141 netdev
->watchdog_timeo
= 5 * HZ
;
6142 strcpy(netdev
->name
, pci_name(pdev
));
6144 adapter
->bd_number
= cards_found
;
6147 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
6148 hw
->mac
.type
= ii
->mac
;
6151 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
6152 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
6153 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6154 if (!(eec
& (1 << 8)))
6155 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
6158 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
6159 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
6160 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6161 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
6162 hw
->phy
.mdio
.mmds
= 0;
6163 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
6164 hw
->phy
.mdio
.dev
= netdev
;
6165 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
6166 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
6168 /* set up this timer and work struct before calling get_invariants
6169 * which might start the timer
6171 init_timer(&adapter
->sfp_timer
);
6172 adapter
->sfp_timer
.function
= &ixgbe_sfp_timer
;
6173 adapter
->sfp_timer
.data
= (unsigned long) adapter
;
6175 INIT_WORK(&adapter
->sfp_task
, ixgbe_sfp_task
);
6177 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6178 INIT_WORK(&adapter
->multispeed_fiber_task
, ixgbe_multispeed_fiber_task
);
6180 /* a new SFP+ module arrival, called from GPI SDP2 context */
6181 INIT_WORK(&adapter
->sfp_config_module_task
,
6182 ixgbe_sfp_config_module_task
);
6184 ii
->get_invariants(hw
);
6186 /* setup the private structure */
6187 err
= ixgbe_sw_init(adapter
);
6191 /* Make it possible the adapter to be woken up via WOL */
6192 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6193 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
6196 * If there is a fan on this device and it has failed log the
6199 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
6200 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
6201 if (esdp
& IXGBE_ESDP_SDP1
)
6202 DPRINTK(PROBE
, CRIT
,
6203 "Fan has stopped, replace the adapter\n");
6206 /* reset_hw fills in the perm_addr as well */
6207 err
= hw
->mac
.ops
.reset_hw(hw
);
6208 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
6209 hw
->mac
.type
== ixgbe_mac_82598EB
) {
6211 * Start a kernel thread to watch for a module to arrive.
6212 * Only do this for 82598, since 82599 will generate
6213 * interrupts on module arrival.
6215 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6216 mod_timer(&adapter
->sfp_timer
,
6217 round_jiffies(jiffies
+ (2 * HZ
)));
6219 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
6220 dev_err(&adapter
->pdev
->dev
, "failed to initialize because "
6221 "an unsupported SFP+ module type was detected.\n"
6222 "Reload the driver after installing a supported "
6226 dev_err(&adapter
->pdev
->dev
, "HW Init failed: %d\n", err
);
6230 ixgbe_probe_vf(adapter
, ii
);
6232 netdev
->features
= NETIF_F_SG
|
6234 NETIF_F_HW_VLAN_TX
|
6235 NETIF_F_HW_VLAN_RX
|
6236 NETIF_F_HW_VLAN_FILTER
;
6238 netdev
->features
|= NETIF_F_IPV6_CSUM
;
6239 netdev
->features
|= NETIF_F_TSO
;
6240 netdev
->features
|= NETIF_F_TSO6
;
6241 netdev
->features
|= NETIF_F_GRO
;
6243 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6244 netdev
->features
|= NETIF_F_SCTP_CSUM
;
6246 netdev
->vlan_features
|= NETIF_F_TSO
;
6247 netdev
->vlan_features
|= NETIF_F_TSO6
;
6248 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
6249 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
6250 netdev
->vlan_features
|= NETIF_F_SG
;
6252 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6253 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
6254 IXGBE_FLAG_DCB_ENABLED
);
6255 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
6256 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
6258 #ifdef CONFIG_IXGBE_DCB
6259 netdev
->dcbnl_ops
= &dcbnl_ops
;
6263 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
6264 if (hw
->mac
.ops
.get_device_caps
) {
6265 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
6266 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
6267 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
6270 #endif /* IXGBE_FCOE */
6272 netdev
->features
|= NETIF_F_HIGHDMA
;
6274 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
6275 netdev
->features
|= NETIF_F_LRO
;
6277 /* make sure the EEPROM is good */
6278 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
6279 dev_err(&pdev
->dev
, "The EEPROM Checksum Is Not Valid\n");
6284 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6285 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6287 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
6288 dev_err(&pdev
->dev
, "invalid MAC address\n");
6293 /* power down the optics */
6294 if (hw
->phy
.multispeed_fiber
)
6295 hw
->mac
.ops
.disable_tx_laser(hw
);
6297 init_timer(&adapter
->watchdog_timer
);
6298 adapter
->watchdog_timer
.function
= &ixgbe_watchdog
;
6299 adapter
->watchdog_timer
.data
= (unsigned long)adapter
;
6301 INIT_WORK(&adapter
->reset_task
, ixgbe_reset_task
);
6302 INIT_WORK(&adapter
->watchdog_task
, ixgbe_watchdog_task
);
6304 err
= ixgbe_init_interrupt_scheme(adapter
);
6308 switch (pdev
->device
) {
6309 case IXGBE_DEV_ID_82599_KX4
:
6310 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
6311 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
6317 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
6319 /* pick up the PCI bus settings for reporting later */
6320 hw
->mac
.ops
.get_bus_info(hw
);
6322 /* print bus type/speed/width info */
6323 dev_info(&pdev
->dev
, "(PCI Express:%s:%s) %pM\n",
6324 ((hw
->bus
.speed
== ixgbe_bus_speed_5000
) ? "5.0Gb/s":
6325 (hw
->bus
.speed
== ixgbe_bus_speed_2500
) ? "2.5Gb/s":"Unknown"),
6326 ((hw
->bus
.width
== ixgbe_bus_width_pcie_x8
) ? "Width x8" :
6327 (hw
->bus
.width
== ixgbe_bus_width_pcie_x4
) ? "Width x4" :
6328 (hw
->bus
.width
== ixgbe_bus_width_pcie_x1
) ? "Width x1" :
6331 ixgbe_read_pba_num_generic(hw
, &part_num
);
6332 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
6333 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6334 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
6335 (part_num
>> 8), (part_num
& 0xff));
6337 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6338 hw
->mac
.type
, hw
->phy
.type
,
6339 (part_num
>> 8), (part_num
& 0xff));
6341 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
6342 dev_warn(&pdev
->dev
, "PCI-Express bandwidth available for "
6343 "this card is not sufficient for optimal "
6345 dev_warn(&pdev
->dev
, "For optimal performance a x8 "
6346 "PCI-Express slot is required.\n");
6349 /* save off EEPROM version number */
6350 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
6352 /* reset the hardware with the new settings */
6353 err
= hw
->mac
.ops
.start_hw(hw
);
6355 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
6356 /* We are running on a pre-production device, log a warning */
6357 dev_warn(&pdev
->dev
, "This device is a pre-production "
6358 "adapter/LOM. Please be aware there may be issues "
6359 "associated with your hardware. If you are "
6360 "experiencing problems please contact your Intel or "
6361 "hardware representative who provided you with this "
6364 strcpy(netdev
->name
, "eth%d");
6365 err
= register_netdev(netdev
);
6369 /* carrier off reporting is important to ethtool even BEFORE open */
6370 netif_carrier_off(netdev
);
6372 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
6373 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
6374 INIT_WORK(&adapter
->fdir_reinit_task
, ixgbe_fdir_reinit_task
);
6376 #ifdef CONFIG_IXGBE_DCA
6377 if (dca_add_requester(&pdev
->dev
) == 0) {
6378 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
6379 ixgbe_setup_dca(adapter
);
6382 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
6383 DPRINTK(PROBE
, INFO
, "IOV is enabled with %d VFs\n",
6385 for (i
= 0; i
< adapter
->num_vfs
; i
++)
6386 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
6389 /* add san mac addr to netdev */
6390 ixgbe_add_sanmac_netdev(netdev
);
6392 dev_info(&pdev
->dev
, "Intel(R) 10 Gigabit Network Connection\n");
6397 ixgbe_release_hw_control(adapter
);
6398 ixgbe_clear_interrupt_scheme(adapter
);
6401 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6402 ixgbe_disable_sriov(adapter
);
6403 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6404 del_timer_sync(&adapter
->sfp_timer
);
6405 cancel_work_sync(&adapter
->sfp_task
);
6406 cancel_work_sync(&adapter
->multispeed_fiber_task
);
6407 cancel_work_sync(&adapter
->sfp_config_module_task
);
6408 iounmap(hw
->hw_addr
);
6410 free_netdev(netdev
);
6412 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6416 pci_disable_device(pdev
);
6421 * ixgbe_remove - Device Removal Routine
6422 * @pdev: PCI device information struct
6424 * ixgbe_remove is called by the PCI subsystem to alert the driver
6425 * that it should release a PCI device. The could be caused by a
6426 * Hot-Plug event, or because the driver is going to be removed from
6429 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
6431 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6432 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6434 set_bit(__IXGBE_DOWN
, &adapter
->state
);
6435 /* clear the module not found bit to make sure the worker won't
6438 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6439 del_timer_sync(&adapter
->watchdog_timer
);
6441 del_timer_sync(&adapter
->sfp_timer
);
6442 cancel_work_sync(&adapter
->watchdog_task
);
6443 cancel_work_sync(&adapter
->sfp_task
);
6444 cancel_work_sync(&adapter
->multispeed_fiber_task
);
6445 cancel_work_sync(&adapter
->sfp_config_module_task
);
6446 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
6447 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
6448 cancel_work_sync(&adapter
->fdir_reinit_task
);
6449 flush_scheduled_work();
6451 #ifdef CONFIG_IXGBE_DCA
6452 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
6453 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
6454 dca_remove_requester(&pdev
->dev
);
6455 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
6460 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
6461 ixgbe_cleanup_fcoe(adapter
);
6463 #endif /* IXGBE_FCOE */
6465 /* remove the added san mac */
6466 ixgbe_del_sanmac_netdev(netdev
);
6468 if (netdev
->reg_state
== NETREG_REGISTERED
)
6469 unregister_netdev(netdev
);
6471 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6472 ixgbe_disable_sriov(adapter
);
6474 ixgbe_clear_interrupt_scheme(adapter
);
6476 ixgbe_release_hw_control(adapter
);
6478 iounmap(adapter
->hw
.hw_addr
);
6479 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6482 DPRINTK(PROBE
, INFO
, "complete\n");
6484 free_netdev(netdev
);
6486 pci_disable_pcie_error_reporting(pdev
);
6488 pci_disable_device(pdev
);
6492 * ixgbe_io_error_detected - called when PCI error is detected
6493 * @pdev: Pointer to PCI device
6494 * @state: The current pci connection state
6496 * This function is called after a PCI bus error affecting
6497 * this device has been detected.
6499 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
6500 pci_channel_state_t state
)
6502 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6503 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6505 netif_device_detach(netdev
);
6507 if (state
== pci_channel_io_perm_failure
)
6508 return PCI_ERS_RESULT_DISCONNECT
;
6510 if (netif_running(netdev
))
6511 ixgbe_down(adapter
);
6512 pci_disable_device(pdev
);
6514 /* Request a slot reset. */
6515 return PCI_ERS_RESULT_NEED_RESET
;
6519 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6520 * @pdev: Pointer to PCI device
6522 * Restart the card from scratch, as if from a cold-boot.
6524 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
6526 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6527 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6528 pci_ers_result_t result
;
6531 if (pci_enable_device_mem(pdev
)) {
6533 "Cannot re-enable PCI device after reset.\n");
6534 result
= PCI_ERS_RESULT_DISCONNECT
;
6536 pci_set_master(pdev
);
6537 pci_restore_state(pdev
);
6538 pci_save_state(pdev
);
6540 pci_wake_from_d3(pdev
, false);
6542 ixgbe_reset(adapter
);
6543 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
6544 result
= PCI_ERS_RESULT_RECOVERED
;
6547 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
6550 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err
);
6551 /* non-fatal, continue */
6558 * ixgbe_io_resume - called when traffic can start flowing again.
6559 * @pdev: Pointer to PCI device
6561 * This callback is called when the error recovery driver tells us that
6562 * its OK to resume normal operation.
6564 static void ixgbe_io_resume(struct pci_dev
*pdev
)
6566 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6567 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6569 if (netif_running(netdev
)) {
6570 if (ixgbe_up(adapter
)) {
6571 DPRINTK(PROBE
, INFO
, "ixgbe_up failed after reset\n");
6576 netif_device_attach(netdev
);
6579 static struct pci_error_handlers ixgbe_err_handler
= {
6580 .error_detected
= ixgbe_io_error_detected
,
6581 .slot_reset
= ixgbe_io_slot_reset
,
6582 .resume
= ixgbe_io_resume
,
6585 static struct pci_driver ixgbe_driver
= {
6586 .name
= ixgbe_driver_name
,
6587 .id_table
= ixgbe_pci_tbl
,
6588 .probe
= ixgbe_probe
,
6589 .remove
= __devexit_p(ixgbe_remove
),
6591 .suspend
= ixgbe_suspend
,
6592 .resume
= ixgbe_resume
,
6594 .shutdown
= ixgbe_shutdown
,
6595 .err_handler
= &ixgbe_err_handler
6599 * ixgbe_init_module - Driver Registration Routine
6601 * ixgbe_init_module is the first routine called when the driver is
6602 * loaded. All it does is register with the PCI subsystem.
6604 static int __init
ixgbe_init_module(void)
6607 printk(KERN_INFO
"%s: %s - version %s\n", ixgbe_driver_name
,
6608 ixgbe_driver_string
, ixgbe_driver_version
);
6610 printk(KERN_INFO
"%s: %s\n", ixgbe_driver_name
, ixgbe_copyright
);
6612 #ifdef CONFIG_IXGBE_DCA
6613 dca_register_notify(&dca_notifier
);
6616 ret
= pci_register_driver(&ixgbe_driver
);
6620 module_init(ixgbe_init_module
);
6623 * ixgbe_exit_module - Driver Exit Cleanup Routine
6625 * ixgbe_exit_module is called just before the driver is removed
6628 static void __exit
ixgbe_exit_module(void)
6630 #ifdef CONFIG_IXGBE_DCA
6631 dca_unregister_notify(&dca_notifier
);
6633 pci_unregister_driver(&ixgbe_driver
);
6636 #ifdef CONFIG_IXGBE_DCA
6637 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
6642 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
6643 __ixgbe_notify_dca
);
6645 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
6648 #endif /* CONFIG_IXGBE_DCA */
6651 * ixgbe_get_hw_dev_name - return device name string
6652 * used by hardware layer to print debugging information
6654 char *ixgbe_get_hw_dev_name(struct ixgbe_hw
*hw
)
6656 struct ixgbe_adapter
*adapter
= hw
->back
;
6657 return adapter
->netdev
->name
;
6661 module_exit(ixgbe_exit_module
);