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ixgbe: remove unnecessary re-init of adapter on Rx-csum change
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_ethtool.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for ixgbe */
29
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/slab.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/vmalloc.h>
37 #include <linux/uaccess.h>
38
39 #include "ixgbe.h"
40
41
42 #define IXGBE_ALL_RAR_ENTRIES 16
43
44 enum {NETDEV_STATS, IXGBE_STATS};
45
46 struct ixgbe_stats {
47 char stat_string[ETH_GSTRING_LEN];
48 int type;
49 int sizeof_stat;
50 int stat_offset;
51 };
52
53 #define IXGBE_STAT(m) IXGBE_STATS, \
54 sizeof(((struct ixgbe_adapter *)0)->m), \
55 offsetof(struct ixgbe_adapter, m)
56 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
57 sizeof(((struct rtnl_link_stats64 *)0)->m), \
58 offsetof(struct rtnl_link_stats64, m)
59
60 static struct ixgbe_stats ixgbe_gstrings_stats[] = {
61 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
62 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
63 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
64 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
65 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
66 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
67 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
68 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
69 {"lsc_int", IXGBE_STAT(lsc_int)},
70 {"tx_busy", IXGBE_STAT(tx_busy)},
71 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
72 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
73 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
74 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
75 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
76 {"multicast", IXGBE_NETDEV_STAT(multicast)},
77 {"broadcast", IXGBE_STAT(stats.bprc)},
78 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
79 {"collisions", IXGBE_NETDEV_STAT(collisions)},
80 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
81 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
82 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
83 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
84 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
85 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
86 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
87 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
88 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
89 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
90 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
91 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
92 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
93 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
94 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
95 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
96 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
97 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
98 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
99 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
100 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
101 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
102 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
103 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
104 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
105 #ifdef IXGBE_FCOE
106 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
107 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
108 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
109 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
110 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
111 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
112 #endif /* IXGBE_FCOE */
113 };
114
115 #define IXGBE_QUEUE_STATS_LEN \
116 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
117 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
118 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
119 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
120 #define IXGBE_PB_STATS_LEN ( \
121 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
122 IXGBE_FLAG_DCB_ENABLED) ? \
123 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
124 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
125 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
126 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
127 / sizeof(u64) : 0)
128 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
129 IXGBE_PB_STATS_LEN + \
130 IXGBE_QUEUE_STATS_LEN)
131
132 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
133 "Register test (offline)", "Eeprom test (offline)",
134 "Interrupt test (offline)", "Loopback test (offline)",
135 "Link test (on/offline)"
136 };
137 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
138
139 static int ixgbe_get_settings(struct net_device *netdev,
140 struct ethtool_cmd *ecmd)
141 {
142 struct ixgbe_adapter *adapter = netdev_priv(netdev);
143 struct ixgbe_hw *hw = &adapter->hw;
144 u32 link_speed = 0;
145 bool link_up;
146
147 ecmd->supported = SUPPORTED_10000baseT_Full;
148 ecmd->autoneg = AUTONEG_ENABLE;
149 ecmd->transceiver = XCVR_EXTERNAL;
150 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
151 (hw->phy.multispeed_fiber)) {
152 ecmd->supported |= (SUPPORTED_1000baseT_Full |
153 SUPPORTED_Autoneg);
154
155 ecmd->advertising = ADVERTISED_Autoneg;
156 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
157 ecmd->advertising |= ADVERTISED_10000baseT_Full;
158 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
159 ecmd->advertising |= ADVERTISED_1000baseT_Full;
160 /*
161 * It's possible that phy.autoneg_advertised may not be
162 * set yet. If so display what the default would be -
163 * both 1G and 10G supported.
164 */
165 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
166 ADVERTISED_10000baseT_Full)))
167 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
168 ADVERTISED_1000baseT_Full);
169
170 if (hw->phy.media_type == ixgbe_media_type_copper) {
171 ecmd->supported |= SUPPORTED_TP;
172 ecmd->advertising |= ADVERTISED_TP;
173 ecmd->port = PORT_TP;
174 } else {
175 ecmd->supported |= SUPPORTED_FIBRE;
176 ecmd->advertising |= ADVERTISED_FIBRE;
177 ecmd->port = PORT_FIBRE;
178 }
179 } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
180 /* Set as FIBRE until SERDES defined in kernel */
181 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
182 ecmd->supported = (SUPPORTED_1000baseT_Full |
183 SUPPORTED_FIBRE);
184 ecmd->advertising = (ADVERTISED_1000baseT_Full |
185 ADVERTISED_FIBRE);
186 ecmd->port = PORT_FIBRE;
187 ecmd->autoneg = AUTONEG_DISABLE;
188 } else {
189 ecmd->supported |= (SUPPORTED_1000baseT_Full |
190 SUPPORTED_FIBRE);
191 ecmd->advertising = (ADVERTISED_10000baseT_Full |
192 ADVERTISED_1000baseT_Full |
193 ADVERTISED_FIBRE);
194 ecmd->port = PORT_FIBRE;
195 }
196 } else {
197 ecmd->supported |= SUPPORTED_FIBRE;
198 ecmd->advertising = (ADVERTISED_10000baseT_Full |
199 ADVERTISED_FIBRE);
200 ecmd->port = PORT_FIBRE;
201 ecmd->autoneg = AUTONEG_DISABLE;
202 }
203
204 /* Get PHY type */
205 switch (adapter->hw.phy.type) {
206 case ixgbe_phy_tn:
207 case ixgbe_phy_cu_unknown:
208 /* Copper 10G-BASET */
209 ecmd->port = PORT_TP;
210 break;
211 case ixgbe_phy_qt:
212 ecmd->port = PORT_FIBRE;
213 break;
214 case ixgbe_phy_nl:
215 case ixgbe_phy_sfp_passive_tyco:
216 case ixgbe_phy_sfp_passive_unknown:
217 case ixgbe_phy_sfp_ftl:
218 case ixgbe_phy_sfp_avago:
219 case ixgbe_phy_sfp_intel:
220 case ixgbe_phy_sfp_unknown:
221 switch (adapter->hw.phy.sfp_type) {
222 /* SFP+ devices, further checking needed */
223 case ixgbe_sfp_type_da_cu:
224 case ixgbe_sfp_type_da_cu_core0:
225 case ixgbe_sfp_type_da_cu_core1:
226 ecmd->port = PORT_DA;
227 break;
228 case ixgbe_sfp_type_sr:
229 case ixgbe_sfp_type_lr:
230 case ixgbe_sfp_type_srlr_core0:
231 case ixgbe_sfp_type_srlr_core1:
232 ecmd->port = PORT_FIBRE;
233 break;
234 case ixgbe_sfp_type_not_present:
235 ecmd->port = PORT_NONE;
236 break;
237 case ixgbe_sfp_type_1g_cu_core0:
238 case ixgbe_sfp_type_1g_cu_core1:
239 ecmd->port = PORT_TP;
240 ecmd->supported = SUPPORTED_TP;
241 ecmd->advertising = (ADVERTISED_1000baseT_Full |
242 ADVERTISED_TP);
243 break;
244 case ixgbe_sfp_type_unknown:
245 default:
246 ecmd->port = PORT_OTHER;
247 break;
248 }
249 break;
250 case ixgbe_phy_xaui:
251 ecmd->port = PORT_NONE;
252 break;
253 case ixgbe_phy_unknown:
254 case ixgbe_phy_generic:
255 case ixgbe_phy_sfp_unsupported:
256 default:
257 ecmd->port = PORT_OTHER;
258 break;
259 }
260
261 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
262 if (link_up) {
263 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
264 SPEED_10000 : SPEED_1000;
265 ecmd->duplex = DUPLEX_FULL;
266 } else {
267 ecmd->speed = -1;
268 ecmd->duplex = -1;
269 }
270
271 return 0;
272 }
273
274 static int ixgbe_set_settings(struct net_device *netdev,
275 struct ethtool_cmd *ecmd)
276 {
277 struct ixgbe_adapter *adapter = netdev_priv(netdev);
278 struct ixgbe_hw *hw = &adapter->hw;
279 u32 advertised, old;
280 s32 err = 0;
281
282 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
283 (hw->phy.multispeed_fiber)) {
284 /* 10000/copper and 1000/copper must autoneg
285 * this function does not support any duplex forcing, but can
286 * limit the advertising of the adapter to only 10000 or 1000 */
287 if (ecmd->autoneg == AUTONEG_DISABLE)
288 return -EINVAL;
289
290 old = hw->phy.autoneg_advertised;
291 advertised = 0;
292 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
293 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
294
295 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
296 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
297
298 if (old == advertised)
299 return err;
300 /* this sets the link speed and restarts auto-neg */
301 hw->mac.autotry_restart = true;
302 err = hw->mac.ops.setup_link(hw, advertised, true, true);
303 if (err) {
304 e_info(probe, "setup link failed with code %d\n", err);
305 hw->mac.ops.setup_link(hw, old, true, true);
306 }
307 } else {
308 /* in this case we currently only support 10Gb/FULL */
309 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
310 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
311 (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
312 return -EINVAL;
313 }
314
315 return err;
316 }
317
318 static void ixgbe_get_pauseparam(struct net_device *netdev,
319 struct ethtool_pauseparam *pause)
320 {
321 struct ixgbe_adapter *adapter = netdev_priv(netdev);
322 struct ixgbe_hw *hw = &adapter->hw;
323
324 /*
325 * Flow Control Autoneg isn't on if
326 * - we didn't ask for it OR
327 * - it failed, we know this by tx & rx being off
328 */
329 if (hw->fc.disable_fc_autoneg ||
330 (hw->fc.current_mode == ixgbe_fc_none))
331 pause->autoneg = 0;
332 else
333 pause->autoneg = 1;
334
335 #ifdef CONFIG_DCB
336 if (hw->fc.current_mode == ixgbe_fc_pfc) {
337 pause->rx_pause = 0;
338 pause->tx_pause = 0;
339 }
340
341 #endif
342 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
343 pause->rx_pause = 1;
344 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
345 pause->tx_pause = 1;
346 } else if (hw->fc.current_mode == ixgbe_fc_full) {
347 pause->rx_pause = 1;
348 pause->tx_pause = 1;
349 }
350 }
351
352 static int ixgbe_set_pauseparam(struct net_device *netdev,
353 struct ethtool_pauseparam *pause)
354 {
355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
356 struct ixgbe_hw *hw = &adapter->hw;
357 struct ixgbe_fc_info fc;
358
359 #ifdef CONFIG_DCB
360 if (adapter->dcb_cfg.pfc_mode_enable ||
361 ((hw->mac.type == ixgbe_mac_82598EB) &&
362 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
363 return -EINVAL;
364
365 #endif
366
367 fc = hw->fc;
368
369 if (pause->autoneg != AUTONEG_ENABLE)
370 fc.disable_fc_autoneg = true;
371 else
372 fc.disable_fc_autoneg = false;
373
374 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
375 fc.requested_mode = ixgbe_fc_full;
376 else if (pause->rx_pause && !pause->tx_pause)
377 fc.requested_mode = ixgbe_fc_rx_pause;
378 else if (!pause->rx_pause && pause->tx_pause)
379 fc.requested_mode = ixgbe_fc_tx_pause;
380 else if (!pause->rx_pause && !pause->tx_pause)
381 fc.requested_mode = ixgbe_fc_none;
382 else
383 return -EINVAL;
384
385 #ifdef CONFIG_DCB
386 adapter->last_lfc_mode = fc.requested_mode;
387 #endif
388
389 /* if the thing changed then we'll update and use new autoneg */
390 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
391 hw->fc = fc;
392 if (netif_running(netdev))
393 ixgbe_reinit_locked(adapter);
394 else
395 ixgbe_reset(adapter);
396 }
397
398 return 0;
399 }
400
401 static u32 ixgbe_get_rx_csum(struct net_device *netdev)
402 {
403 struct ixgbe_adapter *adapter = netdev_priv(netdev);
404 return adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED;
405 }
406
407 static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
408 {
409 struct ixgbe_adapter *adapter = netdev_priv(netdev);
410 if (data)
411 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
412 else
413 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
414
415 return 0;
416 }
417
418 static u32 ixgbe_get_tx_csum(struct net_device *netdev)
419 {
420 return (netdev->features & NETIF_F_IP_CSUM) != 0;
421 }
422
423 static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
424 {
425 struct ixgbe_adapter *adapter = netdev_priv(netdev);
426
427 if (data) {
428 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
429 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
430 netdev->features |= NETIF_F_SCTP_CSUM;
431 } else {
432 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
433 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
434 netdev->features &= ~NETIF_F_SCTP_CSUM;
435 }
436
437 return 0;
438 }
439
440 static int ixgbe_set_tso(struct net_device *netdev, u32 data)
441 {
442 if (data) {
443 netdev->features |= NETIF_F_TSO;
444 netdev->features |= NETIF_F_TSO6;
445 } else {
446 netdev->features &= ~NETIF_F_TSO;
447 netdev->features &= ~NETIF_F_TSO6;
448 }
449 return 0;
450 }
451
452 static u32 ixgbe_get_msglevel(struct net_device *netdev)
453 {
454 struct ixgbe_adapter *adapter = netdev_priv(netdev);
455 return adapter->msg_enable;
456 }
457
458 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
459 {
460 struct ixgbe_adapter *adapter = netdev_priv(netdev);
461 adapter->msg_enable = data;
462 }
463
464 static int ixgbe_get_regs_len(struct net_device *netdev)
465 {
466 #define IXGBE_REGS_LEN 1128
467 return IXGBE_REGS_LEN * sizeof(u32);
468 }
469
470 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
471
472 static void ixgbe_get_regs(struct net_device *netdev,
473 struct ethtool_regs *regs, void *p)
474 {
475 struct ixgbe_adapter *adapter = netdev_priv(netdev);
476 struct ixgbe_hw *hw = &adapter->hw;
477 u32 *regs_buff = p;
478 u8 i;
479
480 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
481
482 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
483
484 /* General Registers */
485 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
486 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
487 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
488 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
489 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
490 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
491 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
492 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
493
494 /* NVM Register */
495 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
496 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
497 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
498 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
499 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
500 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
501 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
502 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
503 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
504 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
505
506 /* Interrupt */
507 /* don't read EICR because it can clear interrupt causes, instead
508 * read EICS which is a shadow but doesn't clear EICR */
509 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
510 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
511 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
512 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
513 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
514 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
515 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
516 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
517 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
518 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
519 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
520 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
521
522 /* Flow Control */
523 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
524 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
525 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
526 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
527 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
528 for (i = 0; i < 8; i++)
529 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
530 for (i = 0; i < 8; i++)
531 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
532 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
533 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
534
535 /* Receive DMA */
536 for (i = 0; i < 64; i++)
537 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
538 for (i = 0; i < 64; i++)
539 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
540 for (i = 0; i < 64; i++)
541 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
542 for (i = 0; i < 64; i++)
543 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
544 for (i = 0; i < 64; i++)
545 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
546 for (i = 0; i < 64; i++)
547 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
548 for (i = 0; i < 16; i++)
549 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
550 for (i = 0; i < 16; i++)
551 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
552 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
553 for (i = 0; i < 8; i++)
554 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
555 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
556 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
557
558 /* Receive */
559 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
560 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
561 for (i = 0; i < 16; i++)
562 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
563 for (i = 0; i < 16; i++)
564 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
565 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
566 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
567 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
568 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
569 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
570 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
571 for (i = 0; i < 8; i++)
572 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
573 for (i = 0; i < 8; i++)
574 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
575 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
576
577 /* Transmit */
578 for (i = 0; i < 32; i++)
579 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
580 for (i = 0; i < 32; i++)
581 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
582 for (i = 0; i < 32; i++)
583 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
584 for (i = 0; i < 32; i++)
585 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
586 for (i = 0; i < 32; i++)
587 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
588 for (i = 0; i < 32; i++)
589 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
590 for (i = 0; i < 32; i++)
591 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
592 for (i = 0; i < 32; i++)
593 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
594 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
595 for (i = 0; i < 16; i++)
596 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
597 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
598 for (i = 0; i < 8; i++)
599 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
600 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
601
602 /* Wake Up */
603 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
604 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
605 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
606 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
607 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
608 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
609 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
610 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
611 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
612
613 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
614 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
615 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
616 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
617 for (i = 0; i < 8; i++)
618 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
619 for (i = 0; i < 8; i++)
620 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
621 for (i = 0; i < 8; i++)
622 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
623 for (i = 0; i < 8; i++)
624 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
625 for (i = 0; i < 8; i++)
626 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
627 for (i = 0; i < 8; i++)
628 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
629
630 /* Statistics */
631 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
632 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
633 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
634 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
635 for (i = 0; i < 8; i++)
636 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
637 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
638 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
639 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
640 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
641 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
642 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
643 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
644 for (i = 0; i < 8; i++)
645 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
646 for (i = 0; i < 8; i++)
647 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
648 for (i = 0; i < 8; i++)
649 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
650 for (i = 0; i < 8; i++)
651 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
652 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
653 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
654 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
655 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
656 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
657 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
658 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
659 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
660 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
661 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
662 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
663 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
664 for (i = 0; i < 8; i++)
665 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
666 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
667 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
668 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
669 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
670 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
671 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
672 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
673 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
674 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
675 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
676 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
677 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
678 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
679 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
680 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
681 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
682 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
683 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
684 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
685 for (i = 0; i < 16; i++)
686 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
687 for (i = 0; i < 16; i++)
688 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
689 for (i = 0; i < 16; i++)
690 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
691 for (i = 0; i < 16; i++)
692 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
693
694 /* MAC */
695 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
696 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
697 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
698 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
699 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
700 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
701 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
702 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
703 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
704 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
705 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
706 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
707 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
708 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
709 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
710 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
711 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
712 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
713 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
714 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
715 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
716 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
717 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
718 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
719 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
720 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
721 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
722 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
723 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
724 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
725 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
726 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
727 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
728
729 /* Diagnostic */
730 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
731 for (i = 0; i < 8; i++)
732 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
733 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
734 for (i = 0; i < 4; i++)
735 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
736 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
737 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
738 for (i = 0; i < 8; i++)
739 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
740 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
741 for (i = 0; i < 4; i++)
742 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
743 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
744 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
745 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
746 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
747 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
748 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
749 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
750 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
751 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
752 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
753 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
754 for (i = 0; i < 8; i++)
755 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
756 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
757 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
758 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
759 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
760 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
761 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
762 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
763 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
764 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
765 }
766
767 static int ixgbe_get_eeprom_len(struct net_device *netdev)
768 {
769 struct ixgbe_adapter *adapter = netdev_priv(netdev);
770 return adapter->hw.eeprom.word_size * 2;
771 }
772
773 static int ixgbe_get_eeprom(struct net_device *netdev,
774 struct ethtool_eeprom *eeprom, u8 *bytes)
775 {
776 struct ixgbe_adapter *adapter = netdev_priv(netdev);
777 struct ixgbe_hw *hw = &adapter->hw;
778 u16 *eeprom_buff;
779 int first_word, last_word, eeprom_len;
780 int ret_val = 0;
781 u16 i;
782
783 if (eeprom->len == 0)
784 return -EINVAL;
785
786 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
787
788 first_word = eeprom->offset >> 1;
789 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
790 eeprom_len = last_word - first_word + 1;
791
792 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
793 if (!eeprom_buff)
794 return -ENOMEM;
795
796 for (i = 0; i < eeprom_len; i++) {
797 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
798 &eeprom_buff[i])))
799 break;
800 }
801
802 /* Device's eeprom is always little-endian, word addressable */
803 for (i = 0; i < eeprom_len; i++)
804 le16_to_cpus(&eeprom_buff[i]);
805
806 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
807 kfree(eeprom_buff);
808
809 return ret_val;
810 }
811
812 static void ixgbe_get_drvinfo(struct net_device *netdev,
813 struct ethtool_drvinfo *drvinfo)
814 {
815 struct ixgbe_adapter *adapter = netdev_priv(netdev);
816 char firmware_version[32];
817
818 strncpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
819 strncpy(drvinfo->version, ixgbe_driver_version,
820 sizeof(drvinfo->version));
821
822 snprintf(firmware_version, sizeof(firmware_version), "%d.%d-%d",
823 (adapter->eeprom_version & 0xF000) >> 12,
824 (adapter->eeprom_version & 0x0FF0) >> 4,
825 adapter->eeprom_version & 0x000F);
826
827 strncpy(drvinfo->fw_version, firmware_version,
828 sizeof(drvinfo->fw_version));
829 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
830 sizeof(drvinfo->bus_info));
831 drvinfo->n_stats = IXGBE_STATS_LEN;
832 drvinfo->testinfo_len = IXGBE_TEST_LEN;
833 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
834 }
835
836 static void ixgbe_get_ringparam(struct net_device *netdev,
837 struct ethtool_ringparam *ring)
838 {
839 struct ixgbe_adapter *adapter = netdev_priv(netdev);
840 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
841 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
842
843 ring->rx_max_pending = IXGBE_MAX_RXD;
844 ring->tx_max_pending = IXGBE_MAX_TXD;
845 ring->rx_mini_max_pending = 0;
846 ring->rx_jumbo_max_pending = 0;
847 ring->rx_pending = rx_ring->count;
848 ring->tx_pending = tx_ring->count;
849 ring->rx_mini_pending = 0;
850 ring->rx_jumbo_pending = 0;
851 }
852
853 static int ixgbe_set_ringparam(struct net_device *netdev,
854 struct ethtool_ringparam *ring)
855 {
856 struct ixgbe_adapter *adapter = netdev_priv(netdev);
857 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
858 int i, err = 0;
859 u32 new_rx_count, new_tx_count;
860 bool need_update = false;
861
862 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
863 return -EINVAL;
864
865 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
866 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
867 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
868
869 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
870 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
871 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
872
873 if ((new_tx_count == adapter->tx_ring[0]->count) &&
874 (new_rx_count == adapter->rx_ring[0]->count)) {
875 /* nothing to do */
876 return 0;
877 }
878
879 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
880 msleep(1);
881
882 if (!netif_running(adapter->netdev)) {
883 for (i = 0; i < adapter->num_tx_queues; i++)
884 adapter->tx_ring[i]->count = new_tx_count;
885 for (i = 0; i < adapter->num_rx_queues; i++)
886 adapter->rx_ring[i]->count = new_rx_count;
887 adapter->tx_ring_count = new_tx_count;
888 adapter->rx_ring_count = new_rx_count;
889 goto clear_reset;
890 }
891
892 temp_tx_ring = vmalloc(adapter->num_tx_queues * sizeof(struct ixgbe_ring));
893 if (!temp_tx_ring) {
894 err = -ENOMEM;
895 goto clear_reset;
896 }
897
898 if (new_tx_count != adapter->tx_ring_count) {
899 for (i = 0; i < adapter->num_tx_queues; i++) {
900 memcpy(&temp_tx_ring[i], adapter->tx_ring[i],
901 sizeof(struct ixgbe_ring));
902 temp_tx_ring[i].count = new_tx_count;
903 err = ixgbe_setup_tx_resources(adapter,
904 &temp_tx_ring[i]);
905 if (err) {
906 while (i) {
907 i--;
908 ixgbe_free_tx_resources(adapter,
909 &temp_tx_ring[i]);
910 }
911 goto clear_reset;
912 }
913 }
914 need_update = true;
915 }
916
917 temp_rx_ring = vmalloc(adapter->num_rx_queues * sizeof(struct ixgbe_ring));
918 if (!temp_rx_ring) {
919 err = -ENOMEM;
920 goto err_setup;
921 }
922
923 if (new_rx_count != adapter->rx_ring_count) {
924 for (i = 0; i < adapter->num_rx_queues; i++) {
925 memcpy(&temp_rx_ring[i], adapter->rx_ring[i],
926 sizeof(struct ixgbe_ring));
927 temp_rx_ring[i].count = new_rx_count;
928 err = ixgbe_setup_rx_resources(adapter,
929 &temp_rx_ring[i]);
930 if (err) {
931 while (i) {
932 i--;
933 ixgbe_free_rx_resources(adapter,
934 &temp_rx_ring[i]);
935 }
936 goto err_setup;
937 }
938 }
939 need_update = true;
940 }
941
942 /* if rings need to be updated, here's the place to do it in one shot */
943 if (need_update) {
944 ixgbe_down(adapter);
945
946 /* tx */
947 if (new_tx_count != adapter->tx_ring_count) {
948 for (i = 0; i < adapter->num_tx_queues; i++) {
949 ixgbe_free_tx_resources(adapter,
950 adapter->tx_ring[i]);
951 memcpy(adapter->tx_ring[i], &temp_tx_ring[i],
952 sizeof(struct ixgbe_ring));
953 }
954 adapter->tx_ring_count = new_tx_count;
955 }
956
957 /* rx */
958 if (new_rx_count != adapter->rx_ring_count) {
959 for (i = 0; i < adapter->num_rx_queues; i++) {
960 ixgbe_free_rx_resources(adapter,
961 adapter->rx_ring[i]);
962 memcpy(adapter->rx_ring[i], &temp_rx_ring[i],
963 sizeof(struct ixgbe_ring));
964 }
965 adapter->rx_ring_count = new_rx_count;
966 }
967 ixgbe_up(adapter);
968 }
969
970 vfree(temp_rx_ring);
971 err_setup:
972 vfree(temp_tx_ring);
973 clear_reset:
974 clear_bit(__IXGBE_RESETTING, &adapter->state);
975 return err;
976 }
977
978 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
979 {
980 switch (sset) {
981 case ETH_SS_TEST:
982 return IXGBE_TEST_LEN;
983 case ETH_SS_STATS:
984 return IXGBE_STATS_LEN;
985 case ETH_SS_NTUPLE_FILTERS:
986 return ETHTOOL_MAX_NTUPLE_LIST_ENTRY *
987 ETHTOOL_MAX_NTUPLE_STRING_PER_ENTRY;
988 default:
989 return -EOPNOTSUPP;
990 }
991 }
992
993 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
994 struct ethtool_stats *stats, u64 *data)
995 {
996 struct ixgbe_adapter *adapter = netdev_priv(netdev);
997 struct rtnl_link_stats64 temp;
998 const struct rtnl_link_stats64 *net_stats;
999 unsigned int start;
1000 struct ixgbe_ring *ring;
1001 int i, j;
1002 char *p = NULL;
1003
1004 ixgbe_update_stats(adapter);
1005 net_stats = dev_get_stats(netdev, &temp);
1006 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1007 switch (ixgbe_gstrings_stats[i].type) {
1008 case NETDEV_STATS:
1009 p = (char *) net_stats +
1010 ixgbe_gstrings_stats[i].stat_offset;
1011 break;
1012 case IXGBE_STATS:
1013 p = (char *) adapter +
1014 ixgbe_gstrings_stats[i].stat_offset;
1015 break;
1016 }
1017
1018 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1019 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1020 }
1021 for (j = 0; j < adapter->num_tx_queues; j++) {
1022 ring = adapter->tx_ring[j];
1023 do {
1024 start = u64_stats_fetch_begin_bh(&ring->syncp);
1025 data[i] = ring->stats.packets;
1026 data[i+1] = ring->stats.bytes;
1027 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1028 i += 2;
1029 }
1030 for (j = 0; j < adapter->num_rx_queues; j++) {
1031 ring = adapter->rx_ring[j];
1032 do {
1033 start = u64_stats_fetch_begin_bh(&ring->syncp);
1034 data[i] = ring->stats.packets;
1035 data[i+1] = ring->stats.bytes;
1036 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1037 i += 2;
1038 }
1039 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1040 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
1041 data[i++] = adapter->stats.pxontxc[j];
1042 data[i++] = adapter->stats.pxofftxc[j];
1043 }
1044 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
1045 data[i++] = adapter->stats.pxonrxc[j];
1046 data[i++] = adapter->stats.pxoffrxc[j];
1047 }
1048 }
1049 }
1050
1051 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1052 u8 *data)
1053 {
1054 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1055 char *p = (char *)data;
1056 int i;
1057
1058 switch (stringset) {
1059 case ETH_SS_TEST:
1060 memcpy(data, *ixgbe_gstrings_test,
1061 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
1062 break;
1063 case ETH_SS_STATS:
1064 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1065 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1066 ETH_GSTRING_LEN);
1067 p += ETH_GSTRING_LEN;
1068 }
1069 for (i = 0; i < adapter->num_tx_queues; i++) {
1070 sprintf(p, "tx_queue_%u_packets", i);
1071 p += ETH_GSTRING_LEN;
1072 sprintf(p, "tx_queue_%u_bytes", i);
1073 p += ETH_GSTRING_LEN;
1074 }
1075 for (i = 0; i < adapter->num_rx_queues; i++) {
1076 sprintf(p, "rx_queue_%u_packets", i);
1077 p += ETH_GSTRING_LEN;
1078 sprintf(p, "rx_queue_%u_bytes", i);
1079 p += ETH_GSTRING_LEN;
1080 }
1081 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1082 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1083 sprintf(p, "tx_pb_%u_pxon", i);
1084 p += ETH_GSTRING_LEN;
1085 sprintf(p, "tx_pb_%u_pxoff", i);
1086 p += ETH_GSTRING_LEN;
1087 }
1088 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
1089 sprintf(p, "rx_pb_%u_pxon", i);
1090 p += ETH_GSTRING_LEN;
1091 sprintf(p, "rx_pb_%u_pxoff", i);
1092 p += ETH_GSTRING_LEN;
1093 }
1094 }
1095 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1096 break;
1097 }
1098 }
1099
1100 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1101 {
1102 struct ixgbe_hw *hw = &adapter->hw;
1103 bool link_up;
1104 u32 link_speed = 0;
1105 *data = 0;
1106
1107 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1108 if (link_up)
1109 return *data;
1110 else
1111 *data = 1;
1112 return *data;
1113 }
1114
1115 /* ethtool register test data */
1116 struct ixgbe_reg_test {
1117 u16 reg;
1118 u8 array_len;
1119 u8 test_type;
1120 u32 mask;
1121 u32 write;
1122 };
1123
1124 /* In the hardware, registers are laid out either singly, in arrays
1125 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1126 * most tests take place on arrays or single registers (handled
1127 * as a single-element array) and special-case the tables.
1128 * Table tests are always pattern tests.
1129 *
1130 * We also make provision for some required setup steps by specifying
1131 * registers to be written without any read-back testing.
1132 */
1133
1134 #define PATTERN_TEST 1
1135 #define SET_READ_TEST 2
1136 #define WRITE_NO_TEST 3
1137 #define TABLE32_TEST 4
1138 #define TABLE64_TEST_LO 5
1139 #define TABLE64_TEST_HI 6
1140
1141 /* default 82599 register test */
1142 static struct ixgbe_reg_test reg_test_82599[] = {
1143 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1144 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1145 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1146 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1147 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1148 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1149 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1150 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1151 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1152 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1153 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1154 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1155 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1156 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1157 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1158 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1159 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1160 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1161 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1162 { 0, 0, 0, 0 }
1163 };
1164
1165 /* default 82598 register test */
1166 static struct ixgbe_reg_test reg_test_82598[] = {
1167 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1168 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1169 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1170 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1171 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1172 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1173 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1174 /* Enable all four RX queues before testing. */
1175 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1176 /* RDH is read-only for 82598, only test RDT. */
1177 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1178 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1179 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1180 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1181 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1182 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1183 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1184 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1185 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1186 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1187 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1188 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1189 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1190 { 0, 0, 0, 0 }
1191 };
1192
1193 #define REG_PATTERN_TEST(R, M, W) \
1194 { \
1195 u32 pat, val, before; \
1196 const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1197 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \
1198 before = readl(adapter->hw.hw_addr + R); \
1199 writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \
1200 val = readl(adapter->hw.hw_addr + R); \
1201 if (val != (_test[pat] & W & M)) { \
1202 e_err(drv, "pattern test reg %04X failed: got " \
1203 "0x%08X expected 0x%08X\n", \
1204 R, val, (_test[pat] & W & M)); \
1205 *data = R; \
1206 writel(before, adapter->hw.hw_addr + R); \
1207 return 1; \
1208 } \
1209 writel(before, adapter->hw.hw_addr + R); \
1210 } \
1211 }
1212
1213 #define REG_SET_AND_CHECK(R, M, W) \
1214 { \
1215 u32 val, before; \
1216 before = readl(adapter->hw.hw_addr + R); \
1217 writel((W & M), (adapter->hw.hw_addr + R)); \
1218 val = readl(adapter->hw.hw_addr + R); \
1219 if ((W & M) != (val & M)) { \
1220 e_err(drv, "set/check reg %04X test failed: got 0x%08X " \
1221 "expected 0x%08X\n", R, (val & M), (W & M)); \
1222 *data = R; \
1223 writel(before, (adapter->hw.hw_addr + R)); \
1224 return 1; \
1225 } \
1226 writel(before, (adapter->hw.hw_addr + R)); \
1227 }
1228
1229 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1230 {
1231 struct ixgbe_reg_test *test;
1232 u32 value, before, after;
1233 u32 i, toggle;
1234
1235 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1236 toggle = 0x7FFFF30F;
1237 test = reg_test_82599;
1238 } else {
1239 toggle = 0x7FFFF3FF;
1240 test = reg_test_82598;
1241 }
1242
1243 /*
1244 * Because the status register is such a special case,
1245 * we handle it separately from the rest of the register
1246 * tests. Some bits are read-only, some toggle, and some
1247 * are writeable on newer MACs.
1248 */
1249 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1250 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1251 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1252 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1253 if (value != after) {
1254 e_err(drv, "failed STATUS register test got: 0x%08X "
1255 "expected: 0x%08X\n", after, value);
1256 *data = 1;
1257 return 1;
1258 }
1259 /* restore previous status */
1260 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1261
1262 /*
1263 * Perform the remainder of the register test, looping through
1264 * the test table until we either fail or reach the null entry.
1265 */
1266 while (test->reg) {
1267 for (i = 0; i < test->array_len; i++) {
1268 switch (test->test_type) {
1269 case PATTERN_TEST:
1270 REG_PATTERN_TEST(test->reg + (i * 0x40),
1271 test->mask,
1272 test->write);
1273 break;
1274 case SET_READ_TEST:
1275 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1276 test->mask,
1277 test->write);
1278 break;
1279 case WRITE_NO_TEST:
1280 writel(test->write,
1281 (adapter->hw.hw_addr + test->reg)
1282 + (i * 0x40));
1283 break;
1284 case TABLE32_TEST:
1285 REG_PATTERN_TEST(test->reg + (i * 4),
1286 test->mask,
1287 test->write);
1288 break;
1289 case TABLE64_TEST_LO:
1290 REG_PATTERN_TEST(test->reg + (i * 8),
1291 test->mask,
1292 test->write);
1293 break;
1294 case TABLE64_TEST_HI:
1295 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1296 test->mask,
1297 test->write);
1298 break;
1299 }
1300 }
1301 test++;
1302 }
1303
1304 *data = 0;
1305 return 0;
1306 }
1307
1308 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1309 {
1310 struct ixgbe_hw *hw = &adapter->hw;
1311 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1312 *data = 1;
1313 else
1314 *data = 0;
1315 return *data;
1316 }
1317
1318 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1319 {
1320 struct net_device *netdev = (struct net_device *) data;
1321 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1322
1323 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1324
1325 return IRQ_HANDLED;
1326 }
1327
1328 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1329 {
1330 struct net_device *netdev = adapter->netdev;
1331 u32 mask, i = 0, shared_int = true;
1332 u32 irq = adapter->pdev->irq;
1333
1334 *data = 0;
1335
1336 /* Hook up test interrupt handler just for this test */
1337 if (adapter->msix_entries) {
1338 /* NOTE: we don't test MSI-X interrupts here, yet */
1339 return 0;
1340 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1341 shared_int = false;
1342 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1343 netdev)) {
1344 *data = 1;
1345 return -1;
1346 }
1347 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1348 netdev->name, netdev)) {
1349 shared_int = false;
1350 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1351 netdev->name, netdev)) {
1352 *data = 1;
1353 return -1;
1354 }
1355 e_info(hw, "testing %s interrupt\n", shared_int ?
1356 "shared" : "unshared");
1357
1358 /* Disable all the interrupts */
1359 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1360 msleep(10);
1361
1362 /* Test each interrupt */
1363 for (; i < 10; i++) {
1364 /* Interrupt to test */
1365 mask = 1 << i;
1366
1367 if (!shared_int) {
1368 /*
1369 * Disable the interrupts to be reported in
1370 * the cause register and then force the same
1371 * interrupt and see if one gets posted. If
1372 * an interrupt was posted to the bus, the
1373 * test failed.
1374 */
1375 adapter->test_icr = 0;
1376 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1377 ~mask & 0x00007FFF);
1378 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1379 ~mask & 0x00007FFF);
1380 msleep(10);
1381
1382 if (adapter->test_icr & mask) {
1383 *data = 3;
1384 break;
1385 }
1386 }
1387
1388 /*
1389 * Enable the interrupt to be reported in the cause
1390 * register and then force the same interrupt and see
1391 * if one gets posted. If an interrupt was not posted
1392 * to the bus, the test failed.
1393 */
1394 adapter->test_icr = 0;
1395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1396 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1397 msleep(10);
1398
1399 if (!(adapter->test_icr &mask)) {
1400 *data = 4;
1401 break;
1402 }
1403
1404 if (!shared_int) {
1405 /*
1406 * Disable the other interrupts to be reported in
1407 * the cause register and then force the other
1408 * interrupts and see if any get posted. If
1409 * an interrupt was posted to the bus, the
1410 * test failed.
1411 */
1412 adapter->test_icr = 0;
1413 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1414 ~mask & 0x00007FFF);
1415 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1416 ~mask & 0x00007FFF);
1417 msleep(10);
1418
1419 if (adapter->test_icr) {
1420 *data = 5;
1421 break;
1422 }
1423 }
1424 }
1425
1426 /* Disable all the interrupts */
1427 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1428 msleep(10);
1429
1430 /* Unhook test interrupt handler */
1431 free_irq(irq, netdev);
1432
1433 return *data;
1434 }
1435
1436 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1437 {
1438 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1439 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1440 struct ixgbe_hw *hw = &adapter->hw;
1441 u32 reg_ctl;
1442
1443 /* shut down the DMA engines now so they can be reinitialized later */
1444
1445 /* first Rx */
1446 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1447 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1448 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1449 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rx_ring->reg_idx));
1450 reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1451 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rx_ring->reg_idx), reg_ctl);
1452
1453 /* now Tx */
1454 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
1455 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1456 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1457
1458 if (hw->mac.type == ixgbe_mac_82599EB) {
1459 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1460 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1461 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1462 }
1463
1464 ixgbe_reset(adapter);
1465
1466 ixgbe_free_tx_resources(adapter, &adapter->test_tx_ring);
1467 ixgbe_free_rx_resources(adapter, &adapter->test_rx_ring);
1468 }
1469
1470 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1471 {
1472 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1473 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1474 u32 rctl, reg_data;
1475 int ret_val;
1476 int err;
1477
1478 /* Setup Tx descriptor ring and Tx buffers */
1479 tx_ring->count = IXGBE_DEFAULT_TXD;
1480 tx_ring->queue_index = 0;
1481 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1482 tx_ring->numa_node = adapter->node;
1483
1484 err = ixgbe_setup_tx_resources(adapter, tx_ring);
1485 if (err)
1486 return 1;
1487
1488 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1489 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1490 reg_data |= IXGBE_DMATXCTL_TE;
1491 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1492 }
1493
1494 ixgbe_configure_tx_ring(adapter, tx_ring);
1495
1496 /* Setup Rx Descriptor ring and Rx buffers */
1497 rx_ring->count = IXGBE_DEFAULT_RXD;
1498 rx_ring->queue_index = 0;
1499 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1500 rx_ring->rx_buf_len = IXGBE_RXBUFFER_2048;
1501 rx_ring->numa_node = adapter->node;
1502
1503 err = ixgbe_setup_rx_resources(adapter, rx_ring);
1504 if (err) {
1505 ret_val = 4;
1506 goto err_nomem;
1507 }
1508
1509 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1510 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1511
1512 ixgbe_configure_rx_ring(adapter, rx_ring);
1513
1514 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1516
1517 return 0;
1518
1519 err_nomem:
1520 ixgbe_free_desc_rings(adapter);
1521 return ret_val;
1522 }
1523
1524 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1525 {
1526 struct ixgbe_hw *hw = &adapter->hw;
1527 u32 reg_data;
1528
1529 /* right now we only support MAC loopback in the driver */
1530 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1531 /* Setup MAC loopback */
1532 reg_data |= IXGBE_HLREG0_LPBK;
1533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1534
1535 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1536 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1537 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1538
1539 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1540 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1541 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1542 IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1543 IXGBE_WRITE_FLUSH(&adapter->hw);
1544 msleep(10);
1545
1546 /* Disable Atlas Tx lanes; re-enabled in reset path */
1547 if (hw->mac.type == ixgbe_mac_82598EB) {
1548 u8 atlas;
1549
1550 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1551 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1552 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1553
1554 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1555 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1556 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1557
1558 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1559 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1560 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1561
1562 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1563 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1564 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1565 }
1566
1567 return 0;
1568 }
1569
1570 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1571 {
1572 u32 reg_data;
1573
1574 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1575 reg_data &= ~IXGBE_HLREG0_LPBK;
1576 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1577 }
1578
1579 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1580 unsigned int frame_size)
1581 {
1582 memset(skb->data, 0xFF, frame_size);
1583 frame_size &= ~1;
1584 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1585 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1586 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1587 }
1588
1589 static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1590 unsigned int frame_size)
1591 {
1592 frame_size &= ~1;
1593 if (*(skb->data + 3) == 0xFF) {
1594 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1595 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1596 return 0;
1597 }
1598 }
1599 return 13;
1600 }
1601
1602 static u16 ixgbe_clean_test_rings(struct ixgbe_adapter *adapter,
1603 struct ixgbe_ring *rx_ring,
1604 struct ixgbe_ring *tx_ring,
1605 unsigned int size)
1606 {
1607 union ixgbe_adv_rx_desc *rx_desc;
1608 struct ixgbe_rx_buffer *rx_buffer_info;
1609 struct ixgbe_tx_buffer *tx_buffer_info;
1610 const int bufsz = rx_ring->rx_buf_len;
1611 u32 staterr;
1612 u16 rx_ntc, tx_ntc, count = 0;
1613
1614 /* initialize next to clean and descriptor values */
1615 rx_ntc = rx_ring->next_to_clean;
1616 tx_ntc = tx_ring->next_to_clean;
1617 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1618 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1619
1620 while (staterr & IXGBE_RXD_STAT_DD) {
1621 /* check Rx buffer */
1622 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1623
1624 /* unmap Rx buffer, will be remapped by alloc_rx_buffers */
1625 dma_unmap_single(&adapter->pdev->dev,
1626 rx_buffer_info->dma,
1627 bufsz,
1628 DMA_FROM_DEVICE);
1629 rx_buffer_info->dma = 0;
1630
1631 /* verify contents of skb */
1632 if (!ixgbe_check_lbtest_frame(rx_buffer_info->skb, size))
1633 count++;
1634
1635 /* unmap buffer on Tx side */
1636 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1637 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
1638
1639 /* increment Rx/Tx next to clean counters */
1640 rx_ntc++;
1641 if (rx_ntc == rx_ring->count)
1642 rx_ntc = 0;
1643 tx_ntc++;
1644 if (tx_ntc == tx_ring->count)
1645 tx_ntc = 0;
1646
1647 /* fetch next descriptor */
1648 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1649 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1650 }
1651
1652 /* re-map buffers to ring, store next to clean values */
1653 ixgbe_alloc_rx_buffers(adapter, rx_ring, count);
1654 rx_ring->next_to_clean = rx_ntc;
1655 tx_ring->next_to_clean = tx_ntc;
1656
1657 return count;
1658 }
1659
1660 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1661 {
1662 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1663 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1664 int i, j, lc, good_cnt, ret_val = 0;
1665 unsigned int size = 1024;
1666 netdev_tx_t tx_ret_val;
1667 struct sk_buff *skb;
1668
1669 /* allocate test skb */
1670 skb = alloc_skb(size, GFP_KERNEL);
1671 if (!skb)
1672 return 11;
1673
1674 /* place data into test skb */
1675 ixgbe_create_lbtest_frame(skb, size);
1676 skb_put(skb, size);
1677
1678 /*
1679 * Calculate the loop count based on the largest descriptor ring
1680 * The idea is to wrap the largest ring a number of times using 64
1681 * send/receive pairs during each loop
1682 */
1683
1684 if (rx_ring->count <= tx_ring->count)
1685 lc = ((tx_ring->count / 64) * 2) + 1;
1686 else
1687 lc = ((rx_ring->count / 64) * 2) + 1;
1688
1689 for (j = 0; j <= lc; j++) {
1690 /* reset count of good packets */
1691 good_cnt = 0;
1692
1693 /* place 64 packets on the transmit queue*/
1694 for (i = 0; i < 64; i++) {
1695 skb_get(skb);
1696 tx_ret_val = ixgbe_xmit_frame_ring(skb,
1697 adapter->netdev,
1698 adapter,
1699 tx_ring);
1700 if (tx_ret_val == NETDEV_TX_OK)
1701 good_cnt++;
1702 }
1703
1704 if (good_cnt != 64) {
1705 ret_val = 12;
1706 break;
1707 }
1708
1709 /* allow 200 milliseconds for packets to go from Tx to Rx */
1710 msleep(200);
1711
1712 good_cnt = ixgbe_clean_test_rings(adapter, rx_ring,
1713 tx_ring, size);
1714 if (good_cnt != 64) {
1715 ret_val = 13;
1716 break;
1717 }
1718 }
1719
1720 /* free the original skb */
1721 kfree_skb(skb);
1722
1723 return ret_val;
1724 }
1725
1726 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1727 {
1728 *data = ixgbe_setup_desc_rings(adapter);
1729 if (*data)
1730 goto out;
1731 *data = ixgbe_setup_loopback_test(adapter);
1732 if (*data)
1733 goto err_loopback;
1734 *data = ixgbe_run_loopback_test(adapter);
1735 ixgbe_loopback_cleanup(adapter);
1736
1737 err_loopback:
1738 ixgbe_free_desc_rings(adapter);
1739 out:
1740 return *data;
1741 }
1742
1743 static void ixgbe_diag_test(struct net_device *netdev,
1744 struct ethtool_test *eth_test, u64 *data)
1745 {
1746 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1747 bool if_running = netif_running(netdev);
1748
1749 set_bit(__IXGBE_TESTING, &adapter->state);
1750 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1751 /* Offline tests */
1752
1753 e_info(hw, "offline testing starting\n");
1754
1755 /* Link test performed before hardware reset so autoneg doesn't
1756 * interfere with test result */
1757 if (ixgbe_link_test(adapter, &data[4]))
1758 eth_test->flags |= ETH_TEST_FL_FAILED;
1759
1760 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1761 int i;
1762 for (i = 0; i < adapter->num_vfs; i++) {
1763 if (adapter->vfinfo[i].clear_to_send) {
1764 netdev_warn(netdev, "%s",
1765 "offline diagnostic is not "
1766 "supported when VFs are "
1767 "present\n");
1768 data[0] = 1;
1769 data[1] = 1;
1770 data[2] = 1;
1771 data[3] = 1;
1772 eth_test->flags |= ETH_TEST_FL_FAILED;
1773 clear_bit(__IXGBE_TESTING,
1774 &adapter->state);
1775 goto skip_ol_tests;
1776 }
1777 }
1778 }
1779
1780 if (if_running)
1781 /* indicate we're in test mode */
1782 dev_close(netdev);
1783 else
1784 ixgbe_reset(adapter);
1785
1786 e_info(hw, "register testing starting\n");
1787 if (ixgbe_reg_test(adapter, &data[0]))
1788 eth_test->flags |= ETH_TEST_FL_FAILED;
1789
1790 ixgbe_reset(adapter);
1791 e_info(hw, "eeprom testing starting\n");
1792 if (ixgbe_eeprom_test(adapter, &data[1]))
1793 eth_test->flags |= ETH_TEST_FL_FAILED;
1794
1795 ixgbe_reset(adapter);
1796 e_info(hw, "interrupt testing starting\n");
1797 if (ixgbe_intr_test(adapter, &data[2]))
1798 eth_test->flags |= ETH_TEST_FL_FAILED;
1799
1800 /* If SRIOV or VMDq is enabled then skip MAC
1801 * loopback diagnostic. */
1802 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1803 IXGBE_FLAG_VMDQ_ENABLED)) {
1804 e_info(hw, "Skip MAC loopback diagnostic in VT "
1805 "mode\n");
1806 data[3] = 0;
1807 goto skip_loopback;
1808 }
1809
1810 ixgbe_reset(adapter);
1811 e_info(hw, "loopback testing starting\n");
1812 if (ixgbe_loopback_test(adapter, &data[3]))
1813 eth_test->flags |= ETH_TEST_FL_FAILED;
1814
1815 skip_loopback:
1816 ixgbe_reset(adapter);
1817
1818 clear_bit(__IXGBE_TESTING, &adapter->state);
1819 if (if_running)
1820 dev_open(netdev);
1821 } else {
1822 e_info(hw, "online testing starting\n");
1823 /* Online tests */
1824 if (ixgbe_link_test(adapter, &data[4]))
1825 eth_test->flags |= ETH_TEST_FL_FAILED;
1826
1827 /* Online tests aren't run; pass by default */
1828 data[0] = 0;
1829 data[1] = 0;
1830 data[2] = 0;
1831 data[3] = 0;
1832
1833 clear_bit(__IXGBE_TESTING, &adapter->state);
1834 }
1835 skip_ol_tests:
1836 msleep_interruptible(4 * 1000);
1837 }
1838
1839 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1840 struct ethtool_wolinfo *wol)
1841 {
1842 struct ixgbe_hw *hw = &adapter->hw;
1843 int retval = 1;
1844
1845 switch(hw->device_id) {
1846 case IXGBE_DEV_ID_82599_KX4:
1847 retval = 0;
1848 break;
1849 default:
1850 wol->supported = 0;
1851 }
1852
1853 return retval;
1854 }
1855
1856 static void ixgbe_get_wol(struct net_device *netdev,
1857 struct ethtool_wolinfo *wol)
1858 {
1859 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1860
1861 wol->supported = WAKE_UCAST | WAKE_MCAST |
1862 WAKE_BCAST | WAKE_MAGIC;
1863 wol->wolopts = 0;
1864
1865 if (ixgbe_wol_exclusion(adapter, wol) ||
1866 !device_can_wakeup(&adapter->pdev->dev))
1867 return;
1868
1869 if (adapter->wol & IXGBE_WUFC_EX)
1870 wol->wolopts |= WAKE_UCAST;
1871 if (adapter->wol & IXGBE_WUFC_MC)
1872 wol->wolopts |= WAKE_MCAST;
1873 if (adapter->wol & IXGBE_WUFC_BC)
1874 wol->wolopts |= WAKE_BCAST;
1875 if (adapter->wol & IXGBE_WUFC_MAG)
1876 wol->wolopts |= WAKE_MAGIC;
1877 }
1878
1879 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1880 {
1881 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1882
1883 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1884 return -EOPNOTSUPP;
1885
1886 if (ixgbe_wol_exclusion(adapter, wol))
1887 return wol->wolopts ? -EOPNOTSUPP : 0;
1888
1889 adapter->wol = 0;
1890
1891 if (wol->wolopts & WAKE_UCAST)
1892 adapter->wol |= IXGBE_WUFC_EX;
1893 if (wol->wolopts & WAKE_MCAST)
1894 adapter->wol |= IXGBE_WUFC_MC;
1895 if (wol->wolopts & WAKE_BCAST)
1896 adapter->wol |= IXGBE_WUFC_BC;
1897 if (wol->wolopts & WAKE_MAGIC)
1898 adapter->wol |= IXGBE_WUFC_MAG;
1899
1900 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1901
1902 return 0;
1903 }
1904
1905 static int ixgbe_nway_reset(struct net_device *netdev)
1906 {
1907 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1908
1909 if (netif_running(netdev))
1910 ixgbe_reinit_locked(adapter);
1911
1912 return 0;
1913 }
1914
1915 static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1916 {
1917 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1918 struct ixgbe_hw *hw = &adapter->hw;
1919 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1920 u32 i;
1921
1922 if (!data || data > 300)
1923 data = 300;
1924
1925 for (i = 0; i < (data * 1000); i += 400) {
1926 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
1927 msleep_interruptible(200);
1928 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
1929 msleep_interruptible(200);
1930 }
1931
1932 /* Restore LED settings */
1933 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
1934
1935 return 0;
1936 }
1937
1938 static int ixgbe_get_coalesce(struct net_device *netdev,
1939 struct ethtool_coalesce *ec)
1940 {
1941 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1942
1943 ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0]->work_limit;
1944
1945 /* only valid if in constant ITR mode */
1946 switch (adapter->rx_itr_setting) {
1947 case 0:
1948 /* throttling disabled */
1949 ec->rx_coalesce_usecs = 0;
1950 break;
1951 case 1:
1952 /* dynamic ITR mode */
1953 ec->rx_coalesce_usecs = 1;
1954 break;
1955 default:
1956 /* fixed interrupt rate mode */
1957 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
1958 break;
1959 }
1960
1961 /* if in mixed tx/rx queues per vector mode, report only rx settings */
1962 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
1963 return 0;
1964
1965 /* only valid if in constant ITR mode */
1966 switch (adapter->tx_itr_setting) {
1967 case 0:
1968 /* throttling disabled */
1969 ec->tx_coalesce_usecs = 0;
1970 break;
1971 case 1:
1972 /* dynamic ITR mode */
1973 ec->tx_coalesce_usecs = 1;
1974 break;
1975 default:
1976 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
1977 break;
1978 }
1979
1980 return 0;
1981 }
1982
1983 static int ixgbe_set_coalesce(struct net_device *netdev,
1984 struct ethtool_coalesce *ec)
1985 {
1986 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1987 struct ixgbe_q_vector *q_vector;
1988 int i;
1989 bool need_reset = false;
1990
1991 /* don't accept tx specific changes if we've got mixed RxTx vectors */
1992 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count
1993 && ec->tx_coalesce_usecs)
1994 return -EINVAL;
1995
1996 if (ec->tx_max_coalesced_frames_irq)
1997 adapter->tx_ring[0]->work_limit = ec->tx_max_coalesced_frames_irq;
1998
1999 if (ec->rx_coalesce_usecs > 1) {
2000 u32 max_int;
2001 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2002 max_int = IXGBE_MAX_RSC_INT_RATE;
2003 else
2004 max_int = IXGBE_MAX_INT_RATE;
2005
2006 /* check the limits */
2007 if ((1000000/ec->rx_coalesce_usecs > max_int) ||
2008 (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2009 return -EINVAL;
2010
2011 /* store the value in ints/second */
2012 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
2013
2014 /* static value of interrupt rate */
2015 adapter->rx_itr_setting = adapter->rx_eitr_param;
2016 /* clear the lower bit as its used for dynamic state */
2017 adapter->rx_itr_setting &= ~1;
2018 } else if (ec->rx_coalesce_usecs == 1) {
2019 /* 1 means dynamic mode */
2020 adapter->rx_eitr_param = 20000;
2021 adapter->rx_itr_setting = 1;
2022 } else {
2023 /*
2024 * any other value means disable eitr, which is best
2025 * served by setting the interrupt rate very high
2026 */
2027 adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
2028 adapter->rx_itr_setting = 0;
2029
2030 /*
2031 * if hardware RSC is enabled, disable it when
2032 * setting low latency mode, to avoid errata, assuming
2033 * that when the user set low latency mode they want
2034 * it at the cost of anything else
2035 */
2036 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2037 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2038 if (netdev->features & NETIF_F_LRO) {
2039 netdev->features &= ~NETIF_F_LRO;
2040 e_info(probe, "rx-usecs set to 0, "
2041 "disabling RSC\n");
2042 }
2043 need_reset = true;
2044 }
2045 }
2046
2047 if (ec->tx_coalesce_usecs > 1) {
2048 /*
2049 * don't have to worry about max_int as above because
2050 * tx vectors don't do hardware RSC (an rx function)
2051 */
2052 /* check the limits */
2053 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2054 (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2055 return -EINVAL;
2056
2057 /* store the value in ints/second */
2058 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2059
2060 /* static value of interrupt rate */
2061 adapter->tx_itr_setting = adapter->tx_eitr_param;
2062
2063 /* clear the lower bit as its used for dynamic state */
2064 adapter->tx_itr_setting &= ~1;
2065 } else if (ec->tx_coalesce_usecs == 1) {
2066 /* 1 means dynamic mode */
2067 adapter->tx_eitr_param = 10000;
2068 adapter->tx_itr_setting = 1;
2069 } else {
2070 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2071 adapter->tx_itr_setting = 0;
2072 }
2073
2074 /* MSI/MSIx Interrupt Mode */
2075 if (adapter->flags &
2076 (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2077 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2078 for (i = 0; i < num_vectors; i++) {
2079 q_vector = adapter->q_vector[i];
2080 if (q_vector->txr_count && !q_vector->rxr_count)
2081 /* tx only */
2082 q_vector->eitr = adapter->tx_eitr_param;
2083 else
2084 /* rx only or mixed */
2085 q_vector->eitr = adapter->rx_eitr_param;
2086 ixgbe_write_eitr(q_vector);
2087 }
2088 /* Legacy Interrupt Mode */
2089 } else {
2090 q_vector = adapter->q_vector[0];
2091 q_vector->eitr = adapter->rx_eitr_param;
2092 ixgbe_write_eitr(q_vector);
2093 }
2094
2095 /*
2096 * do reset here at the end to make sure EITR==0 case is handled
2097 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2098 * also locks in RSC enable/disable which requires reset
2099 */
2100 if (need_reset) {
2101 if (netif_running(netdev))
2102 ixgbe_reinit_locked(adapter);
2103 else
2104 ixgbe_reset(adapter);
2105 }
2106
2107 return 0;
2108 }
2109
2110 static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2111 {
2112 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2113 bool need_reset = false;
2114 int rc;
2115
2116 #ifdef CONFIG_IXGBE_DCB
2117 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
2118 !(data & ETH_FLAG_RXVLAN))
2119 return -EINVAL;
2120 #endif
2121
2122 need_reset = (data & ETH_FLAG_RXVLAN) !=
2123 (netdev->features & NETIF_F_HW_VLAN_RX);
2124
2125 rc = ethtool_op_set_flags(netdev, data, ETH_FLAG_LRO |
2126 ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN);
2127 if (rc)
2128 return rc;
2129
2130 /* if state changes we need to update adapter->flags and reset */
2131 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) {
2132 /*
2133 * cast both to bool and verify if they are set the same
2134 * but only enable RSC if itr is non-zero, as
2135 * itr=0 and RSC are mutually exclusive
2136 */
2137 if (((!!(data & ETH_FLAG_LRO)) !=
2138 (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) &&
2139 adapter->rx_itr_setting) {
2140 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2141 switch (adapter->hw.mac.type) {
2142 case ixgbe_mac_82599EB:
2143 need_reset = true;
2144 break;
2145 default:
2146 break;
2147 }
2148 } else if (!adapter->rx_itr_setting) {
2149 netdev->features &= ~NETIF_F_LRO;
2150 if (data & ETH_FLAG_LRO)
2151 e_info(probe, "rx-usecs set to 0, "
2152 "LRO/RSC cannot be enabled.\n");
2153 }
2154 }
2155
2156 /*
2157 * Check if Flow Director n-tuple support was enabled or disabled. If
2158 * the state changed, we need to reset.
2159 */
2160 if ((adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) &&
2161 (!(data & ETH_FLAG_NTUPLE))) {
2162 /* turn off Flow Director perfect, set hash and reset */
2163 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2164 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
2165 need_reset = true;
2166 } else if ((!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) &&
2167 (data & ETH_FLAG_NTUPLE)) {
2168 /* turn off Flow Director hash, enable perfect and reset */
2169 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
2170 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2171 need_reset = true;
2172 } else {
2173 /* no state change */
2174 }
2175
2176 if (need_reset) {
2177 if (netif_running(netdev))
2178 ixgbe_reinit_locked(adapter);
2179 else
2180 ixgbe_reset(adapter);
2181 }
2182
2183 return 0;
2184 }
2185
2186 static int ixgbe_set_rx_ntuple(struct net_device *dev,
2187 struct ethtool_rx_ntuple *cmd)
2188 {
2189 struct ixgbe_adapter *adapter = netdev_priv(dev);
2190 struct ethtool_rx_ntuple_flow_spec fs = cmd->fs;
2191 struct ixgbe_atr_input input_struct;
2192 struct ixgbe_atr_input_masks input_masks;
2193 int target_queue;
2194
2195 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2196 return -EOPNOTSUPP;
2197
2198 /*
2199 * Don't allow programming if the action is a queue greater than
2200 * the number of online Tx queues.
2201 */
2202 if ((fs.action >= adapter->num_tx_queues) ||
2203 (fs.action < ETHTOOL_RXNTUPLE_ACTION_DROP))
2204 return -EINVAL;
2205
2206 memset(&input_struct, 0, sizeof(struct ixgbe_atr_input));
2207 memset(&input_masks, 0, sizeof(struct ixgbe_atr_input_masks));
2208
2209 input_masks.src_ip_mask = fs.m_u.tcp_ip4_spec.ip4src;
2210 input_masks.dst_ip_mask = fs.m_u.tcp_ip4_spec.ip4dst;
2211 input_masks.src_port_mask = fs.m_u.tcp_ip4_spec.psrc;
2212 input_masks.dst_port_mask = fs.m_u.tcp_ip4_spec.pdst;
2213 input_masks.vlan_id_mask = fs.vlan_tag_mask;
2214 /* only use the lowest 2 bytes for flex bytes */
2215 input_masks.data_mask = (fs.data_mask & 0xffff);
2216
2217 switch (fs.flow_type) {
2218 case TCP_V4_FLOW:
2219 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_TCP);
2220 break;
2221 case UDP_V4_FLOW:
2222 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_UDP);
2223 break;
2224 case SCTP_V4_FLOW:
2225 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_SCTP);
2226 break;
2227 default:
2228 return -1;
2229 }
2230
2231 /* Mask bits from the inputs based on user-supplied mask */
2232 ixgbe_atr_set_src_ipv4_82599(&input_struct,
2233 (fs.h_u.tcp_ip4_spec.ip4src & ~fs.m_u.tcp_ip4_spec.ip4src));
2234 ixgbe_atr_set_dst_ipv4_82599(&input_struct,
2235 (fs.h_u.tcp_ip4_spec.ip4dst & ~fs.m_u.tcp_ip4_spec.ip4dst));
2236 /* 82599 expects these to be byte-swapped for perfect filtering */
2237 ixgbe_atr_set_src_port_82599(&input_struct,
2238 ((ntohs(fs.h_u.tcp_ip4_spec.psrc)) & ~fs.m_u.tcp_ip4_spec.psrc));
2239 ixgbe_atr_set_dst_port_82599(&input_struct,
2240 ((ntohs(fs.h_u.tcp_ip4_spec.pdst)) & ~fs.m_u.tcp_ip4_spec.pdst));
2241
2242 /* VLAN and Flex bytes are either completely masked or not */
2243 if (!fs.vlan_tag_mask)
2244 ixgbe_atr_set_vlan_id_82599(&input_struct, fs.vlan_tag);
2245
2246 if (!input_masks.data_mask)
2247 /* make sure we only use the first 2 bytes of user data */
2248 ixgbe_atr_set_flex_byte_82599(&input_struct,
2249 (fs.data & 0xffff));
2250
2251 /* determine if we need to drop or route the packet */
2252 if (fs.action == ETHTOOL_RXNTUPLE_ACTION_DROP)
2253 target_queue = MAX_RX_QUEUES - 1;
2254 else
2255 target_queue = fs.action;
2256
2257 spin_lock(&adapter->fdir_perfect_lock);
2258 ixgbe_fdir_add_perfect_filter_82599(&adapter->hw, &input_struct,
2259 &input_masks, 0, target_queue);
2260 spin_unlock(&adapter->fdir_perfect_lock);
2261
2262 return 0;
2263 }
2264
2265 static const struct ethtool_ops ixgbe_ethtool_ops = {
2266 .get_settings = ixgbe_get_settings,
2267 .set_settings = ixgbe_set_settings,
2268 .get_drvinfo = ixgbe_get_drvinfo,
2269 .get_regs_len = ixgbe_get_regs_len,
2270 .get_regs = ixgbe_get_regs,
2271 .get_wol = ixgbe_get_wol,
2272 .set_wol = ixgbe_set_wol,
2273 .nway_reset = ixgbe_nway_reset,
2274 .get_link = ethtool_op_get_link,
2275 .get_eeprom_len = ixgbe_get_eeprom_len,
2276 .get_eeprom = ixgbe_get_eeprom,
2277 .get_ringparam = ixgbe_get_ringparam,
2278 .set_ringparam = ixgbe_set_ringparam,
2279 .get_pauseparam = ixgbe_get_pauseparam,
2280 .set_pauseparam = ixgbe_set_pauseparam,
2281 .get_rx_csum = ixgbe_get_rx_csum,
2282 .set_rx_csum = ixgbe_set_rx_csum,
2283 .get_tx_csum = ixgbe_get_tx_csum,
2284 .set_tx_csum = ixgbe_set_tx_csum,
2285 .get_sg = ethtool_op_get_sg,
2286 .set_sg = ethtool_op_set_sg,
2287 .get_msglevel = ixgbe_get_msglevel,
2288 .set_msglevel = ixgbe_set_msglevel,
2289 .get_tso = ethtool_op_get_tso,
2290 .set_tso = ixgbe_set_tso,
2291 .self_test = ixgbe_diag_test,
2292 .get_strings = ixgbe_get_strings,
2293 .phys_id = ixgbe_phys_id,
2294 .get_sset_count = ixgbe_get_sset_count,
2295 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2296 .get_coalesce = ixgbe_get_coalesce,
2297 .set_coalesce = ixgbe_set_coalesce,
2298 .get_flags = ethtool_op_get_flags,
2299 .set_flags = ixgbe_set_flags,
2300 .set_rx_ntuple = ixgbe_set_rx_ntuple,
2301 };
2302
2303 void ixgbe_set_ethtool_ops(struct net_device *netdev)
2304 {
2305 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2306 }
kernel source for telekom puls (alcatel/mediatek)