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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_82599.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
35
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41
42 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
43 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg,
52 bool autoneg_wait_to_complete);
53 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed,
57 bool autoneg,
58 bool autoneg_wait_to_complete);
59 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed speed,
61 bool autoneg,
62 bool autoneg_wait_to_complete);
63 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
64
65 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
66 {
67 struct ixgbe_mac_info *mac = &hw->mac;
68
69 /* enable the laser control functions for SFP+ fiber */
70 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
71 mac->ops.disable_tx_laser =
72 &ixgbe_disable_tx_laser_multispeed_fiber;
73 mac->ops.enable_tx_laser =
74 &ixgbe_enable_tx_laser_multispeed_fiber;
75 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
76 } else {
77 mac->ops.disable_tx_laser = NULL;
78 mac->ops.enable_tx_laser = NULL;
79 mac->ops.flap_tx_laser = NULL;
80 }
81
82 if (hw->phy.multispeed_fiber) {
83 /* Set up dual speed SFP+ support */
84 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
85 } else {
86 if ((mac->ops.get_media_type(hw) ==
87 ixgbe_media_type_backplane) &&
88 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
89 hw->phy.smart_speed == ixgbe_smart_speed_on))
90 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
91 else
92 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
93 }
94 }
95
96 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
97 {
98 s32 ret_val = 0;
99 u16 list_offset, data_offset, data_value;
100
101 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
102 ixgbe_init_mac_link_ops_82599(hw);
103
104 hw->phy.ops.reset = NULL;
105
106 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
107 &data_offset);
108
109 if (ret_val != 0)
110 goto setup_sfp_out;
111
112 /* PHY config will finish before releasing the semaphore */
113 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
114 if (ret_val != 0) {
115 ret_val = IXGBE_ERR_SWFW_SYNC;
116 goto setup_sfp_out;
117 }
118
119 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
120 while (data_value != 0xffff) {
121 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
122 IXGBE_WRITE_FLUSH(hw);
123 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
124 }
125 /* Now restart DSP by setting Restart_AN */
126 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
127 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
128
129 /* Release the semaphore */
130 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
131 /* Delay obtaining semaphore again to allow FW access */
132 msleep(hw->eeprom.semaphore_delay);
133 }
134
135 setup_sfp_out:
136 return ret_val;
137 }
138
139 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
140 {
141 struct ixgbe_mac_info *mac = &hw->mac;
142
143 ixgbe_init_mac_link_ops_82599(hw);
144
145 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
146 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
147 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
148 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
149 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
150 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
151
152 return 0;
153 }
154
155 /**
156 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
157 * @hw: pointer to hardware structure
158 *
159 * Initialize any function pointers that were not able to be
160 * set during get_invariants because the PHY/SFP type was
161 * not known. Perform the SFP init if necessary.
162 *
163 **/
164 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
165 {
166 struct ixgbe_mac_info *mac = &hw->mac;
167 struct ixgbe_phy_info *phy = &hw->phy;
168 s32 ret_val = 0;
169
170 /* Identify the PHY or SFP module */
171 ret_val = phy->ops.identify(hw);
172
173 /* Setup function pointers based on detected SFP module and speeds */
174 ixgbe_init_mac_link_ops_82599(hw);
175
176 /* If copper media, overwrite with copper function pointers */
177 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
178 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
179 mac->ops.get_link_capabilities =
180 &ixgbe_get_copper_link_capabilities_generic;
181 }
182
183 /* Set necessary function pointers based on phy type */
184 switch (hw->phy.type) {
185 case ixgbe_phy_tn:
186 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
187 phy->ops.get_firmware_version =
188 &ixgbe_get_phy_firmware_version_tnx;
189 break;
190 case ixgbe_phy_aq:
191 phy->ops.get_firmware_version =
192 &ixgbe_get_phy_firmware_version_generic;
193 break;
194 default:
195 break;
196 }
197
198 return ret_val;
199 }
200
201 /**
202 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
203 * @hw: pointer to hardware structure
204 * @speed: pointer to link speed
205 * @negotiation: true when autoneg or autotry is enabled
206 *
207 * Determines the link capabilities by reading the AUTOC register.
208 **/
209 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
210 ixgbe_link_speed *speed,
211 bool *negotiation)
212 {
213 s32 status = 0;
214 u32 autoc = 0;
215
216 /* Determine 1G link capabilities off of SFP+ type */
217 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
218 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
219 *speed = IXGBE_LINK_SPEED_1GB_FULL;
220 *negotiation = true;
221 goto out;
222 }
223
224 /*
225 * Determine link capabilities based on the stored value of AUTOC,
226 * which represents EEPROM defaults. If AUTOC value has not been
227 * stored, use the current register value.
228 */
229 if (hw->mac.orig_link_settings_stored)
230 autoc = hw->mac.orig_autoc;
231 else
232 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
233
234 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
235 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
236 *speed = IXGBE_LINK_SPEED_1GB_FULL;
237 *negotiation = false;
238 break;
239
240 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
241 *speed = IXGBE_LINK_SPEED_10GB_FULL;
242 *negotiation = false;
243 break;
244
245 case IXGBE_AUTOC_LMS_1G_AN:
246 *speed = IXGBE_LINK_SPEED_1GB_FULL;
247 *negotiation = true;
248 break;
249
250 case IXGBE_AUTOC_LMS_10G_SERIAL:
251 *speed = IXGBE_LINK_SPEED_10GB_FULL;
252 *negotiation = false;
253 break;
254
255 case IXGBE_AUTOC_LMS_KX4_KX_KR:
256 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
257 *speed = IXGBE_LINK_SPEED_UNKNOWN;
258 if (autoc & IXGBE_AUTOC_KR_SUPP)
259 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
260 if (autoc & IXGBE_AUTOC_KX4_SUPP)
261 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
262 if (autoc & IXGBE_AUTOC_KX_SUPP)
263 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
264 *negotiation = true;
265 break;
266
267 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
268 *speed = IXGBE_LINK_SPEED_100_FULL;
269 if (autoc & IXGBE_AUTOC_KR_SUPP)
270 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
271 if (autoc & IXGBE_AUTOC_KX4_SUPP)
272 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
273 if (autoc & IXGBE_AUTOC_KX_SUPP)
274 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
275 *negotiation = true;
276 break;
277
278 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
279 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
280 *negotiation = false;
281 break;
282
283 default:
284 status = IXGBE_ERR_LINK_SETUP;
285 goto out;
286 break;
287 }
288
289 if (hw->phy.multispeed_fiber) {
290 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
291 IXGBE_LINK_SPEED_1GB_FULL;
292 *negotiation = true;
293 }
294
295 out:
296 return status;
297 }
298
299 /**
300 * ixgbe_get_media_type_82599 - Get media type
301 * @hw: pointer to hardware structure
302 *
303 * Returns the media type (fiber, copper, backplane)
304 **/
305 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
306 {
307 enum ixgbe_media_type media_type;
308
309 /* Detect if there is a copper PHY attached. */
310 if (hw->phy.type == ixgbe_phy_cu_unknown ||
311 hw->phy.type == ixgbe_phy_tn ||
312 hw->phy.type == ixgbe_phy_aq) {
313 media_type = ixgbe_media_type_copper;
314 goto out;
315 }
316
317 switch (hw->device_id) {
318 case IXGBE_DEV_ID_82599_KX4:
319 case IXGBE_DEV_ID_82599_KX4_MEZZ:
320 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
321 case IXGBE_DEV_ID_82599_KR:
322 case IXGBE_DEV_ID_82599_XAUI_LOM:
323 /* Default device ID is mezzanine card KX/KX4 */
324 media_type = ixgbe_media_type_backplane;
325 break;
326 case IXGBE_DEV_ID_82599_SFP:
327 case IXGBE_DEV_ID_82599_SFP_EM:
328 media_type = ixgbe_media_type_fiber;
329 break;
330 case IXGBE_DEV_ID_82599_CX4:
331 media_type = ixgbe_media_type_cx4;
332 break;
333 default:
334 media_type = ixgbe_media_type_unknown;
335 break;
336 }
337 out:
338 return media_type;
339 }
340
341 /**
342 * ixgbe_start_mac_link_82599 - Setup MAC link settings
343 * @hw: pointer to hardware structure
344 * @autoneg_wait_to_complete: true when waiting for completion is needed
345 *
346 * Configures link settings based on values in the ixgbe_hw struct.
347 * Restarts the link. Performs autonegotiation if needed.
348 **/
349 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
350 bool autoneg_wait_to_complete)
351 {
352 u32 autoc_reg;
353 u32 links_reg;
354 u32 i;
355 s32 status = 0;
356
357 /* Restart link */
358 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
359 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
360 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
361
362 /* Only poll for autoneg to complete if specified to do so */
363 if (autoneg_wait_to_complete) {
364 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
365 IXGBE_AUTOC_LMS_KX4_KX_KR ||
366 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
367 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
368 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
369 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
370 links_reg = 0; /* Just in case Autoneg time = 0 */
371 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
372 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
373 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
374 break;
375 msleep(100);
376 }
377 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
378 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
379 hw_dbg(hw, "Autoneg did not complete.\n");
380 }
381 }
382 }
383
384 /* Add delay to filter out noises during initial link setup */
385 msleep(50);
386
387 return status;
388 }
389
390 /**
391 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
392 * @hw: pointer to hardware structure
393 *
394 * The base drivers may require better control over SFP+ module
395 * PHY states. This includes selectively shutting down the Tx
396 * laser on the PHY, effectively halting physical link.
397 **/
398 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
399 {
400 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
401
402 /* Disable tx laser; allow 100us to go dark per spec */
403 esdp_reg |= IXGBE_ESDP_SDP3;
404 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
405 IXGBE_WRITE_FLUSH(hw);
406 udelay(100);
407 }
408
409 /**
410 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
411 * @hw: pointer to hardware structure
412 *
413 * The base drivers may require better control over SFP+ module
414 * PHY states. This includes selectively turning on the Tx
415 * laser on the PHY, effectively starting physical link.
416 **/
417 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
418 {
419 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
420
421 /* Enable tx laser; allow 100ms to light up */
422 esdp_reg &= ~IXGBE_ESDP_SDP3;
423 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
424 IXGBE_WRITE_FLUSH(hw);
425 msleep(100);
426 }
427
428 /**
429 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
430 * @hw: pointer to hardware structure
431 *
432 * When the driver changes the link speeds that it can support,
433 * it sets autotry_restart to true to indicate that we need to
434 * initiate a new autotry session with the link partner. To do
435 * so, we set the speed then disable and re-enable the tx laser, to
436 * alert the link partner that it also needs to restart autotry on its
437 * end. This is consistent with true clause 37 autoneg, which also
438 * involves a loss of signal.
439 **/
440 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
441 {
442 hw_dbg(hw, "ixgbe_flap_tx_laser_multispeed_fiber\n");
443
444 if (hw->mac.autotry_restart) {
445 ixgbe_disable_tx_laser_multispeed_fiber(hw);
446 ixgbe_enable_tx_laser_multispeed_fiber(hw);
447 hw->mac.autotry_restart = false;
448 }
449 }
450
451 /**
452 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
453 * @hw: pointer to hardware structure
454 * @speed: new link speed
455 * @autoneg: true if autonegotiation enabled
456 * @autoneg_wait_to_complete: true when waiting for completion is needed
457 *
458 * Set the link speed in the AUTOC register and restarts link.
459 **/
460 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
461 ixgbe_link_speed speed,
462 bool autoneg,
463 bool autoneg_wait_to_complete)
464 {
465 s32 status = 0;
466 ixgbe_link_speed phy_link_speed;
467 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
468 u32 speedcnt = 0;
469 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
470 bool link_up = false;
471 bool negotiation;
472 int i;
473
474 /* Mask off requested but non-supported speeds */
475 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
476 speed &= phy_link_speed;
477
478 /*
479 * Try each speed one by one, highest priority first. We do this in
480 * software because 10gb fiber doesn't support speed autonegotiation.
481 */
482 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
483 speedcnt++;
484 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
485
486 /* If we already have link at this speed, just jump out */
487 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
488
489 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
490 goto out;
491
492 /* Set the module link speed */
493 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
494 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
495 IXGBE_WRITE_FLUSH(hw);
496
497 /* Allow module to change analog characteristics (1G->10G) */
498 msleep(40);
499
500 status = ixgbe_setup_mac_link_82599(hw,
501 IXGBE_LINK_SPEED_10GB_FULL,
502 autoneg,
503 autoneg_wait_to_complete);
504 if (status != 0)
505 return status;
506
507 /* Flap the tx laser if it has not already been done */
508 hw->mac.ops.flap_tx_laser(hw);
509
510 /*
511 * Wait for the controller to acquire link. Per IEEE 802.3ap,
512 * Section 73.10.2, we may have to wait up to 500ms if KR is
513 * attempted. 82599 uses the same timing for 10g SFI.
514 */
515
516 for (i = 0; i < 5; i++) {
517 /* Wait for the link partner to also set speed */
518 msleep(100);
519
520 /* If we have link, just jump out */
521 hw->mac.ops.check_link(hw, &phy_link_speed,
522 &link_up, false);
523 if (link_up)
524 goto out;
525 }
526 }
527
528 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
529 speedcnt++;
530 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
531 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
532
533 /* If we already have link at this speed, just jump out */
534 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
535
536 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
537 goto out;
538
539 /* Set the module link speed */
540 esdp_reg &= ~IXGBE_ESDP_SDP5;
541 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
542 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
543 IXGBE_WRITE_FLUSH(hw);
544
545 /* Allow module to change analog characteristics (10G->1G) */
546 msleep(40);
547
548 status = ixgbe_setup_mac_link_82599(hw,
549 IXGBE_LINK_SPEED_1GB_FULL,
550 autoneg,
551 autoneg_wait_to_complete);
552 if (status != 0)
553 return status;
554
555 /* Flap the tx laser if it has not already been done */
556 hw->mac.ops.flap_tx_laser(hw);
557
558 /* Wait for the link partner to also set speed */
559 msleep(100);
560
561 /* If we have link, just jump out */
562 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
563 if (link_up)
564 goto out;
565 }
566
567 /*
568 * We didn't get link. Configure back to the highest speed we tried,
569 * (if there was more than one). We call ourselves back with just the
570 * single highest speed that the user requested.
571 */
572 if (speedcnt > 1)
573 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
574 highest_link_speed,
575 autoneg,
576 autoneg_wait_to_complete);
577
578 out:
579 /* Set autoneg_advertised value based on input link speed */
580 hw->phy.autoneg_advertised = 0;
581
582 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
583 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
584
585 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
586 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
587
588 return status;
589 }
590
591 /**
592 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
593 * @hw: pointer to hardware structure
594 * @speed: new link speed
595 * @autoneg: true if autonegotiation enabled
596 * @autoneg_wait_to_complete: true when waiting for completion is needed
597 *
598 * Implements the Intel SmartSpeed algorithm.
599 **/
600 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
601 ixgbe_link_speed speed, bool autoneg,
602 bool autoneg_wait_to_complete)
603 {
604 s32 status = 0;
605 ixgbe_link_speed link_speed;
606 s32 i, j;
607 bool link_up = false;
608 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
609 struct ixgbe_adapter *adapter = hw->back;
610
611 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
612
613 /* Set autoneg_advertised value based on input link speed */
614 hw->phy.autoneg_advertised = 0;
615
616 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
617 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
618
619 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
620 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
621
622 if (speed & IXGBE_LINK_SPEED_100_FULL)
623 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
624
625 /*
626 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
627 * autoneg advertisement if link is unable to be established at the
628 * highest negotiated rate. This can sometimes happen due to integrity
629 * issues with the physical media connection.
630 */
631
632 /* First, try to get link with full advertisement */
633 hw->phy.smart_speed_active = false;
634 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
635 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
636 autoneg_wait_to_complete);
637 if (status)
638 goto out;
639
640 /*
641 * Wait for the controller to acquire link. Per IEEE 802.3ap,
642 * Section 73.10.2, we may have to wait up to 500ms if KR is
643 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
644 * Table 9 in the AN MAS.
645 */
646 for (i = 0; i < 5; i++) {
647 mdelay(100);
648
649 /* If we have link, just jump out */
650 hw->mac.ops.check_link(hw, &link_speed,
651 &link_up, false);
652 if (link_up)
653 goto out;
654 }
655 }
656
657 /*
658 * We didn't get link. If we advertised KR plus one of KX4/KX
659 * (or BX4/BX), then disable KR and try again.
660 */
661 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
662 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
663 goto out;
664
665 /* Turn SmartSpeed on to disable KR support */
666 hw->phy.smart_speed_active = true;
667 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
668 autoneg_wait_to_complete);
669 if (status)
670 goto out;
671
672 /*
673 * Wait for the controller to acquire link. 600ms will allow for
674 * the AN link_fail_inhibit_timer as well for multiple cycles of
675 * parallel detect, both 10g and 1g. This allows for the maximum
676 * connect attempts as defined in the AN MAS table 73-7.
677 */
678 for (i = 0; i < 6; i++) {
679 mdelay(100);
680
681 /* If we have link, just jump out */
682 hw->mac.ops.check_link(hw, &link_speed,
683 &link_up, false);
684 if (link_up)
685 goto out;
686 }
687
688 /* We didn't get link. Turn SmartSpeed back off. */
689 hw->phy.smart_speed_active = false;
690 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
691 autoneg_wait_to_complete);
692
693 out:
694 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
695 e_info(hw, "Smartspeed has downgraded the link speed from "
696 "the maximum advertised\n");
697 return status;
698 }
699
700 /**
701 * ixgbe_setup_mac_link_82599 - Set MAC link speed
702 * @hw: pointer to hardware structure
703 * @speed: new link speed
704 * @autoneg: true if autonegotiation enabled
705 * @autoneg_wait_to_complete: true when waiting for completion is needed
706 *
707 * Set the link speed in the AUTOC register and restarts link.
708 **/
709 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
710 ixgbe_link_speed speed, bool autoneg,
711 bool autoneg_wait_to_complete)
712 {
713 s32 status = 0;
714 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
715 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
716 u32 start_autoc = autoc;
717 u32 orig_autoc = 0;
718 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
719 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
720 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
721 u32 links_reg;
722 u32 i;
723 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
724
725 /* Check to see if speed passed in is supported. */
726 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
727 speed &= link_capabilities;
728
729 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
730 status = IXGBE_ERR_LINK_SETUP;
731 goto out;
732 }
733
734 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
735 if (hw->mac.orig_link_settings_stored)
736 orig_autoc = hw->mac.orig_autoc;
737 else
738 orig_autoc = autoc;
739
740
741 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
742 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
743 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
744 /* Set KX4/KX/KR support according to speed requested */
745 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
746 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
747 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
748 autoc |= IXGBE_AUTOC_KX4_SUPP;
749 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
750 (hw->phy.smart_speed_active == false))
751 autoc |= IXGBE_AUTOC_KR_SUPP;
752 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
753 autoc |= IXGBE_AUTOC_KX_SUPP;
754 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
755 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
756 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
757 /* Switch from 1G SFI to 10G SFI if requested */
758 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
759 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
760 autoc &= ~IXGBE_AUTOC_LMS_MASK;
761 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
762 }
763 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
764 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
765 /* Switch from 10G SFI to 1G SFI if requested */
766 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
767 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
768 autoc &= ~IXGBE_AUTOC_LMS_MASK;
769 if (autoneg)
770 autoc |= IXGBE_AUTOC_LMS_1G_AN;
771 else
772 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
773 }
774 }
775
776 if (autoc != start_autoc) {
777 /* Restart link */
778 autoc |= IXGBE_AUTOC_AN_RESTART;
779 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
780
781 /* Only poll for autoneg to complete if specified to do so */
782 if (autoneg_wait_to_complete) {
783 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
784 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
785 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
786 links_reg = 0; /*Just in case Autoneg time=0*/
787 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
788 links_reg =
789 IXGBE_READ_REG(hw, IXGBE_LINKS);
790 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
791 break;
792 msleep(100);
793 }
794 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
795 status =
796 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
797 hw_dbg(hw, "Autoneg did not "
798 "complete.\n");
799 }
800 }
801 }
802
803 /* Add delay to filter out noises during initial link setup */
804 msleep(50);
805 }
806
807 out:
808 return status;
809 }
810
811 /**
812 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
813 * @hw: pointer to hardware structure
814 * @speed: new link speed
815 * @autoneg: true if autonegotiation enabled
816 * @autoneg_wait_to_complete: true if waiting is needed to complete
817 *
818 * Restarts link on PHY and MAC based on settings passed in.
819 **/
820 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
821 ixgbe_link_speed speed,
822 bool autoneg,
823 bool autoneg_wait_to_complete)
824 {
825 s32 status;
826
827 /* Setup the PHY according to input speed */
828 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
829 autoneg_wait_to_complete);
830 /* Set up MAC */
831 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
832
833 return status;
834 }
835
836 /**
837 * ixgbe_reset_hw_82599 - Perform hardware reset
838 * @hw: pointer to hardware structure
839 *
840 * Resets the hardware by resetting the transmit and receive units, masks
841 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
842 * reset.
843 **/
844 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
845 {
846 s32 status = 0;
847 u32 ctrl;
848 u32 i;
849 u32 autoc;
850 u32 autoc2;
851
852 /* Call adapter stop to disable tx/rx and clear interrupts */
853 hw->mac.ops.stop_adapter(hw);
854
855 /* PHY ops must be identified and initialized prior to reset */
856
857 /* Init PHY and function pointers, perform SFP setup */
858 status = hw->phy.ops.init(hw);
859
860 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
861 goto reset_hw_out;
862
863 /* Setup SFP module if there is one present. */
864 if (hw->phy.sfp_setup_needed) {
865 status = hw->mac.ops.setup_sfp(hw);
866 hw->phy.sfp_setup_needed = false;
867 }
868
869 /* Reset PHY */
870 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
871 hw->phy.ops.reset(hw);
872
873 /*
874 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
875 * access and verify no pending requests before reset
876 */
877 status = ixgbe_disable_pcie_master(hw);
878 if (status != 0) {
879 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
880 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
881 }
882
883 /*
884 * Issue global reset to the MAC. This needs to be a SW reset.
885 * If link reset is used, it might reset the MAC when mng is using it
886 */
887 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
888 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
889 IXGBE_WRITE_FLUSH(hw);
890
891 /* Poll for reset bit to self-clear indicating reset is complete */
892 for (i = 0; i < 10; i++) {
893 udelay(1);
894 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
895 if (!(ctrl & IXGBE_CTRL_RST))
896 break;
897 }
898 if (ctrl & IXGBE_CTRL_RST) {
899 status = IXGBE_ERR_RESET_FAILED;
900 hw_dbg(hw, "Reset polling failed to complete.\n");
901 }
902
903 msleep(50);
904
905 /*
906 * Store the original AUTOC/AUTOC2 values if they have not been
907 * stored off yet. Otherwise restore the stored original
908 * values since the reset operation sets back to defaults.
909 */
910 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
911 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
912 if (hw->mac.orig_link_settings_stored == false) {
913 hw->mac.orig_autoc = autoc;
914 hw->mac.orig_autoc2 = autoc2;
915 hw->mac.orig_link_settings_stored = true;
916 } else {
917 if (autoc != hw->mac.orig_autoc)
918 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
919 IXGBE_AUTOC_AN_RESTART));
920
921 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
922 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
923 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
924 autoc2 |= (hw->mac.orig_autoc2 &
925 IXGBE_AUTOC2_UPPER_MASK);
926 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
927 }
928 }
929
930 /*
931 * Store MAC address from RAR0, clear receive address registers, and
932 * clear the multicast table. Also reset num_rar_entries to 128,
933 * since we modify this value when programming the SAN MAC address.
934 */
935 hw->mac.num_rar_entries = 128;
936 hw->mac.ops.init_rx_addrs(hw);
937
938 /* Store the permanent mac address */
939 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
940
941 /* Store the permanent SAN mac address */
942 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
943
944 /* Add the SAN MAC address to the RAR only if it's a valid address */
945 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
946 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
947 hw->mac.san_addr, 0, IXGBE_RAH_AV);
948
949 /* Reserve the last RAR for the SAN MAC address */
950 hw->mac.num_rar_entries--;
951 }
952
953 /* Store the alternative WWNN/WWPN prefix */
954 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
955 &hw->mac.wwpn_prefix);
956
957 reset_hw_out:
958 return status;
959 }
960
961 /**
962 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
963 * @hw: pointer to hardware structure
964 **/
965 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
966 {
967 int i;
968 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
969 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
970
971 /*
972 * Before starting reinitialization process,
973 * FDIRCMD.CMD must be zero.
974 */
975 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
976 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
977 IXGBE_FDIRCMD_CMD_MASK))
978 break;
979 udelay(10);
980 }
981 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
982 hw_dbg(hw ,"Flow Director previous command isn't complete, "
983 "aborting table re-initialization.\n");
984 return IXGBE_ERR_FDIR_REINIT_FAILED;
985 }
986
987 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
988 IXGBE_WRITE_FLUSH(hw);
989 /*
990 * 82599 adapters flow director init flow cannot be restarted,
991 * Workaround 82599 silicon errata by performing the following steps
992 * before re-writing the FDIRCTRL control register with the same value.
993 * - write 1 to bit 8 of FDIRCMD register &
994 * - write 0 to bit 8 of FDIRCMD register
995 */
996 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
997 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
998 IXGBE_FDIRCMD_CLEARHT));
999 IXGBE_WRITE_FLUSH(hw);
1000 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1001 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1002 ~IXGBE_FDIRCMD_CLEARHT));
1003 IXGBE_WRITE_FLUSH(hw);
1004 /*
1005 * Clear FDIR Hash register to clear any leftover hashes
1006 * waiting to be programmed.
1007 */
1008 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1009 IXGBE_WRITE_FLUSH(hw);
1010
1011 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1012 IXGBE_WRITE_FLUSH(hw);
1013
1014 /* Poll init-done after we write FDIRCTRL register */
1015 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1016 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1017 IXGBE_FDIRCTRL_INIT_DONE)
1018 break;
1019 udelay(10);
1020 }
1021 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1022 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1023 return IXGBE_ERR_FDIR_REINIT_FAILED;
1024 }
1025
1026 /* Clear FDIR statistics registers (read to clear) */
1027 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1028 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1029 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1030 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1031 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1032
1033 return 0;
1034 }
1035
1036 /**
1037 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1038 * @hw: pointer to hardware structure
1039 * @pballoc: which mode to allocate filters with
1040 **/
1041 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1042 {
1043 u32 fdirctrl = 0;
1044 u32 pbsize;
1045 int i;
1046
1047 /*
1048 * Before enabling Flow Director, the Rx Packet Buffer size
1049 * must be reduced. The new value is the current size minus
1050 * flow director memory usage size.
1051 */
1052 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1053 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1054 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1055
1056 /*
1057 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1058 * intialized to zero for non DCB mode otherwise actual total RX PB
1059 * would be bigger than programmed and filter space would run into
1060 * the PB 0 region.
1061 */
1062 for (i = 1; i < 8; i++)
1063 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1064
1065 /* Send interrupt when 64 filters are left */
1066 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1067
1068 /* Set the maximum length per hash bucket to 0xA filters */
1069 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1070
1071 switch (pballoc) {
1072 case IXGBE_FDIR_PBALLOC_64K:
1073 /* 8k - 1 signature filters */
1074 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1075 break;
1076 case IXGBE_FDIR_PBALLOC_128K:
1077 /* 16k - 1 signature filters */
1078 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1079 break;
1080 case IXGBE_FDIR_PBALLOC_256K:
1081 /* 32k - 1 signature filters */
1082 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1083 break;
1084 default:
1085 /* bad value */
1086 return IXGBE_ERR_CONFIG;
1087 };
1088
1089 /* Move the flexible bytes to use the ethertype - shift 6 words */
1090 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1091
1092 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1093
1094 /* Prime the keys for hashing */
1095 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1096 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1097 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1098 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1099
1100 /*
1101 * Poll init-done after we write the register. Estimated times:
1102 * 10G: PBALLOC = 11b, timing is 60us
1103 * 1G: PBALLOC = 11b, timing is 600us
1104 * 100M: PBALLOC = 11b, timing is 6ms
1105 *
1106 * Multiple these timings by 4 if under full Rx load
1107 *
1108 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1109 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1110 * this might not finish in our poll time, but we can live with that
1111 * for now.
1112 */
1113 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1114 IXGBE_WRITE_FLUSH(hw);
1115 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1116 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1117 IXGBE_FDIRCTRL_INIT_DONE)
1118 break;
1119 msleep(1);
1120 }
1121 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1122 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1123
1124 return 0;
1125 }
1126
1127 /**
1128 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1129 * @hw: pointer to hardware structure
1130 * @pballoc: which mode to allocate filters with
1131 **/
1132 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1133 {
1134 u32 fdirctrl = 0;
1135 u32 pbsize;
1136 int i;
1137
1138 /*
1139 * Before enabling Flow Director, the Rx Packet Buffer size
1140 * must be reduced. The new value is the current size minus
1141 * flow director memory usage size.
1142 */
1143 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1144 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1145 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1146
1147 /*
1148 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1149 * intialized to zero for non DCB mode otherwise actual total RX PB
1150 * would be bigger than programmed and filter space would run into
1151 * the PB 0 region.
1152 */
1153 for (i = 1; i < 8; i++)
1154 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1155
1156 /* Send interrupt when 64 filters are left */
1157 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1158
1159 /* Initialize the drop queue to Rx queue 127 */
1160 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1161
1162 switch (pballoc) {
1163 case IXGBE_FDIR_PBALLOC_64K:
1164 /* 2k - 1 perfect filters */
1165 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1166 break;
1167 case IXGBE_FDIR_PBALLOC_128K:
1168 /* 4k - 1 perfect filters */
1169 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1170 break;
1171 case IXGBE_FDIR_PBALLOC_256K:
1172 /* 8k - 1 perfect filters */
1173 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1174 break;
1175 default:
1176 /* bad value */
1177 return IXGBE_ERR_CONFIG;
1178 };
1179
1180 /* Turn perfect match filtering on */
1181 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1182 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1183
1184 /* Move the flexible bytes to use the ethertype - shift 6 words */
1185 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1186
1187 /* Prime the keys for hashing */
1188 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1189 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1190 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1191 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1192
1193 /*
1194 * Poll init-done after we write the register. Estimated times:
1195 * 10G: PBALLOC = 11b, timing is 60us
1196 * 1G: PBALLOC = 11b, timing is 600us
1197 * 100M: PBALLOC = 11b, timing is 6ms
1198 *
1199 * Multiple these timings by 4 if under full Rx load
1200 *
1201 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1202 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1203 * this might not finish in our poll time, but we can live with that
1204 * for now.
1205 */
1206
1207 /* Set the maximum length per hash bucket to 0xA filters */
1208 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1209
1210 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1211 IXGBE_WRITE_FLUSH(hw);
1212 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1213 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1214 IXGBE_FDIRCTRL_INIT_DONE)
1215 break;
1216 msleep(1);
1217 }
1218 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1219 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1220
1221 return 0;
1222 }
1223
1224
1225 /**
1226 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1227 * @stream: input bitstream to compute the hash on
1228 * @key: 32-bit hash key
1229 **/
1230 static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1231 u32 key)
1232 {
1233 /*
1234 * The algorithm is as follows:
1235 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1236 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1237 * and A[n] x B[n] is bitwise AND between same length strings
1238 *
1239 * K[n] is 16 bits, defined as:
1240 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1241 * for n modulo 32 < 15, K[n] =
1242 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1243 *
1244 * S[n] is 16 bits, defined as:
1245 * for n >= 15, S[n] = S[n:n - 15]
1246 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1247 *
1248 * To simplify for programming, the algorithm is implemented
1249 * in software this way:
1250 *
1251 * Key[31:0], Stream[335:0]
1252 *
1253 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1254 * int_key[350:0] = tmp_key[351:1]
1255 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1256 *
1257 * hash[15:0] = 0;
1258 * for (i = 0; i < 351; i++) {
1259 * if (int_key[i])
1260 * hash ^= int_stream[(i + 15):i];
1261 * }
1262 */
1263
1264 union {
1265 u64 fill[6];
1266 u32 key[11];
1267 u8 key_stream[44];
1268 } tmp_key;
1269
1270 u8 *stream = (u8 *)atr_input;
1271 u8 int_key[44]; /* upper-most bit unused */
1272 u8 hash_str[46]; /* upper-most 2 bits unused */
1273 u16 hash_result = 0;
1274 int i, j, k, h;
1275
1276 /*
1277 * Initialize the fill member to prevent warnings
1278 * on some compilers
1279 */
1280 tmp_key.fill[0] = 0;
1281
1282 /* First load the temporary key stream */
1283 for (i = 0; i < 6; i++) {
1284 u64 fillkey = ((u64)key << 32) | key;
1285 tmp_key.fill[i] = fillkey;
1286 }
1287
1288 /*
1289 * Set the interim key for the hashing. Bit 352 is unused, so we must
1290 * shift and compensate when building the key.
1291 */
1292
1293 int_key[0] = tmp_key.key_stream[0] >> 1;
1294 for (i = 1, j = 0; i < 44; i++) {
1295 unsigned int this_key = tmp_key.key_stream[j] << 7;
1296 j++;
1297 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1298 }
1299
1300 /*
1301 * Set the interim bit string for the hashing. Bits 368 and 367 are
1302 * unused, so shift and compensate when building the string.
1303 */
1304 hash_str[0] = (stream[40] & 0x7f) >> 1;
1305 for (i = 1, j = 40; i < 46; i++) {
1306 unsigned int this_str = stream[j] << 7;
1307 j++;
1308 if (j > 41)
1309 j = 0;
1310 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1311 }
1312
1313 /*
1314 * Now compute the hash. i is the index into hash_str, j is into our
1315 * key stream, k is counting the number of bits, and h interates within
1316 * each byte.
1317 */
1318 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1319 for (h = 0; h < 8 && k < 351; h++, k++) {
1320 if (int_key[j] & (1 << h)) {
1321 /*
1322 * Key bit is set, XOR in the current 16-bit
1323 * string. Example of processing:
1324 * h = 0,
1325 * tmp = (hash_str[i - 2] & 0 << 16) |
1326 * (hash_str[i - 1] & 0xff << 8) |
1327 * (hash_str[i] & 0xff >> 0)
1328 * So tmp = hash_str[15 + k:k], since the
1329 * i + 2 clause rolls off the 16-bit value
1330 * h = 7,
1331 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1332 * (hash_str[i - 1] & 0xff << 1) |
1333 * (hash_str[i] & 0x80 >> 7)
1334 */
1335 int tmp = (hash_str[i] >> h);
1336 tmp |= (hash_str[i - 1] << (8 - h));
1337 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1338 << (16 - h);
1339 hash_result ^= (u16)tmp;
1340 }
1341 }
1342 }
1343
1344 return hash_result;
1345 }
1346
1347 /**
1348 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1349 * @input: input stream to modify
1350 * @vlan: the VLAN id to load
1351 **/
1352 s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1353 {
1354 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1355 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1356
1357 return 0;
1358 }
1359
1360 /**
1361 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1362 * @input: input stream to modify
1363 * @src_addr: the IP address to load
1364 **/
1365 s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1366 {
1367 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1368 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1369 (src_addr >> 16) & 0xff;
1370 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1371 (src_addr >> 8) & 0xff;
1372 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1373
1374 return 0;
1375 }
1376
1377 /**
1378 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1379 * @input: input stream to modify
1380 * @dst_addr: the IP address to load
1381 **/
1382 s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1383 {
1384 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1385 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1386 (dst_addr >> 16) & 0xff;
1387 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1388 (dst_addr >> 8) & 0xff;
1389 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1390
1391 return 0;
1392 }
1393
1394 /**
1395 * ixgbe_atr_set_src_port_82599 - Sets the source port
1396 * @input: input stream to modify
1397 * @src_port: the source port to load
1398 **/
1399 s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1400 {
1401 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1402 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1403
1404 return 0;
1405 }
1406
1407 /**
1408 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1409 * @input: input stream to modify
1410 * @dst_port: the destination port to load
1411 **/
1412 s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1413 {
1414 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1415 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1416
1417 return 0;
1418 }
1419
1420 /**
1421 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1422 * @input: input stream to modify
1423 * @flex_bytes: the flexible bytes to load
1424 **/
1425 s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1426 {
1427 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1428 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1429
1430 return 0;
1431 }
1432
1433 /**
1434 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1435 * @input: input stream to modify
1436 * @l4type: the layer 4 type value to load
1437 **/
1438 s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1439 {
1440 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1441
1442 return 0;
1443 }
1444
1445 /**
1446 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1447 * @input: input stream to search
1448 * @vlan: the VLAN id to load
1449 **/
1450 static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
1451 {
1452 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1453 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1454
1455 return 0;
1456 }
1457
1458 /**
1459 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1460 * @input: input stream to search
1461 * @src_addr: the IP address to load
1462 **/
1463 static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1464 u32 *src_addr)
1465 {
1466 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1467 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1468 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1469 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1470
1471 return 0;
1472 }
1473
1474 /**
1475 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1476 * @input: input stream to search
1477 * @dst_addr: the IP address to load
1478 **/
1479 static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1480 u32 *dst_addr)
1481 {
1482 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1483 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1484 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1485 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1486
1487 return 0;
1488 }
1489
1490 /**
1491 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1492 * @input: input stream to search
1493 * @src_addr_1: the first 4 bytes of the IP address to load
1494 * @src_addr_2: the second 4 bytes of the IP address to load
1495 * @src_addr_3: the third 4 bytes of the IP address to load
1496 * @src_addr_4: the fourth 4 bytes of the IP address to load
1497 **/
1498 static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1499 u32 *src_addr_1, u32 *src_addr_2,
1500 u32 *src_addr_3, u32 *src_addr_4)
1501 {
1502 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1503 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1504 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1505 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1506
1507 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1508 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1509 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1510 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1511
1512 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1513 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1514 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1515 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1516
1517 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1518 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1519 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1520 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1521
1522 return 0;
1523 }
1524
1525 /**
1526 * ixgbe_atr_get_src_port_82599 - Gets the source port
1527 * @input: input stream to modify
1528 * @src_port: the source port to load
1529 *
1530 * Even though the input is given in big-endian, the FDIRPORT registers
1531 * expect the ports to be programmed in little-endian. Hence the need to swap
1532 * endianness when retrieving the data. This can be confusing since the
1533 * internal hash engine expects it to be big-endian.
1534 **/
1535 static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1536 u16 *src_port)
1537 {
1538 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1539 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1540
1541 return 0;
1542 }
1543
1544 /**
1545 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1546 * @input: input stream to modify
1547 * @dst_port: the destination port to load
1548 *
1549 * Even though the input is given in big-endian, the FDIRPORT registers
1550 * expect the ports to be programmed in little-endian. Hence the need to swap
1551 * endianness when retrieving the data. This can be confusing since the
1552 * internal hash engine expects it to be big-endian.
1553 **/
1554 static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1555 u16 *dst_port)
1556 {
1557 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1558 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1559
1560 return 0;
1561 }
1562
1563 /**
1564 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1565 * @input: input stream to modify
1566 * @flex_bytes: the flexible bytes to load
1567 **/
1568 static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1569 u16 *flex_byte)
1570 {
1571 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1572 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1573
1574 return 0;
1575 }
1576
1577 /**
1578 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1579 * @input: input stream to modify
1580 * @l4type: the layer 4 type value to load
1581 **/
1582 static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
1583 u8 *l4type)
1584 {
1585 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
1586
1587 return 0;
1588 }
1589
1590 /**
1591 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1592 * @hw: pointer to hardware structure
1593 * @stream: input bitstream
1594 * @queue: queue index to direct traffic to
1595 **/
1596 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1597 struct ixgbe_atr_input *input,
1598 u8 queue)
1599 {
1600 u64 fdirhashcmd;
1601 u64 fdircmd;
1602 u32 fdirhash;
1603 u16 bucket_hash, sig_hash;
1604 u8 l4type;
1605
1606 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1607 IXGBE_ATR_BUCKET_HASH_KEY);
1608
1609 /* bucket_hash is only 15 bits */
1610 bucket_hash &= IXGBE_ATR_HASH_MASK;
1611
1612 sig_hash = ixgbe_atr_compute_hash_82599(input,
1613 IXGBE_ATR_SIGNATURE_HASH_KEY);
1614
1615 /* Get the l4type in order to program FDIRCMD properly */
1616 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1617 ixgbe_atr_get_l4type_82599(input, &l4type);
1618
1619 /*
1620 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1621 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1622 */
1623 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1624
1625 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1626 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
1627
1628 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1629 case IXGBE_ATR_L4TYPE_TCP:
1630 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1631 break;
1632 case IXGBE_ATR_L4TYPE_UDP:
1633 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1634 break;
1635 case IXGBE_ATR_L4TYPE_SCTP:
1636 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1637 break;
1638 default:
1639 hw_dbg(hw, "Error on l4type input\n");
1640 return IXGBE_ERR_CONFIG;
1641 }
1642
1643 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
1644 fdircmd |= IXGBE_FDIRCMD_IPV6;
1645
1646 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
1647 fdirhashcmd = ((fdircmd << 32) | fdirhash);
1648
1649 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1650
1651 return 0;
1652 }
1653
1654 /**
1655 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1656 * @hw: pointer to hardware structure
1657 * @input: input bitstream
1658 * @input_masks: bitwise masks for relevant fields
1659 * @soft_id: software index into the silicon hash tables for filter storage
1660 * @queue: queue index to direct traffic to
1661 *
1662 * Note that the caller to this function must lock before calling, since the
1663 * hardware writes must be protected from one another.
1664 **/
1665 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1666 struct ixgbe_atr_input *input,
1667 struct ixgbe_atr_input_masks *input_masks,
1668 u16 soft_id, u8 queue)
1669 {
1670 u32 fdircmd = 0;
1671 u32 fdirhash;
1672 u32 src_ipv4 = 0, dst_ipv4 = 0;
1673 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
1674 u16 src_port, dst_port, vlan_id, flex_bytes;
1675 u16 bucket_hash;
1676 u8 l4type;
1677 u8 fdirm = 0;
1678
1679 /* Get our input values */
1680 ixgbe_atr_get_l4type_82599(input, &l4type);
1681
1682 /*
1683 * Check l4type formatting, and bail out before we touch the hardware
1684 * if there's a configuration issue
1685 */
1686 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1687 case IXGBE_ATR_L4TYPE_TCP:
1688 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1689 break;
1690 case IXGBE_ATR_L4TYPE_UDP:
1691 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1692 break;
1693 case IXGBE_ATR_L4TYPE_SCTP:
1694 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1695 break;
1696 default:
1697 hw_dbg(hw, "Error on l4type input\n");
1698 return IXGBE_ERR_CONFIG;
1699 }
1700
1701 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1702 IXGBE_ATR_BUCKET_HASH_KEY);
1703
1704 /* bucket_hash is only 15 bits */
1705 bucket_hash &= IXGBE_ATR_HASH_MASK;
1706
1707 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
1708 ixgbe_atr_get_src_port_82599(input, &src_port);
1709 ixgbe_atr_get_dst_port_82599(input, &dst_port);
1710 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
1711
1712 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1713
1714 /* Now figure out if we're IPv4 or IPv6 */
1715 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
1716 /* IPv6 */
1717 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
1718 &src_ipv6_3, &src_ipv6_4);
1719
1720 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
1721 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
1722 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
1723 /* The last 4 bytes is the same register as IPv4 */
1724 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
1725
1726 fdircmd |= IXGBE_FDIRCMD_IPV6;
1727 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
1728 } else {
1729 /* IPv4 */
1730 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
1731 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
1732 }
1733
1734 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
1735 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
1736
1737 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
1738 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
1739 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
1740 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
1741
1742 /*
1743 * Program the relevant mask registers. L4type cannot be
1744 * masked out in this implementation.
1745 *
1746 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1747 * point in time.
1748 */
1749 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
1750 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
1751
1752 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1753 case IXGBE_ATR_L4TYPE_TCP:
1754 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, input_masks->src_port_mask);
1755 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1756 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
1757 (input_masks->dst_port_mask << 16)));
1758 break;
1759 case IXGBE_ATR_L4TYPE_UDP:
1760 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, input_masks->src_port_mask);
1761 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1762 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
1763 (input_masks->src_port_mask << 16)));
1764 break;
1765 default:
1766 /* this already would have failed above */
1767 break;
1768 }
1769
1770 /* Program the last mask register, FDIRM */
1771 if (input_masks->vlan_id_mask)
1772 /* Mask both VLAN and VLANP - bits 0 and 1 */
1773 fdirm |= 0x3;
1774
1775 if (input_masks->data_mask)
1776 /* Flex bytes need masking, so mask the whole thing - bit 4 */
1777 fdirm |= 0x10;
1778
1779 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1780 fdirm |= 0x24;
1781
1782 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1783
1784 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
1785 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
1786 fdircmd |= IXGBE_FDIRCMD_LAST;
1787 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
1788 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1789
1790 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1791 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1792
1793 return 0;
1794 }
1795 /**
1796 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1797 * @hw: pointer to hardware structure
1798 * @reg: analog register to read
1799 * @val: read value
1800 *
1801 * Performs read operation to Omer analog register specified.
1802 **/
1803 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1804 {
1805 u32 core_ctl;
1806
1807 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1808 (reg << 8));
1809 IXGBE_WRITE_FLUSH(hw);
1810 udelay(10);
1811 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1812 *val = (u8)core_ctl;
1813
1814 return 0;
1815 }
1816
1817 /**
1818 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1819 * @hw: pointer to hardware structure
1820 * @reg: atlas register to write
1821 * @val: value to write
1822 *
1823 * Performs write operation to Omer analog register specified.
1824 **/
1825 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1826 {
1827 u32 core_ctl;
1828
1829 core_ctl = (reg << 8) | val;
1830 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1831 IXGBE_WRITE_FLUSH(hw);
1832 udelay(10);
1833
1834 return 0;
1835 }
1836
1837 /**
1838 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1839 * @hw: pointer to hardware structure
1840 *
1841 * Starts the hardware using the generic start_hw function.
1842 * Then performs device-specific:
1843 * Clears the rate limiter registers.
1844 **/
1845 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1846 {
1847 u32 q_num;
1848 s32 ret_val;
1849
1850 ret_val = ixgbe_start_hw_generic(hw);
1851
1852 /* Clear the rate limiters */
1853 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1854 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1855 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1856 }
1857 IXGBE_WRITE_FLUSH(hw);
1858
1859 /* We need to run link autotry after the driver loads */
1860 hw->mac.autotry_restart = true;
1861
1862 if (ret_val == 0)
1863 ret_val = ixgbe_verify_fw_version_82599(hw);
1864
1865 return ret_val;
1866 }
1867
1868 /**
1869 * ixgbe_identify_phy_82599 - Get physical layer module
1870 * @hw: pointer to hardware structure
1871 *
1872 * Determines the physical layer module found on the current adapter.
1873 **/
1874 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1875 {
1876 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1877 status = ixgbe_identify_phy_generic(hw);
1878 if (status != 0)
1879 status = ixgbe_identify_sfp_module_generic(hw);
1880 return status;
1881 }
1882
1883 /**
1884 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1885 * @hw: pointer to hardware structure
1886 *
1887 * Determines physical layer capabilities of the current configuration.
1888 **/
1889 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1890 {
1891 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1892 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1893 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1894 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1895 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1896 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1897 u16 ext_ability = 0;
1898 u8 comp_codes_10g = 0;
1899 u8 comp_codes_1g = 0;
1900
1901 hw->phy.ops.identify(hw);
1902
1903 if (hw->phy.type == ixgbe_phy_tn ||
1904 hw->phy.type == ixgbe_phy_aq ||
1905 hw->phy.type == ixgbe_phy_cu_unknown) {
1906 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1907 &ext_ability);
1908 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1909 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1910 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1911 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1912 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1913 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1914 goto out;
1915 }
1916
1917 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1918 case IXGBE_AUTOC_LMS_1G_AN:
1919 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1920 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1921 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1922 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1923 goto out;
1924 } else
1925 /* SFI mode so read SFP module */
1926 goto sfp_check;
1927 break;
1928 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1929 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1930 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1931 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1932 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1933 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1934 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1935 goto out;
1936 break;
1937 case IXGBE_AUTOC_LMS_10G_SERIAL:
1938 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1939 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1940 goto out;
1941 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1942 goto sfp_check;
1943 break;
1944 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1945 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1946 if (autoc & IXGBE_AUTOC_KX_SUPP)
1947 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1948 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1949 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1950 if (autoc & IXGBE_AUTOC_KR_SUPP)
1951 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1952 goto out;
1953 break;
1954 default:
1955 goto out;
1956 break;
1957 }
1958
1959 sfp_check:
1960 /* SFP check must be done last since DA modules are sometimes used to
1961 * test KR mode - we need to id KR mode correctly before SFP module.
1962 * Call identify_sfp because the pluggable module may have changed */
1963 hw->phy.ops.identify_sfp(hw);
1964 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1965 goto out;
1966
1967 switch (hw->phy.type) {
1968 case ixgbe_phy_sfp_passive_tyco:
1969 case ixgbe_phy_sfp_passive_unknown:
1970 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1971 break;
1972 case ixgbe_phy_sfp_ftl_active:
1973 case ixgbe_phy_sfp_active_unknown:
1974 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1975 break;
1976 case ixgbe_phy_sfp_avago:
1977 case ixgbe_phy_sfp_ftl:
1978 case ixgbe_phy_sfp_intel:
1979 case ixgbe_phy_sfp_unknown:
1980 hw->phy.ops.read_i2c_eeprom(hw,
1981 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1982 hw->phy.ops.read_i2c_eeprom(hw,
1983 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1984 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1985 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1986 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1987 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1988 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1989 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1990 break;
1991 default:
1992 break;
1993 }
1994
1995 out:
1996 return physical_layer;
1997 }
1998
1999 /**
2000 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2001 * @hw: pointer to hardware structure
2002 * @regval: register value to write to RXCTRL
2003 *
2004 * Enables the Rx DMA unit for 82599
2005 **/
2006 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2007 {
2008 #define IXGBE_MAX_SECRX_POLL 30
2009 int i;
2010 int secrxreg;
2011
2012 /*
2013 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2014 * If traffic is incoming before we enable the Rx unit, it could hang
2015 * the Rx DMA unit. Therefore, make sure the security engine is
2016 * completely disabled prior to enabling the Rx unit.
2017 */
2018 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2019 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2020 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2021 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2022 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2023 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2024 break;
2025 else
2026 udelay(10);
2027 }
2028
2029 /* For informational purposes only */
2030 if (i >= IXGBE_MAX_SECRX_POLL)
2031 hw_dbg(hw, "Rx unit being enabled before security "
2032 "path fully disabled. Continuing with init.\n");
2033
2034 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2035 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2036 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2037 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2038 IXGBE_WRITE_FLUSH(hw);
2039
2040 return 0;
2041 }
2042
2043 /**
2044 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2045 * @hw: pointer to hardware structure
2046 * @device_caps: the EEPROM word with the extra device capabilities
2047 *
2048 * This function will read the EEPROM location for the device capabilities,
2049 * and return the word through device_caps.
2050 **/
2051 static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
2052 {
2053 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2054
2055 return 0;
2056 }
2057
2058 /**
2059 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2060 * @hw: pointer to hardware structure
2061 *
2062 * Verifies that installed the firmware version is 0.6 or higher
2063 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2064 *
2065 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2066 * if the FW version is not supported.
2067 **/
2068 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2069 {
2070 s32 status = IXGBE_ERR_EEPROM_VERSION;
2071 u16 fw_offset, fw_ptp_cfg_offset;
2072 u16 fw_version = 0;
2073
2074 /* firmware check is only necessary for SFI devices */
2075 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2076 status = 0;
2077 goto fw_version_out;
2078 }
2079
2080 /* get the offset to the Firmware Module block */
2081 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2082
2083 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2084 goto fw_version_out;
2085
2086 /* get the offset to the Pass Through Patch Configuration block */
2087 hw->eeprom.ops.read(hw, (fw_offset +
2088 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2089 &fw_ptp_cfg_offset);
2090
2091 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2092 goto fw_version_out;
2093
2094 /* get the firmware version */
2095 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2096 IXGBE_FW_PATCH_VERSION_4),
2097 &fw_version);
2098
2099 if (fw_version > 0x5)
2100 status = 0;
2101
2102 fw_version_out:
2103 return status;
2104 }
2105
2106 static struct ixgbe_mac_operations mac_ops_82599 = {
2107 .init_hw = &ixgbe_init_hw_generic,
2108 .reset_hw = &ixgbe_reset_hw_82599,
2109 .start_hw = &ixgbe_start_hw_82599,
2110 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2111 .get_media_type = &ixgbe_get_media_type_82599,
2112 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2113 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2114 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2115 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2116 .get_device_caps = &ixgbe_get_device_caps_82599,
2117 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2118 .stop_adapter = &ixgbe_stop_adapter_generic,
2119 .get_bus_info = &ixgbe_get_bus_info_generic,
2120 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2121 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2122 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2123 .setup_link = &ixgbe_setup_mac_link_82599,
2124 .check_link = &ixgbe_check_mac_link_generic,
2125 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2126 .led_on = &ixgbe_led_on_generic,
2127 .led_off = &ixgbe_led_off_generic,
2128 .blink_led_start = &ixgbe_blink_led_start_generic,
2129 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2130 .set_rar = &ixgbe_set_rar_generic,
2131 .clear_rar = &ixgbe_clear_rar_generic,
2132 .set_vmdq = &ixgbe_set_vmdq_generic,
2133 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2134 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2135 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2136 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2137 .enable_mc = &ixgbe_enable_mc_generic,
2138 .disable_mc = &ixgbe_disable_mc_generic,
2139 .clear_vfta = &ixgbe_clear_vfta_generic,
2140 .set_vfta = &ixgbe_set_vfta_generic,
2141 .fc_enable = &ixgbe_fc_enable_generic,
2142 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2143 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2144 };
2145
2146 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2147 .init_params = &ixgbe_init_eeprom_params_generic,
2148 .read = &ixgbe_read_eerd_generic,
2149 .write = &ixgbe_write_eeprom_generic,
2150 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2151 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2152 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2153 };
2154
2155 static struct ixgbe_phy_operations phy_ops_82599 = {
2156 .identify = &ixgbe_identify_phy_82599,
2157 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2158 .init = &ixgbe_init_phy_ops_82599,
2159 .reset = &ixgbe_reset_phy_generic,
2160 .read_reg = &ixgbe_read_phy_reg_generic,
2161 .write_reg = &ixgbe_write_phy_reg_generic,
2162 .setup_link = &ixgbe_setup_phy_link_generic,
2163 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2164 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2165 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2166 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2167 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2168 .check_overtemp = &ixgbe_tn_check_overtemp,
2169 };
2170
2171 struct ixgbe_info ixgbe_82599_info = {
2172 .mac = ixgbe_mac_82599EB,
2173 .get_invariants = &ixgbe_get_invariants_82599,
2174 .mac_ops = &mac_ops_82599,
2175 .eeprom_ops = &eeprom_ops_82599,
2176 .phy_ops = &phy_ops_82599,
2177 .mbx_ops = &mbx_ops_generic,
2178 };
kernel source for telekom puls (alcatel/mediatek)