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ixgbe: fix namespacecheck issue
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_82599.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
35
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41
42 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
43 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg,
52 bool autoneg_wait_to_complete);
53 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed,
57 bool autoneg,
58 bool autoneg_wait_to_complete);
59 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed speed,
61 bool autoneg,
62 bool autoneg_wait_to_complete);
63 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
64
65 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
66 {
67 struct ixgbe_mac_info *mac = &hw->mac;
68
69 /* enable the laser control functions for SFP+ fiber */
70 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
71 mac->ops.disable_tx_laser =
72 &ixgbe_disable_tx_laser_multispeed_fiber;
73 mac->ops.enable_tx_laser =
74 &ixgbe_enable_tx_laser_multispeed_fiber;
75 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
76 } else {
77 mac->ops.disable_tx_laser = NULL;
78 mac->ops.enable_tx_laser = NULL;
79 mac->ops.flap_tx_laser = NULL;
80 }
81
82 if (hw->phy.multispeed_fiber) {
83 /* Set up dual speed SFP+ support */
84 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
85 } else {
86 if ((mac->ops.get_media_type(hw) ==
87 ixgbe_media_type_backplane) &&
88 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
89 hw->phy.smart_speed == ixgbe_smart_speed_on))
90 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
91 else
92 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
93 }
94 }
95
96 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
97 {
98 s32 ret_val = 0;
99 u32 reg_anlp1 = 0;
100 u32 i = 0;
101 u16 list_offset, data_offset, data_value;
102
103 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
104 ixgbe_init_mac_link_ops_82599(hw);
105
106 hw->phy.ops.reset = NULL;
107
108 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
109 &data_offset);
110
111 if (ret_val != 0)
112 goto setup_sfp_out;
113
114 /* PHY config will finish before releasing the semaphore */
115 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
116 IXGBE_GSSR_MAC_CSR_SM);
117 if (ret_val != 0) {
118 ret_val = IXGBE_ERR_SWFW_SYNC;
119 goto setup_sfp_out;
120 }
121
122 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
123 while (data_value != 0xffff) {
124 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
125 IXGBE_WRITE_FLUSH(hw);
126 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
127 }
128
129 /* Release the semaphore */
130 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
131 /* Delay obtaining semaphore again to allow FW access */
132 msleep(hw->eeprom.semaphore_delay);
133
134 /* Now restart DSP by setting Restart_AN and clearing LMS */
135 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
136 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
137 IXGBE_AUTOC_AN_RESTART));
138
139 /* Wait for AN to leave state 0 */
140 for (i = 0; i < 10; i++) {
141 msleep(4);
142 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
143 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
144 break;
145 }
146 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
147 hw_dbg(hw, "sfp module setup not complete\n");
148 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
149 goto setup_sfp_out;
150 }
151
152 /* Restart DSP by setting Restart_AN and return to SFI mode */
153 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
154 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
155 IXGBE_AUTOC_AN_RESTART));
156 }
157
158 setup_sfp_out:
159 return ret_val;
160 }
161
162 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
163 {
164 struct ixgbe_mac_info *mac = &hw->mac;
165
166 ixgbe_init_mac_link_ops_82599(hw);
167
168 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
169 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
170 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
171 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
172 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
173 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
174
175 return 0;
176 }
177
178 /**
179 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
180 * @hw: pointer to hardware structure
181 *
182 * Initialize any function pointers that were not able to be
183 * set during get_invariants because the PHY/SFP type was
184 * not known. Perform the SFP init if necessary.
185 *
186 **/
187 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
188 {
189 struct ixgbe_mac_info *mac = &hw->mac;
190 struct ixgbe_phy_info *phy = &hw->phy;
191 s32 ret_val = 0;
192
193 /* Identify the PHY or SFP module */
194 ret_val = phy->ops.identify(hw);
195
196 /* Setup function pointers based on detected SFP module and speeds */
197 ixgbe_init_mac_link_ops_82599(hw);
198
199 /* If copper media, overwrite with copper function pointers */
200 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
201 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
202 mac->ops.get_link_capabilities =
203 &ixgbe_get_copper_link_capabilities_generic;
204 }
205
206 /* Set necessary function pointers based on phy type */
207 switch (hw->phy.type) {
208 case ixgbe_phy_tn:
209 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
210 phy->ops.get_firmware_version =
211 &ixgbe_get_phy_firmware_version_tnx;
212 break;
213 case ixgbe_phy_aq:
214 phy->ops.get_firmware_version =
215 &ixgbe_get_phy_firmware_version_generic;
216 break;
217 default:
218 break;
219 }
220
221 return ret_val;
222 }
223
224 /**
225 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
226 * @hw: pointer to hardware structure
227 * @speed: pointer to link speed
228 * @negotiation: true when autoneg or autotry is enabled
229 *
230 * Determines the link capabilities by reading the AUTOC register.
231 **/
232 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
233 ixgbe_link_speed *speed,
234 bool *negotiation)
235 {
236 s32 status = 0;
237 u32 autoc = 0;
238
239 /* Determine 1G link capabilities off of SFP+ type */
240 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
241 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
242 *speed = IXGBE_LINK_SPEED_1GB_FULL;
243 *negotiation = true;
244 goto out;
245 }
246
247 /*
248 * Determine link capabilities based on the stored value of AUTOC,
249 * which represents EEPROM defaults. If AUTOC value has not been
250 * stored, use the current register value.
251 */
252 if (hw->mac.orig_link_settings_stored)
253 autoc = hw->mac.orig_autoc;
254 else
255 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
256
257 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
258 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
259 *speed = IXGBE_LINK_SPEED_1GB_FULL;
260 *negotiation = false;
261 break;
262
263 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
264 *speed = IXGBE_LINK_SPEED_10GB_FULL;
265 *negotiation = false;
266 break;
267
268 case IXGBE_AUTOC_LMS_1G_AN:
269 *speed = IXGBE_LINK_SPEED_1GB_FULL;
270 *negotiation = true;
271 break;
272
273 case IXGBE_AUTOC_LMS_10G_SERIAL:
274 *speed = IXGBE_LINK_SPEED_10GB_FULL;
275 *negotiation = false;
276 break;
277
278 case IXGBE_AUTOC_LMS_KX4_KX_KR:
279 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
280 *speed = IXGBE_LINK_SPEED_UNKNOWN;
281 if (autoc & IXGBE_AUTOC_KR_SUPP)
282 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
283 if (autoc & IXGBE_AUTOC_KX4_SUPP)
284 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
285 if (autoc & IXGBE_AUTOC_KX_SUPP)
286 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
287 *negotiation = true;
288 break;
289
290 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
291 *speed = IXGBE_LINK_SPEED_100_FULL;
292 if (autoc & IXGBE_AUTOC_KR_SUPP)
293 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
294 if (autoc & IXGBE_AUTOC_KX4_SUPP)
295 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
296 if (autoc & IXGBE_AUTOC_KX_SUPP)
297 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
298 *negotiation = true;
299 break;
300
301 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
302 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
303 *negotiation = false;
304 break;
305
306 default:
307 status = IXGBE_ERR_LINK_SETUP;
308 goto out;
309 break;
310 }
311
312 if (hw->phy.multispeed_fiber) {
313 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
314 IXGBE_LINK_SPEED_1GB_FULL;
315 *negotiation = true;
316 }
317
318 out:
319 return status;
320 }
321
322 /**
323 * ixgbe_get_media_type_82599 - Get media type
324 * @hw: pointer to hardware structure
325 *
326 * Returns the media type (fiber, copper, backplane)
327 **/
328 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
329 {
330 enum ixgbe_media_type media_type;
331
332 /* Detect if there is a copper PHY attached. */
333 switch (hw->phy.type) {
334 case ixgbe_phy_cu_unknown:
335 case ixgbe_phy_tn:
336 case ixgbe_phy_aq:
337 media_type = ixgbe_media_type_copper;
338 goto out;
339 default:
340 break;
341 }
342
343 switch (hw->device_id) {
344 case IXGBE_DEV_ID_82599_KX4:
345 case IXGBE_DEV_ID_82599_KX4_MEZZ:
346 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
347 case IXGBE_DEV_ID_82599_KR:
348 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
349 case IXGBE_DEV_ID_82599_XAUI_LOM:
350 /* Default device ID is mezzanine card KX/KX4 */
351 media_type = ixgbe_media_type_backplane;
352 break;
353 case IXGBE_DEV_ID_82599_SFP:
354 case IXGBE_DEV_ID_82599_SFP_FCOE:
355 case IXGBE_DEV_ID_82599_SFP_EM:
356 media_type = ixgbe_media_type_fiber;
357 break;
358 case IXGBE_DEV_ID_82599_CX4:
359 media_type = ixgbe_media_type_cx4;
360 break;
361 case IXGBE_DEV_ID_82599_T3_LOM:
362 media_type = ixgbe_media_type_copper;
363 break;
364 default:
365 media_type = ixgbe_media_type_unknown;
366 break;
367 }
368 out:
369 return media_type;
370 }
371
372 /**
373 * ixgbe_start_mac_link_82599 - Setup MAC link settings
374 * @hw: pointer to hardware structure
375 * @autoneg_wait_to_complete: true when waiting for completion is needed
376 *
377 * Configures link settings based on values in the ixgbe_hw struct.
378 * Restarts the link. Performs autonegotiation if needed.
379 **/
380 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
381 bool autoneg_wait_to_complete)
382 {
383 u32 autoc_reg;
384 u32 links_reg;
385 u32 i;
386 s32 status = 0;
387
388 /* Restart link */
389 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
390 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
391 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
392
393 /* Only poll for autoneg to complete if specified to do so */
394 if (autoneg_wait_to_complete) {
395 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
396 IXGBE_AUTOC_LMS_KX4_KX_KR ||
397 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
398 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
399 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
400 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
401 links_reg = 0; /* Just in case Autoneg time = 0 */
402 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
403 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
404 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
405 break;
406 msleep(100);
407 }
408 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
409 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
410 hw_dbg(hw, "Autoneg did not complete.\n");
411 }
412 }
413 }
414
415 /* Add delay to filter out noises during initial link setup */
416 msleep(50);
417
418 return status;
419 }
420
421 /**
422 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
423 * @hw: pointer to hardware structure
424 *
425 * The base drivers may require better control over SFP+ module
426 * PHY states. This includes selectively shutting down the Tx
427 * laser on the PHY, effectively halting physical link.
428 **/
429 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
430 {
431 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
432
433 /* Disable tx laser; allow 100us to go dark per spec */
434 esdp_reg |= IXGBE_ESDP_SDP3;
435 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
436 IXGBE_WRITE_FLUSH(hw);
437 udelay(100);
438 }
439
440 /**
441 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
442 * @hw: pointer to hardware structure
443 *
444 * The base drivers may require better control over SFP+ module
445 * PHY states. This includes selectively turning on the Tx
446 * laser on the PHY, effectively starting physical link.
447 **/
448 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
449 {
450 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
451
452 /* Enable tx laser; allow 100ms to light up */
453 esdp_reg &= ~IXGBE_ESDP_SDP3;
454 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
455 IXGBE_WRITE_FLUSH(hw);
456 msleep(100);
457 }
458
459 /**
460 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
461 * @hw: pointer to hardware structure
462 *
463 * When the driver changes the link speeds that it can support,
464 * it sets autotry_restart to true to indicate that we need to
465 * initiate a new autotry session with the link partner. To do
466 * so, we set the speed then disable and re-enable the tx laser, to
467 * alert the link partner that it also needs to restart autotry on its
468 * end. This is consistent with true clause 37 autoneg, which also
469 * involves a loss of signal.
470 **/
471 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
472 {
473 if (hw->mac.autotry_restart) {
474 ixgbe_disable_tx_laser_multispeed_fiber(hw);
475 ixgbe_enable_tx_laser_multispeed_fiber(hw);
476 hw->mac.autotry_restart = false;
477 }
478 }
479
480 /**
481 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
482 * @hw: pointer to hardware structure
483 * @speed: new link speed
484 * @autoneg: true if autonegotiation enabled
485 * @autoneg_wait_to_complete: true when waiting for completion is needed
486 *
487 * Set the link speed in the AUTOC register and restarts link.
488 **/
489 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
490 ixgbe_link_speed speed,
491 bool autoneg,
492 bool autoneg_wait_to_complete)
493 {
494 s32 status = 0;
495 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
496 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
497 u32 speedcnt = 0;
498 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
499 u32 i = 0;
500 bool link_up = false;
501 bool negotiation;
502
503 /* Mask off requested but non-supported speeds */
504 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
505 &negotiation);
506 if (status != 0)
507 return status;
508
509 speed &= link_speed;
510
511 /*
512 * Try each speed one by one, highest priority first. We do this in
513 * software because 10gb fiber doesn't support speed autonegotiation.
514 */
515 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
516 speedcnt++;
517 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
518
519 /* If we already have link at this speed, just jump out */
520 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
521 false);
522 if (status != 0)
523 return status;
524
525 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
526 goto out;
527
528 /* Set the module link speed */
529 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
530 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
531 IXGBE_WRITE_FLUSH(hw);
532
533 /* Allow module to change analog characteristics (1G->10G) */
534 msleep(40);
535
536 status = ixgbe_setup_mac_link_82599(hw,
537 IXGBE_LINK_SPEED_10GB_FULL,
538 autoneg,
539 autoneg_wait_to_complete);
540 if (status != 0)
541 return status;
542
543 /* Flap the tx laser if it has not already been done */
544 hw->mac.ops.flap_tx_laser(hw);
545
546 /*
547 * Wait for the controller to acquire link. Per IEEE 802.3ap,
548 * Section 73.10.2, we may have to wait up to 500ms if KR is
549 * attempted. 82599 uses the same timing for 10g SFI.
550 */
551 for (i = 0; i < 5; i++) {
552 /* Wait for the link partner to also set speed */
553 msleep(100);
554
555 /* If we have link, just jump out */
556 status = hw->mac.ops.check_link(hw, &link_speed,
557 &link_up, false);
558 if (status != 0)
559 return status;
560
561 if (link_up)
562 goto out;
563 }
564 }
565
566 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
567 speedcnt++;
568 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
569 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
570
571 /* If we already have link at this speed, just jump out */
572 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
573 false);
574 if (status != 0)
575 return status;
576
577 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
578 goto out;
579
580 /* Set the module link speed */
581 esdp_reg &= ~IXGBE_ESDP_SDP5;
582 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
583 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
584 IXGBE_WRITE_FLUSH(hw);
585
586 /* Allow module to change analog characteristics (10G->1G) */
587 msleep(40);
588
589 status = ixgbe_setup_mac_link_82599(hw,
590 IXGBE_LINK_SPEED_1GB_FULL,
591 autoneg,
592 autoneg_wait_to_complete);
593 if (status != 0)
594 return status;
595
596 /* Flap the tx laser if it has not already been done */
597 hw->mac.ops.flap_tx_laser(hw);
598
599 /* Wait for the link partner to also set speed */
600 msleep(100);
601
602 /* If we have link, just jump out */
603 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
604 false);
605 if (status != 0)
606 return status;
607
608 if (link_up)
609 goto out;
610 }
611
612 /*
613 * We didn't get link. Configure back to the highest speed we tried,
614 * (if there was more than one). We call ourselves back with just the
615 * single highest speed that the user requested.
616 */
617 if (speedcnt > 1)
618 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
619 highest_link_speed,
620 autoneg,
621 autoneg_wait_to_complete);
622
623 out:
624 /* Set autoneg_advertised value based on input link speed */
625 hw->phy.autoneg_advertised = 0;
626
627 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
628 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
629
630 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
631 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
632
633 return status;
634 }
635
636 /**
637 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
638 * @hw: pointer to hardware structure
639 * @speed: new link speed
640 * @autoneg: true if autonegotiation enabled
641 * @autoneg_wait_to_complete: true when waiting for completion is needed
642 *
643 * Implements the Intel SmartSpeed algorithm.
644 **/
645 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
646 ixgbe_link_speed speed, bool autoneg,
647 bool autoneg_wait_to_complete)
648 {
649 s32 status = 0;
650 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
651 s32 i, j;
652 bool link_up = false;
653 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
654
655 /* Set autoneg_advertised value based on input link speed */
656 hw->phy.autoneg_advertised = 0;
657
658 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
659 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
660
661 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
662 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
663
664 if (speed & IXGBE_LINK_SPEED_100_FULL)
665 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
666
667 /*
668 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
669 * autoneg advertisement if link is unable to be established at the
670 * highest negotiated rate. This can sometimes happen due to integrity
671 * issues with the physical media connection.
672 */
673
674 /* First, try to get link with full advertisement */
675 hw->phy.smart_speed_active = false;
676 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
677 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
678 autoneg_wait_to_complete);
679 if (status != 0)
680 goto out;
681
682 /*
683 * Wait for the controller to acquire link. Per IEEE 802.3ap,
684 * Section 73.10.2, we may have to wait up to 500ms if KR is
685 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
686 * Table 9 in the AN MAS.
687 */
688 for (i = 0; i < 5; i++) {
689 mdelay(100);
690
691 /* If we have link, just jump out */
692 status = hw->mac.ops.check_link(hw, &link_speed,
693 &link_up, false);
694 if (status != 0)
695 goto out;
696
697 if (link_up)
698 goto out;
699 }
700 }
701
702 /*
703 * We didn't get link. If we advertised KR plus one of KX4/KX
704 * (or BX4/BX), then disable KR and try again.
705 */
706 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
707 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
708 goto out;
709
710 /* Turn SmartSpeed on to disable KR support */
711 hw->phy.smart_speed_active = true;
712 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
713 autoneg_wait_to_complete);
714 if (status != 0)
715 goto out;
716
717 /*
718 * Wait for the controller to acquire link. 600ms will allow for
719 * the AN link_fail_inhibit_timer as well for multiple cycles of
720 * parallel detect, both 10g and 1g. This allows for the maximum
721 * connect attempts as defined in the AN MAS table 73-7.
722 */
723 for (i = 0; i < 6; i++) {
724 mdelay(100);
725
726 /* If we have link, just jump out */
727 status = hw->mac.ops.check_link(hw, &link_speed,
728 &link_up, false);
729 if (status != 0)
730 goto out;
731
732 if (link_up)
733 goto out;
734 }
735
736 /* We didn't get link. Turn SmartSpeed back off. */
737 hw->phy.smart_speed_active = false;
738 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
739 autoneg_wait_to_complete);
740
741 out:
742 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
743 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
744 "the maximum advertised\n");
745 return status;
746 }
747
748 /**
749 * ixgbe_setup_mac_link_82599 - Set MAC link speed
750 * @hw: pointer to hardware structure
751 * @speed: new link speed
752 * @autoneg: true if autonegotiation enabled
753 * @autoneg_wait_to_complete: true when waiting for completion is needed
754 *
755 * Set the link speed in the AUTOC register and restarts link.
756 **/
757 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
758 ixgbe_link_speed speed, bool autoneg,
759 bool autoneg_wait_to_complete)
760 {
761 s32 status = 0;
762 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
763 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
764 u32 start_autoc = autoc;
765 u32 orig_autoc = 0;
766 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
767 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
768 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
769 u32 links_reg;
770 u32 i;
771 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
772
773 /* Check to see if speed passed in is supported. */
774 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
775 if (status != 0)
776 goto out;
777
778 speed &= link_capabilities;
779
780 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
781 status = IXGBE_ERR_LINK_SETUP;
782 goto out;
783 }
784
785 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
786 if (hw->mac.orig_link_settings_stored)
787 orig_autoc = hw->mac.orig_autoc;
788 else
789 orig_autoc = autoc;
790
791 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
792 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
793 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
794 /* Set KX4/KX/KR support according to speed requested */
795 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
796 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
797 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
798 autoc |= IXGBE_AUTOC_KX4_SUPP;
799 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
800 (hw->phy.smart_speed_active == false))
801 autoc |= IXGBE_AUTOC_KR_SUPP;
802 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
803 autoc |= IXGBE_AUTOC_KX_SUPP;
804 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
805 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
806 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
807 /* Switch from 1G SFI to 10G SFI if requested */
808 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
809 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
810 autoc &= ~IXGBE_AUTOC_LMS_MASK;
811 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
812 }
813 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
814 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
815 /* Switch from 10G SFI to 1G SFI if requested */
816 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
817 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
818 autoc &= ~IXGBE_AUTOC_LMS_MASK;
819 if (autoneg)
820 autoc |= IXGBE_AUTOC_LMS_1G_AN;
821 else
822 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
823 }
824 }
825
826 if (autoc != start_autoc) {
827 /* Restart link */
828 autoc |= IXGBE_AUTOC_AN_RESTART;
829 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
830
831 /* Only poll for autoneg to complete if specified to do so */
832 if (autoneg_wait_to_complete) {
833 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
834 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
835 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
836 links_reg = 0; /*Just in case Autoneg time=0*/
837 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
838 links_reg =
839 IXGBE_READ_REG(hw, IXGBE_LINKS);
840 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
841 break;
842 msleep(100);
843 }
844 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
845 status =
846 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
847 hw_dbg(hw, "Autoneg did not "
848 "complete.\n");
849 }
850 }
851 }
852
853 /* Add delay to filter out noises during initial link setup */
854 msleep(50);
855 }
856
857 out:
858 return status;
859 }
860
861 /**
862 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
863 * @hw: pointer to hardware structure
864 * @speed: new link speed
865 * @autoneg: true if autonegotiation enabled
866 * @autoneg_wait_to_complete: true if waiting is needed to complete
867 *
868 * Restarts link on PHY and MAC based on settings passed in.
869 **/
870 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
871 ixgbe_link_speed speed,
872 bool autoneg,
873 bool autoneg_wait_to_complete)
874 {
875 s32 status;
876
877 /* Setup the PHY according to input speed */
878 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
879 autoneg_wait_to_complete);
880 /* Set up MAC */
881 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
882
883 return status;
884 }
885
886 /**
887 * ixgbe_reset_hw_82599 - Perform hardware reset
888 * @hw: pointer to hardware structure
889 *
890 * Resets the hardware by resetting the transmit and receive units, masks
891 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
892 * reset.
893 **/
894 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
895 {
896 s32 status = 0;
897 u32 ctrl;
898 u32 i;
899 u32 autoc;
900 u32 autoc2;
901
902 /* Call adapter stop to disable tx/rx and clear interrupts */
903 hw->mac.ops.stop_adapter(hw);
904
905 /* PHY ops must be identified and initialized prior to reset */
906
907 /* Identify PHY and related function pointers */
908 status = hw->phy.ops.init(hw);
909
910 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
911 goto reset_hw_out;
912
913 /* Setup SFP module if there is one present. */
914 if (hw->phy.sfp_setup_needed) {
915 status = hw->mac.ops.setup_sfp(hw);
916 hw->phy.sfp_setup_needed = false;
917 }
918
919 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
920 goto reset_hw_out;
921
922 /* Reset PHY */
923 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
924 hw->phy.ops.reset(hw);
925
926 /*
927 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
928 * access and verify no pending requests before reset
929 */
930 ixgbe_disable_pcie_master(hw);
931
932 mac_reset_top:
933 /*
934 * Issue global reset to the MAC. This needs to be a SW reset.
935 * If link reset is used, it might reset the MAC when mng is using it
936 */
937 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
938 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
939 IXGBE_WRITE_FLUSH(hw);
940
941 /* Poll for reset bit to self-clear indicating reset is complete */
942 for (i = 0; i < 10; i++) {
943 udelay(1);
944 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
945 if (!(ctrl & IXGBE_CTRL_RST))
946 break;
947 }
948 if (ctrl & IXGBE_CTRL_RST) {
949 status = IXGBE_ERR_RESET_FAILED;
950 hw_dbg(hw, "Reset polling failed to complete.\n");
951 }
952
953 /*
954 * Double resets are required for recovery from certain error
955 * conditions. Between resets, it is necessary to stall to allow time
956 * for any pending HW events to complete. We use 1usec since that is
957 * what is needed for ixgbe_disable_pcie_master(). The second reset
958 * then clears out any effects of those events.
959 */
960 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
961 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
962 udelay(1);
963 goto mac_reset_top;
964 }
965
966 msleep(50);
967
968 /*
969 * Store the original AUTOC/AUTOC2 values if they have not been
970 * stored off yet. Otherwise restore the stored original
971 * values since the reset operation sets back to defaults.
972 */
973 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
974 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
975 if (hw->mac.orig_link_settings_stored == false) {
976 hw->mac.orig_autoc = autoc;
977 hw->mac.orig_autoc2 = autoc2;
978 hw->mac.orig_link_settings_stored = true;
979 } else {
980 if (autoc != hw->mac.orig_autoc)
981 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
982 IXGBE_AUTOC_AN_RESTART));
983
984 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
985 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
986 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
987 autoc2 |= (hw->mac.orig_autoc2 &
988 IXGBE_AUTOC2_UPPER_MASK);
989 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
990 }
991 }
992
993 /* Store the permanent mac address */
994 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
995
996 /*
997 * Store MAC address from RAR0, clear receive address registers, and
998 * clear the multicast table. Also reset num_rar_entries to 128,
999 * since we modify this value when programming the SAN MAC address.
1000 */
1001 hw->mac.num_rar_entries = 128;
1002 hw->mac.ops.init_rx_addrs(hw);
1003
1004 /* Store the permanent SAN mac address */
1005 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1006
1007 /* Add the SAN MAC address to the RAR only if it's a valid address */
1008 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1009 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1010 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1011
1012 /* Reserve the last RAR for the SAN MAC address */
1013 hw->mac.num_rar_entries--;
1014 }
1015
1016 /* Store the alternative WWNN/WWPN prefix */
1017 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1018 &hw->mac.wwpn_prefix);
1019
1020 reset_hw_out:
1021 return status;
1022 }
1023
1024 /**
1025 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1026 * @hw: pointer to hardware structure
1027 **/
1028 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1029 {
1030 int i;
1031 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1032 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1033
1034 /*
1035 * Before starting reinitialization process,
1036 * FDIRCMD.CMD must be zero.
1037 */
1038 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1039 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1040 IXGBE_FDIRCMD_CMD_MASK))
1041 break;
1042 udelay(10);
1043 }
1044 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1045 hw_dbg(hw, "Flow Director previous command isn't complete, "
1046 "aborting table re-initialization.\n");
1047 return IXGBE_ERR_FDIR_REINIT_FAILED;
1048 }
1049
1050 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1051 IXGBE_WRITE_FLUSH(hw);
1052 /*
1053 * 82599 adapters flow director init flow cannot be restarted,
1054 * Workaround 82599 silicon errata by performing the following steps
1055 * before re-writing the FDIRCTRL control register with the same value.
1056 * - write 1 to bit 8 of FDIRCMD register &
1057 * - write 0 to bit 8 of FDIRCMD register
1058 */
1059 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1060 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1061 IXGBE_FDIRCMD_CLEARHT));
1062 IXGBE_WRITE_FLUSH(hw);
1063 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1064 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1065 ~IXGBE_FDIRCMD_CLEARHT));
1066 IXGBE_WRITE_FLUSH(hw);
1067 /*
1068 * Clear FDIR Hash register to clear any leftover hashes
1069 * waiting to be programmed.
1070 */
1071 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1072 IXGBE_WRITE_FLUSH(hw);
1073
1074 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1075 IXGBE_WRITE_FLUSH(hw);
1076
1077 /* Poll init-done after we write FDIRCTRL register */
1078 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1079 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1080 IXGBE_FDIRCTRL_INIT_DONE)
1081 break;
1082 udelay(10);
1083 }
1084 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1085 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1086 return IXGBE_ERR_FDIR_REINIT_FAILED;
1087 }
1088
1089 /* Clear FDIR statistics registers (read to clear) */
1090 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1091 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1092 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1093 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1094 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1095
1096 return 0;
1097 }
1098
1099 /**
1100 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1101 * @hw: pointer to hardware structure
1102 * @pballoc: which mode to allocate filters with
1103 **/
1104 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1105 {
1106 u32 fdirctrl = 0;
1107 u32 pbsize;
1108 int i;
1109
1110 /*
1111 * Before enabling Flow Director, the Rx Packet Buffer size
1112 * must be reduced. The new value is the current size minus
1113 * flow director memory usage size.
1114 */
1115 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1116 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1117 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1118
1119 /*
1120 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1121 * initialized to zero for non DCB mode otherwise actual total RX PB
1122 * would be bigger than programmed and filter space would run into
1123 * the PB 0 region.
1124 */
1125 for (i = 1; i < 8; i++)
1126 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1127
1128 /* Send interrupt when 64 filters are left */
1129 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1130
1131 /* Set the maximum length per hash bucket to 0xA filters */
1132 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1133
1134 switch (pballoc) {
1135 case IXGBE_FDIR_PBALLOC_64K:
1136 /* 8k - 1 signature filters */
1137 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1138 break;
1139 case IXGBE_FDIR_PBALLOC_128K:
1140 /* 16k - 1 signature filters */
1141 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1142 break;
1143 case IXGBE_FDIR_PBALLOC_256K:
1144 /* 32k - 1 signature filters */
1145 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1146 break;
1147 default:
1148 /* bad value */
1149 return IXGBE_ERR_CONFIG;
1150 };
1151
1152 /* Move the flexible bytes to use the ethertype - shift 6 words */
1153 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1154
1155
1156 /* Prime the keys for hashing */
1157 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1158 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1159
1160 /*
1161 * Poll init-done after we write the register. Estimated times:
1162 * 10G: PBALLOC = 11b, timing is 60us
1163 * 1G: PBALLOC = 11b, timing is 600us
1164 * 100M: PBALLOC = 11b, timing is 6ms
1165 *
1166 * Multiple these timings by 4 if under full Rx load
1167 *
1168 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1169 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1170 * this might not finish in our poll time, but we can live with that
1171 * for now.
1172 */
1173 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1174 IXGBE_WRITE_FLUSH(hw);
1175 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1176 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1177 IXGBE_FDIRCTRL_INIT_DONE)
1178 break;
1179 msleep(1);
1180 }
1181 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1182 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1183
1184 return 0;
1185 }
1186
1187 /**
1188 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1189 * @hw: pointer to hardware structure
1190 * @pballoc: which mode to allocate filters with
1191 **/
1192 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1193 {
1194 u32 fdirctrl = 0;
1195 u32 pbsize;
1196 int i;
1197
1198 /*
1199 * Before enabling Flow Director, the Rx Packet Buffer size
1200 * must be reduced. The new value is the current size minus
1201 * flow director memory usage size.
1202 */
1203 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1204 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1205 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1206
1207 /*
1208 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1209 * initialized to zero for non DCB mode otherwise actual total RX PB
1210 * would be bigger than programmed and filter space would run into
1211 * the PB 0 region.
1212 */
1213 for (i = 1; i < 8; i++)
1214 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1215
1216 /* Send interrupt when 64 filters are left */
1217 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1218
1219 /* Initialize the drop queue to Rx queue 127 */
1220 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1221
1222 switch (pballoc) {
1223 case IXGBE_FDIR_PBALLOC_64K:
1224 /* 2k - 1 perfect filters */
1225 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1226 break;
1227 case IXGBE_FDIR_PBALLOC_128K:
1228 /* 4k - 1 perfect filters */
1229 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1230 break;
1231 case IXGBE_FDIR_PBALLOC_256K:
1232 /* 8k - 1 perfect filters */
1233 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1234 break;
1235 default:
1236 /* bad value */
1237 return IXGBE_ERR_CONFIG;
1238 };
1239
1240 /* Turn perfect match filtering on */
1241 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1242 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1243
1244 /* Move the flexible bytes to use the ethertype - shift 6 words */
1245 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1246
1247 /* Prime the keys for hashing */
1248 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1249 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1250
1251 /*
1252 * Poll init-done after we write the register. Estimated times:
1253 * 10G: PBALLOC = 11b, timing is 60us
1254 * 1G: PBALLOC = 11b, timing is 600us
1255 * 100M: PBALLOC = 11b, timing is 6ms
1256 *
1257 * Multiple these timings by 4 if under full Rx load
1258 *
1259 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1260 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1261 * this might not finish in our poll time, but we can live with that
1262 * for now.
1263 */
1264
1265 /* Set the maximum length per hash bucket to 0xA filters */
1266 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1267
1268 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1269 IXGBE_WRITE_FLUSH(hw);
1270 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1271 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1272 IXGBE_FDIRCTRL_INIT_DONE)
1273 break;
1274 msleep(1);
1275 }
1276 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1277 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1278
1279 return 0;
1280 }
1281
1282
1283 /**
1284 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1285 * @stream: input bitstream to compute the hash on
1286 * @key: 32-bit hash key
1287 **/
1288 static u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
1289 u32 key)
1290 {
1291 /*
1292 * The algorithm is as follows:
1293 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1294 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1295 * and A[n] x B[n] is bitwise AND between same length strings
1296 *
1297 * K[n] is 16 bits, defined as:
1298 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1299 * for n modulo 32 < 15, K[n] =
1300 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1301 *
1302 * S[n] is 16 bits, defined as:
1303 * for n >= 15, S[n] = S[n:n - 15]
1304 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1305 *
1306 * To simplify for programming, the algorithm is implemented
1307 * in software this way:
1308 *
1309 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
1310 *
1311 * for (i = 0; i < 352; i+=32)
1312 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
1313 *
1314 * lo_hash_dword[15:0] ^= Stream[15:0];
1315 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
1316 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
1317 *
1318 * hi_hash_dword[31:0] ^= Stream[351:320];
1319 *
1320 * if(key[0])
1321 * hash[15:0] ^= Stream[15:0];
1322 *
1323 * for (i = 0; i < 16; i++) {
1324 * if (key[i])
1325 * hash[15:0] ^= lo_hash_dword[(i+15):i];
1326 * if (key[i + 16])
1327 * hash[15:0] ^= hi_hash_dword[(i+15):i];
1328 * }
1329 *
1330 */
1331 __be32 common_hash_dword = 0;
1332 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1333 u32 hash_result = 0;
1334 u8 i;
1335
1336 /* record the flow_vm_vlan bits as they are a key part to the hash */
1337 flow_vm_vlan = ntohl(atr_input->dword_stream[0]);
1338
1339 /* generate common hash dword */
1340 for (i = 10; i; i -= 2)
1341 common_hash_dword ^= atr_input->dword_stream[i] ^
1342 atr_input->dword_stream[i - 1];
1343
1344 hi_hash_dword = ntohl(common_hash_dword);
1345
1346 /* low dword is word swapped version of common */
1347 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1348
1349 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1350 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1351
1352 /* Process bits 0 and 16 */
1353 if (key & 0x0001) hash_result ^= lo_hash_dword;
1354 if (key & 0x00010000) hash_result ^= hi_hash_dword;
1355
1356 /*
1357 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1358 * delay this because bit 0 of the stream should not be processed
1359 * so we do not add the vlan until after bit 0 was processed
1360 */
1361 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1362
1363
1364 /* process the remaining 30 bits in the key 2 bits at a time */
1365 for (i = 15; i; i-- ) {
1366 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
1367 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
1368 }
1369
1370 return hash_result & IXGBE_ATR_HASH_MASK;
1371 }
1372
1373 /*
1374 * These defines allow us to quickly generate all of the necessary instructions
1375 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1376 * for values 0 through 15
1377 */
1378 #define IXGBE_ATR_COMMON_HASH_KEY \
1379 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1380 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1381 do { \
1382 u32 n = (_n); \
1383 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1384 common_hash ^= lo_hash_dword >> n; \
1385 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1386 bucket_hash ^= lo_hash_dword >> n; \
1387 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1388 sig_hash ^= lo_hash_dword << (16 - n); \
1389 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1390 common_hash ^= hi_hash_dword >> n; \
1391 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1392 bucket_hash ^= hi_hash_dword >> n; \
1393 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1394 sig_hash ^= hi_hash_dword << (16 - n); \
1395 } while (0);
1396
1397 /**
1398 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1399 * @stream: input bitstream to compute the hash on
1400 *
1401 * This function is almost identical to the function above but contains
1402 * several optomizations such as unwinding all of the loops, letting the
1403 * compiler work out all of the conditional ifs since the keys are static
1404 * defines, and computing two keys at once since the hashed dword stream
1405 * will be the same for both keys.
1406 **/
1407 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1408 union ixgbe_atr_hash_dword common)
1409 {
1410 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1411 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1412
1413 /* record the flow_vm_vlan bits as they are a key part to the hash */
1414 flow_vm_vlan = ntohl(input.dword);
1415
1416 /* generate common hash dword */
1417 hi_hash_dword = ntohl(common.dword);
1418
1419 /* low dword is word swapped version of common */
1420 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1421
1422 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1423 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1424
1425 /* Process bits 0 and 16 */
1426 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1427
1428 /*
1429 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1430 * delay this because bit 0 of the stream should not be processed
1431 * so we do not add the vlan until after bit 0 was processed
1432 */
1433 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1434
1435 /* Process remaining 30 bit of the key */
1436 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1437 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1438 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1439 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1440 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1441 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1442 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1443 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1444 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1445 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1446 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1447 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1448 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1449 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1450 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1451
1452 /* combine common_hash result with signature and bucket hashes */
1453 bucket_hash ^= common_hash;
1454 bucket_hash &= IXGBE_ATR_HASH_MASK;
1455
1456 sig_hash ^= common_hash << 16;
1457 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1458
1459 /* return completed signature hash */
1460 return sig_hash ^ bucket_hash;
1461 }
1462
1463 /**
1464 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1465 * @hw: pointer to hardware structure
1466 * @input: unique input dword
1467 * @common: compressed common input dword
1468 * @queue: queue index to direct traffic to
1469 **/
1470 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1471 union ixgbe_atr_hash_dword input,
1472 union ixgbe_atr_hash_dword common,
1473 u8 queue)
1474 {
1475 u64 fdirhashcmd;
1476 u32 fdircmd;
1477
1478 /*
1479 * Get the flow_type in order to program FDIRCMD properly
1480 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1481 */
1482 switch (input.formatted.flow_type) {
1483 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1484 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1485 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1486 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1487 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1488 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1489 break;
1490 default:
1491 hw_dbg(hw, " Error on flow type input\n");
1492 return IXGBE_ERR_CONFIG;
1493 }
1494
1495 /* configure FDIRCMD register */
1496 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1497 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1498 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1499 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1500
1501 /*
1502 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1503 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1504 */
1505 fdirhashcmd = (u64)fdircmd << 32;
1506 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1507
1508 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1509
1510 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1511
1512 return 0;
1513 }
1514
1515 /**
1516 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1517 * @input_mask: mask to be bit swapped
1518 *
1519 * The source and destination port masks for flow director are bit swapped
1520 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1521 * generate a correctly swapped value we need to bit swap the mask and that
1522 * is what is accomplished by this function.
1523 **/
1524 static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks)
1525 {
1526 u32 mask = ntohs(input_masks->dst_port_mask);
1527 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1528 mask |= ntohs(input_masks->src_port_mask);
1529 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1530 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1531 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1532 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1533 }
1534
1535 /*
1536 * These two macros are meant to address the fact that we have registers
1537 * that are either all or in part big-endian. As a result on big-endian
1538 * systems we will end up byte swapping the value to little-endian before
1539 * it is byte swapped again and written to the hardware in the original
1540 * big-endian format.
1541 */
1542 #define IXGBE_STORE_AS_BE32(_value) \
1543 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1544 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1545
1546 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1547 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1548
1549 #define IXGBE_STORE_AS_BE16(_value) \
1550 (((u16)(_value) >> 8) | ((u16)(_value) << 8))
1551
1552 /**
1553 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1554 * @hw: pointer to hardware structure
1555 * @input: input bitstream
1556 * @input_masks: bitwise masks for relevant fields
1557 * @soft_id: software index into the silicon hash tables for filter storage
1558 * @queue: queue index to direct traffic to
1559 *
1560 * Note that the caller to this function must lock before calling, since the
1561 * hardware writes must be protected from one another.
1562 **/
1563 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1564 union ixgbe_atr_input *input,
1565 struct ixgbe_atr_input_masks *input_masks,
1566 u16 soft_id, u8 queue)
1567 {
1568 u32 fdirhash;
1569 u32 fdircmd;
1570 u32 fdirport, fdirtcpm;
1571 u32 fdirvlan;
1572 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
1573 u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX |
1574 IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
1575
1576 /*
1577 * Check flow_type formatting, and bail out before we touch the hardware
1578 * if there's a configuration issue
1579 */
1580 switch (input->formatted.flow_type) {
1581 case IXGBE_ATR_FLOW_TYPE_IPV4:
1582 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
1583 fdirm |= IXGBE_FDIRM_L4P;
1584 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1585 if (input_masks->dst_port_mask || input_masks->src_port_mask) {
1586 hw_dbg(hw, " Error on src/dst port mask\n");
1587 return IXGBE_ERR_CONFIG;
1588 }
1589 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1590 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1591 break;
1592 default:
1593 hw_dbg(hw, " Error on flow type input\n");
1594 return IXGBE_ERR_CONFIG;
1595 }
1596
1597 /*
1598 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1599 * are zero, then assume a full mask for that field. Also assume that
1600 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1601 * cannot be masked out in this implementation.
1602 *
1603 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1604 * point in time.
1605 */
1606
1607 /* Program FDIRM */
1608 switch (ntohs(input_masks->vlan_id_mask) & 0xEFFF) {
1609 case 0xEFFF:
1610 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */
1611 fdirm &= ~IXGBE_FDIRM_VLANID;
1612 case 0xE000:
1613 /* Unmask VLAN prio - bit 1 */
1614 fdirm &= ~IXGBE_FDIRM_VLANP;
1615 break;
1616 case 0x0FFF:
1617 /* Unmask VLAN ID - bit 0 */
1618 fdirm &= ~IXGBE_FDIRM_VLANID;
1619 break;
1620 case 0x0000:
1621 /* do nothing, vlans already masked */
1622 break;
1623 default:
1624 hw_dbg(hw, " Error on VLAN mask\n");
1625 return IXGBE_ERR_CONFIG;
1626 }
1627
1628 if (input_masks->flex_mask & 0xFFFF) {
1629 if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) {
1630 hw_dbg(hw, " Error on flexible byte mask\n");
1631 return IXGBE_ERR_CONFIG;
1632 }
1633 /* Unmask Flex Bytes - bit 4 */
1634 fdirm &= ~IXGBE_FDIRM_FLEX;
1635 }
1636
1637 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1638 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1639
1640 /* store the TCP/UDP port masks, bit reversed from port layout */
1641 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks);
1642
1643 /* write both the same so that UDP and TCP use the same mask */
1644 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1645 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1646
1647 /* store source and destination IP masks (big-enian) */
1648 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1649 ~input_masks->src_ip_mask[0]);
1650 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1651 ~input_masks->dst_ip_mask[0]);
1652
1653 /* Apply masks to input data */
1654 input->formatted.vlan_id &= input_masks->vlan_id_mask;
1655 input->formatted.flex_bytes &= input_masks->flex_mask;
1656 input->formatted.src_port &= input_masks->src_port_mask;
1657 input->formatted.dst_port &= input_masks->dst_port_mask;
1658 input->formatted.src_ip[0] &= input_masks->src_ip_mask[0];
1659 input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0];
1660
1661 /* record vlan (little-endian) and flex_bytes(big-endian) */
1662 fdirvlan =
1663 IXGBE_STORE_AS_BE16(ntohs(input->formatted.flex_bytes));
1664 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1665 fdirvlan |= ntohs(input->formatted.vlan_id);
1666 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1667
1668 /* record source and destination port (little-endian)*/
1669 fdirport = ntohs(input->formatted.dst_port);
1670 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1671 fdirport |= ntohs(input->formatted.src_port);
1672 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1673
1674 /* record the first 32 bits of the destination address (big-endian) */
1675 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1676
1677 /* record the source address (big-endian) */
1678 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1679
1680 /* configure FDIRCMD register */
1681 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1682 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1683 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1684 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1685
1686 /* we only want the bucket hash so drop the upper 16 bits */
1687 fdirhash = ixgbe_atr_compute_hash_82599(input,
1688 IXGBE_ATR_BUCKET_HASH_KEY);
1689 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1690
1691 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1692 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1693
1694 return 0;
1695 }
1696
1697 /**
1698 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1699 * @hw: pointer to hardware structure
1700 * @reg: analog register to read
1701 * @val: read value
1702 *
1703 * Performs read operation to Omer analog register specified.
1704 **/
1705 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1706 {
1707 u32 core_ctl;
1708
1709 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1710 (reg << 8));
1711 IXGBE_WRITE_FLUSH(hw);
1712 udelay(10);
1713 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1714 *val = (u8)core_ctl;
1715
1716 return 0;
1717 }
1718
1719 /**
1720 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1721 * @hw: pointer to hardware structure
1722 * @reg: atlas register to write
1723 * @val: value to write
1724 *
1725 * Performs write operation to Omer analog register specified.
1726 **/
1727 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1728 {
1729 u32 core_ctl;
1730
1731 core_ctl = (reg << 8) | val;
1732 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1733 IXGBE_WRITE_FLUSH(hw);
1734 udelay(10);
1735
1736 return 0;
1737 }
1738
1739 /**
1740 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1741 * @hw: pointer to hardware structure
1742 *
1743 * Starts the hardware using the generic start_hw function.
1744 * Then performs device-specific:
1745 * Clears the rate limiter registers.
1746 **/
1747 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1748 {
1749 u32 q_num;
1750 s32 ret_val;
1751
1752 ret_val = ixgbe_start_hw_generic(hw);
1753
1754 /* Clear the rate limiters */
1755 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1756 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1757 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1758 }
1759 IXGBE_WRITE_FLUSH(hw);
1760
1761 /* We need to run link autotry after the driver loads */
1762 hw->mac.autotry_restart = true;
1763
1764 if (ret_val == 0)
1765 ret_val = ixgbe_verify_fw_version_82599(hw);
1766
1767 return ret_val;
1768 }
1769
1770 /**
1771 * ixgbe_identify_phy_82599 - Get physical layer module
1772 * @hw: pointer to hardware structure
1773 *
1774 * Determines the physical layer module found on the current adapter.
1775 * If PHY already detected, maintains current PHY type in hw struct,
1776 * otherwise executes the PHY detection routine.
1777 **/
1778 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1779 {
1780 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1781
1782 /* Detect PHY if not unknown - returns success if already detected. */
1783 status = ixgbe_identify_phy_generic(hw);
1784 if (status != 0) {
1785 /* 82599 10GBASE-T requires an external PHY */
1786 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1787 goto out;
1788 else
1789 status = ixgbe_identify_sfp_module_generic(hw);
1790 }
1791
1792 /* Set PHY type none if no PHY detected */
1793 if (hw->phy.type == ixgbe_phy_unknown) {
1794 hw->phy.type = ixgbe_phy_none;
1795 status = 0;
1796 }
1797
1798 /* Return error if SFP module has been detected but is not supported */
1799 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1800 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1801
1802 out:
1803 return status;
1804 }
1805
1806 /**
1807 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1808 * @hw: pointer to hardware structure
1809 *
1810 * Determines physical layer capabilities of the current configuration.
1811 **/
1812 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1813 {
1814 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1815 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1816 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1817 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1818 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1819 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1820 u16 ext_ability = 0;
1821 u8 comp_codes_10g = 0;
1822 u8 comp_codes_1g = 0;
1823
1824 hw->phy.ops.identify(hw);
1825
1826 switch (hw->phy.type) {
1827 case ixgbe_phy_tn:
1828 case ixgbe_phy_aq:
1829 case ixgbe_phy_cu_unknown:
1830 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1831 &ext_ability);
1832 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1833 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1834 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1835 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1836 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1837 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1838 goto out;
1839 default:
1840 break;
1841 }
1842
1843 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1844 case IXGBE_AUTOC_LMS_1G_AN:
1845 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1846 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1847 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1848 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1849 goto out;
1850 } else
1851 /* SFI mode so read SFP module */
1852 goto sfp_check;
1853 break;
1854 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1855 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1856 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1857 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1858 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1859 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1860 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1861 goto out;
1862 break;
1863 case IXGBE_AUTOC_LMS_10G_SERIAL:
1864 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1865 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1866 goto out;
1867 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1868 goto sfp_check;
1869 break;
1870 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1871 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1872 if (autoc & IXGBE_AUTOC_KX_SUPP)
1873 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1874 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1875 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1876 if (autoc & IXGBE_AUTOC_KR_SUPP)
1877 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1878 goto out;
1879 break;
1880 default:
1881 goto out;
1882 break;
1883 }
1884
1885 sfp_check:
1886 /* SFP check must be done last since DA modules are sometimes used to
1887 * test KR mode - we need to id KR mode correctly before SFP module.
1888 * Call identify_sfp because the pluggable module may have changed */
1889 hw->phy.ops.identify_sfp(hw);
1890 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1891 goto out;
1892
1893 switch (hw->phy.type) {
1894 case ixgbe_phy_sfp_passive_tyco:
1895 case ixgbe_phy_sfp_passive_unknown:
1896 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1897 break;
1898 case ixgbe_phy_sfp_ftl_active:
1899 case ixgbe_phy_sfp_active_unknown:
1900 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1901 break;
1902 case ixgbe_phy_sfp_avago:
1903 case ixgbe_phy_sfp_ftl:
1904 case ixgbe_phy_sfp_intel:
1905 case ixgbe_phy_sfp_unknown:
1906 hw->phy.ops.read_i2c_eeprom(hw,
1907 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1908 hw->phy.ops.read_i2c_eeprom(hw,
1909 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1910 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1911 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1912 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1913 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1914 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1915 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1916 break;
1917 default:
1918 break;
1919 }
1920
1921 out:
1922 return physical_layer;
1923 }
1924
1925 /**
1926 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1927 * @hw: pointer to hardware structure
1928 * @regval: register value to write to RXCTRL
1929 *
1930 * Enables the Rx DMA unit for 82599
1931 **/
1932 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1933 {
1934 #define IXGBE_MAX_SECRX_POLL 30
1935 int i;
1936 int secrxreg;
1937
1938 /*
1939 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1940 * If traffic is incoming before we enable the Rx unit, it could hang
1941 * the Rx DMA unit. Therefore, make sure the security engine is
1942 * completely disabled prior to enabling the Rx unit.
1943 */
1944 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1945 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1946 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1947 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1948 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1949 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1950 break;
1951 else
1952 /* Use interrupt-safe sleep just in case */
1953 udelay(10);
1954 }
1955
1956 /* For informational purposes only */
1957 if (i >= IXGBE_MAX_SECRX_POLL)
1958 hw_dbg(hw, "Rx unit being enabled before security "
1959 "path fully disabled. Continuing with init.\n");
1960
1961 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1962 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1963 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1964 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1965 IXGBE_WRITE_FLUSH(hw);
1966
1967 return 0;
1968 }
1969
1970 /**
1971 * ixgbe_get_device_caps_82599 - Get additional device capabilities
1972 * @hw: pointer to hardware structure
1973 * @device_caps: the EEPROM word with the extra device capabilities
1974 *
1975 * This function will read the EEPROM location for the device capabilities,
1976 * and return the word through device_caps.
1977 **/
1978 static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
1979 {
1980 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
1981
1982 return 0;
1983 }
1984
1985 /**
1986 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1987 * @hw: pointer to hardware structure
1988 *
1989 * Verifies that installed the firmware version is 0.6 or higher
1990 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1991 *
1992 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1993 * if the FW version is not supported.
1994 **/
1995 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
1996 {
1997 s32 status = IXGBE_ERR_EEPROM_VERSION;
1998 u16 fw_offset, fw_ptp_cfg_offset;
1999 u16 fw_version = 0;
2000
2001 /* firmware check is only necessary for SFI devices */
2002 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2003 status = 0;
2004 goto fw_version_out;
2005 }
2006
2007 /* get the offset to the Firmware Module block */
2008 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2009
2010 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2011 goto fw_version_out;
2012
2013 /* get the offset to the Pass Through Patch Configuration block */
2014 hw->eeprom.ops.read(hw, (fw_offset +
2015 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2016 &fw_ptp_cfg_offset);
2017
2018 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2019 goto fw_version_out;
2020
2021 /* get the firmware version */
2022 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2023 IXGBE_FW_PATCH_VERSION_4),
2024 &fw_version);
2025
2026 if (fw_version > 0x5)
2027 status = 0;
2028
2029 fw_version_out:
2030 return status;
2031 }
2032
2033 static struct ixgbe_mac_operations mac_ops_82599 = {
2034 .init_hw = &ixgbe_init_hw_generic,
2035 .reset_hw = &ixgbe_reset_hw_82599,
2036 .start_hw = &ixgbe_start_hw_82599,
2037 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2038 .get_media_type = &ixgbe_get_media_type_82599,
2039 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2040 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2041 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2042 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2043 .get_device_caps = &ixgbe_get_device_caps_82599,
2044 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2045 .stop_adapter = &ixgbe_stop_adapter_generic,
2046 .get_bus_info = &ixgbe_get_bus_info_generic,
2047 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2048 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2049 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2050 .setup_link = &ixgbe_setup_mac_link_82599,
2051 .check_link = &ixgbe_check_mac_link_generic,
2052 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2053 .led_on = &ixgbe_led_on_generic,
2054 .led_off = &ixgbe_led_off_generic,
2055 .blink_led_start = &ixgbe_blink_led_start_generic,
2056 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2057 .set_rar = &ixgbe_set_rar_generic,
2058 .clear_rar = &ixgbe_clear_rar_generic,
2059 .set_vmdq = &ixgbe_set_vmdq_generic,
2060 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2061 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2062 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2063 .enable_mc = &ixgbe_enable_mc_generic,
2064 .disable_mc = &ixgbe_disable_mc_generic,
2065 .clear_vfta = &ixgbe_clear_vfta_generic,
2066 .set_vfta = &ixgbe_set_vfta_generic,
2067 .fc_enable = &ixgbe_fc_enable_generic,
2068 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2069 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2070 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2071 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2072 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2073 .release_swfw_sync = &ixgbe_release_swfw_sync,
2074
2075 };
2076
2077 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2078 .init_params = &ixgbe_init_eeprom_params_generic,
2079 .read = &ixgbe_read_eerd_generic,
2080 .write = &ixgbe_write_eeprom_generic,
2081 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2082 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2083 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2084 };
2085
2086 static struct ixgbe_phy_operations phy_ops_82599 = {
2087 .identify = &ixgbe_identify_phy_82599,
2088 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2089 .init = &ixgbe_init_phy_ops_82599,
2090 .reset = &ixgbe_reset_phy_generic,
2091 .read_reg = &ixgbe_read_phy_reg_generic,
2092 .write_reg = &ixgbe_write_phy_reg_generic,
2093 .setup_link = &ixgbe_setup_phy_link_generic,
2094 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2095 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2096 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2097 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2098 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2099 .check_overtemp = &ixgbe_tn_check_overtemp,
2100 };
2101
2102 struct ixgbe_info ixgbe_82599_info = {
2103 .mac = ixgbe_mac_82599EB,
2104 .get_invariants = &ixgbe_get_invariants_82599,
2105 .mac_ops = &mac_ops_82599,
2106 .eeprom_ops = &eeprom_ops_82599,
2107 .phy_ops = &phy_ops_82599,
2108 .mbx_ops = &mbx_ops_generic,
2109 };
kernel source for telekom puls (alcatel/mediatek)