1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/if_ether.h>
29 #include <linux/delay.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
33 #include "e1000_mac.h"
37 static s32
igb_set_default_fc(struct e1000_hw
*hw
);
38 static s32
igb_set_fc_watermarks(struct e1000_hw
*hw
);
41 * igb_get_bus_info_pcie - Get PCIe bus information
42 * @hw: pointer to the HW structure
44 * Determines and stores the system bus information for a particular
45 * network interface. The following bus information is determined and stored:
46 * bus speed, bus width, type (PCIe), and PCIe function.
48 s32
igb_get_bus_info_pcie(struct e1000_hw
*hw
)
50 struct e1000_bus_info
*bus
= &hw
->bus
;
55 bus
->type
= e1000_bus_type_pci_express
;
56 bus
->speed
= e1000_bus_speed_2500
;
58 ret_val
= igb_read_pcie_cap_reg(hw
,
62 bus
->width
= e1000_bus_width_unknown
;
64 bus
->width
= (enum e1000_bus_width
)((pcie_link_status
&
65 PCIE_LINK_WIDTH_MASK
) >>
66 PCIE_LINK_WIDTH_SHIFT
);
68 reg
= rd32(E1000_STATUS
);
69 bus
->func
= (reg
& E1000_STATUS_FUNC_MASK
) >> E1000_STATUS_FUNC_SHIFT
;
75 * igb_clear_vfta - Clear VLAN filter table
76 * @hw: pointer to the HW structure
78 * Clears the register array which contains the VLAN filter table by
79 * setting all the values to 0.
81 void igb_clear_vfta(struct e1000_hw
*hw
)
85 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
86 array_wr32(E1000_VFTA
, offset
, 0);
92 * igb_write_vfta - Write value to VLAN filter table
93 * @hw: pointer to the HW structure
94 * @offset: register offset in VLAN filter table
95 * @value: register value written to VLAN filter table
97 * Writes value at the given offset in the register array which stores
98 * the VLAN filter table.
100 static void igb_write_vfta(struct e1000_hw
*hw
, u32 offset
, u32 value
)
102 array_wr32(E1000_VFTA
, offset
, value
);
107 * igb_init_rx_addrs - Initialize receive address's
108 * @hw: pointer to the HW structure
109 * @rar_count: receive address registers
111 * Setups the receive address registers by setting the base receive address
112 * register to the devices MAC address and clearing all the other receive
113 * address registers to 0.
115 void igb_init_rx_addrs(struct e1000_hw
*hw
, u16 rar_count
)
118 u8 mac_addr
[ETH_ALEN
] = {0};
120 /* Setup the receive address */
121 hw_dbg("Programming MAC Address into RAR[0]\n");
123 hw
->mac
.ops
.rar_set(hw
, hw
->mac
.addr
, 0);
125 /* Zero out the other (rar_entry_count - 1) receive addresses */
126 hw_dbg("Clearing RAR[1-%u]\n", rar_count
-1);
127 for (i
= 1; i
< rar_count
; i
++)
128 hw
->mac
.ops
.rar_set(hw
, mac_addr
, i
);
132 * igb_vfta_set - enable or disable vlan in VLAN filter table
133 * @hw: pointer to the HW structure
134 * @vid: VLAN id to add or remove
135 * @add: if true add filter, if false remove
137 * Sets or clears a bit in the VLAN filter table array based on VLAN id
138 * and if we are adding or removing the filter
140 s32
igb_vfta_set(struct e1000_hw
*hw
, u32 vid
, bool add
)
142 u32 index
= (vid
>> E1000_VFTA_ENTRY_SHIFT
) & E1000_VFTA_ENTRY_MASK
;
143 u32 mask
= 1 << (vid
& E1000_VFTA_ENTRY_BIT_SHIFT_MASK
);
144 u32 vfta
= array_rd32(E1000_VFTA
, index
);
147 /* bit was set/cleared before we started */
148 if ((!!(vfta
& mask
)) == add
) {
149 ret_val
= -E1000_ERR_CONFIG
;
157 igb_write_vfta(hw
, index
, vfta
);
163 * igb_check_alt_mac_addr - Check for alternate MAC addr
164 * @hw: pointer to the HW structure
166 * Checks the nvm for an alternate MAC address. An alternate MAC address
167 * can be setup by pre-boot software and must be treated like a permanent
168 * address and must override the actual permanent MAC address. If an
169 * alternate MAC address is fopund it is saved in the hw struct and
170 * prgrammed into RAR0 and the cuntion returns success, otherwise the
171 * fucntion returns an error.
173 s32
igb_check_alt_mac_addr(struct e1000_hw
*hw
)
177 u16 offset
, nvm_alt_mac_addr_offset
, nvm_data
;
178 u8 alt_mac_addr
[ETH_ALEN
];
180 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_ALT_MAC_ADDR_PTR
, 1,
181 &nvm_alt_mac_addr_offset
);
183 hw_dbg("NVM Read Error\n");
187 if (nvm_alt_mac_addr_offset
== 0xFFFF) {
188 ret_val
= -(E1000_NOT_IMPLEMENTED
);
192 if (hw
->bus
.func
== E1000_FUNC_1
)
193 nvm_alt_mac_addr_offset
+= ETH_ALEN
/sizeof(u16
);
195 for (i
= 0; i
< ETH_ALEN
; i
+= 2) {
196 offset
= nvm_alt_mac_addr_offset
+ (i
>> 1);
197 ret_val
= hw
->nvm
.ops
.read(hw
, offset
, 1, &nvm_data
);
199 hw_dbg("NVM Read Error\n");
203 alt_mac_addr
[i
] = (u8
)(nvm_data
& 0xFF);
204 alt_mac_addr
[i
+ 1] = (u8
)(nvm_data
>> 8);
207 /* if multicast bit is set, the alternate address will not be used */
208 if (alt_mac_addr
[0] & 0x01) {
209 ret_val
= -(E1000_NOT_IMPLEMENTED
);
213 for (i
= 0; i
< ETH_ALEN
; i
++)
214 hw
->mac
.addr
[i
] = hw
->mac
.perm_addr
[i
] = alt_mac_addr
[i
];
216 hw
->mac
.ops
.rar_set(hw
, hw
->mac
.perm_addr
, 0);
223 * igb_rar_set - Set receive address register
224 * @hw: pointer to the HW structure
225 * @addr: pointer to the receive address
226 * @index: receive address array register
228 * Sets the receive address array register at index to the address passed
231 void igb_rar_set(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
233 u32 rar_low
, rar_high
;
236 * HW expects these in little endian so we reverse the byte order
237 * from network order (big endian) to little endian
239 rar_low
= ((u32
) addr
[0] |
240 ((u32
) addr
[1] << 8) |
241 ((u32
) addr
[2] << 16) | ((u32
) addr
[3] << 24));
243 rar_high
= ((u32
) addr
[4] | ((u32
) addr
[5] << 8));
245 /* If MAC address zero, no need to set the AV bit */
246 if (rar_low
|| rar_high
)
247 rar_high
|= E1000_RAH_AV
;
249 wr32(E1000_RAL(index
), rar_low
);
250 wr32(E1000_RAH(index
), rar_high
);
254 * igb_mta_set - Set multicast filter table address
255 * @hw: pointer to the HW structure
256 * @hash_value: determines the MTA register and bit to set
258 * The multicast table address is a register array of 32-bit registers.
259 * The hash_value is used to determine what register the bit is in, the
260 * current value is read, the new bit is OR'd in and the new value is
261 * written back into the register.
263 void igb_mta_set(struct e1000_hw
*hw
, u32 hash_value
)
265 u32 hash_bit
, hash_reg
, mta
;
268 * The MTA is a register array of 32-bit registers. It is
269 * treated like an array of (32*mta_reg_count) bits. We want to
270 * set bit BitArray[hash_value]. So we figure out what register
271 * the bit is in, read it, OR in the new bit, then write
272 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
273 * mask to bits 31:5 of the hash value which gives us the
274 * register we're modifying. The hash bit within that register
275 * is determined by the lower 5 bits of the hash value.
277 hash_reg
= (hash_value
>> 5) & (hw
->mac
.mta_reg_count
- 1);
278 hash_bit
= hash_value
& 0x1F;
280 mta
= array_rd32(E1000_MTA
, hash_reg
);
282 mta
|= (1 << hash_bit
);
284 array_wr32(E1000_MTA
, hash_reg
, mta
);
289 * igb_update_mc_addr_list - Update Multicast addresses
290 * @hw: pointer to the HW structure
291 * @mc_addr_list: array of multicast addresses to program
292 * @mc_addr_count: number of multicast addresses to program
294 * Updates entire Multicast Table Array.
295 * The caller must have a packed mc_addr_list of multicast addresses.
297 void igb_update_mc_addr_list(struct e1000_hw
*hw
,
298 u8
*mc_addr_list
, u32 mc_addr_count
)
300 u32 hash_value
, hash_bit
, hash_reg
;
303 /* clear mta_shadow */
304 memset(&hw
->mac
.mta_shadow
, 0, sizeof(hw
->mac
.mta_shadow
));
306 /* update mta_shadow from mc_addr_list */
307 for (i
= 0; (u32
) i
< mc_addr_count
; i
++) {
308 hash_value
= igb_hash_mc_addr(hw
, mc_addr_list
);
310 hash_reg
= (hash_value
>> 5) & (hw
->mac
.mta_reg_count
- 1);
311 hash_bit
= hash_value
& 0x1F;
313 hw
->mac
.mta_shadow
[hash_reg
] |= (1 << hash_bit
);
314 mc_addr_list
+= (ETH_ALEN
);
317 /* replace the entire MTA table */
318 for (i
= hw
->mac
.mta_reg_count
- 1; i
>= 0; i
--)
319 array_wr32(E1000_MTA
, i
, hw
->mac
.mta_shadow
[i
]);
324 * igb_hash_mc_addr - Generate a multicast hash value
325 * @hw: pointer to the HW structure
326 * @mc_addr: pointer to a multicast address
328 * Generates a multicast address hash value which is used to determine
329 * the multicast filter table array address and new table value. See
332 u32
igb_hash_mc_addr(struct e1000_hw
*hw
, u8
*mc_addr
)
334 u32 hash_value
, hash_mask
;
337 /* Register count multiplied by bits per register */
338 hash_mask
= (hw
->mac
.mta_reg_count
* 32) - 1;
341 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
342 * where 0xFF would still fall within the hash mask.
344 while (hash_mask
>> bit_shift
!= 0xFF)
348 * The portion of the address that is used for the hash table
349 * is determined by the mc_filter_type setting.
350 * The algorithm is such that there is a total of 8 bits of shifting.
351 * The bit_shift for a mc_filter_type of 0 represents the number of
352 * left-shifts where the MSB of mc_addr[5] would still fall within
353 * the hash_mask. Case 0 does this exactly. Since there are a total
354 * of 8 bits of shifting, then mc_addr[4] will shift right the
355 * remaining number of bits. Thus 8 - bit_shift. The rest of the
356 * cases are a variation of this algorithm...essentially raising the
357 * number of bits to shift mc_addr[5] left, while still keeping the
358 * 8-bit shifting total.
360 * For example, given the following Destination MAC Address and an
361 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
362 * we can see that the bit_shift for case 0 is 4. These are the hash
363 * values resulting from each mc_filter_type...
364 * [0] [1] [2] [3] [4] [5]
368 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
369 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
370 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
371 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
373 switch (hw
->mac
.mc_filter_type
) {
388 hash_value
= hash_mask
& (((mc_addr
[4] >> (8 - bit_shift
)) |
389 (((u16
) mc_addr
[5]) << bit_shift
)));
395 * igb_clear_hw_cntrs_base - Clear base hardware counters
396 * @hw: pointer to the HW structure
398 * Clears the base hardware counters by reading the counter registers.
400 void igb_clear_hw_cntrs_base(struct e1000_hw
*hw
)
404 temp
= rd32(E1000_CRCERRS
);
405 temp
= rd32(E1000_SYMERRS
);
406 temp
= rd32(E1000_MPC
);
407 temp
= rd32(E1000_SCC
);
408 temp
= rd32(E1000_ECOL
);
409 temp
= rd32(E1000_MCC
);
410 temp
= rd32(E1000_LATECOL
);
411 temp
= rd32(E1000_COLC
);
412 temp
= rd32(E1000_DC
);
413 temp
= rd32(E1000_SEC
);
414 temp
= rd32(E1000_RLEC
);
415 temp
= rd32(E1000_XONRXC
);
416 temp
= rd32(E1000_XONTXC
);
417 temp
= rd32(E1000_XOFFRXC
);
418 temp
= rd32(E1000_XOFFTXC
);
419 temp
= rd32(E1000_FCRUC
);
420 temp
= rd32(E1000_GPRC
);
421 temp
= rd32(E1000_BPRC
);
422 temp
= rd32(E1000_MPRC
);
423 temp
= rd32(E1000_GPTC
);
424 temp
= rd32(E1000_GORCL
);
425 temp
= rd32(E1000_GORCH
);
426 temp
= rd32(E1000_GOTCL
);
427 temp
= rd32(E1000_GOTCH
);
428 temp
= rd32(E1000_RNBC
);
429 temp
= rd32(E1000_RUC
);
430 temp
= rd32(E1000_RFC
);
431 temp
= rd32(E1000_ROC
);
432 temp
= rd32(E1000_RJC
);
433 temp
= rd32(E1000_TORL
);
434 temp
= rd32(E1000_TORH
);
435 temp
= rd32(E1000_TOTL
);
436 temp
= rd32(E1000_TOTH
);
437 temp
= rd32(E1000_TPR
);
438 temp
= rd32(E1000_TPT
);
439 temp
= rd32(E1000_MPTC
);
440 temp
= rd32(E1000_BPTC
);
444 * igb_check_for_copper_link - Check for link (Copper)
445 * @hw: pointer to the HW structure
447 * Checks to see of the link status of the hardware has changed. If a
448 * change in link status has been detected, then we read the PHY registers
449 * to get the current speed/duplex if link exists.
451 s32
igb_check_for_copper_link(struct e1000_hw
*hw
)
453 struct e1000_mac_info
*mac
= &hw
->mac
;
458 * We only want to go out to the PHY registers to see if Auto-Neg
459 * has completed and/or if our link status has changed. The
460 * get_link_status flag is set upon receiving a Link Status
461 * Change or Rx Sequence Error interrupt.
463 if (!mac
->get_link_status
) {
469 * First we want to see if the MII Status Register reports
470 * link. If so, then we want to get the current speed/duplex
473 ret_val
= igb_phy_has_link(hw
, 1, 0, &link
);
478 goto out
; /* No link detected */
480 mac
->get_link_status
= false;
483 * Check if there was DownShift, must be checked
484 * immediately after link-up
486 igb_check_downshift(hw
);
489 * If we are forcing speed/duplex, then we simply return since
490 * we have already determined whether we have link or not.
493 ret_val
= -E1000_ERR_CONFIG
;
498 * Auto-Neg is enabled. Auto Speed Detection takes care
499 * of MAC speed/duplex configuration. So we only need to
500 * configure Collision Distance in the MAC.
502 igb_config_collision_dist(hw
);
505 * Configure Flow Control now that Auto-Neg has completed.
506 * First, we need to restore the desired flow control
507 * settings because we may have had to re-autoneg with a
508 * different link partner.
510 ret_val
= igb_config_fc_after_link_up(hw
);
512 hw_dbg("Error configuring flow control\n");
519 * igb_setup_link - Setup flow control and link settings
520 * @hw: pointer to the HW structure
522 * Determines which flow control settings to use, then configures flow
523 * control. Calls the appropriate media-specific link configuration
524 * function. Assuming the adapter has a valid link partner, a valid link
525 * should be established. Assumes the hardware has previously been reset
526 * and the transmitter and receiver are not enabled.
528 s32
igb_setup_link(struct e1000_hw
*hw
)
533 * In the case of the phy reset being blocked, we already have a link.
534 * We do not need to set it up again.
536 if (igb_check_reset_block(hw
))
539 ret_val
= igb_set_default_fc(hw
);
544 * We want to save off the original Flow Control configuration just
545 * in case we get disconnected and then reconnected into a different
546 * hub or switch with different Flow Control capabilities.
548 hw
->fc
.original_type
= hw
->fc
.type
;
550 hw_dbg("After fix-ups FlowControl is now = %x\n", hw
->fc
.type
);
552 /* Call the necessary media_type subroutine to configure the link. */
553 ret_val
= hw
->mac
.ops
.setup_physical_interface(hw
);
558 * Initialize the flow control address, type, and PAUSE timer
559 * registers to their default values. This is done even if flow
560 * control is disabled, because it does not hurt anything to
561 * initialize these registers.
563 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
564 wr32(E1000_FCT
, FLOW_CONTROL_TYPE
);
565 wr32(E1000_FCAH
, FLOW_CONTROL_ADDRESS_HIGH
);
566 wr32(E1000_FCAL
, FLOW_CONTROL_ADDRESS_LOW
);
568 wr32(E1000_FCTTV
, hw
->fc
.pause_time
);
570 ret_val
= igb_set_fc_watermarks(hw
);
577 * igb_config_collision_dist - Configure collision distance
578 * @hw: pointer to the HW structure
580 * Configures the collision distance to the default value and is used
581 * during link setup. Currently no func pointer exists and all
582 * implementations are handled in the generic version of this function.
584 void igb_config_collision_dist(struct e1000_hw
*hw
)
588 tctl
= rd32(E1000_TCTL
);
590 tctl
&= ~E1000_TCTL_COLD
;
591 tctl
|= E1000_COLLISION_DISTANCE
<< E1000_COLD_SHIFT
;
593 wr32(E1000_TCTL
, tctl
);
598 * igb_set_fc_watermarks - Set flow control high/low watermarks
599 * @hw: pointer to the HW structure
601 * Sets the flow control high/low threshold (watermark) registers. If
602 * flow control XON frame transmission is enabled, then set XON frame
603 * tansmission as well.
605 static s32
igb_set_fc_watermarks(struct e1000_hw
*hw
)
608 u32 fcrtl
= 0, fcrth
= 0;
611 * Set the flow control receive threshold registers. Normally,
612 * these registers will be set to a default threshold that may be
613 * adjusted later by the driver's runtime code. However, if the
614 * ability to transmit pause frames is not enabled, then these
615 * registers will be set to 0.
617 if (hw
->fc
.type
& e1000_fc_tx_pause
) {
619 * We need to set up the Receive Threshold high and low water
620 * marks as well as (optionally) enabling the transmission of
623 fcrtl
= hw
->fc
.low_water
;
625 fcrtl
|= E1000_FCRTL_XONE
;
627 fcrth
= hw
->fc
.high_water
;
629 wr32(E1000_FCRTL
, fcrtl
);
630 wr32(E1000_FCRTH
, fcrth
);
636 * igb_set_default_fc - Set flow control default values
637 * @hw: pointer to the HW structure
639 * Read the EEPROM for the default values for flow control and store the
642 static s32
igb_set_default_fc(struct e1000_hw
*hw
)
648 * Read and store word 0x0F of the EEPROM. This word contains bits
649 * that determine the hardware's default PAUSE (flow control) mode,
650 * a bit that determines whether the HW defaults to enabling or
651 * disabling auto-negotiation, and the direction of the
652 * SW defined pins. If there is no SW over-ride of the flow
653 * control setting, then the variable hw->fc will
654 * be initialized based on a value in the EEPROM.
656 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL2_REG
, 1, &nvm_data
);
659 hw_dbg("NVM Read Error\n");
663 if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) == 0)
664 hw
->fc
.type
= e1000_fc_none
;
665 else if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) ==
667 hw
->fc
.type
= e1000_fc_tx_pause
;
669 hw
->fc
.type
= e1000_fc_full
;
676 * igb_force_mac_fc - Force the MAC's flow control settings
677 * @hw: pointer to the HW structure
679 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
680 * device control register to reflect the adapter settings. TFCE and RFCE
681 * need to be explicitly set by software when a copper PHY is used because
682 * autonegotiation is managed by the PHY rather than the MAC. Software must
683 * also configure these bits when link is forced on a fiber connection.
685 s32
igb_force_mac_fc(struct e1000_hw
*hw
)
690 ctrl
= rd32(E1000_CTRL
);
693 * Because we didn't get link via the internal auto-negotiation
694 * mechanism (we either forced link or we got link via PHY
695 * auto-neg), we have to manually enable/disable transmit an
696 * receive flow control.
698 * The "Case" statement below enables/disable flow control
699 * according to the "hw->fc.type" parameter.
701 * The possible values of the "fc" parameter are:
702 * 0: Flow control is completely disabled
703 * 1: Rx flow control is enabled (we can receive pause
704 * frames but not send pause frames).
705 * 2: Tx flow control is enabled (we can send pause frames
706 * frames but we do not receive pause frames).
707 * 3: Both Rx and TX flow control (symmetric) is enabled.
708 * other: No other values should be possible at this point.
710 hw_dbg("hw->fc.type = %u\n", hw
->fc
.type
);
712 switch (hw
->fc
.type
) {
714 ctrl
&= (~(E1000_CTRL_TFCE
| E1000_CTRL_RFCE
));
716 case e1000_fc_rx_pause
:
717 ctrl
&= (~E1000_CTRL_TFCE
);
718 ctrl
|= E1000_CTRL_RFCE
;
720 case e1000_fc_tx_pause
:
721 ctrl
&= (~E1000_CTRL_RFCE
);
722 ctrl
|= E1000_CTRL_TFCE
;
725 ctrl
|= (E1000_CTRL_TFCE
| E1000_CTRL_RFCE
);
728 hw_dbg("Flow control param set incorrectly\n");
729 ret_val
= -E1000_ERR_CONFIG
;
733 wr32(E1000_CTRL
, ctrl
);
740 * igb_config_fc_after_link_up - Configures flow control after link
741 * @hw: pointer to the HW structure
743 * Checks the status of auto-negotiation after link up to ensure that the
744 * speed and duplex were not forced. If the link needed to be forced, then
745 * flow control needs to be forced also. If auto-negotiation is enabled
746 * and did not fail, then we configure flow control based on our link
749 s32
igb_config_fc_after_link_up(struct e1000_hw
*hw
)
751 struct e1000_mac_info
*mac
= &hw
->mac
;
753 u16 mii_status_reg
, mii_nway_adv_reg
, mii_nway_lp_ability_reg
;
757 * Check for the case where we have fiber media and auto-neg failed
758 * so we had to force link. In this case, we need to force the
759 * configuration of the MAC to match the "fc" parameter.
761 if (mac
->autoneg_failed
) {
762 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
763 ret_val
= igb_force_mac_fc(hw
);
765 if (hw
->phy
.media_type
== e1000_media_type_copper
)
766 ret_val
= igb_force_mac_fc(hw
);
770 hw_dbg("Error forcing flow control settings\n");
775 * Check for the case where we have copper media and auto-neg is
776 * enabled. In this case, we need to check and see if Auto-Neg
777 * has completed, and if so, how the PHY and link partner has
778 * flow control configured.
780 if ((hw
->phy
.media_type
== e1000_media_type_copper
) && mac
->autoneg
) {
782 * Read the MII Status Register and check to see if AutoNeg
783 * has completed. We read this twice because this reg has
784 * some "sticky" (latched) bits.
786 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
,
790 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
,
795 if (!(mii_status_reg
& MII_SR_AUTONEG_COMPLETE
)) {
796 hw_dbg("Copper PHY and Auto Neg "
797 "has not completed.\n");
802 * The AutoNeg process has completed, so we now need to
803 * read both the Auto Negotiation Advertisement
804 * Register (Address 4) and the Auto_Negotiation Base
805 * Page Ability Register (Address 5) to determine how
806 * flow control was negotiated.
808 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_AUTONEG_ADV
,
812 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_LP_ABILITY
,
813 &mii_nway_lp_ability_reg
);
818 * Two bits in the Auto Negotiation Advertisement Register
819 * (Address 4) and two bits in the Auto Negotiation Base
820 * Page Ability Register (Address 5) determine flow control
821 * for both the PHY and the link partner. The following
822 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
823 * 1999, describes these PAUSE resolution bits and how flow
824 * control is determined based upon these settings.
825 * NOTE: DC = Don't Care
827 * LOCAL DEVICE | LINK PARTNER
828 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
829 *-------|---------|-------|---------|--------------------
830 * 0 | 0 | DC | DC | e1000_fc_none
831 * 0 | 1 | 0 | DC | e1000_fc_none
832 * 0 | 1 | 1 | 0 | e1000_fc_none
833 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
834 * 1 | 0 | 0 | DC | e1000_fc_none
835 * 1 | DC | 1 | DC | e1000_fc_full
836 * 1 | 1 | 0 | 0 | e1000_fc_none
837 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
839 * Are both PAUSE bits set to 1? If so, this implies
840 * Symmetric Flow Control is enabled at both ends. The
841 * ASM_DIR bits are irrelevant per the spec.
843 * For Symmetric Flow Control:
845 * LOCAL DEVICE | LINK PARTNER
846 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
847 *-------|---------|-------|---------|--------------------
848 * 1 | DC | 1 | DC | E1000_fc_full
851 if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
852 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
)) {
854 * Now we need to check if the user selected RX ONLY
855 * of pause frames. In this case, we had to advertise
856 * FULL flow control because we could not advertise RX
857 * ONLY. Hence, we must now check to see if we need to
858 * turn OFF the TRANSMISSION of PAUSE frames.
860 if (hw
->fc
.original_type
== e1000_fc_full
) {
861 hw
->fc
.type
= e1000_fc_full
;
862 hw_dbg("Flow Control = FULL.\r\n");
864 hw
->fc
.type
= e1000_fc_rx_pause
;
865 hw_dbg("Flow Control = "
866 "RX PAUSE frames only.\r\n");
870 * For receiving PAUSE frames ONLY.
872 * LOCAL DEVICE | LINK PARTNER
873 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
874 *-------|---------|-------|---------|--------------------
875 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
877 else if (!(mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
878 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
879 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
880 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
881 hw
->fc
.type
= e1000_fc_tx_pause
;
882 hw_dbg("Flow Control = TX PAUSE frames only.\r\n");
885 * For transmitting PAUSE frames ONLY.
887 * LOCAL DEVICE | LINK PARTNER
888 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
889 *-------|---------|-------|---------|--------------------
890 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
892 else if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
893 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
894 !(mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
895 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
896 hw
->fc
.type
= e1000_fc_rx_pause
;
897 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
900 * Per the IEEE spec, at this point flow control should be
901 * disabled. However, we want to consider that we could
902 * be connected to a legacy switch that doesn't advertise
903 * desired flow control, but can be forced on the link
904 * partner. So if we advertised no flow control, that is
905 * what we will resolve to. If we advertised some kind of
906 * receive capability (Rx Pause Only or Full Flow Control)
907 * and the link partner advertised none, we will configure
908 * ourselves to enable Rx Flow Control only. We can do
909 * this safely for two reasons: If the link partner really
910 * didn't want flow control enabled, and we enable Rx, no
911 * harm done since we won't be receiving any PAUSE frames
912 * anyway. If the intent on the link partner was to have
913 * flow control enabled, then by us enabling RX only, we
914 * can at least receive pause frames and process them.
915 * This is a good idea because in most cases, since we are
916 * predominantly a server NIC, more times than not we will
917 * be asked to delay transmission of packets than asking
918 * our link partner to pause transmission of frames.
920 else if ((hw
->fc
.original_type
== e1000_fc_none
||
921 hw
->fc
.original_type
== e1000_fc_tx_pause
) ||
922 hw
->fc
.strict_ieee
) {
923 hw
->fc
.type
= e1000_fc_none
;
924 hw_dbg("Flow Control = NONE.\r\n");
926 hw
->fc
.type
= e1000_fc_rx_pause
;
927 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
931 * Now we need to do one last check... If we auto-
932 * negotiated to HALF DUPLEX, flow control should not be
933 * enabled per IEEE 802.3 spec.
935 ret_val
= hw
->mac
.ops
.get_speed_and_duplex(hw
, &speed
, &duplex
);
937 hw_dbg("Error getting link speed and duplex\n");
941 if (duplex
== HALF_DUPLEX
)
942 hw
->fc
.type
= e1000_fc_none
;
945 * Now we call a subroutine to actually force the MAC
946 * controller to use the correct flow control settings.
948 ret_val
= igb_force_mac_fc(hw
);
950 hw_dbg("Error forcing flow control settings\n");
960 * igb_get_speed_and_duplex_copper - Retreive current speed/duplex
961 * @hw: pointer to the HW structure
962 * @speed: stores the current speed
963 * @duplex: stores the current duplex
965 * Read the status register for the current speed/duplex and store the current
966 * speed and duplex for copper connections.
968 s32
igb_get_speed_and_duplex_copper(struct e1000_hw
*hw
, u16
*speed
,
973 status
= rd32(E1000_STATUS
);
974 if (status
& E1000_STATUS_SPEED_1000
) {
976 hw_dbg("1000 Mbs, ");
977 } else if (status
& E1000_STATUS_SPEED_100
) {
985 if (status
& E1000_STATUS_FD
) {
986 *duplex
= FULL_DUPLEX
;
987 hw_dbg("Full Duplex\n");
989 *duplex
= HALF_DUPLEX
;
990 hw_dbg("Half Duplex\n");
997 * igb_get_hw_semaphore - Acquire hardware semaphore
998 * @hw: pointer to the HW structure
1000 * Acquire the HW semaphore to access the PHY or NVM
1002 s32
igb_get_hw_semaphore(struct e1000_hw
*hw
)
1006 s32 timeout
= hw
->nvm
.word_size
+ 1;
1009 /* Get the SW semaphore */
1010 while (i
< timeout
) {
1011 swsm
= rd32(E1000_SWSM
);
1012 if (!(swsm
& E1000_SWSM_SMBI
))
1020 hw_dbg("Driver can't access device - SMBI bit is set.\n");
1021 ret_val
= -E1000_ERR_NVM
;
1025 /* Get the FW semaphore. */
1026 for (i
= 0; i
< timeout
; i
++) {
1027 swsm
= rd32(E1000_SWSM
);
1028 wr32(E1000_SWSM
, swsm
| E1000_SWSM_SWESMBI
);
1030 /* Semaphore acquired if bit latched */
1031 if (rd32(E1000_SWSM
) & E1000_SWSM_SWESMBI
)
1038 /* Release semaphores */
1039 igb_put_hw_semaphore(hw
);
1040 hw_dbg("Driver can't access the NVM\n");
1041 ret_val
= -E1000_ERR_NVM
;
1050 * igb_put_hw_semaphore - Release hardware semaphore
1051 * @hw: pointer to the HW structure
1053 * Release hardware semaphore used to access the PHY or NVM
1055 void igb_put_hw_semaphore(struct e1000_hw
*hw
)
1059 swsm
= rd32(E1000_SWSM
);
1061 swsm
&= ~(E1000_SWSM_SMBI
| E1000_SWSM_SWESMBI
);
1063 wr32(E1000_SWSM
, swsm
);
1067 * igb_get_auto_rd_done - Check for auto read completion
1068 * @hw: pointer to the HW structure
1070 * Check EEPROM for Auto Read done bit.
1072 s32
igb_get_auto_rd_done(struct e1000_hw
*hw
)
1078 while (i
< AUTO_READ_DONE_TIMEOUT
) {
1079 if (rd32(E1000_EECD
) & E1000_EECD_AUTO_RD
)
1085 if (i
== AUTO_READ_DONE_TIMEOUT
) {
1086 hw_dbg("Auto read by HW from NVM has not completed.\n");
1087 ret_val
= -E1000_ERR_RESET
;
1096 * igb_valid_led_default - Verify a valid default LED config
1097 * @hw: pointer to the HW structure
1098 * @data: pointer to the NVM (EEPROM)
1100 * Read the EEPROM for the current default LED configuration. If the
1101 * LED configuration is not valid, set to a valid LED configuration.
1103 static s32
igb_valid_led_default(struct e1000_hw
*hw
, u16
*data
)
1107 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1109 hw_dbg("NVM Read Error\n");
1113 if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
) {
1114 switch(hw
->phy
.media_type
) {
1115 case e1000_media_type_internal_serdes
:
1116 *data
= ID_LED_DEFAULT_82575_SERDES
;
1118 case e1000_media_type_copper
:
1120 *data
= ID_LED_DEFAULT
;
1130 * @hw: pointer to the HW structure
1133 s32
igb_id_led_init(struct e1000_hw
*hw
)
1135 struct e1000_mac_info
*mac
= &hw
->mac
;
1137 const u32 ledctl_mask
= 0x000000FF;
1138 const u32 ledctl_on
= E1000_LEDCTL_MODE_LED_ON
;
1139 const u32 ledctl_off
= E1000_LEDCTL_MODE_LED_OFF
;
1141 const u16 led_mask
= 0x0F;
1143 ret_val
= igb_valid_led_default(hw
, &data
);
1147 mac
->ledctl_default
= rd32(E1000_LEDCTL
);
1148 mac
->ledctl_mode1
= mac
->ledctl_default
;
1149 mac
->ledctl_mode2
= mac
->ledctl_default
;
1151 for (i
= 0; i
< 4; i
++) {
1152 temp
= (data
>> (i
<< 2)) & led_mask
;
1154 case ID_LED_ON1_DEF2
:
1155 case ID_LED_ON1_ON2
:
1156 case ID_LED_ON1_OFF2
:
1157 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1158 mac
->ledctl_mode1
|= ledctl_on
<< (i
<< 3);
1160 case ID_LED_OFF1_DEF2
:
1161 case ID_LED_OFF1_ON2
:
1162 case ID_LED_OFF1_OFF2
:
1163 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1164 mac
->ledctl_mode1
|= ledctl_off
<< (i
<< 3);
1171 case ID_LED_DEF1_ON2
:
1172 case ID_LED_ON1_ON2
:
1173 case ID_LED_OFF1_ON2
:
1174 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1175 mac
->ledctl_mode2
|= ledctl_on
<< (i
<< 3);
1177 case ID_LED_DEF1_OFF2
:
1178 case ID_LED_ON1_OFF2
:
1179 case ID_LED_OFF1_OFF2
:
1180 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1181 mac
->ledctl_mode2
|= ledctl_off
<< (i
<< 3);
1194 * igb_cleanup_led - Set LED config to default operation
1195 * @hw: pointer to the HW structure
1197 * Remove the current LED configuration and set the LED configuration
1198 * to the default value, saved from the EEPROM.
1200 s32
igb_cleanup_led(struct e1000_hw
*hw
)
1202 wr32(E1000_LEDCTL
, hw
->mac
.ledctl_default
);
1207 * igb_blink_led - Blink LED
1208 * @hw: pointer to the HW structure
1210 * Blink the led's which are set to be on.
1212 s32
igb_blink_led(struct e1000_hw
*hw
)
1214 u32 ledctl_blink
= 0;
1218 * set the blink bit for each LED that's "on" (0x0E)
1221 ledctl_blink
= hw
->mac
.ledctl_mode2
;
1222 for (i
= 0; i
< 4; i
++)
1223 if (((hw
->mac
.ledctl_mode2
>> (i
* 8)) & 0xFF) ==
1224 E1000_LEDCTL_MODE_LED_ON
)
1225 ledctl_blink
|= (E1000_LEDCTL_LED0_BLINK
<<
1228 wr32(E1000_LEDCTL
, ledctl_blink
);
1234 * igb_led_off - Turn LED off
1235 * @hw: pointer to the HW structure
1239 s32
igb_led_off(struct e1000_hw
*hw
)
1241 switch (hw
->phy
.media_type
) {
1242 case e1000_media_type_copper
:
1243 wr32(E1000_LEDCTL
, hw
->mac
.ledctl_mode1
);
1253 * igb_disable_pcie_master - Disables PCI-express master access
1254 * @hw: pointer to the HW structure
1256 * Returns 0 (0) if successful, else returns -10
1257 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued
1258 * the master requests to be disabled.
1260 * Disables PCI-Express master access and verifies there are no pending
1263 s32
igb_disable_pcie_master(struct e1000_hw
*hw
)
1266 s32 timeout
= MASTER_DISABLE_TIMEOUT
;
1269 if (hw
->bus
.type
!= e1000_bus_type_pci_express
)
1272 ctrl
= rd32(E1000_CTRL
);
1273 ctrl
|= E1000_CTRL_GIO_MASTER_DISABLE
;
1274 wr32(E1000_CTRL
, ctrl
);
1277 if (!(rd32(E1000_STATUS
) &
1278 E1000_STATUS_GIO_MASTER_ENABLE
))
1285 hw_dbg("Master requests are pending.\n");
1286 ret_val
= -E1000_ERR_MASTER_REQUESTS_PENDING
;
1295 * igb_reset_adaptive - Reset Adaptive Interframe Spacing
1296 * @hw: pointer to the HW structure
1298 * Reset the Adaptive Interframe Spacing throttle to default values.
1300 void igb_reset_adaptive(struct e1000_hw
*hw
)
1302 struct e1000_mac_info
*mac
= &hw
->mac
;
1304 if (!mac
->adaptive_ifs
) {
1305 hw_dbg("Not in Adaptive IFS mode!\n");
1309 if (!mac
->ifs_params_forced
) {
1310 mac
->current_ifs_val
= 0;
1311 mac
->ifs_min_val
= IFS_MIN
;
1312 mac
->ifs_max_val
= IFS_MAX
;
1313 mac
->ifs_step_size
= IFS_STEP
;
1314 mac
->ifs_ratio
= IFS_RATIO
;
1317 mac
->in_ifs_mode
= false;
1324 * igb_update_adaptive - Update Adaptive Interframe Spacing
1325 * @hw: pointer to the HW structure
1327 * Update the Adaptive Interframe Spacing Throttle value based on the
1328 * time between transmitted packets and time between collisions.
1330 void igb_update_adaptive(struct e1000_hw
*hw
)
1332 struct e1000_mac_info
*mac
= &hw
->mac
;
1334 if (!mac
->adaptive_ifs
) {
1335 hw_dbg("Not in Adaptive IFS mode!\n");
1339 if ((mac
->collision_delta
* mac
->ifs_ratio
) > mac
->tx_packet_delta
) {
1340 if (mac
->tx_packet_delta
> MIN_NUM_XMITS
) {
1341 mac
->in_ifs_mode
= true;
1342 if (mac
->current_ifs_val
< mac
->ifs_max_val
) {
1343 if (!mac
->current_ifs_val
)
1344 mac
->current_ifs_val
= mac
->ifs_min_val
;
1346 mac
->current_ifs_val
+=
1349 mac
->current_ifs_val
);
1353 if (mac
->in_ifs_mode
&&
1354 (mac
->tx_packet_delta
<= MIN_NUM_XMITS
)) {
1355 mac
->current_ifs_val
= 0;
1356 mac
->in_ifs_mode
= false;
1365 * igb_validate_mdi_setting - Verify MDI/MDIx settings
1366 * @hw: pointer to the HW structure
1368 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
1369 * set, which is forced to MDI mode only.
1371 s32
igb_validate_mdi_setting(struct e1000_hw
*hw
)
1375 if (!hw
->mac
.autoneg
&& (hw
->phy
.mdix
== 0 || hw
->phy
.mdix
== 3)) {
1376 hw_dbg("Invalid MDI setting detected\n");
1378 ret_val
= -E1000_ERR_CONFIG
;
1387 * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
1388 * @hw: pointer to the HW structure
1389 * @reg: 32bit register offset such as E1000_SCTL
1390 * @offset: register offset to write to
1391 * @data: data to write at register offset
1393 * Writes an address/data control type register. There are several of these
1394 * and they all have the format address << 8 | data and bit 31 is polled for
1397 s32
igb_write_8bit_ctrl_reg(struct e1000_hw
*hw
, u32 reg
,
1398 u32 offset
, u8 data
)
1400 u32 i
, regvalue
= 0;
1403 /* Set up the address and data */
1404 regvalue
= ((u32
)data
) | (offset
<< E1000_GEN_CTL_ADDRESS_SHIFT
);
1405 wr32(reg
, regvalue
);
1407 /* Poll the ready bit to see if the MDI read completed */
1408 for (i
= 0; i
< E1000_GEN_POLL_TIMEOUT
; i
++) {
1410 regvalue
= rd32(reg
);
1411 if (regvalue
& E1000_GEN_CTL_READY
)
1414 if (!(regvalue
& E1000_GEN_CTL_READY
)) {
1415 hw_dbg("Reg %08x did not indicate ready\n", reg
);
1416 ret_val
= -E1000_ERR_PHY
;
1425 * igb_enable_mng_pass_thru - Enable processing of ARP's
1426 * @hw: pointer to the HW structure
1428 * Verifies the hardware needs to allow ARPs to be processed by the host.
1430 bool igb_enable_mng_pass_thru(struct e1000_hw
*hw
)
1434 bool ret_val
= false;
1436 if (!hw
->mac
.asf_firmware_present
)
1439 manc
= rd32(E1000_MANC
);
1441 if (!(manc
& E1000_MANC_RCV_TCO_EN
) ||
1442 !(manc
& E1000_MANC_EN_MAC_ADDR_FILTER
))
1445 if (hw
->mac
.arc_subsystem_valid
) {
1446 fwsm
= rd32(E1000_FWSM
);
1447 factps
= rd32(E1000_FACTPS
);
1449 if (!(factps
& E1000_FACTPS_MNGCG
) &&
1450 ((fwsm
& E1000_FWSM_MODE_MASK
) ==
1451 (e1000_mng_mode_pt
<< E1000_FWSM_MODE_SHIFT
))) {
1456 if ((manc
& E1000_MANC_SMBUS_EN
) &&
1457 !(manc
& E1000_MANC_ASF_EN
)) {