1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/slab.h>
34 #include <linux/if_ether.h>
36 #include "e1000_mac.h"
37 #include "e1000_82575.h"
39 static s32
igb_get_invariants_82575(struct e1000_hw
*);
40 static s32
igb_acquire_phy_82575(struct e1000_hw
*);
41 static void igb_release_phy_82575(struct e1000_hw
*);
42 static s32
igb_acquire_nvm_82575(struct e1000_hw
*);
43 static void igb_release_nvm_82575(struct e1000_hw
*);
44 static s32
igb_check_for_link_82575(struct e1000_hw
*);
45 static s32
igb_get_cfg_done_82575(struct e1000_hw
*);
46 static s32
igb_init_hw_82575(struct e1000_hw
*);
47 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*);
48 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
*);
49 static s32
igb_reset_hw_82575(struct e1000_hw
*);
50 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*, bool);
51 static s32
igb_setup_copper_link_82575(struct e1000_hw
*);
52 static s32
igb_setup_fiber_serdes_link_82575(struct e1000_hw
*);
53 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
);
54 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*);
55 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*, u16
);
56 static void igb_configure_pcs_link_82575(struct e1000_hw
*);
57 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*, u16
*,
59 static s32
igb_get_phy_id_82575(struct e1000_hw
*);
60 static void igb_release_swfw_sync_82575(struct e1000_hw
*, u16
);
61 static bool igb_sgmii_active_82575(struct e1000_hw
*);
62 static s32
igb_reset_init_script_82575(struct e1000_hw
*);
63 static s32
igb_read_mac_addr_82575(struct e1000_hw
*);
64 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
);
66 static s32
igb_get_invariants_82575(struct e1000_hw
*hw
)
68 struct e1000_phy_info
*phy
= &hw
->phy
;
69 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
70 struct e1000_mac_info
*mac
= &hw
->mac
;
71 struct e1000_dev_spec_82575
* dev_spec
= &hw
->dev_spec
._82575
;
77 switch (hw
->device_id
) {
78 case E1000_DEV_ID_82575EB_COPPER
:
79 case E1000_DEV_ID_82575EB_FIBER_SERDES
:
80 case E1000_DEV_ID_82575GB_QUAD_COPPER
:
81 mac
->type
= e1000_82575
;
83 case E1000_DEV_ID_82576
:
84 case E1000_DEV_ID_82576_NS
:
85 case E1000_DEV_ID_82576_FIBER
:
86 case E1000_DEV_ID_82576_SERDES
:
87 case E1000_DEV_ID_82576_QUAD_COPPER
:
88 mac
->type
= e1000_82576
;
91 return -E1000_ERR_MAC_INIT
;
97 * The 82575 uses bits 22:23 for link mode. The mode can be changed
98 * based on the EEPROM. We cannot rely upon device ID. There
99 * is no distinguishable difference between fiber and internal
100 * SerDes mode on the 82575. There can be an external PHY attached
101 * on the SGMII interface. For this, we'll set sgmii_active to true.
103 phy
->media_type
= e1000_media_type_copper
;
104 dev_spec
->sgmii_active
= false;
106 ctrl_ext
= rd32(E1000_CTRL_EXT
);
107 if ((ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
) ==
108 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES
) {
109 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
110 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
111 } else if (ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_SGMII
) {
112 dev_spec
->sgmii_active
= true;
113 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
115 ctrl_ext
&= ~E1000_CTRL_I2C_ENA
;
117 wr32(E1000_CTRL_EXT
, ctrl_ext
);
119 /* Set mta register count */
120 mac
->mta_reg_count
= 128;
121 /* Set rar entry count */
122 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82575
;
123 if (mac
->type
== e1000_82576
)
124 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82576
;
125 /* Set if part includes ASF firmware */
126 mac
->asf_firmware_present
= true;
127 /* Set if manageability features are enabled. */
128 mac
->arc_subsystem_valid
=
129 (rd32(E1000_FWSM
) & E1000_FWSM_MODE_MASK
)
132 /* physical interface link setup */
133 mac
->ops
.setup_physical_interface
=
134 (hw
->phy
.media_type
== e1000_media_type_copper
)
135 ? igb_setup_copper_link_82575
136 : igb_setup_fiber_serdes_link_82575
;
138 /* NVM initialization */
139 eecd
= rd32(E1000_EECD
);
141 nvm
->opcode_bits
= 8;
143 switch (nvm
->override
) {
144 case e1000_nvm_override_spi_large
:
146 nvm
->address_bits
= 16;
148 case e1000_nvm_override_spi_small
:
150 nvm
->address_bits
= 8;
153 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
154 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
? 16 : 8;
158 nvm
->type
= e1000_nvm_eeprom_spi
;
160 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
161 E1000_EECD_SIZE_EX_SHIFT
);
164 * Added to a constant, "size" becomes the left-shift value
165 * for setting word_size.
167 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
169 /* EEPROM access above 16k is unsupported */
172 nvm
->word_size
= 1 << size
;
174 /* setup PHY parameters */
175 if (phy
->media_type
!= e1000_media_type_copper
) {
176 phy
->type
= e1000_phy_none
;
180 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
181 phy
->reset_delay_us
= 100;
183 /* PHY function pointers */
184 if (igb_sgmii_active_82575(hw
)) {
185 phy
->ops
.reset
= igb_phy_hw_reset_sgmii_82575
;
186 phy
->ops
.read_reg
= igb_read_phy_reg_sgmii_82575
;
187 phy
->ops
.write_reg
= igb_write_phy_reg_sgmii_82575
;
189 phy
->ops
.reset
= igb_phy_hw_reset
;
190 phy
->ops
.read_reg
= igb_read_phy_reg_igp
;
191 phy
->ops
.write_reg
= igb_write_phy_reg_igp
;
195 hw
->bus
.func
= (rd32(E1000_STATUS
) & E1000_STATUS_FUNC_MASK
) >>
196 E1000_STATUS_FUNC_SHIFT
;
198 /* Set phy->phy_addr and phy->id. */
199 ret_val
= igb_get_phy_id_82575(hw
);
203 /* Verify phy id and set remaining function pointers */
205 case M88E1111_I_PHY_ID
:
206 phy
->type
= e1000_phy_m88
;
207 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
208 phy
->ops
.get_cable_length
= igb_get_cable_length_m88
;
209 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
211 case IGP03E1000_E_PHY_ID
:
212 phy
->type
= e1000_phy_igp_3
;
213 phy
->ops
.get_phy_info
= igb_get_phy_info_igp
;
214 phy
->ops
.get_cable_length
= igb_get_cable_length_igp_2
;
215 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_igp
;
216 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82575
;
217 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state
;
220 return -E1000_ERR_PHY
;
223 /* if 82576 then initialize mailbox parameters */
224 if (mac
->type
== e1000_82576
)
225 igb_init_mbx_params_pf(hw
);
231 * igb_acquire_phy_82575 - Acquire rights to access PHY
232 * @hw: pointer to the HW structure
234 * Acquire access rights to the correct PHY. This is a
235 * function pointer entry point called by the api module.
237 static s32
igb_acquire_phy_82575(struct e1000_hw
*hw
)
241 mask
= hw
->bus
.func
? E1000_SWFW_PHY1_SM
: E1000_SWFW_PHY0_SM
;
243 return igb_acquire_swfw_sync_82575(hw
, mask
);
247 * igb_release_phy_82575 - Release rights to access PHY
248 * @hw: pointer to the HW structure
250 * A wrapper to release access rights to the correct PHY. This is a
251 * function pointer entry point called by the api module.
253 static void igb_release_phy_82575(struct e1000_hw
*hw
)
257 mask
= hw
->bus
.func
? E1000_SWFW_PHY1_SM
: E1000_SWFW_PHY0_SM
;
258 igb_release_swfw_sync_82575(hw
, mask
);
262 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
263 * @hw: pointer to the HW structure
264 * @offset: register offset to be read
265 * @data: pointer to the read data
267 * Reads the PHY register at offset using the serial gigabit media independent
268 * interface and stores the retrieved information in data.
270 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
273 struct e1000_phy_info
*phy
= &hw
->phy
;
276 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
277 hw_dbg("PHY Address %u is out of range\n", offset
);
278 return -E1000_ERR_PARAM
;
282 * Set up Op-code, Phy Address, and register address in the I2CCMD
283 * register. The MAC will take care of interfacing with the
284 * PHY to retrieve the desired data.
286 i2ccmd
= ((offset
<< E1000_I2CCMD_REG_ADDR_SHIFT
) |
287 (phy
->addr
<< E1000_I2CCMD_PHY_ADDR_SHIFT
) |
288 (E1000_I2CCMD_OPCODE_READ
));
290 wr32(E1000_I2CCMD
, i2ccmd
);
292 /* Poll the ready bit to see if the I2C read completed */
293 for (i
= 0; i
< E1000_I2CCMD_PHY_TIMEOUT
; i
++) {
295 i2ccmd
= rd32(E1000_I2CCMD
);
296 if (i2ccmd
& E1000_I2CCMD_READY
)
299 if (!(i2ccmd
& E1000_I2CCMD_READY
)) {
300 hw_dbg("I2CCMD Read did not complete\n");
301 return -E1000_ERR_PHY
;
303 if (i2ccmd
& E1000_I2CCMD_ERROR
) {
304 hw_dbg("I2CCMD Error bit set\n");
305 return -E1000_ERR_PHY
;
308 /* Need to byte-swap the 16-bit value. */
309 *data
= ((i2ccmd
>> 8) & 0x00FF) | ((i2ccmd
<< 8) & 0xFF00);
315 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
316 * @hw: pointer to the HW structure
317 * @offset: register offset to write to
318 * @data: data to write at register offset
320 * Writes the data to PHY register at the offset using the serial gigabit
321 * media independent interface.
323 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
326 struct e1000_phy_info
*phy
= &hw
->phy
;
328 u16 phy_data_swapped
;
330 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
331 hw_dbg("PHY Address %d is out of range\n", offset
);
332 return -E1000_ERR_PARAM
;
335 /* Swap the data bytes for the I2C interface */
336 phy_data_swapped
= ((data
>> 8) & 0x00FF) | ((data
<< 8) & 0xFF00);
339 * Set up Op-code, Phy Address, and register address in the I2CCMD
340 * register. The MAC will take care of interfacing with the
341 * PHY to retrieve the desired data.
343 i2ccmd
= ((offset
<< E1000_I2CCMD_REG_ADDR_SHIFT
) |
344 (phy
->addr
<< E1000_I2CCMD_PHY_ADDR_SHIFT
) |
345 E1000_I2CCMD_OPCODE_WRITE
|
348 wr32(E1000_I2CCMD
, i2ccmd
);
350 /* Poll the ready bit to see if the I2C read completed */
351 for (i
= 0; i
< E1000_I2CCMD_PHY_TIMEOUT
; i
++) {
353 i2ccmd
= rd32(E1000_I2CCMD
);
354 if (i2ccmd
& E1000_I2CCMD_READY
)
357 if (!(i2ccmd
& E1000_I2CCMD_READY
)) {
358 hw_dbg("I2CCMD Write did not complete\n");
359 return -E1000_ERR_PHY
;
361 if (i2ccmd
& E1000_I2CCMD_ERROR
) {
362 hw_dbg("I2CCMD Error bit set\n");
363 return -E1000_ERR_PHY
;
370 * igb_get_phy_id_82575 - Retrieve PHY addr and id
371 * @hw: pointer to the HW structure
373 * Retrieves the PHY address and ID for both PHY's which do and do not use
376 static s32
igb_get_phy_id_82575(struct e1000_hw
*hw
)
378 struct e1000_phy_info
*phy
= &hw
->phy
;
383 * For SGMII PHYs, we try the list of possible addresses until
384 * we find one that works. For non-SGMII PHYs
385 * (e.g. integrated copper PHYs), an address of 1 should
386 * work. The result of this function should mean phy->phy_addr
387 * and phy->id are set correctly.
389 if (!(igb_sgmii_active_82575(hw
))) {
391 ret_val
= igb_get_phy_id(hw
);
396 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
397 * Therefore, we need to test 1-7
399 for (phy
->addr
= 1; phy
->addr
< 8; phy
->addr
++) {
400 ret_val
= igb_read_phy_reg_sgmii_82575(hw
, PHY_ID1
, &phy_id
);
402 hw_dbg("Vendor ID 0x%08X read at address %u\n",
405 * At the time of this writing, The M88 part is
406 * the only supported SGMII PHY product.
408 if (phy_id
== M88_VENDOR
)
411 hw_dbg("PHY address %u was unreadable\n", phy
->addr
);
415 /* A valid PHY type couldn't be found. */
416 if (phy
->addr
== 8) {
418 ret_val
= -E1000_ERR_PHY
;
422 ret_val
= igb_get_phy_id(hw
);
429 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
430 * @hw: pointer to the HW structure
432 * Resets the PHY using the serial gigabit media independent interface.
434 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*hw
)
439 * This isn't a true "hard" reset, but is the only reset
440 * available to us at this time.
443 hw_dbg("Soft resetting SGMII attached PHY...\n");
446 * SFP documentation requires the following to configure the SPF module
447 * to work on SGMII. No further documentation is given.
449 ret_val
= hw
->phy
.ops
.write_reg(hw
, 0x1B, 0x8084);
453 ret_val
= igb_phy_sw_reset(hw
);
460 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
461 * @hw: pointer to the HW structure
462 * @active: true to enable LPLU, false to disable
464 * Sets the LPLU D0 state according to the active flag. When
465 * activating LPLU this function also disables smart speed
466 * and vice versa. LPLU will not be activated unless the
467 * device autonegotiation advertisement meets standards of
468 * either 10 or 10/100 or 10/100/1000 at all duplexes.
469 * This is a function pointer entry point only called by
470 * PHY setup routines.
472 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*hw
, bool active
)
474 struct e1000_phy_info
*phy
= &hw
->phy
;
478 ret_val
= phy
->ops
.read_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
483 data
|= IGP02E1000_PM_D0_LPLU
;
484 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
489 /* When LPLU is enabled, we should disable SmartSpeed */
490 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
492 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
493 ret_val
= phy
->ops
.write_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
498 data
&= ~IGP02E1000_PM_D0_LPLU
;
499 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
502 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
503 * during Dx states where the power conservation is most
504 * important. During driver activity we should enable
505 * SmartSpeed, so performance is maintained.
507 if (phy
->smart_speed
== e1000_smart_speed_on
) {
508 ret_val
= phy
->ops
.read_reg(hw
,
509 IGP01E1000_PHY_PORT_CONFIG
, &data
);
513 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
514 ret_val
= phy
->ops
.write_reg(hw
,
515 IGP01E1000_PHY_PORT_CONFIG
, data
);
518 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
519 ret_val
= phy
->ops
.read_reg(hw
,
520 IGP01E1000_PHY_PORT_CONFIG
, &data
);
524 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
525 ret_val
= phy
->ops
.write_reg(hw
,
526 IGP01E1000_PHY_PORT_CONFIG
, data
);
537 * igb_acquire_nvm_82575 - Request for access to EEPROM
538 * @hw: pointer to the HW structure
540 * Acquire the necessary semaphores for exclusive access to the EEPROM.
541 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
542 * Return successful if access grant bit set, else clear the request for
543 * EEPROM access and return -E1000_ERR_NVM (-1).
545 static s32
igb_acquire_nvm_82575(struct e1000_hw
*hw
)
549 ret_val
= igb_acquire_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
553 ret_val
= igb_acquire_nvm(hw
);
556 igb_release_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
563 * igb_release_nvm_82575 - Release exclusive access to EEPROM
564 * @hw: pointer to the HW structure
566 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
567 * then release the semaphores acquired.
569 static void igb_release_nvm_82575(struct e1000_hw
*hw
)
572 igb_release_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
576 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
577 * @hw: pointer to the HW structure
578 * @mask: specifies which semaphore to acquire
580 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
581 * will also specify which port we're acquiring the lock for.
583 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
587 u32 fwmask
= mask
<< 16;
589 s32 i
= 0, timeout
= 200; /* FIXME: find real value to use here */
591 while (i
< timeout
) {
592 if (igb_get_hw_semaphore(hw
)) {
593 ret_val
= -E1000_ERR_SWFW_SYNC
;
597 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
598 if (!(swfw_sync
& (fwmask
| swmask
)))
602 * Firmware currently using resource (fwmask)
603 * or other software thread using resource (swmask)
605 igb_put_hw_semaphore(hw
);
611 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
612 ret_val
= -E1000_ERR_SWFW_SYNC
;
617 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
619 igb_put_hw_semaphore(hw
);
626 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
627 * @hw: pointer to the HW structure
628 * @mask: specifies which semaphore to acquire
630 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
631 * will also specify which port we're releasing the lock for.
633 static void igb_release_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
637 while (igb_get_hw_semaphore(hw
) != 0);
640 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
642 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
644 igb_put_hw_semaphore(hw
);
648 * igb_get_cfg_done_82575 - Read config done bit
649 * @hw: pointer to the HW structure
651 * Read the management control register for the config done bit for
652 * completion status. NOTE: silicon which is EEPROM-less will fail trying
653 * to read the config done bit, so an error is *ONLY* logged and returns
654 * 0. If we were to return with error, EEPROM-less silicon
655 * would not be able to be reset or change link.
657 static s32
igb_get_cfg_done_82575(struct e1000_hw
*hw
)
659 s32 timeout
= PHY_CFG_TIMEOUT
;
661 u32 mask
= E1000_NVM_CFG_DONE_PORT_0
;
663 if (hw
->bus
.func
== 1)
664 mask
= E1000_NVM_CFG_DONE_PORT_1
;
667 if (rd32(E1000_EEMNGCTL
) & mask
)
673 hw_dbg("MNG configuration cycle has not completed.\n");
675 /* If EEPROM is not marked present, init the PHY manually */
676 if (((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0) &&
677 (hw
->phy
.type
== e1000_phy_igp_3
))
678 igb_phy_init_script_igp3(hw
);
684 * igb_check_for_link_82575 - Check for link
685 * @hw: pointer to the HW structure
687 * If sgmii is enabled, then use the pcs register to determine link, otherwise
688 * use the generic interface for determining link.
690 static s32
igb_check_for_link_82575(struct e1000_hw
*hw
)
695 /* SGMII link check is done through the PCS register. */
696 if ((hw
->phy
.media_type
!= e1000_media_type_copper
) ||
697 (igb_sgmii_active_82575(hw
))) {
698 ret_val
= igb_get_pcs_speed_and_duplex_82575(hw
, &speed
,
701 * Use this flag to determine if link needs to be checked or
702 * not. If we have link clear the flag so that we do not
703 * continue to check for link.
705 hw
->mac
.get_link_status
= !hw
->mac
.serdes_has_link
;
707 ret_val
= igb_check_for_copper_link(hw
);
713 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
714 * @hw: pointer to the HW structure
715 * @speed: stores the current speed
716 * @duplex: stores the current duplex
718 * Using the physical coding sub-layer (PCS), retrieve the current speed and
719 * duplex, then store the values in the pointers provided.
721 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*hw
, u16
*speed
,
724 struct e1000_mac_info
*mac
= &hw
->mac
;
727 /* Set up defaults for the return values of this function */
728 mac
->serdes_has_link
= false;
733 * Read the PCS Status register for link state. For non-copper mode,
734 * the status register is not accurate. The PCS status register is
737 pcs
= rd32(E1000_PCS_LSTAT
);
740 * The link up bit determines when link is up on autoneg. The sync ok
741 * gets set once both sides sync up and agree upon link. Stable link
742 * can be determined by checking for both link up and link sync ok
744 if ((pcs
& E1000_PCS_LSTS_LINK_OK
) && (pcs
& E1000_PCS_LSTS_SYNK_OK
)) {
745 mac
->serdes_has_link
= true;
747 /* Detect and store PCS speed */
748 if (pcs
& E1000_PCS_LSTS_SPEED_1000
) {
750 } else if (pcs
& E1000_PCS_LSTS_SPEED_100
) {
756 /* Detect and store PCS duplex */
757 if (pcs
& E1000_PCS_LSTS_DUPLEX_FULL
) {
758 *duplex
= FULL_DUPLEX
;
760 *duplex
= HALF_DUPLEX
;
768 * igb_shutdown_fiber_serdes_link_82575 - Remove link during power down
769 * @hw: pointer to the HW structure
771 * In the case of fiber serdes, shut down optics and PCS on driver unload
772 * when management pass thru is not enabled.
774 void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw
*hw
)
778 if (hw
->phy
.media_type
!= e1000_media_type_internal_serdes
)
781 /* if the management interface is not enabled, then power down */
782 if (!igb_enable_mng_pass_thru(hw
)) {
783 /* Disable PCS to turn off link */
784 reg
= rd32(E1000_PCS_CFG0
);
785 reg
&= ~E1000_PCS_CFG_PCS_EN
;
786 wr32(E1000_PCS_CFG0
, reg
);
788 /* shutdown the laser */
789 reg
= rd32(E1000_CTRL_EXT
);
790 reg
|= E1000_CTRL_EXT_SDP7_DATA
;
791 wr32(E1000_CTRL_EXT
, reg
);
793 /* flush the write to verify completion */
802 * igb_reset_hw_82575 - Reset hardware
803 * @hw: pointer to the HW structure
805 * This resets the hardware into a known state. This is a
806 * function pointer entry point called by the api module.
808 static s32
igb_reset_hw_82575(struct e1000_hw
*hw
)
814 * Prevent the PCI-E bus from sticking if there is no TLP connection
815 * on the last TLP read/write transaction when MAC is reset.
817 ret_val
= igb_disable_pcie_master(hw
);
819 hw_dbg("PCI-E Master disable polling has failed.\n");
821 /* set the completion timeout for interface */
822 ret_val
= igb_set_pcie_completion_timeout(hw
);
824 hw_dbg("PCI-E Set completion timeout has failed.\n");
827 hw_dbg("Masking off all interrupts\n");
828 wr32(E1000_IMC
, 0xffffffff);
831 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
836 ctrl
= rd32(E1000_CTRL
);
838 hw_dbg("Issuing a global reset to MAC\n");
839 wr32(E1000_CTRL
, ctrl
| E1000_CTRL_RST
);
841 ret_val
= igb_get_auto_rd_done(hw
);
844 * When auto config read does not complete, do not
845 * return with an error. This can happen in situations
846 * where there is no eeprom and prevents getting link.
848 hw_dbg("Auto Read Done did not complete\n");
851 /* If EEPROM is not present, run manual init scripts */
852 if ((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0)
853 igb_reset_init_script_82575(hw
);
855 /* Clear any pending interrupt events. */
856 wr32(E1000_IMC
, 0xffffffff);
857 icr
= rd32(E1000_ICR
);
859 /* Install any alternate MAC address into RAR0 */
860 ret_val
= igb_check_alt_mac_addr(hw
);
866 * igb_init_hw_82575 - Initialize hardware
867 * @hw: pointer to the HW structure
869 * This inits the hardware readying it for operation.
871 static s32
igb_init_hw_82575(struct e1000_hw
*hw
)
873 struct e1000_mac_info
*mac
= &hw
->mac
;
875 u16 i
, rar_count
= mac
->rar_entry_count
;
877 /* Initialize identification LED */
878 ret_val
= igb_id_led_init(hw
);
880 hw_dbg("Error initializing identification LED\n");
881 /* This is not fatal and we should not stop init due to this */
884 /* Disabling VLAN filtering */
885 hw_dbg("Initializing the IEEE VLAN\n");
888 /* Setup the receive address */
889 igb_init_rx_addrs(hw
, rar_count
);
891 /* Zero out the Multicast HASH table */
892 hw_dbg("Zeroing the MTA\n");
893 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
894 array_wr32(E1000_MTA
, i
, 0);
896 /* Setup link and flow control */
897 ret_val
= igb_setup_link(hw
);
900 * Clear all of the statistics registers (clear on read). It is
901 * important that we do this after we have tried to establish link
902 * because the symbol error count will increment wildly if there
905 igb_clear_hw_cntrs_82575(hw
);
911 * igb_setup_copper_link_82575 - Configure copper link settings
912 * @hw: pointer to the HW structure
914 * Configures the link for auto-neg or forced speed and duplex. Then we check
915 * for link, once link is established calls to configure collision distance
916 * and flow control are called.
918 static s32
igb_setup_copper_link_82575(struct e1000_hw
*hw
)
924 ctrl
= rd32(E1000_CTRL
);
925 ctrl
|= E1000_CTRL_SLU
;
926 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
927 wr32(E1000_CTRL
, ctrl
);
929 switch (hw
->phy
.type
) {
931 ret_val
= igb_copper_link_setup_m88(hw
);
933 case e1000_phy_igp_3
:
934 ret_val
= igb_copper_link_setup_igp(hw
);
937 ret_val
= -E1000_ERR_PHY
;
944 if (hw
->mac
.autoneg
) {
946 * Setup autoneg and flow control advertisement
947 * and perform autonegotiation.
949 ret_val
= igb_copper_link_autoneg(hw
);
954 * PHY will be set to 10H, 10F, 100H or 100F
955 * depending on user settings.
957 hw_dbg("Forcing Speed and Duplex\n");
958 ret_val
= hw
->phy
.ops
.force_speed_duplex(hw
);
960 hw_dbg("Error Forcing Speed and Duplex\n");
965 igb_configure_pcs_link_82575(hw
);
968 * Check link status. Wait up to 100 microseconds for link to become
971 ret_val
= igb_phy_has_link(hw
, COPPER_LINK_UP_LIMIT
, 10, &link
);
976 hw_dbg("Valid link established!!!\n");
977 /* Config the MAC and PHY after link is up */
978 igb_config_collision_dist(hw
);
979 ret_val
= igb_config_fc_after_link_up(hw
);
981 hw_dbg("Unable to establish link!!!\n");
989 * igb_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
990 * @hw: pointer to the HW structure
992 * Configures speed and duplex for fiber and serdes links.
994 static s32
igb_setup_fiber_serdes_link_82575(struct e1000_hw
*hw
)
999 * On the 82575, SerDes loopback mode persists until it is
1000 * explicitly turned off or a power cycle is performed. A read to
1001 * the register does not indicate its status. Therefore, we ensure
1002 * loopback mode is disabled during initialization.
1004 wr32(E1000_SCTL
, E1000_SCTL_DISABLE_SERDES_LOOPBACK
);
1006 /* Force link up, set 1gb, set both sw defined pins */
1007 reg
= rd32(E1000_CTRL
);
1008 reg
|= E1000_CTRL_SLU
|
1009 E1000_CTRL_SPD_1000
|
1011 E1000_CTRL_SWDPIN0
|
1013 wr32(E1000_CTRL
, reg
);
1015 /* Power on phy for 82576 fiber adapters */
1016 if (hw
->mac
.type
== e1000_82576
) {
1017 reg
= rd32(E1000_CTRL_EXT
);
1018 reg
&= ~E1000_CTRL_EXT_SDP7_DATA
;
1019 wr32(E1000_CTRL_EXT
, reg
);
1022 /* Set switch control to serdes energy detect */
1023 reg
= rd32(E1000_CONNSW
);
1024 reg
|= E1000_CONNSW_ENRGSRC
;
1025 wr32(E1000_CONNSW
, reg
);
1028 * New SerDes mode allows for forcing speed or autonegotiating speed
1029 * at 1gb. Autoneg should be default set by most drivers. This is the
1030 * mode that will be compatible with older link partners and switches.
1031 * However, both are supported by the hardware and some drivers/tools.
1033 reg
= rd32(E1000_PCS_LCTL
);
1035 reg
&= ~(E1000_PCS_LCTL_AN_ENABLE
| E1000_PCS_LCTL_FLV_LINK_UP
|
1036 E1000_PCS_LCTL_FSD
| E1000_PCS_LCTL_FORCE_LINK
);
1038 if (hw
->mac
.autoneg
) {
1039 /* Set PCS register for autoneg */
1040 reg
|= E1000_PCS_LCTL_FSV_1000
| /* Force 1000 */
1041 E1000_PCS_LCTL_FDV_FULL
| /* SerDes Full duplex */
1042 E1000_PCS_LCTL_AN_ENABLE
| /* Enable Autoneg */
1043 E1000_PCS_LCTL_AN_RESTART
; /* Restart autoneg */
1044 hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg
);
1046 /* Set PCS register for forced speed */
1047 reg
|= E1000_PCS_LCTL_FLV_LINK_UP
| /* Force link up */
1048 E1000_PCS_LCTL_FSV_1000
| /* Force 1000 */
1049 E1000_PCS_LCTL_FDV_FULL
| /* SerDes Full duplex */
1050 E1000_PCS_LCTL_FSD
| /* Force Speed */
1051 E1000_PCS_LCTL_FORCE_LINK
; /* Force Link */
1052 hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg
);
1055 if (hw
->mac
.type
== e1000_82576
) {
1056 reg
|= E1000_PCS_LCTL_FORCE_FCTRL
;
1057 igb_force_mac_fc(hw
);
1060 wr32(E1000_PCS_LCTL
, reg
);
1066 * igb_configure_pcs_link_82575 - Configure PCS link
1067 * @hw: pointer to the HW structure
1069 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1070 * only used on copper connections where the serialized gigabit media
1071 * independent interface (sgmii) is being used. Configures the link
1072 * for auto-negotiation or forces speed/duplex.
1074 static void igb_configure_pcs_link_82575(struct e1000_hw
*hw
)
1076 struct e1000_mac_info
*mac
= &hw
->mac
;
1079 if (hw
->phy
.media_type
!= e1000_media_type_copper
||
1080 !(igb_sgmii_active_82575(hw
)))
1083 /* For SGMII, we need to issue a PCS autoneg restart */
1084 reg
= rd32(E1000_PCS_LCTL
);
1086 /* AN time out should be disabled for SGMII mode */
1087 reg
&= ~(E1000_PCS_LCTL_AN_TIMEOUT
);
1090 /* Make sure forced speed and force link are not set */
1091 reg
&= ~(E1000_PCS_LCTL_FSD
| E1000_PCS_LCTL_FORCE_LINK
);
1094 * The PHY should be setup prior to calling this function.
1095 * All we need to do is restart autoneg and enable autoneg.
1097 reg
|= E1000_PCS_LCTL_AN_RESTART
| E1000_PCS_LCTL_AN_ENABLE
;
1099 /* Set PCS register for forced speed */
1101 /* Turn off bits for full duplex, speed, and autoneg */
1102 reg
&= ~(E1000_PCS_LCTL_FSV_1000
|
1103 E1000_PCS_LCTL_FSV_100
|
1104 E1000_PCS_LCTL_FDV_FULL
|
1105 E1000_PCS_LCTL_AN_ENABLE
);
1107 /* Check for duplex first */
1108 if (mac
->forced_speed_duplex
& E1000_ALL_FULL_DUPLEX
)
1109 reg
|= E1000_PCS_LCTL_FDV_FULL
;
1112 if (mac
->forced_speed_duplex
& E1000_ALL_100_SPEED
)
1113 reg
|= E1000_PCS_LCTL_FSV_100
;
1115 /* Force speed and force link */
1116 reg
|= E1000_PCS_LCTL_FSD
|
1117 E1000_PCS_LCTL_FORCE_LINK
|
1118 E1000_PCS_LCTL_FLV_LINK_UP
;
1120 hw_dbg("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
1123 wr32(E1000_PCS_LCTL
, reg
);
1127 * igb_sgmii_active_82575 - Return sgmii state
1128 * @hw: pointer to the HW structure
1130 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1131 * which can be enabled for use in the embedded applications. Simply
1132 * return the current state of the sgmii interface.
1134 static bool igb_sgmii_active_82575(struct e1000_hw
*hw
)
1136 struct e1000_dev_spec_82575
*dev_spec
= &hw
->dev_spec
._82575
;
1137 return dev_spec
->sgmii_active
;
1141 * igb_reset_init_script_82575 - Inits HW defaults after reset
1142 * @hw: pointer to the HW structure
1144 * Inits recommended HW defaults after a reset when there is no EEPROM
1145 * detected. This is only for the 82575.
1147 static s32
igb_reset_init_script_82575(struct e1000_hw
*hw
)
1149 if (hw
->mac
.type
== e1000_82575
) {
1150 hw_dbg("Running reset init script for 82575\n");
1151 /* SerDes configuration via SERDESCTRL */
1152 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x00, 0x0C);
1153 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x01, 0x78);
1154 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x1B, 0x23);
1155 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x23, 0x15);
1157 /* CCM configuration via CCMCTL register */
1158 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x14, 0x00);
1159 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x10, 0x00);
1161 /* PCIe lanes configuration */
1162 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x00, 0xEC);
1163 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x61, 0xDF);
1164 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x34, 0x05);
1165 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x2F, 0x81);
1167 /* PCIe PLL Configuration */
1168 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x02, 0x47);
1169 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x14, 0x00);
1170 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x10, 0x00);
1177 * igb_read_mac_addr_82575 - Read device MAC address
1178 * @hw: pointer to the HW structure
1180 static s32
igb_read_mac_addr_82575(struct e1000_hw
*hw
)
1184 if (igb_check_alt_mac_addr(hw
))
1185 ret_val
= igb_read_mac_addr(hw
);
1191 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1192 * @hw: pointer to the HW structure
1194 * Clears the hardware counters by reading the counter registers.
1196 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*hw
)
1200 igb_clear_hw_cntrs_base(hw
);
1202 temp
= rd32(E1000_PRC64
);
1203 temp
= rd32(E1000_PRC127
);
1204 temp
= rd32(E1000_PRC255
);
1205 temp
= rd32(E1000_PRC511
);
1206 temp
= rd32(E1000_PRC1023
);
1207 temp
= rd32(E1000_PRC1522
);
1208 temp
= rd32(E1000_PTC64
);
1209 temp
= rd32(E1000_PTC127
);
1210 temp
= rd32(E1000_PTC255
);
1211 temp
= rd32(E1000_PTC511
);
1212 temp
= rd32(E1000_PTC1023
);
1213 temp
= rd32(E1000_PTC1522
);
1215 temp
= rd32(E1000_ALGNERRC
);
1216 temp
= rd32(E1000_RXERRC
);
1217 temp
= rd32(E1000_TNCRS
);
1218 temp
= rd32(E1000_CEXTERR
);
1219 temp
= rd32(E1000_TSCTC
);
1220 temp
= rd32(E1000_TSCTFC
);
1222 temp
= rd32(E1000_MGTPRC
);
1223 temp
= rd32(E1000_MGTPDC
);
1224 temp
= rd32(E1000_MGTPTC
);
1226 temp
= rd32(E1000_IAC
);
1227 temp
= rd32(E1000_ICRXOC
);
1229 temp
= rd32(E1000_ICRXPTC
);
1230 temp
= rd32(E1000_ICRXATC
);
1231 temp
= rd32(E1000_ICTXPTC
);
1232 temp
= rd32(E1000_ICTXATC
);
1233 temp
= rd32(E1000_ICTXQEC
);
1234 temp
= rd32(E1000_ICTXQMTC
);
1235 temp
= rd32(E1000_ICRXDMTC
);
1237 temp
= rd32(E1000_CBTMPC
);
1238 temp
= rd32(E1000_HTDPMC
);
1239 temp
= rd32(E1000_CBRMPC
);
1240 temp
= rd32(E1000_RPTHC
);
1241 temp
= rd32(E1000_HGPTC
);
1242 temp
= rd32(E1000_HTCBDPC
);
1243 temp
= rd32(E1000_HGORCL
);
1244 temp
= rd32(E1000_HGORCH
);
1245 temp
= rd32(E1000_HGOTCL
);
1246 temp
= rd32(E1000_HGOTCH
);
1247 temp
= rd32(E1000_LENERRS
);
1249 /* This register should not be read in copper configurations */
1250 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
1251 temp
= rd32(E1000_SCVPC
);
1255 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1256 * @hw: pointer to the HW structure
1258 * After rx enable if managability is enabled then there is likely some
1259 * bad data at the start of the fifo and possibly in the DMA fifo. This
1260 * function clears the fifos and flushes any packets that came in as rx was
1263 void igb_rx_fifo_flush_82575(struct e1000_hw
*hw
)
1265 u32 rctl
, rlpml
, rxdctl
[4], rfctl
, temp_rctl
, rx_enabled
;
1268 if (hw
->mac
.type
!= e1000_82575
||
1269 !(rd32(E1000_MANC
) & E1000_MANC_RCV_TCO_EN
))
1272 /* Disable all RX queues */
1273 for (i
= 0; i
< 4; i
++) {
1274 rxdctl
[i
] = rd32(E1000_RXDCTL(i
));
1275 wr32(E1000_RXDCTL(i
),
1276 rxdctl
[i
] & ~E1000_RXDCTL_QUEUE_ENABLE
);
1278 /* Poll all queues to verify they have shut down */
1279 for (ms_wait
= 0; ms_wait
< 10; ms_wait
++) {
1282 for (i
= 0; i
< 4; i
++)
1283 rx_enabled
|= rd32(E1000_RXDCTL(i
));
1284 if (!(rx_enabled
& E1000_RXDCTL_QUEUE_ENABLE
))
1289 hw_dbg("Queue disable timed out after 10ms\n");
1291 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1292 * incoming packets are rejected. Set enable and wait 2ms so that
1293 * any packet that was coming in as RCTL.EN was set is flushed
1295 rfctl
= rd32(E1000_RFCTL
);
1296 wr32(E1000_RFCTL
, rfctl
& ~E1000_RFCTL_LEF
);
1298 rlpml
= rd32(E1000_RLPML
);
1299 wr32(E1000_RLPML
, 0);
1301 rctl
= rd32(E1000_RCTL
);
1302 temp_rctl
= rctl
& ~(E1000_RCTL_EN
| E1000_RCTL_SBP
);
1303 temp_rctl
|= E1000_RCTL_LPE
;
1305 wr32(E1000_RCTL
, temp_rctl
);
1306 wr32(E1000_RCTL
, temp_rctl
| E1000_RCTL_EN
);
1310 /* Enable RX queues that were previously enabled and restore our
1313 for (i
= 0; i
< 4; i
++)
1314 wr32(E1000_RXDCTL(i
), rxdctl
[i
]);
1315 wr32(E1000_RCTL
, rctl
);
1318 wr32(E1000_RLPML
, rlpml
);
1319 wr32(E1000_RFCTL
, rfctl
);
1321 /* Flush receive errors generated by workaround */
1328 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1329 * @hw: pointer to the HW structure
1331 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1332 * however the hardware default for these parts is 500us to 1ms which is less
1333 * than the 10ms recommended by the pci-e spec. To address this we need to
1334 * increase the value to either 10ms to 200ms for capability version 1 config,
1335 * or 16ms to 55ms for version 2.
1337 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
)
1339 u32 gcr
= rd32(E1000_GCR
);
1343 /* only take action if timeout value is defaulted to 0 */
1344 if (gcr
& E1000_GCR_CMPL_TMOUT_MASK
)
1348 * if capababilities version is type 1 we can write the
1349 * timeout of 10ms to 200ms through the GCR register
1351 if (!(gcr
& E1000_GCR_CAP_VER2
)) {
1352 gcr
|= E1000_GCR_CMPL_TMOUT_10ms
;
1357 * for version 2 capabilities we need to write the config space
1358 * directly in order to set the completion timeout value for
1361 ret_val
= igb_read_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1366 pcie_devctl2
|= PCIE_DEVICE_CONTROL2_16ms
;
1368 ret_val
= igb_write_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1371 /* disable completion timeout resend */
1372 gcr
&= ~E1000_GCR_CMPL_TMOUT_RESEND
;
1374 wr32(E1000_GCR
, gcr
);
1379 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1380 * @hw: pointer to the hardware struct
1381 * @enable: state to enter, either enabled or disabled
1383 * enables/disables L2 switch loopback functionality.
1385 void igb_vmdq_set_loopback_pf(struct e1000_hw
*hw
, bool enable
)
1387 u32 dtxswc
= rd32(E1000_DTXSWC
);
1390 dtxswc
|= E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1392 dtxswc
&= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1394 wr32(E1000_DTXSWC
, dtxswc
);
1398 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1399 * @hw: pointer to the hardware struct
1400 * @enable: state to enter, either enabled or disabled
1402 * enables/disables replication of packets across multiple pools.
1404 void igb_vmdq_set_replication_pf(struct e1000_hw
*hw
, bool enable
)
1406 u32 vt_ctl
= rd32(E1000_VT_CTL
);
1409 vt_ctl
|= E1000_VT_CTL_VM_REPL_EN
;
1411 vt_ctl
&= ~E1000_VT_CTL_VM_REPL_EN
;
1413 wr32(E1000_VT_CTL
, vt_ctl
);
1416 static struct e1000_mac_operations e1000_mac_ops_82575
= {
1417 .reset_hw
= igb_reset_hw_82575
,
1418 .init_hw
= igb_init_hw_82575
,
1419 .check_for_link
= igb_check_for_link_82575
,
1420 .rar_set
= igb_rar_set
,
1421 .read_mac_addr
= igb_read_mac_addr_82575
,
1422 .get_speed_and_duplex
= igb_get_speed_and_duplex_copper
,
1425 static struct e1000_phy_operations e1000_phy_ops_82575
= {
1426 .acquire
= igb_acquire_phy_82575
,
1427 .get_cfg_done
= igb_get_cfg_done_82575
,
1428 .release
= igb_release_phy_82575
,
1431 static struct e1000_nvm_operations e1000_nvm_ops_82575
= {
1432 .acquire
= igb_acquire_nvm_82575
,
1433 .read
= igb_read_nvm_eerd
,
1434 .release
= igb_release_nvm_82575
,
1435 .write
= igb_write_nvm_spi
,
1438 const struct e1000_info e1000_82575_info
= {
1439 .get_invariants
= igb_get_invariants_82575
,
1440 .mac_ops
= &e1000_mac_ops_82575
,
1441 .phy_ops
= &e1000_phy_ops_82575
,
1442 .nvm_ops
= &e1000_nvm_ops_82575
,