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[POWERPC] Only offer CONFIG_BRIQ_PANEL if CONFIG_PPC_CHRP is enabled
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / fs_enet / mac-fec.c
1 /*
2 * Freescale Ethernet controllers
3 *
4 * Copyright (c) 2005 Intracom S.A.
5 * by Pantelis Antoniou <panto@intracom.gr>
6 *
7 * 2005 (c) MontaVista Software, Inc.
8 * Vitaly Bordug <vbordug@ru.mvista.com>
9 *
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/sched.h>
19 #include <linux/string.h>
20 #include <linux/ptrace.h>
21 #include <linux/errno.h>
22 #include <linux/ioport.h>
23 #include <linux/slab.h>
24 #include <linux/interrupt.h>
25 #include <linux/pci.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/skbuff.h>
31 #include <linux/spinlock.h>
32 #include <linux/mii.h>
33 #include <linux/ethtool.h>
34 #include <linux/bitops.h>
35 #include <linux/fs.h>
36 #include <linux/platform_device.h>
37
38 #include <asm/irq.h>
39 #include <asm/uaccess.h>
40
41 #ifdef CONFIG_8xx
42 #include <asm/8xx_immap.h>
43 #include <asm/pgtable.h>
44 #include <asm/mpc8xx.h>
45 #include <asm/commproc.h>
46 #endif
47
48 #include "fs_enet.h"
49
50 /*************************************************/
51
52 #if defined(CONFIG_CPM1)
53 /* for a CPM1 __raw_xxx's are sufficient */
54 #define __fs_out32(addr, x) __raw_writel(x, addr)
55 #define __fs_out16(addr, x) __raw_writew(x, addr)
56 #define __fs_in32(addr) __raw_readl(addr)
57 #define __fs_in16(addr) __raw_readw(addr)
58 #else
59 /* for others play it safe */
60 #define __fs_out32(addr, x) out_be32(addr, x)
61 #define __fs_out16(addr, x) out_be16(addr, x)
62 #define __fs_in32(addr) in_be32(addr)
63 #define __fs_in16(addr) in_be16(addr)
64 #endif
65
66 /* write */
67 #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v))
68
69 /* read */
70 #define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg)
71
72 /* set bits */
73 #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v))
74
75 /* clear bits */
76 #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
77
78
79 /* CRC polynomium used by the FEC for the multicast group filtering */
80 #define FEC_CRC_POLY 0x04C11DB7
81
82 #define FEC_MAX_MULTICAST_ADDRS 64
83
84 /* Interrupt events/masks.
85 */
86 #define FEC_ENET_HBERR 0x80000000U /* Heartbeat error */
87 #define FEC_ENET_BABR 0x40000000U /* Babbling receiver */
88 #define FEC_ENET_BABT 0x20000000U /* Babbling transmitter */
89 #define FEC_ENET_GRA 0x10000000U /* Graceful stop complete */
90 #define FEC_ENET_TXF 0x08000000U /* Full frame transmitted */
91 #define FEC_ENET_TXB 0x04000000U /* A buffer was transmitted */
92 #define FEC_ENET_RXF 0x02000000U /* Full frame received */
93 #define FEC_ENET_RXB 0x01000000U /* A buffer was received */
94 #define FEC_ENET_MII 0x00800000U /* MII interrupt */
95 #define FEC_ENET_EBERR 0x00400000U /* SDMA bus error */
96
97 #define FEC_ECNTRL_PINMUX 0x00000004
98 #define FEC_ECNTRL_ETHER_EN 0x00000002
99 #define FEC_ECNTRL_RESET 0x00000001
100
101 #define FEC_RCNTRL_BC_REJ 0x00000010
102 #define FEC_RCNTRL_PROM 0x00000008
103 #define FEC_RCNTRL_MII_MODE 0x00000004
104 #define FEC_RCNTRL_DRT 0x00000002
105 #define FEC_RCNTRL_LOOP 0x00000001
106
107 #define FEC_TCNTRL_FDEN 0x00000004
108 #define FEC_TCNTRL_HBC 0x00000002
109 #define FEC_TCNTRL_GTS 0x00000001
110
111
112 /* Make MII read/write commands for the FEC.
113 */
114 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
115 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
116 #define mk_mii_end 0
117
118 #define FEC_MII_LOOPS 10000
119
120 /*
121 * Delay to wait for FEC reset command to complete (in us)
122 */
123 #define FEC_RESET_DELAY 50
124
125 static int whack_reset(fec_t * fecp)
126 {
127 int i;
128
129 FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
130 for (i = 0; i < FEC_RESET_DELAY; i++) {
131 if ((FR(fecp, ecntrl) & FEC_ECNTRL_RESET) == 0)
132 return 0; /* OK */
133 udelay(1);
134 }
135
136 return -1;
137 }
138
139 static int do_pd_setup(struct fs_enet_private *fep)
140 {
141 struct platform_device *pdev = to_platform_device(fep->dev);
142 struct resource *r;
143
144 /* Fill out IRQ field */
145 fep->interrupt = platform_get_irq_byname(pdev,"interrupt");
146 if (fep->interrupt < 0)
147 return -EINVAL;
148
149 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
150 fep->fec.fecp =(void*)r->start;
151
152 if(fep->fec.fecp == NULL)
153 return -EINVAL;
154
155 return 0;
156
157 }
158
159 #define FEC_NAPI_RX_EVENT_MSK (FEC_ENET_RXF | FEC_ENET_RXB)
160 #define FEC_RX_EVENT (FEC_ENET_RXF)
161 #define FEC_TX_EVENT (FEC_ENET_TXF)
162 #define FEC_ERR_EVENT_MSK (FEC_ENET_HBERR | FEC_ENET_BABR | \
163 FEC_ENET_BABT | FEC_ENET_EBERR)
164
165 static int setup_data(struct net_device *dev)
166 {
167 struct fs_enet_private *fep = netdev_priv(dev);
168
169 if (do_pd_setup(fep) != 0)
170 return -EINVAL;
171
172 fep->fec.hthi = 0;
173 fep->fec.htlo = 0;
174
175 fep->ev_napi_rx = FEC_NAPI_RX_EVENT_MSK;
176 fep->ev_rx = FEC_RX_EVENT;
177 fep->ev_tx = FEC_TX_EVENT;
178 fep->ev_err = FEC_ERR_EVENT_MSK;
179
180 return 0;
181 }
182
183 static int allocate_bd(struct net_device *dev)
184 {
185 struct fs_enet_private *fep = netdev_priv(dev);
186 const struct fs_platform_info *fpi = fep->fpi;
187
188 fep->ring_base = dma_alloc_coherent(fep->dev,
189 (fpi->tx_ring + fpi->rx_ring) *
190 sizeof(cbd_t), &fep->ring_mem_addr,
191 GFP_KERNEL);
192 if (fep->ring_base == NULL)
193 return -ENOMEM;
194
195 return 0;
196 }
197
198 static void free_bd(struct net_device *dev)
199 {
200 struct fs_enet_private *fep = netdev_priv(dev);
201 const struct fs_platform_info *fpi = fep->fpi;
202
203 if(fep->ring_base)
204 dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring)
205 * sizeof(cbd_t),
206 fep->ring_base,
207 fep->ring_mem_addr);
208 }
209
210 static void cleanup_data(struct net_device *dev)
211 {
212 /* nothing */
213 }
214
215 static void set_promiscuous_mode(struct net_device *dev)
216 {
217 struct fs_enet_private *fep = netdev_priv(dev);
218 fec_t *fecp = fep->fec.fecp;
219
220 FS(fecp, r_cntrl, FEC_RCNTRL_PROM);
221 }
222
223 static void set_multicast_start(struct net_device *dev)
224 {
225 struct fs_enet_private *fep = netdev_priv(dev);
226
227 fep->fec.hthi = 0;
228 fep->fec.htlo = 0;
229 }
230
231 static void set_multicast_one(struct net_device *dev, const u8 *mac)
232 {
233 struct fs_enet_private *fep = netdev_priv(dev);
234 int temp, hash_index, i, j;
235 u32 crc, csrVal;
236 u8 byte, msb;
237
238 crc = 0xffffffff;
239 for (i = 0; i < 6; i++) {
240 byte = mac[i];
241 for (j = 0; j < 8; j++) {
242 msb = crc >> 31;
243 crc <<= 1;
244 if (msb ^ (byte & 0x1))
245 crc ^= FEC_CRC_POLY;
246 byte >>= 1;
247 }
248 }
249
250 temp = (crc & 0x3f) >> 1;
251 hash_index = ((temp & 0x01) << 4) |
252 ((temp & 0x02) << 2) |
253 ((temp & 0x04)) |
254 ((temp & 0x08) >> 2) |
255 ((temp & 0x10) >> 4);
256 csrVal = 1 << hash_index;
257 if (crc & 1)
258 fep->fec.hthi |= csrVal;
259 else
260 fep->fec.htlo |= csrVal;
261 }
262
263 static void set_multicast_finish(struct net_device *dev)
264 {
265 struct fs_enet_private *fep = netdev_priv(dev);
266 fec_t *fecp = fep->fec.fecp;
267
268 /* if all multi or too many multicasts; just enable all */
269 if ((dev->flags & IFF_ALLMULTI) != 0 ||
270 dev->mc_count > FEC_MAX_MULTICAST_ADDRS) {
271 fep->fec.hthi = 0xffffffffU;
272 fep->fec.htlo = 0xffffffffU;
273 }
274
275 FC(fecp, r_cntrl, FEC_RCNTRL_PROM);
276 FW(fecp, hash_table_high, fep->fec.hthi);
277 FW(fecp, hash_table_low, fep->fec.htlo);
278 }
279
280 static void set_multicast_list(struct net_device *dev)
281 {
282 struct dev_mc_list *pmc;
283
284 if ((dev->flags & IFF_PROMISC) == 0) {
285 set_multicast_start(dev);
286 for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
287 set_multicast_one(dev, pmc->dmi_addr);
288 set_multicast_finish(dev);
289 } else
290 set_promiscuous_mode(dev);
291 }
292
293 static void restart(struct net_device *dev)
294 {
295 #ifdef CONFIG_DUET
296 immap_t *immap = fs_enet_immap;
297 u32 cptr;
298 #endif
299 struct fs_enet_private *fep = netdev_priv(dev);
300 fec_t *fecp = fep->fec.fecp;
301 const struct fs_platform_info *fpi = fep->fpi;
302 dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
303 int r;
304 u32 addrhi, addrlo;
305
306 r = whack_reset(fep->fec.fecp);
307 if (r != 0)
308 printk(KERN_ERR DRV_MODULE_NAME
309 ": %s FEC Reset FAILED!\n", dev->name);
310
311 /*
312 * Set station address.
313 */
314 addrhi = ((u32) dev->dev_addr[0] << 24) |
315 ((u32) dev->dev_addr[1] << 16) |
316 ((u32) dev->dev_addr[2] << 8) |
317 (u32) dev->dev_addr[3];
318 addrlo = ((u32) dev->dev_addr[4] << 24) |
319 ((u32) dev->dev_addr[5] << 16);
320 FW(fecp, addr_low, addrhi);
321 FW(fecp, addr_high, addrlo);
322
323 /*
324 * Reset all multicast.
325 */
326 FW(fecp, hash_table_high, fep->fec.hthi);
327 FW(fecp, hash_table_low, fep->fec.htlo);
328
329 /*
330 * Set maximum receive buffer size.
331 */
332 FW(fecp, r_buff_size, PKT_MAXBLR_SIZE);
333 FW(fecp, r_hash, PKT_MAXBUF_SIZE);
334
335 /* get physical address */
336 rx_bd_base_phys = fep->ring_mem_addr;
337 tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
338
339 /*
340 * Set receive and transmit descriptor base.
341 */
342 FW(fecp, r_des_start, rx_bd_base_phys);
343 FW(fecp, x_des_start, tx_bd_base_phys);
344
345 fs_init_bds(dev);
346
347 /*
348 * Enable big endian and don't care about SDMA FC.
349 */
350 FW(fecp, fun_code, 0x78000000);
351
352 /*
353 * Set MII speed.
354 */
355 FW(fecp, mii_speed, fep->mii_bus->fec.mii_speed);
356
357 /*
358 * Clear any outstanding interrupt.
359 */
360 FW(fecp, ievent, 0xffc0);
361 FW(fecp, ivec, (fep->interrupt / 2) << 29);
362
363
364 /*
365 * adjust to speed (only for DUET & RMII)
366 */
367 #ifdef CONFIG_DUET
368 if (fpi->use_rmii) {
369 cptr = in_be32(&immap->im_cpm.cp_cptr);
370 switch (fs_get_fec_index(fpi->fs_no)) {
371 case 0:
372 cptr |= 0x100;
373 if (fep->speed == 10)
374 cptr |= 0x0000010;
375 else if (fep->speed == 100)
376 cptr &= ~0x0000010;
377 break;
378 case 1:
379 cptr |= 0x80;
380 if (fep->speed == 10)
381 cptr |= 0x0000008;
382 else if (fep->speed == 100)
383 cptr &= ~0x0000008;
384 break;
385 default:
386 BUG(); /* should never happen */
387 break;
388 }
389 out_be32(&immap->im_cpm.cp_cptr, cptr);
390 }
391 #endif
392
393 FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
394 /*
395 * adjust to duplex mode
396 */
397 if (fep->duplex) {
398 FC(fecp, r_cntrl, FEC_RCNTRL_DRT);
399 FS(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
400 } else {
401 FS(fecp, r_cntrl, FEC_RCNTRL_DRT);
402 FC(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
403 }
404
405 /*
406 * Enable interrupts we wish to service.
407 */
408 FW(fecp, imask, FEC_ENET_TXF | FEC_ENET_TXB |
409 FEC_ENET_RXF | FEC_ENET_RXB);
410
411 /*
412 * And last, enable the transmit and receive processing.
413 */
414 FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
415 FW(fecp, r_des_active, 0x01000000);
416 }
417
418 static void stop(struct net_device *dev)
419 {
420 struct fs_enet_private *fep = netdev_priv(dev);
421 fec_t *fecp = fep->fec.fecp;
422 struct fs_enet_mii_bus *bus = fep->mii_bus;
423 const struct fs_mii_bus_info *bi = bus->bus_info;
424 int i;
425
426 if ((FR(fecp, ecntrl) & FEC_ECNTRL_ETHER_EN) == 0)
427 return; /* already down */
428
429 FW(fecp, x_cntrl, 0x01); /* Graceful transmit stop */
430 for (i = 0; ((FR(fecp, ievent) & 0x10000000) == 0) &&
431 i < FEC_RESET_DELAY; i++)
432 udelay(1);
433
434 if (i == FEC_RESET_DELAY)
435 printk(KERN_WARNING DRV_MODULE_NAME
436 ": %s FEC timeout on graceful transmit stop\n",
437 dev->name);
438 /*
439 * Disable FEC. Let only MII interrupts.
440 */
441 FW(fecp, imask, 0);
442 FC(fecp, ecntrl, FEC_ECNTRL_ETHER_EN);
443
444 fs_cleanup_bds(dev);
445
446 /* shut down FEC1? that's where the mii bus is */
447 if (fep->fec.idx == 0 && bus->refs > 1 && bi->method == fsmii_fec) {
448 FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
449 FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
450 FW(fecp, ievent, FEC_ENET_MII);
451 FW(fecp, mii_speed, bus->fec.mii_speed);
452 }
453 }
454
455 static void pre_request_irq(struct net_device *dev, int irq)
456 {
457 immap_t *immap = fs_enet_immap;
458 u32 siel;
459
460 /* SIU interrupt */
461 if (irq >= SIU_IRQ0 && irq < SIU_LEVEL7) {
462
463 siel = in_be32(&immap->im_siu_conf.sc_siel);
464 if ((irq & 1) == 0)
465 siel |= (0x80000000 >> irq);
466 else
467 siel &= ~(0x80000000 >> (irq & ~1));
468 out_be32(&immap->im_siu_conf.sc_siel, siel);
469 }
470 }
471
472 static void post_free_irq(struct net_device *dev, int irq)
473 {
474 /* nothing */
475 }
476
477 static void napi_clear_rx_event(struct net_device *dev)
478 {
479 struct fs_enet_private *fep = netdev_priv(dev);
480 fec_t *fecp = fep->fec.fecp;
481
482 FW(fecp, ievent, FEC_NAPI_RX_EVENT_MSK);
483 }
484
485 static void napi_enable_rx(struct net_device *dev)
486 {
487 struct fs_enet_private *fep = netdev_priv(dev);
488 fec_t *fecp = fep->fec.fecp;
489
490 FS(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
491 }
492
493 static void napi_disable_rx(struct net_device *dev)
494 {
495 struct fs_enet_private *fep = netdev_priv(dev);
496 fec_t *fecp = fep->fec.fecp;
497
498 FC(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
499 }
500
501 static void rx_bd_done(struct net_device *dev)
502 {
503 struct fs_enet_private *fep = netdev_priv(dev);
504 fec_t *fecp = fep->fec.fecp;
505
506 FW(fecp, r_des_active, 0x01000000);
507 }
508
509 static void tx_kickstart(struct net_device *dev)
510 {
511 struct fs_enet_private *fep = netdev_priv(dev);
512 fec_t *fecp = fep->fec.fecp;
513
514 FW(fecp, x_des_active, 0x01000000);
515 }
516
517 static u32 get_int_events(struct net_device *dev)
518 {
519 struct fs_enet_private *fep = netdev_priv(dev);
520 fec_t *fecp = fep->fec.fecp;
521
522 return FR(fecp, ievent) & FR(fecp, imask);
523 }
524
525 static void clear_int_events(struct net_device *dev, u32 int_events)
526 {
527 struct fs_enet_private *fep = netdev_priv(dev);
528 fec_t *fecp = fep->fec.fecp;
529
530 FW(fecp, ievent, int_events);
531 }
532
533 static void ev_error(struct net_device *dev, u32 int_events)
534 {
535 printk(KERN_WARNING DRV_MODULE_NAME
536 ": %s FEC ERROR(s) 0x%x\n", dev->name, int_events);
537 }
538
539 int get_regs(struct net_device *dev, void *p, int *sizep)
540 {
541 struct fs_enet_private *fep = netdev_priv(dev);
542
543 if (*sizep < sizeof(fec_t))
544 return -EINVAL;
545
546 memcpy_fromio(p, fep->fec.fecp, sizeof(fec_t));
547
548 return 0;
549 }
550
551 int get_regs_len(struct net_device *dev)
552 {
553 return sizeof(fec_t);
554 }
555
556 void tx_restart(struct net_device *dev)
557 {
558 /* nothing */
559 }
560
561 /*************************************************************************/
562
563 const struct fs_ops fs_fec_ops = {
564 .setup_data = setup_data,
565 .cleanup_data = cleanup_data,
566 .set_multicast_list = set_multicast_list,
567 .restart = restart,
568 .stop = stop,
569 .pre_request_irq = pre_request_irq,
570 .post_free_irq = post_free_irq,
571 .napi_clear_rx_event = napi_clear_rx_event,
572 .napi_enable_rx = napi_enable_rx,
573 .napi_disable_rx = napi_disable_rx,
574 .rx_bd_done = rx_bd_done,
575 .tx_kickstart = tx_kickstart,
576 .get_int_events = get_int_events,
577 .clear_int_events = clear_int_events,
578 .ev_error = ev_error,
579 .get_regs = get_regs,
580 .get_regs_len = get_regs_len,
581 .tx_restart = tx_restart,
582 .allocate_bd = allocate_bd,
583 .free_bd = free_bd,
584 };
585
586 /***********************************************************************/
587
588 static int mii_read(struct fs_enet_mii_bus *bus, int phy_id, int location)
589 {
590 fec_t *fecp = bus->fec.fecp;
591 int i, ret = -1;
592
593 if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
594 BUG();
595
596 /* Add PHY address to register command. */
597 FW(fecp, mii_data, (phy_id << 23) | mk_mii_read(location));
598
599 for (i = 0; i < FEC_MII_LOOPS; i++)
600 if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
601 break;
602
603 if (i < FEC_MII_LOOPS) {
604 FW(fecp, ievent, FEC_ENET_MII);
605 ret = FR(fecp, mii_data) & 0xffff;
606 }
607
608 return ret;
609 }
610
611 static void mii_write(struct fs_enet_mii_bus *bus, int phy_id, int location, int value)
612 {
613 fec_t *fecp = bus->fec.fecp;
614 int i;
615
616 /* this must never happen */
617 if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
618 BUG();
619
620 /* Add PHY address to register command. */
621 FW(fecp, mii_data, (phy_id << 23) | mk_mii_write(location, value));
622
623 for (i = 0; i < FEC_MII_LOOPS; i++)
624 if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
625 break;
626
627 if (i < FEC_MII_LOOPS)
628 FW(fecp, ievent, FEC_ENET_MII);
629 }
630
631 int fs_mii_fec_init(struct fs_enet_mii_bus *bus)
632 {
633 bd_t *bd = (bd_t *)__res;
634 const struct fs_mii_bus_info *bi = bus->bus_info;
635 fec_t *fecp;
636
637 if (bi->id != 0)
638 return -1;
639
640 bus->fec.fecp = &((immap_t *)fs_enet_immap)->im_cpm.cp_fec;
641 bus->fec.mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2)
642 & 0x3F) << 1;
643
644 fecp = bus->fec.fecp;
645
646 FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
647 FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
648 FW(fecp, ievent, FEC_ENET_MII);
649 FW(fecp, mii_speed, bus->fec.mii_speed);
650
651 bus->mii_read = mii_read;
652 bus->mii_write = mii_write;
653
654 return 0;
655 }
kernel source for telekom puls (alcatel/mediatek)