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[PATCH] forcedeth config: csum
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / forcedeth.c
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
8 *
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
11 * countries.
12 *
13 * Copyright (C) 2003,4,5 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 *
33 * Changelog:
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
42 * irq mask updated
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
57 * open.
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
61 * the tx length.
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
69 * on close.
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
83 * capabilities.
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added.
88 * 0.36: 28 Jun 2005: Add jumbo frame support.
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
90 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
91 * per-packet flags.
92 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
93 * 0.40: 19 Jul 2005: Add support for mac address change.
94 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
95 * of nv_remove
96 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
97 * in the second (and later) nv_open call
98 * 0.43: 10 Aug 2005: Add support for tx checksum.
99 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
100 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
101 * 0.46: 20 Oct 2005: Add irq optimization modes.
102 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
103 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
104 * 0.49: 10 Dec 2005: Fix tso for large buffers.
105 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
106 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
107 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
108 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
109 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
110 * 0.55: 22 Mar 2006: Add flow control (pause frame).
111 *
112 * Known bugs:
113 * We suspect that on some hardware no TX done interrupts are generated.
114 * This means recovery from netif_stop_queue only happens if the hw timer
115 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
116 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
117 * If your hardware reliably generates tx done interrupts, then you can remove
118 * DEV_NEED_TIMERIRQ from the driver_data flags.
119 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
120 * superfluous timer interrupts from the nic.
121 */
122 #define FORCEDETH_VERSION "0.55"
123 #define DRV_NAME "forcedeth"
124
125 #include <linux/module.h>
126 #include <linux/types.h>
127 #include <linux/pci.h>
128 #include <linux/interrupt.h>
129 #include <linux/netdevice.h>
130 #include <linux/etherdevice.h>
131 #include <linux/delay.h>
132 #include <linux/spinlock.h>
133 #include <linux/ethtool.h>
134 #include <linux/timer.h>
135 #include <linux/skbuff.h>
136 #include <linux/mii.h>
137 #include <linux/random.h>
138 #include <linux/init.h>
139 #include <linux/if_vlan.h>
140 #include <linux/dma-mapping.h>
141
142 #include <asm/irq.h>
143 #include <asm/io.h>
144 #include <asm/uaccess.h>
145 #include <asm/system.h>
146
147 #if 0
148 #define dprintk printk
149 #else
150 #define dprintk(x...) do { } while (0)
151 #endif
152
153
154 /*
155 * Hardware access:
156 */
157
158 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
159 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
160 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
161 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
162 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
163 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
164 #define DEV_HAS_MSI 0x0040 /* device supports MSI */
165 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
166 #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
167 #define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
168
169 enum {
170 NvRegIrqStatus = 0x000,
171 #define NVREG_IRQSTAT_MIIEVENT 0x040
172 #define NVREG_IRQSTAT_MASK 0x1ff
173 NvRegIrqMask = 0x004,
174 #define NVREG_IRQ_RX_ERROR 0x0001
175 #define NVREG_IRQ_RX 0x0002
176 #define NVREG_IRQ_RX_NOBUF 0x0004
177 #define NVREG_IRQ_TX_ERR 0x0008
178 #define NVREG_IRQ_TX_OK 0x0010
179 #define NVREG_IRQ_TIMER 0x0020
180 #define NVREG_IRQ_LINK 0x0040
181 #define NVREG_IRQ_RX_FORCED 0x0080
182 #define NVREG_IRQ_TX_FORCED 0x0100
183 #define NVREG_IRQMASK_THROUGHPUT 0x00df
184 #define NVREG_IRQMASK_CPU 0x0040
185 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
186 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
187 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
188
189 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
190 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
191 NVREG_IRQ_TX_FORCED))
192
193 NvRegUnknownSetupReg6 = 0x008,
194 #define NVREG_UNKSETUP6_VAL 3
195
196 /*
197 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
198 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
199 */
200 NvRegPollingInterval = 0x00c,
201 #define NVREG_POLL_DEFAULT_THROUGHPUT 970
202 #define NVREG_POLL_DEFAULT_CPU 13
203 NvRegMSIMap0 = 0x020,
204 NvRegMSIMap1 = 0x024,
205 NvRegMSIIrqMask = 0x030,
206 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
207 NvRegMisc1 = 0x080,
208 #define NVREG_MISC1_PAUSE_TX 0x01
209 #define NVREG_MISC1_HD 0x02
210 #define NVREG_MISC1_FORCE 0x3b0f3c
211
212 NvRegMacReset = 0x3c,
213 #define NVREG_MAC_RESET_ASSERT 0x0F3
214 NvRegTransmitterControl = 0x084,
215 #define NVREG_XMITCTL_START 0x01
216 NvRegTransmitterStatus = 0x088,
217 #define NVREG_XMITSTAT_BUSY 0x01
218
219 NvRegPacketFilterFlags = 0x8c,
220 #define NVREG_PFF_PAUSE_RX 0x08
221 #define NVREG_PFF_ALWAYS 0x7F0000
222 #define NVREG_PFF_PROMISC 0x80
223 #define NVREG_PFF_MYADDR 0x20
224
225 NvRegOffloadConfig = 0x90,
226 #define NVREG_OFFLOAD_HOMEPHY 0x601
227 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
228 NvRegReceiverControl = 0x094,
229 #define NVREG_RCVCTL_START 0x01
230 NvRegReceiverStatus = 0x98,
231 #define NVREG_RCVSTAT_BUSY 0x01
232
233 NvRegRandomSeed = 0x9c,
234 #define NVREG_RNDSEED_MASK 0x00ff
235 #define NVREG_RNDSEED_FORCE 0x7f00
236 #define NVREG_RNDSEED_FORCE2 0x2d00
237 #define NVREG_RNDSEED_FORCE3 0x7400
238
239 NvRegUnknownSetupReg1 = 0xA0,
240 #define NVREG_UNKSETUP1_VAL 0x16070f
241 NvRegUnknownSetupReg2 = 0xA4,
242 #define NVREG_UNKSETUP2_VAL 0x16
243 NvRegMacAddrA = 0xA8,
244 NvRegMacAddrB = 0xAC,
245 NvRegMulticastAddrA = 0xB0,
246 #define NVREG_MCASTADDRA_FORCE 0x01
247 NvRegMulticastAddrB = 0xB4,
248 NvRegMulticastMaskA = 0xB8,
249 NvRegMulticastMaskB = 0xBC,
250
251 NvRegPhyInterface = 0xC0,
252 #define PHY_RGMII 0x10000000
253
254 NvRegTxRingPhysAddr = 0x100,
255 NvRegRxRingPhysAddr = 0x104,
256 NvRegRingSizes = 0x108,
257 #define NVREG_RINGSZ_TXSHIFT 0
258 #define NVREG_RINGSZ_RXSHIFT 16
259 NvRegUnknownTransmitterReg = 0x10c,
260 NvRegLinkSpeed = 0x110,
261 #define NVREG_LINKSPEED_FORCE 0x10000
262 #define NVREG_LINKSPEED_10 1000
263 #define NVREG_LINKSPEED_100 100
264 #define NVREG_LINKSPEED_1000 50
265 #define NVREG_LINKSPEED_MASK (0xFFF)
266 NvRegUnknownSetupReg5 = 0x130,
267 #define NVREG_UNKSETUP5_BIT31 (1<<31)
268 NvRegUnknownSetupReg3 = 0x13c,
269 #define NVREG_UNKSETUP3_VAL1 0x200010
270 NvRegTxRxControl = 0x144,
271 #define NVREG_TXRXCTL_KICK 0x0001
272 #define NVREG_TXRXCTL_BIT1 0x0002
273 #define NVREG_TXRXCTL_BIT2 0x0004
274 #define NVREG_TXRXCTL_IDLE 0x0008
275 #define NVREG_TXRXCTL_RESET 0x0010
276 #define NVREG_TXRXCTL_RXCHECK 0x0400
277 #define NVREG_TXRXCTL_DESC_1 0
278 #define NVREG_TXRXCTL_DESC_2 0x02100
279 #define NVREG_TXRXCTL_DESC_3 0x02200
280 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
281 #define NVREG_TXRXCTL_VLANINS 0x00080
282 NvRegTxRingPhysAddrHigh = 0x148,
283 NvRegRxRingPhysAddrHigh = 0x14C,
284 NvRegTxPauseFrame = 0x170,
285 #define NVREG_TX_PAUSEFRAME_DISABLE 0x1ff0080
286 #define NVREG_TX_PAUSEFRAME_ENABLE 0x0c00030
287 NvRegMIIStatus = 0x180,
288 #define NVREG_MIISTAT_ERROR 0x0001
289 #define NVREG_MIISTAT_LINKCHANGE 0x0008
290 #define NVREG_MIISTAT_MASK 0x000f
291 #define NVREG_MIISTAT_MASK2 0x000f
292 NvRegUnknownSetupReg4 = 0x184,
293 #define NVREG_UNKSETUP4_VAL 8
294
295 NvRegAdapterControl = 0x188,
296 #define NVREG_ADAPTCTL_START 0x02
297 #define NVREG_ADAPTCTL_LINKUP 0x04
298 #define NVREG_ADAPTCTL_PHYVALID 0x40000
299 #define NVREG_ADAPTCTL_RUNNING 0x100000
300 #define NVREG_ADAPTCTL_PHYSHIFT 24
301 NvRegMIISpeed = 0x18c,
302 #define NVREG_MIISPEED_BIT8 (1<<8)
303 #define NVREG_MIIDELAY 5
304 NvRegMIIControl = 0x190,
305 #define NVREG_MIICTL_INUSE 0x08000
306 #define NVREG_MIICTL_WRITE 0x00400
307 #define NVREG_MIICTL_ADDRSHIFT 5
308 NvRegMIIData = 0x194,
309 NvRegWakeUpFlags = 0x200,
310 #define NVREG_WAKEUPFLAGS_VAL 0x7770
311 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
312 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
313 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
314 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
315 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
316 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
317 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
318 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
319 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
320 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
321
322 NvRegPatternCRC = 0x204,
323 NvRegPatternMask = 0x208,
324 NvRegPowerCap = 0x268,
325 #define NVREG_POWERCAP_D3SUPP (1<<30)
326 #define NVREG_POWERCAP_D2SUPP (1<<26)
327 #define NVREG_POWERCAP_D1SUPP (1<<25)
328 NvRegPowerState = 0x26c,
329 #define NVREG_POWERSTATE_POWEREDUP 0x8000
330 #define NVREG_POWERSTATE_VALID 0x0100
331 #define NVREG_POWERSTATE_MASK 0x0003
332 #define NVREG_POWERSTATE_D0 0x0000
333 #define NVREG_POWERSTATE_D1 0x0001
334 #define NVREG_POWERSTATE_D2 0x0002
335 #define NVREG_POWERSTATE_D3 0x0003
336 NvRegVlanControl = 0x300,
337 #define NVREG_VLANCONTROL_ENABLE 0x2000
338 NvRegMSIXMap0 = 0x3e0,
339 NvRegMSIXMap1 = 0x3e4,
340 NvRegMSIXIrqStatus = 0x3f0,
341
342 NvRegPowerState2 = 0x600,
343 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
344 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
345 };
346
347 /* Big endian: should work, but is untested */
348 struct ring_desc {
349 u32 PacketBuffer;
350 u32 FlagLen;
351 };
352
353 struct ring_desc_ex {
354 u32 PacketBufferHigh;
355 u32 PacketBufferLow;
356 u32 TxVlan;
357 u32 FlagLen;
358 };
359
360 typedef union _ring_type {
361 struct ring_desc* orig;
362 struct ring_desc_ex* ex;
363 } ring_type;
364
365 #define FLAG_MASK_V1 0xffff0000
366 #define FLAG_MASK_V2 0xffffc000
367 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
368 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
369
370 #define NV_TX_LASTPACKET (1<<16)
371 #define NV_TX_RETRYERROR (1<<19)
372 #define NV_TX_FORCED_INTERRUPT (1<<24)
373 #define NV_TX_DEFERRED (1<<26)
374 #define NV_TX_CARRIERLOST (1<<27)
375 #define NV_TX_LATECOLLISION (1<<28)
376 #define NV_TX_UNDERFLOW (1<<29)
377 #define NV_TX_ERROR (1<<30)
378 #define NV_TX_VALID (1<<31)
379
380 #define NV_TX2_LASTPACKET (1<<29)
381 #define NV_TX2_RETRYERROR (1<<18)
382 #define NV_TX2_FORCED_INTERRUPT (1<<30)
383 #define NV_TX2_DEFERRED (1<<25)
384 #define NV_TX2_CARRIERLOST (1<<26)
385 #define NV_TX2_LATECOLLISION (1<<27)
386 #define NV_TX2_UNDERFLOW (1<<28)
387 /* error and valid are the same for both */
388 #define NV_TX2_ERROR (1<<30)
389 #define NV_TX2_VALID (1<<31)
390 #define NV_TX2_TSO (1<<28)
391 #define NV_TX2_TSO_SHIFT 14
392 #define NV_TX2_TSO_MAX_SHIFT 14
393 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
394 #define NV_TX2_CHECKSUM_L3 (1<<27)
395 #define NV_TX2_CHECKSUM_L4 (1<<26)
396
397 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
398
399 #define NV_RX_DESCRIPTORVALID (1<<16)
400 #define NV_RX_MISSEDFRAME (1<<17)
401 #define NV_RX_SUBSTRACT1 (1<<18)
402 #define NV_RX_ERROR1 (1<<23)
403 #define NV_RX_ERROR2 (1<<24)
404 #define NV_RX_ERROR3 (1<<25)
405 #define NV_RX_ERROR4 (1<<26)
406 #define NV_RX_CRCERR (1<<27)
407 #define NV_RX_OVERFLOW (1<<28)
408 #define NV_RX_FRAMINGERR (1<<29)
409 #define NV_RX_ERROR (1<<30)
410 #define NV_RX_AVAIL (1<<31)
411
412 #define NV_RX2_CHECKSUMMASK (0x1C000000)
413 #define NV_RX2_CHECKSUMOK1 (0x10000000)
414 #define NV_RX2_CHECKSUMOK2 (0x14000000)
415 #define NV_RX2_CHECKSUMOK3 (0x18000000)
416 #define NV_RX2_DESCRIPTORVALID (1<<29)
417 #define NV_RX2_SUBSTRACT1 (1<<25)
418 #define NV_RX2_ERROR1 (1<<18)
419 #define NV_RX2_ERROR2 (1<<19)
420 #define NV_RX2_ERROR3 (1<<20)
421 #define NV_RX2_ERROR4 (1<<21)
422 #define NV_RX2_CRCERR (1<<22)
423 #define NV_RX2_OVERFLOW (1<<23)
424 #define NV_RX2_FRAMINGERR (1<<24)
425 /* error and avail are the same for both */
426 #define NV_RX2_ERROR (1<<30)
427 #define NV_RX2_AVAIL (1<<31)
428
429 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
430 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
431
432 /* Miscelaneous hardware related defines: */
433 #define NV_PCI_REGSZ_VER1 0x270
434 #define NV_PCI_REGSZ_VER2 0x604
435
436 /* various timeout delays: all in usec */
437 #define NV_TXRX_RESET_DELAY 4
438 #define NV_TXSTOP_DELAY1 10
439 #define NV_TXSTOP_DELAY1MAX 500000
440 #define NV_TXSTOP_DELAY2 100
441 #define NV_RXSTOP_DELAY1 10
442 #define NV_RXSTOP_DELAY1MAX 500000
443 #define NV_RXSTOP_DELAY2 100
444 #define NV_SETUP5_DELAY 5
445 #define NV_SETUP5_DELAYMAX 50000
446 #define NV_POWERUP_DELAY 5
447 #define NV_POWERUP_DELAYMAX 5000
448 #define NV_MIIBUSY_DELAY 50
449 #define NV_MIIPHY_DELAY 10
450 #define NV_MIIPHY_DELAYMAX 10000
451 #define NV_MAC_RESET_DELAY 64
452
453 #define NV_WAKEUPPATTERNS 5
454 #define NV_WAKEUPMASKENTRIES 4
455
456 /* General driver defaults */
457 #define NV_WATCHDOG_TIMEO (5*HZ)
458
459 #define RX_RING_DEFAULT 128
460 #define TX_RING_DEFAULT 256
461 #define RX_RING_MIN 128
462 #define TX_RING_MIN 64
463 #define RING_MAX_DESC_VER_1 1024
464 #define RING_MAX_DESC_VER_2_3 16384
465 /*
466 * Difference between the get and put pointers for the tx ring.
467 * This is used to throttle the amount of data outstanding in the
468 * tx ring.
469 */
470 #define TX_LIMIT_DIFFERENCE 1
471
472 /* rx/tx mac addr + type + vlan + align + slack*/
473 #define NV_RX_HEADERS (64)
474 /* even more slack. */
475 #define NV_RX_ALLOC_PAD (64)
476
477 /* maximum mtu size */
478 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
479 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
480
481 #define OOM_REFILL (1+HZ/20)
482 #define POLL_WAIT (1+HZ/100)
483 #define LINK_TIMEOUT (3*HZ)
484
485 /*
486 * desc_ver values:
487 * The nic supports three different descriptor types:
488 * - DESC_VER_1: Original
489 * - DESC_VER_2: support for jumbo frames.
490 * - DESC_VER_3: 64-bit format.
491 */
492 #define DESC_VER_1 1
493 #define DESC_VER_2 2
494 #define DESC_VER_3 3
495
496 /* PHY defines */
497 #define PHY_OUI_MARVELL 0x5043
498 #define PHY_OUI_CICADA 0x03f1
499 #define PHYID1_OUI_MASK 0x03ff
500 #define PHYID1_OUI_SHFT 6
501 #define PHYID2_OUI_MASK 0xfc00
502 #define PHYID2_OUI_SHFT 10
503 #define PHY_INIT1 0x0f000
504 #define PHY_INIT2 0x0e00
505 #define PHY_INIT3 0x01000
506 #define PHY_INIT4 0x0200
507 #define PHY_INIT5 0x0004
508 #define PHY_INIT6 0x02000
509 #define PHY_GIGABIT 0x0100
510
511 #define PHY_TIMEOUT 0x1
512 #define PHY_ERROR 0x2
513
514 #define PHY_100 0x1
515 #define PHY_1000 0x2
516 #define PHY_HALF 0x100
517
518 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
519 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
520 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
521 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
522 #define NV_PAUSEFRAME_RX_REQ 0x0010
523 #define NV_PAUSEFRAME_TX_REQ 0x0020
524 #define NV_PAUSEFRAME_AUTONEG 0x0040
525
526 /* MSI/MSI-X defines */
527 #define NV_MSI_X_MAX_VECTORS 8
528 #define NV_MSI_X_VECTORS_MASK 0x000f
529 #define NV_MSI_CAPABLE 0x0010
530 #define NV_MSI_X_CAPABLE 0x0020
531 #define NV_MSI_ENABLED 0x0040
532 #define NV_MSI_X_ENABLED 0x0080
533
534 #define NV_MSI_X_VECTOR_ALL 0x0
535 #define NV_MSI_X_VECTOR_RX 0x0
536 #define NV_MSI_X_VECTOR_TX 0x1
537 #define NV_MSI_X_VECTOR_OTHER 0x2
538
539 /*
540 * SMP locking:
541 * All hardware access under dev->priv->lock, except the performance
542 * critical parts:
543 * - rx is (pseudo-) lockless: it relies on the single-threading provided
544 * by the arch code for interrupts.
545 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
546 * needs dev->priv->lock :-(
547 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
548 */
549
550 /* in dev: base, irq */
551 struct fe_priv {
552 spinlock_t lock;
553
554 /* General data:
555 * Locking: spin_lock(&np->lock); */
556 struct net_device_stats stats;
557 int in_shutdown;
558 u32 linkspeed;
559 int duplex;
560 int autoneg;
561 int fixed_mode;
562 int phyaddr;
563 int wolenabled;
564 unsigned int phy_oui;
565 u16 gigabit;
566
567 /* General data: RO fields */
568 dma_addr_t ring_addr;
569 struct pci_dev *pci_dev;
570 u32 orig_mac[2];
571 u32 irqmask;
572 u32 desc_ver;
573 u32 txrxctl_bits;
574 u32 vlanctl_bits;
575 u32 driver_data;
576 u32 register_size;
577
578 void __iomem *base;
579
580 /* rx specific fields.
581 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
582 */
583 ring_type rx_ring;
584 unsigned int cur_rx, refill_rx;
585 struct sk_buff **rx_skbuff;
586 dma_addr_t *rx_dma;
587 unsigned int rx_buf_sz;
588 unsigned int pkt_limit;
589 struct timer_list oom_kick;
590 struct timer_list nic_poll;
591 u32 nic_poll_irq;
592 int rx_ring_size;
593
594 /* media detection workaround.
595 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
596 */
597 int need_linktimer;
598 unsigned long link_timeout;
599 /*
600 * tx specific fields.
601 */
602 ring_type tx_ring;
603 unsigned int next_tx, nic_tx;
604 struct sk_buff **tx_skbuff;
605 dma_addr_t *tx_dma;
606 unsigned int *tx_dma_len;
607 u32 tx_flags;
608 int tx_ring_size;
609 int tx_limit_start;
610 int tx_limit_stop;
611
612 /* vlan fields */
613 struct vlan_group *vlangrp;
614
615 /* msi/msi-x fields */
616 u32 msi_flags;
617 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
618
619 /* flow control */
620 u32 pause_flags;
621 };
622
623 /*
624 * Maximum number of loops until we assume that a bit in the irq mask
625 * is stuck. Overridable with module param.
626 */
627 static int max_interrupt_work = 5;
628
629 /*
630 * Optimization can be either throuput mode or cpu mode
631 *
632 * Throughput Mode: Every tx and rx packet will generate an interrupt.
633 * CPU Mode: Interrupts are controlled by a timer.
634 */
635 #define NV_OPTIMIZATION_MODE_THROUGHPUT 0
636 #define NV_OPTIMIZATION_MODE_CPU 1
637 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
638
639 /*
640 * Poll interval for timer irq
641 *
642 * This interval determines how frequent an interrupt is generated.
643 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
644 * Min = 0, and Max = 65535
645 */
646 static int poll_interval = -1;
647
648 /*
649 * Disable MSI interrupts
650 */
651 static int disable_msi = 0;
652
653 /*
654 * Disable MSIX interrupts
655 */
656 static int disable_msix = 0;
657
658 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
659 {
660 return netdev_priv(dev);
661 }
662
663 static inline u8 __iomem *get_hwbase(struct net_device *dev)
664 {
665 return ((struct fe_priv *)netdev_priv(dev))->base;
666 }
667
668 static inline void pci_push(u8 __iomem *base)
669 {
670 /* force out pending posted writes */
671 readl(base);
672 }
673
674 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
675 {
676 return le32_to_cpu(prd->FlagLen)
677 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
678 }
679
680 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
681 {
682 return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
683 }
684
685 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
686 int delay, int delaymax, const char *msg)
687 {
688 u8 __iomem *base = get_hwbase(dev);
689
690 pci_push(base);
691 do {
692 udelay(delay);
693 delaymax -= delay;
694 if (delaymax < 0) {
695 if (msg)
696 printk(msg);
697 return 1;
698 }
699 } while ((readl(base + offset) & mask) != target);
700 return 0;
701 }
702
703 #define NV_SETUP_RX_RING 0x01
704 #define NV_SETUP_TX_RING 0x02
705
706 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
707 {
708 struct fe_priv *np = get_nvpriv(dev);
709 u8 __iomem *base = get_hwbase(dev);
710
711 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
712 if (rxtx_flags & NV_SETUP_RX_RING) {
713 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
714 }
715 if (rxtx_flags & NV_SETUP_TX_RING) {
716 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
717 }
718 } else {
719 if (rxtx_flags & NV_SETUP_RX_RING) {
720 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
721 writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
722 }
723 if (rxtx_flags & NV_SETUP_TX_RING) {
724 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
725 writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
726 }
727 }
728 }
729
730 static void free_rings(struct net_device *dev)
731 {
732 struct fe_priv *np = get_nvpriv(dev);
733
734 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
735 if(np->rx_ring.orig)
736 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
737 np->rx_ring.orig, np->ring_addr);
738 } else {
739 if (np->rx_ring.ex)
740 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
741 np->rx_ring.ex, np->ring_addr);
742 }
743 if (np->rx_skbuff)
744 kfree(np->rx_skbuff);
745 if (np->rx_dma)
746 kfree(np->rx_dma);
747 if (np->tx_skbuff)
748 kfree(np->tx_skbuff);
749 if (np->tx_dma)
750 kfree(np->tx_dma);
751 if (np->tx_dma_len)
752 kfree(np->tx_dma_len);
753 }
754
755 static int using_multi_irqs(struct net_device *dev)
756 {
757 struct fe_priv *np = get_nvpriv(dev);
758
759 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
760 ((np->msi_flags & NV_MSI_X_ENABLED) &&
761 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
762 return 0;
763 else
764 return 1;
765 }
766
767 static void nv_enable_irq(struct net_device *dev)
768 {
769 struct fe_priv *np = get_nvpriv(dev);
770
771 if (!using_multi_irqs(dev)) {
772 if (np->msi_flags & NV_MSI_X_ENABLED)
773 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
774 else
775 enable_irq(dev->irq);
776 } else {
777 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
778 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
779 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
780 }
781 }
782
783 static void nv_disable_irq(struct net_device *dev)
784 {
785 struct fe_priv *np = get_nvpriv(dev);
786
787 if (!using_multi_irqs(dev)) {
788 if (np->msi_flags & NV_MSI_X_ENABLED)
789 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
790 else
791 disable_irq(dev->irq);
792 } else {
793 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
794 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
795 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
796 }
797 }
798
799 /* In MSIX mode, a write to irqmask behaves as XOR */
800 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
801 {
802 u8 __iomem *base = get_hwbase(dev);
803
804 writel(mask, base + NvRegIrqMask);
805 }
806
807 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
808 {
809 struct fe_priv *np = get_nvpriv(dev);
810 u8 __iomem *base = get_hwbase(dev);
811
812 if (np->msi_flags & NV_MSI_X_ENABLED) {
813 writel(mask, base + NvRegIrqMask);
814 } else {
815 if (np->msi_flags & NV_MSI_ENABLED)
816 writel(0, base + NvRegMSIIrqMask);
817 writel(0, base + NvRegIrqMask);
818 }
819 }
820
821 #define MII_READ (-1)
822 /* mii_rw: read/write a register on the PHY.
823 *
824 * Caller must guarantee serialization
825 */
826 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
827 {
828 u8 __iomem *base = get_hwbase(dev);
829 u32 reg;
830 int retval;
831
832 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
833
834 reg = readl(base + NvRegMIIControl);
835 if (reg & NVREG_MIICTL_INUSE) {
836 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
837 udelay(NV_MIIBUSY_DELAY);
838 }
839
840 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
841 if (value != MII_READ) {
842 writel(value, base + NvRegMIIData);
843 reg |= NVREG_MIICTL_WRITE;
844 }
845 writel(reg, base + NvRegMIIControl);
846
847 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
848 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
849 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
850 dev->name, miireg, addr);
851 retval = -1;
852 } else if (value != MII_READ) {
853 /* it was a write operation - fewer failures are detectable */
854 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
855 dev->name, value, miireg, addr);
856 retval = 0;
857 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
858 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
859 dev->name, miireg, addr);
860 retval = -1;
861 } else {
862 retval = readl(base + NvRegMIIData);
863 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
864 dev->name, miireg, addr, retval);
865 }
866
867 return retval;
868 }
869
870 static int phy_reset(struct net_device *dev)
871 {
872 struct fe_priv *np = netdev_priv(dev);
873 u32 miicontrol;
874 unsigned int tries = 0;
875
876 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
877 miicontrol |= BMCR_RESET;
878 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
879 return -1;
880 }
881
882 /* wait for 500ms */
883 msleep(500);
884
885 /* must wait till reset is deasserted */
886 while (miicontrol & BMCR_RESET) {
887 msleep(10);
888 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
889 /* FIXME: 100 tries seem excessive */
890 if (tries++ > 100)
891 return -1;
892 }
893 return 0;
894 }
895
896 static int phy_init(struct net_device *dev)
897 {
898 struct fe_priv *np = get_nvpriv(dev);
899 u8 __iomem *base = get_hwbase(dev);
900 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
901
902 /* set advertise register */
903 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
904 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
905 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
906 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
907 return PHY_ERROR;
908 }
909
910 /* get phy interface type */
911 phyinterface = readl(base + NvRegPhyInterface);
912
913 /* see if gigabit phy */
914 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
915 if (mii_status & PHY_GIGABIT) {
916 np->gigabit = PHY_GIGABIT;
917 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
918 mii_control_1000 &= ~ADVERTISE_1000HALF;
919 if (phyinterface & PHY_RGMII)
920 mii_control_1000 |= ADVERTISE_1000FULL;
921 else
922 mii_control_1000 &= ~ADVERTISE_1000FULL;
923
924 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
925 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
926 return PHY_ERROR;
927 }
928 }
929 else
930 np->gigabit = 0;
931
932 /* reset the phy */
933 if (phy_reset(dev)) {
934 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
935 return PHY_ERROR;
936 }
937
938 /* phy vendor specific configuration */
939 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
940 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
941 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
942 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
943 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
944 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
945 return PHY_ERROR;
946 }
947 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
948 phy_reserved |= PHY_INIT5;
949 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
950 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
951 return PHY_ERROR;
952 }
953 }
954 if (np->phy_oui == PHY_OUI_CICADA) {
955 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
956 phy_reserved |= PHY_INIT6;
957 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
958 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
959 return PHY_ERROR;
960 }
961 }
962 /* some phys clear out pause advertisment on reset, set it back */
963 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
964
965 /* restart auto negotiation */
966 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
967 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
968 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
969 return PHY_ERROR;
970 }
971
972 return 0;
973 }
974
975 static void nv_start_rx(struct net_device *dev)
976 {
977 struct fe_priv *np = netdev_priv(dev);
978 u8 __iomem *base = get_hwbase(dev);
979
980 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
981 /* Already running? Stop it. */
982 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
983 writel(0, base + NvRegReceiverControl);
984 pci_push(base);
985 }
986 writel(np->linkspeed, base + NvRegLinkSpeed);
987 pci_push(base);
988 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
989 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
990 dev->name, np->duplex, np->linkspeed);
991 pci_push(base);
992 }
993
994 static void nv_stop_rx(struct net_device *dev)
995 {
996 u8 __iomem *base = get_hwbase(dev);
997
998 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
999 writel(0, base + NvRegReceiverControl);
1000 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1001 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1002 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1003
1004 udelay(NV_RXSTOP_DELAY2);
1005 writel(0, base + NvRegLinkSpeed);
1006 }
1007
1008 static void nv_start_tx(struct net_device *dev)
1009 {
1010 u8 __iomem *base = get_hwbase(dev);
1011
1012 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1013 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
1014 pci_push(base);
1015 }
1016
1017 static void nv_stop_tx(struct net_device *dev)
1018 {
1019 u8 __iomem *base = get_hwbase(dev);
1020
1021 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1022 writel(0, base + NvRegTransmitterControl);
1023 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1024 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1025 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1026
1027 udelay(NV_TXSTOP_DELAY2);
1028 writel(0, base + NvRegUnknownTransmitterReg);
1029 }
1030
1031 static void nv_txrx_reset(struct net_device *dev)
1032 {
1033 struct fe_priv *np = netdev_priv(dev);
1034 u8 __iomem *base = get_hwbase(dev);
1035
1036 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1037 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1038 pci_push(base);
1039 udelay(NV_TXRX_RESET_DELAY);
1040 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1041 pci_push(base);
1042 }
1043
1044 static void nv_mac_reset(struct net_device *dev)
1045 {
1046 struct fe_priv *np = netdev_priv(dev);
1047 u8 __iomem *base = get_hwbase(dev);
1048
1049 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1050 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1051 pci_push(base);
1052 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1053 pci_push(base);
1054 udelay(NV_MAC_RESET_DELAY);
1055 writel(0, base + NvRegMacReset);
1056 pci_push(base);
1057 udelay(NV_MAC_RESET_DELAY);
1058 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1059 pci_push(base);
1060 }
1061
1062 /*
1063 * nv_get_stats: dev->get_stats function
1064 * Get latest stats value from the nic.
1065 * Called with read_lock(&dev_base_lock) held for read -
1066 * only synchronized against unregister_netdevice.
1067 */
1068 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1069 {
1070 struct fe_priv *np = netdev_priv(dev);
1071
1072 /* It seems that the nic always generates interrupts and doesn't
1073 * accumulate errors internally. Thus the current values in np->stats
1074 * are already up to date.
1075 */
1076 return &np->stats;
1077 }
1078
1079 /*
1080 * nv_alloc_rx: fill rx ring entries.
1081 * Return 1 if the allocations for the skbs failed and the
1082 * rx engine is without Available descriptors
1083 */
1084 static int nv_alloc_rx(struct net_device *dev)
1085 {
1086 struct fe_priv *np = netdev_priv(dev);
1087 unsigned int refill_rx = np->refill_rx;
1088 int nr;
1089
1090 while (np->cur_rx != refill_rx) {
1091 struct sk_buff *skb;
1092
1093 nr = refill_rx % np->rx_ring_size;
1094 if (np->rx_skbuff[nr] == NULL) {
1095
1096 skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1097 if (!skb)
1098 break;
1099
1100 skb->dev = dev;
1101 np->rx_skbuff[nr] = skb;
1102 } else {
1103 skb = np->rx_skbuff[nr];
1104 }
1105 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
1106 skb->end-skb->data, PCI_DMA_FROMDEVICE);
1107 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1108 np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
1109 wmb();
1110 np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1111 } else {
1112 np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
1113 np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
1114 wmb();
1115 np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1116 }
1117 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1118 dev->name, refill_rx);
1119 refill_rx++;
1120 }
1121 np->refill_rx = refill_rx;
1122 if (np->cur_rx - refill_rx == np->rx_ring_size)
1123 return 1;
1124 return 0;
1125 }
1126
1127 static void nv_do_rx_refill(unsigned long data)
1128 {
1129 struct net_device *dev = (struct net_device *) data;
1130 struct fe_priv *np = netdev_priv(dev);
1131
1132 if (!using_multi_irqs(dev)) {
1133 if (np->msi_flags & NV_MSI_X_ENABLED)
1134 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1135 else
1136 disable_irq(dev->irq);
1137 } else {
1138 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1139 }
1140 if (nv_alloc_rx(dev)) {
1141 spin_lock_irq(&np->lock);
1142 if (!np->in_shutdown)
1143 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1144 spin_unlock_irq(&np->lock);
1145 }
1146 if (!using_multi_irqs(dev)) {
1147 if (np->msi_flags & NV_MSI_X_ENABLED)
1148 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1149 else
1150 enable_irq(dev->irq);
1151 } else {
1152 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1153 }
1154 }
1155
1156 static void nv_init_rx(struct net_device *dev)
1157 {
1158 struct fe_priv *np = netdev_priv(dev);
1159 int i;
1160
1161 np->cur_rx = np->rx_ring_size;
1162 np->refill_rx = 0;
1163 for (i = 0; i < np->rx_ring_size; i++)
1164 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1165 np->rx_ring.orig[i].FlagLen = 0;
1166 else
1167 np->rx_ring.ex[i].FlagLen = 0;
1168 }
1169
1170 static void nv_init_tx(struct net_device *dev)
1171 {
1172 struct fe_priv *np = netdev_priv(dev);
1173 int i;
1174
1175 np->next_tx = np->nic_tx = 0;
1176 for (i = 0; i < np->tx_ring_size; i++) {
1177 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1178 np->tx_ring.orig[i].FlagLen = 0;
1179 else
1180 np->tx_ring.ex[i].FlagLen = 0;
1181 np->tx_skbuff[i] = NULL;
1182 np->tx_dma[i] = 0;
1183 }
1184 }
1185
1186 static int nv_init_ring(struct net_device *dev)
1187 {
1188 nv_init_tx(dev);
1189 nv_init_rx(dev);
1190 return nv_alloc_rx(dev);
1191 }
1192
1193 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1194 {
1195 struct fe_priv *np = netdev_priv(dev);
1196
1197 dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1198 dev->name, skbnr);
1199
1200 if (np->tx_dma[skbnr]) {
1201 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
1202 np->tx_dma_len[skbnr],
1203 PCI_DMA_TODEVICE);
1204 np->tx_dma[skbnr] = 0;
1205 }
1206
1207 if (np->tx_skbuff[skbnr]) {
1208 dev_kfree_skb_any(np->tx_skbuff[skbnr]);
1209 np->tx_skbuff[skbnr] = NULL;
1210 return 1;
1211 } else {
1212 return 0;
1213 }
1214 }
1215
1216 static void nv_drain_tx(struct net_device *dev)
1217 {
1218 struct fe_priv *np = netdev_priv(dev);
1219 unsigned int i;
1220
1221 for (i = 0; i < np->tx_ring_size; i++) {
1222 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1223 np->tx_ring.orig[i].FlagLen = 0;
1224 else
1225 np->tx_ring.ex[i].FlagLen = 0;
1226 if (nv_release_txskb(dev, i))
1227 np->stats.tx_dropped++;
1228 }
1229 }
1230
1231 static void nv_drain_rx(struct net_device *dev)
1232 {
1233 struct fe_priv *np = netdev_priv(dev);
1234 int i;
1235 for (i = 0; i < np->rx_ring_size; i++) {
1236 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1237 np->rx_ring.orig[i].FlagLen = 0;
1238 else
1239 np->rx_ring.ex[i].FlagLen = 0;
1240 wmb();
1241 if (np->rx_skbuff[i]) {
1242 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1243 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1244 PCI_DMA_FROMDEVICE);
1245 dev_kfree_skb(np->rx_skbuff[i]);
1246 np->rx_skbuff[i] = NULL;
1247 }
1248 }
1249 }
1250
1251 static void drain_ring(struct net_device *dev)
1252 {
1253 nv_drain_tx(dev);
1254 nv_drain_rx(dev);
1255 }
1256
1257 /*
1258 * nv_start_xmit: dev->hard_start_xmit function
1259 * Called with dev->xmit_lock held.
1260 */
1261 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1262 {
1263 struct fe_priv *np = netdev_priv(dev);
1264 u32 tx_flags = 0;
1265 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1266 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1267 unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
1268 unsigned int start_nr = np->next_tx % np->tx_ring_size;
1269 unsigned int i;
1270 u32 offset = 0;
1271 u32 bcnt;
1272 u32 size = skb->len-skb->data_len;
1273 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1274 u32 tx_flags_vlan = 0;
1275
1276 /* add fragments to entries count */
1277 for (i = 0; i < fragments; i++) {
1278 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1279 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1280 }
1281
1282 spin_lock_irq(&np->lock);
1283
1284 if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
1285 spin_unlock_irq(&np->lock);
1286 netif_stop_queue(dev);
1287 return NETDEV_TX_BUSY;
1288 }
1289
1290 /* setup the header buffer */
1291 do {
1292 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1293 nr = (nr + 1) % np->tx_ring_size;
1294
1295 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1296 PCI_DMA_TODEVICE);
1297 np->tx_dma_len[nr] = bcnt;
1298
1299 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1300 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1301 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1302 } else {
1303 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1304 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1305 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1306 }
1307 tx_flags = np->tx_flags;
1308 offset += bcnt;
1309 size -= bcnt;
1310 } while(size);
1311
1312 /* setup the fragments */
1313 for (i = 0; i < fragments; i++) {
1314 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1315 u32 size = frag->size;
1316 offset = 0;
1317
1318 do {
1319 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1320 nr = (nr + 1) % np->tx_ring_size;
1321
1322 np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1323 PCI_DMA_TODEVICE);
1324 np->tx_dma_len[nr] = bcnt;
1325
1326 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1327 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1328 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1329 } else {
1330 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1331 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1332 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1333 }
1334 offset += bcnt;
1335 size -= bcnt;
1336 } while (size);
1337 }
1338
1339 /* set last fragment flag */
1340 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1341 np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1342 } else {
1343 np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1344 }
1345
1346 np->tx_skbuff[nr] = skb;
1347
1348 #ifdef NETIF_F_TSO
1349 if (skb_shinfo(skb)->tso_size)
1350 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT);
1351 else
1352 #endif
1353 tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1354
1355 /* vlan tag */
1356 if (np->vlangrp && vlan_tx_tag_present(skb)) {
1357 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1358 }
1359
1360 /* set tx flags */
1361 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1362 np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1363 } else {
1364 np->tx_ring.ex[start_nr].TxVlan = cpu_to_le32(tx_flags_vlan);
1365 np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1366 }
1367
1368 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1369 dev->name, np->next_tx, entries, tx_flags_extra);
1370 {
1371 int j;
1372 for (j=0; j<64; j++) {
1373 if ((j%16) == 0)
1374 dprintk("\n%03x:", j);
1375 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1376 }
1377 dprintk("\n");
1378 }
1379
1380 np->next_tx += entries;
1381
1382 dev->trans_start = jiffies;
1383 spin_unlock_irq(&np->lock);
1384 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1385 pci_push(get_hwbase(dev));
1386 return NETDEV_TX_OK;
1387 }
1388
1389 /*
1390 * nv_tx_done: check for completed packets, release the skbs.
1391 *
1392 * Caller must own np->lock.
1393 */
1394 static void nv_tx_done(struct net_device *dev)
1395 {
1396 struct fe_priv *np = netdev_priv(dev);
1397 u32 Flags;
1398 unsigned int i;
1399 struct sk_buff *skb;
1400
1401 while (np->nic_tx != np->next_tx) {
1402 i = np->nic_tx % np->tx_ring_size;
1403
1404 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1405 Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1406 else
1407 Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1408
1409 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1410 dev->name, np->nic_tx, Flags);
1411 if (Flags & NV_TX_VALID)
1412 break;
1413 if (np->desc_ver == DESC_VER_1) {
1414 if (Flags & NV_TX_LASTPACKET) {
1415 skb = np->tx_skbuff[i];
1416 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1417 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1418 if (Flags & NV_TX_UNDERFLOW)
1419 np->stats.tx_fifo_errors++;
1420 if (Flags & NV_TX_CARRIERLOST)
1421 np->stats.tx_carrier_errors++;
1422 np->stats.tx_errors++;
1423 } else {
1424 np->stats.tx_packets++;
1425 np->stats.tx_bytes += skb->len;
1426 }
1427 }
1428 } else {
1429 if (Flags & NV_TX2_LASTPACKET) {
1430 skb = np->tx_skbuff[i];
1431 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1432 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1433 if (Flags & NV_TX2_UNDERFLOW)
1434 np->stats.tx_fifo_errors++;
1435 if (Flags & NV_TX2_CARRIERLOST)
1436 np->stats.tx_carrier_errors++;
1437 np->stats.tx_errors++;
1438 } else {
1439 np->stats.tx_packets++;
1440 np->stats.tx_bytes += skb->len;
1441 }
1442 }
1443 }
1444 nv_release_txskb(dev, i);
1445 np->nic_tx++;
1446 }
1447 if (np->next_tx - np->nic_tx < np->tx_limit_start)
1448 netif_wake_queue(dev);
1449 }
1450
1451 /*
1452 * nv_tx_timeout: dev->tx_timeout function
1453 * Called with dev->xmit_lock held.
1454 */
1455 static void nv_tx_timeout(struct net_device *dev)
1456 {
1457 struct fe_priv *np = netdev_priv(dev);
1458 u8 __iomem *base = get_hwbase(dev);
1459 u32 status;
1460
1461 if (np->msi_flags & NV_MSI_X_ENABLED)
1462 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1463 else
1464 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1465
1466 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1467
1468 {
1469 int i;
1470
1471 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1472 dev->name, (unsigned long)np->ring_addr,
1473 np->next_tx, np->nic_tx);
1474 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1475 for (i=0;i<=np->register_size;i+= 32) {
1476 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1477 i,
1478 readl(base + i + 0), readl(base + i + 4),
1479 readl(base + i + 8), readl(base + i + 12),
1480 readl(base + i + 16), readl(base + i + 20),
1481 readl(base + i + 24), readl(base + i + 28));
1482 }
1483 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1484 for (i=0;i<np->tx_ring_size;i+= 4) {
1485 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1486 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1487 i,
1488 le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1489 le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1490 le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1491 le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1492 le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1493 le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1494 le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1495 le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1496 } else {
1497 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1498 i,
1499 le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1500 le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1501 le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1502 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1503 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1504 le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1505 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1506 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1507 le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1508 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1509 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1510 le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1511 }
1512 }
1513 }
1514
1515 spin_lock_irq(&np->lock);
1516
1517 /* 1) stop tx engine */
1518 nv_stop_tx(dev);
1519
1520 /* 2) check that the packets were not sent already: */
1521 nv_tx_done(dev);
1522
1523 /* 3) if there are dead entries: clear everything */
1524 if (np->next_tx != np->nic_tx) {
1525 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1526 nv_drain_tx(dev);
1527 np->next_tx = np->nic_tx = 0;
1528 setup_hw_rings(dev, NV_SETUP_TX_RING);
1529 netif_wake_queue(dev);
1530 }
1531
1532 /* 4) restart tx engine */
1533 nv_start_tx(dev);
1534 spin_unlock_irq(&np->lock);
1535 }
1536
1537 /*
1538 * Called when the nic notices a mismatch between the actual data len on the
1539 * wire and the len indicated in the 802 header
1540 */
1541 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1542 {
1543 int hdrlen; /* length of the 802 header */
1544 int protolen; /* length as stored in the proto field */
1545
1546 /* 1) calculate len according to header */
1547 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1548 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1549 hdrlen = VLAN_HLEN;
1550 } else {
1551 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1552 hdrlen = ETH_HLEN;
1553 }
1554 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1555 dev->name, datalen, protolen, hdrlen);
1556 if (protolen > ETH_DATA_LEN)
1557 return datalen; /* Value in proto field not a len, no checks possible */
1558
1559 protolen += hdrlen;
1560 /* consistency checks: */
1561 if (datalen > ETH_ZLEN) {
1562 if (datalen >= protolen) {
1563 /* more data on wire than in 802 header, trim of
1564 * additional data.
1565 */
1566 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1567 dev->name, protolen);
1568 return protolen;
1569 } else {
1570 /* less data on wire than mentioned in header.
1571 * Discard the packet.
1572 */
1573 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1574 dev->name);
1575 return -1;
1576 }
1577 } else {
1578 /* short packet. Accept only if 802 values are also short */
1579 if (protolen > ETH_ZLEN) {
1580 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1581 dev->name);
1582 return -1;
1583 }
1584 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1585 dev->name, datalen);
1586 return datalen;
1587 }
1588 }
1589
1590 static void nv_rx_process(struct net_device *dev)
1591 {
1592 struct fe_priv *np = netdev_priv(dev);
1593 u32 Flags;
1594 u32 vlanflags = 0;
1595
1596 for (;;) {
1597 struct sk_buff *skb;
1598 int len;
1599 int i;
1600 if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
1601 break; /* we scanned the whole ring - do not continue */
1602
1603 i = np->cur_rx % np->rx_ring_size;
1604 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1605 Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1606 len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1607 } else {
1608 Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1609 len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1610 vlanflags = le32_to_cpu(np->rx_ring.ex[i].PacketBufferLow);
1611 }
1612
1613 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1614 dev->name, np->cur_rx, Flags);
1615
1616 if (Flags & NV_RX_AVAIL)
1617 break; /* still owned by hardware, */
1618
1619 /*
1620 * the packet is for us - immediately tear down the pci mapping.
1621 * TODO: check if a prefetch of the first cacheline improves
1622 * the performance.
1623 */
1624 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1625 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1626 PCI_DMA_FROMDEVICE);
1627
1628 {
1629 int j;
1630 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1631 for (j=0; j<64; j++) {
1632 if ((j%16) == 0)
1633 dprintk("\n%03x:", j);
1634 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1635 }
1636 dprintk("\n");
1637 }
1638 /* look at what we actually got: */
1639 if (np->desc_ver == DESC_VER_1) {
1640 if (!(Flags & NV_RX_DESCRIPTORVALID))
1641 goto next_pkt;
1642
1643 if (Flags & NV_RX_ERROR) {
1644 if (Flags & NV_RX_MISSEDFRAME) {
1645 np->stats.rx_missed_errors++;
1646 np->stats.rx_errors++;
1647 goto next_pkt;
1648 }
1649 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1650 np->stats.rx_errors++;
1651 goto next_pkt;
1652 }
1653 if (Flags & NV_RX_CRCERR) {
1654 np->stats.rx_crc_errors++;
1655 np->stats.rx_errors++;
1656 goto next_pkt;
1657 }
1658 if (Flags & NV_RX_OVERFLOW) {
1659 np->stats.rx_over_errors++;
1660 np->stats.rx_errors++;
1661 goto next_pkt;
1662 }
1663 if (Flags & NV_RX_ERROR4) {
1664 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1665 if (len < 0) {
1666 np->stats.rx_errors++;
1667 goto next_pkt;
1668 }
1669 }
1670 /* framing errors are soft errors. */
1671 if (Flags & NV_RX_FRAMINGERR) {
1672 if (Flags & NV_RX_SUBSTRACT1) {
1673 len--;
1674 }
1675 }
1676 }
1677 } else {
1678 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1679 goto next_pkt;
1680
1681 if (Flags & NV_RX2_ERROR) {
1682 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1683 np->stats.rx_errors++;
1684 goto next_pkt;
1685 }
1686 if (Flags & NV_RX2_CRCERR) {
1687 np->stats.rx_crc_errors++;
1688 np->stats.rx_errors++;
1689 goto next_pkt;
1690 }
1691 if (Flags & NV_RX2_OVERFLOW) {
1692 np->stats.rx_over_errors++;
1693 np->stats.rx_errors++;
1694 goto next_pkt;
1695 }
1696 if (Flags & NV_RX2_ERROR4) {
1697 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1698 if (len < 0) {
1699 np->stats.rx_errors++;
1700 goto next_pkt;
1701 }
1702 }
1703 /* framing errors are soft errors */
1704 if (Flags & NV_RX2_FRAMINGERR) {
1705 if (Flags & NV_RX2_SUBSTRACT1) {
1706 len--;
1707 }
1708 }
1709 }
1710 if (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) {
1711 Flags &= NV_RX2_CHECKSUMMASK;
1712 if (Flags == NV_RX2_CHECKSUMOK1 ||
1713 Flags == NV_RX2_CHECKSUMOK2 ||
1714 Flags == NV_RX2_CHECKSUMOK3) {
1715 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1716 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1717 } else {
1718 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1719 }
1720 }
1721 }
1722 /* got a valid packet - forward it to the network core */
1723 skb = np->rx_skbuff[i];
1724 np->rx_skbuff[i] = NULL;
1725
1726 skb_put(skb, len);
1727 skb->protocol = eth_type_trans(skb, dev);
1728 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1729 dev->name, np->cur_rx, len, skb->protocol);
1730 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) {
1731 vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK);
1732 } else {
1733 netif_rx(skb);
1734 }
1735 dev->last_rx = jiffies;
1736 np->stats.rx_packets++;
1737 np->stats.rx_bytes += len;
1738 next_pkt:
1739 np->cur_rx++;
1740 }
1741 }
1742
1743 static void set_bufsize(struct net_device *dev)
1744 {
1745 struct fe_priv *np = netdev_priv(dev);
1746
1747 if (dev->mtu <= ETH_DATA_LEN)
1748 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1749 else
1750 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1751 }
1752
1753 /*
1754 * nv_change_mtu: dev->change_mtu function
1755 * Called with dev_base_lock held for read.
1756 */
1757 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1758 {
1759 struct fe_priv *np = netdev_priv(dev);
1760 int old_mtu;
1761
1762 if (new_mtu < 64 || new_mtu > np->pkt_limit)
1763 return -EINVAL;
1764
1765 old_mtu = dev->mtu;
1766 dev->mtu = new_mtu;
1767
1768 /* return early if the buffer sizes will not change */
1769 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1770 return 0;
1771 if (old_mtu == new_mtu)
1772 return 0;
1773
1774 /* synchronized against open : rtnl_lock() held by caller */
1775 if (netif_running(dev)) {
1776 u8 __iomem *base = get_hwbase(dev);
1777 /*
1778 * It seems that the nic preloads valid ring entries into an
1779 * internal buffer. The procedure for flushing everything is
1780 * guessed, there is probably a simpler approach.
1781 * Changing the MTU is a rare event, it shouldn't matter.
1782 */
1783 nv_disable_irq(dev);
1784 spin_lock_bh(&dev->xmit_lock);
1785 spin_lock(&np->lock);
1786 /* stop engines */
1787 nv_stop_rx(dev);
1788 nv_stop_tx(dev);
1789 nv_txrx_reset(dev);
1790 /* drain rx queue */
1791 nv_drain_rx(dev);
1792 nv_drain_tx(dev);
1793 /* reinit driver view of the rx queue */
1794 set_bufsize(dev);
1795 if (nv_init_ring(dev)) {
1796 if (!np->in_shutdown)
1797 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1798 }
1799 /* reinit nic view of the rx queue */
1800 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1801 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
1802 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
1803 base + NvRegRingSizes);
1804 pci_push(base);
1805 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1806 pci_push(base);
1807
1808 /* restart rx engine */
1809 nv_start_rx(dev);
1810 nv_start_tx(dev);
1811 spin_unlock(&np->lock);
1812 spin_unlock_bh(&dev->xmit_lock);
1813 nv_enable_irq(dev);
1814 }
1815 return 0;
1816 }
1817
1818 static void nv_copy_mac_to_hw(struct net_device *dev)
1819 {
1820 u8 __iomem *base = get_hwbase(dev);
1821 u32 mac[2];
1822
1823 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1824 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1825 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1826
1827 writel(mac[0], base + NvRegMacAddrA);
1828 writel(mac[1], base + NvRegMacAddrB);
1829 }
1830
1831 /*
1832 * nv_set_mac_address: dev->set_mac_address function
1833 * Called with rtnl_lock() held.
1834 */
1835 static int nv_set_mac_address(struct net_device *dev, void *addr)
1836 {
1837 struct fe_priv *np = netdev_priv(dev);
1838 struct sockaddr *macaddr = (struct sockaddr*)addr;
1839
1840 if(!is_valid_ether_addr(macaddr->sa_data))
1841 return -EADDRNOTAVAIL;
1842
1843 /* synchronized against open : rtnl_lock() held by caller */
1844 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1845
1846 if (netif_running(dev)) {
1847 spin_lock_bh(&dev->xmit_lock);
1848 spin_lock_irq(&np->lock);
1849
1850 /* stop rx engine */
1851 nv_stop_rx(dev);
1852
1853 /* set mac address */
1854 nv_copy_mac_to_hw(dev);
1855
1856 /* restart rx engine */
1857 nv_start_rx(dev);
1858 spin_unlock_irq(&np->lock);
1859 spin_unlock_bh(&dev->xmit_lock);
1860 } else {
1861 nv_copy_mac_to_hw(dev);
1862 }
1863 return 0;
1864 }
1865
1866 /*
1867 * nv_set_multicast: dev->set_multicast function
1868 * Called with dev->xmit_lock held.
1869 */
1870 static void nv_set_multicast(struct net_device *dev)
1871 {
1872 struct fe_priv *np = netdev_priv(dev);
1873 u8 __iomem *base = get_hwbase(dev);
1874 u32 addr[2];
1875 u32 mask[2];
1876 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
1877
1878 memset(addr, 0, sizeof(addr));
1879 memset(mask, 0, sizeof(mask));
1880
1881 if (dev->flags & IFF_PROMISC) {
1882 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1883 pff |= NVREG_PFF_PROMISC;
1884 } else {
1885 pff |= NVREG_PFF_MYADDR;
1886
1887 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1888 u32 alwaysOff[2];
1889 u32 alwaysOn[2];
1890
1891 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1892 if (dev->flags & IFF_ALLMULTI) {
1893 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1894 } else {
1895 struct dev_mc_list *walk;
1896
1897 walk = dev->mc_list;
1898 while (walk != NULL) {
1899 u32 a, b;
1900 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1901 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1902 alwaysOn[0] &= a;
1903 alwaysOff[0] &= ~a;
1904 alwaysOn[1] &= b;
1905 alwaysOff[1] &= ~b;
1906 walk = walk->next;
1907 }
1908 }
1909 addr[0] = alwaysOn[0];
1910 addr[1] = alwaysOn[1];
1911 mask[0] = alwaysOn[0] | alwaysOff[0];
1912 mask[1] = alwaysOn[1] | alwaysOff[1];
1913 }
1914 }
1915 addr[0] |= NVREG_MCASTADDRA_FORCE;
1916 pff |= NVREG_PFF_ALWAYS;
1917 spin_lock_irq(&np->lock);
1918 nv_stop_rx(dev);
1919 writel(addr[0], base + NvRegMulticastAddrA);
1920 writel(addr[1], base + NvRegMulticastAddrB);
1921 writel(mask[0], base + NvRegMulticastMaskA);
1922 writel(mask[1], base + NvRegMulticastMaskB);
1923 writel(pff, base + NvRegPacketFilterFlags);
1924 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1925 dev->name);
1926 nv_start_rx(dev);
1927 spin_unlock_irq(&np->lock);
1928 }
1929
1930 void nv_update_pause(struct net_device *dev, u32 pause_flags)
1931 {
1932 struct fe_priv *np = netdev_priv(dev);
1933 u8 __iomem *base = get_hwbase(dev);
1934
1935 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
1936
1937 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
1938 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
1939 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
1940 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
1941 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
1942 } else {
1943 writel(pff, base + NvRegPacketFilterFlags);
1944 }
1945 }
1946 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
1947 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
1948 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
1949 writel(NVREG_TX_PAUSEFRAME_ENABLE, base + NvRegTxPauseFrame);
1950 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
1951 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
1952 } else {
1953 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
1954 writel(regmisc, base + NvRegMisc1);
1955 }
1956 }
1957 }
1958
1959 /**
1960 * nv_update_linkspeed: Setup the MAC according to the link partner
1961 * @dev: Network device to be configured
1962 *
1963 * The function queries the PHY and checks if there is a link partner.
1964 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
1965 * set to 10 MBit HD.
1966 *
1967 * The function returns 0 if there is no link partner and 1 if there is
1968 * a good link partner.
1969 */
1970 static int nv_update_linkspeed(struct net_device *dev)
1971 {
1972 struct fe_priv *np = netdev_priv(dev);
1973 u8 __iomem *base = get_hwbase(dev);
1974 int adv = 0;
1975 int lpa = 0;
1976 int adv_lpa, adv_pause, lpa_pause;
1977 int newls = np->linkspeed;
1978 int newdup = np->duplex;
1979 int mii_status;
1980 int retval = 0;
1981 u32 control_1000, status_1000, phyreg, pause_flags;
1982
1983 /* BMSR_LSTATUS is latched, read it twice:
1984 * we want the current value.
1985 */
1986 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1987 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1988
1989 if (!(mii_status & BMSR_LSTATUS)) {
1990 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1991 dev->name);
1992 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1993 newdup = 0;
1994 retval = 0;
1995 goto set_speed;
1996 }
1997
1998 if (np->autoneg == 0) {
1999 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2000 dev->name, np->fixed_mode);
2001 if (np->fixed_mode & LPA_100FULL) {
2002 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2003 newdup = 1;
2004 } else if (np->fixed_mode & LPA_100HALF) {
2005 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2006 newdup = 0;
2007 } else if (np->fixed_mode & LPA_10FULL) {
2008 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2009 newdup = 1;
2010 } else {
2011 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2012 newdup = 0;
2013 }
2014 retval = 1;
2015 goto set_speed;
2016 }
2017 /* check auto negotiation is complete */
2018 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2019 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2020 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2021 newdup = 0;
2022 retval = 0;
2023 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2024 goto set_speed;
2025 }
2026
2027 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2028 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2029 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2030 dev->name, adv, lpa);
2031
2032 retval = 1;
2033 if (np->gigabit == PHY_GIGABIT) {
2034 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2035 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2036
2037 if ((control_1000 & ADVERTISE_1000FULL) &&
2038 (status_1000 & LPA_1000FULL)) {
2039 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2040 dev->name);
2041 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2042 newdup = 1;
2043 goto set_speed;
2044 }
2045 }
2046
2047 /* FIXME: handle parallel detection properly */
2048 adv_lpa = lpa & adv;
2049 if (adv_lpa & LPA_100FULL) {
2050 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2051 newdup = 1;
2052 } else if (adv_lpa & LPA_100HALF) {
2053 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2054 newdup = 0;
2055 } else if (adv_lpa & LPA_10FULL) {
2056 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2057 newdup = 1;
2058 } else if (adv_lpa & LPA_10HALF) {
2059 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2060 newdup = 0;
2061 } else {
2062 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2063 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2064 newdup = 0;
2065 }
2066
2067 set_speed:
2068 if (np->duplex == newdup && np->linkspeed == newls)
2069 return retval;
2070
2071 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2072 dev->name, np->linkspeed, np->duplex, newls, newdup);
2073
2074 np->duplex = newdup;
2075 np->linkspeed = newls;
2076
2077 if (np->gigabit == PHY_GIGABIT) {
2078 phyreg = readl(base + NvRegRandomSeed);
2079 phyreg &= ~(0x3FF00);
2080 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2081 phyreg |= NVREG_RNDSEED_FORCE3;
2082 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2083 phyreg |= NVREG_RNDSEED_FORCE2;
2084 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2085 phyreg |= NVREG_RNDSEED_FORCE;
2086 writel(phyreg, base + NvRegRandomSeed);
2087 }
2088
2089 phyreg = readl(base + NvRegPhyInterface);
2090 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2091 if (np->duplex == 0)
2092 phyreg |= PHY_HALF;
2093 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2094 phyreg |= PHY_100;
2095 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2096 phyreg |= PHY_1000;
2097 writel(phyreg, base + NvRegPhyInterface);
2098
2099 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2100 base + NvRegMisc1);
2101 pci_push(base);
2102 writel(np->linkspeed, base + NvRegLinkSpeed);
2103 pci_push(base);
2104
2105 pause_flags = 0;
2106 /* setup pause frame */
2107 if (np->duplex != 0) {
2108 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2109 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2110 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2111
2112 switch (adv_pause) {
2113 case (ADVERTISE_PAUSE_CAP):
2114 if (lpa_pause & LPA_PAUSE_CAP) {
2115 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2116 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2117 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2118 }
2119 break;
2120 case (ADVERTISE_PAUSE_ASYM):
2121 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2122 {
2123 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2124 }
2125 break;
2126 case (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM):
2127 if (lpa_pause & LPA_PAUSE_CAP)
2128 {
2129 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2130 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2131 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2132 }
2133 if (lpa_pause == LPA_PAUSE_ASYM)
2134 {
2135 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2136 }
2137 break;
2138 }
2139 } else {
2140 pause_flags = np->pause_flags;
2141 }
2142 }
2143 nv_update_pause(dev, pause_flags);
2144
2145 return retval;
2146 }
2147
2148 static void nv_linkchange(struct net_device *dev)
2149 {
2150 if (nv_update_linkspeed(dev)) {
2151 if (!netif_carrier_ok(dev)) {
2152 netif_carrier_on(dev);
2153 printk(KERN_INFO "%s: link up.\n", dev->name);
2154 nv_start_rx(dev);
2155 }
2156 } else {
2157 if (netif_carrier_ok(dev)) {
2158 netif_carrier_off(dev);
2159 printk(KERN_INFO "%s: link down.\n", dev->name);
2160 nv_stop_rx(dev);
2161 }
2162 }
2163 }
2164
2165 static void nv_link_irq(struct net_device *dev)
2166 {
2167 u8 __iomem *base = get_hwbase(dev);
2168 u32 miistat;
2169
2170 miistat = readl(base + NvRegMIIStatus);
2171 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2172 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2173
2174 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2175 nv_linkchange(dev);
2176 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2177 }
2178
2179 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
2180 {
2181 struct net_device *dev = (struct net_device *) data;
2182 struct fe_priv *np = netdev_priv(dev);
2183 u8 __iomem *base = get_hwbase(dev);
2184 u32 events;
2185 int i;
2186
2187 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2188
2189 for (i=0; ; i++) {
2190 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2191 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2192 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2193 } else {
2194 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2195 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2196 }
2197 pci_push(base);
2198 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2199 if (!(events & np->irqmask))
2200 break;
2201
2202 spin_lock(&np->lock);
2203 nv_tx_done(dev);
2204 spin_unlock(&np->lock);
2205
2206 nv_rx_process(dev);
2207 if (nv_alloc_rx(dev)) {
2208 spin_lock(&np->lock);
2209 if (!np->in_shutdown)
2210 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2211 spin_unlock(&np->lock);
2212 }
2213
2214 if (events & NVREG_IRQ_LINK) {
2215 spin_lock(&np->lock);
2216 nv_link_irq(dev);
2217 spin_unlock(&np->lock);
2218 }
2219 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2220 spin_lock(&np->lock);
2221 nv_linkchange(dev);
2222 spin_unlock(&np->lock);
2223 np->link_timeout = jiffies + LINK_TIMEOUT;
2224 }
2225 if (events & (NVREG_IRQ_TX_ERR)) {
2226 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2227 dev->name, events);
2228 }
2229 if (events & (NVREG_IRQ_UNKNOWN)) {
2230 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2231 dev->name, events);
2232 }
2233 if (i > max_interrupt_work) {
2234 spin_lock(&np->lock);
2235 /* disable interrupts on the nic */
2236 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2237 writel(0, base + NvRegIrqMask);
2238 else
2239 writel(np->irqmask, base + NvRegIrqMask);
2240 pci_push(base);
2241
2242 if (!np->in_shutdown) {
2243 np->nic_poll_irq = np->irqmask;
2244 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2245 }
2246 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2247 spin_unlock(&np->lock);
2248 break;
2249 }
2250
2251 }
2252 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2253
2254 return IRQ_RETVAL(i);
2255 }
2256
2257 static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs)
2258 {
2259 struct net_device *dev = (struct net_device *) data;
2260 struct fe_priv *np = netdev_priv(dev);
2261 u8 __iomem *base = get_hwbase(dev);
2262 u32 events;
2263 int i;
2264
2265 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2266
2267 for (i=0; ; i++) {
2268 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2269 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2270 pci_push(base);
2271 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2272 if (!(events & np->irqmask))
2273 break;
2274
2275 spin_lock_irq(&np->lock);
2276 nv_tx_done(dev);
2277 spin_unlock_irq(&np->lock);
2278
2279 if (events & (NVREG_IRQ_TX_ERR)) {
2280 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2281 dev->name, events);
2282 }
2283 if (i > max_interrupt_work) {
2284 spin_lock_irq(&np->lock);
2285 /* disable interrupts on the nic */
2286 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2287 pci_push(base);
2288
2289 if (!np->in_shutdown) {
2290 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2291 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2292 }
2293 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2294 spin_unlock_irq(&np->lock);
2295 break;
2296 }
2297
2298 }
2299 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2300
2301 return IRQ_RETVAL(i);
2302 }
2303
2304 static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2305 {
2306 struct net_device *dev = (struct net_device *) data;
2307 struct fe_priv *np = netdev_priv(dev);
2308 u8 __iomem *base = get_hwbase(dev);
2309 u32 events;
2310 int i;
2311
2312 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2313
2314 for (i=0; ; i++) {
2315 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2316 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2317 pci_push(base);
2318 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2319 if (!(events & np->irqmask))
2320 break;
2321
2322 nv_rx_process(dev);
2323 if (nv_alloc_rx(dev)) {
2324 spin_lock_irq(&np->lock);
2325 if (!np->in_shutdown)
2326 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2327 spin_unlock_irq(&np->lock);
2328 }
2329
2330 if (i > max_interrupt_work) {
2331 spin_lock_irq(&np->lock);
2332 /* disable interrupts on the nic */
2333 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2334 pci_push(base);
2335
2336 if (!np->in_shutdown) {
2337 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2338 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2339 }
2340 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2341 spin_unlock_irq(&np->lock);
2342 break;
2343 }
2344
2345 }
2346 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2347
2348 return IRQ_RETVAL(i);
2349 }
2350
2351 static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
2352 {
2353 struct net_device *dev = (struct net_device *) data;
2354 struct fe_priv *np = netdev_priv(dev);
2355 u8 __iomem *base = get_hwbase(dev);
2356 u32 events;
2357 int i;
2358
2359 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2360
2361 for (i=0; ; i++) {
2362 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2363 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2364 pci_push(base);
2365 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2366 if (!(events & np->irqmask))
2367 break;
2368
2369 if (events & NVREG_IRQ_LINK) {
2370 spin_lock_irq(&np->lock);
2371 nv_link_irq(dev);
2372 spin_unlock_irq(&np->lock);
2373 }
2374 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2375 spin_lock_irq(&np->lock);
2376 nv_linkchange(dev);
2377 spin_unlock_irq(&np->lock);
2378 np->link_timeout = jiffies + LINK_TIMEOUT;
2379 }
2380 if (events & (NVREG_IRQ_UNKNOWN)) {
2381 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2382 dev->name, events);
2383 }
2384 if (i > max_interrupt_work) {
2385 spin_lock_irq(&np->lock);
2386 /* disable interrupts on the nic */
2387 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2388 pci_push(base);
2389
2390 if (!np->in_shutdown) {
2391 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2392 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2393 }
2394 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2395 spin_unlock_irq(&np->lock);
2396 break;
2397 }
2398
2399 }
2400 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2401
2402 return IRQ_RETVAL(i);
2403 }
2404
2405 static void nv_do_nic_poll(unsigned long data)
2406 {
2407 struct net_device *dev = (struct net_device *) data;
2408 struct fe_priv *np = netdev_priv(dev);
2409 u8 __iomem *base = get_hwbase(dev);
2410 u32 mask = 0;
2411
2412 /*
2413 * First disable irq(s) and then
2414 * reenable interrupts on the nic, we have to do this before calling
2415 * nv_nic_irq because that may decide to do otherwise
2416 */
2417
2418 if (!using_multi_irqs(dev)) {
2419 if (np->msi_flags & NV_MSI_X_ENABLED)
2420 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2421 else
2422 disable_irq(dev->irq);
2423 mask = np->irqmask;
2424 } else {
2425 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2426 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2427 mask |= NVREG_IRQ_RX_ALL;
2428 }
2429 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2430 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2431 mask |= NVREG_IRQ_TX_ALL;
2432 }
2433 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2434 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2435 mask |= NVREG_IRQ_OTHER;
2436 }
2437 }
2438 np->nic_poll_irq = 0;
2439
2440 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2441
2442 writel(mask, base + NvRegIrqMask);
2443 pci_push(base);
2444
2445 if (!using_multi_irqs(dev)) {
2446 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
2447 if (np->msi_flags & NV_MSI_X_ENABLED)
2448 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2449 else
2450 enable_irq(dev->irq);
2451 } else {
2452 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2453 nv_nic_irq_rx((int) 0, (void *) data, (struct pt_regs *) NULL);
2454 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2455 }
2456 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2457 nv_nic_irq_tx((int) 0, (void *) data, (struct pt_regs *) NULL);
2458 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2459 }
2460 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2461 nv_nic_irq_other((int) 0, (void *) data, (struct pt_regs *) NULL);
2462 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2463 }
2464 }
2465 }
2466
2467 #ifdef CONFIG_NET_POLL_CONTROLLER
2468 static void nv_poll_controller(struct net_device *dev)
2469 {
2470 nv_do_nic_poll((unsigned long) dev);
2471 }
2472 #endif
2473
2474 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2475 {
2476 struct fe_priv *np = netdev_priv(dev);
2477 strcpy(info->driver, "forcedeth");
2478 strcpy(info->version, FORCEDETH_VERSION);
2479 strcpy(info->bus_info, pci_name(np->pci_dev));
2480 }
2481
2482 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2483 {
2484 struct fe_priv *np = netdev_priv(dev);
2485 wolinfo->supported = WAKE_MAGIC;
2486
2487 spin_lock_irq(&np->lock);
2488 if (np->wolenabled)
2489 wolinfo->wolopts = WAKE_MAGIC;
2490 spin_unlock_irq(&np->lock);
2491 }
2492
2493 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2494 {
2495 struct fe_priv *np = netdev_priv(dev);
2496 u8 __iomem *base = get_hwbase(dev);
2497 u32 flags = 0;
2498
2499 if (wolinfo->wolopts == 0) {
2500 np->wolenabled = 0;
2501 } else if (wolinfo->wolopts & WAKE_MAGIC) {
2502 np->wolenabled = 1;
2503 flags = NVREG_WAKEUPFLAGS_ENABLE;
2504 }
2505 if (netif_running(dev)) {
2506 spin_lock_irq(&np->lock);
2507 writel(flags, base + NvRegWakeUpFlags);
2508 spin_unlock_irq(&np->lock);
2509 }
2510 return 0;
2511 }
2512
2513 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2514 {
2515 struct fe_priv *np = netdev_priv(dev);
2516 int adv;
2517
2518 spin_lock_irq(&np->lock);
2519 ecmd->port = PORT_MII;
2520 if (!netif_running(dev)) {
2521 /* We do not track link speed / duplex setting if the
2522 * interface is disabled. Force a link check */
2523 if (nv_update_linkspeed(dev)) {
2524 if (!netif_carrier_ok(dev))
2525 netif_carrier_on(dev);
2526 } else {
2527 if (netif_carrier_ok(dev))
2528 netif_carrier_off(dev);
2529 }
2530 }
2531
2532 if (netif_carrier_ok(dev)) {
2533 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
2534 case NVREG_LINKSPEED_10:
2535 ecmd->speed = SPEED_10;
2536 break;
2537 case NVREG_LINKSPEED_100:
2538 ecmd->speed = SPEED_100;
2539 break;
2540 case NVREG_LINKSPEED_1000:
2541 ecmd->speed = SPEED_1000;
2542 break;
2543 }
2544 ecmd->duplex = DUPLEX_HALF;
2545 if (np->duplex)
2546 ecmd->duplex = DUPLEX_FULL;
2547 } else {
2548 ecmd->speed = -1;
2549 ecmd->duplex = -1;
2550 }
2551
2552 ecmd->autoneg = np->autoneg;
2553
2554 ecmd->advertising = ADVERTISED_MII;
2555 if (np->autoneg) {
2556 ecmd->advertising |= ADVERTISED_Autoneg;
2557 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2558 if (adv & ADVERTISE_10HALF)
2559 ecmd->advertising |= ADVERTISED_10baseT_Half;
2560 if (adv & ADVERTISE_10FULL)
2561 ecmd->advertising |= ADVERTISED_10baseT_Full;
2562 if (adv & ADVERTISE_100HALF)
2563 ecmd->advertising |= ADVERTISED_100baseT_Half;
2564 if (adv & ADVERTISE_100FULL)
2565 ecmd->advertising |= ADVERTISED_100baseT_Full;
2566 if (np->gigabit == PHY_GIGABIT) {
2567 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2568 if (adv & ADVERTISE_1000FULL)
2569 ecmd->advertising |= ADVERTISED_1000baseT_Full;
2570 }
2571 }
2572 ecmd->supported = (SUPPORTED_Autoneg |
2573 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2574 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2575 SUPPORTED_MII);
2576 if (np->gigabit == PHY_GIGABIT)
2577 ecmd->supported |= SUPPORTED_1000baseT_Full;
2578
2579 ecmd->phy_address = np->phyaddr;
2580 ecmd->transceiver = XCVR_EXTERNAL;
2581
2582 /* ignore maxtxpkt, maxrxpkt for now */
2583 spin_unlock_irq(&np->lock);
2584 return 0;
2585 }
2586
2587 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2588 {
2589 struct fe_priv *np = netdev_priv(dev);
2590
2591 if (ecmd->port != PORT_MII)
2592 return -EINVAL;
2593 if (ecmd->transceiver != XCVR_EXTERNAL)
2594 return -EINVAL;
2595 if (ecmd->phy_address != np->phyaddr) {
2596 /* TODO: support switching between multiple phys. Should be
2597 * trivial, but not enabled due to lack of test hardware. */
2598 return -EINVAL;
2599 }
2600 if (ecmd->autoneg == AUTONEG_ENABLE) {
2601 u32 mask;
2602
2603 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2604 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
2605 if (np->gigabit == PHY_GIGABIT)
2606 mask |= ADVERTISED_1000baseT_Full;
2607
2608 if ((ecmd->advertising & mask) == 0)
2609 return -EINVAL;
2610
2611 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2612 /* Note: autonegotiation disable, speed 1000 intentionally
2613 * forbidden - noone should need that. */
2614
2615 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2616 return -EINVAL;
2617 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2618 return -EINVAL;
2619 } else {
2620 return -EINVAL;
2621 }
2622
2623 netif_carrier_off(dev);
2624 if (netif_running(dev)) {
2625 nv_disable_irq(dev);
2626 spin_lock_bh(&dev->xmit_lock);
2627 spin_lock(&np->lock);
2628 /* stop engines */
2629 nv_stop_rx(dev);
2630 nv_stop_tx(dev);
2631 spin_unlock(&np->lock);
2632 spin_unlock_bh(&dev->xmit_lock);
2633 }
2634
2635 if (ecmd->autoneg == AUTONEG_ENABLE) {
2636 int adv, bmcr;
2637
2638 np->autoneg = 1;
2639
2640 /* advertise only what has been requested */
2641 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2642 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2643 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2644 adv |= ADVERTISE_10HALF;
2645 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2646 adv |= ADVERTISE_10FULL;
2647 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2648 adv |= ADVERTISE_100HALF;
2649 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2650 adv |= ADVERTISE_100FULL;
2651 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
2652 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2653 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2654 adv |= ADVERTISE_PAUSE_ASYM;
2655 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2656
2657 if (np->gigabit == PHY_GIGABIT) {
2658 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2659 adv &= ~ADVERTISE_1000FULL;
2660 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
2661 adv |= ADVERTISE_1000FULL;
2662 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
2663 }
2664
2665 if (netif_running(dev))
2666 printk(KERN_INFO "%s: link down.\n", dev->name);
2667 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2668 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2669 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2670
2671 } else {
2672 int adv, bmcr;
2673
2674 np->autoneg = 0;
2675
2676 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2677 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2678 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
2679 adv |= ADVERTISE_10HALF;
2680 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
2681 adv |= ADVERTISE_10FULL;
2682 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
2683 adv |= ADVERTISE_100HALF;
2684 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
2685 adv |= ADVERTISE_100FULL;
2686 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
2687 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
2688 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2689 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2690 }
2691 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
2692 adv |= ADVERTISE_PAUSE_ASYM;
2693 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2694 }
2695 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2696 np->fixed_mode = adv;
2697
2698 if (np->gigabit == PHY_GIGABIT) {
2699 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2700 adv &= ~ADVERTISE_1000FULL;
2701 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
2702 }
2703
2704 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2705 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
2706 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
2707 bmcr |= BMCR_FULLDPLX;
2708 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
2709 bmcr |= BMCR_SPEED100;
2710 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2711 if (np->phy_oui == PHY_OUI_MARVELL) {
2712 /* reset the phy */
2713 if (phy_reset(dev)) {
2714 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
2715 return -EINVAL;
2716 }
2717 } else if (netif_running(dev)) {
2718 /* Wait a bit and then reconfigure the nic. */
2719 udelay(10);
2720 nv_linkchange(dev);
2721 }
2722 }
2723
2724 if (netif_running(dev)) {
2725 nv_start_rx(dev);
2726 nv_start_tx(dev);
2727 nv_enable_irq(dev);
2728 }
2729
2730 return 0;
2731 }
2732
2733 #define FORCEDETH_REGS_VER 1
2734
2735 static int nv_get_regs_len(struct net_device *dev)
2736 {
2737 struct fe_priv *np = netdev_priv(dev);
2738 return np->register_size;
2739 }
2740
2741 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2742 {
2743 struct fe_priv *np = netdev_priv(dev);
2744 u8 __iomem *base = get_hwbase(dev);
2745 u32 *rbuf = buf;
2746 int i;
2747
2748 regs->version = FORCEDETH_REGS_VER;
2749 spin_lock_irq(&np->lock);
2750 for (i = 0;i <= np->register_size/sizeof(u32); i++)
2751 rbuf[i] = readl(base + i*sizeof(u32));
2752 spin_unlock_irq(&np->lock);
2753 }
2754
2755 static int nv_nway_reset(struct net_device *dev)
2756 {
2757 struct fe_priv *np = netdev_priv(dev);
2758 int ret;
2759
2760 if (np->autoneg) {
2761 int bmcr;
2762
2763 netif_carrier_off(dev);
2764 if (netif_running(dev)) {
2765 nv_disable_irq(dev);
2766 spin_lock_bh(&dev->xmit_lock);
2767 spin_lock(&np->lock);
2768 /* stop engines */
2769 nv_stop_rx(dev);
2770 nv_stop_tx(dev);
2771 spin_unlock(&np->lock);
2772 spin_unlock_bh(&dev->xmit_lock);
2773 printk(KERN_INFO "%s: link down.\n", dev->name);
2774 }
2775
2776 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2777 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2778 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2779
2780 if (netif_running(dev)) {
2781 nv_start_rx(dev);
2782 nv_start_tx(dev);
2783 nv_enable_irq(dev);
2784 }
2785 ret = 0;
2786 } else {
2787 ret = -EINVAL;
2788 }
2789
2790 return ret;
2791 }
2792
2793 static int nv_set_tso(struct net_device *dev, u32 value)
2794 {
2795 struct fe_priv *np = netdev_priv(dev);
2796
2797 if ((np->driver_data & DEV_HAS_CHECKSUM))
2798 return ethtool_op_set_tso(dev, value);
2799 else
2800 return -EOPNOTSUPP;
2801 }
2802
2803 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
2804 {
2805 struct fe_priv *np = netdev_priv(dev);
2806
2807 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
2808 ring->rx_mini_max_pending = 0;
2809 ring->rx_jumbo_max_pending = 0;
2810 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
2811
2812 ring->rx_pending = np->rx_ring_size;
2813 ring->rx_mini_pending = 0;
2814 ring->rx_jumbo_pending = 0;
2815 ring->tx_pending = np->tx_ring_size;
2816 }
2817
2818 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
2819 {
2820 struct fe_priv *np = netdev_priv(dev);
2821 u8 __iomem *base = get_hwbase(dev);
2822 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
2823 dma_addr_t ring_addr;
2824
2825 if (ring->rx_pending < RX_RING_MIN ||
2826 ring->tx_pending < TX_RING_MIN ||
2827 ring->rx_mini_pending != 0 ||
2828 ring->rx_jumbo_pending != 0 ||
2829 (np->desc_ver == DESC_VER_1 &&
2830 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
2831 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
2832 (np->desc_ver != DESC_VER_1 &&
2833 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
2834 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
2835 return -EINVAL;
2836 }
2837
2838 /* allocate new rings */
2839 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2840 rxtx_ring = pci_alloc_consistent(np->pci_dev,
2841 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
2842 &ring_addr);
2843 } else {
2844 rxtx_ring = pci_alloc_consistent(np->pci_dev,
2845 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
2846 &ring_addr);
2847 }
2848 rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
2849 rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
2850 tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
2851 tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
2852 tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
2853 if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
2854 /* fall back to old rings */
2855 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2856 if(rxtx_ring)
2857 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
2858 rxtx_ring, ring_addr);
2859 } else {
2860 if (rxtx_ring)
2861 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
2862 rxtx_ring, ring_addr);
2863 }
2864 if (rx_skbuff)
2865 kfree(rx_skbuff);
2866 if (rx_dma)
2867 kfree(rx_dma);
2868 if (tx_skbuff)
2869 kfree(tx_skbuff);
2870 if (tx_dma)
2871 kfree(tx_dma);
2872 if (tx_dma_len)
2873 kfree(tx_dma_len);
2874 goto exit;
2875 }
2876
2877 if (netif_running(dev)) {
2878 nv_disable_irq(dev);
2879 spin_lock_bh(&dev->xmit_lock);
2880 spin_lock(&np->lock);
2881 /* stop engines */
2882 nv_stop_rx(dev);
2883 nv_stop_tx(dev);
2884 nv_txrx_reset(dev);
2885 /* drain queues */
2886 nv_drain_rx(dev);
2887 nv_drain_tx(dev);
2888 /* delete queues */
2889 free_rings(dev);
2890 }
2891
2892 /* set new values */
2893 np->rx_ring_size = ring->rx_pending;
2894 np->tx_ring_size = ring->tx_pending;
2895 np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
2896 np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
2897 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2898 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
2899 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
2900 } else {
2901 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
2902 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
2903 }
2904 np->rx_skbuff = (struct sk_buff**)rx_skbuff;
2905 np->rx_dma = (dma_addr_t*)rx_dma;
2906 np->tx_skbuff = (struct sk_buff**)tx_skbuff;
2907 np->tx_dma = (dma_addr_t*)tx_dma;
2908 np->tx_dma_len = (unsigned int*)tx_dma_len;
2909 np->ring_addr = ring_addr;
2910
2911 memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
2912 memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
2913 memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
2914 memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
2915 memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
2916
2917 if (netif_running(dev)) {
2918 /* reinit driver view of the queues */
2919 set_bufsize(dev);
2920 if (nv_init_ring(dev)) {
2921 if (!np->in_shutdown)
2922 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2923 }
2924
2925 /* reinit nic view of the queues */
2926 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2927 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2928 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2929 base + NvRegRingSizes);
2930 pci_push(base);
2931 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2932 pci_push(base);
2933
2934 /* restart engines */
2935 nv_start_rx(dev);
2936 nv_start_tx(dev);
2937 spin_unlock(&np->lock);
2938 spin_unlock_bh(&dev->xmit_lock);
2939 nv_enable_irq(dev);
2940 }
2941 return 0;
2942 exit:
2943 return -ENOMEM;
2944 }
2945
2946 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
2947 {
2948 struct fe_priv *np = netdev_priv(dev);
2949
2950 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
2951 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
2952 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
2953 }
2954
2955 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
2956 {
2957 struct fe_priv *np = netdev_priv(dev);
2958 int adv, bmcr;
2959
2960 if ((!np->autoneg && np->duplex == 0) ||
2961 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
2962 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
2963 dev->name);
2964 return -EINVAL;
2965 }
2966 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
2967 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
2968 return -EINVAL;
2969 }
2970
2971 netif_carrier_off(dev);
2972 if (netif_running(dev)) {
2973 nv_disable_irq(dev);
2974 spin_lock_bh(&dev->xmit_lock);
2975 spin_lock(&np->lock);
2976 /* stop engines */
2977 nv_stop_rx(dev);
2978 nv_stop_tx(dev);
2979 spin_unlock(&np->lock);
2980 spin_unlock_bh(&dev->xmit_lock);
2981 }
2982
2983 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
2984 if (pause->rx_pause)
2985 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
2986 if (pause->tx_pause)
2987 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
2988
2989 if (np->autoneg && pause->autoneg) {
2990 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
2991
2992 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2993 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2994 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
2995 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2996 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2997 adv |= ADVERTISE_PAUSE_ASYM;
2998 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2999
3000 if (netif_running(dev))
3001 printk(KERN_INFO "%s: link down.\n", dev->name);
3002 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3003 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3004 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3005 } else {
3006 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3007 if (pause->rx_pause)
3008 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3009 if (pause->tx_pause)
3010 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3011
3012 if (!netif_running(dev))
3013 nv_update_linkspeed(dev);
3014 else
3015 nv_update_pause(dev, np->pause_flags);
3016 }
3017
3018 if (netif_running(dev)) {
3019 nv_start_rx(dev);
3020 nv_start_tx(dev);
3021 nv_enable_irq(dev);
3022 }
3023 return 0;
3024 }
3025
3026 static u32 nv_get_rx_csum(struct net_device *dev)
3027 {
3028 struct fe_priv *np = netdev_priv(dev);
3029 return (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) != 0;
3030 }
3031
3032 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3033 {
3034 struct fe_priv *np = netdev_priv(dev);
3035 u8 __iomem *base = get_hwbase(dev);
3036 int retcode = 0;
3037
3038 if (np->driver_data & DEV_HAS_CHECKSUM) {
3039
3040 if (((np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && data) ||
3041 (!(np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && !data)) {
3042 /* already set or unset */
3043 return 0;
3044 }
3045
3046 if (data) {
3047 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3048 } else if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) {
3049 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3050 } else {
3051 printk(KERN_INFO "Can not disable rx checksum if vlan is enabled\n");
3052 return -EINVAL;
3053 }
3054
3055 if (netif_running(dev)) {
3056 spin_lock_irq(&np->lock);
3057 writel(np->txrxctl_bits, base + NvRegTxRxControl);
3058 spin_unlock_irq(&np->lock);
3059 }
3060 } else {
3061 return -EINVAL;
3062 }
3063
3064 return retcode;
3065 }
3066
3067 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3068 {
3069 struct fe_priv *np = netdev_priv(dev);
3070
3071 if (np->driver_data & DEV_HAS_CHECKSUM)
3072 return ethtool_op_set_tx_hw_csum(dev, data);
3073 else
3074 return -EOPNOTSUPP;
3075 }
3076
3077 static int nv_set_sg(struct net_device *dev, u32 data)
3078 {
3079 struct fe_priv *np = netdev_priv(dev);
3080
3081 if (np->driver_data & DEV_HAS_CHECKSUM)
3082 return ethtool_op_set_sg(dev, data);
3083 else
3084 return -EOPNOTSUPP;
3085 }
3086
3087 static struct ethtool_ops ops = {
3088 .get_drvinfo = nv_get_drvinfo,
3089 .get_link = ethtool_op_get_link,
3090 .get_wol = nv_get_wol,
3091 .set_wol = nv_set_wol,
3092 .get_settings = nv_get_settings,
3093 .set_settings = nv_set_settings,
3094 .get_regs_len = nv_get_regs_len,
3095 .get_regs = nv_get_regs,
3096 .nway_reset = nv_nway_reset,
3097 .get_perm_addr = ethtool_op_get_perm_addr,
3098 .get_tso = ethtool_op_get_tso,
3099 .set_tso = nv_set_tso,
3100 .get_ringparam = nv_get_ringparam,
3101 .set_ringparam = nv_set_ringparam,
3102 .get_pauseparam = nv_get_pauseparam,
3103 .set_pauseparam = nv_set_pauseparam,
3104 .get_rx_csum = nv_get_rx_csum,
3105 .set_rx_csum = nv_set_rx_csum,
3106 .get_tx_csum = ethtool_op_get_tx_csum,
3107 .set_tx_csum = nv_set_tx_csum,
3108 .get_sg = ethtool_op_get_sg,
3109 .set_sg = nv_set_sg,
3110 };
3111
3112 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
3113 {
3114 struct fe_priv *np = get_nvpriv(dev);
3115
3116 spin_lock_irq(&np->lock);
3117
3118 /* save vlan group */
3119 np->vlangrp = grp;
3120
3121 if (grp) {
3122 /* enable vlan on MAC */
3123 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
3124 } else {
3125 /* disable vlan on MAC */
3126 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
3127 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
3128 }
3129
3130 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3131
3132 spin_unlock_irq(&np->lock);
3133 };
3134
3135 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
3136 {
3137 /* nothing to do */
3138 };
3139
3140 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3141 {
3142 u8 __iomem *base = get_hwbase(dev);
3143 int i;
3144 u32 msixmap = 0;
3145
3146 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3147 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3148 * the remaining 8 interrupts.
3149 */
3150 for (i = 0; i < 8; i++) {
3151 if ((irqmask >> i) & 0x1) {
3152 msixmap |= vector << (i << 2);
3153 }
3154 }
3155 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3156
3157 msixmap = 0;
3158 for (i = 0; i < 8; i++) {
3159 if ((irqmask >> (i + 8)) & 0x1) {
3160 msixmap |= vector << (i << 2);
3161 }
3162 }
3163 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3164 }
3165
3166 static int nv_request_irq(struct net_device *dev)
3167 {
3168 struct fe_priv *np = get_nvpriv(dev);
3169 u8 __iomem *base = get_hwbase(dev);
3170 int ret = 1;
3171 int i;
3172
3173 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3174 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3175 np->msi_x_entry[i].entry = i;
3176 }
3177 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3178 np->msi_flags |= NV_MSI_X_ENABLED;
3179 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
3180 /* Request irq for rx handling */
3181 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, SA_SHIRQ, dev->name, dev) != 0) {
3182 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3183 pci_disable_msix(np->pci_dev);
3184 np->msi_flags &= ~NV_MSI_X_ENABLED;
3185 goto out_err;
3186 }
3187 /* Request irq for tx handling */
3188 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, SA_SHIRQ, dev->name, dev) != 0) {
3189 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3190 pci_disable_msix(np->pci_dev);
3191 np->msi_flags &= ~NV_MSI_X_ENABLED;
3192 goto out_free_rx;
3193 }
3194 /* Request irq for link and timer handling */
3195 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, SA_SHIRQ, dev->name, dev) != 0) {
3196 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3197 pci_disable_msix(np->pci_dev);
3198 np->msi_flags &= ~NV_MSI_X_ENABLED;
3199 goto out_free_tx;
3200 }
3201 /* map interrupts to their respective vector */
3202 writel(0, base + NvRegMSIXMap0);
3203 writel(0, base + NvRegMSIXMap1);
3204 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3205 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3206 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3207 } else {
3208 /* Request irq for all interrupts */
3209 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) {
3210 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3211 pci_disable_msix(np->pci_dev);
3212 np->msi_flags &= ~NV_MSI_X_ENABLED;
3213 goto out_err;
3214 }
3215
3216 /* map interrupts to vector 0 */
3217 writel(0, base + NvRegMSIXMap0);
3218 writel(0, base + NvRegMSIXMap1);
3219 }
3220 }
3221 }
3222 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3223 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3224 np->msi_flags |= NV_MSI_ENABLED;
3225 if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) {
3226 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3227 pci_disable_msi(np->pci_dev);
3228 np->msi_flags &= ~NV_MSI_ENABLED;
3229 goto out_err;
3230 }
3231
3232 /* map interrupts to vector 0 */
3233 writel(0, base + NvRegMSIMap0);
3234 writel(0, base + NvRegMSIMap1);
3235 /* enable msi vector 0 */
3236 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3237 }
3238 }
3239 if (ret != 0) {
3240 if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0)
3241 goto out_err;
3242 }
3243
3244 return 0;
3245 out_free_tx:
3246 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3247 out_free_rx:
3248 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3249 out_err:
3250 return 1;
3251 }
3252
3253 static void nv_free_irq(struct net_device *dev)
3254 {
3255 struct fe_priv *np = get_nvpriv(dev);
3256 int i;
3257
3258 if (np->msi_flags & NV_MSI_X_ENABLED) {
3259 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3260 free_irq(np->msi_x_entry[i].vector, dev);
3261 }
3262 pci_disable_msix(np->pci_dev);
3263 np->msi_flags &= ~NV_MSI_X_ENABLED;
3264 } else {
3265 free_irq(np->pci_dev->irq, dev);
3266 if (np->msi_flags & NV_MSI_ENABLED) {
3267 pci_disable_msi(np->pci_dev);
3268 np->msi_flags &= ~NV_MSI_ENABLED;
3269 }
3270 }
3271 }
3272
3273 static int nv_open(struct net_device *dev)
3274 {
3275 struct fe_priv *np = netdev_priv(dev);
3276 u8 __iomem *base = get_hwbase(dev);
3277 int ret = 1;
3278 int oom, i;
3279
3280 dprintk(KERN_DEBUG "nv_open: begin\n");
3281
3282 /* 1) erase previous misconfiguration */
3283 if (np->driver_data & DEV_HAS_POWER_CNTRL)
3284 nv_mac_reset(dev);
3285 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
3286 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
3287 writel(0, base + NvRegMulticastAddrB);
3288 writel(0, base + NvRegMulticastMaskA);
3289 writel(0, base + NvRegMulticastMaskB);
3290 writel(0, base + NvRegPacketFilterFlags);
3291
3292 writel(0, base + NvRegTransmitterControl);
3293 writel(0, base + NvRegReceiverControl);
3294
3295 writel(0, base + NvRegAdapterControl);
3296
3297 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
3298 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3299
3300 /* 2) initialize descriptor rings */
3301 set_bufsize(dev);
3302 oom = nv_init_ring(dev);
3303
3304 writel(0, base + NvRegLinkSpeed);
3305 writel(0, base + NvRegUnknownTransmitterReg);
3306 nv_txrx_reset(dev);
3307 writel(0, base + NvRegUnknownSetupReg6);
3308
3309 np->in_shutdown = 0;
3310
3311 /* 3) set mac address */
3312 nv_copy_mac_to_hw(dev);
3313
3314 /* 4) give hw rings */
3315 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3316 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3317 base + NvRegRingSizes);
3318
3319 /* 5) continue setup */
3320 writel(np->linkspeed, base + NvRegLinkSpeed);
3321 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
3322 writel(np->txrxctl_bits, base + NvRegTxRxControl);
3323 writel(np->vlanctl_bits, base + NvRegVlanControl);
3324 pci_push(base);
3325 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
3326 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
3327 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
3328 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
3329
3330 writel(0, base + NvRegUnknownSetupReg4);
3331 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3332 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3333
3334 /* 6) continue setup */
3335 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
3336 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
3337 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
3338 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3339
3340 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
3341 get_random_bytes(&i, sizeof(i));
3342 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
3343 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
3344 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
3345 if (poll_interval == -1) {
3346 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
3347 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
3348 else
3349 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3350 }
3351 else
3352 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
3353 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3354 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
3355 base + NvRegAdapterControl);
3356 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
3357 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
3358 if (np->wolenabled)
3359 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
3360
3361 i = readl(base + NvRegPowerState);
3362 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
3363 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
3364
3365 pci_push(base);
3366 udelay(10);
3367 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
3368
3369 nv_disable_hw_interrupts(dev, np->irqmask);
3370 pci_push(base);
3371 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3372 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3373 pci_push(base);
3374
3375 if (nv_request_irq(dev)) {
3376 goto out_drain;
3377 }
3378
3379 /* ask for interrupts */
3380 nv_enable_hw_interrupts(dev, np->irqmask);
3381
3382 spin_lock_irq(&np->lock);
3383 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
3384 writel(0, base + NvRegMulticastAddrB);
3385 writel(0, base + NvRegMulticastMaskA);
3386 writel(0, base + NvRegMulticastMaskB);
3387 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
3388 /* One manual link speed update: Interrupts are enabled, future link
3389 * speed changes cause interrupts and are handled by nv_link_irq().
3390 */
3391 {
3392 u32 miistat;
3393 miistat = readl(base + NvRegMIIStatus);
3394 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
3395 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
3396 }
3397 /* set linkspeed to invalid value, thus force nv_update_linkspeed
3398 * to init hw */
3399 np->linkspeed = 0;
3400 ret = nv_update_linkspeed(dev);
3401 nv_start_rx(dev);
3402 nv_start_tx(dev);
3403 netif_start_queue(dev);
3404 if (ret) {
3405 netif_carrier_on(dev);
3406 } else {
3407 printk("%s: no link during initialization.\n", dev->name);
3408 netif_carrier_off(dev);
3409 }
3410 if (oom)
3411 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3412 spin_unlock_irq(&np->lock);
3413
3414 return 0;
3415 out_drain:
3416 drain_ring(dev);
3417 return ret;
3418 }
3419
3420 static int nv_close(struct net_device *dev)
3421 {
3422 struct fe_priv *np = netdev_priv(dev);
3423 u8 __iomem *base;
3424
3425 spin_lock_irq(&np->lock);
3426 np->in_shutdown = 1;
3427 spin_unlock_irq(&np->lock);
3428 synchronize_irq(dev->irq);
3429
3430 del_timer_sync(&np->oom_kick);
3431 del_timer_sync(&np->nic_poll);
3432
3433 netif_stop_queue(dev);
3434 spin_lock_irq(&np->lock);
3435 nv_stop_tx(dev);
3436 nv_stop_rx(dev);
3437 nv_txrx_reset(dev);
3438
3439 /* disable interrupts on the nic or we will lock up */
3440 base = get_hwbase(dev);
3441 nv_disable_hw_interrupts(dev, np->irqmask);
3442 pci_push(base);
3443 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
3444
3445 spin_unlock_irq(&np->lock);
3446
3447 nv_free_irq(dev);
3448
3449 drain_ring(dev);
3450
3451 if (np->wolenabled)
3452 nv_start_rx(dev);
3453
3454 /* special op: write back the misordered MAC address - otherwise
3455 * the next nv_probe would see a wrong address.
3456 */
3457 writel(np->orig_mac[0], base + NvRegMacAddrA);
3458 writel(np->orig_mac[1], base + NvRegMacAddrB);
3459
3460 /* FIXME: power down nic */
3461
3462 return 0;
3463 }
3464
3465 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
3466 {
3467 struct net_device *dev;
3468 struct fe_priv *np;
3469 unsigned long addr;
3470 u8 __iomem *base;
3471 int err, i;
3472 u32 powerstate;
3473
3474 dev = alloc_etherdev(sizeof(struct fe_priv));
3475 err = -ENOMEM;
3476 if (!dev)
3477 goto out;
3478
3479 np = netdev_priv(dev);
3480 np->pci_dev = pci_dev;
3481 spin_lock_init(&np->lock);
3482 SET_MODULE_OWNER(dev);
3483 SET_NETDEV_DEV(dev, &pci_dev->dev);
3484
3485 init_timer(&np->oom_kick);
3486 np->oom_kick.data = (unsigned long) dev;
3487 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
3488 init_timer(&np->nic_poll);
3489 np->nic_poll.data = (unsigned long) dev;
3490 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
3491
3492 err = pci_enable_device(pci_dev);
3493 if (err) {
3494 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
3495 err, pci_name(pci_dev));
3496 goto out_free;
3497 }
3498
3499 pci_set_master(pci_dev);
3500
3501 err = pci_request_regions(pci_dev, DRV_NAME);
3502 if (err < 0)
3503 goto out_disable;
3504
3505 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL))
3506 np->register_size = NV_PCI_REGSZ_VER2;
3507 else
3508 np->register_size = NV_PCI_REGSZ_VER1;
3509
3510 err = -EINVAL;
3511 addr = 0;
3512 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
3513 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
3514 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
3515 pci_resource_len(pci_dev, i),
3516 pci_resource_flags(pci_dev, i));
3517 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
3518 pci_resource_len(pci_dev, i) >= np->register_size) {
3519 addr = pci_resource_start(pci_dev, i);
3520 break;
3521 }
3522 }
3523 if (i == DEVICE_COUNT_RESOURCE) {
3524 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
3525 pci_name(pci_dev));
3526 goto out_relreg;
3527 }
3528
3529 /* copy of driver data */
3530 np->driver_data = id->driver_data;
3531
3532 /* handle different descriptor versions */
3533 if (id->driver_data & DEV_HAS_HIGH_DMA) {
3534 /* packet format 3: supports 40-bit addressing */
3535 np->desc_ver = DESC_VER_3;
3536 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
3537 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
3538 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
3539 pci_name(pci_dev));
3540 } else {
3541 dev->features |= NETIF_F_HIGHDMA;
3542 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
3543 }
3544 if (pci_set_consistent_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
3545 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed for device %s.\n",
3546 pci_name(pci_dev));
3547 }
3548 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
3549 /* packet format 2: supports jumbo frames */
3550 np->desc_ver = DESC_VER_2;
3551 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
3552 } else {
3553 /* original packet format */
3554 np->desc_ver = DESC_VER_1;
3555 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
3556 }
3557
3558 np->pkt_limit = NV_PKTLIMIT_1;
3559 if (id->driver_data & DEV_HAS_LARGEDESC)
3560 np->pkt_limit = NV_PKTLIMIT_2;
3561
3562 if (id->driver_data & DEV_HAS_CHECKSUM) {
3563 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3564 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
3565 #ifdef NETIF_F_TSO
3566 dev->features |= NETIF_F_TSO;
3567 #endif
3568 }
3569
3570 np->vlanctl_bits = 0;
3571 if (id->driver_data & DEV_HAS_VLAN) {
3572 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
3573 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
3574 dev->vlan_rx_register = nv_vlan_rx_register;
3575 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
3576 }
3577
3578 np->msi_flags = 0;
3579 if ((id->driver_data & DEV_HAS_MSI) && !disable_msi) {
3580 np->msi_flags |= NV_MSI_CAPABLE;
3581 }
3582 if ((id->driver_data & DEV_HAS_MSI_X) && !disable_msix) {
3583 np->msi_flags |= NV_MSI_X_CAPABLE;
3584 }
3585
3586 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
3587 if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
3588 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
3589 }
3590
3591
3592 err = -ENOMEM;
3593 np->base = ioremap(addr, np->register_size);
3594 if (!np->base)
3595 goto out_relreg;
3596 dev->base_addr = (unsigned long)np->base;
3597
3598 dev->irq = pci_dev->irq;
3599
3600 np->rx_ring_size = RX_RING_DEFAULT;
3601 np->tx_ring_size = TX_RING_DEFAULT;
3602 np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
3603 np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
3604
3605 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3606 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
3607 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
3608 &np->ring_addr);
3609 if (!np->rx_ring.orig)
3610 goto out_unmap;
3611 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3612 } else {
3613 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
3614 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
3615 &np->ring_addr);
3616 if (!np->rx_ring.ex)
3617 goto out_unmap;
3618 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3619 }
3620 np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
3621 np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
3622 np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
3623 np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
3624 np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
3625 if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
3626 goto out_freering;
3627 memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
3628 memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
3629 memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
3630 memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3631 memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3632
3633 dev->open = nv_open;
3634 dev->stop = nv_close;
3635 dev->hard_start_xmit = nv_start_xmit;
3636 dev->get_stats = nv_get_stats;
3637 dev->change_mtu = nv_change_mtu;
3638 dev->set_mac_address = nv_set_mac_address;
3639 dev->set_multicast_list = nv_set_multicast;
3640 #ifdef CONFIG_NET_POLL_CONTROLLER
3641 dev->poll_controller = nv_poll_controller;
3642 #endif
3643 SET_ETHTOOL_OPS(dev, &ops);
3644 dev->tx_timeout = nv_tx_timeout;
3645 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
3646
3647 pci_set_drvdata(pci_dev, dev);
3648
3649 /* read the mac address */
3650 base = get_hwbase(dev);
3651 np->orig_mac[0] = readl(base + NvRegMacAddrA);
3652 np->orig_mac[1] = readl(base + NvRegMacAddrB);
3653
3654 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
3655 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
3656 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
3657 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
3658 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
3659 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
3660 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3661
3662 if (!is_valid_ether_addr(dev->perm_addr)) {
3663 /*
3664 * Bad mac address. At least one bios sets the mac address
3665 * to 01:23:45:67:89:ab
3666 */
3667 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
3668 pci_name(pci_dev),
3669 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3670 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3671 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
3672 dev->dev_addr[0] = 0x00;
3673 dev->dev_addr[1] = 0x00;
3674 dev->dev_addr[2] = 0x6c;
3675 get_random_bytes(&dev->dev_addr[3], 3);
3676 }
3677
3678 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
3679 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3680 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3681
3682 /* disable WOL */
3683 writel(0, base + NvRegWakeUpFlags);
3684 np->wolenabled = 0;
3685
3686 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
3687 u8 revision_id;
3688 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
3689
3690 /* take phy and nic out of low power mode */
3691 powerstate = readl(base + NvRegPowerState2);
3692 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
3693 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
3694 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
3695 revision_id >= 0xA3)
3696 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
3697 writel(powerstate, base + NvRegPowerState2);
3698 }
3699
3700 if (np->desc_ver == DESC_VER_1) {
3701 np->tx_flags = NV_TX_VALID;
3702 } else {
3703 np->tx_flags = NV_TX2_VALID;
3704 }
3705 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
3706 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3707 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
3708 np->msi_flags |= 0x0003;
3709 } else {
3710 np->irqmask = NVREG_IRQMASK_CPU;
3711 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
3712 np->msi_flags |= 0x0001;
3713 }
3714
3715 if (id->driver_data & DEV_NEED_TIMERIRQ)
3716 np->irqmask |= NVREG_IRQ_TIMER;
3717 if (id->driver_data & DEV_NEED_LINKTIMER) {
3718 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
3719 np->need_linktimer = 1;
3720 np->link_timeout = jiffies + LINK_TIMEOUT;
3721 } else {
3722 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
3723 np->need_linktimer = 0;
3724 }
3725
3726 /* find a suitable phy */
3727 for (i = 1; i <= 32; i++) {
3728 int id1, id2;
3729 int phyaddr = i & 0x1F;
3730
3731 spin_lock_irq(&np->lock);
3732 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
3733 spin_unlock_irq(&np->lock);
3734 if (id1 < 0 || id1 == 0xffff)
3735 continue;
3736 spin_lock_irq(&np->lock);
3737 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
3738 spin_unlock_irq(&np->lock);
3739 if (id2 < 0 || id2 == 0xffff)
3740 continue;
3741
3742 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
3743 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
3744 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
3745 pci_name(pci_dev), id1, id2, phyaddr);
3746 np->phyaddr = phyaddr;
3747 np->phy_oui = id1 | id2;
3748 break;
3749 }
3750 if (i == 33) {
3751 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
3752 pci_name(pci_dev));
3753 goto out_error;
3754 }
3755
3756 /* reset it */
3757 phy_init(dev);
3758
3759 /* set default link speed settings */
3760 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3761 np->duplex = 0;
3762 np->autoneg = 1;
3763
3764 err = register_netdev(dev);
3765 if (err) {
3766 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
3767 goto out_error;
3768 }
3769 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
3770 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
3771 pci_name(pci_dev));
3772
3773 return 0;
3774
3775 out_error:
3776 pci_set_drvdata(pci_dev, NULL);
3777 out_freering:
3778 free_rings(dev);
3779 out_unmap:
3780 iounmap(get_hwbase(dev));
3781 out_relreg:
3782 pci_release_regions(pci_dev);
3783 out_disable:
3784 pci_disable_device(pci_dev);
3785 out_free:
3786 free_netdev(dev);
3787 out:
3788 return err;
3789 }
3790
3791 static void __devexit nv_remove(struct pci_dev *pci_dev)
3792 {
3793 struct net_device *dev = pci_get_drvdata(pci_dev);
3794
3795 unregister_netdev(dev);
3796
3797 /* free all structures */
3798 free_rings(dev);
3799 iounmap(get_hwbase(dev));
3800 pci_release_regions(pci_dev);
3801 pci_disable_device(pci_dev);
3802 free_netdev(dev);
3803 pci_set_drvdata(pci_dev, NULL);
3804 }
3805
3806 static struct pci_device_id pci_tbl[] = {
3807 { /* nForce Ethernet Controller */
3808 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
3809 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
3810 },
3811 { /* nForce2 Ethernet Controller */
3812 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
3813 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
3814 },
3815 { /* nForce3 Ethernet Controller */
3816 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
3817 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
3818 },
3819 { /* nForce3 Ethernet Controller */
3820 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
3821 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
3822 },
3823 { /* nForce3 Ethernet Controller */
3824 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
3825 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
3826 },
3827 { /* nForce3 Ethernet Controller */
3828 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
3829 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
3830 },
3831 { /* nForce3 Ethernet Controller */
3832 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
3833 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
3834 },
3835 { /* CK804 Ethernet Controller */
3836 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
3837 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
3838 },
3839 { /* CK804 Ethernet Controller */
3840 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
3841 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
3842 },
3843 { /* MCP04 Ethernet Controller */
3844 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
3845 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
3846 },
3847 { /* MCP04 Ethernet Controller */
3848 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
3849 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
3850 },
3851 { /* MCP51 Ethernet Controller */
3852 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
3853 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
3854 },
3855 { /* MCP51 Ethernet Controller */
3856 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
3857 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
3858 },
3859 { /* MCP55 Ethernet Controller */
3860 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
3861 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX,
3862 },
3863 { /* MCP55 Ethernet Controller */
3864 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
3865 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX,
3866 },
3867 {0,},
3868 };
3869
3870 static struct pci_driver driver = {
3871 .name = "forcedeth",
3872 .id_table = pci_tbl,
3873 .probe = nv_probe,
3874 .remove = __devexit_p(nv_remove),
3875 };
3876
3877
3878 static int __init init_nic(void)
3879 {
3880 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
3881 return pci_module_init(&driver);
3882 }
3883
3884 static void __exit exit_nic(void)
3885 {
3886 pci_unregister_driver(&driver);
3887 }
3888
3889 module_param(max_interrupt_work, int, 0);
3890 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
3891 module_param(optimization_mode, int, 0);
3892 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
3893 module_param(poll_interval, int, 0);
3894 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
3895 module_param(disable_msi, int, 0);
3896 MODULE_PARM_DESC(disable_msi, "Disable MSI interrupts by setting to 1.");
3897 module_param(disable_msix, int, 0);
3898 MODULE_PARM_DESC(disable_msix, "Disable MSIX interrupts by setting to 1.");
3899
3900 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
3901 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
3902 MODULE_LICENSE("GPL");
3903
3904 MODULE_DEVICE_TABLE(pci, pci_tbl);
3905
3906 module_init(init_nic);
3907 module_exit(exit_nic);