drivers/net/ethernet/stmicro/stmmac/mmc_core.c

   1 /*******************************************************************************
   2   DWMAC Management Counters
   3
   4   Copyright (C) 2011  STMicroelectronics Ltd
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  23 *******************************************************************************/
  24
  25 #include <linux/io.h>
  26 #include "mmc.h"
  27
  28 /* MAC Management Counters register offset */
  29
  30 #define MMC_CNTRL               0x00000100      /* MMC Control */
  31 #define MMC_RX_INTR             0x00000104      /* MMC RX Interrupt */
  32 #define MMC_TX_INTR             0x00000108      /* MMC TX Interrupt */
  33 #define MMC_RX_INTR_MASK        0x0000010c      /* MMC Interrupt Mask */
  34 #define MMC_TX_INTR_MASK        0x00000110      /* MMC Interrupt Mask */
  35 #define MMC_DEFAUL_MASK         0xffffffff
  36
  37 /* MMC TX counter registers */
  38
  39 /* Note:
  40  * _GB register stands for good and bad frames
  41  * _G is for good only.
  42  */
  43 #define MMC_TX_OCTETCOUNT_GB            0x00000114
  44 #define MMC_TX_FRAMECOUNT_GB            0x00000118
  45 #define MMC_TX_BROADCASTFRAME_G         0x0000011c
  46 #define MMC_TX_MULTICASTFRAME_G         0x00000120
  47 #define MMC_TX_64_OCTETS_GB             0x00000124
  48 #define MMC_TX_65_TO_127_OCTETS_GB      0x00000128
  49 #define MMC_TX_128_TO_255_OCTETS_GB     0x0000012c
  50 #define MMC_TX_256_TO_511_OCTETS_GB     0x00000130
  51 #define MMC_TX_512_TO_1023_OCTETS_GB    0x00000134
  52 #define MMC_TX_1024_TO_MAX_OCTETS_GB    0x00000138
  53 #define MMC_TX_UNICAST_GB               0x0000013c
  54 #define MMC_TX_MULTICAST_GB             0x00000140
  55 #define MMC_TX_BROADCAST_GB             0x00000144
  56 #define MMC_TX_UNDERFLOW_ERROR          0x00000148
  57 #define MMC_TX_SINGLECOL_G              0x0000014c
  58 #define MMC_TX_MULTICOL_G               0x00000150
  59 #define MMC_TX_DEFERRED                 0x00000154
  60 #define MMC_TX_LATECOL                  0x00000158
  61 #define MMC_TX_EXESSCOL                 0x0000015c
  62 #define MMC_TX_CARRIER_ERROR            0x00000160
  63 #define MMC_TX_OCTETCOUNT_G             0x00000164
  64 #define MMC_TX_FRAMECOUNT_G             0x00000168
  65 #define MMC_TX_EXCESSDEF                0x0000016c
  66 #define MMC_TX_PAUSE_FRAME              0x00000170
  67 #define MMC_TX_VLAN_FRAME_G             0x00000174
  68
  69 /* MMC RX counter registers */
  70 #define MMC_RX_FRAMECOUNT_GB            0x00000180
  71 #define MMC_RX_OCTETCOUNT_GB            0x00000184
  72 #define MMC_RX_OCTETCOUNT_G             0x00000188
  73 #define MMC_RX_BROADCASTFRAME_G         0x0000018c
  74 #define MMC_RX_MULTICASTFRAME_G         0x00000190
  75 #define MMC_RX_CRC_ERRROR               0x00000194
  76 #define MMC_RX_ALIGN_ERROR              0x00000198
  77 #define MMC_RX_RUN_ERROR                0x0000019C
  78 #define MMC_RX_JABBER_ERROR             0x000001A0
  79 #define MMC_RX_UNDERSIZE_G              0x000001A4
  80 #define MMC_RX_OVERSIZE_G               0x000001A8
  81 #define MMC_RX_64_OCTETS_GB             0x000001AC
  82 #define MMC_RX_65_TO_127_OCTETS_GB      0x000001b0
  83 #define MMC_RX_128_TO_255_OCTETS_GB     0x000001b4
  84 #define MMC_RX_256_TO_511_OCTETS_GB     0x000001b8
  85 #define MMC_RX_512_TO_1023_OCTETS_GB    0x000001bc
  86 #define MMC_RX_1024_TO_MAX_OCTETS_GB    0x000001c0
  87 #define MMC_RX_UNICAST_G                0x000001c4
  88 #define MMC_RX_LENGTH_ERROR             0x000001c8
  89 #define MMC_RX_AUTOFRANGETYPE           0x000001cc
  90 #define MMC_RX_PAUSE_FRAMES             0x000001d0
  91 #define MMC_RX_FIFO_OVERFLOW            0x000001d4
  92 #define MMC_RX_VLAN_FRAMES_GB           0x000001d8
  93 #define MMC_RX_WATCHDOG_ERROR           0x000001dc
  94 /* IPC*/
  95 #define MMC_RX_IPC_INTR_MASK            0x00000200
  96 #define MMC_RX_IPC_INTR                 0x00000208
  97 /* IPv4*/
  98 #define MMC_RX_IPV4_GD                  0x00000210
  99 #define MMC_RX_IPV4_HDERR               0x00000214
 100 #define MMC_RX_IPV4_NOPAY               0x00000218
 101 #define MMC_RX_IPV4_FRAG                0x0000021C
 102 #define MMC_RX_IPV4_UDSBL               0x00000220
 103
 104 #define MMC_RX_IPV4_GD_OCTETS           0x00000250
 105 #define MMC_RX_IPV4_HDERR_OCTETS        0x00000254
 106 #define MMC_RX_IPV4_NOPAY_OCTETS        0x00000258
 107 #define MMC_RX_IPV4_FRAG_OCTETS         0x0000025c
 108 #define MMC_RX_IPV4_UDSBL_OCTETS        0x00000260
 109
 110 /* IPV6*/
 111 #define MMC_RX_IPV6_GD_OCTETS           0x00000264
 112 #define MMC_RX_IPV6_HDERR_OCTETS        0x00000268
 113 #define MMC_RX_IPV6_NOPAY_OCTETS        0x0000026c
 114
 115 #define MMC_RX_IPV6_GD                  0x00000224
 116 #define MMC_RX_IPV6_HDERR               0x00000228
 117 #define MMC_RX_IPV6_NOPAY               0x0000022c
 118
 119 /* Protocols*/
 120 #define MMC_RX_UDP_GD                   0x00000230
 121 #define MMC_RX_UDP_ERR                  0x00000234
 122 #define MMC_RX_TCP_GD                   0x00000238
 123 #define MMC_RX_TCP_ERR                  0x0000023c
 124 #define MMC_RX_ICMP_GD                  0x00000240
 125 #define MMC_RX_ICMP_ERR                 0x00000244
 126
 127 #define MMC_RX_UDP_GD_OCTETS            0x00000270
 128 #define MMC_RX_UDP_ERR_OCTETS           0x00000274
 129 #define MMC_RX_TCP_GD_OCTETS            0x00000278
 130 #define MMC_RX_TCP_ERR_OCTETS           0x0000027c
 131 #define MMC_RX_ICMP_GD_OCTETS           0x00000280
 132 #define MMC_RX_ICMP_ERR_OCTETS          0x00000284
 133
 134 void dwmac_mmc_ctrl(void __iomem *ioaddr, unsigned int mode)
 135 {
 136         u32 value = readl(ioaddr + MMC_CNTRL);
 137
 138         value |= (mode & 0x3F);
 139
 140         writel(value, ioaddr + MMC_CNTRL);
 141
 142         pr_debug("stmmac: MMC ctrl register (offset 0x%x): 0x%08x\n",
 143                  MMC_CNTRL, value);
 144 }
 145
 146 /* To mask all all interrupts.*/
 147 void dwmac_mmc_intr_all_mask(void __iomem *ioaddr)
 148 {
 149         writel(MMC_DEFAUL_MASK, ioaddr + MMC_RX_INTR_MASK);
 150         writel(MMC_DEFAUL_MASK, ioaddr + MMC_TX_INTR_MASK);
 151 }
 152
 153 /* This reads the MAC core counters (if actaully supported).
 154  * by default the MMC core is programmed to reset each
 155  * counter after a read. So all the field of the mmc struct
 156  * have to be incremented.
 157  */
 158 void dwmac_mmc_read(void __iomem *ioaddr, struct stmmac_counters *mmc)
 159 {
 160         mmc->mmc_tx_octetcount_gb += readl(ioaddr + MMC_TX_OCTETCOUNT_GB);
 161         mmc->mmc_tx_framecount_gb += readl(ioaddr + MMC_TX_FRAMECOUNT_GB);
 162         mmc->mmc_tx_broadcastframe_g += readl(ioaddr + MMC_TX_BROADCASTFRAME_G);
 163         mmc->mmc_tx_multicastframe_g += readl(ioaddr + MMC_TX_MULTICASTFRAME_G);
 164         mmc->mmc_tx_64_octets_gb += readl(ioaddr + MMC_TX_64_OCTETS_GB);
 165         mmc->mmc_tx_65_to_127_octets_gb +=
 166             readl(ioaddr + MMC_TX_65_TO_127_OCTETS_GB);
 167         mmc->mmc_tx_128_to_255_octets_gb +=
 168             readl(ioaddr + MMC_TX_128_TO_255_OCTETS_GB);
 169         mmc->mmc_tx_256_to_511_octets_gb +=
 170             readl(ioaddr + MMC_TX_256_TO_511_OCTETS_GB);
 171         mmc->mmc_tx_512_to_1023_octets_gb +=
 172             readl(ioaddr + MMC_TX_512_TO_1023_OCTETS_GB);
 173         mmc->mmc_tx_1024_to_max_octets_gb +=
 174             readl(ioaddr + MMC_TX_1024_TO_MAX_OCTETS_GB);
 175         mmc->mmc_tx_unicast_gb += readl(ioaddr + MMC_TX_UNICAST_GB);
 176         mmc->mmc_tx_multicast_gb += readl(ioaddr + MMC_TX_MULTICAST_GB);
 177         mmc->mmc_tx_broadcast_gb += readl(ioaddr + MMC_TX_BROADCAST_GB);
 178         mmc->mmc_tx_underflow_error += readl(ioaddr + MMC_TX_UNDERFLOW_ERROR);
 179         mmc->mmc_tx_singlecol_g += readl(ioaddr + MMC_TX_SINGLECOL_G);
 180         mmc->mmc_tx_multicol_g += readl(ioaddr + MMC_TX_MULTICOL_G);
 181         mmc->mmc_tx_deferred += readl(ioaddr + MMC_TX_DEFERRED);
 182         mmc->mmc_tx_latecol += readl(ioaddr + MMC_TX_LATECOL);
 183         mmc->mmc_tx_exesscol += readl(ioaddr + MMC_TX_EXESSCOL);
 184         mmc->mmc_tx_carrier_error += readl(ioaddr + MMC_TX_CARRIER_ERROR);
 185         mmc->mmc_tx_octetcount_g += readl(ioaddr + MMC_TX_OCTETCOUNT_G);
 186         mmc->mmc_tx_framecount_g += readl(ioaddr + MMC_TX_FRAMECOUNT_G);
 187         mmc->mmc_tx_excessdef += readl(ioaddr + MMC_TX_EXCESSDEF);
 188         mmc->mmc_tx_pause_frame += readl(ioaddr + MMC_TX_PAUSE_FRAME);
 189         mmc->mmc_tx_vlan_frame_g += readl(ioaddr + MMC_TX_VLAN_FRAME_G);
 190
 191         /* MMC RX counter registers */
 192         mmc->mmc_rx_framecount_gb += readl(ioaddr + MMC_RX_FRAMECOUNT_GB);
 193         mmc->mmc_rx_octetcount_gb += readl(ioaddr + MMC_RX_OCTETCOUNT_GB);
 194         mmc->mmc_rx_octetcount_g += readl(ioaddr + MMC_RX_OCTETCOUNT_G);
 195         mmc->mmc_rx_broadcastframe_g += readl(ioaddr + MMC_RX_BROADCASTFRAME_G);
 196         mmc->mmc_rx_multicastframe_g += readl(ioaddr + MMC_RX_MULTICASTFRAME_G);
 197         mmc->mmc_rx_crc_errror += readl(ioaddr + MMC_RX_CRC_ERRROR);
 198         mmc->mmc_rx_align_error += readl(ioaddr + MMC_RX_ALIGN_ERROR);
 199         mmc->mmc_rx_run_error += readl(ioaddr + MMC_RX_RUN_ERROR);
 200         mmc->mmc_rx_jabber_error += readl(ioaddr + MMC_RX_JABBER_ERROR);
 201         mmc->mmc_rx_undersize_g += readl(ioaddr + MMC_RX_UNDERSIZE_G);
 202         mmc->mmc_rx_oversize_g += readl(ioaddr + MMC_RX_OVERSIZE_G);
 203         mmc->mmc_rx_64_octets_gb += readl(ioaddr + MMC_RX_64_OCTETS_GB);
 204         mmc->mmc_rx_65_to_127_octets_gb +=
 205             readl(ioaddr + MMC_RX_65_TO_127_OCTETS_GB);
 206         mmc->mmc_rx_128_to_255_octets_gb +=
 207             readl(ioaddr + MMC_RX_128_TO_255_OCTETS_GB);
 208         mmc->mmc_rx_256_to_511_octets_gb +=
 209             readl(ioaddr + MMC_RX_256_TO_511_OCTETS_GB);
 210         mmc->mmc_rx_512_to_1023_octets_gb +=
 211             readl(ioaddr + MMC_RX_512_TO_1023_OCTETS_GB);
 212         mmc->mmc_rx_1024_to_max_octets_gb +=
 213             readl(ioaddr + MMC_RX_1024_TO_MAX_OCTETS_GB);
 214         mmc->mmc_rx_unicast_g += readl(ioaddr + MMC_RX_UNICAST_G);
 215         mmc->mmc_rx_length_error += readl(ioaddr + MMC_RX_LENGTH_ERROR);
 216         mmc->mmc_rx_autofrangetype += readl(ioaddr + MMC_RX_AUTOFRANGETYPE);
 217         mmc->mmc_rx_pause_frames += readl(ioaddr + MMC_RX_PAUSE_FRAMES);
 218         mmc->mmc_rx_fifo_overflow += readl(ioaddr + MMC_RX_FIFO_OVERFLOW);
 219         mmc->mmc_rx_vlan_frames_gb += readl(ioaddr + MMC_RX_VLAN_FRAMES_GB);
 220         mmc->mmc_rx_watchdog_error += readl(ioaddr + MMC_RX_WATCHDOG_ERROR);
 221         /* IPC */
 222         mmc->mmc_rx_ipc_intr_mask += readl(ioaddr + MMC_RX_IPC_INTR_MASK);
 223         mmc->mmc_rx_ipc_intr += readl(ioaddr + MMC_RX_IPC_INTR);
 224         /* IPv4 */
 225         mmc->mmc_rx_ipv4_gd += readl(ioaddr + MMC_RX_IPV4_GD);
 226         mmc->mmc_rx_ipv4_hderr += readl(ioaddr + MMC_RX_IPV4_HDERR);
 227         mmc->mmc_rx_ipv4_nopay += readl(ioaddr + MMC_RX_IPV4_NOPAY);
 228         mmc->mmc_rx_ipv4_frag += readl(ioaddr + MMC_RX_IPV4_FRAG);
 229         mmc->mmc_rx_ipv4_udsbl += readl(ioaddr + MMC_RX_IPV4_UDSBL);
 230
 231         mmc->mmc_rx_ipv4_gd_octets += readl(ioaddr + MMC_RX_IPV4_GD_OCTETS);
 232         mmc->mmc_rx_ipv4_hderr_octets +=
 233             readl(ioaddr + MMC_RX_IPV4_HDERR_OCTETS);
 234         mmc->mmc_rx_ipv4_nopay_octets +=
 235             readl(ioaddr + MMC_RX_IPV4_NOPAY_OCTETS);
 236         mmc->mmc_rx_ipv4_frag_octets += readl(ioaddr + MMC_RX_IPV4_FRAG_OCTETS);
 237         mmc->mmc_rx_ipv4_udsbl_octets +=
 238             readl(ioaddr + MMC_RX_IPV4_UDSBL_OCTETS);
 239
 240         /* IPV6 */
 241         mmc->mmc_rx_ipv6_gd_octets += readl(ioaddr + MMC_RX_IPV6_GD_OCTETS);
 242         mmc->mmc_rx_ipv6_hderr_octets +=
 243             readl(ioaddr + MMC_RX_IPV6_HDERR_OCTETS);
 244         mmc->mmc_rx_ipv6_nopay_octets +=
 245             readl(ioaddr + MMC_RX_IPV6_NOPAY_OCTETS);
 246
 247         mmc->mmc_rx_ipv6_gd += readl(ioaddr + MMC_RX_IPV6_GD);
 248         mmc->mmc_rx_ipv6_hderr += readl(ioaddr + MMC_RX_IPV6_HDERR);
 249         mmc->mmc_rx_ipv6_nopay += readl(ioaddr + MMC_RX_IPV6_NOPAY);
 250
 251         /* Protocols */
 252         mmc->mmc_rx_udp_gd += readl(ioaddr + MMC_RX_UDP_GD);
 253         mmc->mmc_rx_udp_err += readl(ioaddr + MMC_RX_UDP_ERR);
 254         mmc->mmc_rx_tcp_gd += readl(ioaddr + MMC_RX_TCP_GD);
 255         mmc->mmc_rx_tcp_err += readl(ioaddr + MMC_RX_TCP_ERR);
 256         mmc->mmc_rx_icmp_gd += readl(ioaddr + MMC_RX_ICMP_GD);
 257         mmc->mmc_rx_icmp_err += readl(ioaddr + MMC_RX_ICMP_ERR);
 258
 259         mmc->mmc_rx_udp_gd_octets += readl(ioaddr + MMC_RX_UDP_GD_OCTETS);
 260         mmc->mmc_rx_udp_err_octets += readl(ioaddr + MMC_RX_UDP_ERR_OCTETS);
 261         mmc->mmc_rx_tcp_gd_octets += readl(ioaddr + MMC_RX_TCP_GD_OCTETS);
 262         mmc->mmc_rx_tcp_err_octets += readl(ioaddr + MMC_RX_TCP_ERR_OCTETS);
 263         mmc->mmc_rx_icmp_gd_octets += readl(ioaddr + MMC_RX_ICMP_GD_OCTETS);
 264         mmc->mmc_rx_icmp_err_octets += readl(ioaddr + MMC_RX_ICMP_ERR_OCTETS);
 265 }