2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2012 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
26 #define CARDNAME "sh-eth"
27 #define TX_TIMEOUT (5*HZ)
28 #define TX_RING_SIZE 64 /* Tx ring size */
29 #define RX_RING_SIZE 64 /* Rx ring size */
30 #define TX_RING_MIN 64
31 #define RX_RING_MIN 64
32 #define TX_RING_MAX 1024
33 #define RX_RING_MAX 1024
35 #define PKT_BUF_SZ 1538
36 #define SH_ETH_TSU_TIMEOUT_MS 500
37 #define SH_ETH_TSU_CAM_ENTRIES 32
40 /* E-DMAC registers */
108 /* TSU Absolute address */
155 /* This value must be written at last. */
156 SH_ETH_MAX_REGISTER_OFFSET
,
159 static const u16 sh_eth_offset_gigabit
[SH_ETH_MAX_REGISTER_OFFSET
] = {
213 [TSU_CTRST
] = 0x0004,
214 [TSU_FWEN0
] = 0x0010,
215 [TSU_FWEN1
] = 0x0014,
217 [TSU_BSYSL0
] = 0x0020,
218 [TSU_BSYSL1
] = 0x0024,
219 [TSU_PRISL0
] = 0x0028,
220 [TSU_PRISL1
] = 0x002c,
221 [TSU_FWSL0
] = 0x0030,
222 [TSU_FWSL1
] = 0x0034,
223 [TSU_FWSLC
] = 0x0038,
224 [TSU_QTAG0
] = 0x0040,
225 [TSU_QTAG1
] = 0x0044,
227 [TSU_FWINMK
] = 0x0054,
228 [TSU_ADQT0
] = 0x0048,
229 [TSU_ADQT1
] = 0x004c,
230 [TSU_VTAG0
] = 0x0058,
231 [TSU_VTAG1
] = 0x005c,
232 [TSU_ADSBSY
] = 0x0060,
234 [TSU_POST1
] = 0x0070,
235 [TSU_POST2
] = 0x0074,
236 [TSU_POST3
] = 0x0078,
237 [TSU_POST4
] = 0x007c,
238 [TSU_ADRH0
] = 0x0100,
239 [TSU_ADRL0
] = 0x0104,
240 [TSU_ADRH31
] = 0x01f8,
241 [TSU_ADRL31
] = 0x01fc,
257 static const u16 sh_eth_offset_fast_sh4
[SH_ETH_MAX_REGISTER_OFFSET
] = {
309 static const u16 sh_eth_offset_fast_sh3_sh2
[SH_ETH_MAX_REGISTER_OFFSET
] = {
335 [TSU_CTRST
] = 0x0004,
336 [TSU_FWEN0
] = 0x0010,
337 [TSU_FWEN1
] = 0x0014,
339 [TSU_BSYSL0
] = 0x0020,
340 [TSU_BSYSL1
] = 0x0024,
341 [TSU_PRISL0
] = 0x0028,
342 [TSU_PRISL1
] = 0x002c,
343 [TSU_FWSL0
] = 0x0030,
344 [TSU_FWSL1
] = 0x0034,
345 [TSU_FWSLC
] = 0x0038,
346 [TSU_QTAGM0
] = 0x0040,
347 [TSU_QTAGM1
] = 0x0044,
348 [TSU_ADQT0
] = 0x0048,
349 [TSU_ADQT1
] = 0x004c,
351 [TSU_FWINMK
] = 0x0054,
352 [TSU_ADSBSY
] = 0x0060,
354 [TSU_POST1
] = 0x0070,
355 [TSU_POST2
] = 0x0074,
356 [TSU_POST3
] = 0x0078,
357 [TSU_POST4
] = 0x007c,
372 [TSU_ADRH0
] = 0x0100,
373 [TSU_ADRL0
] = 0x0104,
374 [TSU_ADRL31
] = 0x01fc,
378 /* Driver's parameters */
379 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
380 #define SH4_SKB_RX_ALIGN 32
382 #define SH2_SH3_SKB_RX_ALIGN 2
388 #if defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) ||\
389 defined(CONFIG_ARCH_R8A7740)
392 EDSR_ENT
= 0x01, EDSR_ENR
= 0x02,
394 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
398 GECMR_10
= 0x0, GECMR_100
= 0x04, GECMR_1000
= 0x01,
404 EDMR_EL
= 0x40, /* Litte endian */
405 EDMR_DL1
= 0x20, EDMR_DL0
= 0x10,
406 EDMR_SRST_GETHER
= 0x03,
407 EDMR_SRST_ETHER
= 0x01,
412 EDTRR_TRNS_GETHER
= 0x03,
413 EDTRR_TRNS_ETHER
= 0x01,
423 TPAUSER_TPAUSE
= 0x0000ffff,
424 TPAUSER_UNLIMITED
= 0,
429 BCFR_RPAUSE
= 0x0000ffff,
435 PIR_MDI
= 0x08, PIR_MDO
= 0x04, PIR_MMD
= 0x02, PIR_MDC
= 0x01,
439 enum PHY_STATUS_BIT
{ PHY_ST_LINK
= 0x01, };
443 EESR_TWB1
= 0x80000000,
444 EESR_TWB
= 0x40000000, /* same as TWB0 */
445 EESR_TC1
= 0x20000000,
446 EESR_TUC
= 0x10000000,
447 EESR_ROC
= 0x08000000,
448 EESR_TABT
= 0x04000000,
449 EESR_RABT
= 0x02000000,
450 EESR_RFRMER
= 0x01000000, /* same as RFCOF */
451 EESR_ADE
= 0x00800000,
452 EESR_ECI
= 0x00400000,
453 EESR_FTC
= 0x00200000, /* same as TC or TC0 */
454 EESR_TDE
= 0x00100000,
455 EESR_TFE
= 0x00080000, /* same as TFUF */
456 EESR_FRC
= 0x00040000, /* same as FR */
457 EESR_RDE
= 0x00020000,
458 EESR_RFE
= 0x00010000,
459 EESR_CND
= 0x00000800,
460 EESR_DLC
= 0x00000400,
461 EESR_CD
= 0x00000200,
462 EESR_RTO
= 0x00000100,
463 EESR_RMAF
= 0x00000080,
464 EESR_CEEF
= 0x00000040,
465 EESR_CELF
= 0x00000020,
466 EESR_RRF
= 0x00000010,
467 EESR_RTLF
= 0x00000008,
468 EESR_RTSF
= 0x00000004,
469 EESR_PRE
= 0x00000002,
470 EESR_CERF
= 0x00000001,
473 #define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
475 #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | \
476 EESR_RDE | EESR_RFRMER | EESR_ADE | \
477 EESR_TFE | EESR_TDE | EESR_ECI)
478 #define DEFAULT_TX_ERROR_CHECK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
483 DMAC_M_TWB
= 0x40000000, DMAC_M_TABT
= 0x04000000,
484 DMAC_M_RABT
= 0x02000000,
485 DMAC_M_RFRMER
= 0x01000000, DMAC_M_ADF
= 0x00800000,
486 DMAC_M_ECI
= 0x00400000, DMAC_M_FTC
= 0x00200000,
487 DMAC_M_TDE
= 0x00100000, DMAC_M_TFE
= 0x00080000,
488 DMAC_M_FRC
= 0x00040000, DMAC_M_RDE
= 0x00020000,
489 DMAC_M_RFE
= 0x00010000, DMAC_M_TINT4
= 0x00000800,
490 DMAC_M_TINT3
= 0x00000400, DMAC_M_TINT2
= 0x00000200,
491 DMAC_M_TINT1
= 0x00000100, DMAC_M_RINT8
= 0x00000080,
492 DMAC_M_RINT5
= 0x00000010, DMAC_M_RINT4
= 0x00000008,
493 DMAC_M_RINT3
= 0x00000004, DMAC_M_RINT2
= 0x00000002,
494 DMAC_M_RINT1
= 0x00000001,
497 /* Receive descriptor bit */
499 RD_RACT
= 0x80000000, RD_RDEL
= 0x40000000,
500 RD_RFP1
= 0x20000000, RD_RFP0
= 0x10000000,
501 RD_RFE
= 0x08000000, RD_RFS10
= 0x00000200,
502 RD_RFS9
= 0x00000100, RD_RFS8
= 0x00000080,
503 RD_RFS7
= 0x00000040, RD_RFS6
= 0x00000020,
504 RD_RFS5
= 0x00000010, RD_RFS4
= 0x00000008,
505 RD_RFS3
= 0x00000004, RD_RFS2
= 0x00000002,
506 RD_RFS1
= 0x00000001,
508 #define RDF1ST RD_RFP1
509 #define RDFEND RD_RFP0
510 #define RD_RFP (RD_RFP1|RD_RFP0)
514 FCFTR_RFF2
= 0x00040000, FCFTR_RFF1
= 0x00020000,
515 FCFTR_RFF0
= 0x00010000, FCFTR_RFD2
= 0x00000004,
516 FCFTR_RFD1
= 0x00000002, FCFTR_RFD0
= 0x00000001,
518 #define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
519 #define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
521 /* Transfer descriptor bit */
523 TD_TACT
= 0x80000000,
524 TD_TDLE
= 0x40000000, TD_TFP1
= 0x20000000,
525 TD_TFP0
= 0x10000000,
527 #define TDF1ST TD_TFP1
528 #define TDFEND TD_TFP0
529 #define TD_TFP (TD_TFP1|TD_TFP0)
532 #define DEFAULT_RMCR_VALUE 0x00000000
535 enum FELIC_MODE_BIT
{
536 ECMR_TRCCM
= 0x04000000, ECMR_RCSC
= 0x00800000,
537 ECMR_DPAD
= 0x00200000, ECMR_RZPF
= 0x00100000,
538 ECMR_ZPF
= 0x00080000, ECMR_PFR
= 0x00040000, ECMR_RXF
= 0x00020000,
539 ECMR_TXF
= 0x00010000, ECMR_MCT
= 0x00002000, ECMR_PRCEF
= 0x00001000,
540 ECMR_PMDE
= 0x00000200, ECMR_RE
= 0x00000040, ECMR_TE
= 0x00000020,
541 ECMR_RTM
= 0x00000010, ECMR_ILB
= 0x00000008, ECMR_ELB
= 0x00000004,
542 ECMR_DM
= 0x00000002, ECMR_PRM
= 0x00000001,
546 enum ECSR_STATUS_BIT
{
547 ECSR_BRCRX
= 0x20, ECSR_PSRTO
= 0x10,
549 ECSR_MPD
= 0x02, ECSR_ICD
= 0x01,
552 #define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
553 ECSR_ICD | ECSIPR_MPDIP)
556 enum ECSIPR_STATUS_MASK_BIT
{
557 ECSIPR_BRCRXIP
= 0x20, ECSIPR_PSRTOIP
= 0x10,
558 ECSIPR_LCHNGIP
= 0x04,
559 ECSIPR_MPDIP
= 0x02, ECSIPR_ICDIP
= 0x01,
562 #define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
563 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
577 DESC_I_TINT4
= 0x0800, DESC_I_TINT3
= 0x0400, DESC_I_TINT2
= 0x0200,
578 DESC_I_TINT1
= 0x0100, DESC_I_RINT8
= 0x0080, DESC_I_RINT5
= 0x0010,
579 DESC_I_RINT4
= 0x0008, DESC_I_RINT3
= 0x0004, DESC_I_RINT2
= 0x0002,
580 DESC_I_RINT1
= 0x0001,
585 RPADIR_PADS1
= 0x20000, RPADIR_PADS0
= 0x10000,
586 RPADIR_PADR
= 0x0003f,
590 #define DEFAULT_FDR_INIT 0x00000707
593 enum ARSTR_BIT
{ ARSTR_ARSTR
= 0x00000001, };
597 TSU_FWEN0_0
= 0x00000001,
601 enum TSU_ADSBSY_BIT
{
602 TSU_ADSBSY_0
= 0x00000001,
607 TSU_TEN_0
= 0x80000000,
612 TSU_FWSL0_FW50
= 0x1000, TSU_FWSL0_FW40
= 0x0800,
613 TSU_FWSL0_FW30
= 0x0400, TSU_FWSL0_FW20
= 0x0200,
614 TSU_FWSL0_FW10
= 0x0100, TSU_FWSL0_RMSA0
= 0x0010,
619 TSU_FWSLC_POSTENU
= 0x2000, TSU_FWSLC_POSTENL
= 0x1000,
620 TSU_FWSLC_CAMSEL03
= 0x0080, TSU_FWSLC_CAMSEL02
= 0x0040,
621 TSU_FWSLC_CAMSEL01
= 0x0020, TSU_FWSLC_CAMSEL00
= 0x0010,
622 TSU_FWSLC_CAMSEL13
= 0x0008, TSU_FWSLC_CAMSEL12
= 0x0004,
623 TSU_FWSLC_CAMSEL11
= 0x0002, TSU_FWSLC_CAMSEL10
= 0x0001,
627 #define TSU_VTAG_ENABLE 0x80000000
628 #define TSU_VTAG_VID_MASK 0x00000fff
631 * The sh ether Tx buffer descriptors.
632 * This structure should be 20 bytes.
634 struct sh_eth_txdesc
{
635 u32 status
; /* TD0 */
636 #if defined(__LITTLE_ENDIAN)
638 u16 buffer_length
; /* TD1 */
640 u16 buffer_length
; /* TD1 */
644 u32 pad1
; /* padding data */
645 } __attribute__((aligned(2), packed
));
648 * The sh ether Rx buffer descriptors.
649 * This structure should be 20 bytes.
651 struct sh_eth_rxdesc
{
652 u32 status
; /* RD0 */
653 #if defined(__LITTLE_ENDIAN)
654 u16 frame_length
; /* RD1 */
655 u16 buffer_length
; /* RD1 */
657 u16 buffer_length
; /* RD1 */
658 u16 frame_length
; /* RD1 */
661 u32 pad0
; /* padding data */
662 } __attribute__((aligned(2), packed
));
664 /* This structure is used by each CPU dependency handling. */
665 struct sh_eth_cpu_data
{
666 /* optional functions */
667 void (*chip_reset
)(struct net_device
*ndev
);
668 void (*set_duplex
)(struct net_device
*ndev
);
669 void (*set_rate
)(struct net_device
*ndev
);
671 /* mandatory initialize value */
672 unsigned long eesipr_value
;
674 /* optional initialize value */
675 unsigned long ecsr_value
;
676 unsigned long ecsipr_value
;
677 unsigned long fdr_value
;
678 unsigned long fcftr_value
;
679 unsigned long rpadir_value
;
680 unsigned long rmcr_value
;
682 /* interrupt checking mask */
683 unsigned long tx_check
;
684 unsigned long eesr_err_check
;
685 unsigned long tx_error_check
;
687 /* hardware features */
688 unsigned no_psr
:1; /* EtherC DO NOT have PSR */
689 unsigned apr
:1; /* EtherC have APR */
690 unsigned mpr
:1; /* EtherC have MPR */
691 unsigned tpauser
:1; /* EtherC have TPAUSER */
692 unsigned bculr
:1; /* EtherC have BCULR */
693 unsigned tsu
:1; /* EtherC have TSU */
694 unsigned hw_swap
:1; /* E-DMAC have DE bit in EDMR */
695 unsigned rpadir
:1; /* E-DMAC have RPADIR */
696 unsigned no_trimd
:1; /* E-DMAC DO NOT have TRIMD */
697 unsigned no_ade
:1; /* E-DMAC DO NOT have ADE bit in EESR */
698 unsigned hw_crc
:1; /* E-DMAC have CSMR */
699 unsigned select_mii
:1; /* EtherC have RMII_MII (MII select register) */
702 struct sh_eth_private
{
703 struct platform_device
*pdev
;
704 struct sh_eth_cpu_data
*cd
;
705 const u16
*reg_offset
;
707 void __iomem
*tsu_addr
;
710 dma_addr_t rx_desc_dma
;
711 dma_addr_t tx_desc_dma
;
712 struct sh_eth_rxdesc
*rx_ring
;
713 struct sh_eth_txdesc
*tx_ring
;
714 struct sk_buff
**rx_skbuff
;
715 struct sk_buff
**tx_skbuff
;
717 u32 cur_rx
, dirty_rx
; /* Producer/consumer ring indices */
718 u32 cur_tx
, dirty_tx
;
719 u32 rx_buf_sz
; /* Based on MTU+slack. */
721 /* MII transceiver section. */
722 u32 phy_id
; /* PHY ID */
723 struct mii_bus
*mii_bus
; /* MDIO bus control */
724 struct phy_device
*phydev
; /* PHY device control */
726 phy_interface_t phy_interface
;
730 int port
; /* for TSU */
731 int vlan_num_ids
; /* for VLAN tag filter */
733 unsigned no_ether_link
:1;
734 unsigned ether_link_active_low
:1;
737 static inline void sh_eth_soft_swap(char *src
, int len
)
739 #ifdef __LITTLE_ENDIAN__
742 maxp
= p
+ ((len
+ sizeof(u32
) - 1) / sizeof(u32
));
744 for (; p
< maxp
; p
++)
749 static inline void sh_eth_write(struct net_device
*ndev
, unsigned long data
,
752 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
754 iowrite32(data
, mdp
->addr
+ mdp
->reg_offset
[enum_index
]);
757 static inline unsigned long sh_eth_read(struct net_device
*ndev
,
760 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
762 return ioread32(mdp
->addr
+ mdp
->reg_offset
[enum_index
]);
765 static inline void *sh_eth_tsu_get_offset(struct sh_eth_private
*mdp
,
768 return mdp
->tsu_addr
+ mdp
->reg_offset
[enum_index
];
771 static inline void sh_eth_tsu_write(struct sh_eth_private
*mdp
,
772 unsigned long data
, int enum_index
)
774 iowrite32(data
, mdp
->tsu_addr
+ mdp
->reg_offset
[enum_index
]);
777 static inline unsigned long sh_eth_tsu_read(struct sh_eth_private
*mdp
,
780 return ioread32(mdp
->tsu_addr
+ mdp
->reg_offset
[enum_index
]);
783 #endif /* #ifndef __SH_ETH_H__ */