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2183c618914843d30ef2dd7bcbfebcc529c8ddf4
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / realtek / r8169.c
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34
35 #define RTL8169_VERSION "2.3LK-NAPI"
36 #define MODULENAME "r8169"
37 #define PFX MODULENAME ": "
38
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53
54 #ifdef RTL8169_DEBUG
55 #define assert(expr) \
56 if (!(expr)) { \
57 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
58 #expr,__FILE__,__func__,__LINE__); \
59 }
60 #define dprintk(fmt, args...) \
61 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
62 #else
63 #define assert(expr) do {} while (0)
64 #define dprintk(fmt, args...) do {} while (0)
65 #endif /* RTL8169_DEBUG */
66
67 #define R8169_MSG_DEFAULT \
68 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
69
70 #define TX_SLOTS_AVAIL(tp) \
71 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
72
73 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
74 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
75 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
76
77 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
78 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
79 static const int multicast_filter_limit = 32;
80
81 #define MAX_READ_REQUEST_SHIFT 12
82 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
83 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
84
85 #define R8169_REGS_SIZE 256
86 #define R8169_NAPI_WEIGHT 64
87 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
88 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
89 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
90 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
91
92 #define RTL8169_TX_TIMEOUT (6*HZ)
93 #define RTL8169_PHY_TIMEOUT (10*HZ)
94
95 /* write/read MMIO register */
96 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
97 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
98 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
99 #define RTL_R8(reg) readb (ioaddr + (reg))
100 #define RTL_R16(reg) readw (ioaddr + (reg))
101 #define RTL_R32(reg) readl (ioaddr + (reg))
102
103 enum mac_version {
104 RTL_GIGA_MAC_VER_01 = 0,
105 RTL_GIGA_MAC_VER_02,
106 RTL_GIGA_MAC_VER_03,
107 RTL_GIGA_MAC_VER_04,
108 RTL_GIGA_MAC_VER_05,
109 RTL_GIGA_MAC_VER_06,
110 RTL_GIGA_MAC_VER_07,
111 RTL_GIGA_MAC_VER_08,
112 RTL_GIGA_MAC_VER_09,
113 RTL_GIGA_MAC_VER_10,
114 RTL_GIGA_MAC_VER_11,
115 RTL_GIGA_MAC_VER_12,
116 RTL_GIGA_MAC_VER_13,
117 RTL_GIGA_MAC_VER_14,
118 RTL_GIGA_MAC_VER_15,
119 RTL_GIGA_MAC_VER_16,
120 RTL_GIGA_MAC_VER_17,
121 RTL_GIGA_MAC_VER_18,
122 RTL_GIGA_MAC_VER_19,
123 RTL_GIGA_MAC_VER_20,
124 RTL_GIGA_MAC_VER_21,
125 RTL_GIGA_MAC_VER_22,
126 RTL_GIGA_MAC_VER_23,
127 RTL_GIGA_MAC_VER_24,
128 RTL_GIGA_MAC_VER_25,
129 RTL_GIGA_MAC_VER_26,
130 RTL_GIGA_MAC_VER_27,
131 RTL_GIGA_MAC_VER_28,
132 RTL_GIGA_MAC_VER_29,
133 RTL_GIGA_MAC_VER_30,
134 RTL_GIGA_MAC_VER_31,
135 RTL_GIGA_MAC_VER_32,
136 RTL_GIGA_MAC_VER_33,
137 RTL_GIGA_MAC_VER_34,
138 RTL_GIGA_MAC_VER_35,
139 RTL_GIGA_MAC_VER_36,
140 RTL_GIGA_MAC_VER_37,
141 RTL_GIGA_MAC_VER_38,
142 RTL_GIGA_MAC_VER_39,
143 RTL_GIGA_MAC_VER_40,
144 RTL_GIGA_MAC_VER_41,
145 RTL_GIGA_MAC_VER_42,
146 RTL_GIGA_MAC_VER_43,
147 RTL_GIGA_MAC_NONE = 0xff,
148 };
149
150 enum rtl_tx_desc_version {
151 RTL_TD_0 = 0,
152 RTL_TD_1 = 1,
153 };
154
155 #define JUMBO_1K ETH_DATA_LEN
156 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
157 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
158 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
159 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
160
161 #define _R(NAME,TD,FW,SZ,B) { \
162 .name = NAME, \
163 .txd_version = TD, \
164 .fw_name = FW, \
165 .jumbo_max = SZ, \
166 .jumbo_tx_csum = B \
167 }
168
169 static const struct {
170 const char *name;
171 enum rtl_tx_desc_version txd_version;
172 const char *fw_name;
173 u16 jumbo_max;
174 bool jumbo_tx_csum;
175 } rtl_chip_infos[] = {
176 /* PCI devices. */
177 [RTL_GIGA_MAC_VER_01] =
178 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
179 [RTL_GIGA_MAC_VER_02] =
180 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
181 [RTL_GIGA_MAC_VER_03] =
182 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
183 [RTL_GIGA_MAC_VER_04] =
184 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
185 [RTL_GIGA_MAC_VER_05] =
186 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
187 [RTL_GIGA_MAC_VER_06] =
188 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
189 /* PCI-E devices. */
190 [RTL_GIGA_MAC_VER_07] =
191 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
192 [RTL_GIGA_MAC_VER_08] =
193 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
194 [RTL_GIGA_MAC_VER_09] =
195 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
196 [RTL_GIGA_MAC_VER_10] =
197 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
198 [RTL_GIGA_MAC_VER_11] =
199 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
200 [RTL_GIGA_MAC_VER_12] =
201 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
202 [RTL_GIGA_MAC_VER_13] =
203 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
204 [RTL_GIGA_MAC_VER_14] =
205 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
206 [RTL_GIGA_MAC_VER_15] =
207 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
208 [RTL_GIGA_MAC_VER_16] =
209 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
210 [RTL_GIGA_MAC_VER_17] =
211 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
212 [RTL_GIGA_MAC_VER_18] =
213 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
214 [RTL_GIGA_MAC_VER_19] =
215 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
216 [RTL_GIGA_MAC_VER_20] =
217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
218 [RTL_GIGA_MAC_VER_21] =
219 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
220 [RTL_GIGA_MAC_VER_22] =
221 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
222 [RTL_GIGA_MAC_VER_23] =
223 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
224 [RTL_GIGA_MAC_VER_24] =
225 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
226 [RTL_GIGA_MAC_VER_25] =
227 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
228 JUMBO_9K, false),
229 [RTL_GIGA_MAC_VER_26] =
230 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
231 JUMBO_9K, false),
232 [RTL_GIGA_MAC_VER_27] =
233 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
234 [RTL_GIGA_MAC_VER_28] =
235 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
236 [RTL_GIGA_MAC_VER_29] =
237 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
238 JUMBO_1K, true),
239 [RTL_GIGA_MAC_VER_30] =
240 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
241 JUMBO_1K, true),
242 [RTL_GIGA_MAC_VER_31] =
243 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
244 [RTL_GIGA_MAC_VER_32] =
245 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
246 JUMBO_9K, false),
247 [RTL_GIGA_MAC_VER_33] =
248 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
249 JUMBO_9K, false),
250 [RTL_GIGA_MAC_VER_34] =
251 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
252 JUMBO_9K, false),
253 [RTL_GIGA_MAC_VER_35] =
254 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
255 JUMBO_9K, false),
256 [RTL_GIGA_MAC_VER_36] =
257 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
258 JUMBO_9K, false),
259 [RTL_GIGA_MAC_VER_37] =
260 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
261 JUMBO_1K, true),
262 [RTL_GIGA_MAC_VER_38] =
263 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
264 JUMBO_9K, false),
265 [RTL_GIGA_MAC_VER_39] =
266 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
267 JUMBO_1K, true),
268 [RTL_GIGA_MAC_VER_40] =
269 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
270 JUMBO_9K, false),
271 [RTL_GIGA_MAC_VER_41] =
272 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
273 [RTL_GIGA_MAC_VER_42] =
274 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
275 JUMBO_9K, false),
276 [RTL_GIGA_MAC_VER_43] =
277 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
278 JUMBO_1K, true),
279 };
280 #undef _R
281
282 enum cfg_version {
283 RTL_CFG_0 = 0x00,
284 RTL_CFG_1,
285 RTL_CFG_2
286 };
287
288 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
289 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
290 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
291 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
292 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
293 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
294 { PCI_VENDOR_ID_DLINK, 0x4300,
295 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
296 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
297 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
298 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
299 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
300 { PCI_VENDOR_ID_LINKSYS, 0x1032,
301 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
302 { 0x0001, 0x8168,
303 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
304 {0,},
305 };
306
307 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
308
309 static int rx_buf_sz = 16383;
310 static int use_dac;
311 static struct {
312 u32 msg_enable;
313 } debug = { -1 };
314
315 enum rtl_registers {
316 MAC0 = 0, /* Ethernet hardware address. */
317 MAC4 = 4,
318 MAR0 = 8, /* Multicast filter. */
319 CounterAddrLow = 0x10,
320 CounterAddrHigh = 0x14,
321 TxDescStartAddrLow = 0x20,
322 TxDescStartAddrHigh = 0x24,
323 TxHDescStartAddrLow = 0x28,
324 TxHDescStartAddrHigh = 0x2c,
325 FLASH = 0x30,
326 ERSR = 0x36,
327 ChipCmd = 0x37,
328 TxPoll = 0x38,
329 IntrMask = 0x3c,
330 IntrStatus = 0x3e,
331
332 TxConfig = 0x40,
333 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
334 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
335
336 RxConfig = 0x44,
337 #define RX128_INT_EN (1 << 15) /* 8111c and later */
338 #define RX_MULTI_EN (1 << 14) /* 8111c only */
339 #define RXCFG_FIFO_SHIFT 13
340 /* No threshold before first PCI xfer */
341 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
342 #define RX_EARLY_OFF (1 << 11)
343 #define RXCFG_DMA_SHIFT 8
344 /* Unlimited maximum PCI burst. */
345 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
346
347 RxMissed = 0x4c,
348 Cfg9346 = 0x50,
349 Config0 = 0x51,
350 Config1 = 0x52,
351 Config2 = 0x53,
352 #define PME_SIGNAL (1 << 5) /* 8168c and later */
353
354 Config3 = 0x54,
355 Config4 = 0x55,
356 Config5 = 0x56,
357 MultiIntr = 0x5c,
358 PHYAR = 0x60,
359 PHYstatus = 0x6c,
360 RxMaxSize = 0xda,
361 CPlusCmd = 0xe0,
362 IntrMitigate = 0xe2,
363 RxDescAddrLow = 0xe4,
364 RxDescAddrHigh = 0xe8,
365 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
366
367 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
368
369 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
370
371 #define TxPacketMax (8064 >> 7)
372 #define EarlySize 0x27
373
374 FuncEvent = 0xf0,
375 FuncEventMask = 0xf4,
376 FuncPresetState = 0xf8,
377 FuncForceEvent = 0xfc,
378 };
379
380 enum rtl8110_registers {
381 TBICSR = 0x64,
382 TBI_ANAR = 0x68,
383 TBI_LPAR = 0x6a,
384 };
385
386 enum rtl8168_8101_registers {
387 CSIDR = 0x64,
388 CSIAR = 0x68,
389 #define CSIAR_FLAG 0x80000000
390 #define CSIAR_WRITE_CMD 0x80000000
391 #define CSIAR_BYTE_ENABLE 0x0f
392 #define CSIAR_BYTE_ENABLE_SHIFT 12
393 #define CSIAR_ADDR_MASK 0x0fff
394 #define CSIAR_FUNC_CARD 0x00000000
395 #define CSIAR_FUNC_SDIO 0x00010000
396 #define CSIAR_FUNC_NIC 0x00020000
397 PMCH = 0x6f,
398 EPHYAR = 0x80,
399 #define EPHYAR_FLAG 0x80000000
400 #define EPHYAR_WRITE_CMD 0x80000000
401 #define EPHYAR_REG_MASK 0x1f
402 #define EPHYAR_REG_SHIFT 16
403 #define EPHYAR_DATA_MASK 0xffff
404 DLLPR = 0xd0,
405 #define PFM_EN (1 << 6)
406 DBG_REG = 0xd1,
407 #define FIX_NAK_1 (1 << 4)
408 #define FIX_NAK_2 (1 << 3)
409 TWSI = 0xd2,
410 MCU = 0xd3,
411 #define NOW_IS_OOB (1 << 7)
412 #define TX_EMPTY (1 << 5)
413 #define RX_EMPTY (1 << 4)
414 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
415 #define EN_NDP (1 << 3)
416 #define EN_OOB_RESET (1 << 2)
417 #define LINK_LIST_RDY (1 << 1)
418 EFUSEAR = 0xdc,
419 #define EFUSEAR_FLAG 0x80000000
420 #define EFUSEAR_WRITE_CMD 0x80000000
421 #define EFUSEAR_READ_CMD 0x00000000
422 #define EFUSEAR_REG_MASK 0x03ff
423 #define EFUSEAR_REG_SHIFT 8
424 #define EFUSEAR_DATA_MASK 0xff
425 };
426
427 enum rtl8168_registers {
428 LED_FREQ = 0x1a,
429 EEE_LED = 0x1b,
430 ERIDR = 0x70,
431 ERIAR = 0x74,
432 #define ERIAR_FLAG 0x80000000
433 #define ERIAR_WRITE_CMD 0x80000000
434 #define ERIAR_READ_CMD 0x00000000
435 #define ERIAR_ADDR_BYTE_ALIGN 4
436 #define ERIAR_TYPE_SHIFT 16
437 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
438 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
439 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
440 #define ERIAR_MASK_SHIFT 12
441 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
442 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
443 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
444 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
445 EPHY_RXER_NUM = 0x7c,
446 OCPDR = 0xb0, /* OCP GPHY access */
447 #define OCPDR_WRITE_CMD 0x80000000
448 #define OCPDR_READ_CMD 0x00000000
449 #define OCPDR_REG_MASK 0x7f
450 #define OCPDR_GPHY_REG_SHIFT 16
451 #define OCPDR_DATA_MASK 0xffff
452 OCPAR = 0xb4,
453 #define OCPAR_FLAG 0x80000000
454 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
455 #define OCPAR_GPHY_READ_CMD 0x0000f060
456 GPHY_OCP = 0xb8,
457 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
458 MISC = 0xf0, /* 8168e only. */
459 #define TXPLA_RST (1 << 29)
460 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
461 #define PWM_EN (1 << 22)
462 #define RXDV_GATED_EN (1 << 19)
463 #define EARLY_TALLY_EN (1 << 16)
464 };
465
466 enum rtl_register_content {
467 /* InterruptStatusBits */
468 SYSErr = 0x8000,
469 PCSTimeout = 0x4000,
470 SWInt = 0x0100,
471 TxDescUnavail = 0x0080,
472 RxFIFOOver = 0x0040,
473 LinkChg = 0x0020,
474 RxOverflow = 0x0010,
475 TxErr = 0x0008,
476 TxOK = 0x0004,
477 RxErr = 0x0002,
478 RxOK = 0x0001,
479
480 /* RxStatusDesc */
481 RxBOVF = (1 << 24),
482 RxFOVF = (1 << 23),
483 RxRWT = (1 << 22),
484 RxRES = (1 << 21),
485 RxRUNT = (1 << 20),
486 RxCRC = (1 << 19),
487
488 /* ChipCmdBits */
489 StopReq = 0x80,
490 CmdReset = 0x10,
491 CmdRxEnb = 0x08,
492 CmdTxEnb = 0x04,
493 RxBufEmpty = 0x01,
494
495 /* TXPoll register p.5 */
496 HPQ = 0x80, /* Poll cmd on the high prio queue */
497 NPQ = 0x40, /* Poll cmd on the low prio queue */
498 FSWInt = 0x01, /* Forced software interrupt */
499
500 /* Cfg9346Bits */
501 Cfg9346_Lock = 0x00,
502 Cfg9346_Unlock = 0xc0,
503
504 /* rx_mode_bits */
505 AcceptErr = 0x20,
506 AcceptRunt = 0x10,
507 AcceptBroadcast = 0x08,
508 AcceptMulticast = 0x04,
509 AcceptMyPhys = 0x02,
510 AcceptAllPhys = 0x01,
511 #define RX_CONFIG_ACCEPT_MASK 0x3f
512
513 /* TxConfigBits */
514 TxInterFrameGapShift = 24,
515 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
516
517 /* Config1 register p.24 */
518 LEDS1 = (1 << 7),
519 LEDS0 = (1 << 6),
520 Speed_down = (1 << 4),
521 MEMMAP = (1 << 3),
522 IOMAP = (1 << 2),
523 VPD = (1 << 1),
524 PMEnable = (1 << 0), /* Power Management Enable */
525
526 /* Config2 register p. 25 */
527 ClkReqEn = (1 << 7), /* Clock Request Enable */
528 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
529 PCI_Clock_66MHz = 0x01,
530 PCI_Clock_33MHz = 0x00,
531
532 /* Config3 register p.25 */
533 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
534 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
535 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
536 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
537
538 /* Config4 register */
539 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
540
541 /* Config5 register p.27 */
542 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
543 MWF = (1 << 5), /* Accept Multicast wakeup frame */
544 UWF = (1 << 4), /* Accept Unicast wakeup frame */
545 Spi_en = (1 << 3),
546 LanWake = (1 << 1), /* LanWake enable/disable */
547 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
548 ASPM_en = (1 << 0), /* ASPM enable */
549
550 /* TBICSR p.28 */
551 TBIReset = 0x80000000,
552 TBILoopback = 0x40000000,
553 TBINwEnable = 0x20000000,
554 TBINwRestart = 0x10000000,
555 TBILinkOk = 0x02000000,
556 TBINwComplete = 0x01000000,
557
558 /* CPlusCmd p.31 */
559 EnableBist = (1 << 15), // 8168 8101
560 Mac_dbgo_oe = (1 << 14), // 8168 8101
561 Normal_mode = (1 << 13), // unused
562 Force_half_dup = (1 << 12), // 8168 8101
563 Force_rxflow_en = (1 << 11), // 8168 8101
564 Force_txflow_en = (1 << 10), // 8168 8101
565 Cxpl_dbg_sel = (1 << 9), // 8168 8101
566 ASF = (1 << 8), // 8168 8101
567 PktCntrDisable = (1 << 7), // 8168 8101
568 Mac_dbgo_sel = 0x001c, // 8168
569 RxVlan = (1 << 6),
570 RxChkSum = (1 << 5),
571 PCIDAC = (1 << 4),
572 PCIMulRW = (1 << 3),
573 INTT_0 = 0x0000, // 8168
574 INTT_1 = 0x0001, // 8168
575 INTT_2 = 0x0002, // 8168
576 INTT_3 = 0x0003, // 8168
577
578 /* rtl8169_PHYstatus */
579 TBI_Enable = 0x80,
580 TxFlowCtrl = 0x40,
581 RxFlowCtrl = 0x20,
582 _1000bpsF = 0x10,
583 _100bps = 0x08,
584 _10bps = 0x04,
585 LinkStatus = 0x02,
586 FullDup = 0x01,
587
588 /* _TBICSRBit */
589 TBILinkOK = 0x02000000,
590
591 /* DumpCounterCommand */
592 CounterDump = 0x8,
593 };
594
595 enum rtl_desc_bit {
596 /* First doubleword. */
597 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
598 RingEnd = (1 << 30), /* End of descriptor ring */
599 FirstFrag = (1 << 29), /* First segment of a packet */
600 LastFrag = (1 << 28), /* Final segment of a packet */
601 };
602
603 /* Generic case. */
604 enum rtl_tx_desc_bit {
605 /* First doubleword. */
606 TD_LSO = (1 << 27), /* Large Send Offload */
607 #define TD_MSS_MAX 0x07ffu /* MSS value */
608
609 /* Second doubleword. */
610 TxVlanTag = (1 << 17), /* Add VLAN tag */
611 };
612
613 /* 8169, 8168b and 810x except 8102e. */
614 enum rtl_tx_desc_bit_0 {
615 /* First doubleword. */
616 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
617 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
618 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
619 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
620 };
621
622 /* 8102e, 8168c and beyond. */
623 enum rtl_tx_desc_bit_1 {
624 /* Second doubleword. */
625 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
626 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
627 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
628 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
629 };
630
631 static const struct rtl_tx_desc_info {
632 struct {
633 u32 udp;
634 u32 tcp;
635 } checksum;
636 u16 mss_shift;
637 u16 opts_offset;
638 } tx_desc_info [] = {
639 [RTL_TD_0] = {
640 .checksum = {
641 .udp = TD0_IP_CS | TD0_UDP_CS,
642 .tcp = TD0_IP_CS | TD0_TCP_CS
643 },
644 .mss_shift = TD0_MSS_SHIFT,
645 .opts_offset = 0
646 },
647 [RTL_TD_1] = {
648 .checksum = {
649 .udp = TD1_IP_CS | TD1_UDP_CS,
650 .tcp = TD1_IP_CS | TD1_TCP_CS
651 },
652 .mss_shift = TD1_MSS_SHIFT,
653 .opts_offset = 1
654 }
655 };
656
657 enum rtl_rx_desc_bit {
658 /* Rx private */
659 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
660 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
661
662 #define RxProtoUDP (PID1)
663 #define RxProtoTCP (PID0)
664 #define RxProtoIP (PID1 | PID0)
665 #define RxProtoMask RxProtoIP
666
667 IPFail = (1 << 16), /* IP checksum failed */
668 UDPFail = (1 << 15), /* UDP/IP checksum failed */
669 TCPFail = (1 << 14), /* TCP/IP checksum failed */
670 RxVlanTag = (1 << 16), /* VLAN tag available */
671 };
672
673 #define RsvdMask 0x3fffc000
674
675 struct TxDesc {
676 __le32 opts1;
677 __le32 opts2;
678 __le64 addr;
679 };
680
681 struct RxDesc {
682 __le32 opts1;
683 __le32 opts2;
684 __le64 addr;
685 };
686
687 struct ring_info {
688 struct sk_buff *skb;
689 u32 len;
690 u8 __pad[sizeof(void *) - sizeof(u32)];
691 };
692
693 enum features {
694 RTL_FEATURE_WOL = (1 << 0),
695 RTL_FEATURE_MSI = (1 << 1),
696 RTL_FEATURE_GMII = (1 << 2),
697 };
698
699 struct rtl8169_counters {
700 __le64 tx_packets;
701 __le64 rx_packets;
702 __le64 tx_errors;
703 __le32 rx_errors;
704 __le16 rx_missed;
705 __le16 align_errors;
706 __le32 tx_one_collision;
707 __le32 tx_multi_collision;
708 __le64 rx_unicast;
709 __le64 rx_broadcast;
710 __le32 rx_multicast;
711 __le16 tx_aborted;
712 __le16 tx_underun;
713 };
714
715 enum rtl_flag {
716 RTL_FLAG_TASK_ENABLED,
717 RTL_FLAG_TASK_SLOW_PENDING,
718 RTL_FLAG_TASK_RESET_PENDING,
719 RTL_FLAG_TASK_PHY_PENDING,
720 RTL_FLAG_MAX
721 };
722
723 struct rtl8169_stats {
724 u64 packets;
725 u64 bytes;
726 struct u64_stats_sync syncp;
727 };
728
729 struct rtl8169_private {
730 void __iomem *mmio_addr; /* memory map physical address */
731 struct pci_dev *pci_dev;
732 struct net_device *dev;
733 struct napi_struct napi;
734 u32 msg_enable;
735 u16 txd_version;
736 u16 mac_version;
737 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
738 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
739 u32 dirty_tx;
740 struct rtl8169_stats rx_stats;
741 struct rtl8169_stats tx_stats;
742 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
743 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
744 dma_addr_t TxPhyAddr;
745 dma_addr_t RxPhyAddr;
746 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
747 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
748 struct timer_list timer;
749 u16 cp_cmd;
750
751 u16 event_slow;
752
753 struct mdio_ops {
754 void (*write)(struct rtl8169_private *, int, int);
755 int (*read)(struct rtl8169_private *, int);
756 } mdio_ops;
757
758 struct pll_power_ops {
759 void (*down)(struct rtl8169_private *);
760 void (*up)(struct rtl8169_private *);
761 } pll_power_ops;
762
763 struct jumbo_ops {
764 void (*enable)(struct rtl8169_private *);
765 void (*disable)(struct rtl8169_private *);
766 } jumbo_ops;
767
768 struct csi_ops {
769 void (*write)(struct rtl8169_private *, int, int);
770 u32 (*read)(struct rtl8169_private *, int);
771 } csi_ops;
772
773 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
774 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
775 void (*phy_reset_enable)(struct rtl8169_private *tp);
776 void (*hw_start)(struct net_device *);
777 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
778 unsigned int (*link_ok)(void __iomem *);
779 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
780
781 struct {
782 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
783 struct mutex mutex;
784 struct work_struct work;
785 } wk;
786
787 unsigned features;
788
789 struct mii_if_info mii;
790 struct rtl8169_counters counters;
791 u32 saved_wolopts;
792 u32 opts1_mask;
793
794 struct rtl_fw {
795 const struct firmware *fw;
796
797 #define RTL_VER_SIZE 32
798
799 char version[RTL_VER_SIZE];
800
801 struct rtl_fw_phy_action {
802 __le32 *code;
803 size_t size;
804 } phy_action;
805 } *rtl_fw;
806 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
807
808 u32 ocp_base;
809 };
810
811 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
812 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
813 module_param(use_dac, int, 0);
814 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
815 module_param_named(debug, debug.msg_enable, int, 0);
816 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
817 MODULE_LICENSE("GPL");
818 MODULE_VERSION(RTL8169_VERSION);
819 MODULE_FIRMWARE(FIRMWARE_8168D_1);
820 MODULE_FIRMWARE(FIRMWARE_8168D_2);
821 MODULE_FIRMWARE(FIRMWARE_8168E_1);
822 MODULE_FIRMWARE(FIRMWARE_8168E_2);
823 MODULE_FIRMWARE(FIRMWARE_8168E_3);
824 MODULE_FIRMWARE(FIRMWARE_8105E_1);
825 MODULE_FIRMWARE(FIRMWARE_8168F_1);
826 MODULE_FIRMWARE(FIRMWARE_8168F_2);
827 MODULE_FIRMWARE(FIRMWARE_8402_1);
828 MODULE_FIRMWARE(FIRMWARE_8411_1);
829 MODULE_FIRMWARE(FIRMWARE_8106E_1);
830 MODULE_FIRMWARE(FIRMWARE_8106E_2);
831 MODULE_FIRMWARE(FIRMWARE_8168G_2);
832 MODULE_FIRMWARE(FIRMWARE_8168G_3);
833
834 static void rtl_lock_work(struct rtl8169_private *tp)
835 {
836 mutex_lock(&tp->wk.mutex);
837 }
838
839 static void rtl_unlock_work(struct rtl8169_private *tp)
840 {
841 mutex_unlock(&tp->wk.mutex);
842 }
843
844 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
845 {
846 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
847 PCI_EXP_DEVCTL_READRQ, force);
848 }
849
850 struct rtl_cond {
851 bool (*check)(struct rtl8169_private *);
852 const char *msg;
853 };
854
855 static void rtl_udelay(unsigned int d)
856 {
857 udelay(d);
858 }
859
860 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
861 void (*delay)(unsigned int), unsigned int d, int n,
862 bool high)
863 {
864 int i;
865
866 for (i = 0; i < n; i++) {
867 delay(d);
868 if (c->check(tp) == high)
869 return true;
870 }
871 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
872 c->msg, !high, n, d);
873 return false;
874 }
875
876 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
877 const struct rtl_cond *c,
878 unsigned int d, int n)
879 {
880 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
881 }
882
883 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
884 const struct rtl_cond *c,
885 unsigned int d, int n)
886 {
887 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
888 }
889
890 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
891 const struct rtl_cond *c,
892 unsigned int d, int n)
893 {
894 return rtl_loop_wait(tp, c, msleep, d, n, true);
895 }
896
897 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
898 const struct rtl_cond *c,
899 unsigned int d, int n)
900 {
901 return rtl_loop_wait(tp, c, msleep, d, n, false);
902 }
903
904 #define DECLARE_RTL_COND(name) \
905 static bool name ## _check(struct rtl8169_private *); \
906 \
907 static const struct rtl_cond name = { \
908 .check = name ## _check, \
909 .msg = #name \
910 }; \
911 \
912 static bool name ## _check(struct rtl8169_private *tp)
913
914 DECLARE_RTL_COND(rtl_ocpar_cond)
915 {
916 void __iomem *ioaddr = tp->mmio_addr;
917
918 return RTL_R32(OCPAR) & OCPAR_FLAG;
919 }
920
921 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
922 {
923 void __iomem *ioaddr = tp->mmio_addr;
924
925 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
926
927 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
928 RTL_R32(OCPDR) : ~0;
929 }
930
931 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
932 {
933 void __iomem *ioaddr = tp->mmio_addr;
934
935 RTL_W32(OCPDR, data);
936 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
937
938 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
939 }
940
941 DECLARE_RTL_COND(rtl_eriar_cond)
942 {
943 void __iomem *ioaddr = tp->mmio_addr;
944
945 return RTL_R32(ERIAR) & ERIAR_FLAG;
946 }
947
948 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
949 {
950 void __iomem *ioaddr = tp->mmio_addr;
951
952 RTL_W8(ERIDR, cmd);
953 RTL_W32(ERIAR, 0x800010e8);
954 msleep(2);
955
956 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
957 return;
958
959 ocp_write(tp, 0x1, 0x30, 0x00000001);
960 }
961
962 #define OOB_CMD_RESET 0x00
963 #define OOB_CMD_DRIVER_START 0x05
964 #define OOB_CMD_DRIVER_STOP 0x06
965
966 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
967 {
968 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
969 }
970
971 DECLARE_RTL_COND(rtl_ocp_read_cond)
972 {
973 u16 reg;
974
975 reg = rtl8168_get_ocp_reg(tp);
976
977 return ocp_read(tp, 0x0f, reg) & 0x00000800;
978 }
979
980 static void rtl8168_driver_start(struct rtl8169_private *tp)
981 {
982 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
983
984 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
985 }
986
987 static void rtl8168_driver_stop(struct rtl8169_private *tp)
988 {
989 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
990
991 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
992 }
993
994 static int r8168dp_check_dash(struct rtl8169_private *tp)
995 {
996 u16 reg = rtl8168_get_ocp_reg(tp);
997
998 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
999 }
1000
1001 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
1002 {
1003 if (reg & 0xffff0001) {
1004 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
1005 return true;
1006 }
1007 return false;
1008 }
1009
1010 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1011 {
1012 void __iomem *ioaddr = tp->mmio_addr;
1013
1014 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1015 }
1016
1017 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1018 {
1019 void __iomem *ioaddr = tp->mmio_addr;
1020
1021 if (rtl_ocp_reg_failure(tp, reg))
1022 return;
1023
1024 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1025
1026 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1027 }
1028
1029 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1030 {
1031 void __iomem *ioaddr = tp->mmio_addr;
1032
1033 if (rtl_ocp_reg_failure(tp, reg))
1034 return 0;
1035
1036 RTL_W32(GPHY_OCP, reg << 15);
1037
1038 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1039 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1040 }
1041
1042 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1043 {
1044 void __iomem *ioaddr = tp->mmio_addr;
1045
1046 if (rtl_ocp_reg_failure(tp, reg))
1047 return;
1048
1049 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1050 }
1051
1052 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1053 {
1054 void __iomem *ioaddr = tp->mmio_addr;
1055
1056 if (rtl_ocp_reg_failure(tp, reg))
1057 return 0;
1058
1059 RTL_W32(OCPDR, reg << 15);
1060
1061 return RTL_R32(OCPDR);
1062 }
1063
1064 #define OCP_STD_PHY_BASE 0xa400
1065
1066 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1067 {
1068 if (reg == 0x1f) {
1069 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1070 return;
1071 }
1072
1073 if (tp->ocp_base != OCP_STD_PHY_BASE)
1074 reg -= 0x10;
1075
1076 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1077 }
1078
1079 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1080 {
1081 if (tp->ocp_base != OCP_STD_PHY_BASE)
1082 reg -= 0x10;
1083
1084 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1085 }
1086
1087 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1088 {
1089 if (reg == 0x1f) {
1090 tp->ocp_base = value << 4;
1091 return;
1092 }
1093
1094 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1095 }
1096
1097 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1098 {
1099 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1100 }
1101
1102 DECLARE_RTL_COND(rtl_phyar_cond)
1103 {
1104 void __iomem *ioaddr = tp->mmio_addr;
1105
1106 return RTL_R32(PHYAR) & 0x80000000;
1107 }
1108
1109 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1110 {
1111 void __iomem *ioaddr = tp->mmio_addr;
1112
1113 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1114
1115 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1116 /*
1117 * According to hardware specs a 20us delay is required after write
1118 * complete indication, but before sending next command.
1119 */
1120 udelay(20);
1121 }
1122
1123 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1124 {
1125 void __iomem *ioaddr = tp->mmio_addr;
1126 int value;
1127
1128 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1129
1130 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1131 RTL_R32(PHYAR) & 0xffff : ~0;
1132
1133 /*
1134 * According to hardware specs a 20us delay is required after read
1135 * complete indication, but before sending next command.
1136 */
1137 udelay(20);
1138
1139 return value;
1140 }
1141
1142 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1143 {
1144 void __iomem *ioaddr = tp->mmio_addr;
1145
1146 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1147 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1148 RTL_W32(EPHY_RXER_NUM, 0);
1149
1150 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1151 }
1152
1153 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1154 {
1155 r8168dp_1_mdio_access(tp, reg,
1156 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1157 }
1158
1159 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1160 {
1161 void __iomem *ioaddr = tp->mmio_addr;
1162
1163 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1164
1165 mdelay(1);
1166 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1167 RTL_W32(EPHY_RXER_NUM, 0);
1168
1169 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1170 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1171 }
1172
1173 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1174
1175 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1176 {
1177 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1178 }
1179
1180 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1181 {
1182 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1183 }
1184
1185 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1186 {
1187 void __iomem *ioaddr = tp->mmio_addr;
1188
1189 r8168dp_2_mdio_start(ioaddr);
1190
1191 r8169_mdio_write(tp, reg, value);
1192
1193 r8168dp_2_mdio_stop(ioaddr);
1194 }
1195
1196 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1197 {
1198 void __iomem *ioaddr = tp->mmio_addr;
1199 int value;
1200
1201 r8168dp_2_mdio_start(ioaddr);
1202
1203 value = r8169_mdio_read(tp, reg);
1204
1205 r8168dp_2_mdio_stop(ioaddr);
1206
1207 return value;
1208 }
1209
1210 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1211 {
1212 tp->mdio_ops.write(tp, location, val);
1213 }
1214
1215 static int rtl_readphy(struct rtl8169_private *tp, int location)
1216 {
1217 return tp->mdio_ops.read(tp, location);
1218 }
1219
1220 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1221 {
1222 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1223 }
1224
1225 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1226 {
1227 int val;
1228
1229 val = rtl_readphy(tp, reg_addr);
1230 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1231 }
1232
1233 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1234 int val)
1235 {
1236 struct rtl8169_private *tp = netdev_priv(dev);
1237
1238 rtl_writephy(tp, location, val);
1239 }
1240
1241 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1242 {
1243 struct rtl8169_private *tp = netdev_priv(dev);
1244
1245 return rtl_readphy(tp, location);
1246 }
1247
1248 DECLARE_RTL_COND(rtl_ephyar_cond)
1249 {
1250 void __iomem *ioaddr = tp->mmio_addr;
1251
1252 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1253 }
1254
1255 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1256 {
1257 void __iomem *ioaddr = tp->mmio_addr;
1258
1259 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1260 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1261
1262 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1263
1264 udelay(10);
1265 }
1266
1267 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1268 {
1269 void __iomem *ioaddr = tp->mmio_addr;
1270
1271 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1272
1273 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1274 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1275 }
1276
1277 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1278 u32 val, int type)
1279 {
1280 void __iomem *ioaddr = tp->mmio_addr;
1281
1282 BUG_ON((addr & 3) || (mask == 0));
1283 RTL_W32(ERIDR, val);
1284 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1285
1286 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1287 }
1288
1289 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1290 {
1291 void __iomem *ioaddr = tp->mmio_addr;
1292
1293 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1294
1295 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1296 RTL_R32(ERIDR) : ~0;
1297 }
1298
1299 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1300 u32 m, int type)
1301 {
1302 u32 val;
1303
1304 val = rtl_eri_read(tp, addr, type);
1305 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1306 }
1307
1308 struct exgmac_reg {
1309 u16 addr;
1310 u16 mask;
1311 u32 val;
1312 };
1313
1314 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1315 const struct exgmac_reg *r, int len)
1316 {
1317 while (len-- > 0) {
1318 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1319 r++;
1320 }
1321 }
1322
1323 DECLARE_RTL_COND(rtl_efusear_cond)
1324 {
1325 void __iomem *ioaddr = tp->mmio_addr;
1326
1327 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1328 }
1329
1330 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1331 {
1332 void __iomem *ioaddr = tp->mmio_addr;
1333
1334 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1335
1336 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1337 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1338 }
1339
1340 static u16 rtl_get_events(struct rtl8169_private *tp)
1341 {
1342 void __iomem *ioaddr = tp->mmio_addr;
1343
1344 return RTL_R16(IntrStatus);
1345 }
1346
1347 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1348 {
1349 void __iomem *ioaddr = tp->mmio_addr;
1350
1351 RTL_W16(IntrStatus, bits);
1352 mmiowb();
1353 }
1354
1355 static void rtl_irq_disable(struct rtl8169_private *tp)
1356 {
1357 void __iomem *ioaddr = tp->mmio_addr;
1358
1359 RTL_W16(IntrMask, 0);
1360 mmiowb();
1361 }
1362
1363 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1364 {
1365 void __iomem *ioaddr = tp->mmio_addr;
1366
1367 RTL_W16(IntrMask, bits);
1368 }
1369
1370 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1371 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1372 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1373
1374 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1375 {
1376 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1377 }
1378
1379 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1380 {
1381 void __iomem *ioaddr = tp->mmio_addr;
1382
1383 rtl_irq_disable(tp);
1384 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1385 RTL_R8(ChipCmd);
1386 }
1387
1388 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1389 {
1390 void __iomem *ioaddr = tp->mmio_addr;
1391
1392 return RTL_R32(TBICSR) & TBIReset;
1393 }
1394
1395 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1396 {
1397 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1398 }
1399
1400 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1401 {
1402 return RTL_R32(TBICSR) & TBILinkOk;
1403 }
1404
1405 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1406 {
1407 return RTL_R8(PHYstatus) & LinkStatus;
1408 }
1409
1410 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1411 {
1412 void __iomem *ioaddr = tp->mmio_addr;
1413
1414 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1415 }
1416
1417 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1418 {
1419 unsigned int val;
1420
1421 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1422 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1423 }
1424
1425 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1426 {
1427 void __iomem *ioaddr = tp->mmio_addr;
1428 struct net_device *dev = tp->dev;
1429
1430 if (!netif_running(dev))
1431 return;
1432
1433 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1434 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1435 if (RTL_R8(PHYstatus) & _1000bpsF) {
1436 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1437 ERIAR_EXGMAC);
1438 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1439 ERIAR_EXGMAC);
1440 } else if (RTL_R8(PHYstatus) & _100bps) {
1441 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1442 ERIAR_EXGMAC);
1443 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1444 ERIAR_EXGMAC);
1445 } else {
1446 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1447 ERIAR_EXGMAC);
1448 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1449 ERIAR_EXGMAC);
1450 }
1451 /* Reset packet filter */
1452 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1453 ERIAR_EXGMAC);
1454 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1455 ERIAR_EXGMAC);
1456 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1457 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1458 if (RTL_R8(PHYstatus) & _1000bpsF) {
1459 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1460 ERIAR_EXGMAC);
1461 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1462 ERIAR_EXGMAC);
1463 } else {
1464 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1465 ERIAR_EXGMAC);
1466 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1467 ERIAR_EXGMAC);
1468 }
1469 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1470 if (RTL_R8(PHYstatus) & _10bps) {
1471 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1472 ERIAR_EXGMAC);
1473 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1474 ERIAR_EXGMAC);
1475 } else {
1476 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1477 ERIAR_EXGMAC);
1478 }
1479 }
1480 }
1481
1482 static void __rtl8169_check_link_status(struct net_device *dev,
1483 struct rtl8169_private *tp,
1484 void __iomem *ioaddr, bool pm)
1485 {
1486 if (tp->link_ok(ioaddr)) {
1487 rtl_link_chg_patch(tp);
1488 /* This is to cancel a scheduled suspend if there's one. */
1489 if (pm)
1490 pm_request_resume(&tp->pci_dev->dev);
1491 netif_carrier_on(dev);
1492 if (net_ratelimit())
1493 netif_info(tp, ifup, dev, "link up\n");
1494 } else {
1495 netif_carrier_off(dev);
1496 netif_info(tp, ifdown, dev, "link down\n");
1497 if (pm)
1498 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1499 }
1500 }
1501
1502 static void rtl8169_check_link_status(struct net_device *dev,
1503 struct rtl8169_private *tp,
1504 void __iomem *ioaddr)
1505 {
1506 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1507 }
1508
1509 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1510
1511 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1512 {
1513 void __iomem *ioaddr = tp->mmio_addr;
1514 u8 options;
1515 u32 wolopts = 0;
1516
1517 options = RTL_R8(Config1);
1518 if (!(options & PMEnable))
1519 return 0;
1520
1521 options = RTL_R8(Config3);
1522 if (options & LinkUp)
1523 wolopts |= WAKE_PHY;
1524 if (options & MagicPacket)
1525 wolopts |= WAKE_MAGIC;
1526
1527 options = RTL_R8(Config5);
1528 if (options & UWF)
1529 wolopts |= WAKE_UCAST;
1530 if (options & BWF)
1531 wolopts |= WAKE_BCAST;
1532 if (options & MWF)
1533 wolopts |= WAKE_MCAST;
1534
1535 return wolopts;
1536 }
1537
1538 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1539 {
1540 struct rtl8169_private *tp = netdev_priv(dev);
1541
1542 rtl_lock_work(tp);
1543
1544 wol->supported = WAKE_ANY;
1545 wol->wolopts = __rtl8169_get_wol(tp);
1546
1547 rtl_unlock_work(tp);
1548 }
1549
1550 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1551 {
1552 void __iomem *ioaddr = tp->mmio_addr;
1553 unsigned int i;
1554 static const struct {
1555 u32 opt;
1556 u16 reg;
1557 u8 mask;
1558 } cfg[] = {
1559 { WAKE_PHY, Config3, LinkUp },
1560 { WAKE_MAGIC, Config3, MagicPacket },
1561 { WAKE_UCAST, Config5, UWF },
1562 { WAKE_BCAST, Config5, BWF },
1563 { WAKE_MCAST, Config5, MWF },
1564 { WAKE_ANY, Config5, LanWake }
1565 };
1566 u8 options;
1567
1568 RTL_W8(Cfg9346, Cfg9346_Unlock);
1569
1570 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1571 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1572 if (wolopts & cfg[i].opt)
1573 options |= cfg[i].mask;
1574 RTL_W8(cfg[i].reg, options);
1575 }
1576
1577 switch (tp->mac_version) {
1578 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1579 options = RTL_R8(Config1) & ~PMEnable;
1580 if (wolopts)
1581 options |= PMEnable;
1582 RTL_W8(Config1, options);
1583 break;
1584 default:
1585 options = RTL_R8(Config2) & ~PME_SIGNAL;
1586 if (wolopts)
1587 options |= PME_SIGNAL;
1588 RTL_W8(Config2, options);
1589 break;
1590 }
1591
1592 RTL_W8(Cfg9346, Cfg9346_Lock);
1593 }
1594
1595 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1596 {
1597 struct rtl8169_private *tp = netdev_priv(dev);
1598
1599 rtl_lock_work(tp);
1600
1601 if (wol->wolopts)
1602 tp->features |= RTL_FEATURE_WOL;
1603 else
1604 tp->features &= ~RTL_FEATURE_WOL;
1605 __rtl8169_set_wol(tp, wol->wolopts);
1606
1607 rtl_unlock_work(tp);
1608
1609 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1610
1611 return 0;
1612 }
1613
1614 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1615 {
1616 return rtl_chip_infos[tp->mac_version].fw_name;
1617 }
1618
1619 static void rtl8169_get_drvinfo(struct net_device *dev,
1620 struct ethtool_drvinfo *info)
1621 {
1622 struct rtl8169_private *tp = netdev_priv(dev);
1623 struct rtl_fw *rtl_fw = tp->rtl_fw;
1624
1625 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1626 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1627 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1628 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1629 if (!IS_ERR_OR_NULL(rtl_fw))
1630 strlcpy(info->fw_version, rtl_fw->version,
1631 sizeof(info->fw_version));
1632 }
1633
1634 static int rtl8169_get_regs_len(struct net_device *dev)
1635 {
1636 return R8169_REGS_SIZE;
1637 }
1638
1639 static int rtl8169_set_speed_tbi(struct net_device *dev,
1640 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1641 {
1642 struct rtl8169_private *tp = netdev_priv(dev);
1643 void __iomem *ioaddr = tp->mmio_addr;
1644 int ret = 0;
1645 u32 reg;
1646
1647 reg = RTL_R32(TBICSR);
1648 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1649 (duplex == DUPLEX_FULL)) {
1650 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1651 } else if (autoneg == AUTONEG_ENABLE)
1652 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1653 else {
1654 netif_warn(tp, link, dev,
1655 "incorrect speed setting refused in TBI mode\n");
1656 ret = -EOPNOTSUPP;
1657 }
1658
1659 return ret;
1660 }
1661
1662 static int rtl8169_set_speed_xmii(struct net_device *dev,
1663 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1664 {
1665 struct rtl8169_private *tp = netdev_priv(dev);
1666 int giga_ctrl, bmcr;
1667 int rc = -EINVAL;
1668
1669 rtl_writephy(tp, 0x1f, 0x0000);
1670
1671 if (autoneg == AUTONEG_ENABLE) {
1672 int auto_nego;
1673
1674 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1675 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1676 ADVERTISE_100HALF | ADVERTISE_100FULL);
1677
1678 if (adv & ADVERTISED_10baseT_Half)
1679 auto_nego |= ADVERTISE_10HALF;
1680 if (adv & ADVERTISED_10baseT_Full)
1681 auto_nego |= ADVERTISE_10FULL;
1682 if (adv & ADVERTISED_100baseT_Half)
1683 auto_nego |= ADVERTISE_100HALF;
1684 if (adv & ADVERTISED_100baseT_Full)
1685 auto_nego |= ADVERTISE_100FULL;
1686
1687 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1688
1689 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1690 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1691
1692 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1693 if (tp->mii.supports_gmii) {
1694 if (adv & ADVERTISED_1000baseT_Half)
1695 giga_ctrl |= ADVERTISE_1000HALF;
1696 if (adv & ADVERTISED_1000baseT_Full)
1697 giga_ctrl |= ADVERTISE_1000FULL;
1698 } else if (adv & (ADVERTISED_1000baseT_Half |
1699 ADVERTISED_1000baseT_Full)) {
1700 netif_info(tp, link, dev,
1701 "PHY does not support 1000Mbps\n");
1702 goto out;
1703 }
1704
1705 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1706
1707 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1708 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1709 } else {
1710 giga_ctrl = 0;
1711
1712 if (speed == SPEED_10)
1713 bmcr = 0;
1714 else if (speed == SPEED_100)
1715 bmcr = BMCR_SPEED100;
1716 else
1717 goto out;
1718
1719 if (duplex == DUPLEX_FULL)
1720 bmcr |= BMCR_FULLDPLX;
1721 }
1722
1723 rtl_writephy(tp, MII_BMCR, bmcr);
1724
1725 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1726 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1727 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1728 rtl_writephy(tp, 0x17, 0x2138);
1729 rtl_writephy(tp, 0x0e, 0x0260);
1730 } else {
1731 rtl_writephy(tp, 0x17, 0x2108);
1732 rtl_writephy(tp, 0x0e, 0x0000);
1733 }
1734 }
1735
1736 rc = 0;
1737 out:
1738 return rc;
1739 }
1740
1741 static int rtl8169_set_speed(struct net_device *dev,
1742 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1743 {
1744 struct rtl8169_private *tp = netdev_priv(dev);
1745 int ret;
1746
1747 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1748 if (ret < 0)
1749 goto out;
1750
1751 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1752 (advertising & ADVERTISED_1000baseT_Full)) {
1753 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1754 }
1755 out:
1756 return ret;
1757 }
1758
1759 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1760 {
1761 struct rtl8169_private *tp = netdev_priv(dev);
1762 int ret;
1763
1764 del_timer_sync(&tp->timer);
1765
1766 rtl_lock_work(tp);
1767 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1768 cmd->duplex, cmd->advertising);
1769 rtl_unlock_work(tp);
1770
1771 return ret;
1772 }
1773
1774 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1775 netdev_features_t features)
1776 {
1777 struct rtl8169_private *tp = netdev_priv(dev);
1778
1779 if (dev->mtu > TD_MSS_MAX)
1780 features &= ~NETIF_F_ALL_TSO;
1781
1782 if (dev->mtu > JUMBO_1K &&
1783 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1784 features &= ~NETIF_F_IP_CSUM;
1785
1786 return features;
1787 }
1788
1789 static void __rtl8169_set_features(struct net_device *dev,
1790 netdev_features_t features)
1791 {
1792 struct rtl8169_private *tp = netdev_priv(dev);
1793 netdev_features_t changed = features ^ dev->features;
1794 void __iomem *ioaddr = tp->mmio_addr;
1795
1796 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM |
1797 NETIF_F_HW_VLAN_CTAG_RX)))
1798 return;
1799
1800 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) {
1801 if (features & NETIF_F_RXCSUM)
1802 tp->cp_cmd |= RxChkSum;
1803 else
1804 tp->cp_cmd &= ~RxChkSum;
1805
1806 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
1807 tp->cp_cmd |= RxVlan;
1808 else
1809 tp->cp_cmd &= ~RxVlan;
1810
1811 RTL_W16(CPlusCmd, tp->cp_cmd);
1812 RTL_R16(CPlusCmd);
1813 }
1814 if (changed & NETIF_F_RXALL) {
1815 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1816 if (features & NETIF_F_RXALL)
1817 tmp |= (AcceptErr | AcceptRunt);
1818 RTL_W32(RxConfig, tmp);
1819 }
1820 }
1821
1822 static int rtl8169_set_features(struct net_device *dev,
1823 netdev_features_t features)
1824 {
1825 struct rtl8169_private *tp = netdev_priv(dev);
1826
1827 rtl_lock_work(tp);
1828 __rtl8169_set_features(dev, features);
1829 rtl_unlock_work(tp);
1830
1831 return 0;
1832 }
1833
1834
1835 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1836 {
1837 return (vlan_tx_tag_present(skb)) ?
1838 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1839 }
1840
1841 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1842 {
1843 u32 opts2 = le32_to_cpu(desc->opts2);
1844
1845 if (opts2 & RxVlanTag)
1846 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1847 }
1848
1849 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1850 {
1851 struct rtl8169_private *tp = netdev_priv(dev);
1852 void __iomem *ioaddr = tp->mmio_addr;
1853 u32 status;
1854
1855 cmd->supported =
1856 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1857 cmd->port = PORT_FIBRE;
1858 cmd->transceiver = XCVR_INTERNAL;
1859
1860 status = RTL_R32(TBICSR);
1861 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1862 cmd->autoneg = !!(status & TBINwEnable);
1863
1864 ethtool_cmd_speed_set(cmd, SPEED_1000);
1865 cmd->duplex = DUPLEX_FULL; /* Always set */
1866
1867 return 0;
1868 }
1869
1870 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1871 {
1872 struct rtl8169_private *tp = netdev_priv(dev);
1873
1874 return mii_ethtool_gset(&tp->mii, cmd);
1875 }
1876
1877 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1878 {
1879 struct rtl8169_private *tp = netdev_priv(dev);
1880 int rc;
1881
1882 rtl_lock_work(tp);
1883 rc = tp->get_settings(dev, cmd);
1884 rtl_unlock_work(tp);
1885
1886 return rc;
1887 }
1888
1889 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1890 void *p)
1891 {
1892 struct rtl8169_private *tp = netdev_priv(dev);
1893
1894 if (regs->len > R8169_REGS_SIZE)
1895 regs->len = R8169_REGS_SIZE;
1896
1897 rtl_lock_work(tp);
1898 memcpy_fromio(p, tp->mmio_addr, regs->len);
1899 rtl_unlock_work(tp);
1900 }
1901
1902 static u32 rtl8169_get_msglevel(struct net_device *dev)
1903 {
1904 struct rtl8169_private *tp = netdev_priv(dev);
1905
1906 return tp->msg_enable;
1907 }
1908
1909 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1910 {
1911 struct rtl8169_private *tp = netdev_priv(dev);
1912
1913 tp->msg_enable = value;
1914 }
1915
1916 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1917 "tx_packets",
1918 "rx_packets",
1919 "tx_errors",
1920 "rx_errors",
1921 "rx_missed",
1922 "align_errors",
1923 "tx_single_collisions",
1924 "tx_multi_collisions",
1925 "unicast",
1926 "broadcast",
1927 "multicast",
1928 "tx_aborted",
1929 "tx_underrun",
1930 };
1931
1932 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1933 {
1934 switch (sset) {
1935 case ETH_SS_STATS:
1936 return ARRAY_SIZE(rtl8169_gstrings);
1937 default:
1938 return -EOPNOTSUPP;
1939 }
1940 }
1941
1942 DECLARE_RTL_COND(rtl_counters_cond)
1943 {
1944 void __iomem *ioaddr = tp->mmio_addr;
1945
1946 return RTL_R32(CounterAddrLow) & CounterDump;
1947 }
1948
1949 static void rtl8169_update_counters(struct net_device *dev)
1950 {
1951 struct rtl8169_private *tp = netdev_priv(dev);
1952 void __iomem *ioaddr = tp->mmio_addr;
1953 struct device *d = &tp->pci_dev->dev;
1954 struct rtl8169_counters *counters;
1955 dma_addr_t paddr;
1956 u32 cmd;
1957
1958 /*
1959 * Some chips are unable to dump tally counters when the receiver
1960 * is disabled.
1961 */
1962 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1963 return;
1964
1965 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1966 if (!counters)
1967 return;
1968
1969 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1970 cmd = (u64)paddr & DMA_BIT_MASK(32);
1971 RTL_W32(CounterAddrLow, cmd);
1972 RTL_W32(CounterAddrLow, cmd | CounterDump);
1973
1974 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1975 memcpy(&tp->counters, counters, sizeof(*counters));
1976
1977 RTL_W32(CounterAddrLow, 0);
1978 RTL_W32(CounterAddrHigh, 0);
1979
1980 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1981 }
1982
1983 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1984 struct ethtool_stats *stats, u64 *data)
1985 {
1986 struct rtl8169_private *tp = netdev_priv(dev);
1987
1988 ASSERT_RTNL();
1989
1990 rtl8169_update_counters(dev);
1991
1992 data[0] = le64_to_cpu(tp->counters.tx_packets);
1993 data[1] = le64_to_cpu(tp->counters.rx_packets);
1994 data[2] = le64_to_cpu(tp->counters.tx_errors);
1995 data[3] = le32_to_cpu(tp->counters.rx_errors);
1996 data[4] = le16_to_cpu(tp->counters.rx_missed);
1997 data[5] = le16_to_cpu(tp->counters.align_errors);
1998 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1999 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2000 data[8] = le64_to_cpu(tp->counters.rx_unicast);
2001 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2002 data[10] = le32_to_cpu(tp->counters.rx_multicast);
2003 data[11] = le16_to_cpu(tp->counters.tx_aborted);
2004 data[12] = le16_to_cpu(tp->counters.tx_underun);
2005 }
2006
2007 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2008 {
2009 switch(stringset) {
2010 case ETH_SS_STATS:
2011 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2012 break;
2013 }
2014 }
2015
2016 static const struct ethtool_ops rtl8169_ethtool_ops = {
2017 .get_drvinfo = rtl8169_get_drvinfo,
2018 .get_regs_len = rtl8169_get_regs_len,
2019 .get_link = ethtool_op_get_link,
2020 .get_settings = rtl8169_get_settings,
2021 .set_settings = rtl8169_set_settings,
2022 .get_msglevel = rtl8169_get_msglevel,
2023 .set_msglevel = rtl8169_set_msglevel,
2024 .get_regs = rtl8169_get_regs,
2025 .get_wol = rtl8169_get_wol,
2026 .set_wol = rtl8169_set_wol,
2027 .get_strings = rtl8169_get_strings,
2028 .get_sset_count = rtl8169_get_sset_count,
2029 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2030 .get_ts_info = ethtool_op_get_ts_info,
2031 };
2032
2033 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2034 struct net_device *dev, u8 default_version)
2035 {
2036 void __iomem *ioaddr = tp->mmio_addr;
2037 /*
2038 * The driver currently handles the 8168Bf and the 8168Be identically
2039 * but they can be identified more specifically through the test below
2040 * if needed:
2041 *
2042 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2043 *
2044 * Same thing for the 8101Eb and the 8101Ec:
2045 *
2046 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2047 */
2048 static const struct rtl_mac_info {
2049 u32 mask;
2050 u32 val;
2051 int mac_version;
2052 } mac_info[] = {
2053 /* 8168G family. */
2054 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2055 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2056 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2057
2058 /* 8168F family. */
2059 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2060 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2061 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2062
2063 /* 8168E family. */
2064 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2065 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2066 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2067 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2068
2069 /* 8168D family. */
2070 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2071 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2072 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2073
2074 /* 8168DP family. */
2075 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2076 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2077 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2078
2079 /* 8168C family. */
2080 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2081 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2082 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2083 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2084 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2085 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2086 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2087 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2088 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2089
2090 /* 8168B family. */
2091 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2092 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2093 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2094 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2095
2096 /* 8101 family. */
2097 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2098 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2099 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2100 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2101 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2102 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2103 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2104 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2105 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2106 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2107 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2108 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2109 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2110 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2111 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2112 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2113 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2114 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2115 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2116 /* FIXME: where did these entries come from ? -- FR */
2117 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2118 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2119
2120 /* 8110 family. */
2121 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2122 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2123 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2124 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2125 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2126 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2127
2128 /* Catch-all */
2129 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2130 };
2131 const struct rtl_mac_info *p = mac_info;
2132 u32 reg;
2133
2134 reg = RTL_R32(TxConfig);
2135 while ((reg & p->mask) != p->val)
2136 p++;
2137 tp->mac_version = p->mac_version;
2138
2139 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2140 netif_notice(tp, probe, dev,
2141 "unknown MAC, using family default\n");
2142 tp->mac_version = default_version;
2143 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2144 tp->mac_version = tp->mii.supports_gmii ?
2145 RTL_GIGA_MAC_VER_42 :
2146 RTL_GIGA_MAC_VER_43;
2147 }
2148 }
2149
2150 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2151 {
2152 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2153 }
2154
2155 struct phy_reg {
2156 u16 reg;
2157 u16 val;
2158 };
2159
2160 static void rtl_writephy_batch(struct rtl8169_private *tp,
2161 const struct phy_reg *regs, int len)
2162 {
2163 while (len-- > 0) {
2164 rtl_writephy(tp, regs->reg, regs->val);
2165 regs++;
2166 }
2167 }
2168
2169 #define PHY_READ 0x00000000
2170 #define PHY_DATA_OR 0x10000000
2171 #define PHY_DATA_AND 0x20000000
2172 #define PHY_BJMPN 0x30000000
2173 #define PHY_MDIO_CHG 0x40000000
2174 #define PHY_CLEAR_READCOUNT 0x70000000
2175 #define PHY_WRITE 0x80000000
2176 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2177 #define PHY_COMP_EQ_SKIPN 0xa0000000
2178 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2179 #define PHY_WRITE_PREVIOUS 0xc0000000
2180 #define PHY_SKIPN 0xd0000000
2181 #define PHY_DELAY_MS 0xe0000000
2182
2183 struct fw_info {
2184 u32 magic;
2185 char version[RTL_VER_SIZE];
2186 __le32 fw_start;
2187 __le32 fw_len;
2188 u8 chksum;
2189 } __packed;
2190
2191 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2192
2193 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2194 {
2195 const struct firmware *fw = rtl_fw->fw;
2196 struct fw_info *fw_info = (struct fw_info *)fw->data;
2197 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2198 char *version = rtl_fw->version;
2199 bool rc = false;
2200
2201 if (fw->size < FW_OPCODE_SIZE)
2202 goto out;
2203
2204 if (!fw_info->magic) {
2205 size_t i, size, start;
2206 u8 checksum = 0;
2207
2208 if (fw->size < sizeof(*fw_info))
2209 goto out;
2210
2211 for (i = 0; i < fw->size; i++)
2212 checksum += fw->data[i];
2213 if (checksum != 0)
2214 goto out;
2215
2216 start = le32_to_cpu(fw_info->fw_start);
2217 if (start > fw->size)
2218 goto out;
2219
2220 size = le32_to_cpu(fw_info->fw_len);
2221 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2222 goto out;
2223
2224 memcpy(version, fw_info->version, RTL_VER_SIZE);
2225
2226 pa->code = (__le32 *)(fw->data + start);
2227 pa->size = size;
2228 } else {
2229 if (fw->size % FW_OPCODE_SIZE)
2230 goto out;
2231
2232 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2233
2234 pa->code = (__le32 *)fw->data;
2235 pa->size = fw->size / FW_OPCODE_SIZE;
2236 }
2237 version[RTL_VER_SIZE - 1] = 0;
2238
2239 rc = true;
2240 out:
2241 return rc;
2242 }
2243
2244 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2245 struct rtl_fw_phy_action *pa)
2246 {
2247 bool rc = false;
2248 size_t index;
2249
2250 for (index = 0; index < pa->size; index++) {
2251 u32 action = le32_to_cpu(pa->code[index]);
2252 u32 regno = (action & 0x0fff0000) >> 16;
2253
2254 switch(action & 0xf0000000) {
2255 case PHY_READ:
2256 case PHY_DATA_OR:
2257 case PHY_DATA_AND:
2258 case PHY_MDIO_CHG:
2259 case PHY_CLEAR_READCOUNT:
2260 case PHY_WRITE:
2261 case PHY_WRITE_PREVIOUS:
2262 case PHY_DELAY_MS:
2263 break;
2264
2265 case PHY_BJMPN:
2266 if (regno > index) {
2267 netif_err(tp, ifup, tp->dev,
2268 "Out of range of firmware\n");
2269 goto out;
2270 }
2271 break;
2272 case PHY_READCOUNT_EQ_SKIP:
2273 if (index + 2 >= pa->size) {
2274 netif_err(tp, ifup, tp->dev,
2275 "Out of range of firmware\n");
2276 goto out;
2277 }
2278 break;
2279 case PHY_COMP_EQ_SKIPN:
2280 case PHY_COMP_NEQ_SKIPN:
2281 case PHY_SKIPN:
2282 if (index + 1 + regno >= pa->size) {
2283 netif_err(tp, ifup, tp->dev,
2284 "Out of range of firmware\n");
2285 goto out;
2286 }
2287 break;
2288
2289 default:
2290 netif_err(tp, ifup, tp->dev,
2291 "Invalid action 0x%08x\n", action);
2292 goto out;
2293 }
2294 }
2295 rc = true;
2296 out:
2297 return rc;
2298 }
2299
2300 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2301 {
2302 struct net_device *dev = tp->dev;
2303 int rc = -EINVAL;
2304
2305 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2306 netif_err(tp, ifup, dev, "invalid firwmare\n");
2307 goto out;
2308 }
2309
2310 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2311 rc = 0;
2312 out:
2313 return rc;
2314 }
2315
2316 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2317 {
2318 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2319 struct mdio_ops org, *ops = &tp->mdio_ops;
2320 u32 predata, count;
2321 size_t index;
2322
2323 predata = count = 0;
2324 org.write = ops->write;
2325 org.read = ops->read;
2326
2327 for (index = 0; index < pa->size; ) {
2328 u32 action = le32_to_cpu(pa->code[index]);
2329 u32 data = action & 0x0000ffff;
2330 u32 regno = (action & 0x0fff0000) >> 16;
2331
2332 if (!action)
2333 break;
2334
2335 switch(action & 0xf0000000) {
2336 case PHY_READ:
2337 predata = rtl_readphy(tp, regno);
2338 count++;
2339 index++;
2340 break;
2341 case PHY_DATA_OR:
2342 predata |= data;
2343 index++;
2344 break;
2345 case PHY_DATA_AND:
2346 predata &= data;
2347 index++;
2348 break;
2349 case PHY_BJMPN:
2350 index -= regno;
2351 break;
2352 case PHY_MDIO_CHG:
2353 if (data == 0) {
2354 ops->write = org.write;
2355 ops->read = org.read;
2356 } else if (data == 1) {
2357 ops->write = mac_mcu_write;
2358 ops->read = mac_mcu_read;
2359 }
2360
2361 index++;
2362 break;
2363 case PHY_CLEAR_READCOUNT:
2364 count = 0;
2365 index++;
2366 break;
2367 case PHY_WRITE:
2368 rtl_writephy(tp, regno, data);
2369 index++;
2370 break;
2371 case PHY_READCOUNT_EQ_SKIP:
2372 index += (count == data) ? 2 : 1;
2373 break;
2374 case PHY_COMP_EQ_SKIPN:
2375 if (predata == data)
2376 index += regno;
2377 index++;
2378 break;
2379 case PHY_COMP_NEQ_SKIPN:
2380 if (predata != data)
2381 index += regno;
2382 index++;
2383 break;
2384 case PHY_WRITE_PREVIOUS:
2385 rtl_writephy(tp, regno, predata);
2386 index++;
2387 break;
2388 case PHY_SKIPN:
2389 index += regno + 1;
2390 break;
2391 case PHY_DELAY_MS:
2392 mdelay(data);
2393 index++;
2394 break;
2395
2396 default:
2397 BUG();
2398 }
2399 }
2400
2401 ops->write = org.write;
2402 ops->read = org.read;
2403 }
2404
2405 static void rtl_release_firmware(struct rtl8169_private *tp)
2406 {
2407 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2408 release_firmware(tp->rtl_fw->fw);
2409 kfree(tp->rtl_fw);
2410 }
2411 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2412 }
2413
2414 static void rtl_apply_firmware(struct rtl8169_private *tp)
2415 {
2416 struct rtl_fw *rtl_fw = tp->rtl_fw;
2417
2418 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2419 if (!IS_ERR_OR_NULL(rtl_fw))
2420 rtl_phy_write_fw(tp, rtl_fw);
2421 }
2422
2423 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2424 {
2425 if (rtl_readphy(tp, reg) != val)
2426 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2427 else
2428 rtl_apply_firmware(tp);
2429 }
2430
2431 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2432 {
2433 static const struct phy_reg phy_reg_init[] = {
2434 { 0x1f, 0x0001 },
2435 { 0x06, 0x006e },
2436 { 0x08, 0x0708 },
2437 { 0x15, 0x4000 },
2438 { 0x18, 0x65c7 },
2439
2440 { 0x1f, 0x0001 },
2441 { 0x03, 0x00a1 },
2442 { 0x02, 0x0008 },
2443 { 0x01, 0x0120 },
2444 { 0x00, 0x1000 },
2445 { 0x04, 0x0800 },
2446 { 0x04, 0x0000 },
2447
2448 { 0x03, 0xff41 },
2449 { 0x02, 0xdf60 },
2450 { 0x01, 0x0140 },
2451 { 0x00, 0x0077 },
2452 { 0x04, 0x7800 },
2453 { 0x04, 0x7000 },
2454
2455 { 0x03, 0x802f },
2456 { 0x02, 0x4f02 },
2457 { 0x01, 0x0409 },
2458 { 0x00, 0xf0f9 },
2459 { 0x04, 0x9800 },
2460 { 0x04, 0x9000 },
2461
2462 { 0x03, 0xdf01 },
2463 { 0x02, 0xdf20 },
2464 { 0x01, 0xff95 },
2465 { 0x00, 0xba00 },
2466 { 0x04, 0xa800 },
2467 { 0x04, 0xa000 },
2468
2469 { 0x03, 0xff41 },
2470 { 0x02, 0xdf20 },
2471 { 0x01, 0x0140 },
2472 { 0x00, 0x00bb },
2473 { 0x04, 0xb800 },
2474 { 0x04, 0xb000 },
2475
2476 { 0x03, 0xdf41 },
2477 { 0x02, 0xdc60 },
2478 { 0x01, 0x6340 },
2479 { 0x00, 0x007d },
2480 { 0x04, 0xd800 },
2481 { 0x04, 0xd000 },
2482
2483 { 0x03, 0xdf01 },
2484 { 0x02, 0xdf20 },
2485 { 0x01, 0x100a },
2486 { 0x00, 0xa0ff },
2487 { 0x04, 0xf800 },
2488 { 0x04, 0xf000 },
2489
2490 { 0x1f, 0x0000 },
2491 { 0x0b, 0x0000 },
2492 { 0x00, 0x9200 }
2493 };
2494
2495 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2496 }
2497
2498 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2499 {
2500 static const struct phy_reg phy_reg_init[] = {
2501 { 0x1f, 0x0002 },
2502 { 0x01, 0x90d0 },
2503 { 0x1f, 0x0000 }
2504 };
2505
2506 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2507 }
2508
2509 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2510 {
2511 struct pci_dev *pdev = tp->pci_dev;
2512
2513 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2514 (pdev->subsystem_device != 0xe000))
2515 return;
2516
2517 rtl_writephy(tp, 0x1f, 0x0001);
2518 rtl_writephy(tp, 0x10, 0xf01b);
2519 rtl_writephy(tp, 0x1f, 0x0000);
2520 }
2521
2522 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2523 {
2524 static const struct phy_reg phy_reg_init[] = {
2525 { 0x1f, 0x0001 },
2526 { 0x04, 0x0000 },
2527 { 0x03, 0x00a1 },
2528 { 0x02, 0x0008 },
2529 { 0x01, 0x0120 },
2530 { 0x00, 0x1000 },
2531 { 0x04, 0x0800 },
2532 { 0x04, 0x9000 },
2533 { 0x03, 0x802f },
2534 { 0x02, 0x4f02 },
2535 { 0x01, 0x0409 },
2536 { 0x00, 0xf099 },
2537 { 0x04, 0x9800 },
2538 { 0x04, 0xa000 },
2539 { 0x03, 0xdf01 },
2540 { 0x02, 0xdf20 },
2541 { 0x01, 0xff95 },
2542 { 0x00, 0xba00 },
2543 { 0x04, 0xa800 },
2544 { 0x04, 0xf000 },
2545 { 0x03, 0xdf01 },
2546 { 0x02, 0xdf20 },
2547 { 0x01, 0x101a },
2548 { 0x00, 0xa0ff },
2549 { 0x04, 0xf800 },
2550 { 0x04, 0x0000 },
2551 { 0x1f, 0x0000 },
2552
2553 { 0x1f, 0x0001 },
2554 { 0x10, 0xf41b },
2555 { 0x14, 0xfb54 },
2556 { 0x18, 0xf5c7 },
2557 { 0x1f, 0x0000 },
2558
2559 { 0x1f, 0x0001 },
2560 { 0x17, 0x0cc0 },
2561 { 0x1f, 0x0000 }
2562 };
2563
2564 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2565
2566 rtl8169scd_hw_phy_config_quirk(tp);
2567 }
2568
2569 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2570 {
2571 static const struct phy_reg phy_reg_init[] = {
2572 { 0x1f, 0x0001 },
2573 { 0x04, 0x0000 },
2574 { 0x03, 0x00a1 },
2575 { 0x02, 0x0008 },
2576 { 0x01, 0x0120 },
2577 { 0x00, 0x1000 },
2578 { 0x04, 0x0800 },
2579 { 0x04, 0x9000 },
2580 { 0x03, 0x802f },
2581 { 0x02, 0x4f02 },
2582 { 0x01, 0x0409 },
2583 { 0x00, 0xf099 },
2584 { 0x04, 0x9800 },
2585 { 0x04, 0xa000 },
2586 { 0x03, 0xdf01 },
2587 { 0x02, 0xdf20 },
2588 { 0x01, 0xff95 },
2589 { 0x00, 0xba00 },
2590 { 0x04, 0xa800 },
2591 { 0x04, 0xf000 },
2592 { 0x03, 0xdf01 },
2593 { 0x02, 0xdf20 },
2594 { 0x01, 0x101a },
2595 { 0x00, 0xa0ff },
2596 { 0x04, 0xf800 },
2597 { 0x04, 0x0000 },
2598 { 0x1f, 0x0000 },
2599
2600 { 0x1f, 0x0001 },
2601 { 0x0b, 0x8480 },
2602 { 0x1f, 0x0000 },
2603
2604 { 0x1f, 0x0001 },
2605 { 0x18, 0x67c7 },
2606 { 0x04, 0x2000 },
2607 { 0x03, 0x002f },
2608 { 0x02, 0x4360 },
2609 { 0x01, 0x0109 },
2610 { 0x00, 0x3022 },
2611 { 0x04, 0x2800 },
2612 { 0x1f, 0x0000 },
2613
2614 { 0x1f, 0x0001 },
2615 { 0x17, 0x0cc0 },
2616 { 0x1f, 0x0000 }
2617 };
2618
2619 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2620 }
2621
2622 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2623 {
2624 static const struct phy_reg phy_reg_init[] = {
2625 { 0x10, 0xf41b },
2626 { 0x1f, 0x0000 }
2627 };
2628
2629 rtl_writephy(tp, 0x1f, 0x0001);
2630 rtl_patchphy(tp, 0x16, 1 << 0);
2631
2632 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2633 }
2634
2635 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2636 {
2637 static const struct phy_reg phy_reg_init[] = {
2638 { 0x1f, 0x0001 },
2639 { 0x10, 0xf41b },
2640 { 0x1f, 0x0000 }
2641 };
2642
2643 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2644 }
2645
2646 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2647 {
2648 static const struct phy_reg phy_reg_init[] = {
2649 { 0x1f, 0x0000 },
2650 { 0x1d, 0x0f00 },
2651 { 0x1f, 0x0002 },
2652 { 0x0c, 0x1ec8 },
2653 { 0x1f, 0x0000 }
2654 };
2655
2656 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2657 }
2658
2659 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2660 {
2661 static const struct phy_reg phy_reg_init[] = {
2662 { 0x1f, 0x0001 },
2663 { 0x1d, 0x3d98 },
2664 { 0x1f, 0x0000 }
2665 };
2666
2667 rtl_writephy(tp, 0x1f, 0x0000);
2668 rtl_patchphy(tp, 0x14, 1 << 5);
2669 rtl_patchphy(tp, 0x0d, 1 << 5);
2670
2671 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2672 }
2673
2674 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2675 {
2676 static const struct phy_reg phy_reg_init[] = {
2677 { 0x1f, 0x0001 },
2678 { 0x12, 0x2300 },
2679 { 0x1f, 0x0002 },
2680 { 0x00, 0x88d4 },
2681 { 0x01, 0x82b1 },
2682 { 0x03, 0x7002 },
2683 { 0x08, 0x9e30 },
2684 { 0x09, 0x01f0 },
2685 { 0x0a, 0x5500 },
2686 { 0x0c, 0x00c8 },
2687 { 0x1f, 0x0003 },
2688 { 0x12, 0xc096 },
2689 { 0x16, 0x000a },
2690 { 0x1f, 0x0000 },
2691 { 0x1f, 0x0000 },
2692 { 0x09, 0x2000 },
2693 { 0x09, 0x0000 }
2694 };
2695
2696 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2697
2698 rtl_patchphy(tp, 0x14, 1 << 5);
2699 rtl_patchphy(tp, 0x0d, 1 << 5);
2700 rtl_writephy(tp, 0x1f, 0x0000);
2701 }
2702
2703 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2704 {
2705 static const struct phy_reg phy_reg_init[] = {
2706 { 0x1f, 0x0001 },
2707 { 0x12, 0x2300 },
2708 { 0x03, 0x802f },
2709 { 0x02, 0x4f02 },
2710 { 0x01, 0x0409 },
2711 { 0x00, 0xf099 },
2712 { 0x04, 0x9800 },
2713 { 0x04, 0x9000 },
2714 { 0x1d, 0x3d98 },
2715 { 0x1f, 0x0002 },
2716 { 0x0c, 0x7eb8 },
2717 { 0x06, 0x0761 },
2718 { 0x1f, 0x0003 },
2719 { 0x16, 0x0f0a },
2720 { 0x1f, 0x0000 }
2721 };
2722
2723 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2724
2725 rtl_patchphy(tp, 0x16, 1 << 0);
2726 rtl_patchphy(tp, 0x14, 1 << 5);
2727 rtl_patchphy(tp, 0x0d, 1 << 5);
2728 rtl_writephy(tp, 0x1f, 0x0000);
2729 }
2730
2731 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2732 {
2733 static const struct phy_reg phy_reg_init[] = {
2734 { 0x1f, 0x0001 },
2735 { 0x12, 0x2300 },
2736 { 0x1d, 0x3d98 },
2737 { 0x1f, 0x0002 },
2738 { 0x0c, 0x7eb8 },
2739 { 0x06, 0x5461 },
2740 { 0x1f, 0x0003 },
2741 { 0x16, 0x0f0a },
2742 { 0x1f, 0x0000 }
2743 };
2744
2745 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2746
2747 rtl_patchphy(tp, 0x16, 1 << 0);
2748 rtl_patchphy(tp, 0x14, 1 << 5);
2749 rtl_patchphy(tp, 0x0d, 1 << 5);
2750 rtl_writephy(tp, 0x1f, 0x0000);
2751 }
2752
2753 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2754 {
2755 rtl8168c_3_hw_phy_config(tp);
2756 }
2757
2758 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2759 {
2760 static const struct phy_reg phy_reg_init_0[] = {
2761 /* Channel Estimation */
2762 { 0x1f, 0x0001 },
2763 { 0x06, 0x4064 },
2764 { 0x07, 0x2863 },
2765 { 0x08, 0x059c },
2766 { 0x09, 0x26b4 },
2767 { 0x0a, 0x6a19 },
2768 { 0x0b, 0xdcc8 },
2769 { 0x10, 0xf06d },
2770 { 0x14, 0x7f68 },
2771 { 0x18, 0x7fd9 },
2772 { 0x1c, 0xf0ff },
2773 { 0x1d, 0x3d9c },
2774 { 0x1f, 0x0003 },
2775 { 0x12, 0xf49f },
2776 { 0x13, 0x070b },
2777 { 0x1a, 0x05ad },
2778 { 0x14, 0x94c0 },
2779
2780 /*
2781 * Tx Error Issue
2782 * Enhance line driver power
2783 */
2784 { 0x1f, 0x0002 },
2785 { 0x06, 0x5561 },
2786 { 0x1f, 0x0005 },
2787 { 0x05, 0x8332 },
2788 { 0x06, 0x5561 },
2789
2790 /*
2791 * Can not link to 1Gbps with bad cable
2792 * Decrease SNR threshold form 21.07dB to 19.04dB
2793 */
2794 { 0x1f, 0x0001 },
2795 { 0x17, 0x0cc0 },
2796
2797 { 0x1f, 0x0000 },
2798 { 0x0d, 0xf880 }
2799 };
2800
2801 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2802
2803 /*
2804 * Rx Error Issue
2805 * Fine Tune Switching regulator parameter
2806 */
2807 rtl_writephy(tp, 0x1f, 0x0002);
2808 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2809 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2810
2811 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2812 static const struct phy_reg phy_reg_init[] = {
2813 { 0x1f, 0x0002 },
2814 { 0x05, 0x669a },
2815 { 0x1f, 0x0005 },
2816 { 0x05, 0x8330 },
2817 { 0x06, 0x669a },
2818 { 0x1f, 0x0002 }
2819 };
2820 int val;
2821
2822 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2823
2824 val = rtl_readphy(tp, 0x0d);
2825
2826 if ((val & 0x00ff) != 0x006c) {
2827 static const u32 set[] = {
2828 0x0065, 0x0066, 0x0067, 0x0068,
2829 0x0069, 0x006a, 0x006b, 0x006c
2830 };
2831 int i;
2832
2833 rtl_writephy(tp, 0x1f, 0x0002);
2834
2835 val &= 0xff00;
2836 for (i = 0; i < ARRAY_SIZE(set); i++)
2837 rtl_writephy(tp, 0x0d, val | set[i]);
2838 }
2839 } else {
2840 static const struct phy_reg phy_reg_init[] = {
2841 { 0x1f, 0x0002 },
2842 { 0x05, 0x6662 },
2843 { 0x1f, 0x0005 },
2844 { 0x05, 0x8330 },
2845 { 0x06, 0x6662 }
2846 };
2847
2848 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2849 }
2850
2851 /* RSET couple improve */
2852 rtl_writephy(tp, 0x1f, 0x0002);
2853 rtl_patchphy(tp, 0x0d, 0x0300);
2854 rtl_patchphy(tp, 0x0f, 0x0010);
2855
2856 /* Fine tune PLL performance */
2857 rtl_writephy(tp, 0x1f, 0x0002);
2858 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2859 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2860
2861 rtl_writephy(tp, 0x1f, 0x0005);
2862 rtl_writephy(tp, 0x05, 0x001b);
2863
2864 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2865
2866 rtl_writephy(tp, 0x1f, 0x0000);
2867 }
2868
2869 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2870 {
2871 static const struct phy_reg phy_reg_init_0[] = {
2872 /* Channel Estimation */
2873 { 0x1f, 0x0001 },
2874 { 0x06, 0x4064 },
2875 { 0x07, 0x2863 },
2876 { 0x08, 0x059c },
2877 { 0x09, 0x26b4 },
2878 { 0x0a, 0x6a19 },
2879 { 0x0b, 0xdcc8 },
2880 { 0x10, 0xf06d },
2881 { 0x14, 0x7f68 },
2882 { 0x18, 0x7fd9 },
2883 { 0x1c, 0xf0ff },
2884 { 0x1d, 0x3d9c },
2885 { 0x1f, 0x0003 },
2886 { 0x12, 0xf49f },
2887 { 0x13, 0x070b },
2888 { 0x1a, 0x05ad },
2889 { 0x14, 0x94c0 },
2890
2891 /*
2892 * Tx Error Issue
2893 * Enhance line driver power
2894 */
2895 { 0x1f, 0x0002 },
2896 { 0x06, 0x5561 },
2897 { 0x1f, 0x0005 },
2898 { 0x05, 0x8332 },
2899 { 0x06, 0x5561 },
2900
2901 /*
2902 * Can not link to 1Gbps with bad cable
2903 * Decrease SNR threshold form 21.07dB to 19.04dB
2904 */
2905 { 0x1f, 0x0001 },
2906 { 0x17, 0x0cc0 },
2907
2908 { 0x1f, 0x0000 },
2909 { 0x0d, 0xf880 }
2910 };
2911
2912 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2913
2914 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2915 static const struct phy_reg phy_reg_init[] = {
2916 { 0x1f, 0x0002 },
2917 { 0x05, 0x669a },
2918 { 0x1f, 0x0005 },
2919 { 0x05, 0x8330 },
2920 { 0x06, 0x669a },
2921
2922 { 0x1f, 0x0002 }
2923 };
2924 int val;
2925
2926 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2927
2928 val = rtl_readphy(tp, 0x0d);
2929 if ((val & 0x00ff) != 0x006c) {
2930 static const u32 set[] = {
2931 0x0065, 0x0066, 0x0067, 0x0068,
2932 0x0069, 0x006a, 0x006b, 0x006c
2933 };
2934 int i;
2935
2936 rtl_writephy(tp, 0x1f, 0x0002);
2937
2938 val &= 0xff00;
2939 for (i = 0; i < ARRAY_SIZE(set); i++)
2940 rtl_writephy(tp, 0x0d, val | set[i]);
2941 }
2942 } else {
2943 static const struct phy_reg phy_reg_init[] = {
2944 { 0x1f, 0x0002 },
2945 { 0x05, 0x2642 },
2946 { 0x1f, 0x0005 },
2947 { 0x05, 0x8330 },
2948 { 0x06, 0x2642 }
2949 };
2950
2951 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2952 }
2953
2954 /* Fine tune PLL performance */
2955 rtl_writephy(tp, 0x1f, 0x0002);
2956 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2957 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2958
2959 /* Switching regulator Slew rate */
2960 rtl_writephy(tp, 0x1f, 0x0002);
2961 rtl_patchphy(tp, 0x0f, 0x0017);
2962
2963 rtl_writephy(tp, 0x1f, 0x0005);
2964 rtl_writephy(tp, 0x05, 0x001b);
2965
2966 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2967
2968 rtl_writephy(tp, 0x1f, 0x0000);
2969 }
2970
2971 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2972 {
2973 static const struct phy_reg phy_reg_init[] = {
2974 { 0x1f, 0x0002 },
2975 { 0x10, 0x0008 },
2976 { 0x0d, 0x006c },
2977
2978 { 0x1f, 0x0000 },
2979 { 0x0d, 0xf880 },
2980
2981 { 0x1f, 0x0001 },
2982 { 0x17, 0x0cc0 },
2983
2984 { 0x1f, 0x0001 },
2985 { 0x0b, 0xa4d8 },
2986 { 0x09, 0x281c },
2987 { 0x07, 0x2883 },
2988 { 0x0a, 0x6b35 },
2989 { 0x1d, 0x3da4 },
2990 { 0x1c, 0xeffd },
2991 { 0x14, 0x7f52 },
2992 { 0x18, 0x7fc6 },
2993 { 0x08, 0x0601 },
2994 { 0x06, 0x4063 },
2995 { 0x10, 0xf074 },
2996 { 0x1f, 0x0003 },
2997 { 0x13, 0x0789 },
2998 { 0x12, 0xf4bd },
2999 { 0x1a, 0x04fd },
3000 { 0x14, 0x84b0 },
3001 { 0x1f, 0x0000 },
3002 { 0x00, 0x9200 },
3003
3004 { 0x1f, 0x0005 },
3005 { 0x01, 0x0340 },
3006 { 0x1f, 0x0001 },
3007 { 0x04, 0x4000 },
3008 { 0x03, 0x1d21 },
3009 { 0x02, 0x0c32 },
3010 { 0x01, 0x0200 },
3011 { 0x00, 0x5554 },
3012 { 0x04, 0x4800 },
3013 { 0x04, 0x4000 },
3014 { 0x04, 0xf000 },
3015 { 0x03, 0xdf01 },
3016 { 0x02, 0xdf20 },
3017 { 0x01, 0x101a },
3018 { 0x00, 0xa0ff },
3019 { 0x04, 0xf800 },
3020 { 0x04, 0xf000 },
3021 { 0x1f, 0x0000 },
3022
3023 { 0x1f, 0x0007 },
3024 { 0x1e, 0x0023 },
3025 { 0x16, 0x0000 },
3026 { 0x1f, 0x0000 }
3027 };
3028
3029 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3030 }
3031
3032 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3033 {
3034 static const struct phy_reg phy_reg_init[] = {
3035 { 0x1f, 0x0001 },
3036 { 0x17, 0x0cc0 },
3037
3038 { 0x1f, 0x0007 },
3039 { 0x1e, 0x002d },
3040 { 0x18, 0x0040 },
3041 { 0x1f, 0x0000 }
3042 };
3043
3044 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3045 rtl_patchphy(tp, 0x0d, 1 << 5);
3046 }
3047
3048 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3049 {
3050 static const struct phy_reg phy_reg_init[] = {
3051 /* Enable Delay cap */
3052 { 0x1f, 0x0005 },
3053 { 0x05, 0x8b80 },
3054 { 0x06, 0xc896 },
3055 { 0x1f, 0x0000 },
3056
3057 /* Channel estimation fine tune */
3058 { 0x1f, 0x0001 },
3059 { 0x0b, 0x6c20 },
3060 { 0x07, 0x2872 },
3061 { 0x1c, 0xefff },
3062 { 0x1f, 0x0003 },
3063 { 0x14, 0x6420 },
3064 { 0x1f, 0x0000 },
3065
3066 /* Update PFM & 10M TX idle timer */
3067 { 0x1f, 0x0007 },
3068 { 0x1e, 0x002f },
3069 { 0x15, 0x1919 },
3070 { 0x1f, 0x0000 },
3071
3072 { 0x1f, 0x0007 },
3073 { 0x1e, 0x00ac },
3074 { 0x18, 0x0006 },
3075 { 0x1f, 0x0000 }
3076 };
3077
3078 rtl_apply_firmware(tp);
3079
3080 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3081
3082 /* DCO enable for 10M IDLE Power */
3083 rtl_writephy(tp, 0x1f, 0x0007);
3084 rtl_writephy(tp, 0x1e, 0x0023);
3085 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3086 rtl_writephy(tp, 0x1f, 0x0000);
3087
3088 /* For impedance matching */
3089 rtl_writephy(tp, 0x1f, 0x0002);
3090 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3091 rtl_writephy(tp, 0x1f, 0x0000);
3092
3093 /* PHY auto speed down */
3094 rtl_writephy(tp, 0x1f, 0x0007);
3095 rtl_writephy(tp, 0x1e, 0x002d);
3096 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3097 rtl_writephy(tp, 0x1f, 0x0000);
3098 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3099
3100 rtl_writephy(tp, 0x1f, 0x0005);
3101 rtl_writephy(tp, 0x05, 0x8b86);
3102 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3103 rtl_writephy(tp, 0x1f, 0x0000);
3104
3105 rtl_writephy(tp, 0x1f, 0x0005);
3106 rtl_writephy(tp, 0x05, 0x8b85);
3107 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3108 rtl_writephy(tp, 0x1f, 0x0007);
3109 rtl_writephy(tp, 0x1e, 0x0020);
3110 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3111 rtl_writephy(tp, 0x1f, 0x0006);
3112 rtl_writephy(tp, 0x00, 0x5a00);
3113 rtl_writephy(tp, 0x1f, 0x0000);
3114 rtl_writephy(tp, 0x0d, 0x0007);
3115 rtl_writephy(tp, 0x0e, 0x003c);
3116 rtl_writephy(tp, 0x0d, 0x4007);
3117 rtl_writephy(tp, 0x0e, 0x0000);
3118 rtl_writephy(tp, 0x0d, 0x0000);
3119 }
3120
3121 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3122 {
3123 const u16 w[] = {
3124 addr[0] | (addr[1] << 8),
3125 addr[2] | (addr[3] << 8),
3126 addr[4] | (addr[5] << 8)
3127 };
3128 const struct exgmac_reg e[] = {
3129 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3130 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3131 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3132 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3133 };
3134
3135 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3136 }
3137
3138 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3139 {
3140 static const struct phy_reg phy_reg_init[] = {
3141 /* Enable Delay cap */
3142 { 0x1f, 0x0004 },
3143 { 0x1f, 0x0007 },
3144 { 0x1e, 0x00ac },
3145 { 0x18, 0x0006 },
3146 { 0x1f, 0x0002 },
3147 { 0x1f, 0x0000 },
3148 { 0x1f, 0x0000 },
3149
3150 /* Channel estimation fine tune */
3151 { 0x1f, 0x0003 },
3152 { 0x09, 0xa20f },
3153 { 0x1f, 0x0000 },
3154 { 0x1f, 0x0000 },
3155
3156 /* Green Setting */
3157 { 0x1f, 0x0005 },
3158 { 0x05, 0x8b5b },
3159 { 0x06, 0x9222 },
3160 { 0x05, 0x8b6d },
3161 { 0x06, 0x8000 },
3162 { 0x05, 0x8b76 },
3163 { 0x06, 0x8000 },
3164 { 0x1f, 0x0000 }
3165 };
3166
3167 rtl_apply_firmware(tp);
3168
3169 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3170
3171 /* For 4-corner performance improve */
3172 rtl_writephy(tp, 0x1f, 0x0005);
3173 rtl_writephy(tp, 0x05, 0x8b80);
3174 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3175 rtl_writephy(tp, 0x1f, 0x0000);
3176
3177 /* PHY auto speed down */
3178 rtl_writephy(tp, 0x1f, 0x0004);
3179 rtl_writephy(tp, 0x1f, 0x0007);
3180 rtl_writephy(tp, 0x1e, 0x002d);
3181 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3182 rtl_writephy(tp, 0x1f, 0x0002);
3183 rtl_writephy(tp, 0x1f, 0x0000);
3184 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3185
3186 /* improve 10M EEE waveform */
3187 rtl_writephy(tp, 0x1f, 0x0005);
3188 rtl_writephy(tp, 0x05, 0x8b86);
3189 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3190 rtl_writephy(tp, 0x1f, 0x0000);
3191
3192 /* Improve 2-pair detection performance */
3193 rtl_writephy(tp, 0x1f, 0x0005);
3194 rtl_writephy(tp, 0x05, 0x8b85);
3195 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3196 rtl_writephy(tp, 0x1f, 0x0000);
3197
3198 /* EEE setting */
3199 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3200 rtl_writephy(tp, 0x1f, 0x0005);
3201 rtl_writephy(tp, 0x05, 0x8b85);
3202 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3203 rtl_writephy(tp, 0x1f, 0x0004);
3204 rtl_writephy(tp, 0x1f, 0x0007);
3205 rtl_writephy(tp, 0x1e, 0x0020);
3206 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3207 rtl_writephy(tp, 0x1f, 0x0002);
3208 rtl_writephy(tp, 0x1f, 0x0000);
3209 rtl_writephy(tp, 0x0d, 0x0007);
3210 rtl_writephy(tp, 0x0e, 0x003c);
3211 rtl_writephy(tp, 0x0d, 0x4007);
3212 rtl_writephy(tp, 0x0e, 0x0000);
3213 rtl_writephy(tp, 0x0d, 0x0000);
3214
3215 /* Green feature */
3216 rtl_writephy(tp, 0x1f, 0x0003);
3217 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3218 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3219 rtl_writephy(tp, 0x1f, 0x0000);
3220
3221 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3222 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3223 }
3224
3225 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3226 {
3227 /* For 4-corner performance improve */
3228 rtl_writephy(tp, 0x1f, 0x0005);
3229 rtl_writephy(tp, 0x05, 0x8b80);
3230 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3231 rtl_writephy(tp, 0x1f, 0x0000);
3232
3233 /* PHY auto speed down */
3234 rtl_writephy(tp, 0x1f, 0x0007);
3235 rtl_writephy(tp, 0x1e, 0x002d);
3236 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3237 rtl_writephy(tp, 0x1f, 0x0000);
3238 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3239
3240 /* Improve 10M EEE waveform */
3241 rtl_writephy(tp, 0x1f, 0x0005);
3242 rtl_writephy(tp, 0x05, 0x8b86);
3243 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3244 rtl_writephy(tp, 0x1f, 0x0000);
3245 }
3246
3247 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3248 {
3249 static const struct phy_reg phy_reg_init[] = {
3250 /* Channel estimation fine tune */
3251 { 0x1f, 0x0003 },
3252 { 0x09, 0xa20f },
3253 { 0x1f, 0x0000 },
3254
3255 /* Modify green table for giga & fnet */
3256 { 0x1f, 0x0005 },
3257 { 0x05, 0x8b55 },
3258 { 0x06, 0x0000 },
3259 { 0x05, 0x8b5e },
3260 { 0x06, 0x0000 },
3261 { 0x05, 0x8b67 },
3262 { 0x06, 0x0000 },
3263 { 0x05, 0x8b70 },
3264 { 0x06, 0x0000 },
3265 { 0x1f, 0x0000 },
3266 { 0x1f, 0x0007 },
3267 { 0x1e, 0x0078 },
3268 { 0x17, 0x0000 },
3269 { 0x19, 0x00fb },
3270 { 0x1f, 0x0000 },
3271
3272 /* Modify green table for 10M */
3273 { 0x1f, 0x0005 },
3274 { 0x05, 0x8b79 },
3275 { 0x06, 0xaa00 },
3276 { 0x1f, 0x0000 },
3277
3278 /* Disable hiimpedance detection (RTCT) */
3279 { 0x1f, 0x0003 },
3280 { 0x01, 0x328a },
3281 { 0x1f, 0x0000 }
3282 };
3283
3284 rtl_apply_firmware(tp);
3285
3286 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3287
3288 rtl8168f_hw_phy_config(tp);
3289
3290 /* Improve 2-pair detection performance */
3291 rtl_writephy(tp, 0x1f, 0x0005);
3292 rtl_writephy(tp, 0x05, 0x8b85);
3293 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3294 rtl_writephy(tp, 0x1f, 0x0000);
3295 }
3296
3297 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3298 {
3299 rtl_apply_firmware(tp);
3300
3301 rtl8168f_hw_phy_config(tp);
3302 }
3303
3304 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3305 {
3306 static const struct phy_reg phy_reg_init[] = {
3307 /* Channel estimation fine tune */
3308 { 0x1f, 0x0003 },
3309 { 0x09, 0xa20f },
3310 { 0x1f, 0x0000 },
3311
3312 /* Modify green table for giga & fnet */
3313 { 0x1f, 0x0005 },
3314 { 0x05, 0x8b55 },
3315 { 0x06, 0x0000 },
3316 { 0x05, 0x8b5e },
3317 { 0x06, 0x0000 },
3318 { 0x05, 0x8b67 },
3319 { 0x06, 0x0000 },
3320 { 0x05, 0x8b70 },
3321 { 0x06, 0x0000 },
3322 { 0x1f, 0x0000 },
3323 { 0x1f, 0x0007 },
3324 { 0x1e, 0x0078 },
3325 { 0x17, 0x0000 },
3326 { 0x19, 0x00aa },
3327 { 0x1f, 0x0000 },
3328
3329 /* Modify green table for 10M */
3330 { 0x1f, 0x0005 },
3331 { 0x05, 0x8b79 },
3332 { 0x06, 0xaa00 },
3333 { 0x1f, 0x0000 },
3334
3335 /* Disable hiimpedance detection (RTCT) */
3336 { 0x1f, 0x0003 },
3337 { 0x01, 0x328a },
3338 { 0x1f, 0x0000 }
3339 };
3340
3341
3342 rtl_apply_firmware(tp);
3343
3344 rtl8168f_hw_phy_config(tp);
3345
3346 /* Improve 2-pair detection performance */
3347 rtl_writephy(tp, 0x1f, 0x0005);
3348 rtl_writephy(tp, 0x05, 0x8b85);
3349 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3350 rtl_writephy(tp, 0x1f, 0x0000);
3351
3352 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3353
3354 /* Modify green table for giga */
3355 rtl_writephy(tp, 0x1f, 0x0005);
3356 rtl_writephy(tp, 0x05, 0x8b54);
3357 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3358 rtl_writephy(tp, 0x05, 0x8b5d);
3359 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3360 rtl_writephy(tp, 0x05, 0x8a7c);
3361 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3362 rtl_writephy(tp, 0x05, 0x8a7f);
3363 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3364 rtl_writephy(tp, 0x05, 0x8a82);
3365 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3366 rtl_writephy(tp, 0x05, 0x8a85);
3367 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3368 rtl_writephy(tp, 0x05, 0x8a88);
3369 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3370 rtl_writephy(tp, 0x1f, 0x0000);
3371
3372 /* uc same-seed solution */
3373 rtl_writephy(tp, 0x1f, 0x0005);
3374 rtl_writephy(tp, 0x05, 0x8b85);
3375 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3376 rtl_writephy(tp, 0x1f, 0x0000);
3377
3378 /* eee setting */
3379 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3380 rtl_writephy(tp, 0x1f, 0x0005);
3381 rtl_writephy(tp, 0x05, 0x8b85);
3382 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3383 rtl_writephy(tp, 0x1f, 0x0004);
3384 rtl_writephy(tp, 0x1f, 0x0007);
3385 rtl_writephy(tp, 0x1e, 0x0020);
3386 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3387 rtl_writephy(tp, 0x1f, 0x0000);
3388 rtl_writephy(tp, 0x0d, 0x0007);
3389 rtl_writephy(tp, 0x0e, 0x003c);
3390 rtl_writephy(tp, 0x0d, 0x4007);
3391 rtl_writephy(tp, 0x0e, 0x0000);
3392 rtl_writephy(tp, 0x0d, 0x0000);
3393
3394 /* Green feature */
3395 rtl_writephy(tp, 0x1f, 0x0003);
3396 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3397 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3398 rtl_writephy(tp, 0x1f, 0x0000);
3399 }
3400
3401 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3402 {
3403 rtl_apply_firmware(tp);
3404
3405 rtl_writephy(tp, 0x1f, 0x0a46);
3406 if (rtl_readphy(tp, 0x10) & 0x0100) {
3407 rtl_writephy(tp, 0x1f, 0x0bcc);
3408 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3409 } else {
3410 rtl_writephy(tp, 0x1f, 0x0bcc);
3411 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3412 }
3413
3414 rtl_writephy(tp, 0x1f, 0x0a46);
3415 if (rtl_readphy(tp, 0x13) & 0x0100) {
3416 rtl_writephy(tp, 0x1f, 0x0c41);
3417 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3418 } else {
3419 rtl_writephy(tp, 0x1f, 0x0c41);
3420 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
3421 }
3422
3423 /* Enable PHY auto speed down */
3424 rtl_writephy(tp, 0x1f, 0x0a44);
3425 rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
3426
3427 rtl_writephy(tp, 0x1f, 0x0bcc);
3428 rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3429 rtl_writephy(tp, 0x1f, 0x0a44);
3430 rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3431 rtl_writephy(tp, 0x1f, 0x0a43);
3432 rtl_writephy(tp, 0x13, 0x8084);
3433 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3434 rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3435
3436 /* EEE auto-fallback function */
3437 rtl_writephy(tp, 0x1f, 0x0a4b);
3438 rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
3439
3440 /* Enable UC LPF tune function */
3441 rtl_writephy(tp, 0x1f, 0x0a43);
3442 rtl_writephy(tp, 0x13, 0x8012);
3443 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3444
3445 rtl_writephy(tp, 0x1f, 0x0c42);
3446 rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3447
3448 /* Improve SWR Efficiency */
3449 rtl_writephy(tp, 0x1f, 0x0bcd);
3450 rtl_writephy(tp, 0x14, 0x5065);
3451 rtl_writephy(tp, 0x14, 0xd065);
3452 rtl_writephy(tp, 0x1f, 0x0bc8);
3453 rtl_writephy(tp, 0x11, 0x5655);
3454 rtl_writephy(tp, 0x1f, 0x0bcd);
3455 rtl_writephy(tp, 0x14, 0x1065);
3456 rtl_writephy(tp, 0x14, 0x9065);
3457 rtl_writephy(tp, 0x14, 0x1065);
3458
3459 /* Check ALDPS bit, disable it if enabled */
3460 rtl_writephy(tp, 0x1f, 0x0a43);
3461 if (rtl_readphy(tp, 0x10) & 0x0004)
3462 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3463
3464 rtl_writephy(tp, 0x1f, 0x0000);
3465 }
3466
3467 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3468 {
3469 rtl_apply_firmware(tp);
3470 }
3471
3472 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3473 {
3474 static const struct phy_reg phy_reg_init[] = {
3475 { 0x1f, 0x0003 },
3476 { 0x08, 0x441d },
3477 { 0x01, 0x9100 },
3478 { 0x1f, 0x0000 }
3479 };
3480
3481 rtl_writephy(tp, 0x1f, 0x0000);
3482 rtl_patchphy(tp, 0x11, 1 << 12);
3483 rtl_patchphy(tp, 0x19, 1 << 13);
3484 rtl_patchphy(tp, 0x10, 1 << 15);
3485
3486 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3487 }
3488
3489 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3490 {
3491 static const struct phy_reg phy_reg_init[] = {
3492 { 0x1f, 0x0005 },
3493 { 0x1a, 0x0000 },
3494 { 0x1f, 0x0000 },
3495
3496 { 0x1f, 0x0004 },
3497 { 0x1c, 0x0000 },
3498 { 0x1f, 0x0000 },
3499
3500 { 0x1f, 0x0001 },
3501 { 0x15, 0x7701 },
3502 { 0x1f, 0x0000 }
3503 };
3504
3505 /* Disable ALDPS before ram code */
3506 rtl_writephy(tp, 0x1f, 0x0000);
3507 rtl_writephy(tp, 0x18, 0x0310);
3508 msleep(100);
3509
3510 rtl_apply_firmware(tp);
3511
3512 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3513 }
3514
3515 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3516 {
3517 /* Disable ALDPS before setting firmware */
3518 rtl_writephy(tp, 0x1f, 0x0000);
3519 rtl_writephy(tp, 0x18, 0x0310);
3520 msleep(20);
3521
3522 rtl_apply_firmware(tp);
3523
3524 /* EEE setting */
3525 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3526 rtl_writephy(tp, 0x1f, 0x0004);
3527 rtl_writephy(tp, 0x10, 0x401f);
3528 rtl_writephy(tp, 0x19, 0x7030);
3529 rtl_writephy(tp, 0x1f, 0x0000);
3530 }
3531
3532 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3533 {
3534 static const struct phy_reg phy_reg_init[] = {
3535 { 0x1f, 0x0004 },
3536 { 0x10, 0xc07f },
3537 { 0x19, 0x7030 },
3538 { 0x1f, 0x0000 }
3539 };
3540
3541 /* Disable ALDPS before ram code */
3542 rtl_writephy(tp, 0x1f, 0x0000);
3543 rtl_writephy(tp, 0x18, 0x0310);
3544 msleep(100);
3545
3546 rtl_apply_firmware(tp);
3547
3548 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3549 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3550
3551 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3552 }
3553
3554 static void rtl_hw_phy_config(struct net_device *dev)
3555 {
3556 struct rtl8169_private *tp = netdev_priv(dev);
3557
3558 rtl8169_print_mac_version(tp);
3559
3560 switch (tp->mac_version) {
3561 case RTL_GIGA_MAC_VER_01:
3562 break;
3563 case RTL_GIGA_MAC_VER_02:
3564 case RTL_GIGA_MAC_VER_03:
3565 rtl8169s_hw_phy_config(tp);
3566 break;
3567 case RTL_GIGA_MAC_VER_04:
3568 rtl8169sb_hw_phy_config(tp);
3569 break;
3570 case RTL_GIGA_MAC_VER_05:
3571 rtl8169scd_hw_phy_config(tp);
3572 break;
3573 case RTL_GIGA_MAC_VER_06:
3574 rtl8169sce_hw_phy_config(tp);
3575 break;
3576 case RTL_GIGA_MAC_VER_07:
3577 case RTL_GIGA_MAC_VER_08:
3578 case RTL_GIGA_MAC_VER_09:
3579 rtl8102e_hw_phy_config(tp);
3580 break;
3581 case RTL_GIGA_MAC_VER_11:
3582 rtl8168bb_hw_phy_config(tp);
3583 break;
3584 case RTL_GIGA_MAC_VER_12:
3585 rtl8168bef_hw_phy_config(tp);
3586 break;
3587 case RTL_GIGA_MAC_VER_17:
3588 rtl8168bef_hw_phy_config(tp);
3589 break;
3590 case RTL_GIGA_MAC_VER_18:
3591 rtl8168cp_1_hw_phy_config(tp);
3592 break;
3593 case RTL_GIGA_MAC_VER_19:
3594 rtl8168c_1_hw_phy_config(tp);
3595 break;
3596 case RTL_GIGA_MAC_VER_20:
3597 rtl8168c_2_hw_phy_config(tp);
3598 break;
3599 case RTL_GIGA_MAC_VER_21:
3600 rtl8168c_3_hw_phy_config(tp);
3601 break;
3602 case RTL_GIGA_MAC_VER_22:
3603 rtl8168c_4_hw_phy_config(tp);
3604 break;
3605 case RTL_GIGA_MAC_VER_23:
3606 case RTL_GIGA_MAC_VER_24:
3607 rtl8168cp_2_hw_phy_config(tp);
3608 break;
3609 case RTL_GIGA_MAC_VER_25:
3610 rtl8168d_1_hw_phy_config(tp);
3611 break;
3612 case RTL_GIGA_MAC_VER_26:
3613 rtl8168d_2_hw_phy_config(tp);
3614 break;
3615 case RTL_GIGA_MAC_VER_27:
3616 rtl8168d_3_hw_phy_config(tp);
3617 break;
3618 case RTL_GIGA_MAC_VER_28:
3619 rtl8168d_4_hw_phy_config(tp);
3620 break;
3621 case RTL_GIGA_MAC_VER_29:
3622 case RTL_GIGA_MAC_VER_30:
3623 rtl8105e_hw_phy_config(tp);
3624 break;
3625 case RTL_GIGA_MAC_VER_31:
3626 /* None. */
3627 break;
3628 case RTL_GIGA_MAC_VER_32:
3629 case RTL_GIGA_MAC_VER_33:
3630 rtl8168e_1_hw_phy_config(tp);
3631 break;
3632 case RTL_GIGA_MAC_VER_34:
3633 rtl8168e_2_hw_phy_config(tp);
3634 break;
3635 case RTL_GIGA_MAC_VER_35:
3636 rtl8168f_1_hw_phy_config(tp);
3637 break;
3638 case RTL_GIGA_MAC_VER_36:
3639 rtl8168f_2_hw_phy_config(tp);
3640 break;
3641
3642 case RTL_GIGA_MAC_VER_37:
3643 rtl8402_hw_phy_config(tp);
3644 break;
3645
3646 case RTL_GIGA_MAC_VER_38:
3647 rtl8411_hw_phy_config(tp);
3648 break;
3649
3650 case RTL_GIGA_MAC_VER_39:
3651 rtl8106e_hw_phy_config(tp);
3652 break;
3653
3654 case RTL_GIGA_MAC_VER_40:
3655 rtl8168g_1_hw_phy_config(tp);
3656 break;
3657 case RTL_GIGA_MAC_VER_42:
3658 case RTL_GIGA_MAC_VER_43:
3659 rtl8168g_2_hw_phy_config(tp);
3660 break;
3661
3662 case RTL_GIGA_MAC_VER_41:
3663 default:
3664 break;
3665 }
3666 }
3667
3668 static void rtl_phy_work(struct rtl8169_private *tp)
3669 {
3670 struct timer_list *timer = &tp->timer;
3671 void __iomem *ioaddr = tp->mmio_addr;
3672 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3673
3674 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3675
3676 if (tp->phy_reset_pending(tp)) {
3677 /*
3678 * A busy loop could burn quite a few cycles on nowadays CPU.
3679 * Let's delay the execution of the timer for a few ticks.
3680 */
3681 timeout = HZ/10;
3682 goto out_mod_timer;
3683 }
3684
3685 if (tp->link_ok(ioaddr))
3686 return;
3687
3688 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3689
3690 tp->phy_reset_enable(tp);
3691
3692 out_mod_timer:
3693 mod_timer(timer, jiffies + timeout);
3694 }
3695
3696 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3697 {
3698 if (!test_and_set_bit(flag, tp->wk.flags))
3699 schedule_work(&tp->wk.work);
3700 }
3701
3702 static void rtl8169_phy_timer(unsigned long __opaque)
3703 {
3704 struct net_device *dev = (struct net_device *)__opaque;
3705 struct rtl8169_private *tp = netdev_priv(dev);
3706
3707 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3708 }
3709
3710 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3711 void __iomem *ioaddr)
3712 {
3713 iounmap(ioaddr);
3714 pci_release_regions(pdev);
3715 pci_clear_mwi(pdev);
3716 pci_disable_device(pdev);
3717 free_netdev(dev);
3718 }
3719
3720 DECLARE_RTL_COND(rtl_phy_reset_cond)
3721 {
3722 return tp->phy_reset_pending(tp);
3723 }
3724
3725 static void rtl8169_phy_reset(struct net_device *dev,
3726 struct rtl8169_private *tp)
3727 {
3728 tp->phy_reset_enable(tp);
3729 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3730 }
3731
3732 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3733 {
3734 void __iomem *ioaddr = tp->mmio_addr;
3735
3736 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3737 (RTL_R8(PHYstatus) & TBI_Enable);
3738 }
3739
3740 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3741 {
3742 void __iomem *ioaddr = tp->mmio_addr;
3743
3744 rtl_hw_phy_config(dev);
3745
3746 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3747 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3748 RTL_W8(0x82, 0x01);
3749 }
3750
3751 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3752
3753 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3754 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3755
3756 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3757 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3758 RTL_W8(0x82, 0x01);
3759 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3760 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3761 }
3762
3763 rtl8169_phy_reset(dev, tp);
3764
3765 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3766 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3767 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3768 (tp->mii.supports_gmii ?
3769 ADVERTISED_1000baseT_Half |
3770 ADVERTISED_1000baseT_Full : 0));
3771
3772 if (rtl_tbi_enabled(tp))
3773 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3774 }
3775
3776 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3777 {
3778 void __iomem *ioaddr = tp->mmio_addr;
3779
3780 rtl_lock_work(tp);
3781
3782 RTL_W8(Cfg9346, Cfg9346_Unlock);
3783
3784 RTL_W32(MAC4, addr[4] | addr[5] << 8);
3785 RTL_R32(MAC4);
3786
3787 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3788 RTL_R32(MAC0);
3789
3790 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3791 rtl_rar_exgmac_set(tp, addr);
3792
3793 RTL_W8(Cfg9346, Cfg9346_Lock);
3794
3795 rtl_unlock_work(tp);
3796 }
3797
3798 static int rtl_set_mac_address(struct net_device *dev, void *p)
3799 {
3800 struct rtl8169_private *tp = netdev_priv(dev);
3801 struct sockaddr *addr = p;
3802
3803 if (!is_valid_ether_addr(addr->sa_data))
3804 return -EADDRNOTAVAIL;
3805
3806 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3807
3808 rtl_rar_set(tp, dev->dev_addr);
3809
3810 return 0;
3811 }
3812
3813 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3814 {
3815 struct rtl8169_private *tp = netdev_priv(dev);
3816 struct mii_ioctl_data *data = if_mii(ifr);
3817
3818 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3819 }
3820
3821 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3822 struct mii_ioctl_data *data, int cmd)
3823 {
3824 switch (cmd) {
3825 case SIOCGMIIPHY:
3826 data->phy_id = 32; /* Internal PHY */
3827 return 0;
3828
3829 case SIOCGMIIREG:
3830 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3831 return 0;
3832
3833 case SIOCSMIIREG:
3834 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3835 return 0;
3836 }
3837 return -EOPNOTSUPP;
3838 }
3839
3840 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3841 {
3842 return -EOPNOTSUPP;
3843 }
3844
3845 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3846 {
3847 if (tp->features & RTL_FEATURE_MSI) {
3848 pci_disable_msi(pdev);
3849 tp->features &= ~RTL_FEATURE_MSI;
3850 }
3851 }
3852
3853 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
3854 {
3855 struct mdio_ops *ops = &tp->mdio_ops;
3856
3857 switch (tp->mac_version) {
3858 case RTL_GIGA_MAC_VER_27:
3859 ops->write = r8168dp_1_mdio_write;
3860 ops->read = r8168dp_1_mdio_read;
3861 break;
3862 case RTL_GIGA_MAC_VER_28:
3863 case RTL_GIGA_MAC_VER_31:
3864 ops->write = r8168dp_2_mdio_write;
3865 ops->read = r8168dp_2_mdio_read;
3866 break;
3867 case RTL_GIGA_MAC_VER_40:
3868 case RTL_GIGA_MAC_VER_41:
3869 case RTL_GIGA_MAC_VER_42:
3870 case RTL_GIGA_MAC_VER_43:
3871 ops->write = r8168g_mdio_write;
3872 ops->read = r8168g_mdio_read;
3873 break;
3874 default:
3875 ops->write = r8169_mdio_write;
3876 ops->read = r8169_mdio_read;
3877 break;
3878 }
3879 }
3880
3881 static void rtl_speed_down(struct rtl8169_private *tp)
3882 {
3883 u32 adv;
3884 int lpa;
3885
3886 rtl_writephy(tp, 0x1f, 0x0000);
3887 lpa = rtl_readphy(tp, MII_LPA);
3888
3889 if (lpa & (LPA_10HALF | LPA_10FULL))
3890 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3891 else if (lpa & (LPA_100HALF | LPA_100FULL))
3892 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3893 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3894 else
3895 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3896 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3897 (tp->mii.supports_gmii ?
3898 ADVERTISED_1000baseT_Half |
3899 ADVERTISED_1000baseT_Full : 0);
3900
3901 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3902 adv);
3903 }
3904
3905 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3906 {
3907 void __iomem *ioaddr = tp->mmio_addr;
3908
3909 switch (tp->mac_version) {
3910 case RTL_GIGA_MAC_VER_25:
3911 case RTL_GIGA_MAC_VER_26:
3912 case RTL_GIGA_MAC_VER_29:
3913 case RTL_GIGA_MAC_VER_30:
3914 case RTL_GIGA_MAC_VER_32:
3915 case RTL_GIGA_MAC_VER_33:
3916 case RTL_GIGA_MAC_VER_34:
3917 case RTL_GIGA_MAC_VER_37:
3918 case RTL_GIGA_MAC_VER_38:
3919 case RTL_GIGA_MAC_VER_39:
3920 case RTL_GIGA_MAC_VER_40:
3921 case RTL_GIGA_MAC_VER_41:
3922 case RTL_GIGA_MAC_VER_42:
3923 case RTL_GIGA_MAC_VER_43:
3924 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3925 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3926 break;
3927 default:
3928 break;
3929 }
3930 }
3931
3932 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3933 {
3934 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3935 return false;
3936
3937 rtl_speed_down(tp);
3938 rtl_wol_suspend_quirk(tp);
3939
3940 return true;
3941 }
3942
3943 static void r810x_phy_power_down(struct rtl8169_private *tp)
3944 {
3945 rtl_writephy(tp, 0x1f, 0x0000);
3946 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3947 }
3948
3949 static void r810x_phy_power_up(struct rtl8169_private *tp)
3950 {
3951 rtl_writephy(tp, 0x1f, 0x0000);
3952 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3953 }
3954
3955 static void r810x_pll_power_down(struct rtl8169_private *tp)
3956 {
3957 void __iomem *ioaddr = tp->mmio_addr;
3958
3959 if (rtl_wol_pll_power_down(tp))
3960 return;
3961
3962 r810x_phy_power_down(tp);
3963
3964 switch (tp->mac_version) {
3965 case RTL_GIGA_MAC_VER_07:
3966 case RTL_GIGA_MAC_VER_08:
3967 case RTL_GIGA_MAC_VER_09:
3968 case RTL_GIGA_MAC_VER_10:
3969 case RTL_GIGA_MAC_VER_13:
3970 case RTL_GIGA_MAC_VER_16:
3971 break;
3972 default:
3973 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3974 break;
3975 }
3976 }
3977
3978 static void r810x_pll_power_up(struct rtl8169_private *tp)
3979 {
3980 void __iomem *ioaddr = tp->mmio_addr;
3981
3982 r810x_phy_power_up(tp);
3983
3984 switch (tp->mac_version) {
3985 case RTL_GIGA_MAC_VER_07:
3986 case RTL_GIGA_MAC_VER_08:
3987 case RTL_GIGA_MAC_VER_09:
3988 case RTL_GIGA_MAC_VER_10:
3989 case RTL_GIGA_MAC_VER_13:
3990 case RTL_GIGA_MAC_VER_16:
3991 break;
3992 default:
3993 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3994 break;
3995 }
3996 }
3997
3998 static void r8168_phy_power_up(struct rtl8169_private *tp)
3999 {
4000 rtl_writephy(tp, 0x1f, 0x0000);
4001 switch (tp->mac_version) {
4002 case RTL_GIGA_MAC_VER_11:
4003 case RTL_GIGA_MAC_VER_12:
4004 case RTL_GIGA_MAC_VER_17:
4005 case RTL_GIGA_MAC_VER_18:
4006 case RTL_GIGA_MAC_VER_19:
4007 case RTL_GIGA_MAC_VER_20:
4008 case RTL_GIGA_MAC_VER_21:
4009 case RTL_GIGA_MAC_VER_22:
4010 case RTL_GIGA_MAC_VER_23:
4011 case RTL_GIGA_MAC_VER_24:
4012 case RTL_GIGA_MAC_VER_25:
4013 case RTL_GIGA_MAC_VER_26:
4014 case RTL_GIGA_MAC_VER_27:
4015 case RTL_GIGA_MAC_VER_28:
4016 case RTL_GIGA_MAC_VER_31:
4017 rtl_writephy(tp, 0x0e, 0x0000);
4018 break;
4019 default:
4020 break;
4021 }
4022 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4023 }
4024
4025 static void r8168_phy_power_down(struct rtl8169_private *tp)
4026 {
4027 rtl_writephy(tp, 0x1f, 0x0000);
4028 switch (tp->mac_version) {
4029 case RTL_GIGA_MAC_VER_32:
4030 case RTL_GIGA_MAC_VER_33:
4031 case RTL_GIGA_MAC_VER_40:
4032 case RTL_GIGA_MAC_VER_41:
4033 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4034 break;
4035
4036 case RTL_GIGA_MAC_VER_11:
4037 case RTL_GIGA_MAC_VER_12:
4038 case RTL_GIGA_MAC_VER_17:
4039 case RTL_GIGA_MAC_VER_18:
4040 case RTL_GIGA_MAC_VER_19:
4041 case RTL_GIGA_MAC_VER_20:
4042 case RTL_GIGA_MAC_VER_21:
4043 case RTL_GIGA_MAC_VER_22:
4044 case RTL_GIGA_MAC_VER_23:
4045 case RTL_GIGA_MAC_VER_24:
4046 case RTL_GIGA_MAC_VER_25:
4047 case RTL_GIGA_MAC_VER_26:
4048 case RTL_GIGA_MAC_VER_27:
4049 case RTL_GIGA_MAC_VER_28:
4050 case RTL_GIGA_MAC_VER_31:
4051 rtl_writephy(tp, 0x0e, 0x0200);
4052 default:
4053 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4054 break;
4055 }
4056 }
4057
4058 static void r8168_pll_power_down(struct rtl8169_private *tp)
4059 {
4060 void __iomem *ioaddr = tp->mmio_addr;
4061
4062 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4063 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4064 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4065 r8168dp_check_dash(tp)) {
4066 return;
4067 }
4068
4069 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4070 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4071 (RTL_R16(CPlusCmd) & ASF)) {
4072 return;
4073 }
4074
4075 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4076 tp->mac_version == RTL_GIGA_MAC_VER_33)
4077 rtl_ephy_write(tp, 0x19, 0xff64);
4078
4079 if (rtl_wol_pll_power_down(tp))
4080 return;
4081
4082 r8168_phy_power_down(tp);
4083
4084 switch (tp->mac_version) {
4085 case RTL_GIGA_MAC_VER_25:
4086 case RTL_GIGA_MAC_VER_26:
4087 case RTL_GIGA_MAC_VER_27:
4088 case RTL_GIGA_MAC_VER_28:
4089 case RTL_GIGA_MAC_VER_31:
4090 case RTL_GIGA_MAC_VER_32:
4091 case RTL_GIGA_MAC_VER_33:
4092 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4093 break;
4094 case RTL_GIGA_MAC_VER_40:
4095 case RTL_GIGA_MAC_VER_41:
4096 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4097 0xfc000000, ERIAR_EXGMAC);
4098 break;
4099 }
4100 }
4101
4102 static void r8168_pll_power_up(struct rtl8169_private *tp)
4103 {
4104 void __iomem *ioaddr = tp->mmio_addr;
4105
4106 switch (tp->mac_version) {
4107 case RTL_GIGA_MAC_VER_25:
4108 case RTL_GIGA_MAC_VER_26:
4109 case RTL_GIGA_MAC_VER_27:
4110 case RTL_GIGA_MAC_VER_28:
4111 case RTL_GIGA_MAC_VER_31:
4112 case RTL_GIGA_MAC_VER_32:
4113 case RTL_GIGA_MAC_VER_33:
4114 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4115 break;
4116 case RTL_GIGA_MAC_VER_40:
4117 case RTL_GIGA_MAC_VER_41:
4118 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4119 0x00000000, ERIAR_EXGMAC);
4120 break;
4121 }
4122
4123 r8168_phy_power_up(tp);
4124 }
4125
4126 static void rtl_generic_op(struct rtl8169_private *tp,
4127 void (*op)(struct rtl8169_private *))
4128 {
4129 if (op)
4130 op(tp);
4131 }
4132
4133 static void rtl_pll_power_down(struct rtl8169_private *tp)
4134 {
4135 rtl_generic_op(tp, tp->pll_power_ops.down);
4136 }
4137
4138 static void rtl_pll_power_up(struct rtl8169_private *tp)
4139 {
4140 rtl_generic_op(tp, tp->pll_power_ops.up);
4141 }
4142
4143 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4144 {
4145 struct pll_power_ops *ops = &tp->pll_power_ops;
4146
4147 switch (tp->mac_version) {
4148 case RTL_GIGA_MAC_VER_07:
4149 case RTL_GIGA_MAC_VER_08:
4150 case RTL_GIGA_MAC_VER_09:
4151 case RTL_GIGA_MAC_VER_10:
4152 case RTL_GIGA_MAC_VER_16:
4153 case RTL_GIGA_MAC_VER_29:
4154 case RTL_GIGA_MAC_VER_30:
4155 case RTL_GIGA_MAC_VER_37:
4156 case RTL_GIGA_MAC_VER_39:
4157 case RTL_GIGA_MAC_VER_43:
4158 ops->down = r810x_pll_power_down;
4159 ops->up = r810x_pll_power_up;
4160 break;
4161
4162 case RTL_GIGA_MAC_VER_11:
4163 case RTL_GIGA_MAC_VER_12:
4164 case RTL_GIGA_MAC_VER_17:
4165 case RTL_GIGA_MAC_VER_18:
4166 case RTL_GIGA_MAC_VER_19:
4167 case RTL_GIGA_MAC_VER_20:
4168 case RTL_GIGA_MAC_VER_21:
4169 case RTL_GIGA_MAC_VER_22:
4170 case RTL_GIGA_MAC_VER_23:
4171 case RTL_GIGA_MAC_VER_24:
4172 case RTL_GIGA_MAC_VER_25:
4173 case RTL_GIGA_MAC_VER_26:
4174 case RTL_GIGA_MAC_VER_27:
4175 case RTL_GIGA_MAC_VER_28:
4176 case RTL_GIGA_MAC_VER_31:
4177 case RTL_GIGA_MAC_VER_32:
4178 case RTL_GIGA_MAC_VER_33:
4179 case RTL_GIGA_MAC_VER_34:
4180 case RTL_GIGA_MAC_VER_35:
4181 case RTL_GIGA_MAC_VER_36:
4182 case RTL_GIGA_MAC_VER_38:
4183 case RTL_GIGA_MAC_VER_40:
4184 case RTL_GIGA_MAC_VER_41:
4185 case RTL_GIGA_MAC_VER_42:
4186 ops->down = r8168_pll_power_down;
4187 ops->up = r8168_pll_power_up;
4188 break;
4189
4190 default:
4191 ops->down = NULL;
4192 ops->up = NULL;
4193 break;
4194 }
4195 }
4196
4197 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4198 {
4199 void __iomem *ioaddr = tp->mmio_addr;
4200
4201 switch (tp->mac_version) {
4202 case RTL_GIGA_MAC_VER_01:
4203 case RTL_GIGA_MAC_VER_02:
4204 case RTL_GIGA_MAC_VER_03:
4205 case RTL_GIGA_MAC_VER_04:
4206 case RTL_GIGA_MAC_VER_05:
4207 case RTL_GIGA_MAC_VER_06:
4208 case RTL_GIGA_MAC_VER_10:
4209 case RTL_GIGA_MAC_VER_11:
4210 case RTL_GIGA_MAC_VER_12:
4211 case RTL_GIGA_MAC_VER_13:
4212 case RTL_GIGA_MAC_VER_14:
4213 case RTL_GIGA_MAC_VER_15:
4214 case RTL_GIGA_MAC_VER_16:
4215 case RTL_GIGA_MAC_VER_17:
4216 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4217 break;
4218 case RTL_GIGA_MAC_VER_18:
4219 case RTL_GIGA_MAC_VER_19:
4220 case RTL_GIGA_MAC_VER_20:
4221 case RTL_GIGA_MAC_VER_21:
4222 case RTL_GIGA_MAC_VER_22:
4223 case RTL_GIGA_MAC_VER_23:
4224 case RTL_GIGA_MAC_VER_24:
4225 case RTL_GIGA_MAC_VER_34:
4226 case RTL_GIGA_MAC_VER_35:
4227 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4228 break;
4229 case RTL_GIGA_MAC_VER_40:
4230 case RTL_GIGA_MAC_VER_41:
4231 case RTL_GIGA_MAC_VER_42:
4232 case RTL_GIGA_MAC_VER_43:
4233 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4234 break;
4235 default:
4236 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4237 break;
4238 }
4239 }
4240
4241 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4242 {
4243 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4244 }
4245
4246 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4247 {
4248 void __iomem *ioaddr = tp->mmio_addr;
4249
4250 RTL_W8(Cfg9346, Cfg9346_Unlock);
4251 rtl_generic_op(tp, tp->jumbo_ops.enable);
4252 RTL_W8(Cfg9346, Cfg9346_Lock);
4253 }
4254
4255 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4256 {
4257 void __iomem *ioaddr = tp->mmio_addr;
4258
4259 RTL_W8(Cfg9346, Cfg9346_Unlock);
4260 rtl_generic_op(tp, tp->jumbo_ops.disable);
4261 RTL_W8(Cfg9346, Cfg9346_Lock);
4262 }
4263
4264 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4265 {
4266 void __iomem *ioaddr = tp->mmio_addr;
4267
4268 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4269 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4270 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4271 }
4272
4273 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4274 {
4275 void __iomem *ioaddr = tp->mmio_addr;
4276
4277 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4278 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4279 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4280 }
4281
4282 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4283 {
4284 void __iomem *ioaddr = tp->mmio_addr;
4285
4286 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4287 }
4288
4289 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4290 {
4291 void __iomem *ioaddr = tp->mmio_addr;
4292
4293 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4294 }
4295
4296 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4297 {
4298 void __iomem *ioaddr = tp->mmio_addr;
4299
4300 RTL_W8(MaxTxPacketSize, 0x3f);
4301 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4302 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4303 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4304 }
4305
4306 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4307 {
4308 void __iomem *ioaddr = tp->mmio_addr;
4309
4310 RTL_W8(MaxTxPacketSize, 0x0c);
4311 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4312 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4313 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4314 }
4315
4316 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4317 {
4318 rtl_tx_performance_tweak(tp->pci_dev,
4319 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4320 }
4321
4322 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4323 {
4324 rtl_tx_performance_tweak(tp->pci_dev,
4325 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4326 }
4327
4328 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4329 {
4330 void __iomem *ioaddr = tp->mmio_addr;
4331
4332 r8168b_0_hw_jumbo_enable(tp);
4333
4334 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4335 }
4336
4337 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4338 {
4339 void __iomem *ioaddr = tp->mmio_addr;
4340
4341 r8168b_0_hw_jumbo_disable(tp);
4342
4343 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4344 }
4345
4346 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4347 {
4348 struct jumbo_ops *ops = &tp->jumbo_ops;
4349
4350 switch (tp->mac_version) {
4351 case RTL_GIGA_MAC_VER_11:
4352 ops->disable = r8168b_0_hw_jumbo_disable;
4353 ops->enable = r8168b_0_hw_jumbo_enable;
4354 break;
4355 case RTL_GIGA_MAC_VER_12:
4356 case RTL_GIGA_MAC_VER_17:
4357 ops->disable = r8168b_1_hw_jumbo_disable;
4358 ops->enable = r8168b_1_hw_jumbo_enable;
4359 break;
4360 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4361 case RTL_GIGA_MAC_VER_19:
4362 case RTL_GIGA_MAC_VER_20:
4363 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4364 case RTL_GIGA_MAC_VER_22:
4365 case RTL_GIGA_MAC_VER_23:
4366 case RTL_GIGA_MAC_VER_24:
4367 case RTL_GIGA_MAC_VER_25:
4368 case RTL_GIGA_MAC_VER_26:
4369 ops->disable = r8168c_hw_jumbo_disable;
4370 ops->enable = r8168c_hw_jumbo_enable;
4371 break;
4372 case RTL_GIGA_MAC_VER_27:
4373 case RTL_GIGA_MAC_VER_28:
4374 ops->disable = r8168dp_hw_jumbo_disable;
4375 ops->enable = r8168dp_hw_jumbo_enable;
4376 break;
4377 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4378 case RTL_GIGA_MAC_VER_32:
4379 case RTL_GIGA_MAC_VER_33:
4380 case RTL_GIGA_MAC_VER_34:
4381 ops->disable = r8168e_hw_jumbo_disable;
4382 ops->enable = r8168e_hw_jumbo_enable;
4383 break;
4384
4385 /*
4386 * No action needed for jumbo frames with 8169.
4387 * No jumbo for 810x at all.
4388 */
4389 case RTL_GIGA_MAC_VER_40:
4390 case RTL_GIGA_MAC_VER_41:
4391 case RTL_GIGA_MAC_VER_42:
4392 case RTL_GIGA_MAC_VER_43:
4393 default:
4394 ops->disable = NULL;
4395 ops->enable = NULL;
4396 break;
4397 }
4398 }
4399
4400 DECLARE_RTL_COND(rtl_chipcmd_cond)
4401 {
4402 void __iomem *ioaddr = tp->mmio_addr;
4403
4404 return RTL_R8(ChipCmd) & CmdReset;
4405 }
4406
4407 static void rtl_hw_reset(struct rtl8169_private *tp)
4408 {
4409 void __iomem *ioaddr = tp->mmio_addr;
4410
4411 RTL_W8(ChipCmd, CmdReset);
4412
4413 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4414 }
4415
4416 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4417 {
4418 struct rtl_fw *rtl_fw;
4419 const char *name;
4420 int rc = -ENOMEM;
4421
4422 name = rtl_lookup_firmware_name(tp);
4423 if (!name)
4424 goto out_no_firmware;
4425
4426 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4427 if (!rtl_fw)
4428 goto err_warn;
4429
4430 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4431 if (rc < 0)
4432 goto err_free;
4433
4434 rc = rtl_check_firmware(tp, rtl_fw);
4435 if (rc < 0)
4436 goto err_release_firmware;
4437
4438 tp->rtl_fw = rtl_fw;
4439 out:
4440 return;
4441
4442 err_release_firmware:
4443 release_firmware(rtl_fw->fw);
4444 err_free:
4445 kfree(rtl_fw);
4446 err_warn:
4447 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4448 name, rc);
4449 out_no_firmware:
4450 tp->rtl_fw = NULL;
4451 goto out;
4452 }
4453
4454 static void rtl_request_firmware(struct rtl8169_private *tp)
4455 {
4456 if (IS_ERR(tp->rtl_fw))
4457 rtl_request_uncached_firmware(tp);
4458 }
4459
4460 static void rtl_rx_close(struct rtl8169_private *tp)
4461 {
4462 void __iomem *ioaddr = tp->mmio_addr;
4463
4464 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4465 }
4466
4467 DECLARE_RTL_COND(rtl_npq_cond)
4468 {
4469 void __iomem *ioaddr = tp->mmio_addr;
4470
4471 return RTL_R8(TxPoll) & NPQ;
4472 }
4473
4474 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4475 {
4476 void __iomem *ioaddr = tp->mmio_addr;
4477
4478 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4479 }
4480
4481 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4482 {
4483 void __iomem *ioaddr = tp->mmio_addr;
4484
4485 /* Disable interrupts */
4486 rtl8169_irq_mask_and_ack(tp);
4487
4488 rtl_rx_close(tp);
4489
4490 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4491 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4492 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4493 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4494 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4495 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4496 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4497 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4498 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4499 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4500 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4501 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4502 tp->mac_version == RTL_GIGA_MAC_VER_38) {
4503 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4504 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4505 } else {
4506 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4507 udelay(100);
4508 }
4509
4510 rtl_hw_reset(tp);
4511 }
4512
4513 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4514 {
4515 void __iomem *ioaddr = tp->mmio_addr;
4516
4517 /* Set DMA burst size and Interframe Gap Time */
4518 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4519 (InterFrameGap << TxInterFrameGapShift));
4520 }
4521
4522 static void rtl_hw_start(struct net_device *dev)
4523 {
4524 struct rtl8169_private *tp = netdev_priv(dev);
4525
4526 tp->hw_start(dev);
4527
4528 rtl_irq_enable_all(tp);
4529 }
4530
4531 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4532 void __iomem *ioaddr)
4533 {
4534 /*
4535 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4536 * register to be written before TxDescAddrLow to work.
4537 * Switching from MMIO to I/O access fixes the issue as well.
4538 */
4539 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4540 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4541 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4542 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4543 }
4544
4545 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4546 {
4547 u16 cmd;
4548
4549 cmd = RTL_R16(CPlusCmd);
4550 RTL_W16(CPlusCmd, cmd);
4551 return cmd;
4552 }
4553
4554 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4555 {
4556 /* Low hurts. Let's disable the filtering. */
4557 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4558 }
4559
4560 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4561 {
4562 static const struct rtl_cfg2_info {
4563 u32 mac_version;
4564 u32 clk;
4565 u32 val;
4566 } cfg2_info [] = {
4567 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4568 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4569 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4570 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4571 };
4572 const struct rtl_cfg2_info *p = cfg2_info;
4573 unsigned int i;
4574 u32 clk;
4575
4576 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4577 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4578 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4579 RTL_W32(0x7c, p->val);
4580 break;
4581 }
4582 }
4583 }
4584
4585 static void rtl_set_rx_mode(struct net_device *dev)
4586 {
4587 struct rtl8169_private *tp = netdev_priv(dev);
4588 void __iomem *ioaddr = tp->mmio_addr;
4589 u32 mc_filter[2]; /* Multicast hash filter */
4590 int rx_mode;
4591 u32 tmp = 0;
4592
4593 if (dev->flags & IFF_PROMISC) {
4594 /* Unconditionally log net taps. */
4595 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4596 rx_mode =
4597 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4598 AcceptAllPhys;
4599 mc_filter[1] = mc_filter[0] = 0xffffffff;
4600 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4601 (dev->flags & IFF_ALLMULTI)) {
4602 /* Too many to filter perfectly -- accept all multicasts. */
4603 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4604 mc_filter[1] = mc_filter[0] = 0xffffffff;
4605 } else {
4606 struct netdev_hw_addr *ha;
4607
4608 rx_mode = AcceptBroadcast | AcceptMyPhys;
4609 mc_filter[1] = mc_filter[0] = 0;
4610 netdev_for_each_mc_addr(ha, dev) {
4611 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4612 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4613 rx_mode |= AcceptMulticast;
4614 }
4615 }
4616
4617 if (dev->features & NETIF_F_RXALL)
4618 rx_mode |= (AcceptErr | AcceptRunt);
4619
4620 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4621
4622 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4623 u32 data = mc_filter[0];
4624
4625 mc_filter[0] = swab32(mc_filter[1]);
4626 mc_filter[1] = swab32(data);
4627 }
4628
4629 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4630 mc_filter[1] = mc_filter[0] = 0xffffffff;
4631
4632 RTL_W32(MAR0 + 4, mc_filter[1]);
4633 RTL_W32(MAR0 + 0, mc_filter[0]);
4634
4635 RTL_W32(RxConfig, tmp);
4636 }
4637
4638 static void rtl_hw_start_8169(struct net_device *dev)
4639 {
4640 struct rtl8169_private *tp = netdev_priv(dev);
4641 void __iomem *ioaddr = tp->mmio_addr;
4642 struct pci_dev *pdev = tp->pci_dev;
4643
4644 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4645 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4646 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4647 }
4648
4649 RTL_W8(Cfg9346, Cfg9346_Unlock);
4650 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4651 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4652 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4653 tp->mac_version == RTL_GIGA_MAC_VER_04)
4654 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4655
4656 rtl_init_rxcfg(tp);
4657
4658 RTL_W8(EarlyTxThres, NoEarlyTx);
4659
4660 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4661
4662 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4663 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4664 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4665 tp->mac_version == RTL_GIGA_MAC_VER_04)
4666 rtl_set_rx_tx_config_registers(tp);
4667
4668 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4669
4670 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4671 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4672 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4673 "Bit-3 and bit-14 MUST be 1\n");
4674 tp->cp_cmd |= (1 << 14);
4675 }
4676
4677 RTL_W16(CPlusCmd, tp->cp_cmd);
4678
4679 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4680
4681 /*
4682 * Undocumented corner. Supposedly:
4683 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4684 */
4685 RTL_W16(IntrMitigate, 0x0000);
4686
4687 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4688
4689 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4690 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4691 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4692 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4693 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4694 rtl_set_rx_tx_config_registers(tp);
4695 }
4696
4697 RTL_W8(Cfg9346, Cfg9346_Lock);
4698
4699 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4700 RTL_R8(IntrMask);
4701
4702 RTL_W32(RxMissed, 0);
4703
4704 rtl_set_rx_mode(dev);
4705
4706 /* no early-rx interrupts */
4707 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4708 }
4709
4710 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4711 {
4712 if (tp->csi_ops.write)
4713 tp->csi_ops.write(tp, addr, value);
4714 }
4715
4716 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4717 {
4718 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
4719 }
4720
4721 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4722 {
4723 u32 csi;
4724
4725 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4726 rtl_csi_write(tp, 0x070c, csi | bits);
4727 }
4728
4729 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4730 {
4731 rtl_csi_access_enable(tp, 0x17000000);
4732 }
4733
4734 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4735 {
4736 rtl_csi_access_enable(tp, 0x27000000);
4737 }
4738
4739 DECLARE_RTL_COND(rtl_csiar_cond)
4740 {
4741 void __iomem *ioaddr = tp->mmio_addr;
4742
4743 return RTL_R32(CSIAR) & CSIAR_FLAG;
4744 }
4745
4746 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
4747 {
4748 void __iomem *ioaddr = tp->mmio_addr;
4749
4750 RTL_W32(CSIDR, value);
4751 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4752 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4753
4754 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4755 }
4756
4757 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
4758 {
4759 void __iomem *ioaddr = tp->mmio_addr;
4760
4761 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4762 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4763
4764 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4765 RTL_R32(CSIDR) : ~0;
4766 }
4767
4768 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
4769 {
4770 void __iomem *ioaddr = tp->mmio_addr;
4771
4772 RTL_W32(CSIDR, value);
4773 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4774 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4775 CSIAR_FUNC_NIC);
4776
4777 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4778 }
4779
4780 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
4781 {
4782 void __iomem *ioaddr = tp->mmio_addr;
4783
4784 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4785 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4786
4787 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4788 RTL_R32(CSIDR) : ~0;
4789 }
4790
4791 static void rtl_init_csi_ops(struct rtl8169_private *tp)
4792 {
4793 struct csi_ops *ops = &tp->csi_ops;
4794
4795 switch (tp->mac_version) {
4796 case RTL_GIGA_MAC_VER_01:
4797 case RTL_GIGA_MAC_VER_02:
4798 case RTL_GIGA_MAC_VER_03:
4799 case RTL_GIGA_MAC_VER_04:
4800 case RTL_GIGA_MAC_VER_05:
4801 case RTL_GIGA_MAC_VER_06:
4802 case RTL_GIGA_MAC_VER_10:
4803 case RTL_GIGA_MAC_VER_11:
4804 case RTL_GIGA_MAC_VER_12:
4805 case RTL_GIGA_MAC_VER_13:
4806 case RTL_GIGA_MAC_VER_14:
4807 case RTL_GIGA_MAC_VER_15:
4808 case RTL_GIGA_MAC_VER_16:
4809 case RTL_GIGA_MAC_VER_17:
4810 ops->write = NULL;
4811 ops->read = NULL;
4812 break;
4813
4814 case RTL_GIGA_MAC_VER_37:
4815 case RTL_GIGA_MAC_VER_38:
4816 ops->write = r8402_csi_write;
4817 ops->read = r8402_csi_read;
4818 break;
4819
4820 default:
4821 ops->write = r8169_csi_write;
4822 ops->read = r8169_csi_read;
4823 break;
4824 }
4825 }
4826
4827 struct ephy_info {
4828 unsigned int offset;
4829 u16 mask;
4830 u16 bits;
4831 };
4832
4833 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4834 int len)
4835 {
4836 u16 w;
4837
4838 while (len-- > 0) {
4839 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4840 rtl_ephy_write(tp, e->offset, w);
4841 e++;
4842 }
4843 }
4844
4845 static void rtl_disable_clock_request(struct pci_dev *pdev)
4846 {
4847 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4848 PCI_EXP_LNKCTL_CLKREQ_EN);
4849 }
4850
4851 static void rtl_enable_clock_request(struct pci_dev *pdev)
4852 {
4853 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4854 PCI_EXP_LNKCTL_CLKREQ_EN);
4855 }
4856
4857 #define R8168_CPCMD_QUIRK_MASK (\
4858 EnableBist | \
4859 Mac_dbgo_oe | \
4860 Force_half_dup | \
4861 Force_rxflow_en | \
4862 Force_txflow_en | \
4863 Cxpl_dbg_sel | \
4864 ASF | \
4865 PktCntrDisable | \
4866 Mac_dbgo_sel)
4867
4868 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4869 {
4870 void __iomem *ioaddr = tp->mmio_addr;
4871 struct pci_dev *pdev = tp->pci_dev;
4872
4873 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4874
4875 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4876
4877 if (tp->dev->mtu <= ETH_DATA_LEN) {
4878 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4879 PCI_EXP_DEVCTL_NOSNOOP_EN);
4880 }
4881 }
4882
4883 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4884 {
4885 void __iomem *ioaddr = tp->mmio_addr;
4886
4887 rtl_hw_start_8168bb(tp);
4888
4889 RTL_W8(MaxTxPacketSize, TxPacketMax);
4890
4891 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4892 }
4893
4894 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4895 {
4896 void __iomem *ioaddr = tp->mmio_addr;
4897 struct pci_dev *pdev = tp->pci_dev;
4898
4899 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4900
4901 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4902
4903 if (tp->dev->mtu <= ETH_DATA_LEN)
4904 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4905
4906 rtl_disable_clock_request(pdev);
4907
4908 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4909 }
4910
4911 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4912 {
4913 static const struct ephy_info e_info_8168cp[] = {
4914 { 0x01, 0, 0x0001 },
4915 { 0x02, 0x0800, 0x1000 },
4916 { 0x03, 0, 0x0042 },
4917 { 0x06, 0x0080, 0x0000 },
4918 { 0x07, 0, 0x2000 }
4919 };
4920
4921 rtl_csi_access_enable_2(tp);
4922
4923 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4924
4925 __rtl_hw_start_8168cp(tp);
4926 }
4927
4928 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4929 {
4930 void __iomem *ioaddr = tp->mmio_addr;
4931 struct pci_dev *pdev = tp->pci_dev;
4932
4933 rtl_csi_access_enable_2(tp);
4934
4935 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4936
4937 if (tp->dev->mtu <= ETH_DATA_LEN)
4938 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4939
4940 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4941 }
4942
4943 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4944 {
4945 void __iomem *ioaddr = tp->mmio_addr;
4946 struct pci_dev *pdev = tp->pci_dev;
4947
4948 rtl_csi_access_enable_2(tp);
4949
4950 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4951
4952 /* Magic. */
4953 RTL_W8(DBG_REG, 0x20);
4954
4955 RTL_W8(MaxTxPacketSize, TxPacketMax);
4956
4957 if (tp->dev->mtu <= ETH_DATA_LEN)
4958 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4959
4960 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4961 }
4962
4963 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4964 {
4965 void __iomem *ioaddr = tp->mmio_addr;
4966 static const struct ephy_info e_info_8168c_1[] = {
4967 { 0x02, 0x0800, 0x1000 },
4968 { 0x03, 0, 0x0002 },
4969 { 0x06, 0x0080, 0x0000 }
4970 };
4971
4972 rtl_csi_access_enable_2(tp);
4973
4974 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4975
4976 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4977
4978 __rtl_hw_start_8168cp(tp);
4979 }
4980
4981 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4982 {
4983 static const struct ephy_info e_info_8168c_2[] = {
4984 { 0x01, 0, 0x0001 },
4985 { 0x03, 0x0400, 0x0220 }
4986 };
4987
4988 rtl_csi_access_enable_2(tp);
4989
4990 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4991
4992 __rtl_hw_start_8168cp(tp);
4993 }
4994
4995 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4996 {
4997 rtl_hw_start_8168c_2(tp);
4998 }
4999
5000 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5001 {
5002 rtl_csi_access_enable_2(tp);
5003
5004 __rtl_hw_start_8168cp(tp);
5005 }
5006
5007 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5008 {
5009 void __iomem *ioaddr = tp->mmio_addr;
5010 struct pci_dev *pdev = tp->pci_dev;
5011
5012 rtl_csi_access_enable_2(tp);
5013
5014 rtl_disable_clock_request(pdev);
5015
5016 RTL_W8(MaxTxPacketSize, TxPacketMax);
5017
5018 if (tp->dev->mtu <= ETH_DATA_LEN)
5019 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5020
5021 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5022 }
5023
5024 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5025 {
5026 void __iomem *ioaddr = tp->mmio_addr;
5027 struct pci_dev *pdev = tp->pci_dev;
5028
5029 rtl_csi_access_enable_1(tp);
5030
5031 if (tp->dev->mtu <= ETH_DATA_LEN)
5032 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5033
5034 RTL_W8(MaxTxPacketSize, TxPacketMax);
5035
5036 rtl_disable_clock_request(pdev);
5037 }
5038
5039 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5040 {
5041 void __iomem *ioaddr = tp->mmio_addr;
5042 struct pci_dev *pdev = tp->pci_dev;
5043 static const struct ephy_info e_info_8168d_4[] = {
5044 { 0x0b, ~0, 0x48 },
5045 { 0x19, 0x20, 0x50 },
5046 { 0x0c, ~0, 0x20 }
5047 };
5048 int i;
5049
5050 rtl_csi_access_enable_1(tp);
5051
5052 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5053
5054 RTL_W8(MaxTxPacketSize, TxPacketMax);
5055
5056 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5057 const struct ephy_info *e = e_info_8168d_4 + i;
5058 u16 w;
5059
5060 w = rtl_ephy_read(tp, e->offset);
5061 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5062 }
5063
5064 rtl_enable_clock_request(pdev);
5065 }
5066
5067 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5068 {
5069 void __iomem *ioaddr = tp->mmio_addr;
5070 struct pci_dev *pdev = tp->pci_dev;
5071 static const struct ephy_info e_info_8168e_1[] = {
5072 { 0x00, 0x0200, 0x0100 },
5073 { 0x00, 0x0000, 0x0004 },
5074 { 0x06, 0x0002, 0x0001 },
5075 { 0x06, 0x0000, 0x0030 },
5076 { 0x07, 0x0000, 0x2000 },
5077 { 0x00, 0x0000, 0x0020 },
5078 { 0x03, 0x5800, 0x2000 },
5079 { 0x03, 0x0000, 0x0001 },
5080 { 0x01, 0x0800, 0x1000 },
5081 { 0x07, 0x0000, 0x4000 },
5082 { 0x1e, 0x0000, 0x2000 },
5083 { 0x19, 0xffff, 0xfe6c },
5084 { 0x0a, 0x0000, 0x0040 }
5085 };
5086
5087 rtl_csi_access_enable_2(tp);
5088
5089 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5090
5091 if (tp->dev->mtu <= ETH_DATA_LEN)
5092 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5093
5094 RTL_W8(MaxTxPacketSize, TxPacketMax);
5095
5096 rtl_disable_clock_request(pdev);
5097
5098 /* Reset tx FIFO pointer */
5099 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5100 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5101
5102 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5103 }
5104
5105 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5106 {
5107 void __iomem *ioaddr = tp->mmio_addr;
5108 struct pci_dev *pdev = tp->pci_dev;
5109 static const struct ephy_info e_info_8168e_2[] = {
5110 { 0x09, 0x0000, 0x0080 },
5111 { 0x19, 0x0000, 0x0224 }
5112 };
5113
5114 rtl_csi_access_enable_1(tp);
5115
5116 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5117
5118 if (tp->dev->mtu <= ETH_DATA_LEN)
5119 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5120
5121 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5122 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5123 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5124 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5125 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5126 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5127 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5128 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5129
5130 RTL_W8(MaxTxPacketSize, EarlySize);
5131
5132 rtl_disable_clock_request(pdev);
5133
5134 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5135 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5136
5137 /* Adjust EEE LED frequency */
5138 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5139
5140 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5141 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5142 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5143 }
5144
5145 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5146 {
5147 void __iomem *ioaddr = tp->mmio_addr;
5148 struct pci_dev *pdev = tp->pci_dev;
5149
5150 rtl_csi_access_enable_2(tp);
5151
5152 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5153
5154 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5155 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5156 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5157 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5158 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5159 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5160 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5161 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5162 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5163 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5164
5165 RTL_W8(MaxTxPacketSize, EarlySize);
5166
5167 rtl_disable_clock_request(pdev);
5168
5169 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5170 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5171 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5172 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5173 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5174 }
5175
5176 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5177 {
5178 void __iomem *ioaddr = tp->mmio_addr;
5179 static const struct ephy_info e_info_8168f_1[] = {
5180 { 0x06, 0x00c0, 0x0020 },
5181 { 0x08, 0x0001, 0x0002 },
5182 { 0x09, 0x0000, 0x0080 },
5183 { 0x19, 0x0000, 0x0224 }
5184 };
5185
5186 rtl_hw_start_8168f(tp);
5187
5188 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5189
5190 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5191
5192 /* Adjust EEE LED frequency */
5193 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5194 }
5195
5196 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5197 {
5198 static const struct ephy_info e_info_8168f_1[] = {
5199 { 0x06, 0x00c0, 0x0020 },
5200 { 0x0f, 0xffff, 0x5200 },
5201 { 0x1e, 0x0000, 0x4000 },
5202 { 0x19, 0x0000, 0x0224 }
5203 };
5204
5205 rtl_hw_start_8168f(tp);
5206
5207 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5208
5209 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5210 }
5211
5212 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5213 {
5214 void __iomem *ioaddr = tp->mmio_addr;
5215 struct pci_dev *pdev = tp->pci_dev;
5216
5217 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5218
5219 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5220 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5221 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5222 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5223
5224 rtl_csi_access_enable_1(tp);
5225
5226 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5227
5228 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5229 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5230 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5231
5232 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5233 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5234 RTL_W8(MaxTxPacketSize, EarlySize);
5235
5236 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5237 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5238
5239 /* Adjust EEE LED frequency */
5240 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5241
5242 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5243 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5244 }
5245
5246 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5247 {
5248 void __iomem *ioaddr = tp->mmio_addr;
5249 static const struct ephy_info e_info_8168g_2[] = {
5250 { 0x00, 0x0000, 0x0008 },
5251 { 0x0c, 0x3df0, 0x0200 },
5252 { 0x19, 0xffff, 0xfc00 },
5253 { 0x1e, 0xffff, 0x20eb }
5254 };
5255
5256 rtl_hw_start_8168g_1(tp);
5257
5258 /* disable aspm and clock request before access ephy */
5259 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5260 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5261 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5262 }
5263
5264 static void rtl_hw_start_8168(struct net_device *dev)
5265 {
5266 struct rtl8169_private *tp = netdev_priv(dev);
5267 void __iomem *ioaddr = tp->mmio_addr;
5268
5269 RTL_W8(Cfg9346, Cfg9346_Unlock);
5270
5271 RTL_W8(MaxTxPacketSize, TxPacketMax);
5272
5273 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5274
5275 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5276
5277 RTL_W16(CPlusCmd, tp->cp_cmd);
5278
5279 RTL_W16(IntrMitigate, 0x5151);
5280
5281 /* Work around for RxFIFO overflow. */
5282 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5283 tp->event_slow |= RxFIFOOver | PCSTimeout;
5284 tp->event_slow &= ~RxOverflow;
5285 }
5286
5287 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5288
5289 rtl_set_rx_tx_config_registers(tp);
5290
5291 RTL_R8(IntrMask);
5292
5293 switch (tp->mac_version) {
5294 case RTL_GIGA_MAC_VER_11:
5295 rtl_hw_start_8168bb(tp);
5296 break;
5297
5298 case RTL_GIGA_MAC_VER_12:
5299 case RTL_GIGA_MAC_VER_17:
5300 rtl_hw_start_8168bef(tp);
5301 break;
5302
5303 case RTL_GIGA_MAC_VER_18:
5304 rtl_hw_start_8168cp_1(tp);
5305 break;
5306
5307 case RTL_GIGA_MAC_VER_19:
5308 rtl_hw_start_8168c_1(tp);
5309 break;
5310
5311 case RTL_GIGA_MAC_VER_20:
5312 rtl_hw_start_8168c_2(tp);
5313 break;
5314
5315 case RTL_GIGA_MAC_VER_21:
5316 rtl_hw_start_8168c_3(tp);
5317 break;
5318
5319 case RTL_GIGA_MAC_VER_22:
5320 rtl_hw_start_8168c_4(tp);
5321 break;
5322
5323 case RTL_GIGA_MAC_VER_23:
5324 rtl_hw_start_8168cp_2(tp);
5325 break;
5326
5327 case RTL_GIGA_MAC_VER_24:
5328 rtl_hw_start_8168cp_3(tp);
5329 break;
5330
5331 case RTL_GIGA_MAC_VER_25:
5332 case RTL_GIGA_MAC_VER_26:
5333 case RTL_GIGA_MAC_VER_27:
5334 rtl_hw_start_8168d(tp);
5335 break;
5336
5337 case RTL_GIGA_MAC_VER_28:
5338 rtl_hw_start_8168d_4(tp);
5339 break;
5340
5341 case RTL_GIGA_MAC_VER_31:
5342 rtl_hw_start_8168dp(tp);
5343 break;
5344
5345 case RTL_GIGA_MAC_VER_32:
5346 case RTL_GIGA_MAC_VER_33:
5347 rtl_hw_start_8168e_1(tp);
5348 break;
5349 case RTL_GIGA_MAC_VER_34:
5350 rtl_hw_start_8168e_2(tp);
5351 break;
5352
5353 case RTL_GIGA_MAC_VER_35:
5354 case RTL_GIGA_MAC_VER_36:
5355 rtl_hw_start_8168f_1(tp);
5356 break;
5357
5358 case RTL_GIGA_MAC_VER_38:
5359 rtl_hw_start_8411(tp);
5360 break;
5361
5362 case RTL_GIGA_MAC_VER_40:
5363 case RTL_GIGA_MAC_VER_41:
5364 rtl_hw_start_8168g_1(tp);
5365 break;
5366 case RTL_GIGA_MAC_VER_42:
5367 rtl_hw_start_8168g_2(tp);
5368 break;
5369
5370 default:
5371 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5372 dev->name, tp->mac_version);
5373 break;
5374 }
5375
5376 RTL_W8(Cfg9346, Cfg9346_Lock);
5377
5378 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5379
5380 rtl_set_rx_mode(dev);
5381
5382 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5383 }
5384
5385 #define R810X_CPCMD_QUIRK_MASK (\
5386 EnableBist | \
5387 Mac_dbgo_oe | \
5388 Force_half_dup | \
5389 Force_rxflow_en | \
5390 Force_txflow_en | \
5391 Cxpl_dbg_sel | \
5392 ASF | \
5393 PktCntrDisable | \
5394 Mac_dbgo_sel)
5395
5396 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5397 {
5398 void __iomem *ioaddr = tp->mmio_addr;
5399 struct pci_dev *pdev = tp->pci_dev;
5400 static const struct ephy_info e_info_8102e_1[] = {
5401 { 0x01, 0, 0x6e65 },
5402 { 0x02, 0, 0x091f },
5403 { 0x03, 0, 0xc2f9 },
5404 { 0x06, 0, 0xafb5 },
5405 { 0x07, 0, 0x0e00 },
5406 { 0x19, 0, 0xec80 },
5407 { 0x01, 0, 0x2e65 },
5408 { 0x01, 0, 0x6e65 }
5409 };
5410 u8 cfg1;
5411
5412 rtl_csi_access_enable_2(tp);
5413
5414 RTL_W8(DBG_REG, FIX_NAK_1);
5415
5416 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5417
5418 RTL_W8(Config1,
5419 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5420 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5421
5422 cfg1 = RTL_R8(Config1);
5423 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5424 RTL_W8(Config1, cfg1 & ~LEDS0);
5425
5426 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5427 }
5428
5429 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5430 {
5431 void __iomem *ioaddr = tp->mmio_addr;
5432 struct pci_dev *pdev = tp->pci_dev;
5433
5434 rtl_csi_access_enable_2(tp);
5435
5436 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5437
5438 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5439 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5440 }
5441
5442 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5443 {
5444 rtl_hw_start_8102e_2(tp);
5445
5446 rtl_ephy_write(tp, 0x03, 0xc2f9);
5447 }
5448
5449 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5450 {
5451 void __iomem *ioaddr = tp->mmio_addr;
5452 static const struct ephy_info e_info_8105e_1[] = {
5453 { 0x07, 0, 0x4000 },
5454 { 0x19, 0, 0x0200 },
5455 { 0x19, 0, 0x0020 },
5456 { 0x1e, 0, 0x2000 },
5457 { 0x03, 0, 0x0001 },
5458 { 0x19, 0, 0x0100 },
5459 { 0x19, 0, 0x0004 },
5460 { 0x0a, 0, 0x0020 }
5461 };
5462
5463 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5464 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5465
5466 /* Disable Early Tally Counter */
5467 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5468
5469 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5470 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5471
5472 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5473 }
5474
5475 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5476 {
5477 rtl_hw_start_8105e_1(tp);
5478 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5479 }
5480
5481 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5482 {
5483 void __iomem *ioaddr = tp->mmio_addr;
5484 static const struct ephy_info e_info_8402[] = {
5485 { 0x19, 0xffff, 0xff64 },
5486 { 0x1e, 0, 0x4000 }
5487 };
5488
5489 rtl_csi_access_enable_2(tp);
5490
5491 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5492 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5493
5494 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5495 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5496
5497 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5498
5499 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5500
5501 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5502 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5503 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5504 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5505 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5506 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5507 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5508 }
5509
5510 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5511 {
5512 void __iomem *ioaddr = tp->mmio_addr;
5513
5514 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5515 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5516
5517 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5518 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5519 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5520 }
5521
5522 static void rtl_hw_start_8101(struct net_device *dev)
5523 {
5524 struct rtl8169_private *tp = netdev_priv(dev);
5525 void __iomem *ioaddr = tp->mmio_addr;
5526 struct pci_dev *pdev = tp->pci_dev;
5527
5528 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5529 tp->event_slow &= ~RxFIFOOver;
5530
5531 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5532 tp->mac_version == RTL_GIGA_MAC_VER_16)
5533 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5534 PCI_EXP_DEVCTL_NOSNOOP_EN);
5535
5536 RTL_W8(Cfg9346, Cfg9346_Unlock);
5537
5538 RTL_W8(MaxTxPacketSize, TxPacketMax);
5539
5540 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5541
5542 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5543 RTL_W16(CPlusCmd, tp->cp_cmd);
5544
5545 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5546
5547 rtl_set_rx_tx_config_registers(tp);
5548
5549 switch (tp->mac_version) {
5550 case RTL_GIGA_MAC_VER_07:
5551 rtl_hw_start_8102e_1(tp);
5552 break;
5553
5554 case RTL_GIGA_MAC_VER_08:
5555 rtl_hw_start_8102e_3(tp);
5556 break;
5557
5558 case RTL_GIGA_MAC_VER_09:
5559 rtl_hw_start_8102e_2(tp);
5560 break;
5561
5562 case RTL_GIGA_MAC_VER_29:
5563 rtl_hw_start_8105e_1(tp);
5564 break;
5565 case RTL_GIGA_MAC_VER_30:
5566 rtl_hw_start_8105e_2(tp);
5567 break;
5568
5569 case RTL_GIGA_MAC_VER_37:
5570 rtl_hw_start_8402(tp);
5571 break;
5572
5573 case RTL_GIGA_MAC_VER_39:
5574 rtl_hw_start_8106(tp);
5575 break;
5576 case RTL_GIGA_MAC_VER_43:
5577 rtl_hw_start_8168g_2(tp);
5578 break;
5579 }
5580
5581 RTL_W8(Cfg9346, Cfg9346_Lock);
5582
5583 RTL_W16(IntrMitigate, 0x0000);
5584
5585 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5586
5587 rtl_set_rx_mode(dev);
5588
5589 RTL_R8(IntrMask);
5590
5591 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5592 }
5593
5594 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5595 {
5596 struct rtl8169_private *tp = netdev_priv(dev);
5597
5598 if (new_mtu < ETH_ZLEN ||
5599 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5600 return -EINVAL;
5601
5602 if (new_mtu > ETH_DATA_LEN)
5603 rtl_hw_jumbo_enable(tp);
5604 else
5605 rtl_hw_jumbo_disable(tp);
5606
5607 dev->mtu = new_mtu;
5608 netdev_update_features(dev);
5609
5610 return 0;
5611 }
5612
5613 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5614 {
5615 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5616 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5617 }
5618
5619 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5620 void **data_buff, struct RxDesc *desc)
5621 {
5622 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5623 DMA_FROM_DEVICE);
5624
5625 kfree(*data_buff);
5626 *data_buff = NULL;
5627 rtl8169_make_unusable_by_asic(desc);
5628 }
5629
5630 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5631 {
5632 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5633
5634 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5635 }
5636
5637 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5638 u32 rx_buf_sz)
5639 {
5640 desc->addr = cpu_to_le64(mapping);
5641 wmb();
5642 rtl8169_mark_to_asic(desc, rx_buf_sz);
5643 }
5644
5645 static inline void *rtl8169_align(void *data)
5646 {
5647 return (void *)ALIGN((long)data, 16);
5648 }
5649
5650 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5651 struct RxDesc *desc)
5652 {
5653 void *data;
5654 dma_addr_t mapping;
5655 struct device *d = &tp->pci_dev->dev;
5656 struct net_device *dev = tp->dev;
5657 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5658
5659 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5660 if (!data)
5661 return NULL;
5662
5663 if (rtl8169_align(data) != data) {
5664 kfree(data);
5665 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5666 if (!data)
5667 return NULL;
5668 }
5669
5670 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5671 DMA_FROM_DEVICE);
5672 if (unlikely(dma_mapping_error(d, mapping))) {
5673 if (net_ratelimit())
5674 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5675 goto err_out;
5676 }
5677
5678 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5679 return data;
5680
5681 err_out:
5682 kfree(data);
5683 return NULL;
5684 }
5685
5686 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5687 {
5688 unsigned int i;
5689
5690 for (i = 0; i < NUM_RX_DESC; i++) {
5691 if (tp->Rx_databuff[i]) {
5692 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5693 tp->RxDescArray + i);
5694 }
5695 }
5696 }
5697
5698 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5699 {
5700 desc->opts1 |= cpu_to_le32(RingEnd);
5701 }
5702
5703 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5704 {
5705 unsigned int i;
5706
5707 for (i = 0; i < NUM_RX_DESC; i++) {
5708 void *data;
5709
5710 if (tp->Rx_databuff[i])
5711 continue;
5712
5713 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5714 if (!data) {
5715 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5716 goto err_out;
5717 }
5718 tp->Rx_databuff[i] = data;
5719 }
5720
5721 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5722 return 0;
5723
5724 err_out:
5725 rtl8169_rx_clear(tp);
5726 return -ENOMEM;
5727 }
5728
5729 static int rtl8169_init_ring(struct net_device *dev)
5730 {
5731 struct rtl8169_private *tp = netdev_priv(dev);
5732
5733 rtl8169_init_ring_indexes(tp);
5734
5735 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5736 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5737
5738 return rtl8169_rx_fill(tp);
5739 }
5740
5741 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5742 struct TxDesc *desc)
5743 {
5744 unsigned int len = tx_skb->len;
5745
5746 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5747
5748 desc->opts1 = 0x00;
5749 desc->opts2 = 0x00;
5750 desc->addr = 0x00;
5751 tx_skb->len = 0;
5752 }
5753
5754 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5755 unsigned int n)
5756 {
5757 unsigned int i;
5758
5759 for (i = 0; i < n; i++) {
5760 unsigned int entry = (start + i) % NUM_TX_DESC;
5761 struct ring_info *tx_skb = tp->tx_skb + entry;
5762 unsigned int len = tx_skb->len;
5763
5764 if (len) {
5765 struct sk_buff *skb = tx_skb->skb;
5766
5767 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5768 tp->TxDescArray + entry);
5769 if (skb) {
5770 tp->dev->stats.tx_dropped++;
5771 dev_kfree_skb_any(skb);
5772 tx_skb->skb = NULL;
5773 }
5774 }
5775 }
5776 }
5777
5778 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5779 {
5780 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5781 tp->cur_tx = tp->dirty_tx = 0;
5782 }
5783
5784 static void rtl_reset_work(struct rtl8169_private *tp)
5785 {
5786 struct net_device *dev = tp->dev;
5787 int i;
5788
5789 napi_disable(&tp->napi);
5790 netif_stop_queue(dev);
5791 synchronize_sched();
5792
5793 rtl8169_hw_reset(tp);
5794
5795 for (i = 0; i < NUM_RX_DESC; i++)
5796 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5797
5798 rtl8169_tx_clear(tp);
5799 rtl8169_init_ring_indexes(tp);
5800
5801 napi_enable(&tp->napi);
5802 rtl_hw_start(dev);
5803 netif_wake_queue(dev);
5804 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5805 }
5806
5807 static void rtl8169_tx_timeout(struct net_device *dev)
5808 {
5809 struct rtl8169_private *tp = netdev_priv(dev);
5810
5811 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5812 }
5813
5814 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5815 u32 *opts)
5816 {
5817 struct skb_shared_info *info = skb_shinfo(skb);
5818 unsigned int cur_frag, entry;
5819 struct TxDesc * uninitialized_var(txd);
5820 struct device *d = &tp->pci_dev->dev;
5821
5822 entry = tp->cur_tx;
5823 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5824 const skb_frag_t *frag = info->frags + cur_frag;
5825 dma_addr_t mapping;
5826 u32 status, len;
5827 void *addr;
5828
5829 entry = (entry + 1) % NUM_TX_DESC;
5830
5831 txd = tp->TxDescArray + entry;
5832 len = skb_frag_size(frag);
5833 addr = skb_frag_address(frag);
5834 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5835 if (unlikely(dma_mapping_error(d, mapping))) {
5836 if (net_ratelimit())
5837 netif_err(tp, drv, tp->dev,
5838 "Failed to map TX fragments DMA!\n");
5839 goto err_out;
5840 }
5841
5842 /* Anti gcc 2.95.3 bugware (sic) */
5843 status = opts[0] | len |
5844 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5845
5846 txd->opts1 = cpu_to_le32(status);
5847 txd->opts2 = cpu_to_le32(opts[1]);
5848 txd->addr = cpu_to_le64(mapping);
5849
5850 tp->tx_skb[entry].len = len;
5851 }
5852
5853 if (cur_frag) {
5854 tp->tx_skb[entry].skb = skb;
5855 txd->opts1 |= cpu_to_le32(LastFrag);
5856 }
5857
5858 return cur_frag;
5859
5860 err_out:
5861 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5862 return -EIO;
5863 }
5864
5865 static bool rtl_skb_pad(struct sk_buff *skb)
5866 {
5867 if (skb_padto(skb, ETH_ZLEN))
5868 return false;
5869 skb_put(skb, ETH_ZLEN - skb->len);
5870 return true;
5871 }
5872
5873 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5874 {
5875 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5876 }
5877
5878 static inline bool rtl8169_tso_csum(struct rtl8169_private *tp,
5879 struct sk_buff *skb, u32 *opts)
5880 {
5881 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5882 u32 mss = skb_shinfo(skb)->gso_size;
5883 int offset = info->opts_offset;
5884
5885 if (mss) {
5886 opts[0] |= TD_LSO;
5887 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5888 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5889 const struct iphdr *ip = ip_hdr(skb);
5890
5891 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5892 return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
5893
5894 if (ip->protocol == IPPROTO_TCP)
5895 opts[offset] |= info->checksum.tcp;
5896 else if (ip->protocol == IPPROTO_UDP)
5897 opts[offset] |= info->checksum.udp;
5898 else
5899 WARN_ON_ONCE(1);
5900 } else {
5901 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5902 return rtl_skb_pad(skb);
5903 }
5904 return true;
5905 }
5906
5907 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5908 struct net_device *dev)
5909 {
5910 struct rtl8169_private *tp = netdev_priv(dev);
5911 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5912 struct TxDesc *txd = tp->TxDescArray + entry;
5913 void __iomem *ioaddr = tp->mmio_addr;
5914 struct device *d = &tp->pci_dev->dev;
5915 dma_addr_t mapping;
5916 u32 status, len;
5917 u32 opts[2];
5918 int frags;
5919
5920 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5921 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5922 goto err_stop_0;
5923 }
5924
5925 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5926 goto err_stop_0;
5927
5928 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5929 opts[0] = DescOwn;
5930
5931 if (!rtl8169_tso_csum(tp, skb, opts))
5932 goto err_update_stats;
5933
5934 len = skb_headlen(skb);
5935 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5936 if (unlikely(dma_mapping_error(d, mapping))) {
5937 if (net_ratelimit())
5938 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5939 goto err_dma_0;
5940 }
5941
5942 tp->tx_skb[entry].len = len;
5943 txd->addr = cpu_to_le64(mapping);
5944
5945 frags = rtl8169_xmit_frags(tp, skb, opts);
5946 if (frags < 0)
5947 goto err_dma_1;
5948 else if (frags)
5949 opts[0] |= FirstFrag;
5950 else {
5951 opts[0] |= FirstFrag | LastFrag;
5952 tp->tx_skb[entry].skb = skb;
5953 }
5954
5955 txd->opts2 = cpu_to_le32(opts[1]);
5956
5957 skb_tx_timestamp(skb);
5958
5959 wmb();
5960
5961 /* Anti gcc 2.95.3 bugware (sic) */
5962 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5963 txd->opts1 = cpu_to_le32(status);
5964
5965 tp->cur_tx += frags + 1;
5966
5967 wmb();
5968
5969 RTL_W8(TxPoll, NPQ);
5970
5971 mmiowb();
5972
5973 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5974 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5975 * not miss a ring update when it notices a stopped queue.
5976 */
5977 smp_wmb();
5978 netif_stop_queue(dev);
5979 /* Sync with rtl_tx:
5980 * - publish queue status and cur_tx ring index (write barrier)
5981 * - refresh dirty_tx ring index (read barrier).
5982 * May the current thread have a pessimistic view of the ring
5983 * status and forget to wake up queue, a racing rtl_tx thread
5984 * can't.
5985 */
5986 smp_mb();
5987 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5988 netif_wake_queue(dev);
5989 }
5990
5991 return NETDEV_TX_OK;
5992
5993 err_dma_1:
5994 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5995 err_dma_0:
5996 dev_kfree_skb_any(skb);
5997 err_update_stats:
5998 dev->stats.tx_dropped++;
5999 return NETDEV_TX_OK;
6000
6001 err_stop_0:
6002 netif_stop_queue(dev);
6003 dev->stats.tx_dropped++;
6004 return NETDEV_TX_BUSY;
6005 }
6006
6007 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6008 {
6009 struct rtl8169_private *tp = netdev_priv(dev);
6010 struct pci_dev *pdev = tp->pci_dev;
6011 u16 pci_status, pci_cmd;
6012
6013 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6014 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6015
6016 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6017 pci_cmd, pci_status);
6018
6019 /*
6020 * The recovery sequence below admits a very elaborated explanation:
6021 * - it seems to work;
6022 * - I did not see what else could be done;
6023 * - it makes iop3xx happy.
6024 *
6025 * Feel free to adjust to your needs.
6026 */
6027 if (pdev->broken_parity_status)
6028 pci_cmd &= ~PCI_COMMAND_PARITY;
6029 else
6030 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6031
6032 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6033
6034 pci_write_config_word(pdev, PCI_STATUS,
6035 pci_status & (PCI_STATUS_DETECTED_PARITY |
6036 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6037 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6038
6039 /* The infamous DAC f*ckup only happens at boot time */
6040 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6041 void __iomem *ioaddr = tp->mmio_addr;
6042
6043 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6044 tp->cp_cmd &= ~PCIDAC;
6045 RTL_W16(CPlusCmd, tp->cp_cmd);
6046 dev->features &= ~NETIF_F_HIGHDMA;
6047 }
6048
6049 rtl8169_hw_reset(tp);
6050
6051 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6052 }
6053
6054 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6055 {
6056 unsigned int dirty_tx, tx_left;
6057
6058 dirty_tx = tp->dirty_tx;
6059 smp_rmb();
6060 tx_left = tp->cur_tx - dirty_tx;
6061
6062 while (tx_left > 0) {
6063 unsigned int entry = dirty_tx % NUM_TX_DESC;
6064 struct ring_info *tx_skb = tp->tx_skb + entry;
6065 u32 status;
6066
6067 rmb();
6068 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6069 if (status & DescOwn)
6070 break;
6071
6072 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6073 tp->TxDescArray + entry);
6074 if (status & LastFrag) {
6075 u64_stats_update_begin(&tp->tx_stats.syncp);
6076 tp->tx_stats.packets++;
6077 tp->tx_stats.bytes += tx_skb->skb->len;
6078 u64_stats_update_end(&tp->tx_stats.syncp);
6079 dev_kfree_skb_any(tx_skb->skb);
6080 tx_skb->skb = NULL;
6081 }
6082 dirty_tx++;
6083 tx_left--;
6084 }
6085
6086 if (tp->dirty_tx != dirty_tx) {
6087 tp->dirty_tx = dirty_tx;
6088 /* Sync with rtl8169_start_xmit:
6089 * - publish dirty_tx ring index (write barrier)
6090 * - refresh cur_tx ring index and queue status (read barrier)
6091 * May the current thread miss the stopped queue condition,
6092 * a racing xmit thread can only have a right view of the
6093 * ring status.
6094 */
6095 smp_mb();
6096 if (netif_queue_stopped(dev) &&
6097 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6098 netif_wake_queue(dev);
6099 }
6100 /*
6101 * 8168 hack: TxPoll requests are lost when the Tx packets are
6102 * too close. Let's kick an extra TxPoll request when a burst
6103 * of start_xmit activity is detected (if it is not detected,
6104 * it is slow enough). -- FR
6105 */
6106 if (tp->cur_tx != dirty_tx) {
6107 void __iomem *ioaddr = tp->mmio_addr;
6108
6109 RTL_W8(TxPoll, NPQ);
6110 }
6111 }
6112 }
6113
6114 static inline int rtl8169_fragmented_frame(u32 status)
6115 {
6116 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6117 }
6118
6119 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6120 {
6121 u32 status = opts1 & RxProtoMask;
6122
6123 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6124 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6125 skb->ip_summed = CHECKSUM_UNNECESSARY;
6126 else
6127 skb_checksum_none_assert(skb);
6128 }
6129
6130 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6131 struct rtl8169_private *tp,
6132 int pkt_size,
6133 dma_addr_t addr)
6134 {
6135 struct sk_buff *skb;
6136 struct device *d = &tp->pci_dev->dev;
6137
6138 data = rtl8169_align(data);
6139 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6140 prefetch(data);
6141 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6142 if (skb)
6143 memcpy(skb->data, data, pkt_size);
6144 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6145
6146 return skb;
6147 }
6148
6149 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6150 {
6151 unsigned int cur_rx, rx_left;
6152 unsigned int count;
6153
6154 cur_rx = tp->cur_rx;
6155
6156 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6157 unsigned int entry = cur_rx % NUM_RX_DESC;
6158 struct RxDesc *desc = tp->RxDescArray + entry;
6159 u32 status;
6160
6161 rmb();
6162 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
6163
6164 if (status & DescOwn)
6165 break;
6166 if (unlikely(status & RxRES)) {
6167 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6168 status);
6169 dev->stats.rx_errors++;
6170 if (status & (RxRWT | RxRUNT))
6171 dev->stats.rx_length_errors++;
6172 if (status & RxCRC)
6173 dev->stats.rx_crc_errors++;
6174 if (status & RxFOVF) {
6175 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6176 dev->stats.rx_fifo_errors++;
6177 }
6178 if ((status & (RxRUNT | RxCRC)) &&
6179 !(status & (RxRWT | RxFOVF)) &&
6180 (dev->features & NETIF_F_RXALL))
6181 goto process_pkt;
6182 } else {
6183 struct sk_buff *skb;
6184 dma_addr_t addr;
6185 int pkt_size;
6186
6187 process_pkt:
6188 addr = le64_to_cpu(desc->addr);
6189 if (likely(!(dev->features & NETIF_F_RXFCS)))
6190 pkt_size = (status & 0x00003fff) - 4;
6191 else
6192 pkt_size = status & 0x00003fff;
6193
6194 /*
6195 * The driver does not support incoming fragmented
6196 * frames. They are seen as a symptom of over-mtu
6197 * sized frames.
6198 */
6199 if (unlikely(rtl8169_fragmented_frame(status))) {
6200 dev->stats.rx_dropped++;
6201 dev->stats.rx_length_errors++;
6202 goto release_descriptor;
6203 }
6204
6205 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6206 tp, pkt_size, addr);
6207 if (!skb) {
6208 dev->stats.rx_dropped++;
6209 goto release_descriptor;
6210 }
6211
6212 rtl8169_rx_csum(skb, status);
6213 skb_put(skb, pkt_size);
6214 skb->protocol = eth_type_trans(skb, dev);
6215
6216 rtl8169_rx_vlan_tag(desc, skb);
6217
6218 napi_gro_receive(&tp->napi, skb);
6219
6220 u64_stats_update_begin(&tp->rx_stats.syncp);
6221 tp->rx_stats.packets++;
6222 tp->rx_stats.bytes += pkt_size;
6223 u64_stats_update_end(&tp->rx_stats.syncp);
6224 }
6225 release_descriptor:
6226 desc->opts2 = 0;
6227 wmb();
6228 rtl8169_mark_to_asic(desc, rx_buf_sz);
6229 }
6230
6231 count = cur_rx - tp->cur_rx;
6232 tp->cur_rx = cur_rx;
6233
6234 return count;
6235 }
6236
6237 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6238 {
6239 struct net_device *dev = dev_instance;
6240 struct rtl8169_private *tp = netdev_priv(dev);
6241 int handled = 0;
6242 u16 status;
6243
6244 status = rtl_get_events(tp);
6245 if (status && status != 0xffff) {
6246 status &= RTL_EVENT_NAPI | tp->event_slow;
6247 if (status) {
6248 handled = 1;
6249
6250 rtl_irq_disable(tp);
6251 napi_schedule(&tp->napi);
6252 }
6253 }
6254 return IRQ_RETVAL(handled);
6255 }
6256
6257 /*
6258 * Workqueue context.
6259 */
6260 static void rtl_slow_event_work(struct rtl8169_private *tp)
6261 {
6262 struct net_device *dev = tp->dev;
6263 u16 status;
6264
6265 status = rtl_get_events(tp) & tp->event_slow;
6266 rtl_ack_events(tp, status);
6267
6268 if (unlikely(status & RxFIFOOver)) {
6269 switch (tp->mac_version) {
6270 /* Work around for rx fifo overflow */
6271 case RTL_GIGA_MAC_VER_11:
6272 netif_stop_queue(dev);
6273 /* XXX - Hack alert. See rtl_task(). */
6274 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6275 default:
6276 break;
6277 }
6278 }
6279
6280 if (unlikely(status & SYSErr))
6281 rtl8169_pcierr_interrupt(dev);
6282
6283 if (status & LinkChg)
6284 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6285
6286 rtl_irq_enable_all(tp);
6287 }
6288
6289 static void rtl_task(struct work_struct *work)
6290 {
6291 static const struct {
6292 int bitnr;
6293 void (*action)(struct rtl8169_private *);
6294 } rtl_work[] = {
6295 /* XXX - keep rtl_slow_event_work() as first element. */
6296 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6297 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6298 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6299 };
6300 struct rtl8169_private *tp =
6301 container_of(work, struct rtl8169_private, wk.work);
6302 struct net_device *dev = tp->dev;
6303 int i;
6304
6305 rtl_lock_work(tp);
6306
6307 if (!netif_running(dev) ||
6308 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6309 goto out_unlock;
6310
6311 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6312 bool pending;
6313
6314 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6315 if (pending)
6316 rtl_work[i].action(tp);
6317 }
6318
6319 out_unlock:
6320 rtl_unlock_work(tp);
6321 }
6322
6323 static int rtl8169_poll(struct napi_struct *napi, int budget)
6324 {
6325 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6326 struct net_device *dev = tp->dev;
6327 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6328 int work_done= 0;
6329 u16 status;
6330
6331 status = rtl_get_events(tp);
6332 rtl_ack_events(tp, status & ~tp->event_slow);
6333
6334 if (status & RTL_EVENT_NAPI_RX)
6335 work_done = rtl_rx(dev, tp, (u32) budget);
6336
6337 if (status & RTL_EVENT_NAPI_TX)
6338 rtl_tx(dev, tp);
6339
6340 if (status & tp->event_slow) {
6341 enable_mask &= ~tp->event_slow;
6342
6343 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6344 }
6345
6346 if (work_done < budget) {
6347 napi_complete(napi);
6348
6349 rtl_irq_enable(tp, enable_mask);
6350 mmiowb();
6351 }
6352
6353 return work_done;
6354 }
6355
6356 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6357 {
6358 struct rtl8169_private *tp = netdev_priv(dev);
6359
6360 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6361 return;
6362
6363 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6364 RTL_W32(RxMissed, 0);
6365 }
6366
6367 static void rtl8169_down(struct net_device *dev)
6368 {
6369 struct rtl8169_private *tp = netdev_priv(dev);
6370 void __iomem *ioaddr = tp->mmio_addr;
6371
6372 del_timer_sync(&tp->timer);
6373
6374 napi_disable(&tp->napi);
6375 netif_stop_queue(dev);
6376
6377 rtl8169_hw_reset(tp);
6378 /*
6379 * At this point device interrupts can not be enabled in any function,
6380 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6381 * and napi is disabled (rtl8169_poll).
6382 */
6383 rtl8169_rx_missed(dev, ioaddr);
6384
6385 /* Give a racing hard_start_xmit a few cycles to complete. */
6386 synchronize_sched();
6387
6388 rtl8169_tx_clear(tp);
6389
6390 rtl8169_rx_clear(tp);
6391
6392 rtl_pll_power_down(tp);
6393 }
6394
6395 static int rtl8169_close(struct net_device *dev)
6396 {
6397 struct rtl8169_private *tp = netdev_priv(dev);
6398 struct pci_dev *pdev = tp->pci_dev;
6399
6400 pm_runtime_get_sync(&pdev->dev);
6401
6402 /* Update counters before going down */
6403 rtl8169_update_counters(dev);
6404
6405 rtl_lock_work(tp);
6406 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6407
6408 rtl8169_down(dev);
6409 rtl_unlock_work(tp);
6410
6411 free_irq(pdev->irq, dev);
6412
6413 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6414 tp->RxPhyAddr);
6415 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6416 tp->TxPhyAddr);
6417 tp->TxDescArray = NULL;
6418 tp->RxDescArray = NULL;
6419
6420 pm_runtime_put_sync(&pdev->dev);
6421
6422 return 0;
6423 }
6424
6425 #ifdef CONFIG_NET_POLL_CONTROLLER
6426 static void rtl8169_netpoll(struct net_device *dev)
6427 {
6428 struct rtl8169_private *tp = netdev_priv(dev);
6429
6430 rtl8169_interrupt(tp->pci_dev->irq, dev);
6431 }
6432 #endif
6433
6434 static int rtl_open(struct net_device *dev)
6435 {
6436 struct rtl8169_private *tp = netdev_priv(dev);
6437 void __iomem *ioaddr = tp->mmio_addr;
6438 struct pci_dev *pdev = tp->pci_dev;
6439 int retval = -ENOMEM;
6440
6441 pm_runtime_get_sync(&pdev->dev);
6442
6443 /*
6444 * Rx and Tx descriptors needs 256 bytes alignment.
6445 * dma_alloc_coherent provides more.
6446 */
6447 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6448 &tp->TxPhyAddr, GFP_KERNEL);
6449 if (!tp->TxDescArray)
6450 goto err_pm_runtime_put;
6451
6452 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6453 &tp->RxPhyAddr, GFP_KERNEL);
6454 if (!tp->RxDescArray)
6455 goto err_free_tx_0;
6456
6457 retval = rtl8169_init_ring(dev);
6458 if (retval < 0)
6459 goto err_free_rx_1;
6460
6461 INIT_WORK(&tp->wk.work, rtl_task);
6462
6463 smp_mb();
6464
6465 rtl_request_firmware(tp);
6466
6467 retval = request_irq(pdev->irq, rtl8169_interrupt,
6468 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6469 dev->name, dev);
6470 if (retval < 0)
6471 goto err_release_fw_2;
6472
6473 rtl_lock_work(tp);
6474
6475 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6476
6477 napi_enable(&tp->napi);
6478
6479 rtl8169_init_phy(dev, tp);
6480
6481 __rtl8169_set_features(dev, dev->features);
6482
6483 rtl_pll_power_up(tp);
6484
6485 rtl_hw_start(dev);
6486
6487 netif_start_queue(dev);
6488
6489 rtl_unlock_work(tp);
6490
6491 tp->saved_wolopts = 0;
6492 pm_runtime_put_noidle(&pdev->dev);
6493
6494 rtl8169_check_link_status(dev, tp, ioaddr);
6495 out:
6496 return retval;
6497
6498 err_release_fw_2:
6499 rtl_release_firmware(tp);
6500 rtl8169_rx_clear(tp);
6501 err_free_rx_1:
6502 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6503 tp->RxPhyAddr);
6504 tp->RxDescArray = NULL;
6505 err_free_tx_0:
6506 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6507 tp->TxPhyAddr);
6508 tp->TxDescArray = NULL;
6509 err_pm_runtime_put:
6510 pm_runtime_put_noidle(&pdev->dev);
6511 goto out;
6512 }
6513
6514 static struct rtnl_link_stats64 *
6515 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6516 {
6517 struct rtl8169_private *tp = netdev_priv(dev);
6518 void __iomem *ioaddr = tp->mmio_addr;
6519 unsigned int start;
6520
6521 if (netif_running(dev))
6522 rtl8169_rx_missed(dev, ioaddr);
6523
6524 do {
6525 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6526 stats->rx_packets = tp->rx_stats.packets;
6527 stats->rx_bytes = tp->rx_stats.bytes;
6528 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6529
6530
6531 do {
6532 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6533 stats->tx_packets = tp->tx_stats.packets;
6534 stats->tx_bytes = tp->tx_stats.bytes;
6535 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6536
6537 stats->rx_dropped = dev->stats.rx_dropped;
6538 stats->tx_dropped = dev->stats.tx_dropped;
6539 stats->rx_length_errors = dev->stats.rx_length_errors;
6540 stats->rx_errors = dev->stats.rx_errors;
6541 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6542 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6543 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6544
6545 return stats;
6546 }
6547
6548 static void rtl8169_net_suspend(struct net_device *dev)
6549 {
6550 struct rtl8169_private *tp = netdev_priv(dev);
6551
6552 if (!netif_running(dev))
6553 return;
6554
6555 netif_device_detach(dev);
6556 netif_stop_queue(dev);
6557
6558 rtl_lock_work(tp);
6559 napi_disable(&tp->napi);
6560 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6561 rtl_unlock_work(tp);
6562
6563 rtl_pll_power_down(tp);
6564 }
6565
6566 #ifdef CONFIG_PM
6567
6568 static int rtl8169_suspend(struct device *device)
6569 {
6570 struct pci_dev *pdev = to_pci_dev(device);
6571 struct net_device *dev = pci_get_drvdata(pdev);
6572
6573 rtl8169_net_suspend(dev);
6574
6575 return 0;
6576 }
6577
6578 static void __rtl8169_resume(struct net_device *dev)
6579 {
6580 struct rtl8169_private *tp = netdev_priv(dev);
6581
6582 netif_device_attach(dev);
6583
6584 rtl_pll_power_up(tp);
6585
6586 rtl_lock_work(tp);
6587 napi_enable(&tp->napi);
6588 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6589 rtl_unlock_work(tp);
6590
6591 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6592 }
6593
6594 static int rtl8169_resume(struct device *device)
6595 {
6596 struct pci_dev *pdev = to_pci_dev(device);
6597 struct net_device *dev = pci_get_drvdata(pdev);
6598 struct rtl8169_private *tp = netdev_priv(dev);
6599
6600 rtl8169_init_phy(dev, tp);
6601
6602 if (netif_running(dev))
6603 __rtl8169_resume(dev);
6604
6605 return 0;
6606 }
6607
6608 static int rtl8169_runtime_suspend(struct device *device)
6609 {
6610 struct pci_dev *pdev = to_pci_dev(device);
6611 struct net_device *dev = pci_get_drvdata(pdev);
6612 struct rtl8169_private *tp = netdev_priv(dev);
6613
6614 if (!tp->TxDescArray)
6615 return 0;
6616
6617 rtl_lock_work(tp);
6618 tp->saved_wolopts = __rtl8169_get_wol(tp);
6619 __rtl8169_set_wol(tp, WAKE_ANY);
6620 rtl_unlock_work(tp);
6621
6622 rtl8169_net_suspend(dev);
6623
6624 return 0;
6625 }
6626
6627 static int rtl8169_runtime_resume(struct device *device)
6628 {
6629 struct pci_dev *pdev = to_pci_dev(device);
6630 struct net_device *dev = pci_get_drvdata(pdev);
6631 struct rtl8169_private *tp = netdev_priv(dev);
6632
6633 if (!tp->TxDescArray)
6634 return 0;
6635
6636 rtl_lock_work(tp);
6637 __rtl8169_set_wol(tp, tp->saved_wolopts);
6638 tp->saved_wolopts = 0;
6639 rtl_unlock_work(tp);
6640
6641 rtl8169_init_phy(dev, tp);
6642
6643 __rtl8169_resume(dev);
6644
6645 return 0;
6646 }
6647
6648 static int rtl8169_runtime_idle(struct device *device)
6649 {
6650 struct pci_dev *pdev = to_pci_dev(device);
6651 struct net_device *dev = pci_get_drvdata(pdev);
6652 struct rtl8169_private *tp = netdev_priv(dev);
6653
6654 return tp->TxDescArray ? -EBUSY : 0;
6655 }
6656
6657 static const struct dev_pm_ops rtl8169_pm_ops = {
6658 .suspend = rtl8169_suspend,
6659 .resume = rtl8169_resume,
6660 .freeze = rtl8169_suspend,
6661 .thaw = rtl8169_resume,
6662 .poweroff = rtl8169_suspend,
6663 .restore = rtl8169_resume,
6664 .runtime_suspend = rtl8169_runtime_suspend,
6665 .runtime_resume = rtl8169_runtime_resume,
6666 .runtime_idle = rtl8169_runtime_idle,
6667 };
6668
6669 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6670
6671 #else /* !CONFIG_PM */
6672
6673 #define RTL8169_PM_OPS NULL
6674
6675 #endif /* !CONFIG_PM */
6676
6677 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6678 {
6679 void __iomem *ioaddr = tp->mmio_addr;
6680
6681 /* WoL fails with 8168b when the receiver is disabled. */
6682 switch (tp->mac_version) {
6683 case RTL_GIGA_MAC_VER_11:
6684 case RTL_GIGA_MAC_VER_12:
6685 case RTL_GIGA_MAC_VER_17:
6686 pci_clear_master(tp->pci_dev);
6687
6688 RTL_W8(ChipCmd, CmdRxEnb);
6689 /* PCI commit */
6690 RTL_R8(ChipCmd);
6691 break;
6692 default:
6693 break;
6694 }
6695 }
6696
6697 static void rtl_shutdown(struct pci_dev *pdev)
6698 {
6699 struct net_device *dev = pci_get_drvdata(pdev);
6700 struct rtl8169_private *tp = netdev_priv(dev);
6701 struct device *d = &pdev->dev;
6702
6703 pm_runtime_get_sync(d);
6704
6705 rtl8169_net_suspend(dev);
6706
6707 /* Restore original MAC address */
6708 rtl_rar_set(tp, dev->perm_addr);
6709
6710 rtl8169_hw_reset(tp);
6711
6712 if (system_state == SYSTEM_POWER_OFF) {
6713 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6714 rtl_wol_suspend_quirk(tp);
6715 rtl_wol_shutdown_quirk(tp);
6716 }
6717
6718 pci_wake_from_d3(pdev, true);
6719 pci_set_power_state(pdev, PCI_D3hot);
6720 }
6721
6722 pm_runtime_put_noidle(d);
6723 }
6724
6725 static void rtl_remove_one(struct pci_dev *pdev)
6726 {
6727 struct net_device *dev = pci_get_drvdata(pdev);
6728 struct rtl8169_private *tp = netdev_priv(dev);
6729
6730 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6731 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6732 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6733 rtl8168_driver_stop(tp);
6734 }
6735
6736 cancel_work_sync(&tp->wk.work);
6737
6738 netif_napi_del(&tp->napi);
6739
6740 unregister_netdev(dev);
6741
6742 rtl_release_firmware(tp);
6743
6744 if (pci_dev_run_wake(pdev))
6745 pm_runtime_get_noresume(&pdev->dev);
6746
6747 /* restore original MAC address */
6748 rtl_rar_set(tp, dev->perm_addr);
6749
6750 rtl_disable_msi(pdev, tp);
6751 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6752 pci_set_drvdata(pdev, NULL);
6753 }
6754
6755 static const struct net_device_ops rtl_netdev_ops = {
6756 .ndo_open = rtl_open,
6757 .ndo_stop = rtl8169_close,
6758 .ndo_get_stats64 = rtl8169_get_stats64,
6759 .ndo_start_xmit = rtl8169_start_xmit,
6760 .ndo_tx_timeout = rtl8169_tx_timeout,
6761 .ndo_validate_addr = eth_validate_addr,
6762 .ndo_change_mtu = rtl8169_change_mtu,
6763 .ndo_fix_features = rtl8169_fix_features,
6764 .ndo_set_features = rtl8169_set_features,
6765 .ndo_set_mac_address = rtl_set_mac_address,
6766 .ndo_do_ioctl = rtl8169_ioctl,
6767 .ndo_set_rx_mode = rtl_set_rx_mode,
6768 #ifdef CONFIG_NET_POLL_CONTROLLER
6769 .ndo_poll_controller = rtl8169_netpoll,
6770 #endif
6771
6772 };
6773
6774 static const struct rtl_cfg_info {
6775 void (*hw_start)(struct net_device *);
6776 unsigned int region;
6777 unsigned int align;
6778 u16 event_slow;
6779 unsigned features;
6780 u8 default_ver;
6781 } rtl_cfg_infos [] = {
6782 [RTL_CFG_0] = {
6783 .hw_start = rtl_hw_start_8169,
6784 .region = 1,
6785 .align = 0,
6786 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6787 .features = RTL_FEATURE_GMII,
6788 .default_ver = RTL_GIGA_MAC_VER_01,
6789 },
6790 [RTL_CFG_1] = {
6791 .hw_start = rtl_hw_start_8168,
6792 .region = 2,
6793 .align = 8,
6794 .event_slow = SYSErr | LinkChg | RxOverflow,
6795 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6796 .default_ver = RTL_GIGA_MAC_VER_11,
6797 },
6798 [RTL_CFG_2] = {
6799 .hw_start = rtl_hw_start_8101,
6800 .region = 2,
6801 .align = 8,
6802 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6803 PCSTimeout,
6804 .features = RTL_FEATURE_MSI,
6805 .default_ver = RTL_GIGA_MAC_VER_13,
6806 }
6807 };
6808
6809 /* Cfg9346_Unlock assumed. */
6810 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6811 const struct rtl_cfg_info *cfg)
6812 {
6813 void __iomem *ioaddr = tp->mmio_addr;
6814 unsigned msi = 0;
6815 u8 cfg2;
6816
6817 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6818 if (cfg->features & RTL_FEATURE_MSI) {
6819 if (pci_enable_msi(tp->pci_dev)) {
6820 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6821 } else {
6822 cfg2 |= MSIEnable;
6823 msi = RTL_FEATURE_MSI;
6824 }
6825 }
6826 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6827 RTL_W8(Config2, cfg2);
6828 return msi;
6829 }
6830
6831 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6832 {
6833 void __iomem *ioaddr = tp->mmio_addr;
6834
6835 return RTL_R8(MCU) & LINK_LIST_RDY;
6836 }
6837
6838 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6839 {
6840 void __iomem *ioaddr = tp->mmio_addr;
6841
6842 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6843 }
6844
6845 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6846 {
6847 void __iomem *ioaddr = tp->mmio_addr;
6848 u32 data;
6849
6850 tp->ocp_base = OCP_STD_PHY_BASE;
6851
6852 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6853
6854 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6855 return;
6856
6857 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6858 return;
6859
6860 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6861 msleep(1);
6862 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6863
6864 data = r8168_mac_ocp_read(tp, 0xe8de);
6865 data &= ~(1 << 14);
6866 r8168_mac_ocp_write(tp, 0xe8de, data);
6867
6868 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6869 return;
6870
6871 data = r8168_mac_ocp_read(tp, 0xe8de);
6872 data |= (1 << 15);
6873 r8168_mac_ocp_write(tp, 0xe8de, data);
6874
6875 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6876 return;
6877 }
6878
6879 static void rtl_hw_initialize(struct rtl8169_private *tp)
6880 {
6881 switch (tp->mac_version) {
6882 case RTL_GIGA_MAC_VER_40:
6883 case RTL_GIGA_MAC_VER_41:
6884 case RTL_GIGA_MAC_VER_42:
6885 case RTL_GIGA_MAC_VER_43:
6886 rtl_hw_init_8168g(tp);
6887 break;
6888
6889 default:
6890 break;
6891 }
6892 }
6893
6894 static int
6895 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6896 {
6897 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6898 const unsigned int region = cfg->region;
6899 struct rtl8169_private *tp;
6900 struct mii_if_info *mii;
6901 struct net_device *dev;
6902 void __iomem *ioaddr;
6903 int chipset, i;
6904 int rc;
6905
6906 if (netif_msg_drv(&debug)) {
6907 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6908 MODULENAME, RTL8169_VERSION);
6909 }
6910
6911 dev = alloc_etherdev(sizeof (*tp));
6912 if (!dev) {
6913 rc = -ENOMEM;
6914 goto out;
6915 }
6916
6917 SET_NETDEV_DEV(dev, &pdev->dev);
6918 dev->netdev_ops = &rtl_netdev_ops;
6919 tp = netdev_priv(dev);
6920 tp->dev = dev;
6921 tp->pci_dev = pdev;
6922 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6923
6924 mii = &tp->mii;
6925 mii->dev = dev;
6926 mii->mdio_read = rtl_mdio_read;
6927 mii->mdio_write = rtl_mdio_write;
6928 mii->phy_id_mask = 0x1f;
6929 mii->reg_num_mask = 0x1f;
6930 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6931
6932 /* disable ASPM completely as that cause random device stop working
6933 * problems as well as full system hangs for some PCIe devices users */
6934 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6935 PCIE_LINK_STATE_CLKPM);
6936
6937 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6938 rc = pci_enable_device(pdev);
6939 if (rc < 0) {
6940 netif_err(tp, probe, dev, "enable failure\n");
6941 goto err_out_free_dev_1;
6942 }
6943
6944 if (pci_set_mwi(pdev) < 0)
6945 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6946
6947 /* make sure PCI base addr 1 is MMIO */
6948 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6949 netif_err(tp, probe, dev,
6950 "region #%d not an MMIO resource, aborting\n",
6951 region);
6952 rc = -ENODEV;
6953 goto err_out_mwi_2;
6954 }
6955
6956 /* check for weird/broken PCI region reporting */
6957 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6958 netif_err(tp, probe, dev,
6959 "Invalid PCI region size(s), aborting\n");
6960 rc = -ENODEV;
6961 goto err_out_mwi_2;
6962 }
6963
6964 rc = pci_request_regions(pdev, MODULENAME);
6965 if (rc < 0) {
6966 netif_err(tp, probe, dev, "could not request regions\n");
6967 goto err_out_mwi_2;
6968 }
6969
6970 tp->cp_cmd = RxChkSum;
6971
6972 if ((sizeof(dma_addr_t) > 4) &&
6973 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6974 tp->cp_cmd |= PCIDAC;
6975 dev->features |= NETIF_F_HIGHDMA;
6976 } else {
6977 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6978 if (rc < 0) {
6979 netif_err(tp, probe, dev, "DMA configuration failed\n");
6980 goto err_out_free_res_3;
6981 }
6982 }
6983
6984 /* ioremap MMIO region */
6985 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6986 if (!ioaddr) {
6987 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6988 rc = -EIO;
6989 goto err_out_free_res_3;
6990 }
6991 tp->mmio_addr = ioaddr;
6992
6993 if (!pci_is_pcie(pdev))
6994 netif_info(tp, probe, dev, "not PCI Express\n");
6995
6996 /* Identify chip attached to board */
6997 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6998
6999 rtl_init_rxcfg(tp);
7000
7001 rtl_irq_disable(tp);
7002
7003 rtl_hw_initialize(tp);
7004
7005 rtl_hw_reset(tp);
7006
7007 rtl_ack_events(tp, 0xffff);
7008
7009 pci_set_master(pdev);
7010
7011 /*
7012 * Pretend we are using VLANs; This bypasses a nasty bug where
7013 * Interrupts stop flowing on high load on 8110SCd controllers.
7014 */
7015 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7016 tp->cp_cmd |= RxVlan;
7017
7018 rtl_init_mdio_ops(tp);
7019 rtl_init_pll_power_ops(tp);
7020 rtl_init_jumbo_ops(tp);
7021 rtl_init_csi_ops(tp);
7022
7023 rtl8169_print_mac_version(tp);
7024
7025 chipset = tp->mac_version;
7026 tp->txd_version = rtl_chip_infos[chipset].txd_version;
7027
7028 RTL_W8(Cfg9346, Cfg9346_Unlock);
7029 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
7030 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
7031 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7032 tp->features |= RTL_FEATURE_WOL;
7033 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7034 tp->features |= RTL_FEATURE_WOL;
7035 tp->features |= rtl_try_msi(tp, cfg);
7036 RTL_W8(Cfg9346, Cfg9346_Lock);
7037
7038 if (rtl_tbi_enabled(tp)) {
7039 tp->set_speed = rtl8169_set_speed_tbi;
7040 tp->get_settings = rtl8169_gset_tbi;
7041 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7042 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7043 tp->link_ok = rtl8169_tbi_link_ok;
7044 tp->do_ioctl = rtl_tbi_ioctl;
7045 } else {
7046 tp->set_speed = rtl8169_set_speed_xmii;
7047 tp->get_settings = rtl8169_gset_xmii;
7048 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7049 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7050 tp->link_ok = rtl8169_xmii_link_ok;
7051 tp->do_ioctl = rtl_xmii_ioctl;
7052 }
7053
7054 mutex_init(&tp->wk.mutex);
7055
7056 /* Get MAC address */
7057 for (i = 0; i < ETH_ALEN; i++)
7058 dev->dev_addr[i] = RTL_R8(MAC0 + i);
7059
7060 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
7061 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7062
7063 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7064
7065 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7066 * properly for all devices */
7067 dev->features |= NETIF_F_RXCSUM |
7068 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7069
7070 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7071 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7072 NETIF_F_HW_VLAN_CTAG_RX;
7073 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7074 NETIF_F_HIGHDMA;
7075
7076 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7077 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
7078 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7079
7080 dev->hw_features |= NETIF_F_RXALL;
7081 dev->hw_features |= NETIF_F_RXFCS;
7082
7083 tp->hw_start = cfg->hw_start;
7084 tp->event_slow = cfg->event_slow;
7085
7086 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7087 ~(RxBOVF | RxFOVF) : ~0;
7088
7089 init_timer(&tp->timer);
7090 tp->timer.data = (unsigned long) dev;
7091 tp->timer.function = rtl8169_phy_timer;
7092
7093 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7094
7095 rc = register_netdev(dev);
7096 if (rc < 0)
7097 goto err_out_msi_4;
7098
7099 pci_set_drvdata(pdev, dev);
7100
7101 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7102 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7103 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
7104 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7105 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7106 "tx checksumming: %s]\n",
7107 rtl_chip_infos[chipset].jumbo_max,
7108 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7109 }
7110
7111 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7112 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7113 tp->mac_version == RTL_GIGA_MAC_VER_31) {
7114 rtl8168_driver_start(tp);
7115 }
7116
7117 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7118
7119 if (pci_dev_run_wake(pdev))
7120 pm_runtime_put_noidle(&pdev->dev);
7121
7122 netif_carrier_off(dev);
7123
7124 out:
7125 return rc;
7126
7127 err_out_msi_4:
7128 netif_napi_del(&tp->napi);
7129 rtl_disable_msi(pdev, tp);
7130 iounmap(ioaddr);
7131 err_out_free_res_3:
7132 pci_release_regions(pdev);
7133 err_out_mwi_2:
7134 pci_clear_mwi(pdev);
7135 pci_disable_device(pdev);
7136 err_out_free_dev_1:
7137 free_netdev(dev);
7138 goto out;
7139 }
7140
7141 static struct pci_driver rtl8169_pci_driver = {
7142 .name = MODULENAME,
7143 .id_table = rtl8169_pci_tbl,
7144 .probe = rtl_init_one,
7145 .remove = rtl_remove_one,
7146 .shutdown = rtl_shutdown,
7147 .driver.pm = RTL8169_PM_OPS,
7148 };
7149
7150 module_pci_driver(rtl8169_pci_driver);
kernel source for telekom puls (alcatel/mediatek)