2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
32 #include <asm/system.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
50 #define assert(expr) \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
53 #expr,__FILE__,__func__,__LINE__); \
55 #define dprintk(fmt, args...) \
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
58 #define assert(expr) do {} while (0)
59 #define dprintk(fmt, args...) do {} while (0)
60 #endif /* RTL8169_DEBUG */
62 #define R8169_MSG_DEFAULT \
63 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
65 #define TX_BUFFS_AVAIL(tp) \
66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
70 static const int multicast_filter_limit
= 32;
72 #define MAX_READ_REQUEST_SHIFT 12
73 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
74 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77 #define R8169_REGS_SIZE 256
78 #define R8169_NAPI_WEIGHT 64
79 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
82 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
85 #define RTL8169_TX_TIMEOUT (6*HZ)
86 #define RTL8169_PHY_TIMEOUT (10*HZ)
88 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
90 #define RTL_EEPROM_SIG_ADDR 0x0000
92 /* write/read MMIO register */
93 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96 #define RTL_R8(reg) readb (ioaddr + (reg))
97 #define RTL_R16(reg) readw (ioaddr + (reg))
98 #define RTL_R32(reg) readl (ioaddr + (reg))
101 RTL_GIGA_MAC_VER_01
= 0,
137 RTL_GIGA_MAC_NONE
= 0xff,
140 enum rtl_tx_desc_version
{
145 #define JUMBO_1K ETH_DATA_LEN
146 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
151 #define _R(NAME,TD,FW,SZ,B) { \
159 static const struct {
161 enum rtl_tx_desc_version txd_version
;
165 } rtl_chip_infos
[] = {
167 [RTL_GIGA_MAC_VER_01
] =
168 _R("RTL8169", RTL_TD_0
, NULL
, JUMBO_7K
, true),
169 [RTL_GIGA_MAC_VER_02
] =
170 _R("RTL8169s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
171 [RTL_GIGA_MAC_VER_03
] =
172 _R("RTL8110s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
173 [RTL_GIGA_MAC_VER_04
] =
174 _R("RTL8169sb/8110sb", RTL_TD_0
, NULL
, JUMBO_7K
, true),
175 [RTL_GIGA_MAC_VER_05
] =
176 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
177 [RTL_GIGA_MAC_VER_06
] =
178 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
180 [RTL_GIGA_MAC_VER_07
] =
181 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
182 [RTL_GIGA_MAC_VER_08
] =
183 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
184 [RTL_GIGA_MAC_VER_09
] =
185 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
186 [RTL_GIGA_MAC_VER_10
] =
187 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
188 [RTL_GIGA_MAC_VER_11
] =
189 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
190 [RTL_GIGA_MAC_VER_12
] =
191 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
192 [RTL_GIGA_MAC_VER_13
] =
193 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
194 [RTL_GIGA_MAC_VER_14
] =
195 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
196 [RTL_GIGA_MAC_VER_15
] =
197 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
198 [RTL_GIGA_MAC_VER_16
] =
199 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
200 [RTL_GIGA_MAC_VER_17
] =
201 _R("RTL8168b/8111b", RTL_TD_1
, NULL
, JUMBO_4K
, false),
202 [RTL_GIGA_MAC_VER_18
] =
203 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
204 [RTL_GIGA_MAC_VER_19
] =
205 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
206 [RTL_GIGA_MAC_VER_20
] =
207 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
208 [RTL_GIGA_MAC_VER_21
] =
209 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
210 [RTL_GIGA_MAC_VER_22
] =
211 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
212 [RTL_GIGA_MAC_VER_23
] =
213 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
214 [RTL_GIGA_MAC_VER_24
] =
215 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
216 [RTL_GIGA_MAC_VER_25
] =
217 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_1
,
219 [RTL_GIGA_MAC_VER_26
] =
220 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_2
,
222 [RTL_GIGA_MAC_VER_27
] =
223 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
224 [RTL_GIGA_MAC_VER_28
] =
225 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
226 [RTL_GIGA_MAC_VER_29
] =
227 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
229 [RTL_GIGA_MAC_VER_30
] =
230 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
232 [RTL_GIGA_MAC_VER_31
] =
233 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
234 [RTL_GIGA_MAC_VER_32
] =
235 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_1
,
237 [RTL_GIGA_MAC_VER_33
] =
238 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_2
,
240 [RTL_GIGA_MAC_VER_34
] =
241 _R("RTL8168evl/8111evl",RTL_TD_1
, FIRMWARE_8168E_3
,
243 [RTL_GIGA_MAC_VER_35
] =
244 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_1
,
246 [RTL_GIGA_MAC_VER_36
] =
247 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_2
,
258 static void rtl_hw_start_8169(struct net_device
*);
259 static void rtl_hw_start_8168(struct net_device
*);
260 static void rtl_hw_start_8101(struct net_device
*);
262 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl
) = {
263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
268 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
269 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4302), 0, 0, RTL_CFG_0
},
270 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
271 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
272 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
273 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
275 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
279 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
281 static int rx_buf_sz
= 16383;
288 MAC0
= 0, /* Ethernet hardware address. */
290 MAR0
= 8, /* Multicast filter. */
291 CounterAddrLow
= 0x10,
292 CounterAddrHigh
= 0x14,
293 TxDescStartAddrLow
= 0x20,
294 TxDescStartAddrHigh
= 0x24,
295 TxHDescStartAddrLow
= 0x28,
296 TxHDescStartAddrHigh
= 0x2c,
305 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
306 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
309 #define RX128_INT_EN (1 << 15) /* 8111c and later */
310 #define RX_MULTI_EN (1 << 14) /* 8111c only */
311 #define RXCFG_FIFO_SHIFT 13
312 /* No threshold before first PCI xfer */
313 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
314 #define RXCFG_DMA_SHIFT 8
315 /* Unlimited maximum PCI burst. */
316 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
332 RxDescAddrLow
= 0xe4,
333 RxDescAddrHigh
= 0xe8,
334 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
336 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
338 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
340 #define TxPacketMax (8064 >> 7)
341 #define EarlySize 0x27
344 FuncEventMask
= 0xf4,
345 FuncPresetState
= 0xf8,
346 FuncForceEvent
= 0xfc,
349 enum rtl8110_registers
{
355 enum rtl8168_8101_registers
{
358 #define CSIAR_FLAG 0x80000000
359 #define CSIAR_WRITE_CMD 0x80000000
360 #define CSIAR_BYTE_ENABLE 0x0f
361 #define CSIAR_BYTE_ENABLE_SHIFT 12
362 #define CSIAR_ADDR_MASK 0x0fff
365 #define EPHYAR_FLAG 0x80000000
366 #define EPHYAR_WRITE_CMD 0x80000000
367 #define EPHYAR_REG_MASK 0x1f
368 #define EPHYAR_REG_SHIFT 16
369 #define EPHYAR_DATA_MASK 0xffff
371 #define PFM_EN (1 << 6)
373 #define FIX_NAK_1 (1 << 4)
374 #define FIX_NAK_2 (1 << 3)
377 #define NOW_IS_OOB (1 << 7)
378 #define EN_NDP (1 << 3)
379 #define EN_OOB_RESET (1 << 2)
381 #define EFUSEAR_FLAG 0x80000000
382 #define EFUSEAR_WRITE_CMD 0x80000000
383 #define EFUSEAR_READ_CMD 0x00000000
384 #define EFUSEAR_REG_MASK 0x03ff
385 #define EFUSEAR_REG_SHIFT 8
386 #define EFUSEAR_DATA_MASK 0xff
389 enum rtl8168_registers
{
394 #define ERIAR_FLAG 0x80000000
395 #define ERIAR_WRITE_CMD 0x80000000
396 #define ERIAR_READ_CMD 0x00000000
397 #define ERIAR_ADDR_BYTE_ALIGN 4
398 #define ERIAR_TYPE_SHIFT 16
399 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
400 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
401 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
402 #define ERIAR_MASK_SHIFT 12
403 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
404 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
405 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
406 EPHY_RXER_NUM
= 0x7c,
407 OCPDR
= 0xb0, /* OCP GPHY access */
408 #define OCPDR_WRITE_CMD 0x80000000
409 #define OCPDR_READ_CMD 0x00000000
410 #define OCPDR_REG_MASK 0x7f
411 #define OCPDR_GPHY_REG_SHIFT 16
412 #define OCPDR_DATA_MASK 0xffff
414 #define OCPAR_FLAG 0x80000000
415 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
416 #define OCPAR_GPHY_READ_CMD 0x0000f060
417 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
418 MISC
= 0xf0, /* 8168e only. */
419 #define TXPLA_RST (1 << 29)
420 #define PWM_EN (1 << 22)
423 enum rtl_register_content
{
424 /* InterruptStatusBits */
428 TxDescUnavail
= 0x0080,
452 /* TXPoll register p.5 */
453 HPQ
= 0x80, /* Poll cmd on the high prio queue */
454 NPQ
= 0x40, /* Poll cmd on the low prio queue */
455 FSWInt
= 0x01, /* Forced software interrupt */
459 Cfg9346_Unlock
= 0xc0,
464 AcceptBroadcast
= 0x08,
465 AcceptMulticast
= 0x04,
467 AcceptAllPhys
= 0x01,
468 #define RX_CONFIG_ACCEPT_MASK 0x3f
471 TxInterFrameGapShift
= 24,
472 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
474 /* Config1 register p.24 */
477 Speed_down
= (1 << 4),
481 PMEnable
= (1 << 0), /* Power Management Enable */
483 /* Config2 register p. 25 */
484 MSIEnable
= (1 << 5), /* 8169 only. Reserved in the 8168. */
485 PCI_Clock_66MHz
= 0x01,
486 PCI_Clock_33MHz
= 0x00,
488 /* Config3 register p.25 */
489 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
490 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
491 Jumbo_En0
= (1 << 2), /* 8168 only. Reserved in the 8168b */
492 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
494 /* Config4 register */
495 Jumbo_En1
= (1 << 1), /* 8168 only. Reserved in the 8168b */
497 /* Config5 register p.27 */
498 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
499 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
500 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
502 LanWake
= (1 << 1), /* LanWake enable/disable */
503 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
506 TBIReset
= 0x80000000,
507 TBILoopback
= 0x40000000,
508 TBINwEnable
= 0x20000000,
509 TBINwRestart
= 0x10000000,
510 TBILinkOk
= 0x02000000,
511 TBINwComplete
= 0x01000000,
514 EnableBist
= (1 << 15), // 8168 8101
515 Mac_dbgo_oe
= (1 << 14), // 8168 8101
516 Normal_mode
= (1 << 13), // unused
517 Force_half_dup
= (1 << 12), // 8168 8101
518 Force_rxflow_en
= (1 << 11), // 8168 8101
519 Force_txflow_en
= (1 << 10), // 8168 8101
520 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
521 ASF
= (1 << 8), // 8168 8101
522 PktCntrDisable
= (1 << 7), // 8168 8101
523 Mac_dbgo_sel
= 0x001c, // 8168
528 INTT_0
= 0x0000, // 8168
529 INTT_1
= 0x0001, // 8168
530 INTT_2
= 0x0002, // 8168
531 INTT_3
= 0x0003, // 8168
533 /* rtl8169_PHYstatus */
544 TBILinkOK
= 0x02000000,
546 /* DumpCounterCommand */
551 /* First doubleword. */
552 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
553 RingEnd
= (1 << 30), /* End of descriptor ring */
554 FirstFrag
= (1 << 29), /* First segment of a packet */
555 LastFrag
= (1 << 28), /* Final segment of a packet */
559 enum rtl_tx_desc_bit
{
560 /* First doubleword. */
561 TD_LSO
= (1 << 27), /* Large Send Offload */
562 #define TD_MSS_MAX 0x07ffu /* MSS value */
564 /* Second doubleword. */
565 TxVlanTag
= (1 << 17), /* Add VLAN tag */
568 /* 8169, 8168b and 810x except 8102e. */
569 enum rtl_tx_desc_bit_0
{
570 /* First doubleword. */
571 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
572 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
573 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
574 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
577 /* 8102e, 8168c and beyond. */
578 enum rtl_tx_desc_bit_1
{
579 /* Second doubleword. */
580 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
581 TD1_IP_CS
= (1 << 29), /* Calculate IP checksum */
582 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
583 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
586 static const struct rtl_tx_desc_info
{
593 } tx_desc_info
[] = {
596 .udp
= TD0_IP_CS
| TD0_UDP_CS
,
597 .tcp
= TD0_IP_CS
| TD0_TCP_CS
599 .mss_shift
= TD0_MSS_SHIFT
,
604 .udp
= TD1_IP_CS
| TD1_UDP_CS
,
605 .tcp
= TD1_IP_CS
| TD1_TCP_CS
607 .mss_shift
= TD1_MSS_SHIFT
,
612 enum rtl_rx_desc_bit
{
614 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
615 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
617 #define RxProtoUDP (PID1)
618 #define RxProtoTCP (PID0)
619 #define RxProtoIP (PID1 | PID0)
620 #define RxProtoMask RxProtoIP
622 IPFail
= (1 << 16), /* IP checksum failed */
623 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
624 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
625 RxVlanTag
= (1 << 16), /* VLAN tag available */
628 #define RsvdMask 0x3fffc000
645 u8 __pad
[sizeof(void *) - sizeof(u32
)];
649 RTL_FEATURE_WOL
= (1 << 0),
650 RTL_FEATURE_MSI
= (1 << 1),
651 RTL_FEATURE_GMII
= (1 << 2),
654 struct rtl8169_counters
{
661 __le32 tx_one_collision
;
662 __le32 tx_multi_collision
;
670 struct rtl8169_private
{
671 void __iomem
*mmio_addr
; /* memory map physical address */
672 struct pci_dev
*pci_dev
;
673 struct net_device
*dev
;
674 struct napi_struct napi
;
679 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
680 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
683 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
684 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
685 dma_addr_t TxPhyAddr
;
686 dma_addr_t RxPhyAddr
;
687 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
688 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
689 struct timer_list timer
;
696 void (*write
)(void __iomem
*, int, int);
697 int (*read
)(void __iomem
*, int);
700 struct pll_power_ops
{
701 void (*down
)(struct rtl8169_private
*);
702 void (*up
)(struct rtl8169_private
*);
706 void (*enable
)(struct rtl8169_private
*);
707 void (*disable
)(struct rtl8169_private
*);
710 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
711 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
712 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
713 void (*hw_start
)(struct net_device
*);
714 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
715 unsigned int (*link_ok
)(void __iomem
*);
716 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
717 struct delayed_work task
;
720 struct mii_if_info mii
;
721 struct rtl8169_counters counters
;
726 const struct firmware
*fw
;
728 #define RTL_VER_SIZE 32
730 char version
[RTL_VER_SIZE
];
732 struct rtl_fw_phy_action
{
737 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
740 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
741 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
742 module_param(use_dac
, int, 0);
743 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
744 module_param_named(debug
, debug
.msg_enable
, int, 0);
745 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
746 MODULE_LICENSE("GPL");
747 MODULE_VERSION(RTL8169_VERSION
);
748 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
749 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
750 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
751 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
752 MODULE_FIRMWARE(FIRMWARE_8168E_3
);
753 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
754 MODULE_FIRMWARE(FIRMWARE_8168F_1
);
755 MODULE_FIRMWARE(FIRMWARE_8168F_2
);
757 static int rtl8169_open(struct net_device
*dev
);
758 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
759 struct net_device
*dev
);
760 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
761 static int rtl8169_init_ring(struct net_device
*dev
);
762 static void rtl_hw_start(struct net_device
*dev
);
763 static int rtl8169_close(struct net_device
*dev
);
764 static void rtl_set_rx_mode(struct net_device
*dev
);
765 static void rtl8169_tx_timeout(struct net_device
*dev
);
766 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
767 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
768 void __iomem
*, u32 budget
);
769 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
770 static void rtl8169_down(struct net_device
*dev
);
771 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
772 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
774 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
776 int cap
= pci_pcie_cap(pdev
);
781 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
782 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
783 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
787 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
789 void __iomem
*ioaddr
= tp
->mmio_addr
;
792 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
793 for (i
= 0; i
< 20; i
++) {
795 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
798 return RTL_R32(OCPDR
);
801 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
803 void __iomem
*ioaddr
= tp
->mmio_addr
;
806 RTL_W32(OCPDR
, data
);
807 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
808 for (i
= 0; i
< 20; i
++) {
810 if ((RTL_R32(OCPAR
) & OCPAR_FLAG
) == 0)
815 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
817 void __iomem
*ioaddr
= tp
->mmio_addr
;
821 RTL_W32(ERIAR
, 0x800010e8);
823 for (i
= 0; i
< 5; i
++) {
825 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
829 ocp_write(tp
, 0x1, 0x30, 0x00000001);
832 #define OOB_CMD_RESET 0x00
833 #define OOB_CMD_DRIVER_START 0x05
834 #define OOB_CMD_DRIVER_STOP 0x06
836 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
838 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
841 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
846 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
848 reg
= rtl8168_get_ocp_reg(tp
);
850 for (i
= 0; i
< 10; i
++) {
852 if (ocp_read(tp
, 0x0f, reg
) & 0x00000800)
857 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
862 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
864 reg
= rtl8168_get_ocp_reg(tp
);
866 for (i
= 0; i
< 10; i
++) {
868 if ((ocp_read(tp
, 0x0f, reg
) & 0x00000800) == 0)
873 static int r8168dp_check_dash(struct rtl8169_private
*tp
)
875 u16 reg
= rtl8168_get_ocp_reg(tp
);
877 return (ocp_read(tp
, 0x0f, reg
) & 0x00008000) ? 1 : 0;
880 static void r8169_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
884 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
886 for (i
= 20; i
> 0; i
--) {
888 * Check if the RTL8169 has completed writing to the specified
891 if (!(RTL_R32(PHYAR
) & 0x80000000))
896 * According to hardware specs a 20us delay is required after write
897 * complete indication, but before sending next command.
902 static int r8169_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
906 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
908 for (i
= 20; i
> 0; i
--) {
910 * Check if the RTL8169 has completed retrieving data from
911 * the specified MII register.
913 if (RTL_R32(PHYAR
) & 0x80000000) {
914 value
= RTL_R32(PHYAR
) & 0xffff;
920 * According to hardware specs a 20us delay is required after read
921 * complete indication, but before sending next command.
928 static void r8168dp_1_mdio_access(void __iomem
*ioaddr
, int reg_addr
, u32 data
)
932 RTL_W32(OCPDR
, data
|
933 ((reg_addr
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
934 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
935 RTL_W32(EPHY_RXER_NUM
, 0);
937 for (i
= 0; i
< 100; i
++) {
939 if (!(RTL_R32(OCPAR
) & OCPAR_FLAG
))
944 static void r8168dp_1_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
946 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_WRITE_CMD
|
947 (value
& OCPDR_DATA_MASK
));
950 static int r8168dp_1_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
954 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_READ_CMD
);
957 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
958 RTL_W32(EPHY_RXER_NUM
, 0);
960 for (i
= 0; i
< 100; i
++) {
962 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
966 return RTL_R32(OCPDR
) & OCPDR_DATA_MASK
;
969 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
971 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
973 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
976 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
978 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
981 static void r8168dp_2_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
983 r8168dp_2_mdio_start(ioaddr
);
985 r8169_mdio_write(ioaddr
, reg_addr
, value
);
987 r8168dp_2_mdio_stop(ioaddr
);
990 static int r8168dp_2_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
994 r8168dp_2_mdio_start(ioaddr
);
996 value
= r8169_mdio_read(ioaddr
, reg_addr
);
998 r8168dp_2_mdio_stop(ioaddr
);
1003 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
1005 tp
->mdio_ops
.write(tp
->mmio_addr
, location
, val
);
1008 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
1010 return tp
->mdio_ops
.read(tp
->mmio_addr
, location
);
1013 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1015 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
1018 static void rtl_w1w0_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
1022 val
= rtl_readphy(tp
, reg_addr
);
1023 rtl_writephy(tp
, reg_addr
, (val
| p
) & ~m
);
1026 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
1029 struct rtl8169_private
*tp
= netdev_priv(dev
);
1031 rtl_writephy(tp
, location
, val
);
1034 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
1036 struct rtl8169_private
*tp
= netdev_priv(dev
);
1038 return rtl_readphy(tp
, location
);
1041 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
1045 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
1046 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1048 for (i
= 0; i
< 100; i
++) {
1049 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
1055 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
1060 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1062 for (i
= 0; i
< 100; i
++) {
1063 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
1064 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
1073 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
1077 RTL_W32(CSIDR
, value
);
1078 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
1079 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1081 for (i
= 0; i
< 100; i
++) {
1082 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
1088 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
1093 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
1094 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1096 for (i
= 0; i
< 100; i
++) {
1097 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
1098 value
= RTL_R32(CSIDR
);
1108 void rtl_eri_write(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 val
, int type
)
1112 BUG_ON((addr
& 3) || (mask
== 0));
1113 RTL_W32(ERIDR
, val
);
1114 RTL_W32(ERIAR
, ERIAR_WRITE_CMD
| type
| mask
| addr
);
1116 for (i
= 0; i
< 100; i
++) {
1117 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
1123 static u32
rtl_eri_read(void __iomem
*ioaddr
, int addr
, int type
)
1128 RTL_W32(ERIAR
, ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
);
1130 for (i
= 0; i
< 100; i
++) {
1131 if (RTL_R32(ERIAR
) & ERIAR_FLAG
) {
1132 value
= RTL_R32(ERIDR
);
1142 rtl_w1w0_eri(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 p
, u32 m
, int type
)
1146 val
= rtl_eri_read(ioaddr
, addr
, type
);
1147 rtl_eri_write(ioaddr
, addr
, mask
, (val
& ~m
) | p
, type
);
1156 static void rtl_write_exgmac_batch(void __iomem
*ioaddr
,
1157 const struct exgmac_reg
*r
, int len
)
1160 rtl_eri_write(ioaddr
, r
->addr
, r
->mask
, r
->val
, ERIAR_EXGMAC
);
1165 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
1170 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1172 for (i
= 0; i
< 300; i
++) {
1173 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
1174 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
1183 static void rtl8169_irq_mask_and_ack(struct rtl8169_private
*tp
)
1185 void __iomem
*ioaddr
= tp
->mmio_addr
;
1187 RTL_W16(IntrMask
, 0x0000);
1188 RTL_W16(IntrStatus
, tp
->intr_event
);
1192 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1194 void __iomem
*ioaddr
= tp
->mmio_addr
;
1196 return RTL_R32(TBICSR
) & TBIReset
;
1199 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1201 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1204 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1206 return RTL_R32(TBICSR
) & TBILinkOk
;
1209 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1211 return RTL_R8(PHYstatus
) & LinkStatus
;
1214 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1216 void __iomem
*ioaddr
= tp
->mmio_addr
;
1218 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1221 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1225 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1226 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1229 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1231 void __iomem
*ioaddr
= tp
->mmio_addr
;
1232 struct net_device
*dev
= tp
->dev
;
1234 if (!netif_running(dev
))
1237 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
1238 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1239 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1240 0x00000011, ERIAR_EXGMAC
);
1241 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1242 0x00000005, ERIAR_EXGMAC
);
1243 } else if (RTL_R8(PHYstatus
) & _100bps
) {
1244 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1245 0x0000001f, ERIAR_EXGMAC
);
1246 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1247 0x00000005, ERIAR_EXGMAC
);
1249 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1250 0x0000001f, ERIAR_EXGMAC
);
1251 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1252 0x0000003f, ERIAR_EXGMAC
);
1254 /* Reset packet filter */
1255 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01,
1257 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00,
1259 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
1260 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
1261 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1262 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1263 0x00000011, ERIAR_EXGMAC
);
1264 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1265 0x00000005, ERIAR_EXGMAC
);
1267 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1268 0x0000001f, ERIAR_EXGMAC
);
1269 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1270 0x0000003f, ERIAR_EXGMAC
);
1275 static void __rtl8169_check_link_status(struct net_device
*dev
,
1276 struct rtl8169_private
*tp
,
1277 void __iomem
*ioaddr
, bool pm
)
1279 unsigned long flags
;
1281 spin_lock_irqsave(&tp
->lock
, flags
);
1282 if (tp
->link_ok(ioaddr
)) {
1283 rtl_link_chg_patch(tp
);
1284 /* This is to cancel a scheduled suspend if there's one. */
1286 pm_request_resume(&tp
->pci_dev
->dev
);
1287 netif_carrier_on(dev
);
1288 if (net_ratelimit())
1289 netif_info(tp
, ifup
, dev
, "link up\n");
1291 netif_carrier_off(dev
);
1292 netif_info(tp
, ifdown
, dev
, "link down\n");
1294 pm_schedule_suspend(&tp
->pci_dev
->dev
, 5000);
1296 spin_unlock_irqrestore(&tp
->lock
, flags
);
1299 static void rtl8169_check_link_status(struct net_device
*dev
,
1300 struct rtl8169_private
*tp
,
1301 void __iomem
*ioaddr
)
1303 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1306 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1308 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1310 void __iomem
*ioaddr
= tp
->mmio_addr
;
1314 options
= RTL_R8(Config1
);
1315 if (!(options
& PMEnable
))
1318 options
= RTL_R8(Config3
);
1319 if (options
& LinkUp
)
1320 wolopts
|= WAKE_PHY
;
1321 if (options
& MagicPacket
)
1322 wolopts
|= WAKE_MAGIC
;
1324 options
= RTL_R8(Config5
);
1326 wolopts
|= WAKE_UCAST
;
1328 wolopts
|= WAKE_BCAST
;
1330 wolopts
|= WAKE_MCAST
;
1335 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1337 struct rtl8169_private
*tp
= netdev_priv(dev
);
1339 spin_lock_irq(&tp
->lock
);
1341 wol
->supported
= WAKE_ANY
;
1342 wol
->wolopts
= __rtl8169_get_wol(tp
);
1344 spin_unlock_irq(&tp
->lock
);
1347 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1349 void __iomem
*ioaddr
= tp
->mmio_addr
;
1351 static const struct {
1356 { WAKE_ANY
, Config1
, PMEnable
},
1357 { WAKE_PHY
, Config3
, LinkUp
},
1358 { WAKE_MAGIC
, Config3
, MagicPacket
},
1359 { WAKE_UCAST
, Config5
, UWF
},
1360 { WAKE_BCAST
, Config5
, BWF
},
1361 { WAKE_MCAST
, Config5
, MWF
},
1362 { WAKE_ANY
, Config5
, LanWake
}
1365 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1367 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
1368 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1369 if (wolopts
& cfg
[i
].opt
)
1370 options
|= cfg
[i
].mask
;
1371 RTL_W8(cfg
[i
].reg
, options
);
1374 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1377 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1379 struct rtl8169_private
*tp
= netdev_priv(dev
);
1381 spin_lock_irq(&tp
->lock
);
1384 tp
->features
|= RTL_FEATURE_WOL
;
1386 tp
->features
&= ~RTL_FEATURE_WOL
;
1387 __rtl8169_set_wol(tp
, wol
->wolopts
);
1388 spin_unlock_irq(&tp
->lock
);
1390 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1395 static const char *rtl_lookup_firmware_name(struct rtl8169_private
*tp
)
1397 return rtl_chip_infos
[tp
->mac_version
].fw_name
;
1400 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1401 struct ethtool_drvinfo
*info
)
1403 struct rtl8169_private
*tp
= netdev_priv(dev
);
1404 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1406 strlcpy(info
->driver
, MODULENAME
, sizeof(info
->driver
));
1407 strlcpy(info
->version
, RTL8169_VERSION
, sizeof(info
->version
));
1408 strlcpy(info
->bus_info
, pci_name(tp
->pci_dev
), sizeof(info
->bus_info
));
1409 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1410 if (!IS_ERR_OR_NULL(rtl_fw
))
1411 strlcpy(info
->fw_version
, rtl_fw
->version
,
1412 sizeof(info
->fw_version
));
1415 static int rtl8169_get_regs_len(struct net_device
*dev
)
1417 return R8169_REGS_SIZE
;
1420 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1421 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1423 struct rtl8169_private
*tp
= netdev_priv(dev
);
1424 void __iomem
*ioaddr
= tp
->mmio_addr
;
1428 reg
= RTL_R32(TBICSR
);
1429 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1430 (duplex
== DUPLEX_FULL
)) {
1431 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1432 } else if (autoneg
== AUTONEG_ENABLE
)
1433 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1435 netif_warn(tp
, link
, dev
,
1436 "incorrect speed setting refused in TBI mode\n");
1443 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1444 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1446 struct rtl8169_private
*tp
= netdev_priv(dev
);
1447 int giga_ctrl
, bmcr
;
1450 rtl_writephy(tp
, 0x1f, 0x0000);
1452 if (autoneg
== AUTONEG_ENABLE
) {
1455 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1456 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1457 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1459 if (adv
& ADVERTISED_10baseT_Half
)
1460 auto_nego
|= ADVERTISE_10HALF
;
1461 if (adv
& ADVERTISED_10baseT_Full
)
1462 auto_nego
|= ADVERTISE_10FULL
;
1463 if (adv
& ADVERTISED_100baseT_Half
)
1464 auto_nego
|= ADVERTISE_100HALF
;
1465 if (adv
& ADVERTISED_100baseT_Full
)
1466 auto_nego
|= ADVERTISE_100FULL
;
1468 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1470 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1471 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1473 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1474 if (tp
->mii
.supports_gmii
) {
1475 if (adv
& ADVERTISED_1000baseT_Half
)
1476 giga_ctrl
|= ADVERTISE_1000HALF
;
1477 if (adv
& ADVERTISED_1000baseT_Full
)
1478 giga_ctrl
|= ADVERTISE_1000FULL
;
1479 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1480 ADVERTISED_1000baseT_Full
)) {
1481 netif_info(tp
, link
, dev
,
1482 "PHY does not support 1000Mbps\n");
1486 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1488 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1489 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1493 if (speed
== SPEED_10
)
1495 else if (speed
== SPEED_100
)
1496 bmcr
= BMCR_SPEED100
;
1500 if (duplex
== DUPLEX_FULL
)
1501 bmcr
|= BMCR_FULLDPLX
;
1504 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1506 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
1507 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
1508 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1509 rtl_writephy(tp
, 0x17, 0x2138);
1510 rtl_writephy(tp
, 0x0e, 0x0260);
1512 rtl_writephy(tp
, 0x17, 0x2108);
1513 rtl_writephy(tp
, 0x0e, 0x0000);
1522 static int rtl8169_set_speed(struct net_device
*dev
,
1523 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
1525 struct rtl8169_private
*tp
= netdev_priv(dev
);
1528 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
1532 if (netif_running(dev
) && (autoneg
== AUTONEG_ENABLE
) &&
1533 (advertising
& ADVERTISED_1000baseT_Full
)) {
1534 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1540 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1542 struct rtl8169_private
*tp
= netdev_priv(dev
);
1543 unsigned long flags
;
1546 del_timer_sync(&tp
->timer
);
1548 spin_lock_irqsave(&tp
->lock
, flags
);
1549 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, ethtool_cmd_speed(cmd
),
1550 cmd
->duplex
, cmd
->advertising
);
1551 spin_unlock_irqrestore(&tp
->lock
, flags
);
1556 static netdev_features_t
rtl8169_fix_features(struct net_device
*dev
,
1557 netdev_features_t features
)
1559 struct rtl8169_private
*tp
= netdev_priv(dev
);
1561 if (dev
->mtu
> TD_MSS_MAX
)
1562 features
&= ~NETIF_F_ALL_TSO
;
1564 if (dev
->mtu
> JUMBO_1K
&&
1565 !rtl_chip_infos
[tp
->mac_version
].jumbo_tx_csum
)
1566 features
&= ~NETIF_F_IP_CSUM
;
1571 static int rtl8169_set_features(struct net_device
*dev
,
1572 netdev_features_t features
)
1574 struct rtl8169_private
*tp
= netdev_priv(dev
);
1575 void __iomem
*ioaddr
= tp
->mmio_addr
;
1576 unsigned long flags
;
1578 spin_lock_irqsave(&tp
->lock
, flags
);
1580 if (features
& NETIF_F_RXCSUM
)
1581 tp
->cp_cmd
|= RxChkSum
;
1583 tp
->cp_cmd
&= ~RxChkSum
;
1585 if (dev
->features
& NETIF_F_HW_VLAN_RX
)
1586 tp
->cp_cmd
|= RxVlan
;
1588 tp
->cp_cmd
&= ~RxVlan
;
1590 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1593 spin_unlock_irqrestore(&tp
->lock
, flags
);
1598 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1599 struct sk_buff
*skb
)
1601 return (vlan_tx_tag_present(skb
)) ?
1602 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1605 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1607 u32 opts2
= le32_to_cpu(desc
->opts2
);
1609 if (opts2
& RxVlanTag
)
1610 __vlan_hwaccel_put_tag(skb
, swab16(opts2
& 0xffff));
1615 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1617 struct rtl8169_private
*tp
= netdev_priv(dev
);
1618 void __iomem
*ioaddr
= tp
->mmio_addr
;
1622 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1623 cmd
->port
= PORT_FIBRE
;
1624 cmd
->transceiver
= XCVR_INTERNAL
;
1626 status
= RTL_R32(TBICSR
);
1627 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1628 cmd
->autoneg
= !!(status
& TBINwEnable
);
1630 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
1631 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1636 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1638 struct rtl8169_private
*tp
= netdev_priv(dev
);
1640 return mii_ethtool_gset(&tp
->mii
, cmd
);
1643 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1645 struct rtl8169_private
*tp
= netdev_priv(dev
);
1646 unsigned long flags
;
1649 spin_lock_irqsave(&tp
->lock
, flags
);
1651 rc
= tp
->get_settings(dev
, cmd
);
1653 spin_unlock_irqrestore(&tp
->lock
, flags
);
1657 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1660 struct rtl8169_private
*tp
= netdev_priv(dev
);
1661 unsigned long flags
;
1663 if (regs
->len
> R8169_REGS_SIZE
)
1664 regs
->len
= R8169_REGS_SIZE
;
1666 spin_lock_irqsave(&tp
->lock
, flags
);
1667 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1668 spin_unlock_irqrestore(&tp
->lock
, flags
);
1671 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1673 struct rtl8169_private
*tp
= netdev_priv(dev
);
1675 return tp
->msg_enable
;
1678 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1680 struct rtl8169_private
*tp
= netdev_priv(dev
);
1682 tp
->msg_enable
= value
;
1685 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1692 "tx_single_collisions",
1693 "tx_multi_collisions",
1701 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1705 return ARRAY_SIZE(rtl8169_gstrings
);
1711 static void rtl8169_update_counters(struct net_device
*dev
)
1713 struct rtl8169_private
*tp
= netdev_priv(dev
);
1714 void __iomem
*ioaddr
= tp
->mmio_addr
;
1715 struct device
*d
= &tp
->pci_dev
->dev
;
1716 struct rtl8169_counters
*counters
;
1722 * Some chips are unable to dump tally counters when the receiver
1725 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1728 counters
= dma_alloc_coherent(d
, sizeof(*counters
), &paddr
, GFP_KERNEL
);
1732 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1733 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1734 RTL_W32(CounterAddrLow
, cmd
);
1735 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1738 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1739 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1745 RTL_W32(CounterAddrLow
, 0);
1746 RTL_W32(CounterAddrHigh
, 0);
1748 dma_free_coherent(d
, sizeof(*counters
), counters
, paddr
);
1751 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1752 struct ethtool_stats
*stats
, u64
*data
)
1754 struct rtl8169_private
*tp
= netdev_priv(dev
);
1758 rtl8169_update_counters(dev
);
1760 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1761 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1762 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1763 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1764 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1765 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1766 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1767 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1768 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1769 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1770 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1771 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1772 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1775 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1779 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1784 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1785 .get_drvinfo
= rtl8169_get_drvinfo
,
1786 .get_regs_len
= rtl8169_get_regs_len
,
1787 .get_link
= ethtool_op_get_link
,
1788 .get_settings
= rtl8169_get_settings
,
1789 .set_settings
= rtl8169_set_settings
,
1790 .get_msglevel
= rtl8169_get_msglevel
,
1791 .set_msglevel
= rtl8169_set_msglevel
,
1792 .get_regs
= rtl8169_get_regs
,
1793 .get_wol
= rtl8169_get_wol
,
1794 .set_wol
= rtl8169_set_wol
,
1795 .get_strings
= rtl8169_get_strings
,
1796 .get_sset_count
= rtl8169_get_sset_count
,
1797 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1800 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1801 struct net_device
*dev
, u8 default_version
)
1803 void __iomem
*ioaddr
= tp
->mmio_addr
;
1805 * The driver currently handles the 8168Bf and the 8168Be identically
1806 * but they can be identified more specifically through the test below
1809 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1811 * Same thing for the 8101Eb and the 8101Ec:
1813 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1815 static const struct rtl_mac_info
{
1821 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36
},
1822 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35
},
1825 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34
},
1826 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
1827 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
1828 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
1831 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1832 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1833 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1835 /* 8168DP family. */
1836 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1837 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
1838 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
1841 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
1842 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1843 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1844 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1845 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1846 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1847 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1848 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1849 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1852 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1853 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1854 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1855 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1858 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
1859 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
1860 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
1861 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
1862 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1863 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1864 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1865 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1866 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1867 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1868 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1869 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1870 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1871 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1872 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1873 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1874 /* FIXME: where did these entries come from ? -- FR */
1875 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1876 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1879 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1880 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1881 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1882 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1883 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1884 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1887 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1889 const struct rtl_mac_info
*p
= mac_info
;
1892 reg
= RTL_R32(TxConfig
);
1893 while ((reg
& p
->mask
) != p
->val
)
1895 tp
->mac_version
= p
->mac_version
;
1897 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
1898 netif_notice(tp
, probe
, dev
,
1899 "unknown MAC, using family default\n");
1900 tp
->mac_version
= default_version
;
1904 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1906 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1914 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
1915 const struct phy_reg
*regs
, int len
)
1918 rtl_writephy(tp
, regs
->reg
, regs
->val
);
1923 #define PHY_READ 0x00000000
1924 #define PHY_DATA_OR 0x10000000
1925 #define PHY_DATA_AND 0x20000000
1926 #define PHY_BJMPN 0x30000000
1927 #define PHY_READ_EFUSE 0x40000000
1928 #define PHY_READ_MAC_BYTE 0x50000000
1929 #define PHY_WRITE_MAC_BYTE 0x60000000
1930 #define PHY_CLEAR_READCOUNT 0x70000000
1931 #define PHY_WRITE 0x80000000
1932 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1933 #define PHY_COMP_EQ_SKIPN 0xa0000000
1934 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1935 #define PHY_WRITE_PREVIOUS 0xc0000000
1936 #define PHY_SKIPN 0xd0000000
1937 #define PHY_DELAY_MS 0xe0000000
1938 #define PHY_WRITE_ERI_WORD 0xf0000000
1942 char version
[RTL_VER_SIZE
];
1948 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1950 static bool rtl_fw_format_ok(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1952 const struct firmware
*fw
= rtl_fw
->fw
;
1953 struct fw_info
*fw_info
= (struct fw_info
*)fw
->data
;
1954 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
1955 char *version
= rtl_fw
->version
;
1958 if (fw
->size
< FW_OPCODE_SIZE
)
1961 if (!fw_info
->magic
) {
1962 size_t i
, size
, start
;
1965 if (fw
->size
< sizeof(*fw_info
))
1968 for (i
= 0; i
< fw
->size
; i
++)
1969 checksum
+= fw
->data
[i
];
1973 start
= le32_to_cpu(fw_info
->fw_start
);
1974 if (start
> fw
->size
)
1977 size
= le32_to_cpu(fw_info
->fw_len
);
1978 if (size
> (fw
->size
- start
) / FW_OPCODE_SIZE
)
1981 memcpy(version
, fw_info
->version
, RTL_VER_SIZE
);
1983 pa
->code
= (__le32
*)(fw
->data
+ start
);
1986 if (fw
->size
% FW_OPCODE_SIZE
)
1989 strlcpy(version
, rtl_lookup_firmware_name(tp
), RTL_VER_SIZE
);
1991 pa
->code
= (__le32
*)fw
->data
;
1992 pa
->size
= fw
->size
/ FW_OPCODE_SIZE
;
1994 version
[RTL_VER_SIZE
- 1] = 0;
2001 static bool rtl_fw_data_ok(struct rtl8169_private
*tp
, struct net_device
*dev
,
2002 struct rtl_fw_phy_action
*pa
)
2007 for (index
= 0; index
< pa
->size
; index
++) {
2008 u32 action
= le32_to_cpu(pa
->code
[index
]);
2009 u32 regno
= (action
& 0x0fff0000) >> 16;
2011 switch(action
& 0xf0000000) {
2015 case PHY_READ_EFUSE
:
2016 case PHY_CLEAR_READCOUNT
:
2018 case PHY_WRITE_PREVIOUS
:
2023 if (regno
> index
) {
2024 netif_err(tp
, ifup
, tp
->dev
,
2025 "Out of range of firmware\n");
2029 case PHY_READCOUNT_EQ_SKIP
:
2030 if (index
+ 2 >= pa
->size
) {
2031 netif_err(tp
, ifup
, tp
->dev
,
2032 "Out of range of firmware\n");
2036 case PHY_COMP_EQ_SKIPN
:
2037 case PHY_COMP_NEQ_SKIPN
:
2039 if (index
+ 1 + regno
>= pa
->size
) {
2040 netif_err(tp
, ifup
, tp
->dev
,
2041 "Out of range of firmware\n");
2046 case PHY_READ_MAC_BYTE
:
2047 case PHY_WRITE_MAC_BYTE
:
2048 case PHY_WRITE_ERI_WORD
:
2050 netif_err(tp
, ifup
, tp
->dev
,
2051 "Invalid action 0x%08x\n", action
);
2060 static int rtl_check_firmware(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2062 struct net_device
*dev
= tp
->dev
;
2065 if (!rtl_fw_format_ok(tp
, rtl_fw
)) {
2066 netif_err(tp
, ifup
, dev
, "invalid firwmare\n");
2070 if (rtl_fw_data_ok(tp
, dev
, &rtl_fw
->phy_action
))
2076 static void rtl_phy_write_fw(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2078 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2082 predata
= count
= 0;
2084 for (index
= 0; index
< pa
->size
; ) {
2085 u32 action
= le32_to_cpu(pa
->code
[index
]);
2086 u32 data
= action
& 0x0000ffff;
2087 u32 regno
= (action
& 0x0fff0000) >> 16;
2092 switch(action
& 0xf0000000) {
2094 predata
= rtl_readphy(tp
, regno
);
2109 case PHY_READ_EFUSE
:
2110 predata
= rtl8168d_efuse_read(tp
->mmio_addr
, regno
);
2113 case PHY_CLEAR_READCOUNT
:
2118 rtl_writephy(tp
, regno
, data
);
2121 case PHY_READCOUNT_EQ_SKIP
:
2122 index
+= (count
== data
) ? 2 : 1;
2124 case PHY_COMP_EQ_SKIPN
:
2125 if (predata
== data
)
2129 case PHY_COMP_NEQ_SKIPN
:
2130 if (predata
!= data
)
2134 case PHY_WRITE_PREVIOUS
:
2135 rtl_writephy(tp
, regno
, predata
);
2146 case PHY_READ_MAC_BYTE
:
2147 case PHY_WRITE_MAC_BYTE
:
2148 case PHY_WRITE_ERI_WORD
:
2155 static void rtl_release_firmware(struct rtl8169_private
*tp
)
2157 if (!IS_ERR_OR_NULL(tp
->rtl_fw
)) {
2158 release_firmware(tp
->rtl_fw
->fw
);
2161 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
2164 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
2166 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
2168 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2169 if (!IS_ERR_OR_NULL(rtl_fw
))
2170 rtl_phy_write_fw(tp
, rtl_fw
);
2173 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
2175 if (rtl_readphy(tp
, reg
) != val
)
2176 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
2178 rtl_apply_firmware(tp
);
2181 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
2183 static const struct phy_reg phy_reg_init
[] = {
2245 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2248 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
2250 static const struct phy_reg phy_reg_init
[] = {
2256 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2259 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
2261 struct pci_dev
*pdev
= tp
->pci_dev
;
2263 if ((pdev
->subsystem_vendor
!= PCI_VENDOR_ID_GIGABYTE
) ||
2264 (pdev
->subsystem_device
!= 0xe000))
2267 rtl_writephy(tp
, 0x1f, 0x0001);
2268 rtl_writephy(tp
, 0x10, 0xf01b);
2269 rtl_writephy(tp
, 0x1f, 0x0000);
2272 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
2274 static const struct phy_reg phy_reg_init
[] = {
2314 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2316 rtl8169scd_hw_phy_config_quirk(tp
);
2319 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2321 static const struct phy_reg phy_reg_init
[] = {
2369 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2372 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2374 static const struct phy_reg phy_reg_init
[] = {
2379 rtl_writephy(tp
, 0x1f, 0x0001);
2380 rtl_patchphy(tp
, 0x16, 1 << 0);
2382 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2385 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2387 static const struct phy_reg phy_reg_init
[] = {
2393 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2396 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2398 static const struct phy_reg phy_reg_init
[] = {
2406 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2409 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2411 static const struct phy_reg phy_reg_init
[] = {
2417 rtl_writephy(tp
, 0x1f, 0x0000);
2418 rtl_patchphy(tp
, 0x14, 1 << 5);
2419 rtl_patchphy(tp
, 0x0d, 1 << 5);
2421 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2424 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2426 static const struct phy_reg phy_reg_init
[] = {
2446 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2448 rtl_patchphy(tp
, 0x14, 1 << 5);
2449 rtl_patchphy(tp
, 0x0d, 1 << 5);
2450 rtl_writephy(tp
, 0x1f, 0x0000);
2453 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2455 static const struct phy_reg phy_reg_init
[] = {
2473 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2475 rtl_patchphy(tp
, 0x16, 1 << 0);
2476 rtl_patchphy(tp
, 0x14, 1 << 5);
2477 rtl_patchphy(tp
, 0x0d, 1 << 5);
2478 rtl_writephy(tp
, 0x1f, 0x0000);
2481 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2483 static const struct phy_reg phy_reg_init
[] = {
2495 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2497 rtl_patchphy(tp
, 0x16, 1 << 0);
2498 rtl_patchphy(tp
, 0x14, 1 << 5);
2499 rtl_patchphy(tp
, 0x0d, 1 << 5);
2500 rtl_writephy(tp
, 0x1f, 0x0000);
2503 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2505 rtl8168c_3_hw_phy_config(tp
);
2508 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2510 static const struct phy_reg phy_reg_init_0
[] = {
2511 /* Channel Estimation */
2532 * Enhance line driver power
2541 * Can not link to 1Gbps with bad cable
2542 * Decrease SNR threshold form 21.07dB to 19.04dB
2550 void __iomem
*ioaddr
= tp
->mmio_addr
;
2552 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2556 * Fine Tune Switching regulator parameter
2558 rtl_writephy(tp
, 0x1f, 0x0002);
2559 rtl_w1w0_phy(tp
, 0x0b, 0x0010, 0x00ef);
2560 rtl_w1w0_phy(tp
, 0x0c, 0xa200, 0x5d00);
2562 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2563 static const struct phy_reg phy_reg_init
[] = {
2573 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2575 val
= rtl_readphy(tp
, 0x0d);
2577 if ((val
& 0x00ff) != 0x006c) {
2578 static const u32 set
[] = {
2579 0x0065, 0x0066, 0x0067, 0x0068,
2580 0x0069, 0x006a, 0x006b, 0x006c
2584 rtl_writephy(tp
, 0x1f, 0x0002);
2587 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2588 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2591 static const struct phy_reg phy_reg_init
[] = {
2599 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2602 /* RSET couple improve */
2603 rtl_writephy(tp
, 0x1f, 0x0002);
2604 rtl_patchphy(tp
, 0x0d, 0x0300);
2605 rtl_patchphy(tp
, 0x0f, 0x0010);
2607 /* Fine tune PLL performance */
2608 rtl_writephy(tp
, 0x1f, 0x0002);
2609 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2610 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2612 rtl_writephy(tp
, 0x1f, 0x0005);
2613 rtl_writephy(tp
, 0x05, 0x001b);
2615 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
2617 rtl_writephy(tp
, 0x1f, 0x0000);
2620 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
2622 static const struct phy_reg phy_reg_init_0
[] = {
2623 /* Channel Estimation */
2644 * Enhance line driver power
2653 * Can not link to 1Gbps with bad cable
2654 * Decrease SNR threshold form 21.07dB to 19.04dB
2662 void __iomem
*ioaddr
= tp
->mmio_addr
;
2664 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2666 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2667 static const struct phy_reg phy_reg_init
[] = {
2678 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2680 val
= rtl_readphy(tp
, 0x0d);
2681 if ((val
& 0x00ff) != 0x006c) {
2682 static const u32 set
[] = {
2683 0x0065, 0x0066, 0x0067, 0x0068,
2684 0x0069, 0x006a, 0x006b, 0x006c
2688 rtl_writephy(tp
, 0x1f, 0x0002);
2691 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2692 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2695 static const struct phy_reg phy_reg_init
[] = {
2703 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2706 /* Fine tune PLL performance */
2707 rtl_writephy(tp
, 0x1f, 0x0002);
2708 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2709 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2711 /* Switching regulator Slew rate */
2712 rtl_writephy(tp
, 0x1f, 0x0002);
2713 rtl_patchphy(tp
, 0x0f, 0x0017);
2715 rtl_writephy(tp
, 0x1f, 0x0005);
2716 rtl_writephy(tp
, 0x05, 0x001b);
2718 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
2720 rtl_writephy(tp
, 0x1f, 0x0000);
2723 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
2725 static const struct phy_reg phy_reg_init
[] = {
2781 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2784 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
2786 static const struct phy_reg phy_reg_init
[] = {
2796 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2797 rtl_patchphy(tp
, 0x0d, 1 << 5);
2800 static void rtl8168e_1_hw_phy_config(struct rtl8169_private
*tp
)
2802 static const struct phy_reg phy_reg_init
[] = {
2803 /* Enable Delay cap */
2809 /* Channel estimation fine tune */
2818 /* Update PFM & 10M TX idle timer */
2830 rtl_apply_firmware(tp
);
2832 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2834 /* DCO enable for 10M IDLE Power */
2835 rtl_writephy(tp
, 0x1f, 0x0007);
2836 rtl_writephy(tp
, 0x1e, 0x0023);
2837 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2838 rtl_writephy(tp
, 0x1f, 0x0000);
2840 /* For impedance matching */
2841 rtl_writephy(tp
, 0x1f, 0x0002);
2842 rtl_w1w0_phy(tp
, 0x08, 0x8000, 0x7f00);
2843 rtl_writephy(tp
, 0x1f, 0x0000);
2845 /* PHY auto speed down */
2846 rtl_writephy(tp
, 0x1f, 0x0007);
2847 rtl_writephy(tp
, 0x1e, 0x002d);
2848 rtl_w1w0_phy(tp
, 0x18, 0x0050, 0x0000);
2849 rtl_writephy(tp
, 0x1f, 0x0000);
2850 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2852 rtl_writephy(tp
, 0x1f, 0x0005);
2853 rtl_writephy(tp
, 0x05, 0x8b86);
2854 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2855 rtl_writephy(tp
, 0x1f, 0x0000);
2857 rtl_writephy(tp
, 0x1f, 0x0005);
2858 rtl_writephy(tp
, 0x05, 0x8b85);
2859 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2860 rtl_writephy(tp
, 0x1f, 0x0007);
2861 rtl_writephy(tp
, 0x1e, 0x0020);
2862 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x1100);
2863 rtl_writephy(tp
, 0x1f, 0x0006);
2864 rtl_writephy(tp
, 0x00, 0x5a00);
2865 rtl_writephy(tp
, 0x1f, 0x0000);
2866 rtl_writephy(tp
, 0x0d, 0x0007);
2867 rtl_writephy(tp
, 0x0e, 0x003c);
2868 rtl_writephy(tp
, 0x0d, 0x4007);
2869 rtl_writephy(tp
, 0x0e, 0x0000);
2870 rtl_writephy(tp
, 0x0d, 0x0000);
2873 static void rtl8168e_2_hw_phy_config(struct rtl8169_private
*tp
)
2875 static const struct phy_reg phy_reg_init
[] = {
2876 /* Enable Delay cap */
2885 /* Channel estimation fine tune */
2902 rtl_apply_firmware(tp
);
2904 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2906 /* For 4-corner performance improve */
2907 rtl_writephy(tp
, 0x1f, 0x0005);
2908 rtl_writephy(tp
, 0x05, 0x8b80);
2909 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2910 rtl_writephy(tp
, 0x1f, 0x0000);
2912 /* PHY auto speed down */
2913 rtl_writephy(tp
, 0x1f, 0x0004);
2914 rtl_writephy(tp
, 0x1f, 0x0007);
2915 rtl_writephy(tp
, 0x1e, 0x002d);
2916 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
2917 rtl_writephy(tp
, 0x1f, 0x0002);
2918 rtl_writephy(tp
, 0x1f, 0x0000);
2919 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2921 /* improve 10M EEE waveform */
2922 rtl_writephy(tp
, 0x1f, 0x0005);
2923 rtl_writephy(tp
, 0x05, 0x8b86);
2924 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2925 rtl_writephy(tp
, 0x1f, 0x0000);
2927 /* Improve 2-pair detection performance */
2928 rtl_writephy(tp
, 0x1f, 0x0005);
2929 rtl_writephy(tp
, 0x05, 0x8b85);
2930 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
2931 rtl_writephy(tp
, 0x1f, 0x0000);
2934 rtl_w1w0_eri(tp
->mmio_addr
, 0x1b0, ERIAR_MASK_1111
, 0x0000, 0x0003,
2936 rtl_writephy(tp
, 0x1f, 0x0005);
2937 rtl_writephy(tp
, 0x05, 0x8b85);
2938 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2939 rtl_writephy(tp
, 0x1f, 0x0004);
2940 rtl_writephy(tp
, 0x1f, 0x0007);
2941 rtl_writephy(tp
, 0x1e, 0x0020);
2942 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x0100);
2943 rtl_writephy(tp
, 0x1f, 0x0002);
2944 rtl_writephy(tp
, 0x1f, 0x0000);
2945 rtl_writephy(tp
, 0x0d, 0x0007);
2946 rtl_writephy(tp
, 0x0e, 0x003c);
2947 rtl_writephy(tp
, 0x0d, 0x4007);
2948 rtl_writephy(tp
, 0x0e, 0x0000);
2949 rtl_writephy(tp
, 0x0d, 0x0000);
2952 rtl_writephy(tp
, 0x1f, 0x0003);
2953 rtl_w1w0_phy(tp
, 0x19, 0x0000, 0x0001);
2954 rtl_w1w0_phy(tp
, 0x10, 0x0000, 0x0400);
2955 rtl_writephy(tp
, 0x1f, 0x0000);
2958 static void rtl8168f_1_hw_phy_config(struct rtl8169_private
*tp
)
2960 static const struct phy_reg phy_reg_init
[] = {
2961 /* Channel estimation fine tune */
2966 /* Modify green table for giga & fnet */
2983 /* Modify green table for 10M */
2989 /* Disable hiimpedance detection (RTCT) */
2995 rtl_apply_firmware(tp
);
2997 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2999 /* For 4-corner performance improve */
3000 rtl_writephy(tp
, 0x1f, 0x0005);
3001 rtl_writephy(tp
, 0x05, 0x8b80);
3002 rtl_w1w0_phy(tp
, 0x06, 0x0006, 0x0000);
3003 rtl_writephy(tp
, 0x1f, 0x0000);
3005 /* PHY auto speed down */
3006 rtl_writephy(tp
, 0x1f, 0x0007);
3007 rtl_writephy(tp
, 0x1e, 0x002d);
3008 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
3009 rtl_writephy(tp
, 0x1f, 0x0000);
3010 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
3012 /* Improve 10M EEE waveform */
3013 rtl_writephy(tp
, 0x1f, 0x0005);
3014 rtl_writephy(tp
, 0x05, 0x8b86);
3015 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
3016 rtl_writephy(tp
, 0x1f, 0x0000);
3018 /* Improve 2-pair detection performance */
3019 rtl_writephy(tp
, 0x1f, 0x0005);
3020 rtl_writephy(tp
, 0x05, 0x8b85);
3021 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
3022 rtl_writephy(tp
, 0x1f, 0x0000);
3025 static void rtl8168f_2_hw_phy_config(struct rtl8169_private
*tp
)
3027 rtl_apply_firmware(tp
);
3029 /* For 4-corner performance improve */
3030 rtl_writephy(tp
, 0x1f, 0x0005);
3031 rtl_writephy(tp
, 0x05, 0x8b80);
3032 rtl_w1w0_phy(tp
, 0x06, 0x0006, 0x0000);
3033 rtl_writephy(tp
, 0x1f, 0x0000);
3035 /* PHY auto speed down */
3036 rtl_writephy(tp
, 0x1f, 0x0007);
3037 rtl_writephy(tp
, 0x1e, 0x002d);
3038 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
3039 rtl_writephy(tp
, 0x1f, 0x0000);
3040 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
3042 /* Improve 10M EEE waveform */
3043 rtl_writephy(tp
, 0x1f, 0x0005);
3044 rtl_writephy(tp
, 0x05, 0x8b86);
3045 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
3046 rtl_writephy(tp
, 0x1f, 0x0000);
3049 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
3051 static const struct phy_reg phy_reg_init
[] = {
3058 rtl_writephy(tp
, 0x1f, 0x0000);
3059 rtl_patchphy(tp
, 0x11, 1 << 12);
3060 rtl_patchphy(tp
, 0x19, 1 << 13);
3061 rtl_patchphy(tp
, 0x10, 1 << 15);
3063 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3066 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
3068 static const struct phy_reg phy_reg_init
[] = {
3082 /* Disable ALDPS before ram code */
3083 rtl_writephy(tp
, 0x1f, 0x0000);
3084 rtl_writephy(tp
, 0x18, 0x0310);
3087 rtl_apply_firmware(tp
);
3089 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3092 static void rtl_hw_phy_config(struct net_device
*dev
)
3094 struct rtl8169_private
*tp
= netdev_priv(dev
);
3096 rtl8169_print_mac_version(tp
);
3098 switch (tp
->mac_version
) {
3099 case RTL_GIGA_MAC_VER_01
:
3101 case RTL_GIGA_MAC_VER_02
:
3102 case RTL_GIGA_MAC_VER_03
:
3103 rtl8169s_hw_phy_config(tp
);
3105 case RTL_GIGA_MAC_VER_04
:
3106 rtl8169sb_hw_phy_config(tp
);
3108 case RTL_GIGA_MAC_VER_05
:
3109 rtl8169scd_hw_phy_config(tp
);
3111 case RTL_GIGA_MAC_VER_06
:
3112 rtl8169sce_hw_phy_config(tp
);
3114 case RTL_GIGA_MAC_VER_07
:
3115 case RTL_GIGA_MAC_VER_08
:
3116 case RTL_GIGA_MAC_VER_09
:
3117 rtl8102e_hw_phy_config(tp
);
3119 case RTL_GIGA_MAC_VER_11
:
3120 rtl8168bb_hw_phy_config(tp
);
3122 case RTL_GIGA_MAC_VER_12
:
3123 rtl8168bef_hw_phy_config(tp
);
3125 case RTL_GIGA_MAC_VER_17
:
3126 rtl8168bef_hw_phy_config(tp
);
3128 case RTL_GIGA_MAC_VER_18
:
3129 rtl8168cp_1_hw_phy_config(tp
);
3131 case RTL_GIGA_MAC_VER_19
:
3132 rtl8168c_1_hw_phy_config(tp
);
3134 case RTL_GIGA_MAC_VER_20
:
3135 rtl8168c_2_hw_phy_config(tp
);
3137 case RTL_GIGA_MAC_VER_21
:
3138 rtl8168c_3_hw_phy_config(tp
);
3140 case RTL_GIGA_MAC_VER_22
:
3141 rtl8168c_4_hw_phy_config(tp
);
3143 case RTL_GIGA_MAC_VER_23
:
3144 case RTL_GIGA_MAC_VER_24
:
3145 rtl8168cp_2_hw_phy_config(tp
);
3147 case RTL_GIGA_MAC_VER_25
:
3148 rtl8168d_1_hw_phy_config(tp
);
3150 case RTL_GIGA_MAC_VER_26
:
3151 rtl8168d_2_hw_phy_config(tp
);
3153 case RTL_GIGA_MAC_VER_27
:
3154 rtl8168d_3_hw_phy_config(tp
);
3156 case RTL_GIGA_MAC_VER_28
:
3157 rtl8168d_4_hw_phy_config(tp
);
3159 case RTL_GIGA_MAC_VER_29
:
3160 case RTL_GIGA_MAC_VER_30
:
3161 rtl8105e_hw_phy_config(tp
);
3163 case RTL_GIGA_MAC_VER_31
:
3166 case RTL_GIGA_MAC_VER_32
:
3167 case RTL_GIGA_MAC_VER_33
:
3168 rtl8168e_1_hw_phy_config(tp
);
3170 case RTL_GIGA_MAC_VER_34
:
3171 rtl8168e_2_hw_phy_config(tp
);
3173 case RTL_GIGA_MAC_VER_35
:
3174 rtl8168f_1_hw_phy_config(tp
);
3176 case RTL_GIGA_MAC_VER_36
:
3177 rtl8168f_2_hw_phy_config(tp
);
3185 static void rtl8169_phy_timer(unsigned long __opaque
)
3187 struct net_device
*dev
= (struct net_device
*)__opaque
;
3188 struct rtl8169_private
*tp
= netdev_priv(dev
);
3189 struct timer_list
*timer
= &tp
->timer
;
3190 void __iomem
*ioaddr
= tp
->mmio_addr
;
3191 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
3193 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
3195 spin_lock_irq(&tp
->lock
);
3197 if (tp
->phy_reset_pending(tp
)) {
3199 * A busy loop could burn quite a few cycles on nowadays CPU.
3200 * Let's delay the execution of the timer for a few ticks.
3206 if (tp
->link_ok(ioaddr
))
3209 netif_warn(tp
, link
, dev
, "PHY reset until link up\n");
3211 tp
->phy_reset_enable(tp
);
3214 mod_timer(timer
, jiffies
+ timeout
);
3216 spin_unlock_irq(&tp
->lock
);
3219 #ifdef CONFIG_NET_POLL_CONTROLLER
3221 * Polling 'interrupt' - used by things like netconsole to send skbs
3222 * without having to re-enable interrupts. It's not called while
3223 * the interrupt routine is executing.
3225 static void rtl8169_netpoll(struct net_device
*dev
)
3227 struct rtl8169_private
*tp
= netdev_priv(dev
);
3228 struct pci_dev
*pdev
= tp
->pci_dev
;
3230 disable_irq(pdev
->irq
);
3231 rtl8169_interrupt(pdev
->irq
, dev
);
3232 enable_irq(pdev
->irq
);
3236 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
3237 void __iomem
*ioaddr
)
3240 pci_release_regions(pdev
);
3241 pci_clear_mwi(pdev
);
3242 pci_disable_device(pdev
);
3246 static void rtl8169_phy_reset(struct net_device
*dev
,
3247 struct rtl8169_private
*tp
)
3251 tp
->phy_reset_enable(tp
);
3252 for (i
= 0; i
< 100; i
++) {
3253 if (!tp
->phy_reset_pending(tp
))
3257 netif_err(tp
, link
, dev
, "PHY reset failed\n");
3260 static bool rtl_tbi_enabled(struct rtl8169_private
*tp
)
3262 void __iomem
*ioaddr
= tp
->mmio_addr
;
3264 return (tp
->mac_version
== RTL_GIGA_MAC_VER_01
) &&
3265 (RTL_R8(PHYstatus
) & TBI_Enable
);
3268 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
3270 void __iomem
*ioaddr
= tp
->mmio_addr
;
3272 rtl_hw_phy_config(dev
);
3274 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
3275 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3279 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
3281 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
3282 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
3284 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
3285 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3287 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3288 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
3291 rtl8169_phy_reset(dev
, tp
);
3293 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
3294 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
3295 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
3296 (tp
->mii
.supports_gmii
?
3297 ADVERTISED_1000baseT_Half
|
3298 ADVERTISED_1000baseT_Full
: 0));
3300 if (rtl_tbi_enabled(tp
))
3301 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
3304 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
3306 void __iomem
*ioaddr
= tp
->mmio_addr
;
3310 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
3311 high
= addr
[4] | (addr
[5] << 8);
3313 spin_lock_irq(&tp
->lock
);
3315 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3317 RTL_W32(MAC4
, high
);
3323 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
3324 const struct exgmac_reg e
[] = {
3325 { .addr
= 0xe0, ERIAR_MASK_1111
, .val
= low
},
3326 { .addr
= 0xe4, ERIAR_MASK_1111
, .val
= high
},
3327 { .addr
= 0xf0, ERIAR_MASK_1111
, .val
= low
<< 16 },
3328 { .addr
= 0xf4, ERIAR_MASK_1111
, .val
= high
<< 16 |
3332 rtl_write_exgmac_batch(ioaddr
, e
, ARRAY_SIZE(e
));
3335 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3337 spin_unlock_irq(&tp
->lock
);
3340 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
3342 struct rtl8169_private
*tp
= netdev_priv(dev
);
3343 struct sockaddr
*addr
= p
;
3345 if (!is_valid_ether_addr(addr
->sa_data
))
3346 return -EADDRNOTAVAIL
;
3348 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
3350 rtl_rar_set(tp
, dev
->dev_addr
);
3355 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3357 struct rtl8169_private
*tp
= netdev_priv(dev
);
3358 struct mii_ioctl_data
*data
= if_mii(ifr
);
3360 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
3363 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
,
3364 struct mii_ioctl_data
*data
, int cmd
)
3368 data
->phy_id
= 32; /* Internal PHY */
3372 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
3376 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
3382 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
3387 static const struct rtl_cfg_info
{
3388 void (*hw_start
)(struct net_device
*);
3389 unsigned int region
;
3395 } rtl_cfg_infos
[] = {
3397 .hw_start
= rtl_hw_start_8169
,
3400 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
3401 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
3402 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
3403 .features
= RTL_FEATURE_GMII
,
3404 .default_ver
= RTL_GIGA_MAC_VER_01
,
3407 .hw_start
= rtl_hw_start_8168
,
3410 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
3411 TxErr
| TxOK
| RxOK
| RxErr
,
3412 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
3413 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
3414 .default_ver
= RTL_GIGA_MAC_VER_11
,
3417 .hw_start
= rtl_hw_start_8101
,
3420 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
3421 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
3422 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
3423 .features
= RTL_FEATURE_MSI
,
3424 .default_ver
= RTL_GIGA_MAC_VER_13
,
3428 /* Cfg9346_Unlock assumed. */
3429 static unsigned rtl_try_msi(struct rtl8169_private
*tp
,
3430 const struct rtl_cfg_info
*cfg
)
3432 void __iomem
*ioaddr
= tp
->mmio_addr
;
3436 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
3437 if (cfg
->features
& RTL_FEATURE_MSI
) {
3438 if (pci_enable_msi(tp
->pci_dev
)) {
3439 netif_info(tp
, hw
, tp
->dev
, "no MSI. Back to INTx.\n");
3442 msi
= RTL_FEATURE_MSI
;
3445 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
3446 RTL_W8(Config2
, cfg2
);
3450 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
3452 if (tp
->features
& RTL_FEATURE_MSI
) {
3453 pci_disable_msi(pdev
);
3454 tp
->features
&= ~RTL_FEATURE_MSI
;
3458 static const struct net_device_ops rtl8169_netdev_ops
= {
3459 .ndo_open
= rtl8169_open
,
3460 .ndo_stop
= rtl8169_close
,
3461 .ndo_get_stats
= rtl8169_get_stats
,
3462 .ndo_start_xmit
= rtl8169_start_xmit
,
3463 .ndo_tx_timeout
= rtl8169_tx_timeout
,
3464 .ndo_validate_addr
= eth_validate_addr
,
3465 .ndo_change_mtu
= rtl8169_change_mtu
,
3466 .ndo_fix_features
= rtl8169_fix_features
,
3467 .ndo_set_features
= rtl8169_set_features
,
3468 .ndo_set_mac_address
= rtl_set_mac_address
,
3469 .ndo_do_ioctl
= rtl8169_ioctl
,
3470 .ndo_set_rx_mode
= rtl_set_rx_mode
,
3471 #ifdef CONFIG_NET_POLL_CONTROLLER
3472 .ndo_poll_controller
= rtl8169_netpoll
,
3477 static void __devinit
rtl_init_mdio_ops(struct rtl8169_private
*tp
)
3479 struct mdio_ops
*ops
= &tp
->mdio_ops
;
3481 switch (tp
->mac_version
) {
3482 case RTL_GIGA_MAC_VER_27
:
3483 ops
->write
= r8168dp_1_mdio_write
;
3484 ops
->read
= r8168dp_1_mdio_read
;
3486 case RTL_GIGA_MAC_VER_28
:
3487 case RTL_GIGA_MAC_VER_31
:
3488 ops
->write
= r8168dp_2_mdio_write
;
3489 ops
->read
= r8168dp_2_mdio_read
;
3492 ops
->write
= r8169_mdio_write
;
3493 ops
->read
= r8169_mdio_read
;
3498 static void rtl_wol_suspend_quirk(struct rtl8169_private
*tp
)
3500 void __iomem
*ioaddr
= tp
->mmio_addr
;
3502 switch (tp
->mac_version
) {
3503 case RTL_GIGA_MAC_VER_29
:
3504 case RTL_GIGA_MAC_VER_30
:
3505 case RTL_GIGA_MAC_VER_32
:
3506 case RTL_GIGA_MAC_VER_33
:
3507 case RTL_GIGA_MAC_VER_34
:
3508 RTL_W32(RxConfig
, RTL_R32(RxConfig
) |
3509 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
3516 static bool rtl_wol_pll_power_down(struct rtl8169_private
*tp
)
3518 if (!(__rtl8169_get_wol(tp
) & WAKE_ANY
))
3521 rtl_writephy(tp
, 0x1f, 0x0000);
3522 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3524 rtl_wol_suspend_quirk(tp
);
3529 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
3531 rtl_writephy(tp
, 0x1f, 0x0000);
3532 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3535 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
3537 rtl_writephy(tp
, 0x1f, 0x0000);
3538 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3541 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
3543 if (rtl_wol_pll_power_down(tp
))
3546 r810x_phy_power_down(tp
);
3549 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
3551 r810x_phy_power_up(tp
);
3554 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
3556 rtl_writephy(tp
, 0x1f, 0x0000);
3557 switch (tp
->mac_version
) {
3558 case RTL_GIGA_MAC_VER_11
:
3559 case RTL_GIGA_MAC_VER_12
:
3560 case RTL_GIGA_MAC_VER_17
:
3561 case RTL_GIGA_MAC_VER_18
:
3562 case RTL_GIGA_MAC_VER_19
:
3563 case RTL_GIGA_MAC_VER_20
:
3564 case RTL_GIGA_MAC_VER_21
:
3565 case RTL_GIGA_MAC_VER_22
:
3566 case RTL_GIGA_MAC_VER_23
:
3567 case RTL_GIGA_MAC_VER_24
:
3568 case RTL_GIGA_MAC_VER_25
:
3569 case RTL_GIGA_MAC_VER_26
:
3570 case RTL_GIGA_MAC_VER_27
:
3571 case RTL_GIGA_MAC_VER_28
:
3572 case RTL_GIGA_MAC_VER_31
:
3573 rtl_writephy(tp
, 0x0e, 0x0000);
3578 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3581 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
3583 rtl_writephy(tp
, 0x1f, 0x0000);
3584 switch (tp
->mac_version
) {
3585 case RTL_GIGA_MAC_VER_32
:
3586 case RTL_GIGA_MAC_VER_33
:
3587 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
3590 case RTL_GIGA_MAC_VER_11
:
3591 case RTL_GIGA_MAC_VER_12
:
3592 case RTL_GIGA_MAC_VER_17
:
3593 case RTL_GIGA_MAC_VER_18
:
3594 case RTL_GIGA_MAC_VER_19
:
3595 case RTL_GIGA_MAC_VER_20
:
3596 case RTL_GIGA_MAC_VER_21
:
3597 case RTL_GIGA_MAC_VER_22
:
3598 case RTL_GIGA_MAC_VER_23
:
3599 case RTL_GIGA_MAC_VER_24
:
3600 case RTL_GIGA_MAC_VER_25
:
3601 case RTL_GIGA_MAC_VER_26
:
3602 case RTL_GIGA_MAC_VER_27
:
3603 case RTL_GIGA_MAC_VER_28
:
3604 case RTL_GIGA_MAC_VER_31
:
3605 rtl_writephy(tp
, 0x0e, 0x0200);
3607 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3612 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
3614 void __iomem
*ioaddr
= tp
->mmio_addr
;
3616 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3617 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3618 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3619 r8168dp_check_dash(tp
)) {
3623 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_23
||
3624 tp
->mac_version
== RTL_GIGA_MAC_VER_24
) &&
3625 (RTL_R16(CPlusCmd
) & ASF
)) {
3629 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3630 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
3631 rtl_ephy_write(ioaddr
, 0x19, 0xff64);
3633 if (rtl_wol_pll_power_down(tp
))
3636 r8168_phy_power_down(tp
);
3638 switch (tp
->mac_version
) {
3639 case RTL_GIGA_MAC_VER_25
:
3640 case RTL_GIGA_MAC_VER_26
:
3641 case RTL_GIGA_MAC_VER_27
:
3642 case RTL_GIGA_MAC_VER_28
:
3643 case RTL_GIGA_MAC_VER_31
:
3644 case RTL_GIGA_MAC_VER_32
:
3645 case RTL_GIGA_MAC_VER_33
:
3646 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
3651 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
3653 void __iomem
*ioaddr
= tp
->mmio_addr
;
3655 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3656 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3657 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3658 r8168dp_check_dash(tp
)) {
3662 switch (tp
->mac_version
) {
3663 case RTL_GIGA_MAC_VER_25
:
3664 case RTL_GIGA_MAC_VER_26
:
3665 case RTL_GIGA_MAC_VER_27
:
3666 case RTL_GIGA_MAC_VER_28
:
3667 case RTL_GIGA_MAC_VER_31
:
3668 case RTL_GIGA_MAC_VER_32
:
3669 case RTL_GIGA_MAC_VER_33
:
3670 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
3674 r8168_phy_power_up(tp
);
3677 static void rtl_generic_op(struct rtl8169_private
*tp
,
3678 void (*op
)(struct rtl8169_private
*))
3684 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
3686 rtl_generic_op(tp
, tp
->pll_power_ops
.down
);
3689 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
3691 rtl_generic_op(tp
, tp
->pll_power_ops
.up
);
3694 static void __devinit
rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
3696 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
3698 switch (tp
->mac_version
) {
3699 case RTL_GIGA_MAC_VER_07
:
3700 case RTL_GIGA_MAC_VER_08
:
3701 case RTL_GIGA_MAC_VER_09
:
3702 case RTL_GIGA_MAC_VER_10
:
3703 case RTL_GIGA_MAC_VER_16
:
3704 case RTL_GIGA_MAC_VER_29
:
3705 case RTL_GIGA_MAC_VER_30
:
3706 ops
->down
= r810x_pll_power_down
;
3707 ops
->up
= r810x_pll_power_up
;
3710 case RTL_GIGA_MAC_VER_11
:
3711 case RTL_GIGA_MAC_VER_12
:
3712 case RTL_GIGA_MAC_VER_17
:
3713 case RTL_GIGA_MAC_VER_18
:
3714 case RTL_GIGA_MAC_VER_19
:
3715 case RTL_GIGA_MAC_VER_20
:
3716 case RTL_GIGA_MAC_VER_21
:
3717 case RTL_GIGA_MAC_VER_22
:
3718 case RTL_GIGA_MAC_VER_23
:
3719 case RTL_GIGA_MAC_VER_24
:
3720 case RTL_GIGA_MAC_VER_25
:
3721 case RTL_GIGA_MAC_VER_26
:
3722 case RTL_GIGA_MAC_VER_27
:
3723 case RTL_GIGA_MAC_VER_28
:
3724 case RTL_GIGA_MAC_VER_31
:
3725 case RTL_GIGA_MAC_VER_32
:
3726 case RTL_GIGA_MAC_VER_33
:
3727 case RTL_GIGA_MAC_VER_34
:
3728 case RTL_GIGA_MAC_VER_35
:
3729 case RTL_GIGA_MAC_VER_36
:
3730 ops
->down
= r8168_pll_power_down
;
3731 ops
->up
= r8168_pll_power_up
;
3741 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
3743 void __iomem
*ioaddr
= tp
->mmio_addr
;
3745 switch (tp
->mac_version
) {
3746 case RTL_GIGA_MAC_VER_01
:
3747 case RTL_GIGA_MAC_VER_02
:
3748 case RTL_GIGA_MAC_VER_03
:
3749 case RTL_GIGA_MAC_VER_04
:
3750 case RTL_GIGA_MAC_VER_05
:
3751 case RTL_GIGA_MAC_VER_06
:
3752 case RTL_GIGA_MAC_VER_10
:
3753 case RTL_GIGA_MAC_VER_11
:
3754 case RTL_GIGA_MAC_VER_12
:
3755 case RTL_GIGA_MAC_VER_13
:
3756 case RTL_GIGA_MAC_VER_14
:
3757 case RTL_GIGA_MAC_VER_15
:
3758 case RTL_GIGA_MAC_VER_16
:
3759 case RTL_GIGA_MAC_VER_17
:
3760 RTL_W32(RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
3762 case RTL_GIGA_MAC_VER_18
:
3763 case RTL_GIGA_MAC_VER_19
:
3764 case RTL_GIGA_MAC_VER_20
:
3765 case RTL_GIGA_MAC_VER_21
:
3766 case RTL_GIGA_MAC_VER_22
:
3767 case RTL_GIGA_MAC_VER_23
:
3768 case RTL_GIGA_MAC_VER_24
:
3769 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
3772 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
3777 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
3779 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
3782 static void rtl_hw_jumbo_enable(struct rtl8169_private
*tp
)
3784 rtl_generic_op(tp
, tp
->jumbo_ops
.enable
);
3787 static void rtl_hw_jumbo_disable(struct rtl8169_private
*tp
)
3789 rtl_generic_op(tp
, tp
->jumbo_ops
.disable
);
3792 static void r8168c_hw_jumbo_enable(struct rtl8169_private
*tp
)
3794 void __iomem
*ioaddr
= tp
->mmio_addr
;
3796 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
3797 RTL_W8(Config4
, RTL_R8(Config4
) | Jumbo_En1
);
3798 rtl_tx_performance_tweak(tp
->pci_dev
, 0x2 << MAX_READ_REQUEST_SHIFT
);
3801 static void r8168c_hw_jumbo_disable(struct rtl8169_private
*tp
)
3803 void __iomem
*ioaddr
= tp
->mmio_addr
;
3805 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
3806 RTL_W8(Config4
, RTL_R8(Config4
) & ~Jumbo_En1
);
3807 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3810 static void r8168dp_hw_jumbo_enable(struct rtl8169_private
*tp
)
3812 void __iomem
*ioaddr
= tp
->mmio_addr
;
3814 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
3817 static void r8168dp_hw_jumbo_disable(struct rtl8169_private
*tp
)
3819 void __iomem
*ioaddr
= tp
->mmio_addr
;
3821 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
3824 static void r8168e_hw_jumbo_enable(struct rtl8169_private
*tp
)
3826 void __iomem
*ioaddr
= tp
->mmio_addr
;
3827 struct pci_dev
*pdev
= tp
->pci_dev
;
3829 RTL_W8(MaxTxPacketSize
, 0x3f);
3830 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
3831 RTL_W8(Config4
, RTL_R8(Config4
) | 0x01);
3832 pci_write_config_byte(pdev
, 0x79, 0x20);
3835 static void r8168e_hw_jumbo_disable(struct rtl8169_private
*tp
)
3837 void __iomem
*ioaddr
= tp
->mmio_addr
;
3838 struct pci_dev
*pdev
= tp
->pci_dev
;
3840 RTL_W8(MaxTxPacketSize
, 0x0c);
3841 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
3842 RTL_W8(Config4
, RTL_R8(Config4
) & ~0x01);
3843 pci_write_config_byte(pdev
, 0x79, 0x50);
3846 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private
*tp
)
3848 rtl_tx_performance_tweak(tp
->pci_dev
,
3849 (0x2 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3852 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private
*tp
)
3854 rtl_tx_performance_tweak(tp
->pci_dev
,
3855 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3858 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private
*tp
)
3860 void __iomem
*ioaddr
= tp
->mmio_addr
;
3862 r8168b_0_hw_jumbo_enable(tp
);
3864 RTL_W8(Config4
, RTL_R8(Config4
) | (1 << 0));
3867 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private
*tp
)
3869 void __iomem
*ioaddr
= tp
->mmio_addr
;
3871 r8168b_0_hw_jumbo_disable(tp
);
3873 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
3876 static void __devinit
rtl_init_jumbo_ops(struct rtl8169_private
*tp
)
3878 struct jumbo_ops
*ops
= &tp
->jumbo_ops
;
3880 switch (tp
->mac_version
) {
3881 case RTL_GIGA_MAC_VER_11
:
3882 ops
->disable
= r8168b_0_hw_jumbo_disable
;
3883 ops
->enable
= r8168b_0_hw_jumbo_enable
;
3885 case RTL_GIGA_MAC_VER_12
:
3886 case RTL_GIGA_MAC_VER_17
:
3887 ops
->disable
= r8168b_1_hw_jumbo_disable
;
3888 ops
->enable
= r8168b_1_hw_jumbo_enable
;
3890 case RTL_GIGA_MAC_VER_18
: /* Wild guess. Needs info from Realtek. */
3891 case RTL_GIGA_MAC_VER_19
:
3892 case RTL_GIGA_MAC_VER_20
:
3893 case RTL_GIGA_MAC_VER_21
: /* Wild guess. Needs info from Realtek. */
3894 case RTL_GIGA_MAC_VER_22
:
3895 case RTL_GIGA_MAC_VER_23
:
3896 case RTL_GIGA_MAC_VER_24
:
3897 case RTL_GIGA_MAC_VER_25
:
3898 case RTL_GIGA_MAC_VER_26
:
3899 ops
->disable
= r8168c_hw_jumbo_disable
;
3900 ops
->enable
= r8168c_hw_jumbo_enable
;
3902 case RTL_GIGA_MAC_VER_27
:
3903 case RTL_GIGA_MAC_VER_28
:
3904 ops
->disable
= r8168dp_hw_jumbo_disable
;
3905 ops
->enable
= r8168dp_hw_jumbo_enable
;
3907 case RTL_GIGA_MAC_VER_31
: /* Wild guess. Needs info from Realtek. */
3908 case RTL_GIGA_MAC_VER_32
:
3909 case RTL_GIGA_MAC_VER_33
:
3910 case RTL_GIGA_MAC_VER_34
:
3911 ops
->disable
= r8168e_hw_jumbo_disable
;
3912 ops
->enable
= r8168e_hw_jumbo_enable
;
3916 * No action needed for jumbo frames with 8169.
3917 * No jumbo for 810x at all.
3920 ops
->disable
= NULL
;
3926 static void rtl_hw_reset(struct rtl8169_private
*tp
)
3928 void __iomem
*ioaddr
= tp
->mmio_addr
;
3931 /* Soft reset the chip. */
3932 RTL_W8(ChipCmd
, CmdReset
);
3934 /* Check that the chip has finished the reset. */
3935 for (i
= 0; i
< 100; i
++) {
3936 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3942 static int __devinit
3943 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
3945 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
3946 const unsigned int region
= cfg
->region
;
3947 struct rtl8169_private
*tp
;
3948 struct mii_if_info
*mii
;
3949 struct net_device
*dev
;
3950 void __iomem
*ioaddr
;
3954 if (netif_msg_drv(&debug
)) {
3955 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
3956 MODULENAME
, RTL8169_VERSION
);
3959 dev
= alloc_etherdev(sizeof (*tp
));
3961 if (netif_msg_drv(&debug
))
3962 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
3967 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3968 dev
->netdev_ops
= &rtl8169_netdev_ops
;
3969 tp
= netdev_priv(dev
);
3972 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3976 mii
->mdio_read
= rtl_mdio_read
;
3977 mii
->mdio_write
= rtl_mdio_write
;
3978 mii
->phy_id_mask
= 0x1f;
3979 mii
->reg_num_mask
= 0x1f;
3980 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3982 /* disable ASPM completely as that cause random device stop working
3983 * problems as well as full system hangs for some PCIe devices users */
3984 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
3985 PCIE_LINK_STATE_CLKPM
);
3987 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3988 rc
= pci_enable_device(pdev
);
3990 netif_err(tp
, probe
, dev
, "enable failure\n");
3991 goto err_out_free_dev_1
;
3994 if (pci_set_mwi(pdev
) < 0)
3995 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
3997 /* make sure PCI base addr 1 is MMIO */
3998 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3999 netif_err(tp
, probe
, dev
,
4000 "region #%d not an MMIO resource, aborting\n",
4006 /* check for weird/broken PCI region reporting */
4007 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
4008 netif_err(tp
, probe
, dev
,
4009 "Invalid PCI region size(s), aborting\n");
4014 rc
= pci_request_regions(pdev
, MODULENAME
);
4016 netif_err(tp
, probe
, dev
, "could not request regions\n");
4020 tp
->cp_cmd
= RxChkSum
;
4022 if ((sizeof(dma_addr_t
) > 4) &&
4023 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
4024 tp
->cp_cmd
|= PCIDAC
;
4025 dev
->features
|= NETIF_F_HIGHDMA
;
4027 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
4029 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
4030 goto err_out_free_res_3
;
4034 /* ioremap MMIO region */
4035 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
4037 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
4039 goto err_out_free_res_3
;
4041 tp
->mmio_addr
= ioaddr
;
4043 if (!pci_is_pcie(pdev
))
4044 netif_info(tp
, probe
, dev
, "not PCI Express\n");
4046 /* Identify chip attached to board */
4047 rtl8169_get_mac_version(tp
, dev
, cfg
->default_ver
);
4051 RTL_W16(IntrMask
, 0x0000);
4055 RTL_W16(IntrStatus
, 0xffff);
4057 pci_set_master(pdev
);
4060 * Pretend we are using VLANs; This bypasses a nasty bug where
4061 * Interrupts stop flowing on high load on 8110SCd controllers.
4063 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
4064 tp
->cp_cmd
|= RxVlan
;
4066 rtl_init_mdio_ops(tp
);
4067 rtl_init_pll_power_ops(tp
);
4068 rtl_init_jumbo_ops(tp
);
4070 rtl8169_print_mac_version(tp
);
4072 chipset
= tp
->mac_version
;
4073 tp
->txd_version
= rtl_chip_infos
[chipset
].txd_version
;
4075 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4076 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
4077 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
4078 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
4079 tp
->features
|= RTL_FEATURE_WOL
;
4080 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
4081 tp
->features
|= RTL_FEATURE_WOL
;
4082 tp
->features
|= rtl_try_msi(tp
, cfg
);
4083 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4085 if (rtl_tbi_enabled(tp
)) {
4086 tp
->set_speed
= rtl8169_set_speed_tbi
;
4087 tp
->get_settings
= rtl8169_gset_tbi
;
4088 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
4089 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
4090 tp
->link_ok
= rtl8169_tbi_link_ok
;
4091 tp
->do_ioctl
= rtl_tbi_ioctl
;
4093 tp
->set_speed
= rtl8169_set_speed_xmii
;
4094 tp
->get_settings
= rtl8169_gset_xmii
;
4095 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
4096 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
4097 tp
->link_ok
= rtl8169_xmii_link_ok
;
4098 tp
->do_ioctl
= rtl_xmii_ioctl
;
4101 spin_lock_init(&tp
->lock
);
4103 /* Get MAC address */
4104 for (i
= 0; i
< ETH_ALEN
; i
++)
4105 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
4106 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
4108 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
4109 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
4110 dev
->irq
= pdev
->irq
;
4111 dev
->base_addr
= (unsigned long) ioaddr
;
4113 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
4115 /* don't enable SG, IP_CSUM and TSO by default - it might not work
4116 * properly for all devices */
4117 dev
->features
|= NETIF_F_RXCSUM
|
4118 NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
4120 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
4121 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
4122 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
4125 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
4126 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4127 dev
->hw_features
&= ~NETIF_F_HW_VLAN_RX
;
4129 tp
->intr_mask
= 0xffff;
4130 tp
->hw_start
= cfg
->hw_start
;
4131 tp
->intr_event
= cfg
->intr_event
;
4132 tp
->napi_event
= cfg
->napi_event
;
4134 tp
->opts1_mask
= (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) ?
4135 ~(RxBOVF
| RxFOVF
) : ~0;
4137 init_timer(&tp
->timer
);
4138 tp
->timer
.data
= (unsigned long) dev
;
4139 tp
->timer
.function
= rtl8169_phy_timer
;
4141 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
4143 rc
= register_netdev(dev
);
4147 pci_set_drvdata(pdev
, dev
);
4149 netif_info(tp
, probe
, dev
, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
4150 rtl_chip_infos
[chipset
].name
, dev
->base_addr
, dev
->dev_addr
,
4151 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), dev
->irq
);
4152 if (rtl_chip_infos
[chipset
].jumbo_max
!= JUMBO_1K
) {
4153 netif_info(tp
, probe
, dev
, "jumbo features [frames: %d bytes, "
4154 "tx checksumming: %s]\n",
4155 rtl_chip_infos
[chipset
].jumbo_max
,
4156 rtl_chip_infos
[chipset
].jumbo_tx_csum
? "ok" : "ko");
4159 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4160 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4161 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
4162 rtl8168_driver_start(tp
);
4165 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
4167 if (pci_dev_run_wake(pdev
))
4168 pm_runtime_put_noidle(&pdev
->dev
);
4170 netif_carrier_off(dev
);
4176 rtl_disable_msi(pdev
, tp
);
4179 pci_release_regions(pdev
);
4181 pci_clear_mwi(pdev
);
4182 pci_disable_device(pdev
);
4188 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
4190 struct net_device
*dev
= pci_get_drvdata(pdev
);
4191 struct rtl8169_private
*tp
= netdev_priv(dev
);
4193 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4194 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4195 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
4196 rtl8168_driver_stop(tp
);
4199 cancel_delayed_work_sync(&tp
->task
);
4201 unregister_netdev(dev
);
4203 rtl_release_firmware(tp
);
4205 if (pci_dev_run_wake(pdev
))
4206 pm_runtime_get_noresume(&pdev
->dev
);
4208 /* restore original MAC address */
4209 rtl_rar_set(tp
, dev
->perm_addr
);
4211 rtl_disable_msi(pdev
, tp
);
4212 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
4213 pci_set_drvdata(pdev
, NULL
);
4216 static void rtl_request_uncached_firmware(struct rtl8169_private
*tp
)
4218 struct rtl_fw
*rtl_fw
;
4222 name
= rtl_lookup_firmware_name(tp
);
4224 goto out_no_firmware
;
4226 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
4230 rc
= request_firmware(&rtl_fw
->fw
, name
, &tp
->pci_dev
->dev
);
4234 rc
= rtl_check_firmware(tp
, rtl_fw
);
4236 goto err_release_firmware
;
4238 tp
->rtl_fw
= rtl_fw
;
4242 err_release_firmware
:
4243 release_firmware(rtl_fw
->fw
);
4247 netif_warn(tp
, ifup
, tp
->dev
, "unable to load firmware patch %s (%d)\n",
4254 static void rtl_request_firmware(struct rtl8169_private
*tp
)
4256 if (IS_ERR(tp
->rtl_fw
))
4257 rtl_request_uncached_firmware(tp
);
4260 static int rtl8169_open(struct net_device
*dev
)
4262 struct rtl8169_private
*tp
= netdev_priv(dev
);
4263 void __iomem
*ioaddr
= tp
->mmio_addr
;
4264 struct pci_dev
*pdev
= tp
->pci_dev
;
4265 int retval
= -ENOMEM
;
4267 pm_runtime_get_sync(&pdev
->dev
);
4270 * Rx and Tx desscriptors needs 256 bytes alignment.
4271 * dma_alloc_coherent provides more.
4273 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
4274 &tp
->TxPhyAddr
, GFP_KERNEL
);
4275 if (!tp
->TxDescArray
)
4276 goto err_pm_runtime_put
;
4278 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
4279 &tp
->RxPhyAddr
, GFP_KERNEL
);
4280 if (!tp
->RxDescArray
)
4283 retval
= rtl8169_init_ring(dev
);
4287 INIT_DELAYED_WORK(&tp
->task
, NULL
);
4291 rtl_request_firmware(tp
);
4293 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
4294 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
4297 goto err_release_fw_2
;
4299 napi_enable(&tp
->napi
);
4301 rtl8169_init_phy(dev
, tp
);
4303 rtl8169_set_features(dev
, dev
->features
);
4305 rtl_pll_power_up(tp
);
4309 tp
->saved_wolopts
= 0;
4310 pm_runtime_put_noidle(&pdev
->dev
);
4312 rtl8169_check_link_status(dev
, tp
, ioaddr
);
4317 rtl_release_firmware(tp
);
4318 rtl8169_rx_clear(tp
);
4320 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
4322 tp
->RxDescArray
= NULL
;
4324 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
4326 tp
->TxDescArray
= NULL
;
4328 pm_runtime_put_noidle(&pdev
->dev
);
4332 static void rtl_rx_close(struct rtl8169_private
*tp
)
4334 void __iomem
*ioaddr
= tp
->mmio_addr
;
4336 RTL_W32(RxConfig
, RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
4339 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
4341 void __iomem
*ioaddr
= tp
->mmio_addr
;
4343 /* Disable interrupts */
4344 rtl8169_irq_mask_and_ack(tp
);
4348 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4349 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4350 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
4351 while (RTL_R8(TxPoll
) & NPQ
)
4353 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
4354 tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
4355 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
4356 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
4357 while (!(RTL_R32(TxConfig
) & TXCFG_EMPTY
))
4360 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
4367 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
4369 void __iomem
*ioaddr
= tp
->mmio_addr
;
4371 /* Set DMA burst size and Interframe Gap Time */
4372 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4373 (InterFrameGap
<< TxInterFrameGapShift
));
4376 static void rtl_hw_start(struct net_device
*dev
)
4378 struct rtl8169_private
*tp
= netdev_priv(dev
);
4382 netif_start_queue(dev
);
4385 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
4386 void __iomem
*ioaddr
)
4389 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4390 * register to be written before TxDescAddrLow to work.
4391 * Switching from MMIO to I/O access fixes the issue as well.
4393 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
4394 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
4395 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
4396 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
4399 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
4403 cmd
= RTL_R16(CPlusCmd
);
4404 RTL_W16(CPlusCmd
, cmd
);
4408 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
4410 /* Low hurts. Let's disable the filtering. */
4411 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
4414 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
4416 static const struct rtl_cfg2_info
{
4421 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
4422 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
4423 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
4424 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
4426 const struct rtl_cfg2_info
*p
= cfg2_info
;
4430 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
4431 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
4432 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
4433 RTL_W32(0x7c, p
->val
);
4439 static void rtl_hw_start_8169(struct net_device
*dev
)
4441 struct rtl8169_private
*tp
= netdev_priv(dev
);
4442 void __iomem
*ioaddr
= tp
->mmio_addr
;
4443 struct pci_dev
*pdev
= tp
->pci_dev
;
4445 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
4446 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
4447 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
4450 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4451 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4452 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4453 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4454 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4455 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4459 RTL_W8(EarlyTxThres
, NoEarlyTx
);
4461 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4463 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4464 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4465 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4466 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4467 rtl_set_rx_tx_config_registers(tp
);
4469 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
4471 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4472 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
4473 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4474 "Bit-3 and bit-14 MUST be 1\n");
4475 tp
->cp_cmd
|= (1 << 14);
4478 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4480 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
4483 * Undocumented corner. Supposedly:
4484 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4486 RTL_W16(IntrMitigate
, 0x0000);
4488 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4490 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
&&
4491 tp
->mac_version
!= RTL_GIGA_MAC_VER_02
&&
4492 tp
->mac_version
!= RTL_GIGA_MAC_VER_03
&&
4493 tp
->mac_version
!= RTL_GIGA_MAC_VER_04
) {
4494 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4495 rtl_set_rx_tx_config_registers(tp
);
4498 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4500 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4503 RTL_W32(RxMissed
, 0);
4505 rtl_set_rx_mode(dev
);
4507 /* no early-rx interrupts */
4508 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4510 /* Enable all known interrupts by setting the interrupt mask. */
4511 RTL_W16(IntrMask
, tp
->intr_event
);
4514 static void rtl_csi_access_enable(void __iomem
*ioaddr
, u32 bits
)
4518 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
4519 rtl_csi_write(ioaddr
, 0x070c, csi
| bits
);
4522 static void rtl_csi_access_enable_1(void __iomem
*ioaddr
)
4524 rtl_csi_access_enable(ioaddr
, 0x17000000);
4527 static void rtl_csi_access_enable_2(void __iomem
*ioaddr
)
4529 rtl_csi_access_enable(ioaddr
, 0x27000000);
4533 unsigned int offset
;
4538 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
4543 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
4544 rtl_ephy_write(ioaddr
, e
->offset
, w
);
4549 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
4551 int cap
= pci_pcie_cap(pdev
);
4556 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4557 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
4558 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4562 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
4564 int cap
= pci_pcie_cap(pdev
);
4569 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4570 ctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
4571 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4575 #define R8168_CPCMD_QUIRK_MASK (\
4586 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4588 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4590 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4592 rtl_tx_performance_tweak(pdev
,
4593 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
4596 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4598 rtl_hw_start_8168bb(ioaddr
, pdev
);
4600 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4602 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
4605 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4607 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
4609 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4611 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4613 rtl_disable_clock_request(pdev
);
4615 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4618 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4620 static const struct ephy_info e_info_8168cp
[] = {
4621 { 0x01, 0, 0x0001 },
4622 { 0x02, 0x0800, 0x1000 },
4623 { 0x03, 0, 0x0042 },
4624 { 0x06, 0x0080, 0x0000 },
4628 rtl_csi_access_enable_2(ioaddr
);
4630 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
4632 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4635 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4637 rtl_csi_access_enable_2(ioaddr
);
4639 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4641 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4643 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4646 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4648 rtl_csi_access_enable_2(ioaddr
);
4650 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4653 RTL_W8(DBG_REG
, 0x20);
4655 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4657 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4659 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4662 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4664 static const struct ephy_info e_info_8168c_1
[] = {
4665 { 0x02, 0x0800, 0x1000 },
4666 { 0x03, 0, 0x0002 },
4667 { 0x06, 0x0080, 0x0000 }
4670 rtl_csi_access_enable_2(ioaddr
);
4672 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
4674 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
4676 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4679 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4681 static const struct ephy_info e_info_8168c_2
[] = {
4682 { 0x01, 0, 0x0001 },
4683 { 0x03, 0x0400, 0x0220 }
4686 rtl_csi_access_enable_2(ioaddr
);
4688 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
4690 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4693 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4695 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4698 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4700 rtl_csi_access_enable_2(ioaddr
);
4702 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4705 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4707 rtl_csi_access_enable_2(ioaddr
);
4709 rtl_disable_clock_request(pdev
);
4711 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4713 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4715 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4718 static void rtl_hw_start_8168dp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4720 rtl_csi_access_enable_1(ioaddr
);
4722 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4724 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4726 rtl_disable_clock_request(pdev
);
4729 static void rtl_hw_start_8168d_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4731 static const struct ephy_info e_info_8168d_4
[] = {
4733 { 0x19, 0x20, 0x50 },
4738 rtl_csi_access_enable_1(ioaddr
);
4740 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4742 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4744 for (i
= 0; i
< ARRAY_SIZE(e_info_8168d_4
); i
++) {
4745 const struct ephy_info
*e
= e_info_8168d_4
+ i
;
4748 w
= rtl_ephy_read(ioaddr
, e
->offset
);
4749 rtl_ephy_write(ioaddr
, 0x03, (w
& e
->mask
) | e
->bits
);
4752 rtl_enable_clock_request(pdev
);
4755 static void rtl_hw_start_8168e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4757 static const struct ephy_info e_info_8168e_1
[] = {
4758 { 0x00, 0x0200, 0x0100 },
4759 { 0x00, 0x0000, 0x0004 },
4760 { 0x06, 0x0002, 0x0001 },
4761 { 0x06, 0x0000, 0x0030 },
4762 { 0x07, 0x0000, 0x2000 },
4763 { 0x00, 0x0000, 0x0020 },
4764 { 0x03, 0x5800, 0x2000 },
4765 { 0x03, 0x0000, 0x0001 },
4766 { 0x01, 0x0800, 0x1000 },
4767 { 0x07, 0x0000, 0x4000 },
4768 { 0x1e, 0x0000, 0x2000 },
4769 { 0x19, 0xffff, 0xfe6c },
4770 { 0x0a, 0x0000, 0x0040 }
4773 rtl_csi_access_enable_2(ioaddr
);
4775 rtl_ephy_init(ioaddr
, e_info_8168e_1
, ARRAY_SIZE(e_info_8168e_1
));
4777 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4779 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4781 rtl_disable_clock_request(pdev
);
4783 /* Reset tx FIFO pointer */
4784 RTL_W32(MISC
, RTL_R32(MISC
) | TXPLA_RST
);
4785 RTL_W32(MISC
, RTL_R32(MISC
) & ~TXPLA_RST
);
4787 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4790 static void rtl_hw_start_8168e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4792 static const struct ephy_info e_info_8168e_2
[] = {
4793 { 0x09, 0x0000, 0x0080 },
4794 { 0x19, 0x0000, 0x0224 }
4797 rtl_csi_access_enable_1(ioaddr
);
4799 rtl_ephy_init(ioaddr
, e_info_8168e_2
, ARRAY_SIZE(e_info_8168e_2
));
4801 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4803 rtl_eri_write(ioaddr
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4804 rtl_eri_write(ioaddr
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4805 rtl_eri_write(ioaddr
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
4806 rtl_eri_write(ioaddr
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
4807 rtl_eri_write(ioaddr
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
4808 rtl_eri_write(ioaddr
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060, ERIAR_EXGMAC
);
4809 rtl_w1w0_eri(ioaddr
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4810 rtl_w1w0_eri(ioaddr
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00,
4813 RTL_W8(MaxTxPacketSize
, EarlySize
);
4815 rtl_disable_clock_request(pdev
);
4817 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
4818 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
4820 /* Adjust EEE LED frequency */
4821 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
4823 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4824 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
4825 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4828 static void rtl_hw_start_8168f_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4830 static const struct ephy_info e_info_8168f_1
[] = {
4831 { 0x06, 0x00c0, 0x0020 },
4832 { 0x08, 0x0001, 0x0002 },
4833 { 0x09, 0x0000, 0x0080 },
4834 { 0x19, 0x0000, 0x0224 }
4837 rtl_csi_access_enable_1(ioaddr
);
4839 rtl_ephy_init(ioaddr
, e_info_8168f_1
, ARRAY_SIZE(e_info_8168f_1
));
4841 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4843 rtl_eri_write(ioaddr
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4844 rtl_eri_write(ioaddr
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4845 rtl_eri_write(ioaddr
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
4846 rtl_eri_write(ioaddr
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
4847 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
4848 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
4849 rtl_w1w0_eri(ioaddr
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4850 rtl_w1w0_eri(ioaddr
, 0x1d0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4851 rtl_eri_write(ioaddr
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
4852 rtl_eri_write(ioaddr
, 0xd0, ERIAR_MASK_1111
, 0x00000060, ERIAR_EXGMAC
);
4853 rtl_w1w0_eri(ioaddr
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00,
4856 RTL_W8(MaxTxPacketSize
, EarlySize
);
4858 rtl_disable_clock_request(pdev
);
4860 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
4861 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
4863 /* Adjust EEE LED frequency */
4864 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
4866 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4867 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
4868 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4871 static void rtl_hw_start_8168(struct net_device
*dev
)
4873 struct rtl8169_private
*tp
= netdev_priv(dev
);
4874 void __iomem
*ioaddr
= tp
->mmio_addr
;
4875 struct pci_dev
*pdev
= tp
->pci_dev
;
4877 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4879 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4881 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4883 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
4885 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4887 RTL_W16(IntrMitigate
, 0x5151);
4889 /* Work around for RxFIFO overflow. */
4890 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
4891 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
4892 tp
->intr_event
&= ~RxOverflow
;
4895 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4897 rtl_set_rx_mode(dev
);
4899 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4900 (InterFrameGap
<< TxInterFrameGapShift
));
4904 switch (tp
->mac_version
) {
4905 case RTL_GIGA_MAC_VER_11
:
4906 rtl_hw_start_8168bb(ioaddr
, pdev
);
4909 case RTL_GIGA_MAC_VER_12
:
4910 case RTL_GIGA_MAC_VER_17
:
4911 rtl_hw_start_8168bef(ioaddr
, pdev
);
4914 case RTL_GIGA_MAC_VER_18
:
4915 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
4918 case RTL_GIGA_MAC_VER_19
:
4919 rtl_hw_start_8168c_1(ioaddr
, pdev
);
4922 case RTL_GIGA_MAC_VER_20
:
4923 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4926 case RTL_GIGA_MAC_VER_21
:
4927 rtl_hw_start_8168c_3(ioaddr
, pdev
);
4930 case RTL_GIGA_MAC_VER_22
:
4931 rtl_hw_start_8168c_4(ioaddr
, pdev
);
4934 case RTL_GIGA_MAC_VER_23
:
4935 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
4938 case RTL_GIGA_MAC_VER_24
:
4939 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
4942 case RTL_GIGA_MAC_VER_25
:
4943 case RTL_GIGA_MAC_VER_26
:
4944 case RTL_GIGA_MAC_VER_27
:
4945 rtl_hw_start_8168d(ioaddr
, pdev
);
4948 case RTL_GIGA_MAC_VER_28
:
4949 rtl_hw_start_8168d_4(ioaddr
, pdev
);
4952 case RTL_GIGA_MAC_VER_31
:
4953 rtl_hw_start_8168dp(ioaddr
, pdev
);
4956 case RTL_GIGA_MAC_VER_32
:
4957 case RTL_GIGA_MAC_VER_33
:
4958 rtl_hw_start_8168e_1(ioaddr
, pdev
);
4960 case RTL_GIGA_MAC_VER_34
:
4961 rtl_hw_start_8168e_2(ioaddr
, pdev
);
4964 case RTL_GIGA_MAC_VER_35
:
4965 case RTL_GIGA_MAC_VER_36
:
4966 rtl_hw_start_8168f_1(ioaddr
, pdev
);
4970 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
4971 dev
->name
, tp
->mac_version
);
4975 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4977 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4979 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4981 RTL_W16(IntrMask
, tp
->intr_event
);
4984 #define R810X_CPCMD_QUIRK_MASK (\
4995 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4997 static const struct ephy_info e_info_8102e_1
[] = {
4998 { 0x01, 0, 0x6e65 },
4999 { 0x02, 0, 0x091f },
5000 { 0x03, 0, 0xc2f9 },
5001 { 0x06, 0, 0xafb5 },
5002 { 0x07, 0, 0x0e00 },
5003 { 0x19, 0, 0xec80 },
5004 { 0x01, 0, 0x2e65 },
5009 rtl_csi_access_enable_2(ioaddr
);
5011 RTL_W8(DBG_REG
, FIX_NAK_1
);
5013 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5016 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
5017 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5019 cfg1
= RTL_R8(Config1
);
5020 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
5021 RTL_W8(Config1
, cfg1
& ~LEDS0
);
5023 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
5026 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
5028 rtl_csi_access_enable_2(ioaddr
);
5030 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5032 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
5033 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5036 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
5038 rtl_hw_start_8102e_2(ioaddr
, pdev
);
5040 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
5043 static void rtl_hw_start_8105e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
5045 static const struct ephy_info e_info_8105e_1
[] = {
5046 { 0x07, 0, 0x4000 },
5047 { 0x19, 0, 0x0200 },
5048 { 0x19, 0, 0x0020 },
5049 { 0x1e, 0, 0x2000 },
5050 { 0x03, 0, 0x0001 },
5051 { 0x19, 0, 0x0100 },
5052 { 0x19, 0, 0x0004 },
5056 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5057 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
5059 /* Disable Early Tally Counter */
5060 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
5062 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
5063 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
5065 rtl_ephy_init(ioaddr
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
5068 static void rtl_hw_start_8105e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
5070 rtl_hw_start_8105e_1(ioaddr
, pdev
);
5071 rtl_ephy_write(ioaddr
, 0x1e, rtl_ephy_read(ioaddr
, 0x1e) | 0x8000);
5074 static void rtl_hw_start_8101(struct net_device
*dev
)
5076 struct rtl8169_private
*tp
= netdev_priv(dev
);
5077 void __iomem
*ioaddr
= tp
->mmio_addr
;
5078 struct pci_dev
*pdev
= tp
->pci_dev
;
5080 if (tp
->mac_version
>= RTL_GIGA_MAC_VER_30
) {
5081 tp
->intr_event
&= ~RxFIFOOver
;
5082 tp
->napi_event
&= ~RxFIFOOver
;
5085 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
5086 tp
->mac_version
== RTL_GIGA_MAC_VER_16
) {
5087 int cap
= pci_pcie_cap(pdev
);
5090 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
5091 PCI_EXP_DEVCTL_NOSNOOP_EN
);
5095 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
5097 switch (tp
->mac_version
) {
5098 case RTL_GIGA_MAC_VER_07
:
5099 rtl_hw_start_8102e_1(ioaddr
, pdev
);
5102 case RTL_GIGA_MAC_VER_08
:
5103 rtl_hw_start_8102e_3(ioaddr
, pdev
);
5106 case RTL_GIGA_MAC_VER_09
:
5107 rtl_hw_start_8102e_2(ioaddr
, pdev
);
5110 case RTL_GIGA_MAC_VER_29
:
5111 rtl_hw_start_8105e_1(ioaddr
, pdev
);
5113 case RTL_GIGA_MAC_VER_30
:
5114 rtl_hw_start_8105e_2(ioaddr
, pdev
);
5118 RTL_W8(Cfg9346
, Cfg9346_Lock
);
5120 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5122 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
5124 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
5125 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5127 RTL_W16(IntrMitigate
, 0x0000);
5129 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
5131 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5132 rtl_set_rx_tx_config_registers(tp
);
5136 rtl_set_rx_mode(dev
);
5138 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
5140 RTL_W16(IntrMask
, tp
->intr_event
);
5143 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
5145 struct rtl8169_private
*tp
= netdev_priv(dev
);
5147 if (new_mtu
< ETH_ZLEN
||
5148 new_mtu
> rtl_chip_infos
[tp
->mac_version
].jumbo_max
)
5151 if (new_mtu
> ETH_DATA_LEN
)
5152 rtl_hw_jumbo_enable(tp
);
5154 rtl_hw_jumbo_disable(tp
);
5157 netdev_update_features(dev
);
5162 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
5164 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
5165 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
5168 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
5169 void **data_buff
, struct RxDesc
*desc
)
5171 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
5176 rtl8169_make_unusable_by_asic(desc
);
5179 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
5181 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
5183 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
5186 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
5189 desc
->addr
= cpu_to_le64(mapping
);
5191 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5194 static inline void *rtl8169_align(void *data
)
5196 return (void *)ALIGN((long)data
, 16);
5199 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
5200 struct RxDesc
*desc
)
5204 struct device
*d
= &tp
->pci_dev
->dev
;
5205 struct net_device
*dev
= tp
->dev
;
5206 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
5208 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
5212 if (rtl8169_align(data
) != data
) {
5214 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
5219 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
5221 if (unlikely(dma_mapping_error(d
, mapping
))) {
5222 if (net_ratelimit())
5223 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
5227 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
5235 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
5239 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
5240 if (tp
->Rx_databuff
[i
]) {
5241 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
5242 tp
->RxDescArray
+ i
);
5247 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
5249 desc
->opts1
|= cpu_to_le32(RingEnd
);
5252 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
5256 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
5259 if (tp
->Rx_databuff
[i
])
5262 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
5264 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
5267 tp
->Rx_databuff
[i
] = data
;
5270 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
5274 rtl8169_rx_clear(tp
);
5278 static int rtl8169_init_ring(struct net_device
*dev
)
5280 struct rtl8169_private
*tp
= netdev_priv(dev
);
5282 rtl8169_init_ring_indexes(tp
);
5284 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
5285 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
5287 return rtl8169_rx_fill(tp
);
5290 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
5291 struct TxDesc
*desc
)
5293 unsigned int len
= tx_skb
->len
;
5295 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
5303 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
5308 for (i
= 0; i
< n
; i
++) {
5309 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
5310 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5311 unsigned int len
= tx_skb
->len
;
5314 struct sk_buff
*skb
= tx_skb
->skb
;
5316 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
5317 tp
->TxDescArray
+ entry
);
5319 tp
->dev
->stats
.tx_dropped
++;
5327 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
5329 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
5330 tp
->cur_tx
= tp
->dirty_tx
= 0;
5333 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
5335 struct rtl8169_private
*tp
= netdev_priv(dev
);
5337 PREPARE_DELAYED_WORK(&tp
->task
, task
);
5338 schedule_delayed_work(&tp
->task
, 4);
5341 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
5343 struct rtl8169_private
*tp
= netdev_priv(dev
);
5344 void __iomem
*ioaddr
= tp
->mmio_addr
;
5346 synchronize_irq(dev
->irq
);
5348 /* Wait for any pending NAPI task to complete */
5349 napi_disable(&tp
->napi
);
5351 rtl8169_irq_mask_and_ack(tp
);
5353 tp
->intr_mask
= 0xffff;
5354 RTL_W16(IntrMask
, tp
->intr_event
);
5355 napi_enable(&tp
->napi
);
5358 static void rtl8169_reinit_task(struct work_struct
*work
)
5360 struct rtl8169_private
*tp
=
5361 container_of(work
, struct rtl8169_private
, task
.work
);
5362 struct net_device
*dev
= tp
->dev
;
5367 if (!netif_running(dev
))
5370 rtl8169_wait_for_quiescence(dev
);
5373 ret
= rtl8169_open(dev
);
5374 if (unlikely(ret
< 0)) {
5375 if (net_ratelimit())
5376 netif_err(tp
, drv
, dev
,
5377 "reinit failure (status = %d). Rescheduling\n",
5379 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
5386 static void rtl8169_reset_task(struct work_struct
*work
)
5388 struct rtl8169_private
*tp
=
5389 container_of(work
, struct rtl8169_private
, task
.work
);
5390 struct net_device
*dev
= tp
->dev
;
5395 if (!netif_running(dev
))
5398 rtl8169_hw_reset(tp
);
5400 rtl8169_wait_for_quiescence(dev
);
5402 for (i
= 0; i
< NUM_RX_DESC
; i
++)
5403 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
, rx_buf_sz
);
5405 rtl8169_tx_clear(tp
);
5406 rtl8169_init_ring_indexes(tp
);
5409 netif_wake_queue(dev
);
5410 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
5416 static void rtl8169_tx_timeout(struct net_device
*dev
)
5418 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5421 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
5424 struct skb_shared_info
*info
= skb_shinfo(skb
);
5425 unsigned int cur_frag
, entry
;
5426 struct TxDesc
* uninitialized_var(txd
);
5427 struct device
*d
= &tp
->pci_dev
->dev
;
5430 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
5431 const skb_frag_t
*frag
= info
->frags
+ cur_frag
;
5436 entry
= (entry
+ 1) % NUM_TX_DESC
;
5438 txd
= tp
->TxDescArray
+ entry
;
5439 len
= skb_frag_size(frag
);
5440 addr
= skb_frag_address(frag
);
5441 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
5442 if (unlikely(dma_mapping_error(d
, mapping
))) {
5443 if (net_ratelimit())
5444 netif_err(tp
, drv
, tp
->dev
,
5445 "Failed to map TX fragments DMA!\n");
5449 /* Anti gcc 2.95.3 bugware (sic) */
5450 status
= opts
[0] | len
|
5451 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5453 txd
->opts1
= cpu_to_le32(status
);
5454 txd
->opts2
= cpu_to_le32(opts
[1]);
5455 txd
->addr
= cpu_to_le64(mapping
);
5457 tp
->tx_skb
[entry
].len
= len
;
5461 tp
->tx_skb
[entry
].skb
= skb
;
5462 txd
->opts1
|= cpu_to_le32(LastFrag
);
5468 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
5472 static inline void rtl8169_tso_csum(struct rtl8169_private
*tp
,
5473 struct sk_buff
*skb
, u32
*opts
)
5475 const struct rtl_tx_desc_info
*info
= tx_desc_info
+ tp
->txd_version
;
5476 u32 mss
= skb_shinfo(skb
)->gso_size
;
5477 int offset
= info
->opts_offset
;
5481 opts
[offset
] |= min(mss
, TD_MSS_MAX
) << info
->mss_shift
;
5482 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5483 const struct iphdr
*ip
= ip_hdr(skb
);
5485 if (ip
->protocol
== IPPROTO_TCP
)
5486 opts
[offset
] |= info
->checksum
.tcp
;
5487 else if (ip
->protocol
== IPPROTO_UDP
)
5488 opts
[offset
] |= info
->checksum
.udp
;
5494 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
5495 struct net_device
*dev
)
5497 struct rtl8169_private
*tp
= netdev_priv(dev
);
5498 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
5499 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
5500 void __iomem
*ioaddr
= tp
->mmio_addr
;
5501 struct device
*d
= &tp
->pci_dev
->dev
;
5507 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
5508 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
5512 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
5515 len
= skb_headlen(skb
);
5516 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
5517 if (unlikely(dma_mapping_error(d
, mapping
))) {
5518 if (net_ratelimit())
5519 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
5523 tp
->tx_skb
[entry
].len
= len
;
5524 txd
->addr
= cpu_to_le64(mapping
);
5526 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
5529 rtl8169_tso_csum(tp
, skb
, opts
);
5531 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
5535 opts
[0] |= FirstFrag
;
5537 opts
[0] |= FirstFrag
| LastFrag
;
5538 tp
->tx_skb
[entry
].skb
= skb
;
5541 txd
->opts2
= cpu_to_le32(opts
[1]);
5545 /* Anti gcc 2.95.3 bugware (sic) */
5546 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5547 txd
->opts1
= cpu_to_le32(status
);
5549 tp
->cur_tx
+= frags
+ 1;
5553 RTL_W8(TxPoll
, NPQ
);
5555 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
5556 netif_stop_queue(dev
);
5558 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
5559 netif_wake_queue(dev
);
5562 return NETDEV_TX_OK
;
5565 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
5568 dev
->stats
.tx_dropped
++;
5569 return NETDEV_TX_OK
;
5572 netif_stop_queue(dev
);
5573 dev
->stats
.tx_dropped
++;
5574 return NETDEV_TX_BUSY
;
5577 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
5579 struct rtl8169_private
*tp
= netdev_priv(dev
);
5580 struct pci_dev
*pdev
= tp
->pci_dev
;
5581 u16 pci_status
, pci_cmd
;
5583 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
5584 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
5586 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5587 pci_cmd
, pci_status
);
5590 * The recovery sequence below admits a very elaborated explanation:
5591 * - it seems to work;
5592 * - I did not see what else could be done;
5593 * - it makes iop3xx happy.
5595 * Feel free to adjust to your needs.
5597 if (pdev
->broken_parity_status
)
5598 pci_cmd
&= ~PCI_COMMAND_PARITY
;
5600 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
5602 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
5604 pci_write_config_word(pdev
, PCI_STATUS
,
5605 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
5606 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
5607 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
5609 /* The infamous DAC f*ckup only happens at boot time */
5610 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
5611 void __iomem
*ioaddr
= tp
->mmio_addr
;
5613 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
5614 tp
->cp_cmd
&= ~PCIDAC
;
5615 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5616 dev
->features
&= ~NETIF_F_HIGHDMA
;
5619 rtl8169_hw_reset(tp
);
5621 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
5624 static void rtl8169_tx_interrupt(struct net_device
*dev
,
5625 struct rtl8169_private
*tp
,
5626 void __iomem
*ioaddr
)
5628 unsigned int dirty_tx
, tx_left
;
5630 dirty_tx
= tp
->dirty_tx
;
5632 tx_left
= tp
->cur_tx
- dirty_tx
;
5634 while (tx_left
> 0) {
5635 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
5636 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5640 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
5641 if (status
& DescOwn
)
5644 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
5645 tp
->TxDescArray
+ entry
);
5646 if (status
& LastFrag
) {
5647 dev
->stats
.tx_packets
++;
5648 dev
->stats
.tx_bytes
+= tx_skb
->skb
->len
;
5649 dev_kfree_skb(tx_skb
->skb
);
5656 if (tp
->dirty_tx
!= dirty_tx
) {
5657 tp
->dirty_tx
= dirty_tx
;
5659 if (netif_queue_stopped(dev
) &&
5660 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
5661 netif_wake_queue(dev
);
5664 * 8168 hack: TxPoll requests are lost when the Tx packets are
5665 * too close. Let's kick an extra TxPoll request when a burst
5666 * of start_xmit activity is detected (if it is not detected,
5667 * it is slow enough). -- FR
5670 if (tp
->cur_tx
!= dirty_tx
)
5671 RTL_W8(TxPoll
, NPQ
);
5675 static inline int rtl8169_fragmented_frame(u32 status
)
5677 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
5680 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
5682 u32 status
= opts1
& RxProtoMask
;
5684 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
5685 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
5686 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
5688 skb_checksum_none_assert(skb
);
5691 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
5692 struct rtl8169_private
*tp
,
5696 struct sk_buff
*skb
;
5697 struct device
*d
= &tp
->pci_dev
->dev
;
5699 data
= rtl8169_align(data
);
5700 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5702 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
5704 memcpy(skb
->data
, data
, pkt_size
);
5705 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5710 static int rtl8169_rx_interrupt(struct net_device
*dev
,
5711 struct rtl8169_private
*tp
,
5712 void __iomem
*ioaddr
, u32 budget
)
5714 unsigned int cur_rx
, rx_left
;
5717 cur_rx
= tp
->cur_rx
;
5718 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
5719 rx_left
= min(rx_left
, budget
);
5721 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
5722 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
5723 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
5727 status
= le32_to_cpu(desc
->opts1
) & tp
->opts1_mask
;
5729 if (status
& DescOwn
)
5731 if (unlikely(status
& RxRES
)) {
5732 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
5734 dev
->stats
.rx_errors
++;
5735 if (status
& (RxRWT
| RxRUNT
))
5736 dev
->stats
.rx_length_errors
++;
5738 dev
->stats
.rx_crc_errors
++;
5739 if (status
& RxFOVF
) {
5740 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5741 dev
->stats
.rx_fifo_errors
++;
5743 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5745 struct sk_buff
*skb
;
5746 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
5747 int pkt_size
= (status
& 0x00003fff) - 4;
5750 * The driver does not support incoming fragmented
5751 * frames. They are seen as a symptom of over-mtu
5754 if (unlikely(rtl8169_fragmented_frame(status
))) {
5755 dev
->stats
.rx_dropped
++;
5756 dev
->stats
.rx_length_errors
++;
5757 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5761 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
5762 tp
, pkt_size
, addr
);
5763 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5765 dev
->stats
.rx_dropped
++;
5769 rtl8169_rx_csum(skb
, status
);
5770 skb_put(skb
, pkt_size
);
5771 skb
->protocol
= eth_type_trans(skb
, dev
);
5773 rtl8169_rx_vlan_tag(desc
, skb
);
5775 napi_gro_receive(&tp
->napi
, skb
);
5777 dev
->stats
.rx_bytes
+= pkt_size
;
5778 dev
->stats
.rx_packets
++;
5781 /* Work around for AMD plateform. */
5782 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
5783 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
5789 count
= cur_rx
- tp
->cur_rx
;
5790 tp
->cur_rx
= cur_rx
;
5792 tp
->dirty_rx
+= count
;
5797 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
5799 struct net_device
*dev
= dev_instance
;
5800 struct rtl8169_private
*tp
= netdev_priv(dev
);
5801 void __iomem
*ioaddr
= tp
->mmio_addr
;
5805 /* loop handling interrupts until we have no new ones or
5806 * we hit a invalid/hotplug case.
5808 status
= RTL_R16(IntrStatus
);
5809 while (status
&& status
!= 0xffff) {
5810 status
&= tp
->intr_event
;
5816 /* Handle all of the error cases first. These will reset
5817 * the chip, so just exit the loop.
5819 if (unlikely(!netif_running(dev
))) {
5820 rtl8169_hw_reset(tp
);
5824 if (unlikely(status
& RxFIFOOver
)) {
5825 switch (tp
->mac_version
) {
5826 /* Work around for rx fifo overflow */
5827 case RTL_GIGA_MAC_VER_11
:
5828 netif_stop_queue(dev
);
5829 rtl8169_tx_timeout(dev
);
5836 if (unlikely(status
& SYSErr
)) {
5837 rtl8169_pcierr_interrupt(dev
);
5841 if (status
& LinkChg
)
5842 __rtl8169_check_link_status(dev
, tp
, ioaddr
, true);
5844 /* We need to see the lastest version of tp->intr_mask to
5845 * avoid ignoring an MSI interrupt and having to wait for
5846 * another event which may never come.
5849 if (status
& tp
->intr_mask
& tp
->napi_event
) {
5850 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
5851 tp
->intr_mask
= ~tp
->napi_event
;
5853 if (likely(napi_schedule_prep(&tp
->napi
)))
5854 __napi_schedule(&tp
->napi
);
5856 netif_info(tp
, intr
, dev
,
5857 "interrupt %04x in poll\n", status
);
5860 /* We only get a new MSI interrupt when all active irq
5861 * sources on the chip have been acknowledged. So, ack
5862 * everything we've seen and check if new sources have become
5863 * active to avoid blocking all interrupts from the chip.
5866 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
5867 status
= RTL_R16(IntrStatus
);
5870 return IRQ_RETVAL(handled
);
5873 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
5875 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
5876 struct net_device
*dev
= tp
->dev
;
5877 void __iomem
*ioaddr
= tp
->mmio_addr
;
5880 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
5881 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
5883 if (work_done
< budget
) {
5884 napi_complete(napi
);
5886 /* We need for force the visibility of tp->intr_mask
5887 * for other CPUs, as we can loose an MSI interrupt
5888 * and potentially wait for a retransmit timeout if we don't.
5889 * The posted write to IntrMask is safe, as it will
5890 * eventually make it to the chip and we won't loose anything
5893 tp
->intr_mask
= 0xffff;
5895 RTL_W16(IntrMask
, tp
->intr_event
);
5901 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
5903 struct rtl8169_private
*tp
= netdev_priv(dev
);
5905 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
5908 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
5909 RTL_W32(RxMissed
, 0);
5912 static void rtl8169_down(struct net_device
*dev
)
5914 struct rtl8169_private
*tp
= netdev_priv(dev
);
5915 void __iomem
*ioaddr
= tp
->mmio_addr
;
5917 del_timer_sync(&tp
->timer
);
5919 netif_stop_queue(dev
);
5921 napi_disable(&tp
->napi
);
5923 spin_lock_irq(&tp
->lock
);
5925 rtl8169_hw_reset(tp
);
5927 * At this point device interrupts can not be enabled in any function,
5928 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5929 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5931 rtl8169_rx_missed(dev
, ioaddr
);
5933 spin_unlock_irq(&tp
->lock
);
5935 synchronize_irq(dev
->irq
);
5937 /* Give a racing hard_start_xmit a few cycles to complete. */
5938 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5940 rtl8169_tx_clear(tp
);
5942 rtl8169_rx_clear(tp
);
5944 rtl_pll_power_down(tp
);
5947 static int rtl8169_close(struct net_device
*dev
)
5949 struct rtl8169_private
*tp
= netdev_priv(dev
);
5950 struct pci_dev
*pdev
= tp
->pci_dev
;
5952 pm_runtime_get_sync(&pdev
->dev
);
5954 /* Update counters before going down */
5955 rtl8169_update_counters(dev
);
5959 free_irq(dev
->irq
, dev
);
5961 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
5963 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
5965 tp
->TxDescArray
= NULL
;
5966 tp
->RxDescArray
= NULL
;
5968 pm_runtime_put_sync(&pdev
->dev
);
5973 static void rtl_set_rx_mode(struct net_device
*dev
)
5975 struct rtl8169_private
*tp
= netdev_priv(dev
);
5976 void __iomem
*ioaddr
= tp
->mmio_addr
;
5977 unsigned long flags
;
5978 u32 mc_filter
[2]; /* Multicast hash filter */
5982 if (dev
->flags
& IFF_PROMISC
) {
5983 /* Unconditionally log net taps. */
5984 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
5986 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
5988 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5989 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
5990 (dev
->flags
& IFF_ALLMULTI
)) {
5991 /* Too many to filter perfectly -- accept all multicasts. */
5992 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
5993 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5995 struct netdev_hw_addr
*ha
;
5997 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
5998 mc_filter
[1] = mc_filter
[0] = 0;
5999 netdev_for_each_mc_addr(ha
, dev
) {
6000 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
6001 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
6002 rx_mode
|= AcceptMulticast
;
6006 spin_lock_irqsave(&tp
->lock
, flags
);
6008 tmp
= (RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
) | rx_mode
;
6010 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
6011 u32 data
= mc_filter
[0];
6013 mc_filter
[0] = swab32(mc_filter
[1]);
6014 mc_filter
[1] = swab32(data
);
6017 RTL_W32(MAR0
+ 4, mc_filter
[1]);
6018 RTL_W32(MAR0
+ 0, mc_filter
[0]);
6020 RTL_W32(RxConfig
, tmp
);
6022 spin_unlock_irqrestore(&tp
->lock
, flags
);
6026 * rtl8169_get_stats - Get rtl8169 read/write statistics
6027 * @dev: The Ethernet Device to get statistics for
6029 * Get TX/RX statistics for rtl8169
6031 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
6033 struct rtl8169_private
*tp
= netdev_priv(dev
);
6034 void __iomem
*ioaddr
= tp
->mmio_addr
;
6035 unsigned long flags
;
6037 if (netif_running(dev
)) {
6038 spin_lock_irqsave(&tp
->lock
, flags
);
6039 rtl8169_rx_missed(dev
, ioaddr
);
6040 spin_unlock_irqrestore(&tp
->lock
, flags
);
6046 static void rtl8169_net_suspend(struct net_device
*dev
)
6048 struct rtl8169_private
*tp
= netdev_priv(dev
);
6050 if (!netif_running(dev
))
6053 rtl_pll_power_down(tp
);
6055 netif_device_detach(dev
);
6056 netif_stop_queue(dev
);
6061 static int rtl8169_suspend(struct device
*device
)
6063 struct pci_dev
*pdev
= to_pci_dev(device
);
6064 struct net_device
*dev
= pci_get_drvdata(pdev
);
6066 rtl8169_net_suspend(dev
);
6071 static void __rtl8169_resume(struct net_device
*dev
)
6073 struct rtl8169_private
*tp
= netdev_priv(dev
);
6075 netif_device_attach(dev
);
6077 rtl_pll_power_up(tp
);
6079 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
6082 static int rtl8169_resume(struct device
*device
)
6084 struct pci_dev
*pdev
= to_pci_dev(device
);
6085 struct net_device
*dev
= pci_get_drvdata(pdev
);
6086 struct rtl8169_private
*tp
= netdev_priv(dev
);
6088 rtl8169_init_phy(dev
, tp
);
6090 if (netif_running(dev
))
6091 __rtl8169_resume(dev
);
6096 static int rtl8169_runtime_suspend(struct device
*device
)
6098 struct pci_dev
*pdev
= to_pci_dev(device
);
6099 struct net_device
*dev
= pci_get_drvdata(pdev
);
6100 struct rtl8169_private
*tp
= netdev_priv(dev
);
6102 if (!tp
->TxDescArray
)
6105 spin_lock_irq(&tp
->lock
);
6106 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
6107 __rtl8169_set_wol(tp
, WAKE_ANY
);
6108 spin_unlock_irq(&tp
->lock
);
6110 rtl8169_net_suspend(dev
);
6115 static int rtl8169_runtime_resume(struct device
*device
)
6117 struct pci_dev
*pdev
= to_pci_dev(device
);
6118 struct net_device
*dev
= pci_get_drvdata(pdev
);
6119 struct rtl8169_private
*tp
= netdev_priv(dev
);
6121 if (!tp
->TxDescArray
)
6124 spin_lock_irq(&tp
->lock
);
6125 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
6126 tp
->saved_wolopts
= 0;
6127 spin_unlock_irq(&tp
->lock
);
6129 rtl8169_init_phy(dev
, tp
);
6131 __rtl8169_resume(dev
);
6136 static int rtl8169_runtime_idle(struct device
*device
)
6138 struct pci_dev
*pdev
= to_pci_dev(device
);
6139 struct net_device
*dev
= pci_get_drvdata(pdev
);
6140 struct rtl8169_private
*tp
= netdev_priv(dev
);
6142 return tp
->TxDescArray
? -EBUSY
: 0;
6145 static const struct dev_pm_ops rtl8169_pm_ops
= {
6146 .suspend
= rtl8169_suspend
,
6147 .resume
= rtl8169_resume
,
6148 .freeze
= rtl8169_suspend
,
6149 .thaw
= rtl8169_resume
,
6150 .poweroff
= rtl8169_suspend
,
6151 .restore
= rtl8169_resume
,
6152 .runtime_suspend
= rtl8169_runtime_suspend
,
6153 .runtime_resume
= rtl8169_runtime_resume
,
6154 .runtime_idle
= rtl8169_runtime_idle
,
6157 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6159 #else /* !CONFIG_PM */
6161 #define RTL8169_PM_OPS NULL
6163 #endif /* !CONFIG_PM */
6165 static void rtl_wol_shutdown_quirk(struct rtl8169_private
*tp
)
6167 void __iomem
*ioaddr
= tp
->mmio_addr
;
6169 /* WoL fails with 8168b when the receiver is disabled. */
6170 switch (tp
->mac_version
) {
6171 case RTL_GIGA_MAC_VER_11
:
6172 case RTL_GIGA_MAC_VER_12
:
6173 case RTL_GIGA_MAC_VER_17
:
6174 pci_clear_master(tp
->pci_dev
);
6176 RTL_W8(ChipCmd
, CmdRxEnb
);
6185 static void rtl_shutdown(struct pci_dev
*pdev
)
6187 struct net_device
*dev
= pci_get_drvdata(pdev
);
6188 struct rtl8169_private
*tp
= netdev_priv(dev
);
6190 rtl8169_net_suspend(dev
);
6192 /* Restore original MAC address */
6193 rtl_rar_set(tp
, dev
->perm_addr
);
6195 spin_lock_irq(&tp
->lock
);
6197 rtl8169_hw_reset(tp
);
6199 spin_unlock_irq(&tp
->lock
);
6201 if (system_state
== SYSTEM_POWER_OFF
) {
6202 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
6203 rtl_wol_suspend_quirk(tp
);
6204 rtl_wol_shutdown_quirk(tp
);
6207 pci_wake_from_d3(pdev
, true);
6208 pci_set_power_state(pdev
, PCI_D3hot
);
6212 static struct pci_driver rtl8169_pci_driver
= {
6214 .id_table
= rtl8169_pci_tbl
,
6215 .probe
= rtl8169_init_one
,
6216 .remove
= __devexit_p(rtl8169_remove_one
),
6217 .shutdown
= rtl_shutdown
,
6218 .driver
.pm
= RTL8169_PM_OPS
,
6221 static int __init
rtl8169_init_module(void)
6223 return pci_register_driver(&rtl8169_pci_driver
);
6226 static void __exit
rtl8169_cleanup_module(void)
6228 pci_unregister_driver(&rtl8169_pci_driver
);
6231 module_init(rtl8169_init_module
);
6232 module_exit(rtl8169_cleanup_module
);