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5b4103db70f5c25025241672c19e48be6c583eaa
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / rdc / r6040.c
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Copyright (C) 2007-2012 Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/string.h>
29 #include <linux/timer.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/interrupt.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/mii.h>
40 #include <linux/ethtool.h>
41 #include <linux/crc32.h>
42 #include <linux/spinlock.h>
43 #include <linux/bitops.h>
44 #include <linux/io.h>
45 #include <linux/irq.h>
46 #include <linux/uaccess.h>
47 #include <linux/phy.h>
48
49 #include <asm/processor.h>
50
51 #define DRV_NAME "r6040"
52 #define DRV_VERSION "0.28"
53 #define DRV_RELDATE "07Oct2011"
54
55 /* Time in jiffies before concluding the transmitter is hung. */
56 #define TX_TIMEOUT (6000 * HZ / 1000)
57
58 /* RDC MAC I/O Size */
59 #define R6040_IO_SIZE 256
60
61 /* MAX RDC MAC */
62 #define MAX_MAC 2
63
64 /* MAC registers */
65 #define MCR0 0x00 /* Control register 0 */
66 #define MCR0_RCVEN 0x0002 /* Receive enable */
67 #define MCR0_PROMISC 0x0020 /* Promiscuous mode */
68 #define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
69 #define MCR0_XMTEN 0x1000 /* Transmission enable */
70 #define MCR0_FD 0x8000 /* Full/Half duplex */
71 #define MCR1 0x04 /* Control register 1 */
72 #define MAC_RST 0x0001 /* Reset the MAC */
73 #define MBCR 0x08 /* Bus control */
74 #define MT_ICR 0x0C /* TX interrupt control */
75 #define MR_ICR 0x10 /* RX interrupt control */
76 #define MTPR 0x14 /* TX poll command register */
77 #define TM2TX 0x0001 /* Trigger MAC to transmit */
78 #define MR_BSR 0x18 /* RX buffer size */
79 #define MR_DCR 0x1A /* RX descriptor control */
80 #define MLSR 0x1C /* Last status */
81 #define TX_FIFO_UNDR 0x0200 /* TX FIFO under-run */
82 #define TX_EXCEEDC 0x2000 /* Transmit exceed collision */
83 #define TX_LATEC 0x4000 /* Transmit late collision */
84 #define MMDIO 0x20 /* MDIO control register */
85 #define MDIO_WRITE 0x4000 /* MDIO write */
86 #define MDIO_READ 0x2000 /* MDIO read */
87 #define MMRD 0x24 /* MDIO read data register */
88 #define MMWD 0x28 /* MDIO write data register */
89 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
90 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
91 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
92 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
93 #define MISR 0x3C /* Status register */
94 #define MIER 0x40 /* INT enable register */
95 #define MSK_INT 0x0000 /* Mask off interrupts */
96 #define RX_FINISH 0x0001 /* RX finished */
97 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
98 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
99 #define RX_EARLY 0x0008 /* RX early */
100 #define TX_FINISH 0x0010 /* TX finished */
101 #define TX_EARLY 0x0080 /* TX early */
102 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
103 #define LINK_CHANGED 0x0200 /* PHY link changed */
104 #define ME_CISR 0x44 /* Event counter INT status */
105 #define ME_CIER 0x48 /* Event counter INT enable */
106 #define MR_CNT 0x50 /* Successfully received packet counter */
107 #define ME_CNT0 0x52 /* Event counter 0 */
108 #define ME_CNT1 0x54 /* Event counter 1 */
109 #define ME_CNT2 0x56 /* Event counter 2 */
110 #define ME_CNT3 0x58 /* Event counter 3 */
111 #define MT_CNT 0x5A /* Successfully transmit packet counter */
112 #define ME_CNT4 0x5C /* Event counter 4 */
113 #define MP_CNT 0x5E /* Pause frame counter register */
114 #define MAR0 0x60 /* Hash table 0 */
115 #define MAR1 0x62 /* Hash table 1 */
116 #define MAR2 0x64 /* Hash table 2 */
117 #define MAR3 0x66 /* Hash table 3 */
118 #define MID_0L 0x68 /* Multicast address MID0 Low */
119 #define MID_0M 0x6A /* Multicast address MID0 Medium */
120 #define MID_0H 0x6C /* Multicast address MID0 High */
121 #define MID_1L 0x70 /* MID1 Low */
122 #define MID_1M 0x72 /* MID1 Medium */
123 #define MID_1H 0x74 /* MID1 High */
124 #define MID_2L 0x78 /* MID2 Low */
125 #define MID_2M 0x7A /* MID2 Medium */
126 #define MID_2H 0x7C /* MID2 High */
127 #define MID_3L 0x80 /* MID3 Low */
128 #define MID_3M 0x82 /* MID3 Medium */
129 #define MID_3H 0x84 /* MID3 High */
130 #define PHY_CC 0x88 /* PHY status change configuration register */
131 #define SCEN 0x8000 /* PHY status change enable */
132 #define PHYAD_SHIFT 8 /* PHY address shift */
133 #define TMRDIV_SHIFT 0 /* Timer divider shift */
134 #define PHY_ST 0x8A /* PHY status register */
135 #define MAC_SM 0xAC /* MAC status machine */
136 #define MAC_SM_RST 0x0002 /* MAC status machine reset */
137 #define MAC_ID 0xBE /* Identifier register */
138
139 #define TX_DCNT 0x80 /* TX descriptor count */
140 #define RX_DCNT 0x80 /* RX descriptor count */
141 #define MAX_BUF_SIZE 0x600
142 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
143 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
144 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
145 #define MCAST_MAX 3 /* Max number multicast addresses to filter */
146
147 #define MAC_DEF_TIMEOUT 2048 /* Default MAC read/write operation timeout */
148
149 /* Descriptor status */
150 #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
151 #define DSC_RX_OK 0x4000 /* RX was successful */
152 #define DSC_RX_ERR 0x0800 /* RX PHY error */
153 #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
154 #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
155 #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
156 #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
157 #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
158 #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
159 #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
160 #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
161 #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
162 #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
163
164 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
165 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
166 "Florian Fainelli <florian@openwrt.org>");
167 MODULE_LICENSE("GPL");
168 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
169 MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
170
171 /* RX and TX interrupts that we handle */
172 #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
173 #define TX_INTS (TX_FINISH)
174 #define INT_MASK (RX_INTS | TX_INTS)
175
176 struct r6040_descriptor {
177 u16 status, len; /* 0-3 */
178 __le32 buf; /* 4-7 */
179 __le32 ndesc; /* 8-B */
180 u32 rev1; /* C-F */
181 char *vbufp; /* 10-13 */
182 struct r6040_descriptor *vndescp; /* 14-17 */
183 struct sk_buff *skb_ptr; /* 18-1B */
184 u32 rev2; /* 1C-1F */
185 } __aligned(32);
186
187 struct r6040_private {
188 spinlock_t lock; /* driver lock */
189 struct pci_dev *pdev;
190 struct r6040_descriptor *rx_insert_ptr;
191 struct r6040_descriptor *rx_remove_ptr;
192 struct r6040_descriptor *tx_insert_ptr;
193 struct r6040_descriptor *tx_remove_ptr;
194 struct r6040_descriptor *rx_ring;
195 struct r6040_descriptor *tx_ring;
196 dma_addr_t rx_ring_dma;
197 dma_addr_t tx_ring_dma;
198 u16 tx_free_desc;
199 u16 mcr0;
200 struct net_device *dev;
201 struct mii_bus *mii_bus;
202 struct napi_struct napi;
203 void __iomem *base;
204 struct phy_device *phydev;
205 int old_link;
206 int old_duplex;
207 };
208
209 static char version[] = DRV_NAME
210 ": RDC R6040 NAPI net driver,"
211 "version "DRV_VERSION " (" DRV_RELDATE ")";
212
213 /* Read a word data from PHY Chip */
214 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
215 {
216 int limit = MAC_DEF_TIMEOUT;
217 u16 cmd;
218
219 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
220 /* Wait for the read bit to be cleared */
221 while (limit--) {
222 cmd = ioread16(ioaddr + MMDIO);
223 if (!(cmd & MDIO_READ))
224 break;
225 }
226
227 return ioread16(ioaddr + MMRD);
228 }
229
230 /* Write a word data from PHY Chip */
231 static void r6040_phy_write(void __iomem *ioaddr,
232 int phy_addr, int reg, u16 val)
233 {
234 int limit = MAC_DEF_TIMEOUT;
235 u16 cmd;
236
237 iowrite16(val, ioaddr + MMWD);
238 /* Write the command to the MDIO bus */
239 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
240 /* Wait for the write bit to be cleared */
241 while (limit--) {
242 cmd = ioread16(ioaddr + MMDIO);
243 if (!(cmd & MDIO_WRITE))
244 break;
245 }
246 }
247
248 static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
249 {
250 struct net_device *dev = bus->priv;
251 struct r6040_private *lp = netdev_priv(dev);
252 void __iomem *ioaddr = lp->base;
253
254 return r6040_phy_read(ioaddr, phy_addr, reg);
255 }
256
257 static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
258 int reg, u16 value)
259 {
260 struct net_device *dev = bus->priv;
261 struct r6040_private *lp = netdev_priv(dev);
262 void __iomem *ioaddr = lp->base;
263
264 r6040_phy_write(ioaddr, phy_addr, reg, value);
265
266 return 0;
267 }
268
269 static int r6040_mdiobus_reset(struct mii_bus *bus)
270 {
271 return 0;
272 }
273
274 static void r6040_free_txbufs(struct net_device *dev)
275 {
276 struct r6040_private *lp = netdev_priv(dev);
277 int i;
278
279 for (i = 0; i < TX_DCNT; i++) {
280 if (lp->tx_insert_ptr->skb_ptr) {
281 pci_unmap_single(lp->pdev,
282 le32_to_cpu(lp->tx_insert_ptr->buf),
283 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
284 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
285 lp->tx_insert_ptr->skb_ptr = NULL;
286 }
287 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
288 }
289 }
290
291 static void r6040_free_rxbufs(struct net_device *dev)
292 {
293 struct r6040_private *lp = netdev_priv(dev);
294 int i;
295
296 for (i = 0; i < RX_DCNT; i++) {
297 if (lp->rx_insert_ptr->skb_ptr) {
298 pci_unmap_single(lp->pdev,
299 le32_to_cpu(lp->rx_insert_ptr->buf),
300 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
301 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
302 lp->rx_insert_ptr->skb_ptr = NULL;
303 }
304 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
305 }
306 }
307
308 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
309 dma_addr_t desc_dma, int size)
310 {
311 struct r6040_descriptor *desc = desc_ring;
312 dma_addr_t mapping = desc_dma;
313
314 while (size-- > 0) {
315 mapping += sizeof(*desc);
316 desc->ndesc = cpu_to_le32(mapping);
317 desc->vndescp = desc + 1;
318 desc++;
319 }
320 desc--;
321 desc->ndesc = cpu_to_le32(desc_dma);
322 desc->vndescp = desc_ring;
323 }
324
325 static void r6040_init_txbufs(struct net_device *dev)
326 {
327 struct r6040_private *lp = netdev_priv(dev);
328
329 lp->tx_free_desc = TX_DCNT;
330
331 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
332 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
333 }
334
335 static int r6040_alloc_rxbufs(struct net_device *dev)
336 {
337 struct r6040_private *lp = netdev_priv(dev);
338 struct r6040_descriptor *desc;
339 struct sk_buff *skb;
340 int rc;
341
342 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
343 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
344
345 /* Allocate skbs for the rx descriptors */
346 desc = lp->rx_ring;
347 do {
348 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
349 if (!skb) {
350 netdev_err(dev, "failed to alloc skb for rx\n");
351 rc = -ENOMEM;
352 goto err_exit;
353 }
354 desc->skb_ptr = skb;
355 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
356 desc->skb_ptr->data,
357 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
358 desc->status = DSC_OWNER_MAC;
359 desc = desc->vndescp;
360 } while (desc != lp->rx_ring);
361
362 return 0;
363
364 err_exit:
365 /* Deallocate all previously allocated skbs */
366 r6040_free_rxbufs(dev);
367 return rc;
368 }
369
370 static void r6040_reset_mac(struct r6040_private *lp)
371 {
372 void __iomem *ioaddr = lp->base;
373 int limit = MAC_DEF_TIMEOUT;
374 u16 cmd;
375
376 iowrite16(MAC_RST, ioaddr + MCR1);
377 while (limit--) {
378 cmd = ioread16(ioaddr + MCR1);
379 if (cmd & MAC_RST)
380 break;
381 }
382
383 /* Reset internal state machine */
384 iowrite16(MAC_SM_RST, ioaddr + MAC_SM);
385 iowrite16(0, ioaddr + MAC_SM);
386 mdelay(5);
387 }
388
389 static void r6040_init_mac_regs(struct net_device *dev)
390 {
391 struct r6040_private *lp = netdev_priv(dev);
392 void __iomem *ioaddr = lp->base;
393
394 /* Mask Off Interrupt */
395 iowrite16(MSK_INT, ioaddr + MIER);
396
397 /* Reset RDC MAC */
398 r6040_reset_mac(lp);
399
400 /* MAC Bus Control Register */
401 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
402
403 /* Buffer Size Register */
404 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
405
406 /* Write TX ring start address */
407 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
408 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
409
410 /* Write RX ring start address */
411 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
412 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
413
414 /* Set interrupt waiting time and packet numbers */
415 iowrite16(0, ioaddr + MT_ICR);
416 iowrite16(0, ioaddr + MR_ICR);
417
418 /* Enable interrupts */
419 iowrite16(INT_MASK, ioaddr + MIER);
420
421 /* Enable TX and RX */
422 iowrite16(lp->mcr0 | MCR0_RCVEN, ioaddr);
423
424 /* Let TX poll the descriptors
425 * we may got called by r6040_tx_timeout which has left
426 * some unsent tx buffers */
427 iowrite16(TM2TX, ioaddr + MTPR);
428 }
429
430 static void r6040_tx_timeout(struct net_device *dev)
431 {
432 struct r6040_private *priv = netdev_priv(dev);
433 void __iomem *ioaddr = priv->base;
434
435 netdev_warn(dev, "transmit timed out, int enable %4.4x "
436 "status %4.4x\n",
437 ioread16(ioaddr + MIER),
438 ioread16(ioaddr + MISR));
439
440 dev->stats.tx_errors++;
441
442 /* Reset MAC and re-init all registers */
443 r6040_init_mac_regs(dev);
444 }
445
446 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
447 {
448 struct r6040_private *priv = netdev_priv(dev);
449 void __iomem *ioaddr = priv->base;
450 unsigned long flags;
451
452 spin_lock_irqsave(&priv->lock, flags);
453 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
454 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
455 spin_unlock_irqrestore(&priv->lock, flags);
456
457 return &dev->stats;
458 }
459
460 /* Stop RDC MAC and Free the allocated resource */
461 static void r6040_down(struct net_device *dev)
462 {
463 struct r6040_private *lp = netdev_priv(dev);
464 void __iomem *ioaddr = lp->base;
465 u16 *adrp;
466
467 /* Stop MAC */
468 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
469
470 /* Reset RDC MAC */
471 r6040_reset_mac(lp);
472
473 /* Restore MAC Address to MIDx */
474 adrp = (u16 *) dev->dev_addr;
475 iowrite16(adrp[0], ioaddr + MID_0L);
476 iowrite16(adrp[1], ioaddr + MID_0M);
477 iowrite16(adrp[2], ioaddr + MID_0H);
478
479 phy_stop(lp->phydev);
480 }
481
482 static int r6040_close(struct net_device *dev)
483 {
484 struct r6040_private *lp = netdev_priv(dev);
485 struct pci_dev *pdev = lp->pdev;
486
487 spin_lock_irq(&lp->lock);
488 napi_disable(&lp->napi);
489 netif_stop_queue(dev);
490 r6040_down(dev);
491
492 free_irq(dev->irq, dev);
493
494 /* Free RX buffer */
495 r6040_free_rxbufs(dev);
496
497 /* Free TX buffer */
498 r6040_free_txbufs(dev);
499
500 spin_unlock_irq(&lp->lock);
501
502 /* Free Descriptor memory */
503 if (lp->rx_ring) {
504 pci_free_consistent(pdev,
505 RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
506 lp->rx_ring = NULL;
507 }
508
509 if (lp->tx_ring) {
510 pci_free_consistent(pdev,
511 TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
512 lp->tx_ring = NULL;
513 }
514
515 return 0;
516 }
517
518 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
519 {
520 struct r6040_private *lp = netdev_priv(dev);
521
522 if (!lp->phydev)
523 return -EINVAL;
524
525 return phy_mii_ioctl(lp->phydev, rq, cmd);
526 }
527
528 static int r6040_rx(struct net_device *dev, int limit)
529 {
530 struct r6040_private *priv = netdev_priv(dev);
531 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
532 struct sk_buff *skb_ptr, *new_skb;
533 int count = 0;
534 u16 err;
535
536 /* Limit not reached and the descriptor belongs to the CPU */
537 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
538 /* Read the descriptor status */
539 err = descptr->status;
540 /* Global error status set */
541 if (err & DSC_RX_ERR) {
542 /* RX dribble */
543 if (err & DSC_RX_ERR_DRI)
544 dev->stats.rx_frame_errors++;
545 /* Buffer length exceeded */
546 if (err & DSC_RX_ERR_BUF)
547 dev->stats.rx_length_errors++;
548 /* Packet too long */
549 if (err & DSC_RX_ERR_LONG)
550 dev->stats.rx_length_errors++;
551 /* Packet < 64 bytes */
552 if (err & DSC_RX_ERR_RUNT)
553 dev->stats.rx_length_errors++;
554 /* CRC error */
555 if (err & DSC_RX_ERR_CRC) {
556 spin_lock(&priv->lock);
557 dev->stats.rx_crc_errors++;
558 spin_unlock(&priv->lock);
559 }
560 goto next_descr;
561 }
562
563 /* Packet successfully received */
564 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
565 if (!new_skb) {
566 dev->stats.rx_dropped++;
567 goto next_descr;
568 }
569 skb_ptr = descptr->skb_ptr;
570 skb_ptr->dev = priv->dev;
571
572 /* Do not count the CRC */
573 skb_put(skb_ptr, descptr->len - 4);
574 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
575 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
576 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
577
578 /* Send to upper layer */
579 netif_receive_skb(skb_ptr);
580 dev->stats.rx_packets++;
581 dev->stats.rx_bytes += descptr->len - 4;
582
583 /* put new skb into descriptor */
584 descptr->skb_ptr = new_skb;
585 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
586 descptr->skb_ptr->data,
587 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
588
589 next_descr:
590 /* put the descriptor back to the MAC */
591 descptr->status = DSC_OWNER_MAC;
592 descptr = descptr->vndescp;
593 count++;
594 }
595 priv->rx_remove_ptr = descptr;
596
597 return count;
598 }
599
600 static void r6040_tx(struct net_device *dev)
601 {
602 struct r6040_private *priv = netdev_priv(dev);
603 struct r6040_descriptor *descptr;
604 void __iomem *ioaddr = priv->base;
605 struct sk_buff *skb_ptr;
606 u16 err;
607
608 spin_lock(&priv->lock);
609 descptr = priv->tx_remove_ptr;
610 while (priv->tx_free_desc < TX_DCNT) {
611 /* Check for errors */
612 err = ioread16(ioaddr + MLSR);
613
614 if (err & TX_FIFO_UNDR)
615 dev->stats.tx_fifo_errors++;
616 if (err & (TX_EXCEEDC | TX_LATEC))
617 dev->stats.tx_carrier_errors++;
618
619 if (descptr->status & DSC_OWNER_MAC)
620 break; /* Not complete */
621 skb_ptr = descptr->skb_ptr;
622 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
623 skb_ptr->len, PCI_DMA_TODEVICE);
624 /* Free buffer */
625 dev_kfree_skb_irq(skb_ptr);
626 descptr->skb_ptr = NULL;
627 /* To next descriptor */
628 descptr = descptr->vndescp;
629 priv->tx_free_desc++;
630 }
631 priv->tx_remove_ptr = descptr;
632
633 if (priv->tx_free_desc)
634 netif_wake_queue(dev);
635 spin_unlock(&priv->lock);
636 }
637
638 static int r6040_poll(struct napi_struct *napi, int budget)
639 {
640 struct r6040_private *priv =
641 container_of(napi, struct r6040_private, napi);
642 struct net_device *dev = priv->dev;
643 void __iomem *ioaddr = priv->base;
644 int work_done;
645
646 work_done = r6040_rx(dev, budget);
647
648 if (work_done < budget) {
649 napi_complete(napi);
650 /* Enable RX interrupt */
651 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
652 }
653 return work_done;
654 }
655
656 /* The RDC interrupt handler. */
657 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
658 {
659 struct net_device *dev = dev_id;
660 struct r6040_private *lp = netdev_priv(dev);
661 void __iomem *ioaddr = lp->base;
662 u16 misr, status;
663
664 /* Save MIER */
665 misr = ioread16(ioaddr + MIER);
666 /* Mask off RDC MAC interrupt */
667 iowrite16(MSK_INT, ioaddr + MIER);
668 /* Read MISR status and clear */
669 status = ioread16(ioaddr + MISR);
670
671 if (status == 0x0000 || status == 0xffff) {
672 /* Restore RDC MAC interrupt */
673 iowrite16(misr, ioaddr + MIER);
674 return IRQ_NONE;
675 }
676
677 /* RX interrupt request */
678 if (status & RX_INTS) {
679 if (status & RX_NO_DESC) {
680 /* RX descriptor unavailable */
681 dev->stats.rx_dropped++;
682 dev->stats.rx_missed_errors++;
683 }
684 if (status & RX_FIFO_FULL)
685 dev->stats.rx_fifo_errors++;
686
687 if (likely(napi_schedule_prep(&lp->napi))) {
688 /* Mask off RX interrupt */
689 misr &= ~RX_INTS;
690 __napi_schedule(&lp->napi);
691 }
692 }
693
694 /* TX interrupt request */
695 if (status & TX_INTS)
696 r6040_tx(dev);
697
698 /* Restore RDC MAC interrupt */
699 iowrite16(misr, ioaddr + MIER);
700
701 return IRQ_HANDLED;
702 }
703
704 #ifdef CONFIG_NET_POLL_CONTROLLER
705 static void r6040_poll_controller(struct net_device *dev)
706 {
707 disable_irq(dev->irq);
708 r6040_interrupt(dev->irq, dev);
709 enable_irq(dev->irq);
710 }
711 #endif
712
713 /* Init RDC MAC */
714 static int r6040_up(struct net_device *dev)
715 {
716 struct r6040_private *lp = netdev_priv(dev);
717 void __iomem *ioaddr = lp->base;
718 int ret;
719
720 /* Initialise and alloc RX/TX buffers */
721 r6040_init_txbufs(dev);
722 ret = r6040_alloc_rxbufs(dev);
723 if (ret)
724 return ret;
725
726 /* improve performance (by RDC guys) */
727 r6040_phy_write(ioaddr, 30, 17,
728 (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
729 r6040_phy_write(ioaddr, 30, 17,
730 ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
731 r6040_phy_write(ioaddr, 0, 19, 0x0000);
732 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
733
734 /* Initialize all MAC registers */
735 r6040_init_mac_regs(dev);
736
737 phy_start(lp->phydev);
738
739 return 0;
740 }
741
742
743 /* Read/set MAC address routines */
744 static void r6040_mac_address(struct net_device *dev)
745 {
746 struct r6040_private *lp = netdev_priv(dev);
747 void __iomem *ioaddr = lp->base;
748 u16 *adrp;
749
750 /* Reset MAC */
751 r6040_reset_mac(lp);
752
753 /* Restore MAC Address */
754 adrp = (u16 *) dev->dev_addr;
755 iowrite16(adrp[0], ioaddr + MID_0L);
756 iowrite16(adrp[1], ioaddr + MID_0M);
757 iowrite16(adrp[2], ioaddr + MID_0H);
758 }
759
760 static int r6040_open(struct net_device *dev)
761 {
762 struct r6040_private *lp = netdev_priv(dev);
763 int ret;
764
765 /* Request IRQ and Register interrupt handler */
766 ret = request_irq(dev->irq, r6040_interrupt,
767 IRQF_SHARED, dev->name, dev);
768 if (ret)
769 goto out;
770
771 /* Set MAC address */
772 r6040_mac_address(dev);
773
774 /* Allocate Descriptor memory */
775 lp->rx_ring =
776 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
777 if (!lp->rx_ring) {
778 ret = -ENOMEM;
779 goto err_free_irq;
780 }
781
782 lp->tx_ring =
783 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
784 if (!lp->tx_ring) {
785 ret = -ENOMEM;
786 goto err_free_rx_ring;
787 }
788
789 ret = r6040_up(dev);
790 if (ret)
791 goto err_free_tx_ring;
792
793 napi_enable(&lp->napi);
794 netif_start_queue(dev);
795
796 return 0;
797
798 err_free_tx_ring:
799 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
800 lp->tx_ring_dma);
801 err_free_rx_ring:
802 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
803 lp->rx_ring_dma);
804 err_free_irq:
805 free_irq(dev->irq, dev);
806 out:
807 return ret;
808 }
809
810 static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
811 struct net_device *dev)
812 {
813 struct r6040_private *lp = netdev_priv(dev);
814 struct r6040_descriptor *descptr;
815 void __iomem *ioaddr = lp->base;
816 unsigned long flags;
817
818 /* Critical Section */
819 spin_lock_irqsave(&lp->lock, flags);
820
821 /* TX resource check */
822 if (!lp->tx_free_desc) {
823 spin_unlock_irqrestore(&lp->lock, flags);
824 netif_stop_queue(dev);
825 netdev_err(dev, ": no tx descriptor\n");
826 return NETDEV_TX_BUSY;
827 }
828
829 /* Statistic Counter */
830 dev->stats.tx_packets++;
831 dev->stats.tx_bytes += skb->len;
832 /* Set TX descriptor & Transmit it */
833 lp->tx_free_desc--;
834 descptr = lp->tx_insert_ptr;
835 if (skb->len < MISR)
836 descptr->len = MISR;
837 else
838 descptr->len = skb->len;
839
840 descptr->skb_ptr = skb;
841 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
842 skb->data, skb->len, PCI_DMA_TODEVICE));
843 descptr->status = DSC_OWNER_MAC;
844
845 skb_tx_timestamp(skb);
846
847 /* Trigger the MAC to check the TX descriptor */
848 iowrite16(TM2TX, ioaddr + MTPR);
849 lp->tx_insert_ptr = descptr->vndescp;
850
851 /* If no tx resource, stop */
852 if (!lp->tx_free_desc)
853 netif_stop_queue(dev);
854
855 spin_unlock_irqrestore(&lp->lock, flags);
856
857 return NETDEV_TX_OK;
858 }
859
860 static void r6040_multicast_list(struct net_device *dev)
861 {
862 struct r6040_private *lp = netdev_priv(dev);
863 void __iomem *ioaddr = lp->base;
864 unsigned long flags;
865 struct netdev_hw_addr *ha;
866 int i;
867 u16 *adrp;
868 u16 hash_table[4] = { 0 };
869
870 spin_lock_irqsave(&lp->lock, flags);
871
872 /* Keep our MAC Address */
873 adrp = (u16 *)dev->dev_addr;
874 iowrite16(adrp[0], ioaddr + MID_0L);
875 iowrite16(adrp[1], ioaddr + MID_0M);
876 iowrite16(adrp[2], ioaddr + MID_0H);
877
878 /* Clear AMCP & PROM bits */
879 lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN);
880
881 /* Promiscuous mode */
882 if (dev->flags & IFF_PROMISC)
883 lp->mcr0 |= MCR0_PROMISC;
884
885 /* Enable multicast hash table function to
886 * receive all multicast packets. */
887 else if (dev->flags & IFF_ALLMULTI) {
888 lp->mcr0 |= MCR0_HASH_EN;
889
890 for (i = 0; i < MCAST_MAX ; i++) {
891 iowrite16(0, ioaddr + MID_1L + 8 * i);
892 iowrite16(0, ioaddr + MID_1M + 8 * i);
893 iowrite16(0, ioaddr + MID_1H + 8 * i);
894 }
895
896 for (i = 0; i < 4; i++)
897 hash_table[i] = 0xffff;
898 }
899 /* Use internal multicast address registers if the number of
900 * multicast addresses is not greater than MCAST_MAX. */
901 else if (netdev_mc_count(dev) <= MCAST_MAX) {
902 i = 0;
903 netdev_for_each_mc_addr(ha, dev) {
904 u16 *adrp = (u16 *) ha->addr;
905 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
906 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
907 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
908 i++;
909 }
910 while (i < MCAST_MAX) {
911 iowrite16(0, ioaddr + MID_1L + 8 * i);
912 iowrite16(0, ioaddr + MID_1M + 8 * i);
913 iowrite16(0, ioaddr + MID_1H + 8 * i);
914 i++;
915 }
916 }
917 /* Otherwise, Enable multicast hash table function. */
918 else {
919 u32 crc;
920
921 lp->mcr0 |= MCR0_HASH_EN;
922
923 for (i = 0; i < MCAST_MAX ; i++) {
924 iowrite16(0, ioaddr + MID_1L + 8 * i);
925 iowrite16(0, ioaddr + MID_1M + 8 * i);
926 iowrite16(0, ioaddr + MID_1H + 8 * i);
927 }
928
929 /* Build multicast hash table */
930 netdev_for_each_mc_addr(ha, dev) {
931 u8 *addrs = ha->addr;
932
933 crc = ether_crc(ETH_ALEN, addrs);
934 crc >>= 26;
935 hash_table[crc >> 4] |= 1 << (crc & 0xf);
936 }
937 }
938
939 iowrite16(lp->mcr0, ioaddr + MCR0);
940
941 /* Fill the MAC hash tables with their values */
942 if (lp->mcr0 & MCR0_HASH_EN) {
943 iowrite16(hash_table[0], ioaddr + MAR0);
944 iowrite16(hash_table[1], ioaddr + MAR1);
945 iowrite16(hash_table[2], ioaddr + MAR2);
946 iowrite16(hash_table[3], ioaddr + MAR3);
947 }
948
949 spin_unlock_irqrestore(&lp->lock, flags);
950 }
951
952 static void netdev_get_drvinfo(struct net_device *dev,
953 struct ethtool_drvinfo *info)
954 {
955 struct r6040_private *rp = netdev_priv(dev);
956
957 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
958 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
959 strlcpy(info->bus_info, pci_name(rp->pdev), sizeof(info->bus_info));
960 }
961
962 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
963 {
964 struct r6040_private *rp = netdev_priv(dev);
965
966 return phy_ethtool_gset(rp->phydev, cmd);
967 }
968
969 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
970 {
971 struct r6040_private *rp = netdev_priv(dev);
972
973 return phy_ethtool_sset(rp->phydev, cmd);
974 }
975
976 static const struct ethtool_ops netdev_ethtool_ops = {
977 .get_drvinfo = netdev_get_drvinfo,
978 .get_settings = netdev_get_settings,
979 .set_settings = netdev_set_settings,
980 .get_link = ethtool_op_get_link,
981 .get_ts_info = ethtool_op_get_ts_info,
982 };
983
984 static const struct net_device_ops r6040_netdev_ops = {
985 .ndo_open = r6040_open,
986 .ndo_stop = r6040_close,
987 .ndo_start_xmit = r6040_start_xmit,
988 .ndo_get_stats = r6040_get_stats,
989 .ndo_set_rx_mode = r6040_multicast_list,
990 .ndo_change_mtu = eth_change_mtu,
991 .ndo_validate_addr = eth_validate_addr,
992 .ndo_set_mac_address = eth_mac_addr,
993 .ndo_do_ioctl = r6040_ioctl,
994 .ndo_tx_timeout = r6040_tx_timeout,
995 #ifdef CONFIG_NET_POLL_CONTROLLER
996 .ndo_poll_controller = r6040_poll_controller,
997 #endif
998 };
999
1000 static void r6040_adjust_link(struct net_device *dev)
1001 {
1002 struct r6040_private *lp = netdev_priv(dev);
1003 struct phy_device *phydev = lp->phydev;
1004 int status_changed = 0;
1005 void __iomem *ioaddr = lp->base;
1006
1007 BUG_ON(!phydev);
1008
1009 if (lp->old_link != phydev->link) {
1010 status_changed = 1;
1011 lp->old_link = phydev->link;
1012 }
1013
1014 /* reflect duplex change */
1015 if (phydev->link && (lp->old_duplex != phydev->duplex)) {
1016 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? MCR0_FD : 0);
1017 iowrite16(lp->mcr0, ioaddr);
1018
1019 status_changed = 1;
1020 lp->old_duplex = phydev->duplex;
1021 }
1022
1023 if (status_changed) {
1024 pr_info("%s: link %s", dev->name, phydev->link ?
1025 "UP" : "DOWN");
1026 if (phydev->link)
1027 pr_cont(" - %d/%s", phydev->speed,
1028 DUPLEX_FULL == phydev->duplex ? "full" : "half");
1029 pr_cont("\n");
1030 }
1031 }
1032
1033 static int r6040_mii_probe(struct net_device *dev)
1034 {
1035 struct r6040_private *lp = netdev_priv(dev);
1036 struct phy_device *phydev = NULL;
1037
1038 phydev = phy_find_first(lp->mii_bus);
1039 if (!phydev) {
1040 dev_err(&lp->pdev->dev, "no PHY found\n");
1041 return -ENODEV;
1042 }
1043
1044 phydev = phy_connect(dev, dev_name(&phydev->dev), &r6040_adjust_link,
1045 PHY_INTERFACE_MODE_MII);
1046
1047 if (IS_ERR(phydev)) {
1048 dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1049 return PTR_ERR(phydev);
1050 }
1051
1052 /* mask with MAC supported features */
1053 phydev->supported &= (SUPPORTED_10baseT_Half
1054 | SUPPORTED_10baseT_Full
1055 | SUPPORTED_100baseT_Half
1056 | SUPPORTED_100baseT_Full
1057 | SUPPORTED_Autoneg
1058 | SUPPORTED_MII
1059 | SUPPORTED_TP);
1060
1061 phydev->advertising = phydev->supported;
1062 lp->phydev = phydev;
1063 lp->old_link = 0;
1064 lp->old_duplex = -1;
1065
1066 dev_info(&lp->pdev->dev, "attached PHY driver [%s] "
1067 "(mii_bus:phy_addr=%s)\n",
1068 phydev->drv->name, dev_name(&phydev->dev));
1069
1070 return 0;
1071 }
1072
1073 static int r6040_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1074 {
1075 struct net_device *dev;
1076 struct r6040_private *lp;
1077 void __iomem *ioaddr;
1078 int err, io_size = R6040_IO_SIZE;
1079 static int card_idx = -1;
1080 int bar = 0;
1081 u16 *adrp;
1082 int i;
1083
1084 pr_info("%s\n", version);
1085
1086 err = pci_enable_device(pdev);
1087 if (err)
1088 goto err_out;
1089
1090 /* this should always be supported */
1091 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1092 if (err) {
1093 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1094 "not supported by the card\n");
1095 goto err_out_disable_dev;
1096 }
1097 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1098 if (err) {
1099 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1100 "not supported by the card\n");
1101 goto err_out_disable_dev;
1102 }
1103
1104 /* IO Size check */
1105 if (pci_resource_len(pdev, bar) < io_size) {
1106 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
1107 err = -EIO;
1108 goto err_out_disable_dev;
1109 }
1110
1111 pci_set_master(pdev);
1112
1113 dev = alloc_etherdev(sizeof(struct r6040_private));
1114 if (!dev) {
1115 err = -ENOMEM;
1116 goto err_out_disable_dev;
1117 }
1118 SET_NETDEV_DEV(dev, &pdev->dev);
1119 lp = netdev_priv(dev);
1120
1121 err = pci_request_regions(pdev, DRV_NAME);
1122
1123 if (err) {
1124 dev_err(&pdev->dev, "Failed to request PCI regions\n");
1125 goto err_out_free_dev;
1126 }
1127
1128 ioaddr = pci_iomap(pdev, bar, io_size);
1129 if (!ioaddr) {
1130 dev_err(&pdev->dev, "ioremap failed for device\n");
1131 err = -EIO;
1132 goto err_out_free_res;
1133 }
1134
1135 /* If PHY status change register is still set to zero it means the
1136 * bootloader didn't initialize it, so we set it to:
1137 * - enable phy status change
1138 * - enable all phy addresses
1139 * - set to lowest timer divider */
1140 if (ioread16(ioaddr + PHY_CC) == 0)
1141 iowrite16(SCEN | PHY_MAX_ADDR << PHYAD_SHIFT |
1142 7 << TMRDIV_SHIFT, ioaddr + PHY_CC);
1143
1144 /* Init system & device */
1145 lp->base = ioaddr;
1146 dev->irq = pdev->irq;
1147
1148 spin_lock_init(&lp->lock);
1149 pci_set_drvdata(pdev, dev);
1150
1151 /* Set MAC address */
1152 card_idx++;
1153
1154 adrp = (u16 *)dev->dev_addr;
1155 adrp[0] = ioread16(ioaddr + MID_0L);
1156 adrp[1] = ioread16(ioaddr + MID_0M);
1157 adrp[2] = ioread16(ioaddr + MID_0H);
1158
1159 /* Some bootloader/BIOSes do not initialize
1160 * MAC address, warn about that */
1161 if (!(adrp[0] || adrp[1] || adrp[2])) {
1162 netdev_warn(dev, "MAC address not initialized, "
1163 "generating random\n");
1164 eth_hw_addr_random(dev);
1165 }
1166
1167 /* Link new device into r6040_root_dev */
1168 lp->pdev = pdev;
1169 lp->dev = dev;
1170
1171 /* Init RDC private data */
1172 lp->mcr0 = MCR0_XMTEN | MCR0_RCVEN;
1173
1174 /* The RDC-specific entries in the device structure. */
1175 dev->netdev_ops = &r6040_netdev_ops;
1176 dev->ethtool_ops = &netdev_ethtool_ops;
1177 dev->watchdog_timeo = TX_TIMEOUT;
1178
1179 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1180
1181 lp->mii_bus = mdiobus_alloc();
1182 if (!lp->mii_bus) {
1183 dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
1184 err = -ENOMEM;
1185 goto err_out_unmap;
1186 }
1187
1188 lp->mii_bus->priv = dev;
1189 lp->mii_bus->read = r6040_mdiobus_read;
1190 lp->mii_bus->write = r6040_mdiobus_write;
1191 lp->mii_bus->reset = r6040_mdiobus_reset;
1192 lp->mii_bus->name = "r6040_eth_mii";
1193 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1194 dev_name(&pdev->dev), card_idx);
1195 lp->mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1196 if (!lp->mii_bus->irq) {
1197 err = -ENOMEM;
1198 goto err_out_mdio;
1199 }
1200
1201 for (i = 0; i < PHY_MAX_ADDR; i++)
1202 lp->mii_bus->irq[i] = PHY_POLL;
1203
1204 err = mdiobus_register(lp->mii_bus);
1205 if (err) {
1206 dev_err(&pdev->dev, "failed to register MII bus\n");
1207 goto err_out_mdio_irq;
1208 }
1209
1210 err = r6040_mii_probe(dev);
1211 if (err) {
1212 dev_err(&pdev->dev, "failed to probe MII bus\n");
1213 goto err_out_mdio_unregister;
1214 }
1215
1216 /* Register net device. After this dev->name assign */
1217 err = register_netdev(dev);
1218 if (err) {
1219 dev_err(&pdev->dev, "Failed to register net device\n");
1220 goto err_out_mdio_unregister;
1221 }
1222 return 0;
1223
1224 err_out_mdio_unregister:
1225 mdiobus_unregister(lp->mii_bus);
1226 err_out_mdio_irq:
1227 kfree(lp->mii_bus->irq);
1228 err_out_mdio:
1229 mdiobus_free(lp->mii_bus);
1230 err_out_unmap:
1231 netif_napi_del(&lp->napi);
1232 pci_set_drvdata(pdev, NULL);
1233 pci_iounmap(pdev, ioaddr);
1234 err_out_free_res:
1235 pci_release_regions(pdev);
1236 err_out_free_dev:
1237 free_netdev(dev);
1238 err_out_disable_dev:
1239 pci_disable_device(pdev);
1240 err_out:
1241 return err;
1242 }
1243
1244 static void r6040_remove_one(struct pci_dev *pdev)
1245 {
1246 struct net_device *dev = pci_get_drvdata(pdev);
1247 struct r6040_private *lp = netdev_priv(dev);
1248
1249 unregister_netdev(dev);
1250 mdiobus_unregister(lp->mii_bus);
1251 kfree(lp->mii_bus->irq);
1252 mdiobus_free(lp->mii_bus);
1253 netif_napi_del(&lp->napi);
1254 pci_iounmap(pdev, lp->base);
1255 pci_release_regions(pdev);
1256 free_netdev(dev);
1257 pci_disable_device(pdev);
1258 pci_set_drvdata(pdev, NULL);
1259 }
1260
1261
1262 static DEFINE_PCI_DEVICE_TABLE(r6040_pci_tbl) = {
1263 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1264 { 0 }
1265 };
1266 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1267
1268 static struct pci_driver r6040_driver = {
1269 .name = DRV_NAME,
1270 .id_table = r6040_pci_tbl,
1271 .probe = r6040_init_one,
1272 .remove = r6040_remove_one,
1273 };
1274
1275 module_pci_driver(r6040_driver);
kernel source for telekom puls (alcatel/mediatek)