projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
xfs: remote attribute lookups require the value length
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_hw.c
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #include "qlcnic.h"
9 #include "qlcnic_sriov.h"
10 #include <linux/if_vlan.h>
11 #include <linux/ipv6.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14
15 #define QLCNIC_MAX_TX_QUEUES 1
16 #define RSS_HASHTYPE_IP_TCP 0x3
17 #define QLC_83XX_FW_MBX_CMD 0
18
19 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
20 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
21 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
22 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
23 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
24 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
25 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
26 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
27 {QLCNIC_CMD_INTRPT_TEST, 22, 12},
28 {QLCNIC_CMD_SET_MTU, 3, 1},
29 {QLCNIC_CMD_READ_PHY, 4, 2},
30 {QLCNIC_CMD_WRITE_PHY, 5, 1},
31 {QLCNIC_CMD_READ_HW_REG, 4, 1},
32 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
33 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
34 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
35 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
36 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
37 {QLCNIC_CMD_GET_PCI_INFO, 1, 66},
38 {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
39 {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
40 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
41 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
42 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
43 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
44 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
45 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
46 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
47 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
48 {QLCNIC_CMD_TEMP_SIZE, 1, 4},
49 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
50 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
51 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
52 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
53 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
54 {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
55 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
56 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
57 {QLCNIC_CMD_GET_STATISTICS, 2, 80},
58 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
59 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
60 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
61 {QLCNIC_CMD_IDC_ACK, 5, 1},
62 {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
63 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
64 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
65 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
66 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
67 {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
68 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
69 };
70
71 const u32 qlcnic_83xx_ext_reg_tbl[] = {
72 0x38CC, /* Global Reset */
73 0x38F0, /* Wildcard */
74 0x38FC, /* Informant */
75 0x3038, /* Host MBX ctrl */
76 0x303C, /* FW MBX ctrl */
77 0x355C, /* BOOT LOADER ADDRESS REG */
78 0x3560, /* BOOT LOADER SIZE REG */
79 0x3564, /* FW IMAGE ADDR REG */
80 0x1000, /* MBX intr enable */
81 0x1200, /* Default Intr mask */
82 0x1204, /* Default Interrupt ID */
83 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
84 0x3784, /* QLC_83XX_IDC_DEV_STATE */
85 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
86 0x378C, /* QLC_83XX_IDC_DRV_ACK */
87 0x3790, /* QLC_83XX_IDC_CTRL */
88 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
89 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
90 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
91 0x37A0, /* QLC_83XX_IDC_PF_0 */
92 0x37A4, /* QLC_83XX_IDC_PF_1 */
93 0x37A8, /* QLC_83XX_IDC_PF_2 */
94 0x37AC, /* QLC_83XX_IDC_PF_3 */
95 0x37B0, /* QLC_83XX_IDC_PF_4 */
96 0x37B4, /* QLC_83XX_IDC_PF_5 */
97 0x37B8, /* QLC_83XX_IDC_PF_6 */
98 0x37BC, /* QLC_83XX_IDC_PF_7 */
99 0x37C0, /* QLC_83XX_IDC_PF_8 */
100 0x37C4, /* QLC_83XX_IDC_PF_9 */
101 0x37C8, /* QLC_83XX_IDC_PF_10 */
102 0x37CC, /* QLC_83XX_IDC_PF_11 */
103 0x37D0, /* QLC_83XX_IDC_PF_12 */
104 0x37D4, /* QLC_83XX_IDC_PF_13 */
105 0x37D8, /* QLC_83XX_IDC_PF_14 */
106 0x37DC, /* QLC_83XX_IDC_PF_15 */
107 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
108 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
109 0x37F0, /* QLC_83XX_DRV_OP_MODE */
110 0x37F4, /* QLC_83XX_VNIC_STATE */
111 0x3868, /* QLC_83XX_DRV_LOCK */
112 0x386C, /* QLC_83XX_DRV_UNLOCK */
113 0x3504, /* QLC_83XX_DRV_LOCK_ID */
114 0x34A4, /* QLC_83XX_ASIC_TEMP */
115 };
116
117 const u32 qlcnic_83xx_reg_tbl[] = {
118 0x34A8, /* PEG_HALT_STAT1 */
119 0x34AC, /* PEG_HALT_STAT2 */
120 0x34B0, /* FW_HEARTBEAT */
121 0x3500, /* FLASH LOCK_ID */
122 0x3528, /* FW_CAPABILITIES */
123 0x3538, /* Driver active, DRV_REG0 */
124 0x3540, /* Device state, DRV_REG1 */
125 0x3544, /* Driver state, DRV_REG2 */
126 0x3548, /* Driver scratch, DRV_REG3 */
127 0x354C, /* Device partiton info, DRV_REG4 */
128 0x3524, /* Driver IDC ver, DRV_REG5 */
129 0x3550, /* FW_VER_MAJOR */
130 0x3554, /* FW_VER_MINOR */
131 0x3558, /* FW_VER_SUB */
132 0x359C, /* NPAR STATE */
133 0x35FC, /* FW_IMG_VALID */
134 0x3650, /* CMD_PEG_STATE */
135 0x373C, /* RCV_PEG_STATE */
136 0x37B4, /* ASIC TEMP */
137 0x356C, /* FW API */
138 0x3570, /* DRV OP MODE */
139 0x3850, /* FLASH LOCK */
140 0x3854, /* FLASH UNLOCK */
141 };
142
143 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
144 .read_crb = qlcnic_83xx_read_crb,
145 .write_crb = qlcnic_83xx_write_crb,
146 .read_reg = qlcnic_83xx_rd_reg_indirect,
147 .write_reg = qlcnic_83xx_wrt_reg_indirect,
148 .get_mac_address = qlcnic_83xx_get_mac_address,
149 .setup_intr = qlcnic_83xx_setup_intr,
150 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
151 .mbx_cmd = qlcnic_83xx_mbx_op,
152 .get_func_no = qlcnic_83xx_get_func_no,
153 .api_lock = qlcnic_83xx_cam_lock,
154 .api_unlock = qlcnic_83xx_cam_unlock,
155 .add_sysfs = qlcnic_83xx_add_sysfs,
156 .remove_sysfs = qlcnic_83xx_remove_sysfs,
157 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
158 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
159 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
160 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
161 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
162 .setup_link_event = qlcnic_83xx_setup_link_event,
163 .get_nic_info = qlcnic_83xx_get_nic_info,
164 .get_pci_info = qlcnic_83xx_get_pci_info,
165 .set_nic_info = qlcnic_83xx_set_nic_info,
166 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
167 .napi_enable = qlcnic_83xx_napi_enable,
168 .napi_disable = qlcnic_83xx_napi_disable,
169 .config_intr_coal = qlcnic_83xx_config_intr_coal,
170 .config_rss = qlcnic_83xx_config_rss,
171 .config_hw_lro = qlcnic_83xx_config_hw_lro,
172 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
173 .change_l2_filter = qlcnic_83xx_change_l2_filter,
174 .get_board_info = qlcnic_83xx_get_port_info,
175 .free_mac_list = qlcnic_82xx_free_mac_list,
176 };
177
178 static struct qlcnic_nic_template qlcnic_83xx_ops = {
179 .config_bridged_mode = qlcnic_config_bridged_mode,
180 .config_led = qlcnic_config_led,
181 .request_reset = qlcnic_83xx_idc_request_reset,
182 .cancel_idc_work = qlcnic_83xx_idc_exit,
183 .napi_add = qlcnic_83xx_napi_add,
184 .napi_del = qlcnic_83xx_napi_del,
185 .config_ipaddr = qlcnic_83xx_config_ipaddr,
186 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
187 };
188
189 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
190 {
191 ahw->hw_ops = &qlcnic_83xx_hw_ops;
192 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
193 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
194 }
195
196 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
197 {
198 u32 fw_major, fw_minor, fw_build;
199 struct pci_dev *pdev = adapter->pdev;
200
201 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
202 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
203 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
204 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
205
206 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
207 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
208
209 return adapter->fw_version;
210 }
211
212 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
213 {
214 void __iomem *base;
215 u32 val;
216
217 base = adapter->ahw->pci_base0 +
218 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
219 writel(addr, base);
220 val = readl(base);
221 if (val != addr)
222 return -EIO;
223
224 return 0;
225 }
226
227 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr)
228 {
229 int ret;
230 struct qlcnic_hardware_context *ahw = adapter->ahw;
231
232 ret = __qlcnic_set_win_base(adapter, (u32) addr);
233 if (!ret) {
234 return QLCRDX(ahw, QLCNIC_WILDCARD);
235 } else {
236 dev_err(&adapter->pdev->dev,
237 "%s failed, addr = 0x%x\n", __func__, (int)addr);
238 return -EIO;
239 }
240 }
241
242 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
243 u32 data)
244 {
245 int err;
246 struct qlcnic_hardware_context *ahw = adapter->ahw;
247
248 err = __qlcnic_set_win_base(adapter, (u32) addr);
249 if (!err) {
250 QLCWRX(ahw, QLCNIC_WILDCARD, data);
251 return 0;
252 } else {
253 dev_err(&adapter->pdev->dev,
254 "%s failed, addr = 0x%x data = 0x%x\n",
255 __func__, (int)addr, data);
256 return err;
257 }
258 }
259
260 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr)
261 {
262 int err, i, num_msix;
263 struct qlcnic_hardware_context *ahw = adapter->ahw;
264
265 if (!num_intr)
266 num_intr = QLCNIC_DEF_NUM_STS_DESC_RINGS;
267 num_msix = rounddown_pow_of_two(min_t(int, num_online_cpus(),
268 num_intr));
269 /* account for AEN interrupt MSI-X based interrupts */
270 num_msix += 1;
271
272 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
273 num_msix += adapter->max_drv_tx_rings;
274
275 err = qlcnic_enable_msix(adapter, num_msix);
276 if (err == -ENOMEM)
277 return err;
278 if (adapter->flags & QLCNIC_MSIX_ENABLED)
279 num_msix = adapter->ahw->num_msix;
280 else {
281 if (qlcnic_sriov_vf_check(adapter))
282 return -EINVAL;
283 num_msix = 1;
284 }
285 /* setup interrupt mapping table for fw */
286 ahw->intr_tbl = vzalloc(num_msix *
287 sizeof(struct qlcnic_intrpt_config));
288 if (!ahw->intr_tbl)
289 return -ENOMEM;
290 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
291 /* MSI-X enablement failed, use legacy interrupt */
292 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
293 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
294 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
295 adapter->msix_entries[0].vector = adapter->pdev->irq;
296 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
297 }
298
299 for (i = 0; i < num_msix; i++) {
300 if (adapter->flags & QLCNIC_MSIX_ENABLED)
301 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
302 else
303 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
304 ahw->intr_tbl[i].id = i;
305 ahw->intr_tbl[i].src = 0;
306 }
307 return 0;
308 }
309
310 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
311 {
312 writel(0, adapter->tgt_mask_reg);
313 }
314
315 /* Enable MSI-x and INT-x interrupts */
316 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
317 struct qlcnic_host_sds_ring *sds_ring)
318 {
319 writel(0, sds_ring->crb_intr_mask);
320 }
321
322 /* Disable MSI-x and INT-x interrupts */
323 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
324 struct qlcnic_host_sds_ring *sds_ring)
325 {
326 writel(1, sds_ring->crb_intr_mask);
327 }
328
329 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
330 *adapter)
331 {
332 u32 mask;
333
334 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
335 * source register. We could be here before contexts are created
336 * and sds_ring->crb_intr_mask has not been initialized, calculate
337 * BAR offset for Interrupt Source Register
338 */
339 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
340 writel(0, adapter->ahw->pci_base0 + mask);
341 }
342
343 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
344 {
345 u32 mask;
346
347 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
348 writel(1, adapter->ahw->pci_base0 + mask);
349 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
350 }
351
352 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
353 struct qlcnic_cmd_args *cmd)
354 {
355 int i;
356 for (i = 0; i < cmd->rsp.num; i++)
357 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
358 }
359
360 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
361 {
362 u32 intr_val;
363 struct qlcnic_hardware_context *ahw = adapter->ahw;
364 int retries = 0;
365
366 intr_val = readl(adapter->tgt_status_reg);
367
368 if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
369 return IRQ_NONE;
370
371 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
372 adapter->stats.spurious_intr++;
373 return IRQ_NONE;
374 }
375 /* The barrier is required to ensure writes to the registers */
376 wmb();
377
378 /* clear the interrupt trigger control register */
379 writel(0, adapter->isr_int_vec);
380 intr_val = readl(adapter->isr_int_vec);
381 do {
382 intr_val = readl(adapter->tgt_status_reg);
383 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
384 break;
385 retries++;
386 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
387 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
388
389 return IRQ_HANDLED;
390 }
391
392 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
393 {
394 u32 resp, event;
395 unsigned long flags;
396
397 spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
398
399 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
400 if (!(resp & QLCNIC_SET_OWNER))
401 goto out;
402
403 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
404 if (event & QLCNIC_MBX_ASYNC_EVENT)
405 __qlcnic_83xx_process_aen(adapter);
406
407 out:
408 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
409 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
410 }
411
412 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
413 {
414 struct qlcnic_adapter *adapter = data;
415 struct qlcnic_host_sds_ring *sds_ring;
416 struct qlcnic_hardware_context *ahw = adapter->ahw;
417
418 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
419 return IRQ_NONE;
420
421 qlcnic_83xx_poll_process_aen(adapter);
422
423 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
424 ahw->diag_cnt++;
425 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
426 return IRQ_HANDLED;
427 }
428
429 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
430 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
431 } else {
432 sds_ring = &adapter->recv_ctx->sds_rings[0];
433 napi_schedule(&sds_ring->napi);
434 }
435
436 return IRQ_HANDLED;
437 }
438
439 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
440 {
441 struct qlcnic_host_sds_ring *sds_ring = data;
442 struct qlcnic_adapter *adapter = sds_ring->adapter;
443
444 if (adapter->flags & QLCNIC_MSIX_ENABLED)
445 goto done;
446
447 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
448 return IRQ_NONE;
449
450 done:
451 adapter->ahw->diag_cnt++;
452 qlcnic_83xx_enable_intr(adapter, sds_ring);
453
454 return IRQ_HANDLED;
455 }
456
457 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
458 {
459 u32 num_msix;
460
461 qlcnic_83xx_disable_mbx_intr(adapter);
462
463 if (adapter->flags & QLCNIC_MSIX_ENABLED)
464 num_msix = adapter->ahw->num_msix - 1;
465 else
466 num_msix = 0;
467
468 msleep(20);
469 synchronize_irq(adapter->msix_entries[num_msix].vector);
470 free_irq(adapter->msix_entries[num_msix].vector, adapter);
471 }
472
473 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
474 {
475 irq_handler_t handler;
476 u32 val;
477 char name[32];
478 int err = 0;
479 unsigned long flags = 0;
480
481 if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
482 !(adapter->flags & QLCNIC_MSIX_ENABLED))
483 flags |= IRQF_SHARED;
484
485 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
486 handler = qlcnic_83xx_handle_aen;
487 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
488 snprintf(name, (IFNAMSIZ + 4),
489 "%s[%s]", "qlcnic", "aen");
490 err = request_irq(val, handler, flags, name, adapter);
491 if (err) {
492 dev_err(&adapter->pdev->dev,
493 "failed to register MBX interrupt\n");
494 return err;
495 }
496 } else {
497 handler = qlcnic_83xx_intr;
498 val = adapter->msix_entries[0].vector;
499 err = request_irq(val, handler, flags, "qlcnic", adapter);
500 if (err) {
501 dev_err(&adapter->pdev->dev,
502 "failed to register INTx interrupt\n");
503 return err;
504 }
505 qlcnic_83xx_clear_legacy_intr_mask(adapter);
506 }
507
508 /* Enable mailbox interrupt */
509 qlcnic_83xx_enable_mbx_intrpt(adapter);
510
511 return err;
512 }
513
514 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
515 {
516 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
517 adapter->ahw->pci_func = (val >> 24) & 0xff;
518 }
519
520 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
521 {
522 void __iomem *addr;
523 u32 val, limit = 0;
524
525 struct qlcnic_hardware_context *ahw = adapter->ahw;
526
527 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
528 do {
529 val = readl(addr);
530 if (val) {
531 /* write the function number to register */
532 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
533 ahw->pci_func);
534 return 0;
535 }
536 usleep_range(1000, 2000);
537 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
538
539 return -EIO;
540 }
541
542 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
543 {
544 void __iomem *addr;
545 u32 val;
546 struct qlcnic_hardware_context *ahw = adapter->ahw;
547
548 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
549 val = readl(addr);
550 }
551
552 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
553 loff_t offset, size_t size)
554 {
555 int ret;
556 u32 data;
557
558 if (qlcnic_api_lock(adapter)) {
559 dev_err(&adapter->pdev->dev,
560 "%s: failed to acquire lock. addr offset 0x%x\n",
561 __func__, (u32)offset);
562 return;
563 }
564
565 ret = qlcnic_83xx_rd_reg_indirect(adapter, (u32) offset);
566 qlcnic_api_unlock(adapter);
567
568 if (ret == -EIO) {
569 dev_err(&adapter->pdev->dev,
570 "%s: failed. addr offset 0x%x\n",
571 __func__, (u32)offset);
572 return;
573 }
574 data = ret;
575 memcpy(buf, &data, size);
576 }
577
578 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
579 loff_t offset, size_t size)
580 {
581 u32 data;
582
583 memcpy(&data, buf, size);
584 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
585 }
586
587 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
588 {
589 int status;
590
591 status = qlcnic_83xx_get_port_config(adapter);
592 if (status) {
593 dev_err(&adapter->pdev->dev,
594 "Get Port Info failed\n");
595 } else {
596 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
597 adapter->ahw->port_type = QLCNIC_XGBE;
598 else
599 adapter->ahw->port_type = QLCNIC_GBE;
600
601 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
602 adapter->ahw->link_autoneg = AUTONEG_ENABLE;
603 }
604 return status;
605 }
606
607 void qlcnic_83xx_enable_mbx_intrpt(struct qlcnic_adapter *adapter)
608 {
609 u32 val;
610
611 if (adapter->flags & QLCNIC_MSIX_ENABLED)
612 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
613 else
614 val = BIT_2;
615
616 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
617 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
618 }
619
620 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
621 const struct pci_device_id *ent)
622 {
623 u32 op_mode, priv_level;
624 struct qlcnic_hardware_context *ahw = adapter->ahw;
625
626 ahw->fw_hal_version = 2;
627 qlcnic_get_func_no(adapter);
628
629 if (qlcnic_sriov_vf_check(adapter)) {
630 qlcnic_sriov_vf_set_ops(adapter);
631 return;
632 }
633
634 /* Determine function privilege level */
635 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
636 if (op_mode == QLC_83XX_DEFAULT_OPMODE)
637 priv_level = QLCNIC_MGMT_FUNC;
638 else
639 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
640 ahw->pci_func);
641
642 if (priv_level == QLCNIC_NON_PRIV_FUNC) {
643 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
644 dev_info(&adapter->pdev->dev,
645 "HAL Version: %d Non Privileged function\n",
646 ahw->fw_hal_version);
647 adapter->nic_ops = &qlcnic_vf_ops;
648 } else {
649 if (pci_find_ext_capability(adapter->pdev,
650 PCI_EXT_CAP_ID_SRIOV))
651 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
652 adapter->nic_ops = &qlcnic_83xx_ops;
653 }
654 }
655
656 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
657 u32 data[]);
658 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
659 u32 data[]);
660
661 static void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
662 struct qlcnic_cmd_args *cmd)
663 {
664 int i;
665
666 dev_info(&adapter->pdev->dev,
667 "Host MBX regs(%d)\n", cmd->req.num);
668 for (i = 0; i < cmd->req.num; i++) {
669 if (i && !(i % 8))
670 pr_info("\n");
671 pr_info("%08x ", cmd->req.arg[i]);
672 }
673 pr_info("\n");
674 dev_info(&adapter->pdev->dev,
675 "FW MBX regs(%d)\n", cmd->rsp.num);
676 for (i = 0; i < cmd->rsp.num; i++) {
677 if (i && !(i % 8))
678 pr_info("\n");
679 pr_info("%08x ", cmd->rsp.arg[i]);
680 }
681 pr_info("\n");
682 }
683
684 /* Mailbox response for mac rcode */
685 u32 qlcnic_83xx_mac_rcode(struct qlcnic_adapter *adapter)
686 {
687 u32 fw_data;
688 u8 mac_cmd_rcode;
689
690 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
691 mac_cmd_rcode = (u8)fw_data;
692 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
693 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
694 mac_cmd_rcode == QLC_83XX_MAC_ABSENT)
695 return QLCNIC_RCODE_SUCCESS;
696 return 1;
697 }
698
699 u32 qlcnic_83xx_mbx_poll(struct qlcnic_adapter *adapter)
700 {
701 u32 data;
702 unsigned long wait_time = 0;
703 struct qlcnic_hardware_context *ahw = adapter->ahw;
704 /* wait for mailbox completion */
705 do {
706 data = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
707 if (++wait_time > QLCNIC_MBX_TIMEOUT) {
708 data = QLCNIC_RCODE_TIMEOUT;
709 break;
710 }
711 mdelay(1);
712 } while (!data);
713 return data;
714 }
715
716 int qlcnic_83xx_mbx_op(struct qlcnic_adapter *adapter,
717 struct qlcnic_cmd_args *cmd)
718 {
719 int i;
720 u16 opcode;
721 u8 mbx_err_code;
722 unsigned long flags;
723 u32 rsp, mbx_val, fw_data, rsp_num, mbx_cmd;
724 struct qlcnic_hardware_context *ahw = adapter->ahw;
725
726 opcode = LSW(cmd->req.arg[0]);
727 if (!test_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status)) {
728 dev_info(&adapter->pdev->dev,
729 "Mailbox cmd attempted, 0x%x\n", opcode);
730 dev_info(&adapter->pdev->dev, "Mailbox detached\n");
731 return 0;
732 }
733
734 spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
735 mbx_val = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
736
737 if (mbx_val) {
738 QLCDB(adapter, DRV,
739 "Mailbox cmd attempted, 0x%x\n", opcode);
740 QLCDB(adapter, DRV,
741 "Mailbox not available, 0x%x, collect FW dump\n",
742 mbx_val);
743 cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
744 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
745 return cmd->rsp.arg[0];
746 }
747
748 /* Fill in mailbox registers */
749 mbx_cmd = cmd->req.arg[0];
750 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
751 for (i = 1; i < cmd->req.num; i++)
752 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
753
754 /* Signal FW about the impending command */
755 QLCWRX(ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
756 poll:
757 rsp = qlcnic_83xx_mbx_poll(adapter);
758 if (rsp != QLCNIC_RCODE_TIMEOUT) {
759 /* Get the FW response data */
760 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
761 if (fw_data & QLCNIC_MBX_ASYNC_EVENT) {
762 __qlcnic_83xx_process_aen(adapter);
763 mbx_val = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
764 if (mbx_val)
765 goto poll;
766 }
767 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
768 rsp_num = QLCNIC_MBX_NUM_REGS(fw_data);
769 opcode = QLCNIC_MBX_RSP(fw_data);
770 qlcnic_83xx_get_mbx_data(adapter, cmd);
771
772 switch (mbx_err_code) {
773 case QLCNIC_MBX_RSP_OK:
774 case QLCNIC_MBX_PORT_RSP_OK:
775 rsp = QLCNIC_RCODE_SUCCESS;
776 break;
777 default:
778 if (opcode == QLCNIC_CMD_CONFIG_MAC_VLAN) {
779 rsp = qlcnic_83xx_mac_rcode(adapter);
780 if (!rsp)
781 goto out;
782 }
783 dev_err(&adapter->pdev->dev,
784 "MBX command 0x%x failed with err:0x%x\n",
785 opcode, mbx_err_code);
786 rsp = mbx_err_code;
787 qlcnic_dump_mbx(adapter, cmd);
788 break;
789 }
790 goto out;
791 }
792
793 dev_err(&adapter->pdev->dev, "MBX command 0x%x timed out\n",
794 QLCNIC_MBX_RSP(mbx_cmd));
795 rsp = QLCNIC_RCODE_TIMEOUT;
796 out:
797 /* clear fw mbx control register */
798 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
799 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
800 return rsp;
801 }
802
803 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
804 struct qlcnic_adapter *adapter, u32 type)
805 {
806 int i, size;
807 u32 temp;
808 const struct qlcnic_mailbox_metadata *mbx_tbl;
809
810 mbx_tbl = qlcnic_83xx_mbx_tbl;
811 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
812 for (i = 0; i < size; i++) {
813 if (type == mbx_tbl[i].cmd) {
814 mbx->op_type = QLC_83XX_FW_MBX_CMD;
815 mbx->req.num = mbx_tbl[i].in_args;
816 mbx->rsp.num = mbx_tbl[i].out_args;
817 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
818 GFP_ATOMIC);
819 if (!mbx->req.arg)
820 return -ENOMEM;
821 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
822 GFP_ATOMIC);
823 if (!mbx->rsp.arg) {
824 kfree(mbx->req.arg);
825 mbx->req.arg = NULL;
826 return -ENOMEM;
827 }
828 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
829 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
830 temp = adapter->ahw->fw_hal_version << 29;
831 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
832 return 0;
833 }
834 }
835 return -EINVAL;
836 }
837
838 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
839 {
840 struct qlcnic_adapter *adapter;
841 struct qlcnic_cmd_args cmd;
842 int i, err = 0;
843
844 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
845 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
846
847 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
848 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
849
850 err = qlcnic_issue_cmd(adapter, &cmd);
851 if (err)
852 dev_info(&adapter->pdev->dev,
853 "%s: Mailbox IDC ACK failed.\n", __func__);
854 qlcnic_free_mbx_args(&cmd);
855 }
856
857 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
858 u32 data[])
859 {
860 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
861 QLCNIC_MBX_RSP(data[0]));
862 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
863 return;
864 }
865
866 void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
867 {
868 u32 event[QLC_83XX_MBX_AEN_CNT];
869 int i;
870 struct qlcnic_hardware_context *ahw = adapter->ahw;
871
872 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
873 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
874
875 switch (QLCNIC_MBX_RSP(event[0])) {
876
877 case QLCNIC_MBX_LINK_EVENT:
878 qlcnic_83xx_handle_link_aen(adapter, event);
879 break;
880 case QLCNIC_MBX_COMP_EVENT:
881 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
882 break;
883 case QLCNIC_MBX_REQUEST_EVENT:
884 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
885 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
886 queue_delayed_work(adapter->qlcnic_wq,
887 &adapter->idc_aen_work, 0);
888 break;
889 case QLCNIC_MBX_TIME_EXTEND_EVENT:
890 break;
891 case QLCNIC_MBX_BC_EVENT:
892 qlcnic_sriov_handle_bc_event(adapter, event[1]);
893 break;
894 case QLCNIC_MBX_SFP_INSERT_EVENT:
895 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
896 QLCNIC_MBX_RSP(event[0]));
897 break;
898 case QLCNIC_MBX_SFP_REMOVE_EVENT:
899 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
900 QLCNIC_MBX_RSP(event[0]));
901 break;
902 default:
903 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
904 QLCNIC_MBX_RSP(event[0]));
905 break;
906 }
907
908 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
909 }
910
911 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
912 {
913 struct qlcnic_hardware_context *ahw = adapter->ahw;
914 u32 resp, event;
915 unsigned long flags;
916
917 spin_lock_irqsave(&ahw->mbx_lock, flags);
918
919 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
920 if (resp & QLCNIC_SET_OWNER) {
921 event = readl(QLCNIC_MBX_FW(ahw, 0));
922 if (event & QLCNIC_MBX_ASYNC_EVENT)
923 __qlcnic_83xx_process_aen(adapter);
924 }
925
926 spin_unlock_irqrestore(&ahw->mbx_lock, flags);
927 }
928
929 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
930 {
931 struct qlcnic_adapter *adapter;
932
933 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
934
935 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
936 return;
937
938 qlcnic_83xx_process_aen(adapter);
939 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
940 (HZ / 10));
941 }
942
943 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
944 {
945 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
946 return;
947
948 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
949 }
950
951 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
952 {
953 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
954 return;
955 cancel_delayed_work_sync(&adapter->mbx_poll_work);
956 }
957
958 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
959 {
960 int index, i, err, sds_mbx_size;
961 u32 *buf, intrpt_id, intr_mask;
962 u16 context_id;
963 u8 num_sds;
964 struct qlcnic_cmd_args cmd;
965 struct qlcnic_host_sds_ring *sds;
966 struct qlcnic_sds_mbx sds_mbx;
967 struct qlcnic_add_rings_mbx_out *mbx_out;
968 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
969 struct qlcnic_hardware_context *ahw = adapter->ahw;
970
971 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
972 context_id = recv_ctx->context_id;
973 num_sds = (adapter->max_sds_rings - QLCNIC_MAX_RING_SETS);
974 ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
975 QLCNIC_CMD_ADD_RCV_RINGS);
976 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
977
978 /* set up status rings, mbx 2-81 */
979 index = 2;
980 for (i = 8; i < adapter->max_sds_rings; i++) {
981 memset(&sds_mbx, 0, sds_mbx_size);
982 sds = &recv_ctx->sds_rings[i];
983 sds->consumer = 0;
984 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
985 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
986 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
987 sds_mbx.sds_ring_size = sds->num_desc;
988
989 if (adapter->flags & QLCNIC_MSIX_ENABLED)
990 intrpt_id = ahw->intr_tbl[i].id;
991 else
992 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
993
994 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
995 sds_mbx.intrpt_id = intrpt_id;
996 else
997 sds_mbx.intrpt_id = 0xffff;
998 sds_mbx.intrpt_val = 0;
999 buf = &cmd.req.arg[index];
1000 memcpy(buf, &sds_mbx, sds_mbx_size);
1001 index += sds_mbx_size / sizeof(u32);
1002 }
1003
1004 /* send the mailbox command */
1005 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1006 if (err) {
1007 dev_err(&adapter->pdev->dev,
1008 "Failed to add rings %d\n", err);
1009 goto out;
1010 }
1011
1012 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1013 index = 0;
1014 /* status descriptor ring */
1015 for (i = 8; i < adapter->max_sds_rings; i++) {
1016 sds = &recv_ctx->sds_rings[i];
1017 sds->crb_sts_consumer = ahw->pci_base0 +
1018 mbx_out->host_csmr[index];
1019 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1020 intr_mask = ahw->intr_tbl[i].src;
1021 else
1022 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1023
1024 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1025 index++;
1026 }
1027 out:
1028 qlcnic_free_mbx_args(&cmd);
1029 return err;
1030 }
1031
1032 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1033 {
1034 int err;
1035 u32 temp = 0;
1036 struct qlcnic_cmd_args cmd;
1037 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1038
1039 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1040 return;
1041
1042 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1043 cmd.req.arg[0] |= (0x3 << 29);
1044
1045 if (qlcnic_sriov_pf_check(adapter))
1046 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1047
1048 cmd.req.arg[1] = recv_ctx->context_id | temp;
1049 err = qlcnic_issue_cmd(adapter, &cmd);
1050 if (err)
1051 dev_err(&adapter->pdev->dev,
1052 "Failed to destroy rx ctx in firmware\n");
1053
1054 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1055 qlcnic_free_mbx_args(&cmd);
1056 }
1057
1058 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1059 {
1060 int i, err, index, sds_mbx_size, rds_mbx_size;
1061 u8 num_sds, num_rds;
1062 u32 *buf, intrpt_id, intr_mask, cap = 0;
1063 struct qlcnic_host_sds_ring *sds;
1064 struct qlcnic_host_rds_ring *rds;
1065 struct qlcnic_sds_mbx sds_mbx;
1066 struct qlcnic_rds_mbx rds_mbx;
1067 struct qlcnic_cmd_args cmd;
1068 struct qlcnic_rcv_mbx_out *mbx_out;
1069 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1070 struct qlcnic_hardware_context *ahw = adapter->ahw;
1071 num_rds = adapter->max_rds_rings;
1072
1073 if (adapter->max_sds_rings <= QLCNIC_MAX_RING_SETS)
1074 num_sds = adapter->max_sds_rings;
1075 else
1076 num_sds = QLCNIC_MAX_RING_SETS;
1077
1078 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1079 rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1080 cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1081
1082 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1083 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1084
1085 /* set mailbox hdr and capabilities */
1086 qlcnic_alloc_mbx_args(&cmd, adapter,
1087 QLCNIC_CMD_CREATE_RX_CTX);
1088
1089 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1090 cmd.req.arg[0] |= (0x3 << 29);
1091
1092 cmd.req.arg[1] = cap;
1093 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1094 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1095
1096 if (qlcnic_sriov_pf_check(adapter))
1097 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1098 &cmd.req.arg[6]);
1099 /* set up status rings, mbx 8-57/87 */
1100 index = QLC_83XX_HOST_SDS_MBX_IDX;
1101 for (i = 0; i < num_sds; i++) {
1102 memset(&sds_mbx, 0, sds_mbx_size);
1103 sds = &recv_ctx->sds_rings[i];
1104 sds->consumer = 0;
1105 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1106 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1107 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1108 sds_mbx.sds_ring_size = sds->num_desc;
1109 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1110 intrpt_id = ahw->intr_tbl[i].id;
1111 else
1112 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1113 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1114 sds_mbx.intrpt_id = intrpt_id;
1115 else
1116 sds_mbx.intrpt_id = 0xffff;
1117 sds_mbx.intrpt_val = 0;
1118 buf = &cmd.req.arg[index];
1119 memcpy(buf, &sds_mbx, sds_mbx_size);
1120 index += sds_mbx_size / sizeof(u32);
1121 }
1122 /* set up receive rings, mbx 88-111/135 */
1123 index = QLCNIC_HOST_RDS_MBX_IDX;
1124 rds = &recv_ctx->rds_rings[0];
1125 rds->producer = 0;
1126 memset(&rds_mbx, 0, rds_mbx_size);
1127 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1128 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1129 rds_mbx.reg_ring_sz = rds->dma_size;
1130 rds_mbx.reg_ring_len = rds->num_desc;
1131 /* Jumbo ring */
1132 rds = &recv_ctx->rds_rings[1];
1133 rds->producer = 0;
1134 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1135 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1136 rds_mbx.jmb_ring_sz = rds->dma_size;
1137 rds_mbx.jmb_ring_len = rds->num_desc;
1138 buf = &cmd.req.arg[index];
1139 memcpy(buf, &rds_mbx, rds_mbx_size);
1140
1141 /* send the mailbox command */
1142 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1143 if (err) {
1144 dev_err(&adapter->pdev->dev,
1145 "Failed to create Rx ctx in firmware%d\n", err);
1146 goto out;
1147 }
1148 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1149 recv_ctx->context_id = mbx_out->ctx_id;
1150 recv_ctx->state = mbx_out->state;
1151 recv_ctx->virt_port = mbx_out->vport_id;
1152 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1153 recv_ctx->context_id, recv_ctx->state);
1154 /* Receive descriptor ring */
1155 /* Standard ring */
1156 rds = &recv_ctx->rds_rings[0];
1157 rds->crb_rcv_producer = ahw->pci_base0 +
1158 mbx_out->host_prod[0].reg_buf;
1159 /* Jumbo ring */
1160 rds = &recv_ctx->rds_rings[1];
1161 rds->crb_rcv_producer = ahw->pci_base0 +
1162 mbx_out->host_prod[0].jmb_buf;
1163 /* status descriptor ring */
1164 for (i = 0; i < num_sds; i++) {
1165 sds = &recv_ctx->sds_rings[i];
1166 sds->crb_sts_consumer = ahw->pci_base0 +
1167 mbx_out->host_csmr[i];
1168 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1169 intr_mask = ahw->intr_tbl[i].src;
1170 else
1171 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1172 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1173 }
1174
1175 if (adapter->max_sds_rings > QLCNIC_MAX_RING_SETS)
1176 err = qlcnic_83xx_add_rings(adapter);
1177 out:
1178 qlcnic_free_mbx_args(&cmd);
1179 return err;
1180 }
1181
1182 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1183 struct qlcnic_host_tx_ring *tx_ring)
1184 {
1185 struct qlcnic_cmd_args cmd;
1186 u32 temp = 0;
1187
1188 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1189 return;
1190
1191 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1192 cmd.req.arg[0] |= (0x3 << 29);
1193
1194 if (qlcnic_sriov_pf_check(adapter))
1195 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1196
1197 cmd.req.arg[1] = tx_ring->ctx_id | temp;
1198 if (qlcnic_issue_cmd(adapter, &cmd))
1199 dev_err(&adapter->pdev->dev,
1200 "Failed to destroy tx ctx in firmware\n");
1201 qlcnic_free_mbx_args(&cmd);
1202 }
1203
1204 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1205 struct qlcnic_host_tx_ring *tx, int ring)
1206 {
1207 int err;
1208 u16 msix_id;
1209 u32 *buf, intr_mask, temp = 0;
1210 struct qlcnic_cmd_args cmd;
1211 struct qlcnic_tx_mbx mbx;
1212 struct qlcnic_tx_mbx_out *mbx_out;
1213 struct qlcnic_hardware_context *ahw = adapter->ahw;
1214 u32 msix_vector;
1215
1216 /* Reset host resources */
1217 tx->producer = 0;
1218 tx->sw_consumer = 0;
1219 *(tx->hw_consumer) = 0;
1220
1221 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1222
1223 /* setup mailbox inbox registerss */
1224 mbx.phys_addr_low = LSD(tx->phys_addr);
1225 mbx.phys_addr_high = MSD(tx->phys_addr);
1226 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1227 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1228 mbx.size = tx->num_desc;
1229 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1230 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1231 msix_vector = adapter->max_sds_rings + ring;
1232 else
1233 msix_vector = adapter->max_sds_rings - 1;
1234 msix_id = ahw->intr_tbl[msix_vector].id;
1235 } else {
1236 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1237 }
1238
1239 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1240 mbx.intr_id = msix_id;
1241 else
1242 mbx.intr_id = 0xffff;
1243 mbx.src = 0;
1244
1245 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1246
1247 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1248 cmd.req.arg[0] |= (0x3 << 29);
1249
1250 if (qlcnic_sriov_pf_check(adapter))
1251 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1252
1253 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1254 cmd.req.arg[5] = QLCNIC_MAX_TX_QUEUES | temp;
1255 buf = &cmd.req.arg[6];
1256 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1257 /* send the mailbox command*/
1258 err = qlcnic_issue_cmd(adapter, &cmd);
1259 if (err) {
1260 dev_err(&adapter->pdev->dev,
1261 "Failed to create Tx ctx in firmware 0x%x\n", err);
1262 goto out;
1263 }
1264 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1265 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1266 tx->ctx_id = mbx_out->ctx_id;
1267 if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1268 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1269 intr_mask = ahw->intr_tbl[adapter->max_sds_rings + ring].src;
1270 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1271 }
1272 dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1273 tx->ctx_id, mbx_out->state);
1274 out:
1275 qlcnic_free_mbx_args(&cmd);
1276 return err;
1277 }
1278
1279 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test)
1280 {
1281 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1282 struct qlcnic_host_sds_ring *sds_ring;
1283 struct qlcnic_host_rds_ring *rds_ring;
1284 u8 ring;
1285 int ret;
1286
1287 netif_device_detach(netdev);
1288
1289 if (netif_running(netdev))
1290 __qlcnic_down(adapter, netdev);
1291
1292 qlcnic_detach(adapter);
1293
1294 adapter->max_sds_rings = 1;
1295 adapter->ahw->diag_test = test;
1296 adapter->ahw->linkup = 0;
1297
1298 ret = qlcnic_attach(adapter);
1299 if (ret) {
1300 netif_device_attach(netdev);
1301 return ret;
1302 }
1303
1304 ret = qlcnic_fw_create_ctx(adapter);
1305 if (ret) {
1306 qlcnic_detach(adapter);
1307 netif_device_attach(netdev);
1308 return ret;
1309 }
1310
1311 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1312 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1313 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1314 }
1315
1316 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1317 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1318 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1319 qlcnic_83xx_enable_intr(adapter, sds_ring);
1320 }
1321 }
1322
1323 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1324 /* disable and free mailbox interrupt */
1325 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1326 qlcnic_83xx_free_mbx_intr(adapter);
1327 adapter->ahw->loopback_state = 0;
1328 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1329 }
1330
1331 set_bit(__QLCNIC_DEV_UP, &adapter->state);
1332 return 0;
1333 }
1334
1335 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1336 int max_sds_rings)
1337 {
1338 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1339 struct qlcnic_host_sds_ring *sds_ring;
1340 int ring, err;
1341
1342 clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1343 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1344 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1345 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1346 qlcnic_83xx_disable_intr(adapter, sds_ring);
1347 }
1348 }
1349
1350 qlcnic_fw_destroy_ctx(adapter);
1351 qlcnic_detach(adapter);
1352
1353 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1354 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1355 err = qlcnic_83xx_setup_mbx_intr(adapter);
1356 if (err) {
1357 dev_err(&adapter->pdev->dev,
1358 "%s: failed to setup mbx interrupt\n",
1359 __func__);
1360 goto out;
1361 }
1362 }
1363 }
1364 adapter->ahw->diag_test = 0;
1365 adapter->max_sds_rings = max_sds_rings;
1366
1367 if (qlcnic_attach(adapter))
1368 goto out;
1369
1370 if (netif_running(netdev))
1371 __qlcnic_up(adapter, netdev);
1372 out:
1373 netif_device_attach(netdev);
1374 }
1375
1376 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1377 u32 beacon)
1378 {
1379 struct qlcnic_cmd_args cmd;
1380 u32 mbx_in;
1381 int i, status = 0;
1382
1383 if (state) {
1384 /* Get LED configuration */
1385 qlcnic_alloc_mbx_args(&cmd, adapter,
1386 QLCNIC_CMD_GET_LED_CONFIG);
1387 status = qlcnic_issue_cmd(adapter, &cmd);
1388 if (status) {
1389 dev_err(&adapter->pdev->dev,
1390 "Get led config failed.\n");
1391 goto mbx_err;
1392 } else {
1393 for (i = 0; i < 4; i++)
1394 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1395 }
1396 qlcnic_free_mbx_args(&cmd);
1397 /* Set LED Configuration */
1398 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1399 LSW(QLC_83XX_LED_CONFIG);
1400 qlcnic_alloc_mbx_args(&cmd, adapter,
1401 QLCNIC_CMD_SET_LED_CONFIG);
1402 cmd.req.arg[1] = mbx_in;
1403 cmd.req.arg[2] = mbx_in;
1404 cmd.req.arg[3] = mbx_in;
1405 if (beacon)
1406 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1407 status = qlcnic_issue_cmd(adapter, &cmd);
1408 if (status) {
1409 dev_err(&adapter->pdev->dev,
1410 "Set led config failed.\n");
1411 }
1412 mbx_err:
1413 qlcnic_free_mbx_args(&cmd);
1414 return status;
1415
1416 } else {
1417 /* Restoring default LED configuration */
1418 qlcnic_alloc_mbx_args(&cmd, adapter,
1419 QLCNIC_CMD_SET_LED_CONFIG);
1420 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1421 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1422 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1423 if (beacon)
1424 cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1425 status = qlcnic_issue_cmd(adapter, &cmd);
1426 if (status)
1427 dev_err(&adapter->pdev->dev,
1428 "Restoring led config failed.\n");
1429 qlcnic_free_mbx_args(&cmd);
1430 return status;
1431 }
1432 }
1433
1434 int qlcnic_83xx_set_led(struct net_device *netdev,
1435 enum ethtool_phys_id_state state)
1436 {
1437 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1438 int err = -EIO, active = 1;
1439
1440 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1441 netdev_warn(netdev,
1442 "LED test is not supported in non-privileged mode\n");
1443 return -EOPNOTSUPP;
1444 }
1445
1446 switch (state) {
1447 case ETHTOOL_ID_ACTIVE:
1448 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1449 return -EBUSY;
1450
1451 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1452 break;
1453
1454 err = qlcnic_83xx_config_led(adapter, active, 0);
1455 if (err)
1456 netdev_err(netdev, "Failed to set LED blink state\n");
1457 break;
1458 case ETHTOOL_ID_INACTIVE:
1459 active = 0;
1460
1461 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1462 break;
1463
1464 err = qlcnic_83xx_config_led(adapter, active, 0);
1465 if (err)
1466 netdev_err(netdev, "Failed to reset LED blink state\n");
1467 break;
1468
1469 default:
1470 return -EINVAL;
1471 }
1472
1473 if (!active || err)
1474 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1475
1476 return err;
1477 }
1478
1479 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *adapter,
1480 int enable)
1481 {
1482 struct qlcnic_cmd_args cmd;
1483 int status;
1484
1485 if (qlcnic_sriov_vf_check(adapter))
1486 return;
1487
1488 if (enable) {
1489 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INIT_NIC_FUNC);
1490 cmd.req.arg[1] = BIT_0 | BIT_31;
1491 } else {
1492 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_STOP_NIC_FUNC);
1493 cmd.req.arg[1] = BIT_0 | BIT_31;
1494 }
1495 status = qlcnic_issue_cmd(adapter, &cmd);
1496 if (status)
1497 dev_err(&adapter->pdev->dev,
1498 "Failed to %s in NIC IDC function event.\n",
1499 (enable ? "register" : "unregister"));
1500
1501 qlcnic_free_mbx_args(&cmd);
1502 }
1503
1504 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1505 {
1506 struct qlcnic_cmd_args cmd;
1507 int err;
1508
1509 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1510 cmd.req.arg[1] = adapter->ahw->port_config;
1511 err = qlcnic_issue_cmd(adapter, &cmd);
1512 if (err)
1513 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1514 qlcnic_free_mbx_args(&cmd);
1515 return err;
1516 }
1517
1518 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1519 {
1520 struct qlcnic_cmd_args cmd;
1521 int err;
1522
1523 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1524 err = qlcnic_issue_cmd(adapter, &cmd);
1525 if (err)
1526 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1527 else
1528 adapter->ahw->port_config = cmd.rsp.arg[1];
1529 qlcnic_free_mbx_args(&cmd);
1530 return err;
1531 }
1532
1533 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1534 {
1535 int err;
1536 u32 temp;
1537 struct qlcnic_cmd_args cmd;
1538
1539 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1540 temp = adapter->recv_ctx->context_id << 16;
1541 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1542 err = qlcnic_issue_cmd(adapter, &cmd);
1543 if (err)
1544 dev_info(&adapter->pdev->dev,
1545 "Setup linkevent mailbox failed\n");
1546 qlcnic_free_mbx_args(&cmd);
1547 return err;
1548 }
1549
1550 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1551 u32 *interface_id)
1552 {
1553 if (qlcnic_sriov_pf_check(adapter)) {
1554 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1555 } else {
1556 if (!qlcnic_sriov_vf_check(adapter))
1557 *interface_id = adapter->recv_ctx->context_id << 16;
1558 }
1559 }
1560
1561 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1562 {
1563 int err;
1564 u32 temp = 0;
1565 struct qlcnic_cmd_args cmd;
1566
1567 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1568 return -EIO;
1569
1570 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1571 qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1572 cmd.req.arg[1] = (mode ? 1 : 0) | temp;
1573 err = qlcnic_issue_cmd(adapter, &cmd);
1574 if (err)
1575 dev_info(&adapter->pdev->dev,
1576 "Promiscous mode config failed\n");
1577
1578 qlcnic_free_mbx_args(&cmd);
1579 return err;
1580 }
1581
1582 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1583 {
1584 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1585 struct qlcnic_hardware_context *ahw = adapter->ahw;
1586 int ret = 0, loop = 0, max_sds_rings = adapter->max_sds_rings;
1587
1588 QLCDB(adapter, DRV, "%s loopback test in progress\n",
1589 mode == QLCNIC_ILB_MODE ? "internal" : "external");
1590 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1591 dev_warn(&adapter->pdev->dev,
1592 "Loopback test not supported for non privilege function\n");
1593 return ret;
1594 }
1595
1596 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1597 return -EBUSY;
1598
1599 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST);
1600 if (ret)
1601 goto fail_diag_alloc;
1602
1603 ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1604 if (ret)
1605 goto free_diag_res;
1606
1607 /* Poll for link up event before running traffic */
1608 do {
1609 msleep(500);
1610 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1611 qlcnic_83xx_process_aen(adapter);
1612
1613 if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
1614 dev_info(&adapter->pdev->dev,
1615 "Firmware didn't sent link up event to loopback request\n");
1616 ret = -QLCNIC_FW_NOT_RESPOND;
1617 qlcnic_83xx_clear_lb_mode(adapter, mode);
1618 goto free_diag_res;
1619 }
1620 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1621
1622 /* Make sure carrier is off and queue is stopped during loopback */
1623 if (netif_running(netdev)) {
1624 netif_carrier_off(netdev);
1625 netif_stop_queue(netdev);
1626 }
1627
1628 ret = qlcnic_do_lb_test(adapter, mode);
1629
1630 qlcnic_83xx_clear_lb_mode(adapter, mode);
1631
1632 free_diag_res:
1633 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
1634
1635 fail_diag_alloc:
1636 adapter->max_sds_rings = max_sds_rings;
1637 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1638 return ret;
1639 }
1640
1641 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1642 {
1643 struct qlcnic_hardware_context *ahw = adapter->ahw;
1644 int status = 0, loop = 0;
1645 u32 config;
1646
1647 status = qlcnic_83xx_get_port_config(adapter);
1648 if (status)
1649 return status;
1650
1651 config = ahw->port_config;
1652 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1653
1654 if (mode == QLCNIC_ILB_MODE)
1655 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1656 if (mode == QLCNIC_ELB_MODE)
1657 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1658
1659 status = qlcnic_83xx_set_port_config(adapter);
1660 if (status) {
1661 dev_err(&adapter->pdev->dev,
1662 "Failed to Set Loopback Mode = 0x%x.\n",
1663 ahw->port_config);
1664 ahw->port_config = config;
1665 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1666 return status;
1667 }
1668
1669 /* Wait for Link and IDC Completion AEN */
1670 do {
1671 msleep(300);
1672 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1673 qlcnic_83xx_process_aen(adapter);
1674
1675 if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
1676 dev_err(&adapter->pdev->dev,
1677 "FW did not generate IDC completion AEN\n");
1678 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1679 qlcnic_83xx_clear_lb_mode(adapter, mode);
1680 return -EIO;
1681 }
1682 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1683
1684 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1685 QLCNIC_MAC_ADD);
1686 return status;
1687 }
1688
1689 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1690 {
1691 struct qlcnic_hardware_context *ahw = adapter->ahw;
1692 int status = 0, loop = 0;
1693 u32 config = ahw->port_config;
1694
1695 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1696 if (mode == QLCNIC_ILB_MODE)
1697 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1698 if (mode == QLCNIC_ELB_MODE)
1699 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1700
1701 status = qlcnic_83xx_set_port_config(adapter);
1702 if (status) {
1703 dev_err(&adapter->pdev->dev,
1704 "Failed to Clear Loopback Mode = 0x%x.\n",
1705 ahw->port_config);
1706 ahw->port_config = config;
1707 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1708 return status;
1709 }
1710
1711 /* Wait for Link and IDC Completion AEN */
1712 do {
1713 msleep(300);
1714 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1715 qlcnic_83xx_process_aen(adapter);
1716
1717 if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
1718 dev_err(&adapter->pdev->dev,
1719 "Firmware didn't sent IDC completion AEN\n");
1720 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1721 return -EIO;
1722 }
1723 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1724
1725 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1726 QLCNIC_MAC_DEL);
1727 return status;
1728 }
1729
1730 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1731 u32 *interface_id)
1732 {
1733 if (qlcnic_sriov_pf_check(adapter)) {
1734 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1735 } else {
1736 if (!qlcnic_sriov_vf_check(adapter))
1737 *interface_id = adapter->recv_ctx->context_id << 16;
1738 }
1739 }
1740
1741 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1742 int mode)
1743 {
1744 int err;
1745 u32 temp = 0, temp_ip;
1746 struct qlcnic_cmd_args cmd;
1747
1748 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_IP_ADDR);
1749 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1750
1751 if (mode == QLCNIC_IP_UP)
1752 cmd.req.arg[1] = 1 | temp;
1753 else
1754 cmd.req.arg[1] = 2 | temp;
1755
1756 /*
1757 * Adapter needs IP address in network byte order.
1758 * But hardware mailbox registers go through writel(), hence IP address
1759 * gets swapped on big endian architecture.
1760 * To negate swapping of writel() on big endian architecture
1761 * use swab32(value).
1762 */
1763
1764 temp_ip = swab32(ntohl(ip));
1765 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1766 err = qlcnic_issue_cmd(adapter, &cmd);
1767 if (err != QLCNIC_RCODE_SUCCESS)
1768 dev_err(&adapter->netdev->dev,
1769 "could not notify %s IP 0x%x request\n",
1770 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1771
1772 qlcnic_free_mbx_args(&cmd);
1773 }
1774
1775 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1776 {
1777 int err;
1778 u32 temp, arg1;
1779 struct qlcnic_cmd_args cmd;
1780 int lro_bit_mask;
1781
1782 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1783
1784 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1785 return 0;
1786
1787 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1788 temp = adapter->recv_ctx->context_id << 16;
1789 arg1 = lro_bit_mask | temp;
1790 cmd.req.arg[1] = arg1;
1791
1792 err = qlcnic_issue_cmd(adapter, &cmd);
1793 if (err)
1794 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1795 qlcnic_free_mbx_args(&cmd);
1796
1797 return err;
1798 }
1799
1800 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1801 {
1802 int err;
1803 u32 word;
1804 struct qlcnic_cmd_args cmd;
1805 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1806 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1807 0x255b0ec26d5a56daULL };
1808
1809 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1810
1811 /*
1812 * RSS request:
1813 * bits 3-0: Rsvd
1814 * 5-4: hash_type_ipv4
1815 * 7-6: hash_type_ipv6
1816 * 8: enable
1817 * 9: use indirection table
1818 * 16-31: indirection table mask
1819 */
1820 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1821 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1822 ((u32)(enable & 0x1) << 8) |
1823 ((0x7ULL) << 16);
1824 cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1825 cmd.req.arg[2] = word;
1826 memcpy(&cmd.req.arg[4], key, sizeof(key));
1827
1828 err = qlcnic_issue_cmd(adapter, &cmd);
1829
1830 if (err)
1831 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1832 qlcnic_free_mbx_args(&cmd);
1833
1834 return err;
1835
1836 }
1837
1838 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1839 u32 *interface_id)
1840 {
1841 if (qlcnic_sriov_pf_check(adapter)) {
1842 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1843 } else {
1844 if (!qlcnic_sriov_vf_check(adapter))
1845 *interface_id = adapter->recv_ctx->context_id << 16;
1846 }
1847 }
1848
1849 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
1850 u16 vlan_id, u8 op)
1851 {
1852 int err;
1853 u32 *buf, temp = 0;
1854 struct qlcnic_cmd_args cmd;
1855 struct qlcnic_macvlan_mbx mv;
1856
1857 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1858 return -EIO;
1859
1860 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
1861 if (err)
1862 return err;
1863
1864 if (vlan_id)
1865 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
1866 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
1867
1868 cmd.req.arg[1] = op | (1 << 8);
1869 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
1870 cmd.req.arg[1] |= temp;
1871 mv.vlan = vlan_id;
1872 mv.mac_addr0 = addr[0];
1873 mv.mac_addr1 = addr[1];
1874 mv.mac_addr2 = addr[2];
1875 mv.mac_addr3 = addr[3];
1876 mv.mac_addr4 = addr[4];
1877 mv.mac_addr5 = addr[5];
1878 buf = &cmd.req.arg[2];
1879 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
1880 err = qlcnic_issue_cmd(adapter, &cmd);
1881 if (err)
1882 dev_err(&adapter->pdev->dev,
1883 "MAC-VLAN %s to CAM failed, err=%d.\n",
1884 ((op == 1) ? "add " : "delete "), err);
1885 qlcnic_free_mbx_args(&cmd);
1886 return err;
1887 }
1888
1889 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
1890 u16 vlan_id)
1891 {
1892 u8 mac[ETH_ALEN];
1893 memcpy(&mac, addr, ETH_ALEN);
1894 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
1895 }
1896
1897 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
1898 u8 type, struct qlcnic_cmd_args *cmd)
1899 {
1900 switch (type) {
1901 case QLCNIC_SET_STATION_MAC:
1902 case QLCNIC_SET_FAC_DEF_MAC:
1903 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
1904 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
1905 break;
1906 }
1907 cmd->req.arg[1] = type;
1908 }
1909
1910 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
1911 {
1912 int err, i;
1913 struct qlcnic_cmd_args cmd;
1914 u32 mac_low, mac_high;
1915
1916 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
1917 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
1918 err = qlcnic_issue_cmd(adapter, &cmd);
1919
1920 if (err == QLCNIC_RCODE_SUCCESS) {
1921 mac_low = cmd.rsp.arg[1];
1922 mac_high = cmd.rsp.arg[2];
1923
1924 for (i = 0; i < 2; i++)
1925 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
1926 for (i = 2; i < 6; i++)
1927 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
1928 } else {
1929 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
1930 err);
1931 err = -EIO;
1932 }
1933 qlcnic_free_mbx_args(&cmd);
1934 return err;
1935 }
1936
1937 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
1938 {
1939 int err;
1940 u16 temp;
1941 struct qlcnic_cmd_args cmd;
1942 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
1943
1944 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1945 return;
1946
1947 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
1948 if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
1949 temp = adapter->recv_ctx->context_id;
1950 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
1951 temp = coal->rx_time_us;
1952 cmd.req.arg[2] = coal->rx_packets | temp << 16;
1953 } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
1954 temp = adapter->tx_ring->ctx_id;
1955 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
1956 temp = coal->tx_time_us;
1957 cmd.req.arg[2] = coal->tx_packets | temp << 16;
1958 }
1959 cmd.req.arg[3] = coal->flag;
1960 err = qlcnic_issue_cmd(adapter, &cmd);
1961 if (err != QLCNIC_RCODE_SUCCESS)
1962 dev_info(&adapter->pdev->dev,
1963 "Failed to send interrupt coalescence parameters\n");
1964 qlcnic_free_mbx_args(&cmd);
1965 }
1966
1967 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
1968 u32 data[])
1969 {
1970 u8 link_status, duplex;
1971 /* link speed */
1972 link_status = LSB(data[3]) & 1;
1973 adapter->ahw->link_speed = MSW(data[2]);
1974 adapter->ahw->link_autoneg = MSB(MSW(data[3]));
1975 adapter->ahw->module_type = MSB(LSW(data[3]));
1976 duplex = LSB(MSW(data[3]));
1977 if (duplex)
1978 adapter->ahw->link_duplex = DUPLEX_FULL;
1979 else
1980 adapter->ahw->link_duplex = DUPLEX_HALF;
1981 adapter->ahw->has_link_events = 1;
1982 qlcnic_advert_link_change(adapter, link_status);
1983 }
1984
1985 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
1986 {
1987 struct qlcnic_adapter *adapter = data;
1988 unsigned long flags;
1989 u32 mask, resp, event;
1990
1991 spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
1992 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
1993 if (!(resp & QLCNIC_SET_OWNER))
1994 goto out;
1995
1996 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
1997 if (event & QLCNIC_MBX_ASYNC_EVENT)
1998 __qlcnic_83xx_process_aen(adapter);
1999 out:
2000 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2001 writel(0, adapter->ahw->pci_base0 + mask);
2002 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
2003
2004 return IRQ_HANDLED;
2005 }
2006
2007 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
2008 {
2009 int err = -EIO;
2010 struct qlcnic_cmd_args cmd;
2011
2012 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2013 dev_err(&adapter->pdev->dev,
2014 "%s: Error, invoked by non management func\n",
2015 __func__);
2016 return err;
2017 }
2018
2019 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
2020 cmd.req.arg[1] = (port & 0xf) | BIT_4;
2021 err = qlcnic_issue_cmd(adapter, &cmd);
2022
2023 if (err != QLCNIC_RCODE_SUCCESS) {
2024 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
2025 err);
2026 err = -EIO;
2027 }
2028 qlcnic_free_mbx_args(&cmd);
2029
2030 return err;
2031
2032 }
2033
2034 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2035 struct qlcnic_info *nic)
2036 {
2037 int i, err = -EIO;
2038 struct qlcnic_cmd_args cmd;
2039
2040 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2041 dev_err(&adapter->pdev->dev,
2042 "%s: Error, invoked by non management func\n",
2043 __func__);
2044 return err;
2045 }
2046
2047 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2048 cmd.req.arg[1] = (nic->pci_func << 16);
2049 cmd.req.arg[2] = 0x1 << 16;
2050 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2051 cmd.req.arg[4] = nic->capabilities;
2052 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2053 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2054 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2055 for (i = 8; i < 32; i++)
2056 cmd.req.arg[i] = 0;
2057
2058 err = qlcnic_issue_cmd(adapter, &cmd);
2059
2060 if (err != QLCNIC_RCODE_SUCCESS) {
2061 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2062 err);
2063 err = -EIO;
2064 }
2065
2066 qlcnic_free_mbx_args(&cmd);
2067
2068 return err;
2069 }
2070
2071 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2072 struct qlcnic_info *npar_info, u8 func_id)
2073 {
2074 int err;
2075 u32 temp;
2076 u8 op = 0;
2077 struct qlcnic_cmd_args cmd;
2078
2079 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2080 if (func_id != adapter->ahw->pci_func) {
2081 temp = func_id << 16;
2082 cmd.req.arg[1] = op | BIT_31 | temp;
2083 } else {
2084 cmd.req.arg[1] = adapter->ahw->pci_func << 16;
2085 }
2086 err = qlcnic_issue_cmd(adapter, &cmd);
2087 if (err) {
2088 dev_info(&adapter->pdev->dev,
2089 "Failed to get nic info %d\n", err);
2090 goto out;
2091 }
2092
2093 npar_info->op_type = cmd.rsp.arg[1];
2094 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2095 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2096 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2097 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2098 npar_info->capabilities = cmd.rsp.arg[4];
2099 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2100 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2101 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2102 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2103 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2104 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2105 if (cmd.rsp.arg[8] & 0x1)
2106 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2107 if (cmd.rsp.arg[8] & 0x10000) {
2108 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2109 npar_info->max_linkspeed_reg_offset = temp;
2110 }
2111
2112 out:
2113 qlcnic_free_mbx_args(&cmd);
2114 return err;
2115 }
2116
2117 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2118 struct qlcnic_pci_info *pci_info)
2119 {
2120 int i, err = 0, j = 0;
2121 u32 temp;
2122 struct qlcnic_cmd_args cmd;
2123
2124 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2125 err = qlcnic_issue_cmd(adapter, &cmd);
2126
2127 adapter->ahw->act_pci_func = 0;
2128 if (err == QLCNIC_RCODE_SUCCESS) {
2129 pci_info->func_count = cmd.rsp.arg[1] & 0xFF;
2130 dev_info(&adapter->pdev->dev,
2131 "%s: total functions = %d\n",
2132 __func__, pci_info->func_count);
2133 for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) {
2134 pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2135 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2136 i++;
2137 pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2138 if (pci_info->type == QLCNIC_TYPE_NIC)
2139 adapter->ahw->act_pci_func++;
2140 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2141 pci_info->default_port = temp;
2142 i++;
2143 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2144 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2145 pci_info->tx_max_bw = temp;
2146 i = i + 2;
2147 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2148 i++;
2149 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2150 i = i + 3;
2151
2152 dev_info(&adapter->pdev->dev, "%s:\n"
2153 "\tid = %d active = %d type = %d\n"
2154 "\tport = %d min bw = %d max bw = %d\n"
2155 "\tmac_addr = %pM\n", __func__,
2156 pci_info->id, pci_info->active, pci_info->type,
2157 pci_info->default_port, pci_info->tx_min_bw,
2158 pci_info->tx_max_bw, pci_info->mac);
2159 }
2160 } else {
2161 dev_err(&adapter->pdev->dev, "Failed to get PCI Info%d\n",
2162 err);
2163 err = -EIO;
2164 }
2165
2166 qlcnic_free_mbx_args(&cmd);
2167
2168 return err;
2169 }
2170
2171 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2172 {
2173 int i, index, err;
2174 u8 max_ints;
2175 u32 val, temp, type;
2176 struct qlcnic_cmd_args cmd;
2177
2178 max_ints = adapter->ahw->num_msix - 1;
2179 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2180 cmd.req.arg[1] = max_ints;
2181
2182 if (qlcnic_sriov_vf_check(adapter))
2183 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2184
2185 for (i = 0, index = 2; i < max_ints; i++) {
2186 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2187 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2188 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2189 val |= (adapter->ahw->intr_tbl[i].id << 16);
2190 cmd.req.arg[index++] = val;
2191 }
2192 err = qlcnic_issue_cmd(adapter, &cmd);
2193 if (err) {
2194 dev_err(&adapter->pdev->dev,
2195 "Failed to configure interrupts 0x%x\n", err);
2196 goto out;
2197 }
2198
2199 max_ints = cmd.rsp.arg[1];
2200 for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2201 val = cmd.rsp.arg[index];
2202 if (LSB(val)) {
2203 dev_info(&adapter->pdev->dev,
2204 "Can't configure interrupt %d\n",
2205 adapter->ahw->intr_tbl[i].id);
2206 continue;
2207 }
2208 if (op_type) {
2209 adapter->ahw->intr_tbl[i].id = MSW(val);
2210 adapter->ahw->intr_tbl[i].enabled = 1;
2211 temp = cmd.rsp.arg[index + 1];
2212 adapter->ahw->intr_tbl[i].src = temp;
2213 } else {
2214 adapter->ahw->intr_tbl[i].id = i;
2215 adapter->ahw->intr_tbl[i].enabled = 0;
2216 adapter->ahw->intr_tbl[i].src = 0;
2217 }
2218 }
2219 out:
2220 qlcnic_free_mbx_args(&cmd);
2221 return err;
2222 }
2223
2224 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2225 {
2226 int id, timeout = 0;
2227 u32 status = 0;
2228
2229 while (status == 0) {
2230 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2231 if (status)
2232 break;
2233
2234 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2235 id = QLC_SHARED_REG_RD32(adapter,
2236 QLCNIC_FLASH_LOCK_OWNER);
2237 dev_err(&adapter->pdev->dev,
2238 "%s: failed, lock held by %d\n", __func__, id);
2239 return -EIO;
2240 }
2241 usleep_range(1000, 2000);
2242 }
2243
2244 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2245 return 0;
2246 }
2247
2248 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2249 {
2250 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2251 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2252 }
2253
2254 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2255 u32 flash_addr, u8 *p_data,
2256 int count)
2257 {
2258 int i, ret;
2259 u32 word, range, flash_offset, addr = flash_addr;
2260 ulong indirect_add, direct_window;
2261
2262 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2263 if (addr & 0x3) {
2264 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2265 return -EIO;
2266 }
2267
2268 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2269 (addr));
2270
2271 range = flash_offset + (count * sizeof(u32));
2272 /* Check if data is spread across multiple sectors */
2273 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2274
2275 /* Multi sector read */
2276 for (i = 0; i < count; i++) {
2277 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2278 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2279 indirect_add);
2280 if (ret == -EIO)
2281 return -EIO;
2282
2283 word = ret;
2284 *(u32 *)p_data = word;
2285 p_data = p_data + 4;
2286 addr = addr + 4;
2287 flash_offset = flash_offset + 4;
2288
2289 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2290 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2291 /* This write is needed once for each sector */
2292 qlcnic_83xx_wrt_reg_indirect(adapter,
2293 direct_window,
2294 (addr));
2295 flash_offset = 0;
2296 }
2297 }
2298 } else {
2299 /* Single sector read */
2300 for (i = 0; i < count; i++) {
2301 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2302 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2303 indirect_add);
2304 if (ret == -EIO)
2305 return -EIO;
2306
2307 word = ret;
2308 *(u32 *)p_data = word;
2309 p_data = p_data + 4;
2310 addr = addr + 4;
2311 }
2312 }
2313
2314 return 0;
2315 }
2316
2317 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2318 {
2319 u32 status;
2320 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2321
2322 do {
2323 status = qlcnic_83xx_rd_reg_indirect(adapter,
2324 QLC_83XX_FLASH_STATUS);
2325 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2326 QLC_83XX_FLASH_STATUS_READY)
2327 break;
2328
2329 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2330 } while (--retries);
2331
2332 if (!retries)
2333 return -EIO;
2334
2335 return 0;
2336 }
2337
2338 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2339 {
2340 int ret;
2341 u32 cmd;
2342 cmd = adapter->ahw->fdt.write_statusreg_cmd;
2343 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2344 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2345 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2346 adapter->ahw->fdt.write_enable_bits);
2347 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2348 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2349 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2350 if (ret)
2351 return -EIO;
2352
2353 return 0;
2354 }
2355
2356 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2357 {
2358 int ret;
2359
2360 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2361 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2362 adapter->ahw->fdt.write_statusreg_cmd));
2363 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2364 adapter->ahw->fdt.write_disable_bits);
2365 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2366 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2367 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2368 if (ret)
2369 return -EIO;
2370
2371 return 0;
2372 }
2373
2374 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2375 {
2376 int ret, mfg_id;
2377
2378 if (qlcnic_83xx_lock_flash(adapter))
2379 return -EIO;
2380
2381 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2382 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2383 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2384 QLC_83XX_FLASH_READ_CTRL);
2385 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2386 if (ret) {
2387 qlcnic_83xx_unlock_flash(adapter);
2388 return -EIO;
2389 }
2390
2391 mfg_id = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
2392 if (mfg_id == -EIO)
2393 return -EIO;
2394
2395 adapter->flash_mfg_id = (mfg_id & 0xFF);
2396 qlcnic_83xx_unlock_flash(adapter);
2397
2398 return 0;
2399 }
2400
2401 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2402 {
2403 int count, fdt_size, ret = 0;
2404
2405 fdt_size = sizeof(struct qlcnic_fdt);
2406 count = fdt_size / sizeof(u32);
2407
2408 if (qlcnic_83xx_lock_flash(adapter))
2409 return -EIO;
2410
2411 memset(&adapter->ahw->fdt, 0, fdt_size);
2412 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2413 (u8 *)&adapter->ahw->fdt,
2414 count);
2415
2416 qlcnic_83xx_unlock_flash(adapter);
2417 return ret;
2418 }
2419
2420 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2421 u32 sector_start_addr)
2422 {
2423 u32 reversed_addr, addr1, addr2, cmd;
2424 int ret = -EIO;
2425
2426 if (qlcnic_83xx_lock_flash(adapter) != 0)
2427 return -EIO;
2428
2429 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2430 ret = qlcnic_83xx_enable_flash_write(adapter);
2431 if (ret) {
2432 qlcnic_83xx_unlock_flash(adapter);
2433 dev_err(&adapter->pdev->dev,
2434 "%s failed at %d\n",
2435 __func__, __LINE__);
2436 return ret;
2437 }
2438 }
2439
2440 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2441 if (ret) {
2442 qlcnic_83xx_unlock_flash(adapter);
2443 dev_err(&adapter->pdev->dev,
2444 "%s: failed at %d\n", __func__, __LINE__);
2445 return -EIO;
2446 }
2447
2448 addr1 = (sector_start_addr & 0xFF) << 16;
2449 addr2 = (sector_start_addr & 0xFF0000) >> 16;
2450 reversed_addr = addr1 | addr2;
2451
2452 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2453 reversed_addr);
2454 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2455 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2456 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2457 else
2458 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2459 QLC_83XX_FLASH_OEM_ERASE_SIG);
2460 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2461 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2462
2463 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2464 if (ret) {
2465 qlcnic_83xx_unlock_flash(adapter);
2466 dev_err(&adapter->pdev->dev,
2467 "%s: failed at %d\n", __func__, __LINE__);
2468 return -EIO;
2469 }
2470
2471 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2472 ret = qlcnic_83xx_disable_flash_write(adapter);
2473 if (ret) {
2474 qlcnic_83xx_unlock_flash(adapter);
2475 dev_err(&adapter->pdev->dev,
2476 "%s: failed at %d\n", __func__, __LINE__);
2477 return ret;
2478 }
2479 }
2480
2481 qlcnic_83xx_unlock_flash(adapter);
2482
2483 return 0;
2484 }
2485
2486 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2487 u32 *p_data)
2488 {
2489 int ret = -EIO;
2490 u32 addr1 = 0x00800000 | (addr >> 2);
2491
2492 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2493 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2494 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2495 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2496 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2497 if (ret) {
2498 dev_err(&adapter->pdev->dev,
2499 "%s: failed at %d\n", __func__, __LINE__);
2500 return -EIO;
2501 }
2502
2503 return 0;
2504 }
2505
2506 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2507 u32 *p_data, int count)
2508 {
2509 u32 temp;
2510 int ret = -EIO;
2511
2512 if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2513 (count > QLC_83XX_FLASH_WRITE_MAX)) {
2514 dev_err(&adapter->pdev->dev,
2515 "%s: Invalid word count\n", __func__);
2516 return -EIO;
2517 }
2518
2519 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2520 QLC_83XX_FLASH_SPI_CONTROL);
2521 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2522 (temp | QLC_83XX_FLASH_SPI_CTRL));
2523 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2524 QLC_83XX_FLASH_ADDR_TEMP_VAL);
2525
2526 /* First DWORD write */
2527 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2528 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2529 QLC_83XX_FLASH_FIRST_MS_PATTERN);
2530 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2531 if (ret) {
2532 dev_err(&adapter->pdev->dev,
2533 "%s: failed at %d\n", __func__, __LINE__);
2534 return -EIO;
2535 }
2536
2537 count--;
2538 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2539 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2540 /* Second to N-1 DWORD writes */
2541 while (count != 1) {
2542 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2543 *p_data++);
2544 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2545 QLC_83XX_FLASH_SECOND_MS_PATTERN);
2546 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2547 if (ret) {
2548 dev_err(&adapter->pdev->dev,
2549 "%s: failed at %d\n", __func__, __LINE__);
2550 return -EIO;
2551 }
2552 count--;
2553 }
2554
2555 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2556 QLC_83XX_FLASH_ADDR_TEMP_VAL |
2557 (addr >> 2));
2558 /* Last DWORD write */
2559 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2560 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2561 QLC_83XX_FLASH_LAST_MS_PATTERN);
2562 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2563 if (ret) {
2564 dev_err(&adapter->pdev->dev,
2565 "%s: failed at %d\n", __func__, __LINE__);
2566 return -EIO;
2567 }
2568
2569 ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_SPI_STATUS);
2570 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2571 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2572 __func__, __LINE__);
2573 /* Operation failed, clear error bit */
2574 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2575 QLC_83XX_FLASH_SPI_CONTROL);
2576 qlcnic_83xx_wrt_reg_indirect(adapter,
2577 QLC_83XX_FLASH_SPI_CONTROL,
2578 (temp | QLC_83XX_FLASH_SPI_CTRL));
2579 }
2580
2581 return 0;
2582 }
2583
2584 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2585 {
2586 u32 val, id;
2587
2588 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2589
2590 /* Check if recovery need to be performed by the calling function */
2591 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2592 val = val & ~0x3F;
2593 val = val | ((adapter->portnum << 2) |
2594 QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2595 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2596 dev_info(&adapter->pdev->dev,
2597 "%s: lock recovery initiated\n", __func__);
2598 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2599 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2600 id = ((val >> 2) & 0xF);
2601 if (id == adapter->portnum) {
2602 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2603 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2604 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2605 /* Force release the lock */
2606 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2607 /* Clear recovery bits */
2608 val = val & ~0x3F;
2609 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2610 dev_info(&adapter->pdev->dev,
2611 "%s: lock recovery completed\n", __func__);
2612 } else {
2613 dev_info(&adapter->pdev->dev,
2614 "%s: func %d to resume lock recovery process\n",
2615 __func__, id);
2616 }
2617 } else {
2618 dev_info(&adapter->pdev->dev,
2619 "%s: lock recovery initiated by other functions\n",
2620 __func__);
2621 }
2622 }
2623
2624 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2625 {
2626 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2627 int max_attempt = 0;
2628
2629 while (status == 0) {
2630 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2631 if (status)
2632 break;
2633
2634 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2635 i++;
2636
2637 if (i == 1)
2638 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2639
2640 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2641 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2642 if (val == temp) {
2643 id = val & 0xFF;
2644 dev_info(&adapter->pdev->dev,
2645 "%s: lock to be recovered from %d\n",
2646 __func__, id);
2647 qlcnic_83xx_recover_driver_lock(adapter);
2648 i = 0;
2649 max_attempt++;
2650 } else {
2651 dev_err(&adapter->pdev->dev,
2652 "%s: failed to get lock\n", __func__);
2653 return -EIO;
2654 }
2655 }
2656
2657 /* Force exit from while loop after few attempts */
2658 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2659 dev_err(&adapter->pdev->dev,
2660 "%s: failed to get lock\n", __func__);
2661 return -EIO;
2662 }
2663 }
2664
2665 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2666 lock_alive_counter = val >> 8;
2667 lock_alive_counter++;
2668 val = lock_alive_counter << 8 | adapter->portnum;
2669 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2670
2671 return 0;
2672 }
2673
2674 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2675 {
2676 u32 val, lock_alive_counter, id;
2677
2678 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2679 id = val & 0xFF;
2680 lock_alive_counter = val >> 8;
2681
2682 if (id != adapter->portnum)
2683 dev_err(&adapter->pdev->dev,
2684 "%s:Warning func %d is unlocking lock owned by %d\n",
2685 __func__, adapter->portnum, id);
2686
2687 val = (lock_alive_counter << 8) | 0xFF;
2688 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2689 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2690 }
2691
2692 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2693 u32 *data, u32 count)
2694 {
2695 int i, j, ret = 0;
2696 u32 temp;
2697
2698 /* Check alignment */
2699 if (addr & 0xF)
2700 return -EIO;
2701
2702 mutex_lock(&adapter->ahw->mem_lock);
2703 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2704
2705 for (i = 0; i < count; i++, addr += 16) {
2706 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2707 QLCNIC_ADDR_QDR_NET_MAX)) ||
2708 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2709 QLCNIC_ADDR_DDR_NET_MAX)))) {
2710 mutex_unlock(&adapter->ahw->mem_lock);
2711 return -EIO;
2712 }
2713
2714 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2715 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2716 *data++);
2717 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2718 *data++);
2719 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2720 *data++);
2721 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2722 *data++);
2723 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2724 QLCNIC_TA_WRITE_ENABLE);
2725 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2726 QLCNIC_TA_WRITE_START);
2727
2728 for (j = 0; j < MAX_CTL_CHECK; j++) {
2729 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2730 QLCNIC_MS_CTRL);
2731 if ((temp & TA_CTL_BUSY) == 0)
2732 break;
2733 }
2734
2735 /* Status check failure */
2736 if (j >= MAX_CTL_CHECK) {
2737 printk_ratelimited(KERN_WARNING
2738 "MS memory write failed\n");
2739 mutex_unlock(&adapter->ahw->mem_lock);
2740 return -EIO;
2741 }
2742 }
2743
2744 mutex_unlock(&adapter->ahw->mem_lock);
2745
2746 return ret;
2747 }
2748
2749 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2750 u8 *p_data, int count)
2751 {
2752 int i, ret;
2753 u32 word, addr = flash_addr;
2754 ulong indirect_addr;
2755
2756 if (qlcnic_83xx_lock_flash(adapter) != 0)
2757 return -EIO;
2758
2759 if (addr & 0x3) {
2760 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2761 qlcnic_83xx_unlock_flash(adapter);
2762 return -EIO;
2763 }
2764
2765 for (i = 0; i < count; i++) {
2766 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2767 QLC_83XX_FLASH_DIRECT_WINDOW,
2768 (addr))) {
2769 qlcnic_83xx_unlock_flash(adapter);
2770 return -EIO;
2771 }
2772
2773 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2774 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2775 indirect_addr);
2776 if (ret == -EIO)
2777 return -EIO;
2778 word = ret;
2779 *(u32 *)p_data = word;
2780 p_data = p_data + 4;
2781 addr = addr + 4;
2782 }
2783
2784 qlcnic_83xx_unlock_flash(adapter);
2785
2786 return 0;
2787 }
2788
2789 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2790 {
2791 u8 pci_func;
2792 int err;
2793 u32 config = 0, state;
2794 struct qlcnic_cmd_args cmd;
2795 struct qlcnic_hardware_context *ahw = adapter->ahw;
2796
2797 if (qlcnic_sriov_vf_check(adapter))
2798 pci_func = adapter->portnum;
2799 else
2800 pci_func = ahw->pci_func;
2801
2802 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
2803 if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
2804 dev_info(&adapter->pdev->dev, "link state down\n");
2805 return config;
2806 }
2807 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
2808 err = qlcnic_issue_cmd(adapter, &cmd);
2809 if (err) {
2810 dev_info(&adapter->pdev->dev,
2811 "Get Link Status Command failed: 0x%x\n", err);
2812 goto out;
2813 } else {
2814 config = cmd.rsp.arg[1];
2815 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
2816 case QLC_83XX_10M_LINK:
2817 ahw->link_speed = SPEED_10;
2818 break;
2819 case QLC_83XX_100M_LINK:
2820 ahw->link_speed = SPEED_100;
2821 break;
2822 case QLC_83XX_1G_LINK:
2823 ahw->link_speed = SPEED_1000;
2824 break;
2825 case QLC_83XX_10G_LINK:
2826 ahw->link_speed = SPEED_10000;
2827 break;
2828 default:
2829 ahw->link_speed = 0;
2830 break;
2831 }
2832 config = cmd.rsp.arg[3];
2833 if (config & 1)
2834 err = 1;
2835 }
2836 out:
2837 qlcnic_free_mbx_args(&cmd);
2838 return config;
2839 }
2840
2841 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter)
2842 {
2843 u32 config = 0;
2844 int status = 0;
2845 struct qlcnic_hardware_context *ahw = adapter->ahw;
2846
2847 /* Get port configuration info */
2848 status = qlcnic_83xx_get_port_info(adapter);
2849 /* Get Link Status related info */
2850 config = qlcnic_83xx_test_link(adapter);
2851 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
2852 /* hard code until there is a way to get it from flash */
2853 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
2854 return status;
2855 }
2856
2857 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
2858 struct ethtool_cmd *ecmd)
2859 {
2860 int status = 0;
2861 u32 config = adapter->ahw->port_config;
2862
2863 if (ecmd->autoneg)
2864 adapter->ahw->port_config |= BIT_15;
2865
2866 switch (ethtool_cmd_speed(ecmd)) {
2867 case SPEED_10:
2868 adapter->ahw->port_config |= BIT_8;
2869 break;
2870 case SPEED_100:
2871 adapter->ahw->port_config |= BIT_9;
2872 break;
2873 case SPEED_1000:
2874 adapter->ahw->port_config |= BIT_10;
2875 break;
2876 case SPEED_10000:
2877 adapter->ahw->port_config |= BIT_11;
2878 break;
2879 default:
2880 return -EINVAL;
2881 }
2882
2883 status = qlcnic_83xx_set_port_config(adapter);
2884 if (status) {
2885 dev_info(&adapter->pdev->dev,
2886 "Faild to Set Link Speed and autoneg.\n");
2887 adapter->ahw->port_config = config;
2888 }
2889 return status;
2890 }
2891
2892 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
2893 u64 *data, int index)
2894 {
2895 u32 low, hi;
2896 u64 val;
2897
2898 low = cmd->rsp.arg[index];
2899 hi = cmd->rsp.arg[index + 1];
2900 val = (((u64) low) | (((u64) hi) << 32));
2901 *data++ = val;
2902 return data;
2903 }
2904
2905 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
2906 struct qlcnic_cmd_args *cmd, u64 *data,
2907 int type, int *ret)
2908 {
2909 int err, k, total_regs;
2910
2911 *ret = 0;
2912 err = qlcnic_issue_cmd(adapter, cmd);
2913 if (err != QLCNIC_RCODE_SUCCESS) {
2914 dev_info(&adapter->pdev->dev,
2915 "Error in get statistics mailbox command\n");
2916 *ret = -EIO;
2917 return data;
2918 }
2919 total_regs = cmd->rsp.num;
2920 switch (type) {
2921 case QLC_83XX_STAT_MAC:
2922 /* fill in MAC tx counters */
2923 for (k = 2; k < 28; k += 2)
2924 data = qlcnic_83xx_copy_stats(cmd, data, k);
2925 /* skip 24 bytes of reserved area */
2926 /* fill in MAC rx counters */
2927 for (k += 6; k < 60; k += 2)
2928 data = qlcnic_83xx_copy_stats(cmd, data, k);
2929 /* skip 24 bytes of reserved area */
2930 /* fill in MAC rx frame stats */
2931 for (k += 6; k < 80; k += 2)
2932 data = qlcnic_83xx_copy_stats(cmd, data, k);
2933 /* fill in eSwitch stats */
2934 for (; k < total_regs; k += 2)
2935 data = qlcnic_83xx_copy_stats(cmd, data, k);
2936 break;
2937 case QLC_83XX_STAT_RX:
2938 for (k = 2; k < 8; k += 2)
2939 data = qlcnic_83xx_copy_stats(cmd, data, k);
2940 /* skip 8 bytes of reserved data */
2941 for (k += 2; k < 24; k += 2)
2942 data = qlcnic_83xx_copy_stats(cmd, data, k);
2943 /* skip 8 bytes containing RE1FBQ error data */
2944 for (k += 2; k < total_regs; k += 2)
2945 data = qlcnic_83xx_copy_stats(cmd, data, k);
2946 break;
2947 case QLC_83XX_STAT_TX:
2948 for (k = 2; k < 10; k += 2)
2949 data = qlcnic_83xx_copy_stats(cmd, data, k);
2950 /* skip 8 bytes of reserved data */
2951 for (k += 2; k < total_regs; k += 2)
2952 data = qlcnic_83xx_copy_stats(cmd, data, k);
2953 break;
2954 default:
2955 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
2956 *ret = -EIO;
2957 }
2958 return data;
2959 }
2960
2961 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
2962 {
2963 struct qlcnic_cmd_args cmd;
2964 struct net_device *netdev = adapter->netdev;
2965 int ret = 0;
2966
2967 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
2968 /* Get Tx stats */
2969 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
2970 cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
2971 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
2972 QLC_83XX_STAT_TX, &ret);
2973 if (ret) {
2974 netdev_err(netdev, "Error getting Tx stats\n");
2975 goto out;
2976 }
2977 /* Get MAC stats */
2978 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
2979 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
2980 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
2981 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
2982 QLC_83XX_STAT_MAC, &ret);
2983 if (ret) {
2984 netdev_err(netdev, "Error getting MAC stats\n");
2985 goto out;
2986 }
2987 /* Get Rx stats */
2988 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
2989 cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
2990 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
2991 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
2992 QLC_83XX_STAT_RX, &ret);
2993 if (ret)
2994 netdev_err(netdev, "Error getting Rx stats\n");
2995 out:
2996 qlcnic_free_mbx_args(&cmd);
2997 }
2998
2999 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3000 {
3001 u32 major, minor, sub;
3002
3003 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3004 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3005 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3006
3007 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3008 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3009 __func__);
3010 return 1;
3011 }
3012 return 0;
3013 }
3014
3015 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3016 {
3017 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3018 sizeof(adapter->ahw->ext_reg_tbl)) +
3019 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) +
3020 sizeof(adapter->ahw->reg_tbl));
3021 }
3022
3023 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3024 {
3025 int i, j = 0;
3026
3027 for (i = QLCNIC_DEV_INFO_SIZE + 1;
3028 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3029 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3030
3031 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3032 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3033 return i;
3034 }
3035
3036 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3037 {
3038 struct qlcnic_adapter *adapter = netdev_priv(netdev);
3039 struct qlcnic_hardware_context *ahw = adapter->ahw;
3040 struct qlcnic_cmd_args cmd;
3041 u32 data;
3042 u16 intrpt_id, id;
3043 u8 val;
3044 int ret, max_sds_rings = adapter->max_sds_rings;
3045
3046 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
3047 return -EIO;
3048
3049 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST);
3050 if (ret)
3051 goto fail_diag_irq;
3052
3053 ahw->diag_cnt = 0;
3054 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3055
3056 if (adapter->flags & QLCNIC_MSIX_ENABLED)
3057 intrpt_id = ahw->intr_tbl[0].id;
3058 else
3059 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3060
3061 cmd.req.arg[1] = 1;
3062 cmd.req.arg[2] = intrpt_id;
3063 cmd.req.arg[3] = BIT_0;
3064
3065 ret = qlcnic_issue_cmd(adapter, &cmd);
3066 data = cmd.rsp.arg[2];
3067 id = LSW(data);
3068 val = LSB(MSW(data));
3069 if (id != intrpt_id)
3070 dev_info(&adapter->pdev->dev,
3071 "Interrupt generated: 0x%x, requested:0x%x\n",
3072 id, intrpt_id);
3073 if (val)
3074 dev_err(&adapter->pdev->dev,
3075 "Interrupt test error: 0x%x\n", val);
3076 if (ret)
3077 goto done;
3078
3079 msleep(20);
3080 ret = !ahw->diag_cnt;
3081
3082 done:
3083 qlcnic_free_mbx_args(&cmd);
3084 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
3085
3086 fail_diag_irq:
3087 adapter->max_sds_rings = max_sds_rings;
3088 clear_bit(__QLCNIC_RESETTING, &adapter->state);
3089 return ret;
3090 }
3091
3092 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3093 struct ethtool_pauseparam *pause)
3094 {
3095 struct qlcnic_hardware_context *ahw = adapter->ahw;
3096 int status = 0;
3097 u32 config;
3098
3099 status = qlcnic_83xx_get_port_config(adapter);
3100 if (status) {
3101 dev_err(&adapter->pdev->dev,
3102 "%s: Get Pause Config failed\n", __func__);
3103 return;
3104 }
3105 config = ahw->port_config;
3106 if (config & QLC_83XX_CFG_STD_PAUSE) {
3107 if (config & QLC_83XX_CFG_STD_TX_PAUSE)
3108 pause->tx_pause = 1;
3109 if (config & QLC_83XX_CFG_STD_RX_PAUSE)
3110 pause->rx_pause = 1;
3111 }
3112
3113 if (QLC_83XX_AUTONEG(config))
3114 pause->autoneg = 1;
3115 }
3116
3117 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3118 struct ethtool_pauseparam *pause)
3119 {
3120 struct qlcnic_hardware_context *ahw = adapter->ahw;
3121 int status = 0;
3122 u32 config;
3123
3124 status = qlcnic_83xx_get_port_config(adapter);
3125 if (status) {
3126 dev_err(&adapter->pdev->dev,
3127 "%s: Get Pause Config failed.\n", __func__);
3128 return status;
3129 }
3130 config = ahw->port_config;
3131
3132 if (ahw->port_type == QLCNIC_GBE) {
3133 if (pause->autoneg)
3134 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3135 if (!pause->autoneg)
3136 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3137 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3138 return -EOPNOTSUPP;
3139 }
3140
3141 if (!(config & QLC_83XX_CFG_STD_PAUSE))
3142 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3143
3144 if (pause->rx_pause && pause->tx_pause) {
3145 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3146 } else if (pause->rx_pause && !pause->tx_pause) {
3147 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3148 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3149 } else if (pause->tx_pause && !pause->rx_pause) {
3150 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3151 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3152 } else if (!pause->rx_pause && !pause->tx_pause) {
3153 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_RX_PAUSE;
3154 }
3155 status = qlcnic_83xx_set_port_config(adapter);
3156 if (status) {
3157 dev_err(&adapter->pdev->dev,
3158 "%s: Set Pause Config failed.\n", __func__);
3159 ahw->port_config = config;
3160 }
3161 return status;
3162 }
3163
3164 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3165 {
3166 int ret;
3167
3168 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3169 QLC_83XX_FLASH_OEM_READ_SIG);
3170 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3171 QLC_83XX_FLASH_READ_CTRL);
3172 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3173 if (ret)
3174 return -EIO;
3175
3176 ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
3177 return ret & 0xFF;
3178 }
3179
3180 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3181 {
3182 int status;
3183
3184 status = qlcnic_83xx_read_flash_status_reg(adapter);
3185 if (status == -EIO) {
3186 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3187 __func__);
3188 return 1;
3189 }
3190 return 0;
3191 }
kernel source for telekom puls (alcatel/mediatek)