2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
9 #include "qlcnic_sriov.h"
10 #include <linux/if_vlan.h>
11 #include <linux/ipv6.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14 #include <linux/aer.h>
16 #define RSS_HASHTYPE_IP_TCP 0x3
17 #define QLC_83XX_FW_MBX_CMD 0
19 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl
[] = {
20 {QLCNIC_CMD_CONFIGURE_IP_ADDR
, 6, 1},
21 {QLCNIC_CMD_CONFIG_INTRPT
, 18, 34},
22 {QLCNIC_CMD_CREATE_RX_CTX
, 136, 27},
23 {QLCNIC_CMD_DESTROY_RX_CTX
, 2, 1},
24 {QLCNIC_CMD_CREATE_TX_CTX
, 54, 18},
25 {QLCNIC_CMD_DESTROY_TX_CTX
, 2, 1},
26 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING
, 2, 1},
27 {QLCNIC_CMD_INTRPT_TEST
, 22, 12},
28 {QLCNIC_CMD_SET_MTU
, 3, 1},
29 {QLCNIC_CMD_READ_PHY
, 4, 2},
30 {QLCNIC_CMD_WRITE_PHY
, 5, 1},
31 {QLCNIC_CMD_READ_HW_REG
, 4, 1},
32 {QLCNIC_CMD_GET_FLOW_CTL
, 4, 2},
33 {QLCNIC_CMD_SET_FLOW_CTL
, 4, 1},
34 {QLCNIC_CMD_READ_MAX_MTU
, 4, 2},
35 {QLCNIC_CMD_READ_MAX_LRO
, 4, 2},
36 {QLCNIC_CMD_MAC_ADDRESS
, 4, 3},
37 {QLCNIC_CMD_GET_PCI_INFO
, 1, 66},
38 {QLCNIC_CMD_GET_NIC_INFO
, 2, 19},
39 {QLCNIC_CMD_SET_NIC_INFO
, 32, 1},
40 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY
, 4, 3},
41 {QLCNIC_CMD_TOGGLE_ESWITCH
, 4, 1},
42 {QLCNIC_CMD_GET_ESWITCH_STATUS
, 4, 3},
43 {QLCNIC_CMD_SET_PORTMIRRORING
, 4, 1},
44 {QLCNIC_CMD_CONFIGURE_ESWITCH
, 4, 1},
45 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG
, 4, 3},
46 {QLCNIC_CMD_GET_ESWITCH_STATS
, 5, 1},
47 {QLCNIC_CMD_CONFIG_PORT
, 4, 1},
48 {QLCNIC_CMD_TEMP_SIZE
, 1, 4},
49 {QLCNIC_CMD_GET_TEMP_HDR
, 5, 5},
50 {QLCNIC_CMD_GET_LINK_EVENT
, 2, 1},
51 {QLCNIC_CMD_CONFIG_MAC_VLAN
, 4, 3},
52 {QLCNIC_CMD_CONFIG_INTR_COAL
, 6, 1},
53 {QLCNIC_CMD_CONFIGURE_RSS
, 14, 1},
54 {QLCNIC_CMD_CONFIGURE_LED
, 2, 1},
55 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE
, 2, 1},
56 {QLCNIC_CMD_CONFIGURE_HW_LRO
, 2, 1},
57 {QLCNIC_CMD_GET_STATISTICS
, 2, 80},
58 {QLCNIC_CMD_SET_PORT_CONFIG
, 2, 1},
59 {QLCNIC_CMD_GET_PORT_CONFIG
, 2, 2},
60 {QLCNIC_CMD_GET_LINK_STATUS
, 2, 4},
61 {QLCNIC_CMD_IDC_ACK
, 5, 1},
62 {QLCNIC_CMD_INIT_NIC_FUNC
, 2, 1},
63 {QLCNIC_CMD_STOP_NIC_FUNC
, 2, 1},
64 {QLCNIC_CMD_SET_LED_CONFIG
, 5, 1},
65 {QLCNIC_CMD_GET_LED_CONFIG
, 1, 5},
66 {QLCNIC_CMD_83XX_SET_DRV_VER
, 4, 1},
67 {QLCNIC_CMD_ADD_RCV_RINGS
, 130, 26},
68 {QLCNIC_CMD_CONFIG_VPORT
, 4, 4},
69 {QLCNIC_CMD_BC_EVENT_SETUP
, 2, 1},
70 {QLCNIC_CMD_DCB_QUERY_CAP
, 1, 2},
71 {QLCNIC_CMD_DCB_QUERY_PARAM
, 2, 50},
74 const u32 qlcnic_83xx_ext_reg_tbl
[] = {
75 0x38CC, /* Global Reset */
76 0x38F0, /* Wildcard */
77 0x38FC, /* Informant */
78 0x3038, /* Host MBX ctrl */
79 0x303C, /* FW MBX ctrl */
80 0x355C, /* BOOT LOADER ADDRESS REG */
81 0x3560, /* BOOT LOADER SIZE REG */
82 0x3564, /* FW IMAGE ADDR REG */
83 0x1000, /* MBX intr enable */
84 0x1200, /* Default Intr mask */
85 0x1204, /* Default Interrupt ID */
86 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
87 0x3784, /* QLC_83XX_IDC_DEV_STATE */
88 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
89 0x378C, /* QLC_83XX_IDC_DRV_ACK */
90 0x3790, /* QLC_83XX_IDC_CTRL */
91 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
92 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
93 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
94 0x37A0, /* QLC_83XX_IDC_PF_0 */
95 0x37A4, /* QLC_83XX_IDC_PF_1 */
96 0x37A8, /* QLC_83XX_IDC_PF_2 */
97 0x37AC, /* QLC_83XX_IDC_PF_3 */
98 0x37B0, /* QLC_83XX_IDC_PF_4 */
99 0x37B4, /* QLC_83XX_IDC_PF_5 */
100 0x37B8, /* QLC_83XX_IDC_PF_6 */
101 0x37BC, /* QLC_83XX_IDC_PF_7 */
102 0x37C0, /* QLC_83XX_IDC_PF_8 */
103 0x37C4, /* QLC_83XX_IDC_PF_9 */
104 0x37C8, /* QLC_83XX_IDC_PF_10 */
105 0x37CC, /* QLC_83XX_IDC_PF_11 */
106 0x37D0, /* QLC_83XX_IDC_PF_12 */
107 0x37D4, /* QLC_83XX_IDC_PF_13 */
108 0x37D8, /* QLC_83XX_IDC_PF_14 */
109 0x37DC, /* QLC_83XX_IDC_PF_15 */
110 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
111 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
112 0x37F0, /* QLC_83XX_DRV_OP_MODE */
113 0x37F4, /* QLC_83XX_VNIC_STATE */
114 0x3868, /* QLC_83XX_DRV_LOCK */
115 0x386C, /* QLC_83XX_DRV_UNLOCK */
116 0x3504, /* QLC_83XX_DRV_LOCK_ID */
117 0x34A4, /* QLC_83XX_ASIC_TEMP */
120 const u32 qlcnic_83xx_reg_tbl
[] = {
121 0x34A8, /* PEG_HALT_STAT1 */
122 0x34AC, /* PEG_HALT_STAT2 */
123 0x34B0, /* FW_HEARTBEAT */
124 0x3500, /* FLASH LOCK_ID */
125 0x3528, /* FW_CAPABILITIES */
126 0x3538, /* Driver active, DRV_REG0 */
127 0x3540, /* Device state, DRV_REG1 */
128 0x3544, /* Driver state, DRV_REG2 */
129 0x3548, /* Driver scratch, DRV_REG3 */
130 0x354C, /* Device partiton info, DRV_REG4 */
131 0x3524, /* Driver IDC ver, DRV_REG5 */
132 0x3550, /* FW_VER_MAJOR */
133 0x3554, /* FW_VER_MINOR */
134 0x3558, /* FW_VER_SUB */
135 0x359C, /* NPAR STATE */
136 0x35FC, /* FW_IMG_VALID */
137 0x3650, /* CMD_PEG_STATE */
138 0x373C, /* RCV_PEG_STATE */
139 0x37B4, /* ASIC TEMP */
141 0x3570, /* DRV OP MODE */
142 0x3850, /* FLASH LOCK */
143 0x3854, /* FLASH UNLOCK */
146 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops
= {
147 .read_crb
= qlcnic_83xx_read_crb
,
148 .write_crb
= qlcnic_83xx_write_crb
,
149 .read_reg
= qlcnic_83xx_rd_reg_indirect
,
150 .write_reg
= qlcnic_83xx_wrt_reg_indirect
,
151 .get_mac_address
= qlcnic_83xx_get_mac_address
,
152 .setup_intr
= qlcnic_83xx_setup_intr
,
153 .alloc_mbx_args
= qlcnic_83xx_alloc_mbx_args
,
154 .mbx_cmd
= qlcnic_83xx_issue_cmd
,
155 .get_func_no
= qlcnic_83xx_get_func_no
,
156 .api_lock
= qlcnic_83xx_cam_lock
,
157 .api_unlock
= qlcnic_83xx_cam_unlock
,
158 .add_sysfs
= qlcnic_83xx_add_sysfs
,
159 .remove_sysfs
= qlcnic_83xx_remove_sysfs
,
160 .process_lb_rcv_ring_diag
= qlcnic_83xx_process_rcv_ring_diag
,
161 .create_rx_ctx
= qlcnic_83xx_create_rx_ctx
,
162 .create_tx_ctx
= qlcnic_83xx_create_tx_ctx
,
163 .del_rx_ctx
= qlcnic_83xx_del_rx_ctx
,
164 .del_tx_ctx
= qlcnic_83xx_del_tx_ctx
,
165 .setup_link_event
= qlcnic_83xx_setup_link_event
,
166 .get_nic_info
= qlcnic_83xx_get_nic_info
,
167 .get_pci_info
= qlcnic_83xx_get_pci_info
,
168 .set_nic_info
= qlcnic_83xx_set_nic_info
,
169 .change_macvlan
= qlcnic_83xx_sre_macaddr_change
,
170 .napi_enable
= qlcnic_83xx_napi_enable
,
171 .napi_disable
= qlcnic_83xx_napi_disable
,
172 .config_intr_coal
= qlcnic_83xx_config_intr_coal
,
173 .config_rss
= qlcnic_83xx_config_rss
,
174 .config_hw_lro
= qlcnic_83xx_config_hw_lro
,
175 .config_promisc_mode
= qlcnic_83xx_nic_set_promisc
,
176 .change_l2_filter
= qlcnic_83xx_change_l2_filter
,
177 .get_board_info
= qlcnic_83xx_get_port_info
,
178 .set_mac_filter_count
= qlcnic_83xx_set_mac_filter_count
,
179 .free_mac_list
= qlcnic_82xx_free_mac_list
,
180 .io_error_detected
= qlcnic_83xx_io_error_detected
,
181 .io_slot_reset
= qlcnic_83xx_io_slot_reset
,
182 .io_resume
= qlcnic_83xx_io_resume
,
186 static struct qlcnic_nic_template qlcnic_83xx_ops
= {
187 .config_bridged_mode
= qlcnic_config_bridged_mode
,
188 .config_led
= qlcnic_config_led
,
189 .request_reset
= qlcnic_83xx_idc_request_reset
,
190 .cancel_idc_work
= qlcnic_83xx_idc_exit
,
191 .napi_add
= qlcnic_83xx_napi_add
,
192 .napi_del
= qlcnic_83xx_napi_del
,
193 .config_ipaddr
= qlcnic_83xx_config_ipaddr
,
194 .clear_legacy_intr
= qlcnic_83xx_clear_legacy_intr
,
195 .shutdown
= qlcnic_83xx_shutdown
,
196 .resume
= qlcnic_83xx_resume
,
199 void qlcnic_83xx_register_map(struct qlcnic_hardware_context
*ahw
)
201 ahw
->hw_ops
= &qlcnic_83xx_hw_ops
;
202 ahw
->reg_tbl
= (u32
*)qlcnic_83xx_reg_tbl
;
203 ahw
->ext_reg_tbl
= (u32
*)qlcnic_83xx_ext_reg_tbl
;
206 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter
*adapter
)
208 u32 fw_major
, fw_minor
, fw_build
;
209 struct pci_dev
*pdev
= adapter
->pdev
;
211 fw_major
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MAJOR
);
212 fw_minor
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MINOR
);
213 fw_build
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_SUB
);
214 adapter
->fw_version
= QLCNIC_VERSION_CODE(fw_major
, fw_minor
, fw_build
);
216 dev_info(&pdev
->dev
, "Driver v%s, firmware version %d.%d.%d\n",
217 QLCNIC_LINUX_VERSIONID
, fw_major
, fw_minor
, fw_build
);
219 return adapter
->fw_version
;
222 static int __qlcnic_set_win_base(struct qlcnic_adapter
*adapter
, u32 addr
)
227 base
= adapter
->ahw
->pci_base0
+
228 QLC_83XX_CRB_WIN_FUNC(adapter
->ahw
->pci_func
);
237 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter
*adapter
, ulong addr
,
240 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
242 *err
= __qlcnic_set_win_base(adapter
, (u32
) addr
);
244 return QLCRDX(ahw
, QLCNIC_WILDCARD
);
246 dev_err(&adapter
->pdev
->dev
,
247 "%s failed, addr = 0x%lx\n", __func__
, addr
);
252 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter
*adapter
, ulong addr
,
256 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
258 err
= __qlcnic_set_win_base(adapter
, (u32
) addr
);
260 QLCWRX(ahw
, QLCNIC_WILDCARD
, data
);
263 dev_err(&adapter
->pdev
->dev
,
264 "%s failed, addr = 0x%x data = 0x%x\n",
265 __func__
, (int)addr
, data
);
270 int qlcnic_83xx_setup_intr(struct qlcnic_adapter
*adapter
)
272 int err
, i
, num_msix
;
273 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
275 num_msix
= adapter
->drv_sds_rings
;
277 /* account for AEN interrupt MSI-X based interrupts */
280 if (!(adapter
->flags
& QLCNIC_TX_INTR_SHARED
))
281 num_msix
+= adapter
->drv_tx_rings
;
283 err
= qlcnic_enable_msix(adapter
, num_msix
);
286 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
287 num_msix
= adapter
->ahw
->num_msix
;
289 if (qlcnic_sriov_vf_check(adapter
))
293 /* setup interrupt mapping table for fw */
294 ahw
->intr_tbl
= vzalloc(num_msix
*
295 sizeof(struct qlcnic_intrpt_config
));
298 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
)) {
299 /* MSI-X enablement failed, use legacy interrupt */
300 adapter
->tgt_status_reg
= ahw
->pci_base0
+ QLC_83XX_INTX_PTR
;
301 adapter
->tgt_mask_reg
= ahw
->pci_base0
+ QLC_83XX_INTX_MASK
;
302 adapter
->isr_int_vec
= ahw
->pci_base0
+ QLC_83XX_INTX_TRGR
;
303 adapter
->msix_entries
[0].vector
= adapter
->pdev
->irq
;
304 dev_info(&adapter
->pdev
->dev
, "using legacy interrupt\n");
307 for (i
= 0; i
< num_msix
; i
++) {
308 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
309 ahw
->intr_tbl
[i
].type
= QLCNIC_INTRPT_MSIX
;
311 ahw
->intr_tbl
[i
].type
= QLCNIC_INTRPT_INTX
;
312 ahw
->intr_tbl
[i
].id
= i
;
313 ahw
->intr_tbl
[i
].src
= 0;
318 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter
*adapter
)
320 writel(0, adapter
->tgt_mask_reg
);
323 inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter
*adapter
)
325 if (adapter
->tgt_mask_reg
)
326 writel(1, adapter
->tgt_mask_reg
);
329 /* Enable MSI-x and INT-x interrupts */
330 void qlcnic_83xx_enable_intr(struct qlcnic_adapter
*adapter
,
331 struct qlcnic_host_sds_ring
*sds_ring
)
333 writel(0, sds_ring
->crb_intr_mask
);
336 /* Disable MSI-x and INT-x interrupts */
337 void qlcnic_83xx_disable_intr(struct qlcnic_adapter
*adapter
,
338 struct qlcnic_host_sds_ring
*sds_ring
)
340 writel(1, sds_ring
->crb_intr_mask
);
343 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
348 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
349 * source register. We could be here before contexts are created
350 * and sds_ring->crb_intr_mask has not been initialized, calculate
351 * BAR offset for Interrupt Source Register
353 mask
= QLCRDX(adapter
->ahw
, QLCNIC_DEF_INT_MASK
);
354 writel(0, adapter
->ahw
->pci_base0
+ mask
);
357 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter
*adapter
)
361 mask
= QLCRDX(adapter
->ahw
, QLCNIC_DEF_INT_MASK
);
362 writel(1, adapter
->ahw
->pci_base0
+ mask
);
363 QLCWRX(adapter
->ahw
, QLCNIC_MBX_INTR_ENBL
, 0);
366 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter
*adapter
,
367 struct qlcnic_cmd_args
*cmd
)
371 if (cmd
->op_type
== QLC_83XX_MBX_POST_BC_OP
)
374 for (i
= 0; i
< cmd
->rsp
.num
; i
++)
375 cmd
->rsp
.arg
[i
] = readl(QLCNIC_MBX_FW(adapter
->ahw
, i
));
378 irqreturn_t
qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter
*adapter
)
381 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
384 intr_val
= readl(adapter
->tgt_status_reg
);
386 if (!QLC_83XX_VALID_INTX_BIT31(intr_val
))
389 if (QLC_83XX_INTX_FUNC(intr_val
) != adapter
->ahw
->pci_func
) {
390 adapter
->stats
.spurious_intr
++;
393 /* The barrier is required to ensure writes to the registers */
396 /* clear the interrupt trigger control register */
397 writel(0, adapter
->isr_int_vec
);
398 intr_val
= readl(adapter
->isr_int_vec
);
400 intr_val
= readl(adapter
->tgt_status_reg
);
401 if (QLC_83XX_INTX_FUNC(intr_val
) != ahw
->pci_func
)
404 } while (QLC_83XX_VALID_INTX_BIT30(intr_val
) &&
405 (retries
< QLC_83XX_LEGACY_INTX_MAX_RETRY
));
410 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox
*mbx
)
412 atomic_set(&mbx
->rsp_status
, QLC_83XX_MBX_RESPONSE_ARRIVED
);
413 complete(&mbx
->completion
);
416 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter
*adapter
)
418 u32 resp
, event
, rsp_status
= QLC_83XX_MBX_RESPONSE_ARRIVED
;
419 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
422 spin_lock_irqsave(&mbx
->aen_lock
, flags
);
423 resp
= QLCRDX(adapter
->ahw
, QLCNIC_FW_MBX_CTRL
);
424 if (!(resp
& QLCNIC_SET_OWNER
))
427 event
= readl(QLCNIC_MBX_FW(adapter
->ahw
, 0));
428 if (event
& QLCNIC_MBX_ASYNC_EVENT
) {
429 __qlcnic_83xx_process_aen(adapter
);
431 if (atomic_read(&mbx
->rsp_status
) != rsp_status
)
432 qlcnic_83xx_notify_mbx_response(mbx
);
435 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
436 spin_unlock_irqrestore(&mbx
->aen_lock
, flags
);
439 irqreturn_t
qlcnic_83xx_intr(int irq
, void *data
)
441 struct qlcnic_adapter
*adapter
= data
;
442 struct qlcnic_host_sds_ring
*sds_ring
;
443 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
445 if (qlcnic_83xx_clear_legacy_intr(adapter
) == IRQ_NONE
)
448 qlcnic_83xx_poll_process_aen(adapter
);
450 if (ahw
->diag_test
== QLCNIC_INTERRUPT_TEST
) {
452 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
456 if (!test_bit(__QLCNIC_DEV_UP
, &adapter
->state
)) {
457 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
459 sds_ring
= &adapter
->recv_ctx
->sds_rings
[0];
460 napi_schedule(&sds_ring
->napi
);
466 irqreturn_t
qlcnic_83xx_tmp_intr(int irq
, void *data
)
468 struct qlcnic_host_sds_ring
*sds_ring
= data
;
469 struct qlcnic_adapter
*adapter
= sds_ring
->adapter
;
471 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
474 if (adapter
->nic_ops
->clear_legacy_intr(adapter
) == IRQ_NONE
)
478 adapter
->ahw
->diag_cnt
++;
479 qlcnic_83xx_enable_intr(adapter
, sds_ring
);
484 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter
*adapter
)
488 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
489 qlcnic_83xx_set_legacy_intr_mask(adapter
);
491 qlcnic_83xx_disable_mbx_intr(adapter
);
493 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
494 num_msix
= adapter
->ahw
->num_msix
- 1;
500 if (adapter
->msix_entries
) {
501 synchronize_irq(adapter
->msix_entries
[num_msix
].vector
);
502 free_irq(adapter
->msix_entries
[num_msix
].vector
, adapter
);
506 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter
*adapter
)
508 irq_handler_t handler
;
511 unsigned long flags
= 0;
513 if (!(adapter
->flags
& QLCNIC_MSI_ENABLED
) &&
514 !(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
515 flags
|= IRQF_SHARED
;
517 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
) {
518 handler
= qlcnic_83xx_handle_aen
;
519 val
= adapter
->msix_entries
[adapter
->ahw
->num_msix
- 1].vector
;
520 err
= request_irq(val
, handler
, flags
, "qlcnic-MB", adapter
);
522 dev_err(&adapter
->pdev
->dev
,
523 "failed to register MBX interrupt\n");
527 handler
= qlcnic_83xx_intr
;
528 val
= adapter
->msix_entries
[0].vector
;
529 err
= request_irq(val
, handler
, flags
, "qlcnic", adapter
);
531 dev_err(&adapter
->pdev
->dev
,
532 "failed to register INTx interrupt\n");
535 qlcnic_83xx_clear_legacy_intr_mask(adapter
);
538 /* Enable mailbox interrupt */
539 qlcnic_83xx_enable_mbx_interrupt(adapter
);
544 void qlcnic_83xx_get_func_no(struct qlcnic_adapter
*adapter
)
546 u32 val
= QLCRDX(adapter
->ahw
, QLCNIC_INFORMANT
);
547 adapter
->ahw
->pci_func
= (val
>> 24) & 0xff;
550 int qlcnic_83xx_cam_lock(struct qlcnic_adapter
*adapter
)
555 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
557 addr
= ahw
->pci_base0
+ QLC_83XX_SEM_LOCK_FUNC(ahw
->pci_func
);
561 /* write the function number to register */
562 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FLASH_LOCK_OWNER
,
566 usleep_range(1000, 2000);
567 } while (++limit
<= QLCNIC_PCIE_SEM_TIMEOUT
);
572 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter
*adapter
)
576 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
578 addr
= ahw
->pci_base0
+ QLC_83XX_SEM_UNLOCK_FUNC(ahw
->pci_func
);
582 void qlcnic_83xx_read_crb(struct qlcnic_adapter
*adapter
, char *buf
,
583 loff_t offset
, size_t size
)
588 if (qlcnic_api_lock(adapter
)) {
589 dev_err(&adapter
->pdev
->dev
,
590 "%s: failed to acquire lock. addr offset 0x%x\n",
591 __func__
, (u32
)offset
);
595 data
= QLCRD32(adapter
, (u32
) offset
, &ret
);
596 qlcnic_api_unlock(adapter
);
599 dev_err(&adapter
->pdev
->dev
,
600 "%s: failed. addr offset 0x%x\n",
601 __func__
, (u32
)offset
);
604 memcpy(buf
, &data
, size
);
607 void qlcnic_83xx_write_crb(struct qlcnic_adapter
*adapter
, char *buf
,
608 loff_t offset
, size_t size
)
612 memcpy(&data
, buf
, size
);
613 qlcnic_83xx_wrt_reg_indirect(adapter
, (u32
) offset
, data
);
616 int qlcnic_83xx_get_port_info(struct qlcnic_adapter
*adapter
)
620 status
= qlcnic_83xx_get_port_config(adapter
);
622 dev_err(&adapter
->pdev
->dev
,
623 "Get Port Info failed\n");
625 if (QLC_83XX_SFP_10G_CAPABLE(adapter
->ahw
->port_config
))
626 adapter
->ahw
->port_type
= QLCNIC_XGBE
;
628 adapter
->ahw
->port_type
= QLCNIC_GBE
;
630 if (QLC_83XX_AUTONEG(adapter
->ahw
->port_config
))
631 adapter
->ahw
->link_autoneg
= AUTONEG_ENABLE
;
636 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter
*adapter
)
638 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
639 u16 act_pci_fn
= ahw
->act_pci_func
;
642 ahw
->max_mc_count
= QLC_83XX_MAX_MC_COUNT
;
644 count
= (QLC_83XX_MAX_UC_COUNT
- QLC_83XX_MAX_MC_COUNT
) /
647 count
= (QLC_83XX_LB_MAX_FILTERS
- QLC_83XX_MAX_MC_COUNT
) /
649 ahw
->max_uc_count
= count
;
652 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter
*adapter
)
656 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
657 val
= BIT_2
| ((adapter
->ahw
->num_msix
- 1) << 8);
661 QLCWRX(adapter
->ahw
, QLCNIC_MBX_INTR_ENBL
, val
);
662 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
665 void qlcnic_83xx_check_vf(struct qlcnic_adapter
*adapter
,
666 const struct pci_device_id
*ent
)
668 u32 op_mode
, priv_level
;
669 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
671 ahw
->fw_hal_version
= 2;
672 qlcnic_get_func_no(adapter
);
674 if (qlcnic_sriov_vf_check(adapter
)) {
675 qlcnic_sriov_vf_set_ops(adapter
);
679 /* Determine function privilege level */
680 op_mode
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_OP_MODE
);
681 if (op_mode
== QLC_83XX_DEFAULT_OPMODE
)
682 priv_level
= QLCNIC_MGMT_FUNC
;
684 priv_level
= QLC_83XX_GET_FUNC_PRIVILEGE(op_mode
,
687 if (priv_level
== QLCNIC_NON_PRIV_FUNC
) {
688 ahw
->op_mode
= QLCNIC_NON_PRIV_FUNC
;
689 dev_info(&adapter
->pdev
->dev
,
690 "HAL Version: %d Non Privileged function\n",
691 ahw
->fw_hal_version
);
692 adapter
->nic_ops
= &qlcnic_vf_ops
;
694 if (pci_find_ext_capability(adapter
->pdev
,
695 PCI_EXT_CAP_ID_SRIOV
))
696 set_bit(__QLCNIC_SRIOV_CAPABLE
, &adapter
->state
);
697 adapter
->nic_ops
= &qlcnic_83xx_ops
;
701 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter
*adapter
,
703 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter
*adapter
,
706 void qlcnic_dump_mbx(struct qlcnic_adapter
*adapter
,
707 struct qlcnic_cmd_args
*cmd
)
711 if (cmd
->op_type
== QLC_83XX_MBX_POST_BC_OP
)
714 dev_info(&adapter
->pdev
->dev
,
715 "Host MBX regs(%d)\n", cmd
->req
.num
);
716 for (i
= 0; i
< cmd
->req
.num
; i
++) {
719 pr_info("%08x ", cmd
->req
.arg
[i
]);
722 dev_info(&adapter
->pdev
->dev
,
723 "FW MBX regs(%d)\n", cmd
->rsp
.num
);
724 for (i
= 0; i
< cmd
->rsp
.num
; i
++) {
727 pr_info("%08x ", cmd
->rsp
.arg
[i
]);
732 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter
*adapter
,
733 struct qlcnic_cmd_args
*cmd
)
735 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
736 int opcode
= LSW(cmd
->req
.arg
[0]);
737 unsigned long max_loops
;
739 max_loops
= cmd
->total_cmds
* QLC_83XX_MBX_CMD_LOOP
;
741 for (; max_loops
; max_loops
--) {
742 if (atomic_read(&cmd
->rsp_status
) ==
743 QLC_83XX_MBX_RESPONSE_ARRIVED
)
749 dev_err(&adapter
->pdev
->dev
,
750 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
751 __func__
, opcode
, cmd
->type
, ahw
->pci_func
, ahw
->op_mode
);
752 flush_workqueue(ahw
->mailbox
->work_q
);
756 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter
*adapter
,
757 struct qlcnic_cmd_args
*cmd
)
759 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
760 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
761 int cmd_type
, err
, opcode
;
762 unsigned long timeout
;
767 opcode
= LSW(cmd
->req
.arg
[0]);
768 cmd_type
= cmd
->type
;
769 err
= mbx
->ops
->enqueue_cmd(adapter
, cmd
, &timeout
);
771 dev_err(&adapter
->pdev
->dev
,
772 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
773 __func__
, opcode
, cmd
->type
, ahw
->pci_func
,
779 case QLC_83XX_MBX_CMD_WAIT
:
780 if (!wait_for_completion_timeout(&cmd
->completion
, timeout
)) {
781 dev_err(&adapter
->pdev
->dev
,
782 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
783 __func__
, opcode
, cmd_type
, ahw
->pci_func
,
785 flush_workqueue(mbx
->work_q
);
788 case QLC_83XX_MBX_CMD_NO_WAIT
:
790 case QLC_83XX_MBX_CMD_BUSY_WAIT
:
791 qlcnic_83xx_poll_for_mbx_completion(adapter
, cmd
);
794 dev_err(&adapter
->pdev
->dev
,
795 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
796 __func__
, opcode
, cmd_type
, ahw
->pci_func
,
798 qlcnic_83xx_detach_mailbox_work(adapter
);
801 return cmd
->rsp_opcode
;
804 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args
*mbx
,
805 struct qlcnic_adapter
*adapter
, u32 type
)
809 const struct qlcnic_mailbox_metadata
*mbx_tbl
;
811 memset(mbx
, 0, sizeof(struct qlcnic_cmd_args
));
812 mbx_tbl
= qlcnic_83xx_mbx_tbl
;
813 size
= ARRAY_SIZE(qlcnic_83xx_mbx_tbl
);
814 for (i
= 0; i
< size
; i
++) {
815 if (type
== mbx_tbl
[i
].cmd
) {
816 mbx
->op_type
= QLC_83XX_FW_MBX_CMD
;
817 mbx
->req
.num
= mbx_tbl
[i
].in_args
;
818 mbx
->rsp
.num
= mbx_tbl
[i
].out_args
;
819 mbx
->req
.arg
= kcalloc(mbx
->req
.num
, sizeof(u32
),
823 mbx
->rsp
.arg
= kcalloc(mbx
->rsp
.num
, sizeof(u32
),
830 memset(mbx
->req
.arg
, 0, sizeof(u32
) * mbx
->req
.num
);
831 memset(mbx
->rsp
.arg
, 0, sizeof(u32
) * mbx
->rsp
.num
);
832 temp
= adapter
->ahw
->fw_hal_version
<< 29;
833 mbx
->req
.arg
[0] = (type
| (mbx
->req
.num
<< 16) | temp
);
841 void qlcnic_83xx_idc_aen_work(struct work_struct
*work
)
843 struct qlcnic_adapter
*adapter
;
844 struct qlcnic_cmd_args cmd
;
847 adapter
= container_of(work
, struct qlcnic_adapter
, idc_aen_work
.work
);
848 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_IDC_ACK
);
852 for (i
= 1; i
< QLC_83XX_MBX_AEN_CNT
; i
++)
853 cmd
.req
.arg
[i
] = adapter
->ahw
->mbox_aen
[i
];
855 err
= qlcnic_issue_cmd(adapter
, &cmd
);
857 dev_info(&adapter
->pdev
->dev
,
858 "%s: Mailbox IDC ACK failed.\n", __func__
);
859 qlcnic_free_mbx_args(&cmd
);
862 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter
*adapter
,
865 dev_dbg(&adapter
->pdev
->dev
, "Completion AEN:0x%x.\n",
866 QLCNIC_MBX_RSP(data
[0]));
867 clear_bit(QLC_83XX_IDC_COMP_AEN
, &adapter
->ahw
->idc
.status
);
871 void __qlcnic_83xx_process_aen(struct qlcnic_adapter
*adapter
)
873 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
874 u32 event
[QLC_83XX_MBX_AEN_CNT
];
877 for (i
= 0; i
< QLC_83XX_MBX_AEN_CNT
; i
++)
878 event
[i
] = readl(QLCNIC_MBX_FW(ahw
, i
));
880 switch (QLCNIC_MBX_RSP(event
[0])) {
882 case QLCNIC_MBX_LINK_EVENT
:
883 qlcnic_83xx_handle_link_aen(adapter
, event
);
885 case QLCNIC_MBX_COMP_EVENT
:
886 qlcnic_83xx_handle_idc_comp_aen(adapter
, event
);
888 case QLCNIC_MBX_REQUEST_EVENT
:
889 for (i
= 0; i
< QLC_83XX_MBX_AEN_CNT
; i
++)
890 adapter
->ahw
->mbox_aen
[i
] = QLCNIC_MBX_RSP(event
[i
]);
891 queue_delayed_work(adapter
->qlcnic_wq
,
892 &adapter
->idc_aen_work
, 0);
894 case QLCNIC_MBX_TIME_EXTEND_EVENT
:
895 ahw
->extend_lb_time
= event
[1] >> 8 & 0xf;
897 case QLCNIC_MBX_BC_EVENT
:
898 qlcnic_sriov_handle_bc_event(adapter
, event
[1]);
900 case QLCNIC_MBX_SFP_INSERT_EVENT
:
901 dev_info(&adapter
->pdev
->dev
, "SFP+ Insert AEN:0x%x.\n",
902 QLCNIC_MBX_RSP(event
[0]));
904 case QLCNIC_MBX_SFP_REMOVE_EVENT
:
905 dev_info(&adapter
->pdev
->dev
, "SFP Removed AEN:0x%x.\n",
906 QLCNIC_MBX_RSP(event
[0]));
908 case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT
:
909 qlcnic_dcb_aen_handler(adapter
->dcb
, (void *)&event
[1]);
912 dev_dbg(&adapter
->pdev
->dev
, "Unsupported AEN:0x%x.\n",
913 QLCNIC_MBX_RSP(event
[0]));
917 QLCWRX(ahw
, QLCNIC_FW_MBX_CTRL
, QLCNIC_CLR_OWNER
);
920 static void qlcnic_83xx_process_aen(struct qlcnic_adapter
*adapter
)
922 u32 resp
, event
, rsp_status
= QLC_83XX_MBX_RESPONSE_ARRIVED
;
923 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
924 struct qlcnic_mailbox
*mbx
= ahw
->mailbox
;
927 spin_lock_irqsave(&mbx
->aen_lock
, flags
);
928 resp
= QLCRDX(ahw
, QLCNIC_FW_MBX_CTRL
);
929 if (resp
& QLCNIC_SET_OWNER
) {
930 event
= readl(QLCNIC_MBX_FW(ahw
, 0));
931 if (event
& QLCNIC_MBX_ASYNC_EVENT
) {
932 __qlcnic_83xx_process_aen(adapter
);
934 if (atomic_read(&mbx
->rsp_status
) != rsp_status
)
935 qlcnic_83xx_notify_mbx_response(mbx
);
938 spin_unlock_irqrestore(&mbx
->aen_lock
, flags
);
941 static void qlcnic_83xx_mbx_poll_work(struct work_struct
*work
)
943 struct qlcnic_adapter
*adapter
;
945 adapter
= container_of(work
, struct qlcnic_adapter
, mbx_poll_work
.work
);
947 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE
, &adapter
->state
))
950 qlcnic_83xx_process_aen(adapter
);
951 queue_delayed_work(adapter
->qlcnic_wq
, &adapter
->mbx_poll_work
,
955 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter
*adapter
)
957 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE
, &adapter
->state
))
960 INIT_DELAYED_WORK(&adapter
->mbx_poll_work
, qlcnic_83xx_mbx_poll_work
);
961 queue_delayed_work(adapter
->qlcnic_wq
, &adapter
->mbx_poll_work
, 0);
964 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter
*adapter
)
966 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE
, &adapter
->state
))
968 cancel_delayed_work_sync(&adapter
->mbx_poll_work
);
971 static int qlcnic_83xx_add_rings(struct qlcnic_adapter
*adapter
)
973 int index
, i
, err
, sds_mbx_size
;
974 u32
*buf
, intrpt_id
, intr_mask
;
977 struct qlcnic_cmd_args cmd
;
978 struct qlcnic_host_sds_ring
*sds
;
979 struct qlcnic_sds_mbx sds_mbx
;
980 struct qlcnic_add_rings_mbx_out
*mbx_out
;
981 struct qlcnic_recv_context
*recv_ctx
= adapter
->recv_ctx
;
982 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
984 sds_mbx_size
= sizeof(struct qlcnic_sds_mbx
);
985 context_id
= recv_ctx
->context_id
;
986 num_sds
= adapter
->drv_sds_rings
- QLCNIC_MAX_SDS_RINGS
;
987 ahw
->hw_ops
->alloc_mbx_args(&cmd
, adapter
,
988 QLCNIC_CMD_ADD_RCV_RINGS
);
989 cmd
.req
.arg
[1] = 0 | (num_sds
<< 8) | (context_id
<< 16);
991 /* set up status rings, mbx 2-81 */
993 for (i
= 8; i
< adapter
->drv_sds_rings
; i
++) {
994 memset(&sds_mbx
, 0, sds_mbx_size
);
995 sds
= &recv_ctx
->sds_rings
[i
];
997 memset(sds
->desc_head
, 0, STATUS_DESC_RINGSIZE(sds
));
998 sds_mbx
.phy_addr_low
= LSD(sds
->phys_addr
);
999 sds_mbx
.phy_addr_high
= MSD(sds
->phys_addr
);
1000 sds_mbx
.sds_ring_size
= sds
->num_desc
;
1002 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
1003 intrpt_id
= ahw
->intr_tbl
[i
].id
;
1005 intrpt_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
1007 if (adapter
->ahw
->diag_test
!= QLCNIC_LOOPBACK_TEST
)
1008 sds_mbx
.intrpt_id
= intrpt_id
;
1010 sds_mbx
.intrpt_id
= 0xffff;
1011 sds_mbx
.intrpt_val
= 0;
1012 buf
= &cmd
.req
.arg
[index
];
1013 memcpy(buf
, &sds_mbx
, sds_mbx_size
);
1014 index
+= sds_mbx_size
/ sizeof(u32
);
1017 /* send the mailbox command */
1018 err
= ahw
->hw_ops
->mbx_cmd(adapter
, &cmd
);
1020 dev_err(&adapter
->pdev
->dev
,
1021 "Failed to add rings %d\n", err
);
1025 mbx_out
= (struct qlcnic_add_rings_mbx_out
*)&cmd
.rsp
.arg
[1];
1027 /* status descriptor ring */
1028 for (i
= 8; i
< adapter
->drv_sds_rings
; i
++) {
1029 sds
= &recv_ctx
->sds_rings
[i
];
1030 sds
->crb_sts_consumer
= ahw
->pci_base0
+
1031 mbx_out
->host_csmr
[index
];
1032 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
1033 intr_mask
= ahw
->intr_tbl
[i
].src
;
1035 intr_mask
= QLCRDX(ahw
, QLCNIC_DEF_INT_MASK
);
1037 sds
->crb_intr_mask
= ahw
->pci_base0
+ intr_mask
;
1041 qlcnic_free_mbx_args(&cmd
);
1045 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter
*adapter
)
1049 struct qlcnic_cmd_args cmd
;
1050 struct qlcnic_recv_context
*recv_ctx
= adapter
->recv_ctx
;
1052 if (qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_DESTROY_RX_CTX
))
1055 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1056 cmd
.req
.arg
[0] |= (0x3 << 29);
1058 if (qlcnic_sriov_pf_check(adapter
))
1059 qlcnic_pf_set_interface_id_del_rx_ctx(adapter
, &temp
);
1061 cmd
.req
.arg
[1] = recv_ctx
->context_id
| temp
;
1062 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1064 dev_err(&adapter
->pdev
->dev
,
1065 "Failed to destroy rx ctx in firmware\n");
1067 recv_ctx
->state
= QLCNIC_HOST_CTX_STATE_FREED
;
1068 qlcnic_free_mbx_args(&cmd
);
1071 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter
*adapter
)
1073 int i
, err
, index
, sds_mbx_size
, rds_mbx_size
;
1074 u8 num_sds
, num_rds
;
1075 u32
*buf
, intrpt_id
, intr_mask
, cap
= 0;
1076 struct qlcnic_host_sds_ring
*sds
;
1077 struct qlcnic_host_rds_ring
*rds
;
1078 struct qlcnic_sds_mbx sds_mbx
;
1079 struct qlcnic_rds_mbx rds_mbx
;
1080 struct qlcnic_cmd_args cmd
;
1081 struct qlcnic_rcv_mbx_out
*mbx_out
;
1082 struct qlcnic_recv_context
*recv_ctx
= adapter
->recv_ctx
;
1083 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1084 num_rds
= adapter
->max_rds_rings
;
1086 if (adapter
->drv_sds_rings
<= QLCNIC_MAX_SDS_RINGS
)
1087 num_sds
= adapter
->drv_sds_rings
;
1089 num_sds
= QLCNIC_MAX_SDS_RINGS
;
1091 sds_mbx_size
= sizeof(struct qlcnic_sds_mbx
);
1092 rds_mbx_size
= sizeof(struct qlcnic_rds_mbx
);
1093 cap
= QLCNIC_CAP0_LEGACY_CONTEXT
;
1095 if (adapter
->flags
& QLCNIC_FW_LRO_MSS_CAP
)
1096 cap
|= QLC_83XX_FW_CAP_LRO_MSS
;
1098 /* set mailbox hdr and capabilities */
1099 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1100 QLCNIC_CMD_CREATE_RX_CTX
);
1104 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1105 cmd
.req
.arg
[0] |= (0x3 << 29);
1107 cmd
.req
.arg
[1] = cap
;
1108 cmd
.req
.arg
[5] = 1 | (num_rds
<< 5) | (num_sds
<< 8) |
1109 (QLC_83XX_HOST_RDS_MODE_UNIQUE
<< 16);
1111 if (qlcnic_sriov_pf_check(adapter
))
1112 qlcnic_pf_set_interface_id_create_rx_ctx(adapter
,
1114 /* set up status rings, mbx 8-57/87 */
1115 index
= QLC_83XX_HOST_SDS_MBX_IDX
;
1116 for (i
= 0; i
< num_sds
; i
++) {
1117 memset(&sds_mbx
, 0, sds_mbx_size
);
1118 sds
= &recv_ctx
->sds_rings
[i
];
1120 memset(sds
->desc_head
, 0, STATUS_DESC_RINGSIZE(sds
));
1121 sds_mbx
.phy_addr_low
= LSD(sds
->phys_addr
);
1122 sds_mbx
.phy_addr_high
= MSD(sds
->phys_addr
);
1123 sds_mbx
.sds_ring_size
= sds
->num_desc
;
1124 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
1125 intrpt_id
= ahw
->intr_tbl
[i
].id
;
1127 intrpt_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
1128 if (adapter
->ahw
->diag_test
!= QLCNIC_LOOPBACK_TEST
)
1129 sds_mbx
.intrpt_id
= intrpt_id
;
1131 sds_mbx
.intrpt_id
= 0xffff;
1132 sds_mbx
.intrpt_val
= 0;
1133 buf
= &cmd
.req
.arg
[index
];
1134 memcpy(buf
, &sds_mbx
, sds_mbx_size
);
1135 index
+= sds_mbx_size
/ sizeof(u32
);
1137 /* set up receive rings, mbx 88-111/135 */
1138 index
= QLCNIC_HOST_RDS_MBX_IDX
;
1139 rds
= &recv_ctx
->rds_rings
[0];
1141 memset(&rds_mbx
, 0, rds_mbx_size
);
1142 rds_mbx
.phy_addr_reg_low
= LSD(rds
->phys_addr
);
1143 rds_mbx
.phy_addr_reg_high
= MSD(rds
->phys_addr
);
1144 rds_mbx
.reg_ring_sz
= rds
->dma_size
;
1145 rds_mbx
.reg_ring_len
= rds
->num_desc
;
1147 rds
= &recv_ctx
->rds_rings
[1];
1149 rds_mbx
.phy_addr_jmb_low
= LSD(rds
->phys_addr
);
1150 rds_mbx
.phy_addr_jmb_high
= MSD(rds
->phys_addr
);
1151 rds_mbx
.jmb_ring_sz
= rds
->dma_size
;
1152 rds_mbx
.jmb_ring_len
= rds
->num_desc
;
1153 buf
= &cmd
.req
.arg
[index
];
1154 memcpy(buf
, &rds_mbx
, rds_mbx_size
);
1156 /* send the mailbox command */
1157 err
= ahw
->hw_ops
->mbx_cmd(adapter
, &cmd
);
1159 dev_err(&adapter
->pdev
->dev
,
1160 "Failed to create Rx ctx in firmware%d\n", err
);
1163 mbx_out
= (struct qlcnic_rcv_mbx_out
*)&cmd
.rsp
.arg
[1];
1164 recv_ctx
->context_id
= mbx_out
->ctx_id
;
1165 recv_ctx
->state
= mbx_out
->state
;
1166 recv_ctx
->virt_port
= mbx_out
->vport_id
;
1167 dev_info(&adapter
->pdev
->dev
, "Rx Context[%d] Created, state:0x%x\n",
1168 recv_ctx
->context_id
, recv_ctx
->state
);
1169 /* Receive descriptor ring */
1171 rds
= &recv_ctx
->rds_rings
[0];
1172 rds
->crb_rcv_producer
= ahw
->pci_base0
+
1173 mbx_out
->host_prod
[0].reg_buf
;
1175 rds
= &recv_ctx
->rds_rings
[1];
1176 rds
->crb_rcv_producer
= ahw
->pci_base0
+
1177 mbx_out
->host_prod
[0].jmb_buf
;
1178 /* status descriptor ring */
1179 for (i
= 0; i
< num_sds
; i
++) {
1180 sds
= &recv_ctx
->sds_rings
[i
];
1181 sds
->crb_sts_consumer
= ahw
->pci_base0
+
1182 mbx_out
->host_csmr
[i
];
1183 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
1184 intr_mask
= ahw
->intr_tbl
[i
].src
;
1186 intr_mask
= QLCRDX(ahw
, QLCNIC_DEF_INT_MASK
);
1187 sds
->crb_intr_mask
= ahw
->pci_base0
+ intr_mask
;
1190 if (adapter
->drv_sds_rings
> QLCNIC_MAX_SDS_RINGS
)
1191 err
= qlcnic_83xx_add_rings(adapter
);
1193 qlcnic_free_mbx_args(&cmd
);
1197 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter
*adapter
,
1198 struct qlcnic_host_tx_ring
*tx_ring
)
1200 struct qlcnic_cmd_args cmd
;
1203 if (qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_DESTROY_TX_CTX
))
1206 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1207 cmd
.req
.arg
[0] |= (0x3 << 29);
1209 if (qlcnic_sriov_pf_check(adapter
))
1210 qlcnic_pf_set_interface_id_del_tx_ctx(adapter
, &temp
);
1212 cmd
.req
.arg
[1] = tx_ring
->ctx_id
| temp
;
1213 if (qlcnic_issue_cmd(adapter
, &cmd
))
1214 dev_err(&adapter
->pdev
->dev
,
1215 "Failed to destroy tx ctx in firmware\n");
1216 qlcnic_free_mbx_args(&cmd
);
1219 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter
*adapter
,
1220 struct qlcnic_host_tx_ring
*tx
, int ring
)
1224 u32
*buf
, intr_mask
, temp
= 0;
1225 struct qlcnic_cmd_args cmd
;
1226 struct qlcnic_tx_mbx mbx
;
1227 struct qlcnic_tx_mbx_out
*mbx_out
;
1228 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1231 /* Reset host resources */
1233 tx
->sw_consumer
= 0;
1234 *(tx
->hw_consumer
) = 0;
1236 memset(&mbx
, 0, sizeof(struct qlcnic_tx_mbx
));
1238 /* setup mailbox inbox registerss */
1239 mbx
.phys_addr_low
= LSD(tx
->phys_addr
);
1240 mbx
.phys_addr_high
= MSD(tx
->phys_addr
);
1241 mbx
.cnsmr_index_low
= LSD(tx
->hw_cons_phys_addr
);
1242 mbx
.cnsmr_index_high
= MSD(tx
->hw_cons_phys_addr
);
1243 mbx
.size
= tx
->num_desc
;
1244 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
) {
1245 if (!(adapter
->flags
& QLCNIC_TX_INTR_SHARED
))
1246 msix_vector
= adapter
->drv_sds_rings
+ ring
;
1248 msix_vector
= adapter
->drv_sds_rings
- 1;
1249 msix_id
= ahw
->intr_tbl
[msix_vector
].id
;
1251 msix_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
1254 if (adapter
->ahw
->diag_test
!= QLCNIC_LOOPBACK_TEST
)
1255 mbx
.intr_id
= msix_id
;
1257 mbx
.intr_id
= 0xffff;
1260 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CREATE_TX_CTX
);
1264 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1265 cmd
.req
.arg
[0] |= (0x3 << 29);
1267 if (qlcnic_sriov_pf_check(adapter
))
1268 qlcnic_pf_set_interface_id_create_tx_ctx(adapter
, &temp
);
1270 cmd
.req
.arg
[1] = QLCNIC_CAP0_LEGACY_CONTEXT
;
1271 cmd
.req
.arg
[5] = QLCNIC_SINGLE_RING
| temp
;
1273 buf
= &cmd
.req
.arg
[6];
1274 memcpy(buf
, &mbx
, sizeof(struct qlcnic_tx_mbx
));
1275 /* send the mailbox command*/
1276 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1278 dev_err(&adapter
->pdev
->dev
,
1279 "Failed to create Tx ctx in firmware 0x%x\n", err
);
1282 mbx_out
= (struct qlcnic_tx_mbx_out
*)&cmd
.rsp
.arg
[2];
1283 tx
->crb_cmd_producer
= ahw
->pci_base0
+ mbx_out
->host_prod
;
1284 tx
->ctx_id
= mbx_out
->ctx_id
;
1285 if ((adapter
->flags
& QLCNIC_MSIX_ENABLED
) &&
1286 !(adapter
->flags
& QLCNIC_TX_INTR_SHARED
)) {
1287 intr_mask
= ahw
->intr_tbl
[adapter
->drv_sds_rings
+ ring
].src
;
1288 tx
->crb_intr_mask
= ahw
->pci_base0
+ intr_mask
;
1290 dev_info(&adapter
->pdev
->dev
, "Tx Context[0x%x] Created, state:0x%x\n",
1291 tx
->ctx_id
, mbx_out
->state
);
1293 qlcnic_free_mbx_args(&cmd
);
1297 static int qlcnic_83xx_diag_alloc_res(struct net_device
*netdev
, int test
,
1300 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1301 struct qlcnic_host_sds_ring
*sds_ring
;
1302 struct qlcnic_host_rds_ring
*rds_ring
;
1303 u16 adapter_state
= adapter
->is_up
;
1307 netif_device_detach(netdev
);
1309 if (netif_running(netdev
))
1310 __qlcnic_down(adapter
, netdev
);
1312 qlcnic_detach(adapter
);
1314 adapter
->drv_sds_rings
= QLCNIC_SINGLE_RING
;
1315 adapter
->ahw
->diag_test
= test
;
1316 adapter
->ahw
->linkup
= 0;
1318 ret
= qlcnic_attach(adapter
);
1320 netif_device_attach(netdev
);
1324 ret
= qlcnic_fw_create_ctx(adapter
);
1326 qlcnic_detach(adapter
);
1327 if (adapter_state
== QLCNIC_ADAPTER_UP_MAGIC
) {
1328 adapter
->drv_sds_rings
= num_sds_ring
;
1329 qlcnic_attach(adapter
);
1331 netif_device_attach(netdev
);
1335 for (ring
= 0; ring
< adapter
->max_rds_rings
; ring
++) {
1336 rds_ring
= &adapter
->recv_ctx
->rds_rings
[ring
];
1337 qlcnic_post_rx_buffers(adapter
, rds_ring
, ring
);
1340 if (adapter
->ahw
->diag_test
== QLCNIC_INTERRUPT_TEST
) {
1341 for (ring
= 0; ring
< adapter
->drv_sds_rings
; ring
++) {
1342 sds_ring
= &adapter
->recv_ctx
->sds_rings
[ring
];
1343 qlcnic_83xx_enable_intr(adapter
, sds_ring
);
1347 if (adapter
->ahw
->diag_test
== QLCNIC_LOOPBACK_TEST
) {
1348 /* disable and free mailbox interrupt */
1349 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
)) {
1350 qlcnic_83xx_enable_mbx_poll(adapter
);
1351 qlcnic_83xx_free_mbx_intr(adapter
);
1353 adapter
->ahw
->loopback_state
= 0;
1354 adapter
->ahw
->hw_ops
->setup_link_event(adapter
, 1);
1357 set_bit(__QLCNIC_DEV_UP
, &adapter
->state
);
1361 static void qlcnic_83xx_diag_free_res(struct net_device
*netdev
,
1364 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1365 struct qlcnic_host_sds_ring
*sds_ring
;
1368 clear_bit(__QLCNIC_DEV_UP
, &adapter
->state
);
1369 if (adapter
->ahw
->diag_test
== QLCNIC_INTERRUPT_TEST
) {
1370 for (ring
= 0; ring
< adapter
->drv_sds_rings
; ring
++) {
1371 sds_ring
= &adapter
->recv_ctx
->sds_rings
[ring
];
1372 qlcnic_83xx_disable_intr(adapter
, sds_ring
);
1373 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
1374 qlcnic_83xx_enable_mbx_poll(adapter
);
1378 qlcnic_fw_destroy_ctx(adapter
);
1379 qlcnic_detach(adapter
);
1381 if (adapter
->ahw
->diag_test
== QLCNIC_LOOPBACK_TEST
) {
1382 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
)) {
1383 err
= qlcnic_83xx_setup_mbx_intr(adapter
);
1384 qlcnic_83xx_disable_mbx_poll(adapter
);
1386 dev_err(&adapter
->pdev
->dev
,
1387 "%s: failed to setup mbx interrupt\n",
1393 adapter
->ahw
->diag_test
= 0;
1394 adapter
->drv_sds_rings
= drv_sds_rings
;
1396 if (qlcnic_attach(adapter
))
1399 if (netif_running(netdev
))
1400 __qlcnic_up(adapter
, netdev
);
1402 if (adapter
->ahw
->diag_test
== QLCNIC_INTERRUPT_TEST
&&
1403 !(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
1404 qlcnic_83xx_disable_mbx_poll(adapter
);
1406 netif_device_attach(netdev
);
1409 int qlcnic_83xx_config_led(struct qlcnic_adapter
*adapter
, u32 state
,
1412 struct qlcnic_cmd_args cmd
;
1417 /* Get LED configuration */
1418 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1419 QLCNIC_CMD_GET_LED_CONFIG
);
1423 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1425 dev_err(&adapter
->pdev
->dev
,
1426 "Get led config failed.\n");
1429 for (i
= 0; i
< 4; i
++)
1430 adapter
->ahw
->mbox_reg
[i
] = cmd
.rsp
.arg
[i
+1];
1432 qlcnic_free_mbx_args(&cmd
);
1433 /* Set LED Configuration */
1434 mbx_in
= (LSW(QLC_83XX_LED_CONFIG
) << 16) |
1435 LSW(QLC_83XX_LED_CONFIG
);
1436 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1437 QLCNIC_CMD_SET_LED_CONFIG
);
1441 cmd
.req
.arg
[1] = mbx_in
;
1442 cmd
.req
.arg
[2] = mbx_in
;
1443 cmd
.req
.arg
[3] = mbx_in
;
1445 cmd
.req
.arg
[4] = QLC_83XX_ENABLE_BEACON
;
1446 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1448 dev_err(&adapter
->pdev
->dev
,
1449 "Set led config failed.\n");
1452 qlcnic_free_mbx_args(&cmd
);
1456 /* Restoring default LED configuration */
1457 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1458 QLCNIC_CMD_SET_LED_CONFIG
);
1462 cmd
.req
.arg
[1] = adapter
->ahw
->mbox_reg
[0];
1463 cmd
.req
.arg
[2] = adapter
->ahw
->mbox_reg
[1];
1464 cmd
.req
.arg
[3] = adapter
->ahw
->mbox_reg
[2];
1466 cmd
.req
.arg
[4] = adapter
->ahw
->mbox_reg
[3];
1467 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1469 dev_err(&adapter
->pdev
->dev
,
1470 "Restoring led config failed.\n");
1471 qlcnic_free_mbx_args(&cmd
);
1476 int qlcnic_83xx_set_led(struct net_device
*netdev
,
1477 enum ethtool_phys_id_state state
)
1479 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1480 int err
= -EIO
, active
= 1;
1482 if (adapter
->ahw
->op_mode
== QLCNIC_NON_PRIV_FUNC
) {
1484 "LED test is not supported in non-privileged mode\n");
1489 case ETHTOOL_ID_ACTIVE
:
1490 if (test_and_set_bit(__QLCNIC_LED_ENABLE
, &adapter
->state
))
1493 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
))
1496 err
= qlcnic_83xx_config_led(adapter
, active
, 0);
1498 netdev_err(netdev
, "Failed to set LED blink state\n");
1500 case ETHTOOL_ID_INACTIVE
:
1503 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
))
1506 err
= qlcnic_83xx_config_led(adapter
, active
, 0);
1508 netdev_err(netdev
, "Failed to reset LED blink state\n");
1516 clear_bit(__QLCNIC_LED_ENABLE
, &adapter
->state
);
1521 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter
*adapter
,
1524 struct qlcnic_cmd_args cmd
;
1527 if (qlcnic_sriov_vf_check(adapter
))
1531 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1532 QLCNIC_CMD_INIT_NIC_FUNC
);
1536 cmd
.req
.arg
[1] = BIT_0
| BIT_31
;
1538 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1539 QLCNIC_CMD_STOP_NIC_FUNC
);
1543 cmd
.req
.arg
[1] = BIT_0
| BIT_31
;
1545 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1547 dev_err(&adapter
->pdev
->dev
,
1548 "Failed to %s in NIC IDC function event.\n",
1549 (enable
? "register" : "unregister"));
1551 qlcnic_free_mbx_args(&cmd
);
1554 int qlcnic_83xx_set_port_config(struct qlcnic_adapter
*adapter
)
1556 struct qlcnic_cmd_args cmd
;
1559 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_SET_PORT_CONFIG
);
1563 cmd
.req
.arg
[1] = adapter
->ahw
->port_config
;
1564 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1566 dev_info(&adapter
->pdev
->dev
, "Set Port Config failed.\n");
1567 qlcnic_free_mbx_args(&cmd
);
1571 int qlcnic_83xx_get_port_config(struct qlcnic_adapter
*adapter
)
1573 struct qlcnic_cmd_args cmd
;
1576 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_PORT_CONFIG
);
1580 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1582 dev_info(&adapter
->pdev
->dev
, "Get Port config failed\n");
1584 adapter
->ahw
->port_config
= cmd
.rsp
.arg
[1];
1585 qlcnic_free_mbx_args(&cmd
);
1589 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter
*adapter
, int enable
)
1593 struct qlcnic_cmd_args cmd
;
1595 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_LINK_EVENT
);
1599 temp
= adapter
->recv_ctx
->context_id
<< 16;
1600 cmd
.req
.arg
[1] = (enable
? 1 : 0) | BIT_8
| temp
;
1601 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1603 dev_info(&adapter
->pdev
->dev
,
1604 "Setup linkevent mailbox failed\n");
1605 qlcnic_free_mbx_args(&cmd
);
1609 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter
*adapter
,
1612 if (qlcnic_sriov_pf_check(adapter
)) {
1613 qlcnic_pf_set_interface_id_promisc(adapter
, interface_id
);
1615 if (!qlcnic_sriov_vf_check(adapter
))
1616 *interface_id
= adapter
->recv_ctx
->context_id
<< 16;
1620 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter
*adapter
, u32 mode
)
1622 struct qlcnic_cmd_args
*cmd
= NULL
;
1626 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
1629 cmd
= kzalloc(sizeof(*cmd
), GFP_ATOMIC
);
1633 err
= qlcnic_alloc_mbx_args(cmd
, adapter
,
1634 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE
);
1638 cmd
->type
= QLC_83XX_MBX_CMD_NO_WAIT
;
1639 qlcnic_83xx_set_interface_id_promisc(adapter
, &temp
);
1640 cmd
->req
.arg
[1] = (mode
? 1 : 0) | temp
;
1641 err
= qlcnic_issue_cmd(adapter
, cmd
);
1645 qlcnic_free_mbx_args(cmd
);
1652 int qlcnic_83xx_loopback_test(struct net_device
*netdev
, u8 mode
)
1654 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1655 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1656 u8 drv_sds_rings
= adapter
->drv_sds_rings
;
1657 u8 drv_tx_rings
= adapter
->drv_tx_rings
;
1658 int ret
= 0, loop
= 0;
1660 if (ahw
->op_mode
== QLCNIC_NON_PRIV_FUNC
) {
1662 "Loopback test not supported in non privileged mode\n");
1666 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1667 netdev_info(netdev
, "Device is resetting\n");
1671 if (qlcnic_get_diag_lock(adapter
)) {
1672 netdev_info(netdev
, "Device is in diagnostics mode\n");
1676 netdev_info(netdev
, "%s loopback test in progress\n",
1677 mode
== QLCNIC_ILB_MODE
? "internal" : "external");
1679 ret
= qlcnic_83xx_diag_alloc_res(netdev
, QLCNIC_LOOPBACK_TEST
,
1682 goto fail_diag_alloc
;
1684 ret
= qlcnic_83xx_set_lb_mode(adapter
, mode
);
1688 /* Poll for link up event before running traffic */
1690 msleep(QLC_83XX_LB_MSLEEP_COUNT
);
1692 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1694 "Device is resetting, free LB test resources\n");
1698 if (loop
++ > QLC_83XX_LB_WAIT_COUNT
) {
1700 "Firmware didn't sent link up event to loopback request\n");
1702 qlcnic_83xx_clear_lb_mode(adapter
, mode
);
1705 } while ((adapter
->ahw
->linkup
&& ahw
->has_link_events
) != 1);
1707 /* Make sure carrier is off and queue is stopped during loopback */
1708 if (netif_running(netdev
)) {
1709 netif_carrier_off(netdev
);
1710 netif_tx_stop_all_queues(netdev
);
1713 ret
= qlcnic_do_lb_test(adapter
, mode
);
1715 qlcnic_83xx_clear_lb_mode(adapter
, mode
);
1718 qlcnic_83xx_diag_free_res(netdev
, drv_sds_rings
);
1721 adapter
->drv_sds_rings
= drv_sds_rings
;
1722 adapter
->drv_tx_rings
= drv_tx_rings
;
1723 qlcnic_release_diag_lock(adapter
);
1727 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter
*adapter
,
1728 u32
*max_wait_count
)
1730 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1733 netdev_info(adapter
->netdev
, "Received loopback IDC time extend event for 0x%x seconds\n",
1734 ahw
->extend_lb_time
);
1735 temp
= ahw
->extend_lb_time
* 1000;
1736 *max_wait_count
+= temp
/ QLC_83XX_LB_MSLEEP_COUNT
;
1737 ahw
->extend_lb_time
= 0;
1740 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter
*adapter
, u8 mode
)
1742 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1743 struct net_device
*netdev
= adapter
->netdev
;
1744 u32 config
, max_wait_count
;
1745 int status
= 0, loop
= 0;
1747 ahw
->extend_lb_time
= 0;
1748 max_wait_count
= QLC_83XX_LB_WAIT_COUNT
;
1749 status
= qlcnic_83xx_get_port_config(adapter
);
1753 config
= ahw
->port_config
;
1755 /* Check if port is already in loopback mode */
1756 if ((config
& QLC_83XX_CFG_LOOPBACK_HSS
) ||
1757 (config
& QLC_83XX_CFG_LOOPBACK_EXT
)) {
1759 "Port already in Loopback mode.\n");
1760 return -EINPROGRESS
;
1763 set_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1765 if (mode
== QLCNIC_ILB_MODE
)
1766 ahw
->port_config
|= QLC_83XX_CFG_LOOPBACK_HSS
;
1767 if (mode
== QLCNIC_ELB_MODE
)
1768 ahw
->port_config
|= QLC_83XX_CFG_LOOPBACK_EXT
;
1770 status
= qlcnic_83xx_set_port_config(adapter
);
1773 "Failed to Set Loopback Mode = 0x%x.\n",
1775 ahw
->port_config
= config
;
1776 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1780 /* Wait for Link and IDC Completion AEN */
1782 msleep(QLC_83XX_LB_MSLEEP_COUNT
);
1784 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1786 "Device is resetting, free LB test resources\n");
1787 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1791 if (ahw
->extend_lb_time
)
1792 qlcnic_extend_lb_idc_cmpltn_wait(adapter
,
1795 if (loop
++ > max_wait_count
) {
1796 netdev_err(netdev
, "%s: Did not receive loopback IDC completion AEN\n",
1798 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1799 qlcnic_83xx_clear_lb_mode(adapter
, mode
);
1802 } while (test_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
));
1804 qlcnic_sre_macaddr_change(adapter
, adapter
->mac_addr
, 0,
1809 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter
*adapter
, u8 mode
)
1811 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1812 u32 config
= ahw
->port_config
, max_wait_count
;
1813 struct net_device
*netdev
= adapter
->netdev
;
1814 int status
= 0, loop
= 0;
1816 ahw
->extend_lb_time
= 0;
1817 max_wait_count
= QLC_83XX_LB_WAIT_COUNT
;
1818 set_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1819 if (mode
== QLCNIC_ILB_MODE
)
1820 ahw
->port_config
&= ~QLC_83XX_CFG_LOOPBACK_HSS
;
1821 if (mode
== QLCNIC_ELB_MODE
)
1822 ahw
->port_config
&= ~QLC_83XX_CFG_LOOPBACK_EXT
;
1824 status
= qlcnic_83xx_set_port_config(adapter
);
1827 "Failed to Clear Loopback Mode = 0x%x.\n",
1829 ahw
->port_config
= config
;
1830 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1834 /* Wait for Link and IDC Completion AEN */
1836 msleep(QLC_83XX_LB_MSLEEP_COUNT
);
1838 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1840 "Device is resetting, free LB test resources\n");
1841 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1845 if (ahw
->extend_lb_time
)
1846 qlcnic_extend_lb_idc_cmpltn_wait(adapter
,
1849 if (loop
++ > max_wait_count
) {
1850 netdev_err(netdev
, "%s: Did not receive loopback IDC completion AEN\n",
1852 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1855 } while (test_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
));
1857 qlcnic_sre_macaddr_change(adapter
, adapter
->mac_addr
, 0,
1862 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter
*adapter
,
1865 if (qlcnic_sriov_pf_check(adapter
)) {
1866 qlcnic_pf_set_interface_id_ipaddr(adapter
, interface_id
);
1868 if (!qlcnic_sriov_vf_check(adapter
))
1869 *interface_id
= adapter
->recv_ctx
->context_id
<< 16;
1873 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter
*adapter
, __be32 ip
,
1877 u32 temp
= 0, temp_ip
;
1878 struct qlcnic_cmd_args cmd
;
1880 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1881 QLCNIC_CMD_CONFIGURE_IP_ADDR
);
1885 qlcnic_83xx_set_interface_id_ipaddr(adapter
, &temp
);
1887 if (mode
== QLCNIC_IP_UP
)
1888 cmd
.req
.arg
[1] = 1 | temp
;
1890 cmd
.req
.arg
[1] = 2 | temp
;
1893 * Adapter needs IP address in network byte order.
1894 * But hardware mailbox registers go through writel(), hence IP address
1895 * gets swapped on big endian architecture.
1896 * To negate swapping of writel() on big endian architecture
1897 * use swab32(value).
1900 temp_ip
= swab32(ntohl(ip
));
1901 memcpy(&cmd
.req
.arg
[2], &temp_ip
, sizeof(u32
));
1902 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1903 if (err
!= QLCNIC_RCODE_SUCCESS
)
1904 dev_err(&adapter
->netdev
->dev
,
1905 "could not notify %s IP 0x%x request\n",
1906 (mode
== QLCNIC_IP_UP
) ? "Add" : "Remove", ip
);
1908 qlcnic_free_mbx_args(&cmd
);
1911 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter
*adapter
, int mode
)
1915 struct qlcnic_cmd_args cmd
;
1918 lro_bit_mask
= (mode
? (BIT_0
| BIT_1
| BIT_2
| BIT_3
) : 0);
1920 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
1923 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIGURE_HW_LRO
);
1927 temp
= adapter
->recv_ctx
->context_id
<< 16;
1928 arg1
= lro_bit_mask
| temp
;
1929 cmd
.req
.arg
[1] = arg1
;
1931 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1933 dev_info(&adapter
->pdev
->dev
, "LRO config failed\n");
1934 qlcnic_free_mbx_args(&cmd
);
1939 int qlcnic_83xx_config_rss(struct qlcnic_adapter
*adapter
, int enable
)
1943 struct qlcnic_cmd_args cmd
;
1944 const u64 key
[] = { 0xbeac01fa6a42b73bULL
, 0x8030f20c77cb2da3ULL
,
1945 0xae7b30b4d0ca2bcbULL
, 0x43a38fb04167253dULL
,
1946 0x255b0ec26d5a56daULL
};
1948 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIGURE_RSS
);
1954 * 5-4: hash_type_ipv4
1955 * 7-6: hash_type_ipv6
1957 * 9: use indirection table
1958 * 16-31: indirection table mask
1960 word
= ((u32
)(RSS_HASHTYPE_IP_TCP
& 0x3) << 4) |
1961 ((u32
)(RSS_HASHTYPE_IP_TCP
& 0x3) << 6) |
1962 ((u32
)(enable
& 0x1) << 8) |
1964 cmd
.req
.arg
[1] = (adapter
->recv_ctx
->context_id
);
1965 cmd
.req
.arg
[2] = word
;
1966 memcpy(&cmd
.req
.arg
[4], key
, sizeof(key
));
1968 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1971 dev_info(&adapter
->pdev
->dev
, "RSS config failed\n");
1972 qlcnic_free_mbx_args(&cmd
);
1978 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter
*adapter
,
1981 if (qlcnic_sriov_pf_check(adapter
)) {
1982 qlcnic_pf_set_interface_id_macaddr(adapter
, interface_id
);
1984 if (!qlcnic_sriov_vf_check(adapter
))
1985 *interface_id
= adapter
->recv_ctx
->context_id
<< 16;
1989 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter
*adapter
, u8
*addr
,
1992 struct qlcnic_cmd_args
*cmd
= NULL
;
1993 struct qlcnic_macvlan_mbx mv
;
1997 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
2000 cmd
= kzalloc(sizeof(*cmd
), GFP_ATOMIC
);
2004 err
= qlcnic_alloc_mbx_args(cmd
, adapter
, QLCNIC_CMD_CONFIG_MAC_VLAN
);
2008 cmd
->type
= QLC_83XX_MBX_CMD_NO_WAIT
;
2011 op
= (op
== QLCNIC_MAC_ADD
|| op
== QLCNIC_MAC_VLAN_ADD
) ?
2012 QLCNIC_MAC_VLAN_ADD
: QLCNIC_MAC_VLAN_DEL
;
2014 cmd
->req
.arg
[1] = op
| (1 << 8);
2015 qlcnic_83xx_set_interface_id_macaddr(adapter
, &temp
);
2016 cmd
->req
.arg
[1] |= temp
;
2018 mv
.mac_addr0
= addr
[0];
2019 mv
.mac_addr1
= addr
[1];
2020 mv
.mac_addr2
= addr
[2];
2021 mv
.mac_addr3
= addr
[3];
2022 mv
.mac_addr4
= addr
[4];
2023 mv
.mac_addr5
= addr
[5];
2024 buf
= &cmd
->req
.arg
[2];
2025 memcpy(buf
, &mv
, sizeof(struct qlcnic_macvlan_mbx
));
2026 err
= qlcnic_issue_cmd(adapter
, cmd
);
2030 qlcnic_free_mbx_args(cmd
);
2036 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter
*adapter
, u64
*addr
,
2040 memcpy(&mac
, addr
, ETH_ALEN
);
2041 qlcnic_83xx_sre_macaddr_change(adapter
, mac
, vlan_id
, QLCNIC_MAC_ADD
);
2044 void qlcnic_83xx_configure_mac(struct qlcnic_adapter
*adapter
, u8
*mac
,
2045 u8 type
, struct qlcnic_cmd_args
*cmd
)
2048 case QLCNIC_SET_STATION_MAC
:
2049 case QLCNIC_SET_FAC_DEF_MAC
:
2050 memcpy(&cmd
->req
.arg
[2], mac
, sizeof(u32
));
2051 memcpy(&cmd
->req
.arg
[3], &mac
[4], sizeof(u16
));
2054 cmd
->req
.arg
[1] = type
;
2057 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter
*adapter
, u8
*mac
,
2061 struct qlcnic_cmd_args cmd
;
2062 u32 mac_low
, mac_high
;
2065 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_MAC_ADDRESS
);
2069 qlcnic_83xx_configure_mac(adapter
, mac
, QLCNIC_GET_CURRENT_MAC
, &cmd
);
2070 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2072 if (err
== QLCNIC_RCODE_SUCCESS
) {
2073 mac_low
= cmd
.rsp
.arg
[1];
2074 mac_high
= cmd
.rsp
.arg
[2];
2076 for (i
= 0; i
< 2; i
++)
2077 mac
[i
] = (u8
) (mac_high
>> ((1 - i
) * 8));
2078 for (i
= 2; i
< 6; i
++)
2079 mac
[i
] = (u8
) (mac_low
>> ((5 - i
) * 8));
2081 dev_err(&adapter
->pdev
->dev
, "Failed to get mac address%d\n",
2085 qlcnic_free_mbx_args(&cmd
);
2089 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter
*adapter
)
2093 struct qlcnic_cmd_args cmd
;
2094 struct qlcnic_nic_intr_coalesce
*coal
= &adapter
->ahw
->coal
;
2096 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
2099 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIG_INTR_COAL
);
2103 if (coal
->type
== QLCNIC_INTR_COAL_TYPE_RX
) {
2104 temp
= adapter
->recv_ctx
->context_id
;
2105 cmd
.req
.arg
[1] = QLCNIC_INTR_COAL_TYPE_RX
| temp
<< 16;
2106 temp
= coal
->rx_time_us
;
2107 cmd
.req
.arg
[2] = coal
->rx_packets
| temp
<< 16;
2108 } else if (coal
->type
== QLCNIC_INTR_COAL_TYPE_TX
) {
2109 temp
= adapter
->tx_ring
->ctx_id
;
2110 cmd
.req
.arg
[1] = QLCNIC_INTR_COAL_TYPE_TX
| temp
<< 16;
2111 temp
= coal
->tx_time_us
;
2112 cmd
.req
.arg
[2] = coal
->tx_packets
| temp
<< 16;
2114 cmd
.req
.arg
[3] = coal
->flag
;
2115 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2116 if (err
!= QLCNIC_RCODE_SUCCESS
)
2117 dev_info(&adapter
->pdev
->dev
,
2118 "Failed to send interrupt coalescence parameters\n");
2119 qlcnic_free_mbx_args(&cmd
);
2122 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter
*adapter
,
2125 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2126 u8 link_status
, duplex
;
2128 link_status
= LSB(data
[3]) & 1;
2130 ahw
->link_speed
= MSW(data
[2]);
2131 duplex
= LSB(MSW(data
[3]));
2133 ahw
->link_duplex
= DUPLEX_FULL
;
2135 ahw
->link_duplex
= DUPLEX_HALF
;
2137 ahw
->link_speed
= SPEED_UNKNOWN
;
2138 ahw
->link_duplex
= DUPLEX_UNKNOWN
;
2141 ahw
->link_autoneg
= MSB(MSW(data
[3]));
2142 ahw
->module_type
= MSB(LSW(data
[3]));
2143 ahw
->has_link_events
= 1;
2144 qlcnic_advert_link_change(adapter
, link_status
);
2147 irqreturn_t
qlcnic_83xx_handle_aen(int irq
, void *data
)
2149 struct qlcnic_adapter
*adapter
= data
;
2150 struct qlcnic_mailbox
*mbx
;
2151 u32 mask
, resp
, event
;
2152 unsigned long flags
;
2154 mbx
= adapter
->ahw
->mailbox
;
2155 spin_lock_irqsave(&mbx
->aen_lock
, flags
);
2156 resp
= QLCRDX(adapter
->ahw
, QLCNIC_FW_MBX_CTRL
);
2157 if (!(resp
& QLCNIC_SET_OWNER
))
2160 event
= readl(QLCNIC_MBX_FW(adapter
->ahw
, 0));
2161 if (event
& QLCNIC_MBX_ASYNC_EVENT
)
2162 __qlcnic_83xx_process_aen(adapter
);
2164 qlcnic_83xx_notify_mbx_response(mbx
);
2167 mask
= QLCRDX(adapter
->ahw
, QLCNIC_DEF_INT_MASK
);
2168 writel(0, adapter
->ahw
->pci_base0
+ mask
);
2169 spin_unlock_irqrestore(&mbx
->aen_lock
, flags
);
2173 int qlcnic_enable_eswitch(struct qlcnic_adapter
*adapter
, u8 port
, u8 enable
)
2176 struct qlcnic_cmd_args cmd
;
2178 if (adapter
->ahw
->op_mode
!= QLCNIC_MGMT_FUNC
) {
2179 dev_err(&adapter
->pdev
->dev
,
2180 "%s: Error, invoked by non management func\n",
2185 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_TOGGLE_ESWITCH
);
2189 cmd
.req
.arg
[1] = (port
& 0xf) | BIT_4
;
2190 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2192 if (err
!= QLCNIC_RCODE_SUCCESS
) {
2193 dev_err(&adapter
->pdev
->dev
, "Failed to enable eswitch%d\n",
2197 qlcnic_free_mbx_args(&cmd
);
2203 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter
*adapter
,
2204 struct qlcnic_info
*nic
)
2207 struct qlcnic_cmd_args cmd
;
2209 if (adapter
->ahw
->op_mode
!= QLCNIC_MGMT_FUNC
) {
2210 dev_err(&adapter
->pdev
->dev
,
2211 "%s: Error, invoked by non management func\n",
2216 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_SET_NIC_INFO
);
2220 cmd
.req
.arg
[1] = (nic
->pci_func
<< 16);
2221 cmd
.req
.arg
[2] = 0x1 << 16;
2222 cmd
.req
.arg
[3] = nic
->phys_port
| (nic
->switch_mode
<< 16);
2223 cmd
.req
.arg
[4] = nic
->capabilities
;
2224 cmd
.req
.arg
[5] = (nic
->max_mac_filters
& 0xFF) | ((nic
->max_mtu
) << 16);
2225 cmd
.req
.arg
[6] = (nic
->max_tx_ques
) | ((nic
->max_rx_ques
) << 16);
2226 cmd
.req
.arg
[7] = (nic
->min_tx_bw
) | ((nic
->max_tx_bw
) << 16);
2227 for (i
= 8; i
< 32; i
++)
2230 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2232 if (err
!= QLCNIC_RCODE_SUCCESS
) {
2233 dev_err(&adapter
->pdev
->dev
, "Failed to set nic info%d\n",
2238 qlcnic_free_mbx_args(&cmd
);
2243 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter
*adapter
,
2244 struct qlcnic_info
*npar_info
, u8 func_id
)
2249 struct qlcnic_cmd_args cmd
;
2250 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2252 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_NIC_INFO
);
2256 if (func_id
!= ahw
->pci_func
) {
2257 temp
= func_id
<< 16;
2258 cmd
.req
.arg
[1] = op
| BIT_31
| temp
;
2260 cmd
.req
.arg
[1] = ahw
->pci_func
<< 16;
2262 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2264 dev_info(&adapter
->pdev
->dev
,
2265 "Failed to get nic info %d\n", err
);
2269 npar_info
->op_type
= cmd
.rsp
.arg
[1];
2270 npar_info
->pci_func
= cmd
.rsp
.arg
[2] & 0xFFFF;
2271 npar_info
->op_mode
= (cmd
.rsp
.arg
[2] & 0xFFFF0000) >> 16;
2272 npar_info
->phys_port
= cmd
.rsp
.arg
[3] & 0xFFFF;
2273 npar_info
->switch_mode
= (cmd
.rsp
.arg
[3] & 0xFFFF0000) >> 16;
2274 npar_info
->capabilities
= cmd
.rsp
.arg
[4];
2275 npar_info
->max_mac_filters
= cmd
.rsp
.arg
[5] & 0xFF;
2276 npar_info
->max_mtu
= (cmd
.rsp
.arg
[5] & 0xFFFF0000) >> 16;
2277 npar_info
->max_tx_ques
= cmd
.rsp
.arg
[6] & 0xFFFF;
2278 npar_info
->max_rx_ques
= (cmd
.rsp
.arg
[6] & 0xFFFF0000) >> 16;
2279 npar_info
->min_tx_bw
= cmd
.rsp
.arg
[7] & 0xFFFF;
2280 npar_info
->max_tx_bw
= (cmd
.rsp
.arg
[7] & 0xFFFF0000) >> 16;
2281 if (cmd
.rsp
.arg
[8] & 0x1)
2282 npar_info
->max_bw_reg_offset
= (cmd
.rsp
.arg
[8] & 0x7FFE) >> 1;
2283 if (cmd
.rsp
.arg
[8] & 0x10000) {
2284 temp
= (cmd
.rsp
.arg
[8] & 0x7FFE0000) >> 17;
2285 npar_info
->max_linkspeed_reg_offset
= temp
;
2288 memcpy(ahw
->extra_capability
, &cmd
.rsp
.arg
[16],
2289 sizeof(ahw
->extra_capability
));
2292 qlcnic_free_mbx_args(&cmd
);
2296 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter
*adapter
,
2297 struct qlcnic_pci_info
*pci_info
)
2299 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2300 struct device
*dev
= &adapter
->pdev
->dev
;
2301 struct qlcnic_cmd_args cmd
;
2302 int i
, err
= 0, j
= 0;
2305 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_PCI_INFO
);
2309 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2311 ahw
->act_pci_func
= 0;
2312 if (err
== QLCNIC_RCODE_SUCCESS
) {
2313 ahw
->max_pci_func
= cmd
.rsp
.arg
[1] & 0xFF;
2314 for (i
= 2, j
= 0; j
< QLCNIC_MAX_PCI_FUNC
; j
++, pci_info
++) {
2315 pci_info
->id
= cmd
.rsp
.arg
[i
] & 0xFFFF;
2316 pci_info
->active
= (cmd
.rsp
.arg
[i
] & 0xFFFF0000) >> 16;
2318 pci_info
->type
= cmd
.rsp
.arg
[i
] & 0xFFFF;
2319 if (pci_info
->type
== QLCNIC_TYPE_NIC
)
2320 ahw
->act_pci_func
++;
2321 temp
= (cmd
.rsp
.arg
[i
] & 0xFFFF0000) >> 16;
2322 pci_info
->default_port
= temp
;
2324 pci_info
->tx_min_bw
= cmd
.rsp
.arg
[i
] & 0xFFFF;
2325 temp
= (cmd
.rsp
.arg
[i
] & 0xFFFF0000) >> 16;
2326 pci_info
->tx_max_bw
= temp
;
2328 memcpy(pci_info
->mac
, &cmd
.rsp
.arg
[i
], ETH_ALEN
- 2);
2330 memcpy(pci_info
->mac
+ sizeof(u32
), &cmd
.rsp
.arg
[i
], 2);
2334 dev_err(dev
, "Failed to get PCI Info, error = %d\n", err
);
2338 qlcnic_free_mbx_args(&cmd
);
2343 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter
*adapter
, bool op_type
)
2347 u32 val
, temp
, type
;
2348 struct qlcnic_cmd_args cmd
;
2350 max_ints
= adapter
->ahw
->num_msix
- 1;
2351 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIG_INTRPT
);
2355 cmd
.req
.arg
[1] = max_ints
;
2357 if (qlcnic_sriov_vf_check(adapter
))
2358 cmd
.req
.arg
[1] |= (adapter
->ahw
->pci_func
<< 8) | BIT_16
;
2360 for (i
= 0, index
= 2; i
< max_ints
; i
++) {
2361 type
= op_type
? QLCNIC_INTRPT_ADD
: QLCNIC_INTRPT_DEL
;
2362 val
= type
| (adapter
->ahw
->intr_tbl
[i
].type
<< 4);
2363 if (adapter
->ahw
->intr_tbl
[i
].type
== QLCNIC_INTRPT_MSIX
)
2364 val
|= (adapter
->ahw
->intr_tbl
[i
].id
<< 16);
2365 cmd
.req
.arg
[index
++] = val
;
2367 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2369 dev_err(&adapter
->pdev
->dev
,
2370 "Failed to configure interrupts 0x%x\n", err
);
2374 max_ints
= cmd
.rsp
.arg
[1];
2375 for (i
= 0, index
= 2; i
< max_ints
; i
++, index
+= 2) {
2376 val
= cmd
.rsp
.arg
[index
];
2378 dev_info(&adapter
->pdev
->dev
,
2379 "Can't configure interrupt %d\n",
2380 adapter
->ahw
->intr_tbl
[i
].id
);
2384 adapter
->ahw
->intr_tbl
[i
].id
= MSW(val
);
2385 adapter
->ahw
->intr_tbl
[i
].enabled
= 1;
2386 temp
= cmd
.rsp
.arg
[index
+ 1];
2387 adapter
->ahw
->intr_tbl
[i
].src
= temp
;
2389 adapter
->ahw
->intr_tbl
[i
].id
= i
;
2390 adapter
->ahw
->intr_tbl
[i
].enabled
= 0;
2391 adapter
->ahw
->intr_tbl
[i
].src
= 0;
2395 qlcnic_free_mbx_args(&cmd
);
2399 int qlcnic_83xx_lock_flash(struct qlcnic_adapter
*adapter
)
2401 int id
, timeout
= 0;
2404 while (status
== 0) {
2405 status
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FLASH_LOCK
);
2409 if (++timeout
>= QLC_83XX_FLASH_LOCK_TIMEOUT
) {
2410 id
= QLC_SHARED_REG_RD32(adapter
,
2411 QLCNIC_FLASH_LOCK_OWNER
);
2412 dev_err(&adapter
->pdev
->dev
,
2413 "%s: failed, lock held by %d\n", __func__
, id
);
2416 usleep_range(1000, 2000);
2419 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FLASH_LOCK_OWNER
, adapter
->portnum
);
2423 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter
*adapter
)
2425 QLC_SHARED_REG_RD32(adapter
, QLCNIC_FLASH_UNLOCK
);
2426 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FLASH_LOCK_OWNER
, 0xFF);
2429 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter
*adapter
,
2430 u32 flash_addr
, u8
*p_data
,
2433 u32 word
, range
, flash_offset
, addr
= flash_addr
, ret
;
2434 ulong indirect_add
, direct_window
;
2437 flash_offset
= addr
& (QLCNIC_FLASH_SECTOR_SIZE
- 1);
2439 dev_err(&adapter
->pdev
->dev
, "Illegal addr = 0x%x\n", addr
);
2443 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_DIRECT_WINDOW
,
2446 range
= flash_offset
+ (count
* sizeof(u32
));
2447 /* Check if data is spread across multiple sectors */
2448 if (range
> (QLCNIC_FLASH_SECTOR_SIZE
- 1)) {
2450 /* Multi sector read */
2451 for (i
= 0; i
< count
; i
++) {
2452 indirect_add
= QLC_83XX_FLASH_DIRECT_DATA(addr
);
2453 ret
= QLCRD32(adapter
, indirect_add
, &err
);
2458 *(u32
*)p_data
= word
;
2459 p_data
= p_data
+ 4;
2461 flash_offset
= flash_offset
+ 4;
2463 if (flash_offset
> (QLCNIC_FLASH_SECTOR_SIZE
- 1)) {
2464 direct_window
= QLC_83XX_FLASH_DIRECT_WINDOW
;
2465 /* This write is needed once for each sector */
2466 qlcnic_83xx_wrt_reg_indirect(adapter
,
2473 /* Single sector read */
2474 for (i
= 0; i
< count
; i
++) {
2475 indirect_add
= QLC_83XX_FLASH_DIRECT_DATA(addr
);
2476 ret
= QLCRD32(adapter
, indirect_add
, &err
);
2481 *(u32
*)p_data
= word
;
2482 p_data
= p_data
+ 4;
2490 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter
*adapter
)
2493 int retries
= QLC_83XX_FLASH_READ_RETRY_COUNT
;
2497 status
= QLCRD32(adapter
, QLC_83XX_FLASH_STATUS
, &err
);
2501 if ((status
& QLC_83XX_FLASH_STATUS_READY
) ==
2502 QLC_83XX_FLASH_STATUS_READY
)
2505 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY
);
2506 } while (--retries
);
2514 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter
*adapter
)
2518 cmd
= adapter
->ahw
->fdt
.write_statusreg_cmd
;
2519 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2520 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG
| cmd
));
2521 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2522 adapter
->ahw
->fdt
.write_enable_bits
);
2523 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2524 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL
);
2525 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2532 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter
*adapter
)
2536 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2537 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG
|
2538 adapter
->ahw
->fdt
.write_statusreg_cmd
));
2539 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2540 adapter
->ahw
->fdt
.write_disable_bits
);
2541 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2542 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL
);
2543 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2550 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter
*adapter
)
2555 if (qlcnic_83xx_lock_flash(adapter
))
2558 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2559 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL
);
2560 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2561 QLC_83XX_FLASH_READ_CTRL
);
2562 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2564 qlcnic_83xx_unlock_flash(adapter
);
2568 mfg_id
= QLCRD32(adapter
, QLC_83XX_FLASH_RDDATA
, &err
);
2570 qlcnic_83xx_unlock_flash(adapter
);
2574 adapter
->flash_mfg_id
= (mfg_id
& 0xFF);
2575 qlcnic_83xx_unlock_flash(adapter
);
2580 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter
*adapter
)
2582 int count
, fdt_size
, ret
= 0;
2584 fdt_size
= sizeof(struct qlcnic_fdt
);
2585 count
= fdt_size
/ sizeof(u32
);
2587 if (qlcnic_83xx_lock_flash(adapter
))
2590 memset(&adapter
->ahw
->fdt
, 0, fdt_size
);
2591 ret
= qlcnic_83xx_lockless_flash_read32(adapter
, QLCNIC_FDT_LOCATION
,
2592 (u8
*)&adapter
->ahw
->fdt
,
2595 qlcnic_83xx_unlock_flash(adapter
);
2599 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter
*adapter
,
2600 u32 sector_start_addr
)
2602 u32 reversed_addr
, addr1
, addr2
, cmd
;
2605 if (qlcnic_83xx_lock_flash(adapter
) != 0)
2608 if (adapter
->ahw
->fdt
.mfg_id
== adapter
->flash_mfg_id
) {
2609 ret
= qlcnic_83xx_enable_flash_write(adapter
);
2611 qlcnic_83xx_unlock_flash(adapter
);
2612 dev_err(&adapter
->pdev
->dev
,
2613 "%s failed at %d\n",
2614 __func__
, __LINE__
);
2619 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2621 qlcnic_83xx_unlock_flash(adapter
);
2622 dev_err(&adapter
->pdev
->dev
,
2623 "%s: failed at %d\n", __func__
, __LINE__
);
2627 addr1
= (sector_start_addr
& 0xFF) << 16;
2628 addr2
= (sector_start_addr
& 0xFF0000) >> 16;
2629 reversed_addr
= addr1
| addr2
;
2631 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2633 cmd
= QLC_83XX_FLASH_FDT_ERASE_DEF_SIG
| adapter
->ahw
->fdt
.erase_cmd
;
2634 if (adapter
->ahw
->fdt
.mfg_id
== adapter
->flash_mfg_id
)
2635 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
, cmd
);
2637 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2638 QLC_83XX_FLASH_OEM_ERASE_SIG
);
2639 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2640 QLC_83XX_FLASH_LAST_ERASE_MS_VAL
);
2642 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2644 qlcnic_83xx_unlock_flash(adapter
);
2645 dev_err(&adapter
->pdev
->dev
,
2646 "%s: failed at %d\n", __func__
, __LINE__
);
2650 if (adapter
->ahw
->fdt
.mfg_id
== adapter
->flash_mfg_id
) {
2651 ret
= qlcnic_83xx_disable_flash_write(adapter
);
2653 qlcnic_83xx_unlock_flash(adapter
);
2654 dev_err(&adapter
->pdev
->dev
,
2655 "%s: failed at %d\n", __func__
, __LINE__
);
2660 qlcnic_83xx_unlock_flash(adapter
);
2665 int qlcnic_83xx_flash_write32(struct qlcnic_adapter
*adapter
, u32 addr
,
2669 u32 addr1
= 0x00800000 | (addr
>> 2);
2671 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
, addr1
);
2672 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
, *p_data
);
2673 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2674 QLC_83XX_FLASH_LAST_ERASE_MS_VAL
);
2675 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2677 dev_err(&adapter
->pdev
->dev
,
2678 "%s: failed at %d\n", __func__
, __LINE__
);
2685 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter
*adapter
, u32 addr
,
2686 u32
*p_data
, int count
)
2689 int ret
= -EIO
, err
= 0;
2691 if ((count
< QLC_83XX_FLASH_WRITE_MIN
) ||
2692 (count
> QLC_83XX_FLASH_WRITE_MAX
)) {
2693 dev_err(&adapter
->pdev
->dev
,
2694 "%s: Invalid word count\n", __func__
);
2698 temp
= QLCRD32(adapter
, QLC_83XX_FLASH_SPI_CONTROL
, &err
);
2702 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_SPI_CONTROL
,
2703 (temp
| QLC_83XX_FLASH_SPI_CTRL
));
2704 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2705 QLC_83XX_FLASH_ADDR_TEMP_VAL
);
2707 /* First DWORD write */
2708 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
, *p_data
++);
2709 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2710 QLC_83XX_FLASH_FIRST_MS_PATTERN
);
2711 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2713 dev_err(&adapter
->pdev
->dev
,
2714 "%s: failed at %d\n", __func__
, __LINE__
);
2719 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2720 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL
);
2721 /* Second to N-1 DWORD writes */
2722 while (count
!= 1) {
2723 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2725 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2726 QLC_83XX_FLASH_SECOND_MS_PATTERN
);
2727 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2729 dev_err(&adapter
->pdev
->dev
,
2730 "%s: failed at %d\n", __func__
, __LINE__
);
2736 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2737 QLC_83XX_FLASH_ADDR_TEMP_VAL
|
2739 /* Last DWORD write */
2740 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
, *p_data
++);
2741 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2742 QLC_83XX_FLASH_LAST_MS_PATTERN
);
2743 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2745 dev_err(&adapter
->pdev
->dev
,
2746 "%s: failed at %d\n", __func__
, __LINE__
);
2750 ret
= QLCRD32(adapter
, QLC_83XX_FLASH_SPI_STATUS
, &err
);
2754 if ((ret
& QLC_83XX_FLASH_SPI_CTRL
) == QLC_83XX_FLASH_SPI_CTRL
) {
2755 dev_err(&adapter
->pdev
->dev
, "%s: failed at %d\n",
2756 __func__
, __LINE__
);
2757 /* Operation failed, clear error bit */
2758 temp
= QLCRD32(adapter
, QLC_83XX_FLASH_SPI_CONTROL
, &err
);
2762 qlcnic_83xx_wrt_reg_indirect(adapter
,
2763 QLC_83XX_FLASH_SPI_CONTROL
,
2764 (temp
| QLC_83XX_FLASH_SPI_CTRL
));
2770 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter
*adapter
)
2774 val
= QLCRDX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
);
2776 /* Check if recovery need to be performed by the calling function */
2777 if ((val
& QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK
) == 0) {
2779 val
= val
| ((adapter
->portnum
<< 2) |
2780 QLC_83XX_NEED_DRV_LOCK_RECOVERY
);
2781 QLCWRX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
, val
);
2782 dev_info(&adapter
->pdev
->dev
,
2783 "%s: lock recovery initiated\n", __func__
);
2784 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY
);
2785 val
= QLCRDX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
);
2786 id
= ((val
>> 2) & 0xF);
2787 if (id
== adapter
->portnum
) {
2788 val
= val
& ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK
;
2789 val
= val
| QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS
;
2790 QLCWRX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
, val
);
2791 /* Force release the lock */
2792 QLCRDX(adapter
->ahw
, QLC_83XX_DRV_UNLOCK
);
2793 /* Clear recovery bits */
2795 QLCWRX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
, val
);
2796 dev_info(&adapter
->pdev
->dev
,
2797 "%s: lock recovery completed\n", __func__
);
2799 dev_info(&adapter
->pdev
->dev
,
2800 "%s: func %d to resume lock recovery process\n",
2804 dev_info(&adapter
->pdev
->dev
,
2805 "%s: lock recovery initiated by other functions\n",
2810 int qlcnic_83xx_lock_driver(struct qlcnic_adapter
*adapter
)
2812 u32 lock_alive_counter
, val
, id
, i
= 0, status
= 0, temp
= 0;
2813 int max_attempt
= 0;
2815 while (status
== 0) {
2816 status
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK
);
2820 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY
);
2824 temp
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2826 if (i
== QLC_83XX_DRV_LOCK_WAIT_COUNTER
) {
2827 val
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2830 dev_info(&adapter
->pdev
->dev
,
2831 "%s: lock to be recovered from %d\n",
2833 qlcnic_83xx_recover_driver_lock(adapter
);
2837 dev_err(&adapter
->pdev
->dev
,
2838 "%s: failed to get lock\n", __func__
);
2843 /* Force exit from while loop after few attempts */
2844 if (max_attempt
== QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT
) {
2845 dev_err(&adapter
->pdev
->dev
,
2846 "%s: failed to get lock\n", __func__
);
2851 val
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2852 lock_alive_counter
= val
>> 8;
2853 lock_alive_counter
++;
2854 val
= lock_alive_counter
<< 8 | adapter
->portnum
;
2855 QLCWRX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
, val
);
2860 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter
*adapter
)
2862 u32 val
, lock_alive_counter
, id
;
2864 val
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2866 lock_alive_counter
= val
>> 8;
2868 if (id
!= adapter
->portnum
)
2869 dev_err(&adapter
->pdev
->dev
,
2870 "%s:Warning func %d is unlocking lock owned by %d\n",
2871 __func__
, adapter
->portnum
, id
);
2873 val
= (lock_alive_counter
<< 8) | 0xFF;
2874 QLCWRX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
, val
);
2875 QLCRDX(adapter
->ahw
, QLC_83XX_DRV_UNLOCK
);
2878 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter
*adapter
, u64 addr
,
2879 u32
*data
, u32 count
)
2885 /* Check alignment */
2889 mutex_lock(&adapter
->ahw
->mem_lock
);
2890 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_ADDR_HI
, 0);
2892 for (i
= 0; i
< count
; i
++, addr
+= 16) {
2893 if (!((ADDR_IN_RANGE(addr
, QLCNIC_ADDR_QDR_NET
,
2894 QLCNIC_ADDR_QDR_NET_MAX
)) ||
2895 (ADDR_IN_RANGE(addr
, QLCNIC_ADDR_DDR_NET
,
2896 QLCNIC_ADDR_DDR_NET_MAX
)))) {
2897 mutex_unlock(&adapter
->ahw
->mem_lock
);
2901 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_ADDR_LO
, addr
);
2902 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_LO
,
2904 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_HI
,
2906 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_ULO
,
2908 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_UHI
,
2910 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_CTRL
,
2911 QLCNIC_TA_WRITE_ENABLE
);
2912 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_CTRL
,
2913 QLCNIC_TA_WRITE_START
);
2915 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
2916 temp
= QLCRD32(adapter
, QLCNIC_MS_CTRL
, &err
);
2918 mutex_unlock(&adapter
->ahw
->mem_lock
);
2922 if ((temp
& TA_CTL_BUSY
) == 0)
2926 /* Status check failure */
2927 if (j
>= MAX_CTL_CHECK
) {
2928 printk_ratelimited(KERN_WARNING
2929 "MS memory write failed\n");
2930 mutex_unlock(&adapter
->ahw
->mem_lock
);
2935 mutex_unlock(&adapter
->ahw
->mem_lock
);
2940 int qlcnic_83xx_flash_read32(struct qlcnic_adapter
*adapter
, u32 flash_addr
,
2941 u8
*p_data
, int count
)
2943 u32 word
, addr
= flash_addr
, ret
;
2944 ulong indirect_addr
;
2947 if (qlcnic_83xx_lock_flash(adapter
) != 0)
2951 dev_err(&adapter
->pdev
->dev
, "Illegal addr = 0x%x\n", addr
);
2952 qlcnic_83xx_unlock_flash(adapter
);
2956 for (i
= 0; i
< count
; i
++) {
2957 if (qlcnic_83xx_wrt_reg_indirect(adapter
,
2958 QLC_83XX_FLASH_DIRECT_WINDOW
,
2960 qlcnic_83xx_unlock_flash(adapter
);
2964 indirect_addr
= QLC_83XX_FLASH_DIRECT_DATA(addr
);
2965 ret
= QLCRD32(adapter
, indirect_addr
, &err
);
2970 *(u32
*)p_data
= word
;
2971 p_data
= p_data
+ 4;
2975 qlcnic_83xx_unlock_flash(adapter
);
2980 int qlcnic_83xx_test_link(struct qlcnic_adapter
*adapter
)
2984 u32 config
= 0, state
;
2985 struct qlcnic_cmd_args cmd
;
2986 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2988 if (qlcnic_sriov_vf_check(adapter
))
2989 pci_func
= adapter
->portnum
;
2991 pci_func
= ahw
->pci_func
;
2993 state
= readl(ahw
->pci_base0
+ QLC_83XX_LINK_STATE(pci_func
));
2994 if (!QLC_83xx_FUNC_VAL(state
, pci_func
)) {
2995 dev_info(&adapter
->pdev
->dev
, "link state down\n");
2999 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_LINK_STATUS
);
3003 err
= qlcnic_issue_cmd(adapter
, &cmd
);
3005 dev_info(&adapter
->pdev
->dev
,
3006 "Get Link Status Command failed: 0x%x\n", err
);
3009 config
= cmd
.rsp
.arg
[1];
3010 switch (QLC_83XX_CURRENT_LINK_SPEED(config
)) {
3011 case QLC_83XX_10M_LINK
:
3012 ahw
->link_speed
= SPEED_10
;
3014 case QLC_83XX_100M_LINK
:
3015 ahw
->link_speed
= SPEED_100
;
3017 case QLC_83XX_1G_LINK
:
3018 ahw
->link_speed
= SPEED_1000
;
3020 case QLC_83XX_10G_LINK
:
3021 ahw
->link_speed
= SPEED_10000
;
3024 ahw
->link_speed
= 0;
3027 config
= cmd
.rsp
.arg
[3];
3028 if (QLC_83XX_SFP_PRESENT(config
)) {
3029 switch (ahw
->module_type
) {
3030 case LINKEVENT_MODULE_OPTICAL_UNKNOWN
:
3031 case LINKEVENT_MODULE_OPTICAL_SRLR
:
3032 case LINKEVENT_MODULE_OPTICAL_LRM
:
3033 case LINKEVENT_MODULE_OPTICAL_SFP_1G
:
3034 ahw
->supported_type
= PORT_FIBRE
;
3036 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE
:
3037 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN
:
3038 case LINKEVENT_MODULE_TWINAX
:
3039 ahw
->supported_type
= PORT_TP
;
3042 ahw
->supported_type
= PORT_OTHER
;
3049 qlcnic_free_mbx_args(&cmd
);
3053 int qlcnic_83xx_get_settings(struct qlcnic_adapter
*adapter
,
3054 struct ethtool_cmd
*ecmd
)
3058 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3060 if (!test_bit(__QLCNIC_MAINTENANCE_MODE
, &adapter
->state
)) {
3061 /* Get port configuration info */
3062 status
= qlcnic_83xx_get_port_info(adapter
);
3063 /* Get Link Status related info */
3064 config
= qlcnic_83xx_test_link(adapter
);
3065 ahw
->module_type
= QLC_83XX_SFP_MODULE_TYPE(config
);
3068 /* hard code until there is a way to get it from flash */
3069 ahw
->board_type
= QLCNIC_BRDTYPE_83XX_10G
;
3071 if (netif_running(adapter
->netdev
) && ahw
->has_link_events
) {
3072 ethtool_cmd_speed_set(ecmd
, ahw
->link_speed
);
3073 ecmd
->duplex
= ahw
->link_duplex
;
3074 ecmd
->autoneg
= ahw
->link_autoneg
;
3076 ethtool_cmd_speed_set(ecmd
, SPEED_UNKNOWN
);
3077 ecmd
->duplex
= DUPLEX_UNKNOWN
;
3078 ecmd
->autoneg
= AUTONEG_DISABLE
;
3081 if (ahw
->port_type
== QLCNIC_XGBE
) {
3082 ecmd
->supported
= SUPPORTED_10000baseT_Full
;
3083 ecmd
->advertising
= ADVERTISED_10000baseT_Full
;
3085 ecmd
->supported
= (SUPPORTED_10baseT_Half
|
3086 SUPPORTED_10baseT_Full
|
3087 SUPPORTED_100baseT_Half
|
3088 SUPPORTED_100baseT_Full
|
3089 SUPPORTED_1000baseT_Half
|
3090 SUPPORTED_1000baseT_Full
);
3091 ecmd
->advertising
= (ADVERTISED_100baseT_Half
|
3092 ADVERTISED_100baseT_Full
|
3093 ADVERTISED_1000baseT_Half
|
3094 ADVERTISED_1000baseT_Full
);
3097 switch (ahw
->supported_type
) {
3099 ecmd
->supported
|= SUPPORTED_FIBRE
;
3100 ecmd
->advertising
|= ADVERTISED_FIBRE
;
3101 ecmd
->port
= PORT_FIBRE
;
3102 ecmd
->transceiver
= XCVR_EXTERNAL
;
3105 ecmd
->supported
|= SUPPORTED_TP
;
3106 ecmd
->advertising
|= ADVERTISED_TP
;
3107 ecmd
->port
= PORT_TP
;
3108 ecmd
->transceiver
= XCVR_INTERNAL
;
3111 ecmd
->supported
|= SUPPORTED_FIBRE
;
3112 ecmd
->advertising
|= ADVERTISED_FIBRE
;
3113 ecmd
->port
= PORT_OTHER
;
3114 ecmd
->transceiver
= XCVR_EXTERNAL
;
3117 ecmd
->phy_address
= ahw
->physical_port
;
3121 int qlcnic_83xx_set_settings(struct qlcnic_adapter
*adapter
,
3122 struct ethtool_cmd
*ecmd
)
3125 u32 config
= adapter
->ahw
->port_config
;
3128 adapter
->ahw
->port_config
|= BIT_15
;
3130 switch (ethtool_cmd_speed(ecmd
)) {
3132 adapter
->ahw
->port_config
|= BIT_8
;
3135 adapter
->ahw
->port_config
|= BIT_9
;
3138 adapter
->ahw
->port_config
|= BIT_10
;
3141 adapter
->ahw
->port_config
|= BIT_11
;
3147 status
= qlcnic_83xx_set_port_config(adapter
);
3149 dev_info(&adapter
->pdev
->dev
,
3150 "Failed to Set Link Speed and autoneg.\n");
3151 adapter
->ahw
->port_config
= config
;
3156 static inline u64
*qlcnic_83xx_copy_stats(struct qlcnic_cmd_args
*cmd
,
3157 u64
*data
, int index
)
3162 low
= cmd
->rsp
.arg
[index
];
3163 hi
= cmd
->rsp
.arg
[index
+ 1];
3164 val
= (((u64
) low
) | (((u64
) hi
) << 32));
3169 static u64
*qlcnic_83xx_fill_stats(struct qlcnic_adapter
*adapter
,
3170 struct qlcnic_cmd_args
*cmd
, u64
*data
,
3173 int err
, k
, total_regs
;
3176 err
= qlcnic_issue_cmd(adapter
, cmd
);
3177 if (err
!= QLCNIC_RCODE_SUCCESS
) {
3178 dev_info(&adapter
->pdev
->dev
,
3179 "Error in get statistics mailbox command\n");
3183 total_regs
= cmd
->rsp
.num
;
3185 case QLC_83XX_STAT_MAC
:
3186 /* fill in MAC tx counters */
3187 for (k
= 2; k
< 28; k
+= 2)
3188 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3189 /* skip 24 bytes of reserved area */
3190 /* fill in MAC rx counters */
3191 for (k
+= 6; k
< 60; k
+= 2)
3192 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3193 /* skip 24 bytes of reserved area */
3194 /* fill in MAC rx frame stats */
3195 for (k
+= 6; k
< 80; k
+= 2)
3196 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3197 /* fill in eSwitch stats */
3198 for (; k
< total_regs
; k
+= 2)
3199 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3201 case QLC_83XX_STAT_RX
:
3202 for (k
= 2; k
< 8; k
+= 2)
3203 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3204 /* skip 8 bytes of reserved data */
3205 for (k
+= 2; k
< 24; k
+= 2)
3206 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3207 /* skip 8 bytes containing RE1FBQ error data */
3208 for (k
+= 2; k
< total_regs
; k
+= 2)
3209 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3211 case QLC_83XX_STAT_TX
:
3212 for (k
= 2; k
< 10; k
+= 2)
3213 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3214 /* skip 8 bytes of reserved data */
3215 for (k
+= 2; k
< total_regs
; k
+= 2)
3216 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3219 dev_warn(&adapter
->pdev
->dev
, "Unknown get statistics mode\n");
3225 void qlcnic_83xx_get_stats(struct qlcnic_adapter
*adapter
, u64
*data
)
3227 struct qlcnic_cmd_args cmd
;
3228 struct net_device
*netdev
= adapter
->netdev
;
3231 ret
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_STATISTICS
);
3235 cmd
.req
.arg
[1] = BIT_1
| (adapter
->tx_ring
->ctx_id
<< 16);
3236 cmd
.rsp
.num
= QLC_83XX_TX_STAT_REGS
;
3237 data
= qlcnic_83xx_fill_stats(adapter
, &cmd
, data
,
3238 QLC_83XX_STAT_TX
, &ret
);
3240 netdev_err(netdev
, "Error getting Tx stats\n");
3244 cmd
.req
.arg
[1] = BIT_2
| (adapter
->portnum
<< 16);
3245 cmd
.rsp
.num
= QLC_83XX_MAC_STAT_REGS
;
3246 memset(cmd
.rsp
.arg
, 0, sizeof(u32
) * cmd
.rsp
.num
);
3247 data
= qlcnic_83xx_fill_stats(adapter
, &cmd
, data
,
3248 QLC_83XX_STAT_MAC
, &ret
);
3250 netdev_err(netdev
, "Error getting MAC stats\n");
3254 cmd
.req
.arg
[1] = adapter
->recv_ctx
->context_id
<< 16;
3255 cmd
.rsp
.num
= QLC_83XX_RX_STAT_REGS
;
3256 memset(cmd
.rsp
.arg
, 0, sizeof(u32
) * cmd
.rsp
.num
);
3257 data
= qlcnic_83xx_fill_stats(adapter
, &cmd
, data
,
3258 QLC_83XX_STAT_RX
, &ret
);
3260 netdev_err(netdev
, "Error getting Rx stats\n");
3262 qlcnic_free_mbx_args(&cmd
);
3265 int qlcnic_83xx_reg_test(struct qlcnic_adapter
*adapter
)
3267 u32 major
, minor
, sub
;
3269 major
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MAJOR
);
3270 minor
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MINOR
);
3271 sub
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_SUB
);
3273 if (adapter
->fw_version
!= QLCNIC_VERSION_CODE(major
, minor
, sub
)) {
3274 dev_info(&adapter
->pdev
->dev
, "%s: Reg test failed\n",
3281 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter
*adapter
)
3283 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl
) *
3284 sizeof(*adapter
->ahw
->ext_reg_tbl
)) +
3285 (ARRAY_SIZE(qlcnic_83xx_reg_tbl
) *
3286 sizeof(*adapter
->ahw
->reg_tbl
));
3289 int qlcnic_83xx_get_registers(struct qlcnic_adapter
*adapter
, u32
*regs_buff
)
3293 for (i
= QLCNIC_DEV_INFO_SIZE
+ 1;
3294 j
< ARRAY_SIZE(qlcnic_83xx_reg_tbl
); i
++, j
++)
3295 regs_buff
[i
] = QLC_SHARED_REG_RD32(adapter
, j
);
3297 for (j
= 0; j
< ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl
); j
++)
3298 regs_buff
[i
++] = QLCRDX(adapter
->ahw
, j
);
3302 int qlcnic_83xx_interrupt_test(struct net_device
*netdev
)
3304 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
3305 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3306 struct qlcnic_cmd_args cmd
;
3307 u8 val
, drv_sds_rings
= adapter
->drv_sds_rings
;
3308 u8 drv_tx_rings
= adapter
->drv_tx_rings
;
3313 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
3314 netdev_info(netdev
, "Device is resetting\n");
3318 if (qlcnic_get_diag_lock(adapter
)) {
3319 netdev_info(netdev
, "Device in diagnostics mode\n");
3323 ret
= qlcnic_83xx_diag_alloc_res(netdev
, QLCNIC_INTERRUPT_TEST
,
3329 ret
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_INTRPT_TEST
);
3333 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
3334 intrpt_id
= ahw
->intr_tbl
[0].id
;
3336 intrpt_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
3339 cmd
.req
.arg
[2] = intrpt_id
;
3340 cmd
.req
.arg
[3] = BIT_0
;
3342 ret
= qlcnic_issue_cmd(adapter
, &cmd
);
3343 data
= cmd
.rsp
.arg
[2];
3345 val
= LSB(MSW(data
));
3346 if (id
!= intrpt_id
)
3347 dev_info(&adapter
->pdev
->dev
,
3348 "Interrupt generated: 0x%x, requested:0x%x\n",
3351 dev_err(&adapter
->pdev
->dev
,
3352 "Interrupt test error: 0x%x\n", val
);
3357 ret
= !ahw
->diag_cnt
;
3360 qlcnic_free_mbx_args(&cmd
);
3361 qlcnic_83xx_diag_free_res(netdev
, drv_sds_rings
);
3364 adapter
->drv_sds_rings
= drv_sds_rings
;
3365 adapter
->drv_tx_rings
= drv_tx_rings
;
3366 qlcnic_release_diag_lock(adapter
);
3370 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter
*adapter
,
3371 struct ethtool_pauseparam
*pause
)
3373 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3377 status
= qlcnic_83xx_get_port_config(adapter
);
3379 dev_err(&adapter
->pdev
->dev
,
3380 "%s: Get Pause Config failed\n", __func__
);
3383 config
= ahw
->port_config
;
3384 if (config
& QLC_83XX_CFG_STD_PAUSE
) {
3385 switch (MSW(config
)) {
3386 case QLC_83XX_TX_PAUSE
:
3387 pause
->tx_pause
= 1;
3389 case QLC_83XX_RX_PAUSE
:
3390 pause
->rx_pause
= 1;
3392 case QLC_83XX_TX_RX_PAUSE
:
3394 /* Backward compatibility for existing
3397 pause
->tx_pause
= 1;
3398 pause
->rx_pause
= 1;
3402 if (QLC_83XX_AUTONEG(config
))
3406 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter
*adapter
,
3407 struct ethtool_pauseparam
*pause
)
3409 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3413 status
= qlcnic_83xx_get_port_config(adapter
);
3415 dev_err(&adapter
->pdev
->dev
,
3416 "%s: Get Pause Config failed.\n", __func__
);
3419 config
= ahw
->port_config
;
3421 if (ahw
->port_type
== QLCNIC_GBE
) {
3423 ahw
->port_config
|= QLC_83XX_ENABLE_AUTONEG
;
3424 if (!pause
->autoneg
)
3425 ahw
->port_config
&= ~QLC_83XX_ENABLE_AUTONEG
;
3426 } else if ((ahw
->port_type
== QLCNIC_XGBE
) && (pause
->autoneg
)) {
3430 if (!(config
& QLC_83XX_CFG_STD_PAUSE
))
3431 ahw
->port_config
|= QLC_83XX_CFG_STD_PAUSE
;
3433 if (pause
->rx_pause
&& pause
->tx_pause
) {
3434 ahw
->port_config
|= QLC_83XX_CFG_STD_TX_RX_PAUSE
;
3435 } else if (pause
->rx_pause
&& !pause
->tx_pause
) {
3436 ahw
->port_config
&= ~QLC_83XX_CFG_STD_TX_PAUSE
;
3437 ahw
->port_config
|= QLC_83XX_CFG_STD_RX_PAUSE
;
3438 } else if (pause
->tx_pause
&& !pause
->rx_pause
) {
3439 ahw
->port_config
&= ~QLC_83XX_CFG_STD_RX_PAUSE
;
3440 ahw
->port_config
|= QLC_83XX_CFG_STD_TX_PAUSE
;
3441 } else if (!pause
->rx_pause
&& !pause
->tx_pause
) {
3442 ahw
->port_config
&= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE
|
3443 QLC_83XX_CFG_STD_PAUSE
);
3445 status
= qlcnic_83xx_set_port_config(adapter
);
3447 dev_err(&adapter
->pdev
->dev
,
3448 "%s: Set Pause Config failed.\n", __func__
);
3449 ahw
->port_config
= config
;
3454 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter
*adapter
)
3459 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
3460 QLC_83XX_FLASH_OEM_READ_SIG
);
3461 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
3462 QLC_83XX_FLASH_READ_CTRL
);
3463 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
3467 temp
= QLCRD32(adapter
, QLC_83XX_FLASH_RDDATA
, &err
);
3474 int qlcnic_83xx_flash_test(struct qlcnic_adapter
*adapter
)
3478 status
= qlcnic_83xx_read_flash_status_reg(adapter
);
3479 if (status
== -EIO
) {
3480 dev_info(&adapter
->pdev
->dev
, "%s: EEPROM test failed.\n",
3487 int qlcnic_83xx_shutdown(struct pci_dev
*pdev
)
3489 struct qlcnic_adapter
*adapter
= pci_get_drvdata(pdev
);
3490 struct net_device
*netdev
= adapter
->netdev
;
3493 netif_device_detach(netdev
);
3494 qlcnic_cancel_idc_work(adapter
);
3496 if (netif_running(netdev
))
3497 qlcnic_down(adapter
, netdev
);
3499 qlcnic_83xx_disable_mbx_intr(adapter
);
3500 cancel_delayed_work_sync(&adapter
->idc_aen_work
);
3502 retval
= pci_save_state(pdev
);
3509 int qlcnic_83xx_resume(struct qlcnic_adapter
*adapter
)
3511 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3512 struct qlc_83xx_idc
*idc
= &ahw
->idc
;
3515 err
= qlcnic_83xx_idc_init(adapter
);
3519 if (ahw
->nic_mode
== QLCNIC_VNIC_MODE
) {
3520 if (ahw
->op_mode
== QLCNIC_MGMT_FUNC
) {
3521 qlcnic_83xx_set_vnic_opmode(adapter
);
3523 err
= qlcnic_83xx_check_vnic_state(adapter
);
3529 err
= qlcnic_83xx_idc_reattach_driver(adapter
);
3533 qlcnic_schedule_work(adapter
, qlcnic_83xx_idc_poll_dev_state
,
3538 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox
*mbx
)
3540 reinit_completion(&mbx
->completion
);
3541 set_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3544 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox
*mbx
)
3549 destroy_workqueue(mbx
->work_q
);
3554 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter
*adapter
,
3555 struct qlcnic_cmd_args
*cmd
)
3557 atomic_set(&cmd
->rsp_status
, QLC_83XX_MBX_RESPONSE_ARRIVED
);
3559 if (cmd
->type
== QLC_83XX_MBX_CMD_NO_WAIT
) {
3560 qlcnic_free_mbx_args(cmd
);
3564 complete(&cmd
->completion
);
3567 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter
*adapter
)
3569 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3570 struct list_head
*head
= &mbx
->cmd_q
;
3571 struct qlcnic_cmd_args
*cmd
= NULL
;
3573 spin_lock(&mbx
->queue_lock
);
3575 while (!list_empty(head
)) {
3576 cmd
= list_entry(head
->next
, struct qlcnic_cmd_args
, list
);
3577 dev_info(&adapter
->pdev
->dev
, "%s: Mailbox command 0x%x\n",
3578 __func__
, cmd
->cmd_op
);
3579 list_del(&cmd
->list
);
3581 qlcnic_83xx_notify_cmd_completion(adapter
, cmd
);
3584 spin_unlock(&mbx
->queue_lock
);
3587 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter
*adapter
)
3589 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3590 struct qlcnic_mailbox
*mbx
= ahw
->mailbox
;
3593 if (!test_bit(QLC_83XX_MBX_READY
, &mbx
->status
))
3596 host_mbx_ctrl
= QLCRDX(ahw
, QLCNIC_HOST_MBX_CTRL
);
3597 if (host_mbx_ctrl
) {
3598 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3599 ahw
->idc
.collect_dump
= 1;
3606 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter
*adapter
,
3610 QLCWRX(adapter
->ahw
, QLCNIC_HOST_MBX_CTRL
, QLCNIC_SET_OWNER
);
3612 QLCWRX(adapter
->ahw
, QLCNIC_FW_MBX_CTRL
, QLCNIC_CLR_OWNER
);
3615 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter
*adapter
,
3616 struct qlcnic_cmd_args
*cmd
)
3618 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3620 spin_lock(&mbx
->queue_lock
);
3622 list_del(&cmd
->list
);
3625 spin_unlock(&mbx
->queue_lock
);
3627 qlcnic_83xx_notify_cmd_completion(adapter
, cmd
);
3630 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter
*adapter
,
3631 struct qlcnic_cmd_args
*cmd
)
3633 u32 mbx_cmd
, fw_hal_version
, hdr_size
, total_size
, tmp
;
3634 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3637 if (cmd
->op_type
!= QLC_83XX_MBX_POST_BC_OP
) {
3638 mbx_cmd
= cmd
->req
.arg
[0];
3639 writel(mbx_cmd
, QLCNIC_MBX_HOST(ahw
, 0));
3640 for (i
= 1; i
< cmd
->req
.num
; i
++)
3641 writel(cmd
->req
.arg
[i
], QLCNIC_MBX_HOST(ahw
, i
));
3643 fw_hal_version
= ahw
->fw_hal_version
;
3644 hdr_size
= sizeof(struct qlcnic_bc_hdr
) / sizeof(u32
);
3645 total_size
= cmd
->pay_size
+ hdr_size
;
3646 tmp
= QLCNIC_CMD_BC_EVENT_SETUP
| total_size
<< 16;
3647 mbx_cmd
= tmp
| fw_hal_version
<< 29;
3648 writel(mbx_cmd
, QLCNIC_MBX_HOST(ahw
, 0));
3650 /* Back channel specific operations bits */
3651 mbx_cmd
= 0x1 | 1 << 4;
3653 if (qlcnic_sriov_pf_check(adapter
))
3654 mbx_cmd
|= cmd
->func_num
<< 5;
3656 writel(mbx_cmd
, QLCNIC_MBX_HOST(ahw
, 1));
3658 for (i
= 2, j
= 0; j
< hdr_size
; i
++, j
++)
3659 writel(*(cmd
->hdr
++), QLCNIC_MBX_HOST(ahw
, i
));
3660 for (j
= 0; j
< cmd
->pay_size
; j
++, i
++)
3661 writel(*(cmd
->pay
++), QLCNIC_MBX_HOST(ahw
, i
));
3665 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter
*adapter
)
3667 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3672 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3673 complete(&mbx
->completion
);
3674 cancel_work_sync(&mbx
->work
);
3675 flush_workqueue(mbx
->work_q
);
3676 qlcnic_83xx_flush_mbx_queue(adapter
);
3679 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter
*adapter
,
3680 struct qlcnic_cmd_args
*cmd
,
3681 unsigned long *timeout
)
3683 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3685 if (test_bit(QLC_83XX_MBX_READY
, &mbx
->status
)) {
3686 atomic_set(&cmd
->rsp_status
, QLC_83XX_MBX_RESPONSE_WAIT
);
3687 init_completion(&cmd
->completion
);
3688 cmd
->rsp_opcode
= QLC_83XX_MBX_RESPONSE_UNKNOWN
;
3690 spin_lock(&mbx
->queue_lock
);
3692 list_add_tail(&cmd
->list
, &mbx
->cmd_q
);
3694 cmd
->total_cmds
= mbx
->num_cmds
;
3695 *timeout
= cmd
->total_cmds
* QLC_83XX_MBX_TIMEOUT
;
3696 queue_work(mbx
->work_q
, &mbx
->work
);
3698 spin_unlock(&mbx
->queue_lock
);
3706 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter
*adapter
,
3707 struct qlcnic_cmd_args
*cmd
)
3712 if (cmd
->cmd_op
== QLCNIC_CMD_CONFIG_MAC_VLAN
) {
3713 fw_data
= readl(QLCNIC_MBX_FW(adapter
->ahw
, 2));
3714 mac_cmd_rcode
= (u8
)fw_data
;
3715 if (mac_cmd_rcode
== QLC_83XX_NO_NIC_RESOURCE
||
3716 mac_cmd_rcode
== QLC_83XX_MAC_PRESENT
||
3717 mac_cmd_rcode
== QLC_83XX_MAC_ABSENT
) {
3718 cmd
->rsp_opcode
= QLCNIC_RCODE_SUCCESS
;
3719 return QLCNIC_RCODE_SUCCESS
;
3726 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter
*adapter
,
3727 struct qlcnic_cmd_args
*cmd
)
3729 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3730 struct device
*dev
= &adapter
->pdev
->dev
;
3734 fw_data
= readl(QLCNIC_MBX_FW(ahw
, 0));
3735 mbx_err_code
= QLCNIC_MBX_STATUS(fw_data
);
3736 qlcnic_83xx_get_mbx_data(adapter
, cmd
);
3738 switch (mbx_err_code
) {
3739 case QLCNIC_MBX_RSP_OK
:
3740 case QLCNIC_MBX_PORT_RSP_OK
:
3741 cmd
->rsp_opcode
= QLCNIC_RCODE_SUCCESS
;
3744 if (!qlcnic_83xx_check_mac_rcode(adapter
, cmd
))
3747 dev_err(dev
, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3748 __func__
, cmd
->cmd_op
, cmd
->type
, ahw
->pci_func
,
3749 ahw
->op_mode
, mbx_err_code
);
3750 cmd
->rsp_opcode
= QLC_83XX_MBX_RESPONSE_FAILED
;
3751 qlcnic_dump_mbx(adapter
, cmd
);
3757 static void qlcnic_83xx_mailbox_worker(struct work_struct
*work
)
3759 struct qlcnic_mailbox
*mbx
= container_of(work
, struct qlcnic_mailbox
,
3761 struct qlcnic_adapter
*adapter
= mbx
->adapter
;
3762 struct qlcnic_mbx_ops
*mbx_ops
= mbx
->ops
;
3763 struct device
*dev
= &adapter
->pdev
->dev
;
3764 atomic_t
*rsp_status
= &mbx
->rsp_status
;
3765 struct list_head
*head
= &mbx
->cmd_q
;
3766 struct qlcnic_hardware_context
*ahw
;
3767 struct qlcnic_cmd_args
*cmd
= NULL
;
3772 if (qlcnic_83xx_check_mbx_status(adapter
)) {
3773 qlcnic_83xx_flush_mbx_queue(adapter
);
3777 atomic_set(rsp_status
, QLC_83XX_MBX_RESPONSE_WAIT
);
3779 spin_lock(&mbx
->queue_lock
);
3781 if (list_empty(head
)) {
3782 spin_unlock(&mbx
->queue_lock
);
3785 cmd
= list_entry(head
->next
, struct qlcnic_cmd_args
, list
);
3787 spin_unlock(&mbx
->queue_lock
);
3789 mbx_ops
->encode_cmd(adapter
, cmd
);
3790 mbx_ops
->nofity_fw(adapter
, QLC_83XX_MBX_REQUEST
);
3792 if (wait_for_completion_timeout(&mbx
->completion
,
3793 QLC_83XX_MBX_TIMEOUT
)) {
3794 mbx_ops
->decode_resp(adapter
, cmd
);
3795 mbx_ops
->nofity_fw(adapter
, QLC_83XX_MBX_COMPLETION
);
3797 dev_err(dev
, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3798 __func__
, cmd
->cmd_op
, cmd
->type
, ahw
->pci_func
,
3800 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3801 qlcnic_dump_mbx(adapter
, cmd
);
3802 qlcnic_83xx_idc_request_reset(adapter
,
3803 QLCNIC_FORCE_FW_DUMP_KEY
);
3804 cmd
->rsp_opcode
= QLCNIC_RCODE_TIMEOUT
;
3806 mbx_ops
->dequeue_cmd(adapter
, cmd
);
3810 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops
= {
3811 .enqueue_cmd
= qlcnic_83xx_enqueue_mbx_cmd
,
3812 .dequeue_cmd
= qlcnic_83xx_dequeue_mbx_cmd
,
3813 .decode_resp
= qlcnic_83xx_decode_mbx_rsp
,
3814 .encode_cmd
= qlcnic_83xx_encode_mbx_cmd
,
3815 .nofity_fw
= qlcnic_83xx_signal_mbx_cmd
,
3818 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter
*adapter
)
3820 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3821 struct qlcnic_mailbox
*mbx
;
3823 ahw
->mailbox
= kzalloc(sizeof(*mbx
), GFP_KERNEL
);
3828 mbx
->ops
= &qlcnic_83xx_mbx_ops
;
3829 mbx
->adapter
= adapter
;
3831 spin_lock_init(&mbx
->queue_lock
);
3832 spin_lock_init(&mbx
->aen_lock
);
3833 INIT_LIST_HEAD(&mbx
->cmd_q
);
3834 init_completion(&mbx
->completion
);
3836 mbx
->work_q
= create_singlethread_workqueue("qlcnic_mailbox");
3837 if (mbx
->work_q
== NULL
) {
3842 INIT_WORK(&mbx
->work
, qlcnic_83xx_mailbox_worker
);
3843 set_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3847 pci_ers_result_t
qlcnic_83xx_io_error_detected(struct pci_dev
*pdev
,
3848 pci_channel_state_t state
)
3850 struct qlcnic_adapter
*adapter
= pci_get_drvdata(pdev
);
3852 if (state
== pci_channel_io_perm_failure
)
3853 return PCI_ERS_RESULT_DISCONNECT
;
3855 if (state
== pci_channel_io_normal
)
3856 return PCI_ERS_RESULT_RECOVERED
;
3858 set_bit(__QLCNIC_AER
, &adapter
->state
);
3859 set_bit(__QLCNIC_RESETTING
, &adapter
->state
);
3861 qlcnic_83xx_aer_stop_poll_work(adapter
);
3863 pci_save_state(pdev
);
3864 pci_disable_device(pdev
);
3866 return PCI_ERS_RESULT_NEED_RESET
;
3869 pci_ers_result_t
qlcnic_83xx_io_slot_reset(struct pci_dev
*pdev
)
3871 struct qlcnic_adapter
*adapter
= pci_get_drvdata(pdev
);
3874 pdev
->error_state
= pci_channel_io_normal
;
3875 err
= pci_enable_device(pdev
);
3879 pci_set_power_state(pdev
, PCI_D0
);
3880 pci_set_master(pdev
);
3881 pci_restore_state(pdev
);
3883 err
= qlcnic_83xx_aer_reset(adapter
);
3885 return PCI_ERS_RESULT_RECOVERED
;
3887 clear_bit(__QLCNIC_AER
, &adapter
->state
);
3888 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
3889 return PCI_ERS_RESULT_DISCONNECT
;
3892 void qlcnic_83xx_io_resume(struct pci_dev
*pdev
)
3894 struct qlcnic_adapter
*adapter
= pci_get_drvdata(pdev
);
3896 pci_cleanup_aer_uncorrect_error_status(pdev
);
3897 if (test_and_clear_bit(__QLCNIC_AER
, &adapter
->state
))
3898 qlcnic_83xx_aer_start_poll_work(adapter
);