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qlcnic: Support VF-PF communication channel commands.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_hw.c
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #include "qlcnic.h"
9 #include "qlcnic_sriov.h"
10 #include <linux/if_vlan.h>
11 #include <linux/ipv6.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14
15 #define QLCNIC_MAX_TX_QUEUES 1
16 #define RSS_HASHTYPE_IP_TCP 0x3
17 #define QLC_83XX_FW_MBX_CMD 0
18
19 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
20 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
21 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
22 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
23 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
24 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
25 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
26 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
27 {QLCNIC_CMD_INTRPT_TEST, 22, 12},
28 {QLCNIC_CMD_SET_MTU, 3, 1},
29 {QLCNIC_CMD_READ_PHY, 4, 2},
30 {QLCNIC_CMD_WRITE_PHY, 5, 1},
31 {QLCNIC_CMD_READ_HW_REG, 4, 1},
32 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
33 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
34 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
35 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
36 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
37 {QLCNIC_CMD_GET_PCI_INFO, 1, 66},
38 {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
39 {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
40 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
41 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
42 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
43 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
44 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
45 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
46 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
47 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
48 {QLCNIC_CMD_TEMP_SIZE, 1, 4},
49 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
50 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
51 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
52 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
53 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
54 {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
55 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
56 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
57 {QLCNIC_CMD_GET_STATISTICS, 2, 80},
58 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
59 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
60 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
61 {QLCNIC_CMD_IDC_ACK, 5, 1},
62 {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
63 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
64 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
65 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
66 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
67 {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
68 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
69 };
70
71 const u32 qlcnic_83xx_ext_reg_tbl[] = {
72 0x38CC, /* Global Reset */
73 0x38F0, /* Wildcard */
74 0x38FC, /* Informant */
75 0x3038, /* Host MBX ctrl */
76 0x303C, /* FW MBX ctrl */
77 0x355C, /* BOOT LOADER ADDRESS REG */
78 0x3560, /* BOOT LOADER SIZE REG */
79 0x3564, /* FW IMAGE ADDR REG */
80 0x1000, /* MBX intr enable */
81 0x1200, /* Default Intr mask */
82 0x1204, /* Default Interrupt ID */
83 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
84 0x3784, /* QLC_83XX_IDC_DEV_STATE */
85 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
86 0x378C, /* QLC_83XX_IDC_DRV_ACK */
87 0x3790, /* QLC_83XX_IDC_CTRL */
88 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
89 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
90 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
91 0x37A0, /* QLC_83XX_IDC_PF_0 */
92 0x37A4, /* QLC_83XX_IDC_PF_1 */
93 0x37A8, /* QLC_83XX_IDC_PF_2 */
94 0x37AC, /* QLC_83XX_IDC_PF_3 */
95 0x37B0, /* QLC_83XX_IDC_PF_4 */
96 0x37B4, /* QLC_83XX_IDC_PF_5 */
97 0x37B8, /* QLC_83XX_IDC_PF_6 */
98 0x37BC, /* QLC_83XX_IDC_PF_7 */
99 0x37C0, /* QLC_83XX_IDC_PF_8 */
100 0x37C4, /* QLC_83XX_IDC_PF_9 */
101 0x37C8, /* QLC_83XX_IDC_PF_10 */
102 0x37CC, /* QLC_83XX_IDC_PF_11 */
103 0x37D0, /* QLC_83XX_IDC_PF_12 */
104 0x37D4, /* QLC_83XX_IDC_PF_13 */
105 0x37D8, /* QLC_83XX_IDC_PF_14 */
106 0x37DC, /* QLC_83XX_IDC_PF_15 */
107 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
108 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
109 0x37F0, /* QLC_83XX_DRV_OP_MODE */
110 0x37F4, /* QLC_83XX_VNIC_STATE */
111 0x3868, /* QLC_83XX_DRV_LOCK */
112 0x386C, /* QLC_83XX_DRV_UNLOCK */
113 0x3504, /* QLC_83XX_DRV_LOCK_ID */
114 0x34A4, /* QLC_83XX_ASIC_TEMP */
115 };
116
117 const u32 qlcnic_83xx_reg_tbl[] = {
118 0x34A8, /* PEG_HALT_STAT1 */
119 0x34AC, /* PEG_HALT_STAT2 */
120 0x34B0, /* FW_HEARTBEAT */
121 0x3500, /* FLASH LOCK_ID */
122 0x3528, /* FW_CAPABILITIES */
123 0x3538, /* Driver active, DRV_REG0 */
124 0x3540, /* Device state, DRV_REG1 */
125 0x3544, /* Driver state, DRV_REG2 */
126 0x3548, /* Driver scratch, DRV_REG3 */
127 0x354C, /* Device partiton info, DRV_REG4 */
128 0x3524, /* Driver IDC ver, DRV_REG5 */
129 0x3550, /* FW_VER_MAJOR */
130 0x3554, /* FW_VER_MINOR */
131 0x3558, /* FW_VER_SUB */
132 0x359C, /* NPAR STATE */
133 0x35FC, /* FW_IMG_VALID */
134 0x3650, /* CMD_PEG_STATE */
135 0x373C, /* RCV_PEG_STATE */
136 0x37B4, /* ASIC TEMP */
137 0x356C, /* FW API */
138 0x3570, /* DRV OP MODE */
139 0x3850, /* FLASH LOCK */
140 0x3854, /* FLASH UNLOCK */
141 };
142
143 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
144 .read_crb = qlcnic_83xx_read_crb,
145 .write_crb = qlcnic_83xx_write_crb,
146 .read_reg = qlcnic_83xx_rd_reg_indirect,
147 .write_reg = qlcnic_83xx_wrt_reg_indirect,
148 .get_mac_address = qlcnic_83xx_get_mac_address,
149 .setup_intr = qlcnic_83xx_setup_intr,
150 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
151 .mbx_cmd = qlcnic_83xx_mbx_op,
152 .get_func_no = qlcnic_83xx_get_func_no,
153 .api_lock = qlcnic_83xx_cam_lock,
154 .api_unlock = qlcnic_83xx_cam_unlock,
155 .add_sysfs = qlcnic_83xx_add_sysfs,
156 .remove_sysfs = qlcnic_83xx_remove_sysfs,
157 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
158 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
159 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
160 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
161 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
162 .setup_link_event = qlcnic_83xx_setup_link_event,
163 .get_nic_info = qlcnic_83xx_get_nic_info,
164 .get_pci_info = qlcnic_83xx_get_pci_info,
165 .set_nic_info = qlcnic_83xx_set_nic_info,
166 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
167 .napi_enable = qlcnic_83xx_napi_enable,
168 .napi_disable = qlcnic_83xx_napi_disable,
169 .config_intr_coal = qlcnic_83xx_config_intr_coal,
170 .config_rss = qlcnic_83xx_config_rss,
171 .config_hw_lro = qlcnic_83xx_config_hw_lro,
172 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
173 .change_l2_filter = qlcnic_83xx_change_l2_filter,
174 .get_board_info = qlcnic_83xx_get_port_info,
175 };
176
177 static struct qlcnic_nic_template qlcnic_83xx_ops = {
178 .config_bridged_mode = qlcnic_config_bridged_mode,
179 .config_led = qlcnic_config_led,
180 .request_reset = qlcnic_83xx_idc_request_reset,
181 .cancel_idc_work = qlcnic_83xx_idc_exit,
182 .napi_add = qlcnic_83xx_napi_add,
183 .napi_del = qlcnic_83xx_napi_del,
184 .config_ipaddr = qlcnic_83xx_config_ipaddr,
185 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
186 };
187
188 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
189 {
190 ahw->hw_ops = &qlcnic_83xx_hw_ops;
191 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
192 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
193 }
194
195 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
196 {
197 u32 fw_major, fw_minor, fw_build;
198 struct pci_dev *pdev = adapter->pdev;
199
200 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
201 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
202 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
203 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
204
205 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
206 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
207
208 return adapter->fw_version;
209 }
210
211 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
212 {
213 void __iomem *base;
214 u32 val;
215
216 base = adapter->ahw->pci_base0 +
217 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
218 writel(addr, base);
219 val = readl(base);
220 if (val != addr)
221 return -EIO;
222
223 return 0;
224 }
225
226 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr)
227 {
228 int ret;
229 struct qlcnic_hardware_context *ahw = adapter->ahw;
230
231 ret = __qlcnic_set_win_base(adapter, (u32) addr);
232 if (!ret) {
233 return QLCRDX(ahw, QLCNIC_WILDCARD);
234 } else {
235 dev_err(&adapter->pdev->dev,
236 "%s failed, addr = 0x%x\n", __func__, (int)addr);
237 return -EIO;
238 }
239 }
240
241 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
242 u32 data)
243 {
244 int err;
245 struct qlcnic_hardware_context *ahw = adapter->ahw;
246
247 err = __qlcnic_set_win_base(adapter, (u32) addr);
248 if (!err) {
249 QLCWRX(ahw, QLCNIC_WILDCARD, data);
250 return 0;
251 } else {
252 dev_err(&adapter->pdev->dev,
253 "%s failed, addr = 0x%x data = 0x%x\n",
254 __func__, (int)addr, data);
255 return err;
256 }
257 }
258
259 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr)
260 {
261 int err, i, num_msix;
262 struct qlcnic_hardware_context *ahw = adapter->ahw;
263
264 if (!num_intr)
265 num_intr = QLCNIC_DEF_NUM_STS_DESC_RINGS;
266 num_msix = rounddown_pow_of_two(min_t(int, num_online_cpus(),
267 num_intr));
268 /* account for AEN interrupt MSI-X based interrupts */
269 num_msix += 1;
270
271 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
272 num_msix += adapter->max_drv_tx_rings;
273
274 err = qlcnic_enable_msix(adapter, num_msix);
275 if (err == -ENOMEM)
276 return err;
277 if (adapter->flags & QLCNIC_MSIX_ENABLED)
278 num_msix = adapter->ahw->num_msix;
279 else {
280 if (qlcnic_sriov_vf_check(adapter))
281 return -EINVAL;
282 num_msix = 1;
283 }
284 /* setup interrupt mapping table for fw */
285 ahw->intr_tbl = vzalloc(num_msix *
286 sizeof(struct qlcnic_intrpt_config));
287 if (!ahw->intr_tbl)
288 return -ENOMEM;
289 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
290 /* MSI-X enablement failed, use legacy interrupt */
291 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
292 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
293 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
294 adapter->msix_entries[0].vector = adapter->pdev->irq;
295 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
296 }
297
298 for (i = 0; i < num_msix; i++) {
299 if (adapter->flags & QLCNIC_MSIX_ENABLED)
300 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
301 else
302 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
303 ahw->intr_tbl[i].id = i;
304 ahw->intr_tbl[i].src = 0;
305 }
306 return 0;
307 }
308
309 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
310 {
311 writel(0, adapter->tgt_mask_reg);
312 }
313
314 /* Enable MSI-x and INT-x interrupts */
315 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
316 struct qlcnic_host_sds_ring *sds_ring)
317 {
318 writel(0, sds_ring->crb_intr_mask);
319 }
320
321 /* Disable MSI-x and INT-x interrupts */
322 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
323 struct qlcnic_host_sds_ring *sds_ring)
324 {
325 writel(1, sds_ring->crb_intr_mask);
326 }
327
328 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
329 *adapter)
330 {
331 u32 mask;
332
333 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
334 * source register. We could be here before contexts are created
335 * and sds_ring->crb_intr_mask has not been initialized, calculate
336 * BAR offset for Interrupt Source Register
337 */
338 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
339 writel(0, adapter->ahw->pci_base0 + mask);
340 }
341
342 inline void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
343 {
344 u32 mask;
345
346 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
347 writel(1, adapter->ahw->pci_base0 + mask);
348 }
349
350 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
351 struct qlcnic_cmd_args *cmd)
352 {
353 int i;
354 for (i = 0; i < cmd->rsp.num; i++)
355 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
356 }
357
358 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
359 {
360 u32 intr_val;
361 struct qlcnic_hardware_context *ahw = adapter->ahw;
362 int retries = 0;
363
364 intr_val = readl(adapter->tgt_status_reg);
365
366 if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
367 return IRQ_NONE;
368
369 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
370 adapter->stats.spurious_intr++;
371 return IRQ_NONE;
372 }
373 /* The barrier is required to ensure writes to the registers */
374 wmb();
375
376 /* clear the interrupt trigger control register */
377 writel(0, adapter->isr_int_vec);
378 intr_val = readl(adapter->isr_int_vec);
379 do {
380 intr_val = readl(adapter->tgt_status_reg);
381 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
382 break;
383 retries++;
384 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
385 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
386
387 return IRQ_HANDLED;
388 }
389
390 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
391 {
392 u32 resp, event;
393 unsigned long flags;
394
395 spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
396
397 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
398 if (!(resp & QLCNIC_SET_OWNER))
399 goto out;
400
401 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
402 if (event & QLCNIC_MBX_ASYNC_EVENT)
403 qlcnic_83xx_process_aen(adapter);
404 out:
405 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
406 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
407 }
408
409 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
410 {
411 struct qlcnic_adapter *adapter = data;
412 struct qlcnic_host_sds_ring *sds_ring;
413 struct qlcnic_hardware_context *ahw = adapter->ahw;
414
415 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
416 return IRQ_NONE;
417
418 qlcnic_83xx_poll_process_aen(adapter);
419
420 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
421 ahw->diag_cnt++;
422 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
423 return IRQ_HANDLED;
424 }
425
426 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
427 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
428 } else {
429 sds_ring = &adapter->recv_ctx->sds_rings[0];
430 napi_schedule(&sds_ring->napi);
431 }
432
433 return IRQ_HANDLED;
434 }
435
436 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
437 {
438 struct qlcnic_host_sds_ring *sds_ring = data;
439 struct qlcnic_adapter *adapter = sds_ring->adapter;
440
441 if (adapter->flags & QLCNIC_MSIX_ENABLED)
442 goto done;
443
444 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
445 return IRQ_NONE;
446
447 done:
448 adapter->ahw->diag_cnt++;
449 qlcnic_83xx_enable_intr(adapter, sds_ring);
450
451 return IRQ_HANDLED;
452 }
453
454 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
455 {
456 u32 val = 0, num_msix = adapter->ahw->num_msix - 1;
457
458 if (adapter->flags & QLCNIC_MSIX_ENABLED)
459 num_msix = adapter->ahw->num_msix - 1;
460 else
461 num_msix = 0;
462
463 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
464
465 qlcnic_83xx_disable_mbx_intr(adapter);
466
467 msleep(20);
468 synchronize_irq(adapter->msix_entries[num_msix].vector);
469 free_irq(adapter->msix_entries[num_msix].vector, adapter);
470 }
471
472 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
473 {
474 irq_handler_t handler;
475 u32 val;
476 char name[32];
477 int err = 0;
478 unsigned long flags = 0;
479
480 if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
481 !(adapter->flags & QLCNIC_MSIX_ENABLED))
482 flags |= IRQF_SHARED;
483
484 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
485 handler = qlcnic_83xx_handle_aen;
486 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
487 snprintf(name, (IFNAMSIZ + 4),
488 "%s[%s]", "qlcnic", "aen");
489 err = request_irq(val, handler, flags, name, adapter);
490 if (err) {
491 dev_err(&adapter->pdev->dev,
492 "failed to register MBX interrupt\n");
493 return err;
494 }
495 } else {
496 handler = qlcnic_83xx_intr;
497 val = adapter->msix_entries[0].vector;
498 err = request_irq(val, handler, flags, "qlcnic", adapter);
499 if (err) {
500 dev_err(&adapter->pdev->dev,
501 "failed to register INTx interrupt\n");
502 return err;
503 }
504 qlcnic_83xx_clear_legacy_intr_mask(adapter);
505 }
506
507 /* Enable mailbox interrupt */
508 qlcnic_83xx_enable_mbx_intrpt(adapter);
509
510 return err;
511 }
512
513 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
514 {
515 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
516 adapter->ahw->pci_func = (val >> 24) & 0xff;
517 }
518
519 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
520 {
521 void __iomem *addr;
522 u32 val, limit = 0;
523
524 struct qlcnic_hardware_context *ahw = adapter->ahw;
525
526 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
527 do {
528 val = readl(addr);
529 if (val) {
530 /* write the function number to register */
531 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
532 ahw->pci_func);
533 return 0;
534 }
535 usleep_range(1000, 2000);
536 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
537
538 return -EIO;
539 }
540
541 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
542 {
543 void __iomem *addr;
544 u32 val;
545 struct qlcnic_hardware_context *ahw = adapter->ahw;
546
547 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
548 val = readl(addr);
549 }
550
551 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
552 loff_t offset, size_t size)
553 {
554 int ret;
555 u32 data;
556
557 if (qlcnic_api_lock(adapter)) {
558 dev_err(&adapter->pdev->dev,
559 "%s: failed to acquire lock. addr offset 0x%x\n",
560 __func__, (u32)offset);
561 return;
562 }
563
564 ret = qlcnic_83xx_rd_reg_indirect(adapter, (u32) offset);
565 qlcnic_api_unlock(adapter);
566
567 if (ret == -EIO) {
568 dev_err(&adapter->pdev->dev,
569 "%s: failed. addr offset 0x%x\n",
570 __func__, (u32)offset);
571 return;
572 }
573 data = ret;
574 memcpy(buf, &data, size);
575 }
576
577 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
578 loff_t offset, size_t size)
579 {
580 u32 data;
581
582 memcpy(&data, buf, size);
583 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
584 }
585
586 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
587 {
588 int status;
589
590 status = qlcnic_83xx_get_port_config(adapter);
591 if (status) {
592 dev_err(&adapter->pdev->dev,
593 "Get Port Info failed\n");
594 } else {
595 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
596 adapter->ahw->port_type = QLCNIC_XGBE;
597 else
598 adapter->ahw->port_type = QLCNIC_GBE;
599
600 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
601 adapter->ahw->link_autoneg = AUTONEG_ENABLE;
602 }
603 return status;
604 }
605
606 void qlcnic_83xx_enable_mbx_intrpt(struct qlcnic_adapter *adapter)
607 {
608 u32 val;
609
610 if (adapter->flags & QLCNIC_MSIX_ENABLED)
611 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
612 else
613 val = BIT_2;
614
615 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
616 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
617 }
618
619 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
620 const struct pci_device_id *ent)
621 {
622 u32 op_mode, priv_level;
623 struct qlcnic_hardware_context *ahw = adapter->ahw;
624
625 ahw->fw_hal_version = 2;
626 qlcnic_get_func_no(adapter);
627
628 if (qlcnic_sriov_vf_check(adapter)) {
629 qlcnic_sriov_vf_set_ops(adapter);
630 return;
631 }
632
633 /* Determine function privilege level */
634 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
635 if (op_mode == QLC_83XX_DEFAULT_OPMODE)
636 priv_level = QLCNIC_MGMT_FUNC;
637 else
638 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
639 ahw->pci_func);
640
641 if (priv_level == QLCNIC_NON_PRIV_FUNC) {
642 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
643 dev_info(&adapter->pdev->dev,
644 "HAL Version: %d Non Privileged function\n",
645 ahw->fw_hal_version);
646 adapter->nic_ops = &qlcnic_vf_ops;
647 } else {
648 if (pci_find_ext_capability(adapter->pdev,
649 PCI_EXT_CAP_ID_SRIOV))
650 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
651 adapter->nic_ops = &qlcnic_83xx_ops;
652 }
653 }
654
655 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
656 u32 data[]);
657 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
658 u32 data[]);
659
660 static void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
661 struct qlcnic_cmd_args *cmd)
662 {
663 int i;
664
665 dev_info(&adapter->pdev->dev,
666 "Host MBX regs(%d)\n", cmd->req.num);
667 for (i = 0; i < cmd->req.num; i++) {
668 if (i && !(i % 8))
669 pr_info("\n");
670 pr_info("%08x ", cmd->req.arg[i]);
671 }
672 pr_info("\n");
673 dev_info(&adapter->pdev->dev,
674 "FW MBX regs(%d)\n", cmd->rsp.num);
675 for (i = 0; i < cmd->rsp.num; i++) {
676 if (i && !(i % 8))
677 pr_info("\n");
678 pr_info("%08x ", cmd->rsp.arg[i]);
679 }
680 pr_info("\n");
681 }
682
683 /* Mailbox response for mac rcode */
684 u32 qlcnic_83xx_mac_rcode(struct qlcnic_adapter *adapter)
685 {
686 u32 fw_data;
687 u8 mac_cmd_rcode;
688
689 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
690 mac_cmd_rcode = (u8)fw_data;
691 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
692 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
693 mac_cmd_rcode == QLC_83XX_MAC_ABSENT)
694 return QLCNIC_RCODE_SUCCESS;
695 return 1;
696 }
697
698 u32 qlcnic_83xx_mbx_poll(struct qlcnic_adapter *adapter)
699 {
700 u32 data;
701 unsigned long wait_time = 0;
702 struct qlcnic_hardware_context *ahw = adapter->ahw;
703 /* wait for mailbox completion */
704 do {
705 data = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
706 if (++wait_time > QLCNIC_MBX_TIMEOUT) {
707 data = QLCNIC_RCODE_TIMEOUT;
708 break;
709 }
710 mdelay(1);
711 } while (!data);
712 return data;
713 }
714
715 int qlcnic_83xx_mbx_op(struct qlcnic_adapter *adapter,
716 struct qlcnic_cmd_args *cmd)
717 {
718 int i;
719 u16 opcode;
720 u8 mbx_err_code;
721 unsigned long flags;
722 u32 rsp, mbx_val, fw_data, rsp_num, mbx_cmd;
723 struct qlcnic_hardware_context *ahw = adapter->ahw;
724
725 opcode = LSW(cmd->req.arg[0]);
726 if (!test_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status)) {
727 dev_info(&adapter->pdev->dev,
728 "Mailbox cmd attempted, 0x%x\n", opcode);
729 dev_info(&adapter->pdev->dev, "Mailbox detached\n");
730 return 0;
731 }
732
733 spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
734 mbx_val = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
735
736 if (mbx_val) {
737 QLCDB(adapter, DRV,
738 "Mailbox cmd attempted, 0x%x\n", opcode);
739 QLCDB(adapter, DRV,
740 "Mailbox not available, 0x%x, collect FW dump\n",
741 mbx_val);
742 cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
743 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
744 return cmd->rsp.arg[0];
745 }
746
747 /* Fill in mailbox registers */
748 mbx_cmd = cmd->req.arg[0];
749 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
750 for (i = 1; i < cmd->req.num; i++)
751 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
752
753 /* Signal FW about the impending command */
754 QLCWRX(ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
755 poll:
756 rsp = qlcnic_83xx_mbx_poll(adapter);
757 if (rsp != QLCNIC_RCODE_TIMEOUT) {
758 /* Get the FW response data */
759 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
760 if (fw_data & QLCNIC_MBX_ASYNC_EVENT) {
761 qlcnic_83xx_process_aen(adapter);
762 mbx_val = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
763 if (mbx_val)
764 goto poll;
765 }
766 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
767 rsp_num = QLCNIC_MBX_NUM_REGS(fw_data);
768 opcode = QLCNIC_MBX_RSP(fw_data);
769 qlcnic_83xx_get_mbx_data(adapter, cmd);
770
771 switch (mbx_err_code) {
772 case QLCNIC_MBX_RSP_OK:
773 case QLCNIC_MBX_PORT_RSP_OK:
774 rsp = QLCNIC_RCODE_SUCCESS;
775 break;
776 default:
777 if (opcode == QLCNIC_CMD_CONFIG_MAC_VLAN) {
778 rsp = qlcnic_83xx_mac_rcode(adapter);
779 if (!rsp)
780 goto out;
781 }
782 dev_err(&adapter->pdev->dev,
783 "MBX command 0x%x failed with err:0x%x\n",
784 opcode, mbx_err_code);
785 rsp = mbx_err_code;
786 qlcnic_dump_mbx(adapter, cmd);
787 break;
788 }
789 goto out;
790 }
791
792 dev_err(&adapter->pdev->dev, "MBX command 0x%x timed out\n",
793 QLCNIC_MBX_RSP(mbx_cmd));
794 rsp = QLCNIC_RCODE_TIMEOUT;
795 out:
796 /* clear fw mbx control register */
797 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
798 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
799 return rsp;
800 }
801
802 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
803 struct qlcnic_adapter *adapter, u32 type)
804 {
805 int i, size;
806 u32 temp;
807 const struct qlcnic_mailbox_metadata *mbx_tbl;
808
809 mbx_tbl = qlcnic_83xx_mbx_tbl;
810 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
811 for (i = 0; i < size; i++) {
812 if (type == mbx_tbl[i].cmd) {
813 mbx->op_type = QLC_83XX_FW_MBX_CMD;
814 mbx->req.num = mbx_tbl[i].in_args;
815 mbx->rsp.num = mbx_tbl[i].out_args;
816 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
817 GFP_ATOMIC);
818 if (!mbx->req.arg)
819 return -ENOMEM;
820 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
821 GFP_ATOMIC);
822 if (!mbx->rsp.arg) {
823 kfree(mbx->req.arg);
824 mbx->req.arg = NULL;
825 return -ENOMEM;
826 }
827 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
828 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
829 temp = adapter->ahw->fw_hal_version << 29;
830 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
831 return 0;
832 }
833 }
834 return -EINVAL;
835 }
836
837 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
838 {
839 struct qlcnic_adapter *adapter;
840 struct qlcnic_cmd_args cmd;
841 int i, err = 0;
842
843 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
844 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
845
846 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
847 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
848
849 err = qlcnic_issue_cmd(adapter, &cmd);
850 if (err)
851 dev_info(&adapter->pdev->dev,
852 "%s: Mailbox IDC ACK failed.\n", __func__);
853 qlcnic_free_mbx_args(&cmd);
854 }
855
856 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
857 u32 data[])
858 {
859 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
860 QLCNIC_MBX_RSP(data[0]));
861 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
862 return;
863 }
864
865 void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
866 {
867 u32 event[QLC_83XX_MBX_AEN_CNT];
868 int i;
869 struct qlcnic_hardware_context *ahw = adapter->ahw;
870
871 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
872 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
873
874 switch (QLCNIC_MBX_RSP(event[0])) {
875
876 case QLCNIC_MBX_LINK_EVENT:
877 qlcnic_83xx_handle_link_aen(adapter, event);
878 break;
879 case QLCNIC_MBX_COMP_EVENT:
880 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
881 break;
882 case QLCNIC_MBX_REQUEST_EVENT:
883 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
884 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
885 queue_delayed_work(adapter->qlcnic_wq,
886 &adapter->idc_aen_work, 0);
887 break;
888 case QLCNIC_MBX_TIME_EXTEND_EVENT:
889 break;
890 case QLCNIC_MBX_BC_EVENT:
891 qlcnic_sriov_handle_bc_event(adapter, event[1]);
892 break;
893 case QLCNIC_MBX_SFP_INSERT_EVENT:
894 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
895 QLCNIC_MBX_RSP(event[0]));
896 break;
897 case QLCNIC_MBX_SFP_REMOVE_EVENT:
898 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
899 QLCNIC_MBX_RSP(event[0]));
900 break;
901 default:
902 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
903 QLCNIC_MBX_RSP(event[0]));
904 break;
905 }
906
907 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
908 }
909
910 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
911 {
912 int index, i, err, sds_mbx_size;
913 u32 *buf, intrpt_id, intr_mask;
914 u16 context_id;
915 u8 num_sds;
916 struct qlcnic_cmd_args cmd;
917 struct qlcnic_host_sds_ring *sds;
918 struct qlcnic_sds_mbx sds_mbx;
919 struct qlcnic_add_rings_mbx_out *mbx_out;
920 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
921 struct qlcnic_hardware_context *ahw = adapter->ahw;
922
923 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
924 context_id = recv_ctx->context_id;
925 num_sds = (adapter->max_sds_rings - QLCNIC_MAX_RING_SETS);
926 ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
927 QLCNIC_CMD_ADD_RCV_RINGS);
928 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
929
930 /* set up status rings, mbx 2-81 */
931 index = 2;
932 for (i = 8; i < adapter->max_sds_rings; i++) {
933 memset(&sds_mbx, 0, sds_mbx_size);
934 sds = &recv_ctx->sds_rings[i];
935 sds->consumer = 0;
936 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
937 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
938 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
939 sds_mbx.sds_ring_size = sds->num_desc;
940
941 if (adapter->flags & QLCNIC_MSIX_ENABLED)
942 intrpt_id = ahw->intr_tbl[i].id;
943 else
944 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
945
946 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
947 sds_mbx.intrpt_id = intrpt_id;
948 else
949 sds_mbx.intrpt_id = 0xffff;
950 sds_mbx.intrpt_val = 0;
951 buf = &cmd.req.arg[index];
952 memcpy(buf, &sds_mbx, sds_mbx_size);
953 index += sds_mbx_size / sizeof(u32);
954 }
955
956 /* send the mailbox command */
957 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
958 if (err) {
959 dev_err(&adapter->pdev->dev,
960 "Failed to add rings %d\n", err);
961 goto out;
962 }
963
964 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
965 index = 0;
966 /* status descriptor ring */
967 for (i = 8; i < adapter->max_sds_rings; i++) {
968 sds = &recv_ctx->sds_rings[i];
969 sds->crb_sts_consumer = ahw->pci_base0 +
970 mbx_out->host_csmr[index];
971 if (adapter->flags & QLCNIC_MSIX_ENABLED)
972 intr_mask = ahw->intr_tbl[i].src;
973 else
974 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
975
976 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
977 index++;
978 }
979 out:
980 qlcnic_free_mbx_args(&cmd);
981 return err;
982 }
983
984 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
985 {
986 int err;
987 u32 temp = 0;
988 struct qlcnic_cmd_args cmd;
989 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
990
991 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
992 return;
993
994 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
995 cmd.req.arg[0] |= (0x3 << 29);
996
997 if (qlcnic_sriov_pf_check(adapter))
998 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
999
1000 cmd.req.arg[1] = recv_ctx->context_id | temp;
1001 err = qlcnic_issue_cmd(adapter, &cmd);
1002 if (err)
1003 dev_err(&adapter->pdev->dev,
1004 "Failed to destroy rx ctx in firmware\n");
1005
1006 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1007 qlcnic_free_mbx_args(&cmd);
1008 }
1009
1010 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1011 {
1012 int i, err, index, sds_mbx_size, rds_mbx_size;
1013 u8 num_sds, num_rds;
1014 u32 *buf, intrpt_id, intr_mask, cap = 0;
1015 struct qlcnic_host_sds_ring *sds;
1016 struct qlcnic_host_rds_ring *rds;
1017 struct qlcnic_sds_mbx sds_mbx;
1018 struct qlcnic_rds_mbx rds_mbx;
1019 struct qlcnic_cmd_args cmd;
1020 struct qlcnic_rcv_mbx_out *mbx_out;
1021 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1022 struct qlcnic_hardware_context *ahw = adapter->ahw;
1023 num_rds = adapter->max_rds_rings;
1024
1025 if (adapter->max_sds_rings <= QLCNIC_MAX_RING_SETS)
1026 num_sds = adapter->max_sds_rings;
1027 else
1028 num_sds = QLCNIC_MAX_RING_SETS;
1029
1030 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1031 rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1032 cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1033
1034 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1035 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1036
1037 /* set mailbox hdr and capabilities */
1038 qlcnic_alloc_mbx_args(&cmd, adapter,
1039 QLCNIC_CMD_CREATE_RX_CTX);
1040
1041 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1042 cmd.req.arg[0] |= (0x3 << 29);
1043
1044 cmd.req.arg[1] = cap;
1045 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1046 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1047
1048 if (qlcnic_sriov_pf_check(adapter))
1049 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1050 &cmd.req.arg[6]);
1051 /* set up status rings, mbx 8-57/87 */
1052 index = QLC_83XX_HOST_SDS_MBX_IDX;
1053 for (i = 0; i < num_sds; i++) {
1054 memset(&sds_mbx, 0, sds_mbx_size);
1055 sds = &recv_ctx->sds_rings[i];
1056 sds->consumer = 0;
1057 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1058 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1059 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1060 sds_mbx.sds_ring_size = sds->num_desc;
1061 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1062 intrpt_id = ahw->intr_tbl[i].id;
1063 else
1064 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1065 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1066 sds_mbx.intrpt_id = intrpt_id;
1067 else
1068 sds_mbx.intrpt_id = 0xffff;
1069 sds_mbx.intrpt_val = 0;
1070 buf = &cmd.req.arg[index];
1071 memcpy(buf, &sds_mbx, sds_mbx_size);
1072 index += sds_mbx_size / sizeof(u32);
1073 }
1074 /* set up receive rings, mbx 88-111/135 */
1075 index = QLCNIC_HOST_RDS_MBX_IDX;
1076 rds = &recv_ctx->rds_rings[0];
1077 rds->producer = 0;
1078 memset(&rds_mbx, 0, rds_mbx_size);
1079 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1080 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1081 rds_mbx.reg_ring_sz = rds->dma_size;
1082 rds_mbx.reg_ring_len = rds->num_desc;
1083 /* Jumbo ring */
1084 rds = &recv_ctx->rds_rings[1];
1085 rds->producer = 0;
1086 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1087 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1088 rds_mbx.jmb_ring_sz = rds->dma_size;
1089 rds_mbx.jmb_ring_len = rds->num_desc;
1090 buf = &cmd.req.arg[index];
1091 memcpy(buf, &rds_mbx, rds_mbx_size);
1092
1093 /* send the mailbox command */
1094 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1095 if (err) {
1096 dev_err(&adapter->pdev->dev,
1097 "Failed to create Rx ctx in firmware%d\n", err);
1098 goto out;
1099 }
1100 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1101 recv_ctx->context_id = mbx_out->ctx_id;
1102 recv_ctx->state = mbx_out->state;
1103 recv_ctx->virt_port = mbx_out->vport_id;
1104 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1105 recv_ctx->context_id, recv_ctx->state);
1106 /* Receive descriptor ring */
1107 /* Standard ring */
1108 rds = &recv_ctx->rds_rings[0];
1109 rds->crb_rcv_producer = ahw->pci_base0 +
1110 mbx_out->host_prod[0].reg_buf;
1111 /* Jumbo ring */
1112 rds = &recv_ctx->rds_rings[1];
1113 rds->crb_rcv_producer = ahw->pci_base0 +
1114 mbx_out->host_prod[0].jmb_buf;
1115 /* status descriptor ring */
1116 for (i = 0; i < num_sds; i++) {
1117 sds = &recv_ctx->sds_rings[i];
1118 sds->crb_sts_consumer = ahw->pci_base0 +
1119 mbx_out->host_csmr[i];
1120 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1121 intr_mask = ahw->intr_tbl[i].src;
1122 else
1123 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1124 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1125 }
1126
1127 if (adapter->max_sds_rings > QLCNIC_MAX_RING_SETS)
1128 err = qlcnic_83xx_add_rings(adapter);
1129 out:
1130 qlcnic_free_mbx_args(&cmd);
1131 return err;
1132 }
1133
1134 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1135 struct qlcnic_host_tx_ring *tx_ring)
1136 {
1137 struct qlcnic_cmd_args cmd;
1138 u32 temp = 0;
1139
1140 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1141 return;
1142
1143 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1144 cmd.req.arg[0] |= (0x3 << 29);
1145
1146 if (qlcnic_sriov_pf_check(adapter))
1147 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1148
1149 cmd.req.arg[1] = tx_ring->ctx_id | temp;
1150 if (qlcnic_issue_cmd(adapter, &cmd))
1151 dev_err(&adapter->pdev->dev,
1152 "Failed to destroy tx ctx in firmware\n");
1153 qlcnic_free_mbx_args(&cmd);
1154 }
1155
1156 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1157 struct qlcnic_host_tx_ring *tx, int ring)
1158 {
1159 int err;
1160 u16 msix_id;
1161 u32 *buf, intr_mask, temp = 0;
1162 struct qlcnic_cmd_args cmd;
1163 struct qlcnic_tx_mbx mbx;
1164 struct qlcnic_tx_mbx_out *mbx_out;
1165 struct qlcnic_hardware_context *ahw = adapter->ahw;
1166 u32 msix_vector;
1167
1168 /* Reset host resources */
1169 tx->producer = 0;
1170 tx->sw_consumer = 0;
1171 *(tx->hw_consumer) = 0;
1172
1173 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1174
1175 /* setup mailbox inbox registerss */
1176 mbx.phys_addr_low = LSD(tx->phys_addr);
1177 mbx.phys_addr_high = MSD(tx->phys_addr);
1178 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1179 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1180 mbx.size = tx->num_desc;
1181 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1182 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1183 msix_vector = adapter->max_sds_rings + ring;
1184 else
1185 msix_vector = adapter->max_sds_rings - 1;
1186 msix_id = ahw->intr_tbl[msix_vector].id;
1187 } else {
1188 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1189 }
1190
1191 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1192 mbx.intr_id = msix_id;
1193 else
1194 mbx.intr_id = 0xffff;
1195 mbx.src = 0;
1196
1197 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1198
1199 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1200 cmd.req.arg[0] |= (0x3 << 29);
1201
1202 if (qlcnic_sriov_pf_check(adapter))
1203 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1204
1205 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1206 cmd.req.arg[5] = QLCNIC_MAX_TX_QUEUES | temp;
1207 buf = &cmd.req.arg[6];
1208 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1209 /* send the mailbox command*/
1210 err = qlcnic_issue_cmd(adapter, &cmd);
1211 if (err) {
1212 dev_err(&adapter->pdev->dev,
1213 "Failed to create Tx ctx in firmware 0x%x\n", err);
1214 goto out;
1215 }
1216 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1217 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1218 tx->ctx_id = mbx_out->ctx_id;
1219 if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1220 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1221 intr_mask = ahw->intr_tbl[adapter->max_sds_rings + ring].src;
1222 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1223 }
1224 dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1225 tx->ctx_id, mbx_out->state);
1226 out:
1227 qlcnic_free_mbx_args(&cmd);
1228 return err;
1229 }
1230
1231 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test)
1232 {
1233 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1234 struct qlcnic_host_sds_ring *sds_ring;
1235 struct qlcnic_host_rds_ring *rds_ring;
1236 u8 ring;
1237 int ret;
1238
1239 netif_device_detach(netdev);
1240
1241 if (netif_running(netdev))
1242 __qlcnic_down(adapter, netdev);
1243
1244 qlcnic_detach(adapter);
1245
1246 adapter->max_sds_rings = 1;
1247 adapter->ahw->diag_test = test;
1248 adapter->ahw->linkup = 0;
1249
1250 ret = qlcnic_attach(adapter);
1251 if (ret) {
1252 netif_device_attach(netdev);
1253 return ret;
1254 }
1255
1256 ret = qlcnic_fw_create_ctx(adapter);
1257 if (ret) {
1258 qlcnic_detach(adapter);
1259 netif_device_attach(netdev);
1260 return ret;
1261 }
1262
1263 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1264 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1265 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1266 }
1267
1268 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1269 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1270 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1271 qlcnic_83xx_enable_intr(adapter, sds_ring);
1272 }
1273 }
1274
1275 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1276 /* disable and free mailbox interrupt */
1277 qlcnic_83xx_free_mbx_intr(adapter);
1278 adapter->ahw->loopback_state = 0;
1279 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1280 }
1281
1282 set_bit(__QLCNIC_DEV_UP, &adapter->state);
1283 return 0;
1284 }
1285
1286 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1287 int max_sds_rings)
1288 {
1289 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1290 struct qlcnic_host_sds_ring *sds_ring;
1291 int ring, err;
1292
1293 clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1294 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1295 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1296 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1297 qlcnic_83xx_disable_intr(adapter, sds_ring);
1298 }
1299 }
1300
1301 qlcnic_fw_destroy_ctx(adapter);
1302 qlcnic_detach(adapter);
1303
1304 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1305 err = qlcnic_83xx_setup_mbx_intr(adapter);
1306 if (err) {
1307 dev_err(&adapter->pdev->dev,
1308 "%s: failed to setup mbx interrupt\n",
1309 __func__);
1310 goto out;
1311 }
1312 }
1313 adapter->ahw->diag_test = 0;
1314 adapter->max_sds_rings = max_sds_rings;
1315
1316 if (qlcnic_attach(adapter))
1317 goto out;
1318
1319 if (netif_running(netdev))
1320 __qlcnic_up(adapter, netdev);
1321 out:
1322 netif_device_attach(netdev);
1323 }
1324
1325 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1326 u32 beacon)
1327 {
1328 struct qlcnic_cmd_args cmd;
1329 u32 mbx_in;
1330 int i, status = 0;
1331
1332 if (state) {
1333 /* Get LED configuration */
1334 qlcnic_alloc_mbx_args(&cmd, adapter,
1335 QLCNIC_CMD_GET_LED_CONFIG);
1336 status = qlcnic_issue_cmd(adapter, &cmd);
1337 if (status) {
1338 dev_err(&adapter->pdev->dev,
1339 "Get led config failed.\n");
1340 goto mbx_err;
1341 } else {
1342 for (i = 0; i < 4; i++)
1343 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1344 }
1345 qlcnic_free_mbx_args(&cmd);
1346 /* Set LED Configuration */
1347 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1348 LSW(QLC_83XX_LED_CONFIG);
1349 qlcnic_alloc_mbx_args(&cmd, adapter,
1350 QLCNIC_CMD_SET_LED_CONFIG);
1351 cmd.req.arg[1] = mbx_in;
1352 cmd.req.arg[2] = mbx_in;
1353 cmd.req.arg[3] = mbx_in;
1354 if (beacon)
1355 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1356 status = qlcnic_issue_cmd(adapter, &cmd);
1357 if (status) {
1358 dev_err(&adapter->pdev->dev,
1359 "Set led config failed.\n");
1360 }
1361 mbx_err:
1362 qlcnic_free_mbx_args(&cmd);
1363 return status;
1364
1365 } else {
1366 /* Restoring default LED configuration */
1367 qlcnic_alloc_mbx_args(&cmd, adapter,
1368 QLCNIC_CMD_SET_LED_CONFIG);
1369 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1370 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1371 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1372 if (beacon)
1373 cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1374 status = qlcnic_issue_cmd(adapter, &cmd);
1375 if (status)
1376 dev_err(&adapter->pdev->dev,
1377 "Restoring led config failed.\n");
1378 qlcnic_free_mbx_args(&cmd);
1379 return status;
1380 }
1381 }
1382
1383 int qlcnic_83xx_set_led(struct net_device *netdev,
1384 enum ethtool_phys_id_state state)
1385 {
1386 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1387 int err = -EIO, active = 1;
1388
1389 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1390 netdev_warn(netdev,
1391 "LED test is not supported in non-privileged mode\n");
1392 return -EOPNOTSUPP;
1393 }
1394
1395 switch (state) {
1396 case ETHTOOL_ID_ACTIVE:
1397 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1398 return -EBUSY;
1399
1400 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1401 break;
1402
1403 err = qlcnic_83xx_config_led(adapter, active, 0);
1404 if (err)
1405 netdev_err(netdev, "Failed to set LED blink state\n");
1406 break;
1407 case ETHTOOL_ID_INACTIVE:
1408 active = 0;
1409
1410 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1411 break;
1412
1413 err = qlcnic_83xx_config_led(adapter, active, 0);
1414 if (err)
1415 netdev_err(netdev, "Failed to reset LED blink state\n");
1416 break;
1417
1418 default:
1419 return -EINVAL;
1420 }
1421
1422 if (!active || err)
1423 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1424
1425 return err;
1426 }
1427
1428 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *adapter,
1429 int enable)
1430 {
1431 struct qlcnic_cmd_args cmd;
1432 int status;
1433
1434 if (qlcnic_sriov_vf_check(adapter))
1435 return;
1436
1437 if (enable) {
1438 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INIT_NIC_FUNC);
1439 cmd.req.arg[1] = BIT_0 | BIT_31;
1440 } else {
1441 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_STOP_NIC_FUNC);
1442 cmd.req.arg[1] = BIT_0 | BIT_31;
1443 }
1444 status = qlcnic_issue_cmd(adapter, &cmd);
1445 if (status)
1446 dev_err(&adapter->pdev->dev,
1447 "Failed to %s in NIC IDC function event.\n",
1448 (enable ? "register" : "unregister"));
1449
1450 qlcnic_free_mbx_args(&cmd);
1451 }
1452
1453 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1454 {
1455 struct qlcnic_cmd_args cmd;
1456 int err;
1457
1458 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1459 cmd.req.arg[1] = adapter->ahw->port_config;
1460 err = qlcnic_issue_cmd(adapter, &cmd);
1461 if (err)
1462 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1463 qlcnic_free_mbx_args(&cmd);
1464 return err;
1465 }
1466
1467 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1468 {
1469 struct qlcnic_cmd_args cmd;
1470 int err;
1471
1472 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1473 err = qlcnic_issue_cmd(adapter, &cmd);
1474 if (err)
1475 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1476 else
1477 adapter->ahw->port_config = cmd.rsp.arg[1];
1478 qlcnic_free_mbx_args(&cmd);
1479 return err;
1480 }
1481
1482 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1483 {
1484 int err;
1485 u32 temp;
1486 struct qlcnic_cmd_args cmd;
1487
1488 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1489 temp = adapter->recv_ctx->context_id << 16;
1490 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1491 err = qlcnic_issue_cmd(adapter, &cmd);
1492 if (err)
1493 dev_info(&adapter->pdev->dev,
1494 "Setup linkevent mailbox failed\n");
1495 qlcnic_free_mbx_args(&cmd);
1496 return err;
1497 }
1498
1499 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1500 u32 *interface_id)
1501 {
1502 if (qlcnic_sriov_pf_check(adapter)) {
1503 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1504 } else {
1505 if (!qlcnic_sriov_vf_check(adapter))
1506 *interface_id = adapter->recv_ctx->context_id << 16;
1507 }
1508 }
1509
1510 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1511 {
1512 int err;
1513 u32 temp = 0;
1514 struct qlcnic_cmd_args cmd;
1515
1516 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1517 return -EIO;
1518
1519 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1520 qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1521 cmd.req.arg[1] = (mode ? 1 : 0) | temp;
1522 err = qlcnic_issue_cmd(adapter, &cmd);
1523 if (err)
1524 dev_info(&adapter->pdev->dev,
1525 "Promiscous mode config failed\n");
1526
1527 qlcnic_free_mbx_args(&cmd);
1528 return err;
1529 }
1530
1531 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1532 {
1533 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1534 struct qlcnic_hardware_context *ahw = adapter->ahw;
1535 int ret = 0, loop = 0, max_sds_rings = adapter->max_sds_rings;
1536
1537 QLCDB(adapter, DRV, "%s loopback test in progress\n",
1538 mode == QLCNIC_ILB_MODE ? "internal" : "external");
1539 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1540 dev_warn(&adapter->pdev->dev,
1541 "Loopback test not supported for non privilege function\n");
1542 return ret;
1543 }
1544
1545 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1546 return -EBUSY;
1547
1548 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST);
1549 if (ret)
1550 goto fail_diag_alloc;
1551
1552 ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1553 if (ret)
1554 goto free_diag_res;
1555
1556 /* Poll for link up event before running traffic */
1557 do {
1558 msleep(500);
1559 qlcnic_83xx_process_aen(adapter);
1560 if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
1561 dev_info(&adapter->pdev->dev,
1562 "Firmware didn't sent link up event to loopback request\n");
1563 ret = -QLCNIC_FW_NOT_RESPOND;
1564 qlcnic_83xx_clear_lb_mode(adapter, mode);
1565 goto free_diag_res;
1566 }
1567 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1568
1569 ret = qlcnic_do_lb_test(adapter, mode);
1570
1571 qlcnic_83xx_clear_lb_mode(adapter, mode);
1572
1573 free_diag_res:
1574 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
1575
1576 fail_diag_alloc:
1577 adapter->max_sds_rings = max_sds_rings;
1578 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1579 return ret;
1580 }
1581
1582 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1583 {
1584 struct qlcnic_hardware_context *ahw = adapter->ahw;
1585 int status = 0, loop = 0;
1586 u32 config;
1587
1588 status = qlcnic_83xx_get_port_config(adapter);
1589 if (status)
1590 return status;
1591
1592 config = ahw->port_config;
1593 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1594
1595 if (mode == QLCNIC_ILB_MODE)
1596 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1597 if (mode == QLCNIC_ELB_MODE)
1598 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1599
1600 status = qlcnic_83xx_set_port_config(adapter);
1601 if (status) {
1602 dev_err(&adapter->pdev->dev,
1603 "Failed to Set Loopback Mode = 0x%x.\n",
1604 ahw->port_config);
1605 ahw->port_config = config;
1606 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1607 return status;
1608 }
1609
1610 /* Wait for Link and IDC Completion AEN */
1611 do {
1612 msleep(300);
1613 qlcnic_83xx_process_aen(adapter);
1614 if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
1615 dev_err(&adapter->pdev->dev,
1616 "FW did not generate IDC completion AEN\n");
1617 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1618 qlcnic_83xx_clear_lb_mode(adapter, mode);
1619 return -EIO;
1620 }
1621 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1622
1623 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1624 QLCNIC_MAC_ADD);
1625 return status;
1626 }
1627
1628 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1629 {
1630 struct qlcnic_hardware_context *ahw = adapter->ahw;
1631 int status = 0, loop = 0;
1632 u32 config = ahw->port_config;
1633
1634 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1635 if (mode == QLCNIC_ILB_MODE)
1636 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1637 if (mode == QLCNIC_ELB_MODE)
1638 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1639
1640 status = qlcnic_83xx_set_port_config(adapter);
1641 if (status) {
1642 dev_err(&adapter->pdev->dev,
1643 "Failed to Clear Loopback Mode = 0x%x.\n",
1644 ahw->port_config);
1645 ahw->port_config = config;
1646 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1647 return status;
1648 }
1649
1650 /* Wait for Link and IDC Completion AEN */
1651 do {
1652 msleep(300);
1653 qlcnic_83xx_process_aen(adapter);
1654 if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
1655 dev_err(&adapter->pdev->dev,
1656 "Firmware didn't sent IDC completion AEN\n");
1657 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1658 return -EIO;
1659 }
1660 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1661
1662 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1663 QLCNIC_MAC_DEL);
1664 return status;
1665 }
1666
1667 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1668 u32 *interface_id)
1669 {
1670 if (qlcnic_sriov_pf_check(adapter)) {
1671 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1672 } else {
1673 if (!qlcnic_sriov_vf_check(adapter))
1674 *interface_id = adapter->recv_ctx->context_id << 16;
1675 }
1676 }
1677
1678 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1679 int mode)
1680 {
1681 int err;
1682 u32 temp = 0, temp_ip;
1683 struct qlcnic_cmd_args cmd;
1684
1685 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_IP_ADDR);
1686 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1687
1688 if (mode == QLCNIC_IP_UP)
1689 cmd.req.arg[1] = 1 | temp;
1690 else
1691 cmd.req.arg[1] = 2 | temp;
1692
1693 /*
1694 * Adapter needs IP address in network byte order.
1695 * But hardware mailbox registers go through writel(), hence IP address
1696 * gets swapped on big endian architecture.
1697 * To negate swapping of writel() on big endian architecture
1698 * use swab32(value).
1699 */
1700
1701 temp_ip = swab32(ntohl(ip));
1702 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1703 err = qlcnic_issue_cmd(adapter, &cmd);
1704 if (err != QLCNIC_RCODE_SUCCESS)
1705 dev_err(&adapter->netdev->dev,
1706 "could not notify %s IP 0x%x request\n",
1707 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1708
1709 qlcnic_free_mbx_args(&cmd);
1710 }
1711
1712 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1713 {
1714 int err;
1715 u32 temp, arg1;
1716 struct qlcnic_cmd_args cmd;
1717 int lro_bit_mask;
1718
1719 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1720
1721 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1722 return 0;
1723
1724 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1725 temp = adapter->recv_ctx->context_id << 16;
1726 arg1 = lro_bit_mask | temp;
1727 cmd.req.arg[1] = arg1;
1728
1729 err = qlcnic_issue_cmd(adapter, &cmd);
1730 if (err)
1731 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1732 qlcnic_free_mbx_args(&cmd);
1733
1734 return err;
1735 }
1736
1737 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1738 {
1739 int err;
1740 u32 word;
1741 struct qlcnic_cmd_args cmd;
1742 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1743 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1744 0x255b0ec26d5a56daULL };
1745
1746 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1747
1748 /*
1749 * RSS request:
1750 * bits 3-0: Rsvd
1751 * 5-4: hash_type_ipv4
1752 * 7-6: hash_type_ipv6
1753 * 8: enable
1754 * 9: use indirection table
1755 * 16-31: indirection table mask
1756 */
1757 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1758 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1759 ((u32)(enable & 0x1) << 8) |
1760 ((0x7ULL) << 16);
1761 cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1762 cmd.req.arg[2] = word;
1763 memcpy(&cmd.req.arg[4], key, sizeof(key));
1764
1765 err = qlcnic_issue_cmd(adapter, &cmd);
1766
1767 if (err)
1768 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1769 qlcnic_free_mbx_args(&cmd);
1770
1771 return err;
1772
1773 }
1774
1775 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1776 u32 *interface_id)
1777 {
1778 if (qlcnic_sriov_pf_check(adapter)) {
1779 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1780 } else {
1781 if (!qlcnic_sriov_vf_check(adapter))
1782 *interface_id = adapter->recv_ctx->context_id << 16;
1783 }
1784 }
1785
1786 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
1787 __le16 vlan_id, u8 op)
1788 {
1789 int err;
1790 u32 *buf, temp = 0;
1791 struct qlcnic_cmd_args cmd;
1792 struct qlcnic_macvlan_mbx mv;
1793
1794 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1795 return -EIO;
1796
1797 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
1798 if (err)
1799 return err;
1800
1801 cmd.req.arg[1] = op | (1 << 8);
1802 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
1803 cmd.req.arg[1] |= temp;
1804 mv.vlan = le16_to_cpu(vlan_id);
1805 mv.mac_addr0 = addr[0];
1806 mv.mac_addr1 = addr[1];
1807 mv.mac_addr2 = addr[2];
1808 mv.mac_addr3 = addr[3];
1809 mv.mac_addr4 = addr[4];
1810 mv.mac_addr5 = addr[5];
1811 buf = &cmd.req.arg[2];
1812 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
1813 err = qlcnic_issue_cmd(adapter, &cmd);
1814 if (err)
1815 dev_err(&adapter->pdev->dev,
1816 "MAC-VLAN %s to CAM failed, err=%d.\n",
1817 ((op == 1) ? "add " : "delete "), err);
1818 qlcnic_free_mbx_args(&cmd);
1819 return err;
1820 }
1821
1822 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
1823 __le16 vlan_id)
1824 {
1825 u8 mac[ETH_ALEN];
1826 memcpy(&mac, addr, ETH_ALEN);
1827 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
1828 }
1829
1830 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
1831 u8 type, struct qlcnic_cmd_args *cmd)
1832 {
1833 switch (type) {
1834 case QLCNIC_SET_STATION_MAC:
1835 case QLCNIC_SET_FAC_DEF_MAC:
1836 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
1837 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
1838 break;
1839 }
1840 cmd->req.arg[1] = type;
1841 }
1842
1843 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
1844 {
1845 int err, i;
1846 struct qlcnic_cmd_args cmd;
1847 u32 mac_low, mac_high;
1848
1849 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
1850 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
1851 err = qlcnic_issue_cmd(adapter, &cmd);
1852
1853 if (err == QLCNIC_RCODE_SUCCESS) {
1854 mac_low = cmd.rsp.arg[1];
1855 mac_high = cmd.rsp.arg[2];
1856
1857 for (i = 0; i < 2; i++)
1858 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
1859 for (i = 2; i < 6; i++)
1860 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
1861 } else {
1862 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
1863 err);
1864 err = -EIO;
1865 }
1866 qlcnic_free_mbx_args(&cmd);
1867 return err;
1868 }
1869
1870 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
1871 {
1872 int err;
1873 u32 temp;
1874 struct qlcnic_cmd_args cmd;
1875 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
1876
1877 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1878 return;
1879
1880 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
1881 cmd.req.arg[1] = 1 | (adapter->recv_ctx->context_id << 16);
1882 cmd.req.arg[3] = coal->flag;
1883 temp = coal->rx_time_us << 16;
1884 cmd.req.arg[2] = coal->rx_packets | temp;
1885 err = qlcnic_issue_cmd(adapter, &cmd);
1886 if (err != QLCNIC_RCODE_SUCCESS)
1887 dev_info(&adapter->pdev->dev,
1888 "Failed to send interrupt coalescence parameters\n");
1889 qlcnic_free_mbx_args(&cmd);
1890 }
1891
1892 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
1893 u32 data[])
1894 {
1895 u8 link_status, duplex;
1896 /* link speed */
1897 link_status = LSB(data[3]) & 1;
1898 adapter->ahw->link_speed = MSW(data[2]);
1899 adapter->ahw->link_autoneg = MSB(MSW(data[3]));
1900 adapter->ahw->module_type = MSB(LSW(data[3]));
1901 duplex = LSB(MSW(data[3]));
1902 if (duplex)
1903 adapter->ahw->link_duplex = DUPLEX_FULL;
1904 else
1905 adapter->ahw->link_duplex = DUPLEX_HALF;
1906 adapter->ahw->has_link_events = 1;
1907 qlcnic_advert_link_change(adapter, link_status);
1908 }
1909
1910 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
1911 {
1912 struct qlcnic_adapter *adapter = data;
1913 unsigned long flags;
1914 u32 mask, resp, event;
1915
1916 spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
1917 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
1918 if (!(resp & QLCNIC_SET_OWNER))
1919 goto out;
1920
1921 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
1922 if (event & QLCNIC_MBX_ASYNC_EVENT)
1923 qlcnic_83xx_process_aen(adapter);
1924 out:
1925 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
1926 writel(0, adapter->ahw->pci_base0 + mask);
1927 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
1928
1929 return IRQ_HANDLED;
1930 }
1931
1932 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
1933 {
1934 int err = -EIO;
1935 struct qlcnic_cmd_args cmd;
1936
1937 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
1938 dev_err(&adapter->pdev->dev,
1939 "%s: Error, invoked by non management func\n",
1940 __func__);
1941 return err;
1942 }
1943
1944 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
1945 cmd.req.arg[1] = (port & 0xf) | BIT_4;
1946 err = qlcnic_issue_cmd(adapter, &cmd);
1947
1948 if (err != QLCNIC_RCODE_SUCCESS) {
1949 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
1950 err);
1951 err = -EIO;
1952 }
1953 qlcnic_free_mbx_args(&cmd);
1954
1955 return err;
1956
1957 }
1958
1959 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
1960 struct qlcnic_info *nic)
1961 {
1962 int i, err = -EIO;
1963 struct qlcnic_cmd_args cmd;
1964
1965 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
1966 dev_err(&adapter->pdev->dev,
1967 "%s: Error, invoked by non management func\n",
1968 __func__);
1969 return err;
1970 }
1971
1972 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
1973 cmd.req.arg[1] = (nic->pci_func << 16);
1974 cmd.req.arg[2] = 0x1 << 16;
1975 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
1976 cmd.req.arg[4] = nic->capabilities;
1977 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
1978 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
1979 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
1980 for (i = 8; i < 32; i++)
1981 cmd.req.arg[i] = 0;
1982
1983 err = qlcnic_issue_cmd(adapter, &cmd);
1984
1985 if (err != QLCNIC_RCODE_SUCCESS) {
1986 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
1987 err);
1988 err = -EIO;
1989 }
1990
1991 qlcnic_free_mbx_args(&cmd);
1992
1993 return err;
1994 }
1995
1996 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
1997 struct qlcnic_info *npar_info, u8 func_id)
1998 {
1999 int err;
2000 u32 temp;
2001 u8 op = 0;
2002 struct qlcnic_cmd_args cmd;
2003
2004 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2005 if (func_id != adapter->ahw->pci_func) {
2006 temp = func_id << 16;
2007 cmd.req.arg[1] = op | BIT_31 | temp;
2008 } else {
2009 cmd.req.arg[1] = adapter->ahw->pci_func << 16;
2010 }
2011 err = qlcnic_issue_cmd(adapter, &cmd);
2012 if (err) {
2013 dev_info(&adapter->pdev->dev,
2014 "Failed to get nic info %d\n", err);
2015 goto out;
2016 }
2017
2018 npar_info->op_type = cmd.rsp.arg[1];
2019 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2020 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2021 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2022 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2023 npar_info->capabilities = cmd.rsp.arg[4];
2024 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2025 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2026 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2027 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2028 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2029 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2030 if (cmd.rsp.arg[8] & 0x1)
2031 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2032 if (cmd.rsp.arg[8] & 0x10000) {
2033 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2034 npar_info->max_linkspeed_reg_offset = temp;
2035 }
2036
2037 out:
2038 qlcnic_free_mbx_args(&cmd);
2039 return err;
2040 }
2041
2042 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2043 struct qlcnic_pci_info *pci_info)
2044 {
2045 int i, err = 0, j = 0;
2046 u32 temp;
2047 struct qlcnic_cmd_args cmd;
2048
2049 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2050 err = qlcnic_issue_cmd(adapter, &cmd);
2051
2052 adapter->ahw->act_pci_func = 0;
2053 if (err == QLCNIC_RCODE_SUCCESS) {
2054 pci_info->func_count = cmd.rsp.arg[1] & 0xFF;
2055 dev_info(&adapter->pdev->dev,
2056 "%s: total functions = %d\n",
2057 __func__, pci_info->func_count);
2058 for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) {
2059 pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2060 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2061 i++;
2062 pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2063 if (pci_info->type == QLCNIC_TYPE_NIC)
2064 adapter->ahw->act_pci_func++;
2065 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2066 pci_info->default_port = temp;
2067 i++;
2068 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2069 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2070 pci_info->tx_max_bw = temp;
2071 i = i + 2;
2072 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2073 i++;
2074 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2075 i = i + 3;
2076
2077 dev_info(&adapter->pdev->dev, "%s:\n"
2078 "\tid = %d active = %d type = %d\n"
2079 "\tport = %d min bw = %d max bw = %d\n"
2080 "\tmac_addr = %pM\n", __func__,
2081 pci_info->id, pci_info->active, pci_info->type,
2082 pci_info->default_port, pci_info->tx_min_bw,
2083 pci_info->tx_max_bw, pci_info->mac);
2084 }
2085 } else {
2086 dev_err(&adapter->pdev->dev, "Failed to get PCI Info%d\n",
2087 err);
2088 err = -EIO;
2089 }
2090
2091 qlcnic_free_mbx_args(&cmd);
2092
2093 return err;
2094 }
2095
2096 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2097 {
2098 int i, index, err;
2099 u8 max_ints;
2100 u32 val, temp, type;
2101 struct qlcnic_cmd_args cmd;
2102
2103 max_ints = adapter->ahw->num_msix - 1;
2104 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2105 cmd.req.arg[1] = max_ints;
2106
2107 if (qlcnic_sriov_vf_check(adapter))
2108 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2109
2110 for (i = 0, index = 2; i < max_ints; i++) {
2111 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2112 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2113 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2114 val |= (adapter->ahw->intr_tbl[i].id << 16);
2115 cmd.req.arg[index++] = val;
2116 }
2117 err = qlcnic_issue_cmd(adapter, &cmd);
2118 if (err) {
2119 dev_err(&adapter->pdev->dev,
2120 "Failed to configure interrupts 0x%x\n", err);
2121 goto out;
2122 }
2123
2124 max_ints = cmd.rsp.arg[1];
2125 for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2126 val = cmd.rsp.arg[index];
2127 if (LSB(val)) {
2128 dev_info(&adapter->pdev->dev,
2129 "Can't configure interrupt %d\n",
2130 adapter->ahw->intr_tbl[i].id);
2131 continue;
2132 }
2133 if (op_type) {
2134 adapter->ahw->intr_tbl[i].id = MSW(val);
2135 adapter->ahw->intr_tbl[i].enabled = 1;
2136 temp = cmd.rsp.arg[index + 1];
2137 adapter->ahw->intr_tbl[i].src = temp;
2138 } else {
2139 adapter->ahw->intr_tbl[i].id = i;
2140 adapter->ahw->intr_tbl[i].enabled = 0;
2141 adapter->ahw->intr_tbl[i].src = 0;
2142 }
2143 }
2144 out:
2145 qlcnic_free_mbx_args(&cmd);
2146 return err;
2147 }
2148
2149 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2150 {
2151 int id, timeout = 0;
2152 u32 status = 0;
2153
2154 while (status == 0) {
2155 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2156 if (status)
2157 break;
2158
2159 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2160 id = QLC_SHARED_REG_RD32(adapter,
2161 QLCNIC_FLASH_LOCK_OWNER);
2162 dev_err(&adapter->pdev->dev,
2163 "%s: failed, lock held by %d\n", __func__, id);
2164 return -EIO;
2165 }
2166 usleep_range(1000, 2000);
2167 }
2168
2169 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2170 return 0;
2171 }
2172
2173 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2174 {
2175 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2176 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2177 }
2178
2179 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2180 u32 flash_addr, u8 *p_data,
2181 int count)
2182 {
2183 int i, ret;
2184 u32 word, range, flash_offset, addr = flash_addr;
2185 ulong indirect_add, direct_window;
2186
2187 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2188 if (addr & 0x3) {
2189 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2190 return -EIO;
2191 }
2192
2193 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2194 (addr));
2195
2196 range = flash_offset + (count * sizeof(u32));
2197 /* Check if data is spread across multiple sectors */
2198 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2199
2200 /* Multi sector read */
2201 for (i = 0; i < count; i++) {
2202 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2203 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2204 indirect_add);
2205 if (ret == -EIO)
2206 return -EIO;
2207
2208 word = ret;
2209 *(u32 *)p_data = word;
2210 p_data = p_data + 4;
2211 addr = addr + 4;
2212 flash_offset = flash_offset + 4;
2213
2214 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2215 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2216 /* This write is needed once for each sector */
2217 qlcnic_83xx_wrt_reg_indirect(adapter,
2218 direct_window,
2219 (addr));
2220 flash_offset = 0;
2221 }
2222 }
2223 } else {
2224 /* Single sector read */
2225 for (i = 0; i < count; i++) {
2226 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2227 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2228 indirect_add);
2229 if (ret == -EIO)
2230 return -EIO;
2231
2232 word = ret;
2233 *(u32 *)p_data = word;
2234 p_data = p_data + 4;
2235 addr = addr + 4;
2236 }
2237 }
2238
2239 return 0;
2240 }
2241
2242 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2243 {
2244 u32 status;
2245 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2246
2247 do {
2248 status = qlcnic_83xx_rd_reg_indirect(adapter,
2249 QLC_83XX_FLASH_STATUS);
2250 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2251 QLC_83XX_FLASH_STATUS_READY)
2252 break;
2253
2254 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2255 } while (--retries);
2256
2257 if (!retries)
2258 return -EIO;
2259
2260 return 0;
2261 }
2262
2263 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2264 {
2265 int ret;
2266 u32 cmd;
2267 cmd = adapter->ahw->fdt.write_statusreg_cmd;
2268 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2269 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2270 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2271 adapter->ahw->fdt.write_enable_bits);
2272 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2273 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2274 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2275 if (ret)
2276 return -EIO;
2277
2278 return 0;
2279 }
2280
2281 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2282 {
2283 int ret;
2284
2285 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2286 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2287 adapter->ahw->fdt.write_statusreg_cmd));
2288 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2289 adapter->ahw->fdt.write_disable_bits);
2290 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2291 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2292 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2293 if (ret)
2294 return -EIO;
2295
2296 return 0;
2297 }
2298
2299 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2300 {
2301 int ret, mfg_id;
2302
2303 if (qlcnic_83xx_lock_flash(adapter))
2304 return -EIO;
2305
2306 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2307 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2308 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2309 QLC_83XX_FLASH_READ_CTRL);
2310 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2311 if (ret) {
2312 qlcnic_83xx_unlock_flash(adapter);
2313 return -EIO;
2314 }
2315
2316 mfg_id = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
2317 if (mfg_id == -EIO)
2318 return -EIO;
2319
2320 adapter->flash_mfg_id = (mfg_id & 0xFF);
2321 qlcnic_83xx_unlock_flash(adapter);
2322
2323 return 0;
2324 }
2325
2326 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2327 {
2328 int count, fdt_size, ret = 0;
2329
2330 fdt_size = sizeof(struct qlcnic_fdt);
2331 count = fdt_size / sizeof(u32);
2332
2333 if (qlcnic_83xx_lock_flash(adapter))
2334 return -EIO;
2335
2336 memset(&adapter->ahw->fdt, 0, fdt_size);
2337 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2338 (u8 *)&adapter->ahw->fdt,
2339 count);
2340
2341 qlcnic_83xx_unlock_flash(adapter);
2342 return ret;
2343 }
2344
2345 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2346 u32 sector_start_addr)
2347 {
2348 u32 reversed_addr, addr1, addr2, cmd;
2349 int ret = -EIO;
2350
2351 if (qlcnic_83xx_lock_flash(adapter) != 0)
2352 return -EIO;
2353
2354 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2355 ret = qlcnic_83xx_enable_flash_write(adapter);
2356 if (ret) {
2357 qlcnic_83xx_unlock_flash(adapter);
2358 dev_err(&adapter->pdev->dev,
2359 "%s failed at %d\n",
2360 __func__, __LINE__);
2361 return ret;
2362 }
2363 }
2364
2365 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2366 if (ret) {
2367 qlcnic_83xx_unlock_flash(adapter);
2368 dev_err(&adapter->pdev->dev,
2369 "%s: failed at %d\n", __func__, __LINE__);
2370 return -EIO;
2371 }
2372
2373 addr1 = (sector_start_addr & 0xFF) << 16;
2374 addr2 = (sector_start_addr & 0xFF0000) >> 16;
2375 reversed_addr = addr1 | addr2;
2376
2377 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2378 reversed_addr);
2379 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2380 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2381 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2382 else
2383 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2384 QLC_83XX_FLASH_OEM_ERASE_SIG);
2385 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2386 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2387
2388 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2389 if (ret) {
2390 qlcnic_83xx_unlock_flash(adapter);
2391 dev_err(&adapter->pdev->dev,
2392 "%s: failed at %d\n", __func__, __LINE__);
2393 return -EIO;
2394 }
2395
2396 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2397 ret = qlcnic_83xx_disable_flash_write(adapter);
2398 if (ret) {
2399 qlcnic_83xx_unlock_flash(adapter);
2400 dev_err(&adapter->pdev->dev,
2401 "%s: failed at %d\n", __func__, __LINE__);
2402 return ret;
2403 }
2404 }
2405
2406 qlcnic_83xx_unlock_flash(adapter);
2407
2408 return 0;
2409 }
2410
2411 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2412 u32 *p_data)
2413 {
2414 int ret = -EIO;
2415 u32 addr1 = 0x00800000 | (addr >> 2);
2416
2417 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2418 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2419 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2420 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2421 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2422 if (ret) {
2423 dev_err(&adapter->pdev->dev,
2424 "%s: failed at %d\n", __func__, __LINE__);
2425 return -EIO;
2426 }
2427
2428 return 0;
2429 }
2430
2431 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2432 u32 *p_data, int count)
2433 {
2434 u32 temp;
2435 int ret = -EIO;
2436
2437 if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2438 (count > QLC_83XX_FLASH_WRITE_MAX)) {
2439 dev_err(&adapter->pdev->dev,
2440 "%s: Invalid word count\n", __func__);
2441 return -EIO;
2442 }
2443
2444 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2445 QLC_83XX_FLASH_SPI_CONTROL);
2446 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2447 (temp | QLC_83XX_FLASH_SPI_CTRL));
2448 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2449 QLC_83XX_FLASH_ADDR_TEMP_VAL);
2450
2451 /* First DWORD write */
2452 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2453 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2454 QLC_83XX_FLASH_FIRST_MS_PATTERN);
2455 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2456 if (ret) {
2457 dev_err(&adapter->pdev->dev,
2458 "%s: failed at %d\n", __func__, __LINE__);
2459 return -EIO;
2460 }
2461
2462 count--;
2463 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2464 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2465 /* Second to N-1 DWORD writes */
2466 while (count != 1) {
2467 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2468 *p_data++);
2469 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2470 QLC_83XX_FLASH_SECOND_MS_PATTERN);
2471 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2472 if (ret) {
2473 dev_err(&adapter->pdev->dev,
2474 "%s: failed at %d\n", __func__, __LINE__);
2475 return -EIO;
2476 }
2477 count--;
2478 }
2479
2480 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2481 QLC_83XX_FLASH_ADDR_TEMP_VAL |
2482 (addr >> 2));
2483 /* Last DWORD write */
2484 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2485 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2486 QLC_83XX_FLASH_LAST_MS_PATTERN);
2487 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2488 if (ret) {
2489 dev_err(&adapter->pdev->dev,
2490 "%s: failed at %d\n", __func__, __LINE__);
2491 return -EIO;
2492 }
2493
2494 ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_SPI_STATUS);
2495 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2496 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2497 __func__, __LINE__);
2498 /* Operation failed, clear error bit */
2499 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2500 QLC_83XX_FLASH_SPI_CONTROL);
2501 qlcnic_83xx_wrt_reg_indirect(adapter,
2502 QLC_83XX_FLASH_SPI_CONTROL,
2503 (temp | QLC_83XX_FLASH_SPI_CTRL));
2504 }
2505
2506 return 0;
2507 }
2508
2509 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2510 {
2511 u32 val, id;
2512
2513 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2514
2515 /* Check if recovery need to be performed by the calling function */
2516 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2517 val = val & ~0x3F;
2518 val = val | ((adapter->portnum << 2) |
2519 QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2520 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2521 dev_info(&adapter->pdev->dev,
2522 "%s: lock recovery initiated\n", __func__);
2523 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2524 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2525 id = ((val >> 2) & 0xF);
2526 if (id == adapter->portnum) {
2527 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2528 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2529 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2530 /* Force release the lock */
2531 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2532 /* Clear recovery bits */
2533 val = val & ~0x3F;
2534 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2535 dev_info(&adapter->pdev->dev,
2536 "%s: lock recovery completed\n", __func__);
2537 } else {
2538 dev_info(&adapter->pdev->dev,
2539 "%s: func %d to resume lock recovery process\n",
2540 __func__, id);
2541 }
2542 } else {
2543 dev_info(&adapter->pdev->dev,
2544 "%s: lock recovery initiated by other functions\n",
2545 __func__);
2546 }
2547 }
2548
2549 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2550 {
2551 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2552 int max_attempt = 0;
2553
2554 while (status == 0) {
2555 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2556 if (status)
2557 break;
2558
2559 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2560 i++;
2561
2562 if (i == 1)
2563 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2564
2565 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2566 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2567 if (val == temp) {
2568 id = val & 0xFF;
2569 dev_info(&adapter->pdev->dev,
2570 "%s: lock to be recovered from %d\n",
2571 __func__, id);
2572 qlcnic_83xx_recover_driver_lock(adapter);
2573 i = 0;
2574 max_attempt++;
2575 } else {
2576 dev_err(&adapter->pdev->dev,
2577 "%s: failed to get lock\n", __func__);
2578 return -EIO;
2579 }
2580 }
2581
2582 /* Force exit from while loop after few attempts */
2583 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2584 dev_err(&adapter->pdev->dev,
2585 "%s: failed to get lock\n", __func__);
2586 return -EIO;
2587 }
2588 }
2589
2590 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2591 lock_alive_counter = val >> 8;
2592 lock_alive_counter++;
2593 val = lock_alive_counter << 8 | adapter->portnum;
2594 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2595
2596 return 0;
2597 }
2598
2599 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2600 {
2601 u32 val, lock_alive_counter, id;
2602
2603 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2604 id = val & 0xFF;
2605 lock_alive_counter = val >> 8;
2606
2607 if (id != adapter->portnum)
2608 dev_err(&adapter->pdev->dev,
2609 "%s:Warning func %d is unlocking lock owned by %d\n",
2610 __func__, adapter->portnum, id);
2611
2612 val = (lock_alive_counter << 8) | 0xFF;
2613 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2614 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2615 }
2616
2617 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2618 u32 *data, u32 count)
2619 {
2620 int i, j, ret = 0;
2621 u32 temp;
2622
2623 /* Check alignment */
2624 if (addr & 0xF)
2625 return -EIO;
2626
2627 mutex_lock(&adapter->ahw->mem_lock);
2628 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2629
2630 for (i = 0; i < count; i++, addr += 16) {
2631 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2632 QLCNIC_ADDR_QDR_NET_MAX)) ||
2633 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2634 QLCNIC_ADDR_DDR_NET_MAX)))) {
2635 mutex_unlock(&adapter->ahw->mem_lock);
2636 return -EIO;
2637 }
2638
2639 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2640 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2641 *data++);
2642 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2643 *data++);
2644 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2645 *data++);
2646 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2647 *data++);
2648 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2649 QLCNIC_TA_WRITE_ENABLE);
2650 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2651 QLCNIC_TA_WRITE_START);
2652
2653 for (j = 0; j < MAX_CTL_CHECK; j++) {
2654 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2655 QLCNIC_MS_CTRL);
2656 if ((temp & TA_CTL_BUSY) == 0)
2657 break;
2658 }
2659
2660 /* Status check failure */
2661 if (j >= MAX_CTL_CHECK) {
2662 printk_ratelimited(KERN_WARNING
2663 "MS memory write failed\n");
2664 mutex_unlock(&adapter->ahw->mem_lock);
2665 return -EIO;
2666 }
2667 }
2668
2669 mutex_unlock(&adapter->ahw->mem_lock);
2670
2671 return ret;
2672 }
2673
2674 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2675 u8 *p_data, int count)
2676 {
2677 int i, ret;
2678 u32 word, addr = flash_addr;
2679 ulong indirect_addr;
2680
2681 if (qlcnic_83xx_lock_flash(adapter) != 0)
2682 return -EIO;
2683
2684 if (addr & 0x3) {
2685 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2686 qlcnic_83xx_unlock_flash(adapter);
2687 return -EIO;
2688 }
2689
2690 for (i = 0; i < count; i++) {
2691 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2692 QLC_83XX_FLASH_DIRECT_WINDOW,
2693 (addr))) {
2694 qlcnic_83xx_unlock_flash(adapter);
2695 return -EIO;
2696 }
2697
2698 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2699 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2700 indirect_addr);
2701 if (ret == -EIO)
2702 return -EIO;
2703 word = ret;
2704 *(u32 *)p_data = word;
2705 p_data = p_data + 4;
2706 addr = addr + 4;
2707 }
2708
2709 qlcnic_83xx_unlock_flash(adapter);
2710
2711 return 0;
2712 }
2713
2714 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2715 {
2716 u8 pci_func;
2717 int err;
2718 u32 config = 0, state;
2719 struct qlcnic_cmd_args cmd;
2720 struct qlcnic_hardware_context *ahw = adapter->ahw;
2721
2722 if (qlcnic_sriov_vf_check(adapter))
2723 pci_func = adapter->portnum;
2724 else
2725 pci_func = ahw->pci_func;
2726
2727 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
2728 if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
2729 dev_info(&adapter->pdev->dev, "link state down\n");
2730 return config;
2731 }
2732 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
2733 err = qlcnic_issue_cmd(adapter, &cmd);
2734 if (err) {
2735 dev_info(&adapter->pdev->dev,
2736 "Get Link Status Command failed: 0x%x\n", err);
2737 goto out;
2738 } else {
2739 config = cmd.rsp.arg[1];
2740 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
2741 case QLC_83XX_10M_LINK:
2742 ahw->link_speed = SPEED_10;
2743 break;
2744 case QLC_83XX_100M_LINK:
2745 ahw->link_speed = SPEED_100;
2746 break;
2747 case QLC_83XX_1G_LINK:
2748 ahw->link_speed = SPEED_1000;
2749 break;
2750 case QLC_83XX_10G_LINK:
2751 ahw->link_speed = SPEED_10000;
2752 break;
2753 default:
2754 ahw->link_speed = 0;
2755 break;
2756 }
2757 config = cmd.rsp.arg[3];
2758 if (config & 1)
2759 err = 1;
2760 }
2761 out:
2762 qlcnic_free_mbx_args(&cmd);
2763 return config;
2764 }
2765
2766 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter)
2767 {
2768 u32 config = 0;
2769 int status = 0;
2770 struct qlcnic_hardware_context *ahw = adapter->ahw;
2771
2772 /* Get port configuration info */
2773 status = qlcnic_83xx_get_port_info(adapter);
2774 /* Get Link Status related info */
2775 config = qlcnic_83xx_test_link(adapter);
2776 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
2777 /* hard code until there is a way to get it from flash */
2778 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
2779 return status;
2780 }
2781
2782 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
2783 struct ethtool_cmd *ecmd)
2784 {
2785 int status = 0;
2786 u32 config = adapter->ahw->port_config;
2787
2788 if (ecmd->autoneg)
2789 adapter->ahw->port_config |= BIT_15;
2790
2791 switch (ethtool_cmd_speed(ecmd)) {
2792 case SPEED_10:
2793 adapter->ahw->port_config |= BIT_8;
2794 break;
2795 case SPEED_100:
2796 adapter->ahw->port_config |= BIT_9;
2797 break;
2798 case SPEED_1000:
2799 adapter->ahw->port_config |= BIT_10;
2800 break;
2801 case SPEED_10000:
2802 adapter->ahw->port_config |= BIT_11;
2803 break;
2804 default:
2805 return -EINVAL;
2806 }
2807
2808 status = qlcnic_83xx_set_port_config(adapter);
2809 if (status) {
2810 dev_info(&adapter->pdev->dev,
2811 "Faild to Set Link Speed and autoneg.\n");
2812 adapter->ahw->port_config = config;
2813 }
2814 return status;
2815 }
2816
2817 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
2818 u64 *data, int index)
2819 {
2820 u32 low, hi;
2821 u64 val;
2822
2823 low = cmd->rsp.arg[index];
2824 hi = cmd->rsp.arg[index + 1];
2825 val = (((u64) low) | (((u64) hi) << 32));
2826 *data++ = val;
2827 return data;
2828 }
2829
2830 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
2831 struct qlcnic_cmd_args *cmd, u64 *data,
2832 int type, int *ret)
2833 {
2834 int err, k, total_regs;
2835
2836 *ret = 0;
2837 err = qlcnic_issue_cmd(adapter, cmd);
2838 if (err != QLCNIC_RCODE_SUCCESS) {
2839 dev_info(&adapter->pdev->dev,
2840 "Error in get statistics mailbox command\n");
2841 *ret = -EIO;
2842 return data;
2843 }
2844 total_regs = cmd->rsp.num;
2845 switch (type) {
2846 case QLC_83XX_STAT_MAC:
2847 /* fill in MAC tx counters */
2848 for (k = 2; k < 28; k += 2)
2849 data = qlcnic_83xx_copy_stats(cmd, data, k);
2850 /* skip 24 bytes of reserved area */
2851 /* fill in MAC rx counters */
2852 for (k += 6; k < 60; k += 2)
2853 data = qlcnic_83xx_copy_stats(cmd, data, k);
2854 /* skip 24 bytes of reserved area */
2855 /* fill in MAC rx frame stats */
2856 for (k += 6; k < 80; k += 2)
2857 data = qlcnic_83xx_copy_stats(cmd, data, k);
2858 break;
2859 case QLC_83XX_STAT_RX:
2860 for (k = 2; k < 8; k += 2)
2861 data = qlcnic_83xx_copy_stats(cmd, data, k);
2862 /* skip 8 bytes of reserved data */
2863 for (k += 2; k < 24; k += 2)
2864 data = qlcnic_83xx_copy_stats(cmd, data, k);
2865 /* skip 8 bytes containing RE1FBQ error data */
2866 for (k += 2; k < total_regs; k += 2)
2867 data = qlcnic_83xx_copy_stats(cmd, data, k);
2868 break;
2869 case QLC_83XX_STAT_TX:
2870 for (k = 2; k < 10; k += 2)
2871 data = qlcnic_83xx_copy_stats(cmd, data, k);
2872 /* skip 8 bytes of reserved data */
2873 for (k += 2; k < total_regs; k += 2)
2874 data = qlcnic_83xx_copy_stats(cmd, data, k);
2875 break;
2876 default:
2877 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
2878 *ret = -EIO;
2879 }
2880 return data;
2881 }
2882
2883 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
2884 {
2885 struct qlcnic_cmd_args cmd;
2886 int ret = 0;
2887
2888 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
2889 /* Get Tx stats */
2890 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
2891 cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
2892 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
2893 QLC_83XX_STAT_TX, &ret);
2894 if (ret) {
2895 dev_info(&adapter->pdev->dev, "Error getting MAC stats\n");
2896 goto out;
2897 }
2898 /* Get MAC stats */
2899 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
2900 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
2901 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
2902 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
2903 QLC_83XX_STAT_MAC, &ret);
2904 if (ret) {
2905 dev_info(&adapter->pdev->dev,
2906 "Error getting Rx stats\n");
2907 goto out;
2908 }
2909 /* Get Rx stats */
2910 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
2911 cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
2912 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
2913 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
2914 QLC_83XX_STAT_RX, &ret);
2915 if (ret)
2916 dev_info(&adapter->pdev->dev,
2917 "Error getting Tx stats\n");
2918 out:
2919 qlcnic_free_mbx_args(&cmd);
2920 }
2921
2922 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
2923 {
2924 u32 major, minor, sub;
2925
2926 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
2927 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
2928 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
2929
2930 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
2931 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
2932 __func__);
2933 return 1;
2934 }
2935 return 0;
2936 }
2937
2938 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
2939 {
2940 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
2941 sizeof(adapter->ahw->ext_reg_tbl)) +
2942 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) +
2943 sizeof(adapter->ahw->reg_tbl));
2944 }
2945
2946 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
2947 {
2948 int i, j = 0;
2949
2950 for (i = QLCNIC_DEV_INFO_SIZE + 1;
2951 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
2952 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
2953
2954 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
2955 regs_buff[i++] = QLCRDX(adapter->ahw, j);
2956 return i;
2957 }
2958
2959 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
2960 {
2961 struct qlcnic_adapter *adapter = netdev_priv(netdev);
2962 struct qlcnic_hardware_context *ahw = adapter->ahw;
2963 struct qlcnic_cmd_args cmd;
2964 u32 data;
2965 u16 intrpt_id, id;
2966 u8 val;
2967 int ret, max_sds_rings = adapter->max_sds_rings;
2968
2969 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
2970 return -EIO;
2971
2972 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST);
2973 if (ret)
2974 goto fail_diag_irq;
2975
2976 ahw->diag_cnt = 0;
2977 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
2978
2979 if (adapter->flags & QLCNIC_MSIX_ENABLED)
2980 intrpt_id = ahw->intr_tbl[0].id;
2981 else
2982 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
2983
2984 cmd.req.arg[1] = 1;
2985 cmd.req.arg[2] = intrpt_id;
2986 cmd.req.arg[3] = BIT_0;
2987
2988 ret = qlcnic_issue_cmd(adapter, &cmd);
2989 data = cmd.rsp.arg[2];
2990 id = LSW(data);
2991 val = LSB(MSW(data));
2992 if (id != intrpt_id)
2993 dev_info(&adapter->pdev->dev,
2994 "Interrupt generated: 0x%x, requested:0x%x\n",
2995 id, intrpt_id);
2996 if (val)
2997 dev_err(&adapter->pdev->dev,
2998 "Interrupt test error: 0x%x\n", val);
2999 if (ret)
3000 goto done;
3001
3002 msleep(20);
3003 ret = !ahw->diag_cnt;
3004
3005 done:
3006 qlcnic_free_mbx_args(&cmd);
3007 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
3008
3009 fail_diag_irq:
3010 adapter->max_sds_rings = max_sds_rings;
3011 clear_bit(__QLCNIC_RESETTING, &adapter->state);
3012 return ret;
3013 }
3014
3015 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3016 struct ethtool_pauseparam *pause)
3017 {
3018 struct qlcnic_hardware_context *ahw = adapter->ahw;
3019 int status = 0;
3020 u32 config;
3021
3022 status = qlcnic_83xx_get_port_config(adapter);
3023 if (status) {
3024 dev_err(&adapter->pdev->dev,
3025 "%s: Get Pause Config failed\n", __func__);
3026 return;
3027 }
3028 config = ahw->port_config;
3029 if (config & QLC_83XX_CFG_STD_PAUSE) {
3030 if (config & QLC_83XX_CFG_STD_TX_PAUSE)
3031 pause->tx_pause = 1;
3032 if (config & QLC_83XX_CFG_STD_RX_PAUSE)
3033 pause->rx_pause = 1;
3034 }
3035
3036 if (QLC_83XX_AUTONEG(config))
3037 pause->autoneg = 1;
3038 }
3039
3040 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3041 struct ethtool_pauseparam *pause)
3042 {
3043 struct qlcnic_hardware_context *ahw = adapter->ahw;
3044 int status = 0;
3045 u32 config;
3046
3047 status = qlcnic_83xx_get_port_config(adapter);
3048 if (status) {
3049 dev_err(&adapter->pdev->dev,
3050 "%s: Get Pause Config failed.\n", __func__);
3051 return status;
3052 }
3053 config = ahw->port_config;
3054
3055 if (ahw->port_type == QLCNIC_GBE) {
3056 if (pause->autoneg)
3057 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3058 if (!pause->autoneg)
3059 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3060 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3061 return -EOPNOTSUPP;
3062 }
3063
3064 if (!(config & QLC_83XX_CFG_STD_PAUSE))
3065 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3066
3067 if (pause->rx_pause && pause->tx_pause) {
3068 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3069 } else if (pause->rx_pause && !pause->tx_pause) {
3070 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3071 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3072 } else if (pause->tx_pause && !pause->rx_pause) {
3073 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3074 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3075 } else if (!pause->rx_pause && !pause->tx_pause) {
3076 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_RX_PAUSE;
3077 }
3078 status = qlcnic_83xx_set_port_config(adapter);
3079 if (status) {
3080 dev_err(&adapter->pdev->dev,
3081 "%s: Set Pause Config failed.\n", __func__);
3082 ahw->port_config = config;
3083 }
3084 return status;
3085 }
3086
3087 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3088 {
3089 int ret;
3090
3091 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3092 QLC_83XX_FLASH_OEM_READ_SIG);
3093 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3094 QLC_83XX_FLASH_READ_CTRL);
3095 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3096 if (ret)
3097 return -EIO;
3098
3099 ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
3100 return ret & 0xFF;
3101 }
3102
3103 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3104 {
3105 int status;
3106
3107 status = qlcnic_83xx_read_flash_status_reg(adapter);
3108 if (status == -EIO) {
3109 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3110 __func__);
3111 return 1;
3112 }
3113 return 0;
3114 }
kernel source for telekom puls (alcatel/mediatek)