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Merge branch 'for-3.10' of git://linux-nfs.org/~bfields/linux
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic.h
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #ifndef _QLCNIC_H_
9 #define _QLCNIC_H_
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ip.h>
19 #include <linux/in.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
23
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/timer.h>
27
28 #include <linux/vmalloc.h>
29
30 #include <linux/io.h>
31 #include <asm/byteorder.h>
32 #include <linux/bitops.h>
33 #include <linux/if_vlan.h>
34
35 #include "qlcnic_hdr.h"
36 #include "qlcnic_hw.h"
37 #include "qlcnic_83xx_hw.h"
38
39 #define _QLCNIC_LINUX_MAJOR 5
40 #define _QLCNIC_LINUX_MINOR 2
41 #define _QLCNIC_LINUX_SUBVERSION 42
42 #define QLCNIC_LINUX_VERSIONID "5.2.42"
43 #define QLCNIC_DRV_IDC_VER 0x01
44 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
45 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
46
47 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
48 #define _major(v) (((v) >> 24) & 0xff)
49 #define _minor(v) (((v) >> 16) & 0xff)
50 #define _build(v) ((v) & 0xffff)
51
52 /* version in image has weird encoding:
53 * 7:0 - major
54 * 15:8 - minor
55 * 31:16 - build (little endian)
56 */
57 #define QLCNIC_DECODE_VERSION(v) \
58 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
59
60 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
61 #define QLCNIC_NUM_FLASH_SECTORS (64)
62 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
63 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
64 * QLCNIC_FLASH_SECTOR_SIZE)
65
66 #define RCV_DESC_RINGSIZE(rds_ring) \
67 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
68 #define RCV_BUFF_RINGSIZE(rds_ring) \
69 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
70 #define STATUS_DESC_RINGSIZE(sds_ring) \
71 (sizeof(struct status_desc) * (sds_ring)->num_desc)
72 #define TX_BUFF_RINGSIZE(tx_ring) \
73 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
74 #define TX_DESC_RINGSIZE(tx_ring) \
75 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
76
77 #define QLCNIC_P3P_A0 0x50
78 #define QLCNIC_P3P_C0 0x58
79
80 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
81
82 #define FIRST_PAGE_GROUP_START 0
83 #define FIRST_PAGE_GROUP_END 0x100000
84
85 #define P3P_MAX_MTU (9600)
86 #define P3P_MIN_MTU (68)
87 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
88
89 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
90 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
91 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
92 #define QLCNIC_LRO_BUFFER_EXTRA 2048
93
94 /* Tx defines */
95 #define QLCNIC_MAX_FRAGS_PER_TX 14
96 #define MAX_TSO_HEADER_DESC 2
97 #define MGMT_CMD_DESC_RESV 4
98 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
99 + MGMT_CMD_DESC_RESV)
100 #define QLCNIC_MAX_TX_TIMEOUTS 2
101 /*
102 * Following are the states of the Phantom. Phantom will set them and
103 * Host will read to check if the fields are correct.
104 */
105 #define PHAN_INITIALIZE_FAILED 0xffff
106 #define PHAN_INITIALIZE_COMPLETE 0xff01
107
108 /* Host writes the following to notify that it has done the init-handshake */
109 #define PHAN_INITIALIZE_ACK 0xf00f
110 #define PHAN_PEG_RCV_INITIALIZED 0xff01
111
112 #define NUM_RCV_DESC_RINGS 3
113
114 #define RCV_RING_NORMAL 0
115 #define RCV_RING_JUMBO 1
116
117 #define MIN_CMD_DESCRIPTORS 64
118 #define MIN_RCV_DESCRIPTORS 64
119 #define MIN_JUMBO_DESCRIPTORS 32
120
121 #define MAX_CMD_DESCRIPTORS 1024
122 #define MAX_RCV_DESCRIPTORS_1G 4096
123 #define MAX_RCV_DESCRIPTORS_10G 8192
124 #define MAX_RCV_DESCRIPTORS_VF 2048
125 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
126 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
127
128 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
129 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
130 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
131 #define MAX_RDS_RINGS 2
132
133 #define get_next_index(index, length) \
134 (((index) + 1) & ((length) - 1))
135
136 /*
137 * Following data structures describe the descriptors that will be used.
138 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
139 * we are doing LSO (above the 1500 size packet) only.
140 */
141 struct cmd_desc_type0 {
142 u8 tcp_hdr_offset; /* For LSO only */
143 u8 ip_hdr_offset; /* For LSO only */
144 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
145 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
146
147 __le64 addr_buffer2;
148
149 __le16 reference_handle;
150 __le16 mss;
151 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
152 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
153 __le16 conn_id; /* IPSec offoad only */
154
155 __le64 addr_buffer3;
156 __le64 addr_buffer1;
157
158 __le16 buffer_length[4];
159
160 __le64 addr_buffer4;
161
162 u8 eth_addr[ETH_ALEN];
163 __le16 vlan_TCI;
164
165 } __attribute__ ((aligned(64)));
166
167 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
168 struct rcv_desc {
169 __le16 reference_handle;
170 __le16 reserved;
171 __le32 buffer_length; /* allocated buffer length (usually 2K) */
172 __le64 addr_buffer;
173 } __packed;
174
175 struct status_desc {
176 __le64 status_desc_data[2];
177 } __attribute__ ((aligned(16)));
178
179 /* UNIFIED ROMIMAGE */
180 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
181 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
182 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
183 #define QLCNIC_UNI_DIR_SECT_FW 0x7
184
185 /*Offsets */
186 #define QLCNIC_UNI_CHIP_REV_OFF 10
187 #define QLCNIC_UNI_FLAGS_OFF 11
188 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
189 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
190 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
191
192 struct uni_table_desc{
193 __le32 findex;
194 __le32 num_entries;
195 __le32 entry_size;
196 __le32 reserved[5];
197 };
198
199 struct uni_data_desc{
200 __le32 findex;
201 __le32 size;
202 __le32 reserved[5];
203 };
204
205 /* Flash Defines and Structures */
206 #define QLCNIC_FLT_LOCATION 0x3F1000
207 #define QLCNIC_FDT_LOCATION 0x3F0000
208 #define QLCNIC_B0_FW_IMAGE_REGION 0x74
209 #define QLCNIC_C0_FW_IMAGE_REGION 0x97
210 #define QLCNIC_BOOTLD_REGION 0X72
211 struct qlcnic_flt_header {
212 u16 version;
213 u16 len;
214 u16 checksum;
215 u16 reserved;
216 };
217
218 struct qlcnic_flt_entry {
219 u8 region;
220 u8 reserved0;
221 u8 attrib;
222 u8 reserved1;
223 u32 size;
224 u32 start_addr;
225 u32 end_addr;
226 };
227
228 /* Flash Descriptor Table */
229 struct qlcnic_fdt {
230 u32 valid;
231 u16 ver;
232 u16 len;
233 u16 cksum;
234 u16 unused;
235 u8 model[16];
236 u16 mfg_id;
237 u16 id;
238 u8 flag;
239 u8 erase_cmd;
240 u8 alt_erase_cmd;
241 u8 write_enable_cmd;
242 u8 write_enable_bits;
243 u8 write_statusreg_cmd;
244 u8 unprotected_sec_cmd;
245 u8 read_manuf_cmd;
246 u32 block_size;
247 u32 alt_block_size;
248 u32 flash_size;
249 u32 write_enable_data;
250 u8 readid_addr_len;
251 u8 write_disable_bits;
252 u8 read_dev_id_len;
253 u8 chip_erase_cmd;
254 u16 read_timeo;
255 u8 protected_sec_cmd;
256 u8 resvd[65];
257 };
258 /* Magic number to let user know flash is programmed */
259 #define QLCNIC_BDINFO_MAGIC 0x12345678
260
261 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
262 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
263 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
264 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
265 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
266 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
267 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
268 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
269 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
270 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
271 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
272 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
273 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
274 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
275
276 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
277
278 /* Flash memory map */
279 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
280 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
281 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
282 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
283
284 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
285 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
286 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
287 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
288
289 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
290 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
291
292 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
293 #define QLCNIC_UNIFIED_ROMIMAGE 0
294 #define QLCNIC_FLASH_ROMIMAGE 1
295 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
296
297 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
298 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
299
300 extern char qlcnic_driver_name[];
301
302 extern int qlcnic_use_msi;
303 extern int qlcnic_use_msi_x;
304 extern int qlcnic_auto_fw_reset;
305 extern int qlcnic_load_fw_file;
306 extern int qlcnic_config_npars;
307
308 /* Number of status descriptors to handle per interrupt */
309 #define MAX_STATUS_HANDLE (64)
310
311 /*
312 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
313 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
314 */
315 struct qlcnic_skb_frag {
316 u64 dma;
317 u64 length;
318 };
319
320 /* Following defines are for the state of the buffers */
321 #define QLCNIC_BUFFER_FREE 0
322 #define QLCNIC_BUFFER_BUSY 1
323
324 /*
325 * There will be one qlcnic_buffer per skb packet. These will be
326 * used to save the dma info for pci_unmap_page()
327 */
328 struct qlcnic_cmd_buffer {
329 struct sk_buff *skb;
330 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
331 u32 frag_count;
332 };
333
334 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
335 struct qlcnic_rx_buffer {
336 u16 ref_handle;
337 struct sk_buff *skb;
338 struct list_head list;
339 u64 dma;
340 };
341
342 /* Board types */
343 #define QLCNIC_GBE 0x01
344 #define QLCNIC_XGBE 0x02
345
346 /*
347 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
348 * adjusted based on configured MTU.
349 */
350 #define QLCNIC_INTR_COAL_TYPE_RX 1
351 #define QLCNIC_INTR_COAL_TYPE_TX 2
352
353 #define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3
354 #define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256
355
356 #define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64
357 #define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64
358
359 #define QLCNIC_INTR_DEFAULT 0x04
360 #define QLCNIC_CONFIG_INTR_COALESCE 3
361 #define QLCNIC_DEV_INFO_SIZE 1
362
363 struct qlcnic_nic_intr_coalesce {
364 u8 type;
365 u8 sts_ring_mask;
366 u16 rx_packets;
367 u16 rx_time_us;
368 u16 tx_packets;
369 u16 tx_time_us;
370 u16 flag;
371 u32 timer_out;
372 };
373
374 struct qlcnic_dump_template_hdr {
375 u32 type;
376 u32 offset;
377 u32 size;
378 u32 cap_mask;
379 u32 num_entries;
380 u32 version;
381 u32 timestamp;
382 u32 checksum;
383 u32 drv_cap_mask;
384 u32 sys_info[3];
385 u32 saved_state[16];
386 u32 cap_sizes[8];
387 u32 ocm_wnd_reg[16];
388 u32 rsvd[0];
389 };
390
391 struct qlcnic_fw_dump {
392 u8 clr; /* flag to indicate if dump is cleared */
393 u8 enable; /* enable/disable dump */
394 u32 size; /* total size of the dump */
395 void *data; /* dump data area */
396 struct qlcnic_dump_template_hdr *tmpl_hdr;
397 };
398
399 /*
400 * One hardware_context{} per adapter
401 * contains interrupt info as well shared hardware info.
402 */
403 struct qlcnic_hardware_context {
404 void __iomem *pci_base0;
405 void __iomem *ocm_win_crb;
406
407 unsigned long pci_len0;
408
409 rwlock_t crb_lock;
410 struct mutex mem_lock;
411
412 u8 revision_id;
413 u8 pci_func;
414 u8 linkup;
415 u8 loopback_state;
416 u8 beacon_state;
417 u8 has_link_events;
418 u8 fw_type;
419 u8 physical_port;
420 u8 reset_context;
421 u8 msix_supported;
422 u8 max_mac_filters;
423 u8 mc_enabled;
424 u8 max_mc_count;
425 u8 diag_test;
426 u8 num_msix;
427 u8 nic_mode;
428 char diag_cnt;
429
430 u16 port_type;
431 u16 board_type;
432 u16 supported_type;
433
434 u16 link_speed;
435 u16 link_duplex;
436 u16 link_autoneg;
437 u16 module_type;
438
439 u16 op_mode;
440 u16 switch_mode;
441 u16 max_tx_ques;
442 u16 max_rx_ques;
443 u16 max_mtu;
444 u32 msg_enable;
445 u16 act_pci_func;
446
447 u32 capabilities;
448 u32 capabilities2;
449 u32 temp;
450 u32 int_vec_bit;
451 u32 fw_hal_version;
452 u32 port_config;
453 struct qlcnic_hardware_ops *hw_ops;
454 struct qlcnic_nic_intr_coalesce coal;
455 struct qlcnic_fw_dump fw_dump;
456 struct qlcnic_fdt fdt;
457 struct qlc_83xx_reset reset;
458 struct qlc_83xx_idc idc;
459 struct qlc_83xx_fw_info fw_info;
460 struct qlcnic_intrpt_config *intr_tbl;
461 struct qlcnic_sriov *sriov;
462 u32 *reg_tbl;
463 u32 *ext_reg_tbl;
464 u32 mbox_aen[QLC_83XX_MBX_AEN_CNT];
465 u32 mbox_reg[4];
466 spinlock_t mbx_lock;
467 };
468
469 struct qlcnic_adapter_stats {
470 u64 xmitcalled;
471 u64 xmitfinished;
472 u64 rxdropped;
473 u64 txdropped;
474 u64 csummed;
475 u64 rx_pkts;
476 u64 lro_pkts;
477 u64 rxbytes;
478 u64 txbytes;
479 u64 lrobytes;
480 u64 lso_frames;
481 u64 xmit_on;
482 u64 xmit_off;
483 u64 skb_alloc_failure;
484 u64 null_rxbuf;
485 u64 rx_dma_map_error;
486 u64 tx_dma_map_error;
487 u64 spurious_intr;
488 u64 mac_filter_limit_overrun;
489 };
490
491 /*
492 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
493 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
494 */
495 struct qlcnic_host_rds_ring {
496 void __iomem *crb_rcv_producer;
497 struct rcv_desc *desc_head;
498 struct qlcnic_rx_buffer *rx_buf_arr;
499 u32 num_desc;
500 u32 producer;
501 u32 dma_size;
502 u32 skb_size;
503 u32 flags;
504 struct list_head free_list;
505 spinlock_t lock;
506 dma_addr_t phys_addr;
507 } ____cacheline_internodealigned_in_smp;
508
509 struct qlcnic_host_sds_ring {
510 u32 consumer;
511 u32 num_desc;
512 void __iomem *crb_sts_consumer;
513
514 struct status_desc *desc_head;
515 struct qlcnic_adapter *adapter;
516 struct napi_struct napi;
517 struct list_head free_list[NUM_RCV_DESC_RINGS];
518
519 void __iomem *crb_intr_mask;
520 int irq;
521
522 dma_addr_t phys_addr;
523 char name[IFNAMSIZ + 12];
524 } ____cacheline_internodealigned_in_smp;
525
526 struct qlcnic_host_tx_ring {
527 int irq;
528 void __iomem *crb_intr_mask;
529 char name[IFNAMSIZ + 12];
530 u16 ctx_id;
531 u32 producer;
532 u32 sw_consumer;
533 u32 num_desc;
534 void __iomem *crb_cmd_producer;
535 struct cmd_desc_type0 *desc_head;
536 struct qlcnic_adapter *adapter;
537 struct napi_struct napi;
538 struct qlcnic_cmd_buffer *cmd_buf_arr;
539 __le32 *hw_consumer;
540
541 dma_addr_t phys_addr;
542 dma_addr_t hw_cons_phys_addr;
543 struct netdev_queue *txq;
544 } ____cacheline_internodealigned_in_smp;
545
546 /*
547 * Receive context. There is one such structure per instance of the
548 * receive processing. Any state information that is relevant to
549 * the receive, and is must be in this structure. The global data may be
550 * present elsewhere.
551 */
552 struct qlcnic_recv_context {
553 struct qlcnic_host_rds_ring *rds_rings;
554 struct qlcnic_host_sds_ring *sds_rings;
555 u32 state;
556 u16 context_id;
557 u16 virt_port;
558
559 };
560
561 /* HW context creation */
562
563 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
564
565 #define QLCNIC_CDRP_CMD_BIT 0x80000000
566
567 /*
568 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
569 * in the crb QLCNIC_CDRP_CRB_OFFSET.
570 */
571 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
572 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
573
574 #define QLCNIC_CDRP_RSP_OK 0x00000001
575 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
576 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
577
578 /*
579 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
580 * the crb QLCNIC_CDRP_CRB_OFFSET.
581 */
582 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
583
584 #define QLCNIC_RCODE_SUCCESS 0
585 #define QLCNIC_RCODE_INVALID_ARGS 6
586 #define QLCNIC_RCODE_NOT_SUPPORTED 9
587 #define QLCNIC_RCODE_NOT_PERMITTED 10
588 #define QLCNIC_RCODE_NOT_IMPL 15
589 #define QLCNIC_RCODE_INVALID 16
590 #define QLCNIC_RCODE_TIMEOUT 17
591 #define QLCNIC_DESTROY_CTX_RESET 0
592
593 /*
594 * Capabilities Announced
595 */
596 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
597 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
598 #define QLCNIC_CAP0_LSO (1 << 6)
599 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
600 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
601 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
602 #define QLCNIC_CAP0_LRO_MSS (1 << 21)
603
604 /*
605 * Context state
606 */
607 #define QLCNIC_HOST_CTX_STATE_FREED 0
608 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
609
610 /*
611 * Rx context
612 */
613
614 struct qlcnic_hostrq_sds_ring {
615 __le64 host_phys_addr; /* Ring base addr */
616 __le32 ring_size; /* Ring entries */
617 __le16 msi_index;
618 __le16 rsvd; /* Padding */
619 } __packed;
620
621 struct qlcnic_hostrq_rds_ring {
622 __le64 host_phys_addr; /* Ring base addr */
623 __le64 buff_size; /* Packet buffer size */
624 __le32 ring_size; /* Ring entries */
625 __le32 ring_kind; /* Class of ring */
626 } __packed;
627
628 struct qlcnic_hostrq_rx_ctx {
629 __le64 host_rsp_dma_addr; /* Response dma'd here */
630 __le32 capabilities[4]; /* Flag bit vector */
631 __le32 host_int_crb_mode; /* Interrupt crb usage */
632 __le32 host_rds_crb_mode; /* RDS crb usage */
633 /* These ring offsets are relative to data[0] below */
634 __le32 rds_ring_offset; /* Offset to RDS config */
635 __le32 sds_ring_offset; /* Offset to SDS config */
636 __le16 num_rds_rings; /* Count of RDS rings */
637 __le16 num_sds_rings; /* Count of SDS rings */
638 __le16 valid_field_offset;
639 u8 txrx_sds_binding;
640 u8 msix_handler;
641 u8 reserved[128]; /* reserve space for future expansion*/
642 /* MUST BE 64-bit aligned.
643 The following is packed:
644 - N hostrq_rds_rings
645 - N hostrq_sds_rings */
646 char data[0];
647 } __packed;
648
649 struct qlcnic_cardrsp_rds_ring{
650 __le32 host_producer_crb; /* Crb to use */
651 __le32 rsvd1; /* Padding */
652 } __packed;
653
654 struct qlcnic_cardrsp_sds_ring {
655 __le32 host_consumer_crb; /* Crb to use */
656 __le32 interrupt_crb; /* Crb to use */
657 } __packed;
658
659 struct qlcnic_cardrsp_rx_ctx {
660 /* These ring offsets are relative to data[0] below */
661 __le32 rds_ring_offset; /* Offset to RDS config */
662 __le32 sds_ring_offset; /* Offset to SDS config */
663 __le32 host_ctx_state; /* Starting State */
664 __le32 num_fn_per_port; /* How many PCI fn share the port */
665 __le16 num_rds_rings; /* Count of RDS rings */
666 __le16 num_sds_rings; /* Count of SDS rings */
667 __le16 context_id; /* Handle for context */
668 u8 phys_port; /* Physical id of port */
669 u8 virt_port; /* Virtual/Logical id of port */
670 u8 reserved[128]; /* save space for future expansion */
671 /* MUST BE 64-bit aligned.
672 The following is packed:
673 - N cardrsp_rds_rings
674 - N cardrs_sds_rings */
675 char data[0];
676 } __packed;
677
678 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
679 (sizeof(HOSTRQ_RX) + \
680 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
681 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
682
683 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
684 (sizeof(CARDRSP_RX) + \
685 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
686 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
687
688 /*
689 * Tx context
690 */
691
692 struct qlcnic_hostrq_cds_ring {
693 __le64 host_phys_addr; /* Ring base addr */
694 __le32 ring_size; /* Ring entries */
695 __le32 rsvd; /* Padding */
696 } __packed;
697
698 struct qlcnic_hostrq_tx_ctx {
699 __le64 host_rsp_dma_addr; /* Response dma'd here */
700 __le64 cmd_cons_dma_addr; /* */
701 __le64 dummy_dma_addr; /* */
702 __le32 capabilities[4]; /* Flag bit vector */
703 __le32 host_int_crb_mode; /* Interrupt crb usage */
704 __le32 rsvd1; /* Padding */
705 __le16 rsvd2; /* Padding */
706 __le16 interrupt_ctl;
707 __le16 msi_index;
708 __le16 rsvd3; /* Padding */
709 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
710 u8 reserved[128]; /* future expansion */
711 } __packed;
712
713 struct qlcnic_cardrsp_cds_ring {
714 __le32 host_producer_crb; /* Crb to use */
715 __le32 interrupt_crb; /* Crb to use */
716 } __packed;
717
718 struct qlcnic_cardrsp_tx_ctx {
719 __le32 host_ctx_state; /* Starting state */
720 __le16 context_id; /* Handle for context */
721 u8 phys_port; /* Physical id of port */
722 u8 virt_port; /* Virtual/Logical id of port */
723 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
724 u8 reserved[128]; /* future expansion */
725 } __packed;
726
727 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
728 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
729
730 /* CRB */
731
732 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
733 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
734 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
735 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
736
737 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
738 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
739 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
740 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
741 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
742
743
744 /* MAC */
745
746 #define MC_COUNT_P3P 38
747
748 #define QLCNIC_MAC_NOOP 0
749 #define QLCNIC_MAC_ADD 1
750 #define QLCNIC_MAC_DEL 2
751 #define QLCNIC_MAC_VLAN_ADD 3
752 #define QLCNIC_MAC_VLAN_DEL 4
753
754 struct qlcnic_mac_list_s {
755 struct list_head list;
756 uint8_t mac_addr[ETH_ALEN+2];
757 };
758
759 /* MAC Learn */
760 #define NO_MAC_LEARN 0
761 #define DRV_MAC_LEARN 1
762 #define FDB_MAC_LEARN 2
763
764 #define QLCNIC_HOST_REQUEST 0x13
765 #define QLCNIC_REQUEST 0x14
766
767 #define QLCNIC_MAC_EVENT 0x1
768
769 #define QLCNIC_IP_UP 2
770 #define QLCNIC_IP_DOWN 3
771
772 #define QLCNIC_ILB_MODE 0x1
773 #define QLCNIC_ELB_MODE 0x2
774
775 #define QLCNIC_LINKEVENT 0x1
776 #define QLCNIC_LB_RESPONSE 0x2
777 #define QLCNIC_IS_LB_CONFIGURED(VAL) \
778 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
779
780 /*
781 * Driver --> Firmware
782 */
783 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
784 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
785 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
786 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
787 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
788 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
789
790 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
791 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
792 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
793 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13
794
795 /*
796 * Firmware --> Driver
797 */
798
799 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f
800 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D
801
802 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
803 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
804 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
805
806 #define QLCNIC_LRO_REQUEST_CLEANUP 4
807
808 /* Capabilites received */
809 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
810 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
811 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
812 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
813 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27
814 #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31
815
816 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2
817 #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3
818 #define QLCNIC_FW_CAPABILITY_2_OCBB BIT_5
819
820 /* module types */
821 #define LINKEVENT_MODULE_NOT_PRESENT 1
822 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
823 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
824 #define LINKEVENT_MODULE_OPTICAL_LRM 4
825 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
826 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
827 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
828 #define LINKEVENT_MODULE_TWINAX 8
829
830 #define LINKSPEED_10GBPS 10000
831 #define LINKSPEED_1GBPS 1000
832 #define LINKSPEED_100MBPS 100
833 #define LINKSPEED_10MBPS 10
834
835 #define LINKSPEED_ENCODED_10MBPS 0
836 #define LINKSPEED_ENCODED_100MBPS 1
837 #define LINKSPEED_ENCODED_1GBPS 2
838
839 #define LINKEVENT_AUTONEG_DISABLED 0
840 #define LINKEVENT_AUTONEG_ENABLED 1
841
842 #define LINKEVENT_HALF_DUPLEX 0
843 #define LINKEVENT_FULL_DUPLEX 1
844
845 #define LINKEVENT_LINKSPEED_MBPS 0
846 #define LINKEVENT_LINKSPEED_ENCODED 1
847
848 /* firmware response header:
849 * 63:58 - message type
850 * 57:56 - owner
851 * 55:53 - desc count
852 * 52:48 - reserved
853 * 47:40 - completion id
854 * 39:32 - opcode
855 * 31:16 - error code
856 * 15:00 - reserved
857 */
858 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
859 ((msg_hdr >> 32) & 0xFF)
860
861 struct qlcnic_fw_msg {
862 union {
863 struct {
864 u64 hdr;
865 u64 body[7];
866 };
867 u64 words[8];
868 };
869 };
870
871 struct qlcnic_nic_req {
872 __le64 qhdr;
873 __le64 req_hdr;
874 __le64 words[6];
875 } __packed;
876
877 struct qlcnic_mac_req {
878 u8 op;
879 u8 tag;
880 u8 mac_addr[6];
881 };
882
883 struct qlcnic_vlan_req {
884 __le16 vlan_id;
885 __le16 rsvd[3];
886 } __packed;
887
888 struct qlcnic_ipaddr {
889 __be32 ipv4;
890 __be32 ipv6[4];
891 };
892
893 #define QLCNIC_MSI_ENABLED 0x02
894 #define QLCNIC_MSIX_ENABLED 0x04
895 #define QLCNIC_LRO_ENABLED 0x01
896 #define QLCNIC_LRO_DISABLED 0x00
897 #define QLCNIC_BRIDGE_ENABLED 0X10
898 #define QLCNIC_DIAG_ENABLED 0x20
899 #define QLCNIC_ESWITCH_ENABLED 0x40
900 #define QLCNIC_ADAPTER_INITIALIZED 0x80
901 #define QLCNIC_TAGGING_ENABLED 0x100
902 #define QLCNIC_MACSPOOF 0x200
903 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
904 #define QLCNIC_PROMISC_DISABLED 0x800
905 #define QLCNIC_NEED_FLR 0x1000
906 #define QLCNIC_FW_RESET_OWNER 0x2000
907 #define QLCNIC_FW_HANG 0x4000
908 #define QLCNIC_FW_LRO_MSS_CAP 0x8000
909 #define QLCNIC_TX_INTR_SHARED 0x10000
910 #define QLCNIC_APP_CHANGED_FLAGS 0x20000
911 #define QLCNIC_IS_MSI_FAMILY(adapter) \
912 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
913 #define QLCNIC_IS_TSO_CAPABLE(adapter) \
914 ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
915
916 #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4
917 #define QLCNIC_MSIX_TBL_SPACE 8192
918 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
919 #define QLCNIC_MSIX_TBL_PGSIZE 4096
920
921 #define QLCNIC_NETDEV_WEIGHT 128
922 #define QLCNIC_ADAPTER_UP_MAGIC 777
923
924 #define __QLCNIC_FW_ATTACHED 0
925 #define __QLCNIC_DEV_UP 1
926 #define __QLCNIC_RESETTING 2
927 #define __QLCNIC_START_FW 4
928 #define __QLCNIC_AER 5
929 #define __QLCNIC_DIAG_RES_ALLOC 6
930 #define __QLCNIC_LED_ENABLE 7
931 #define __QLCNIC_ELB_INPROGRESS 8
932 #define __QLCNIC_SRIOV_ENABLE 10
933 #define __QLCNIC_SRIOV_CAPABLE 11
934 #define __QLCNIC_MBX_POLL_ENABLE 12
935
936 #define QLCNIC_INTERRUPT_TEST 1
937 #define QLCNIC_LOOPBACK_TEST 2
938 #define QLCNIC_LED_TEST 3
939
940 #define QLCNIC_FILTER_AGE 80
941 #define QLCNIC_READD_AGE 20
942 #define QLCNIC_LB_MAX_FILTERS 64
943 #define QLCNIC_LB_BUCKET_SIZE 32
944
945 /* QLCNIC Driver Error Code */
946 #define QLCNIC_FW_NOT_RESPOND 51
947 #define QLCNIC_TEST_IN_PROGRESS 52
948 #define QLCNIC_UNDEFINED_ERROR 53
949 #define QLCNIC_LB_CABLE_NOT_CONN 54
950 #define QLCNIC_ILB_MAX_RCV_LOOP 10
951
952 struct qlcnic_filter {
953 struct hlist_node fnode;
954 u8 faddr[ETH_ALEN];
955 u16 vlan_id;
956 unsigned long ftime;
957 };
958
959 struct qlcnic_filter_hash {
960 struct hlist_head *fhead;
961 u8 fnum;
962 u16 fmax;
963 u16 fbucket_size;
964 };
965
966 struct qlcnic_adapter {
967 struct qlcnic_hardware_context *ahw;
968 struct qlcnic_recv_context *recv_ctx;
969 struct qlcnic_host_tx_ring *tx_ring;
970 struct net_device *netdev;
971 struct pci_dev *pdev;
972
973 unsigned long state;
974 u32 flags;
975
976 int max_drv_tx_rings;
977 u16 num_txd;
978 u16 num_rxd;
979 u16 num_jumbo_rxd;
980 u16 max_rxd;
981 u16 max_jumbo_rxd;
982
983 u8 max_rds_rings;
984 u8 max_sds_rings;
985 u8 rx_csum;
986 u8 portnum;
987
988 u8 fw_wait_cnt;
989 u8 fw_fail_cnt;
990 u8 tx_timeo_cnt;
991 u8 need_fw_reset;
992 u8 reset_ctx_cnt;
993
994 u16 is_up;
995 u16 rx_pvid;
996 u16 tx_pvid;
997
998 u32 irq;
999 u32 heartbeat;
1000
1001 u8 dev_state;
1002 u8 reset_ack_timeo;
1003 u8 dev_init_timeo;
1004
1005 u8 mac_addr[ETH_ALEN];
1006
1007 u64 dev_rst_time;
1008 bool drv_mac_learn;
1009 bool fdb_mac_learn;
1010 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
1011 u8 flash_mfg_id;
1012 struct qlcnic_npar_info *npars;
1013 struct qlcnic_eswitch *eswitch;
1014 struct qlcnic_nic_template *nic_ops;
1015
1016 struct qlcnic_adapter_stats stats;
1017 struct list_head mac_list;
1018
1019 void __iomem *tgt_mask_reg;
1020 void __iomem *tgt_status_reg;
1021 void __iomem *crb_int_state_reg;
1022 void __iomem *isr_int_vec;
1023
1024 struct msix_entry *msix_entries;
1025 struct workqueue_struct *qlcnic_wq;
1026 struct delayed_work fw_work;
1027 struct delayed_work idc_aen_work;
1028 struct delayed_work mbx_poll_work;
1029
1030 struct qlcnic_filter_hash fhash;
1031 struct qlcnic_filter_hash rx_fhash;
1032 struct list_head vf_mc_list;
1033
1034 spinlock_t tx_clean_lock;
1035 spinlock_t mac_learn_lock;
1036 /* spinlock for catching rcv filters for eswitch traffic */
1037 spinlock_t rx_mac_learn_lock;
1038 u32 file_prd_off; /*File fw product offset*/
1039 u32 fw_version;
1040 u32 offload_flags;
1041 const struct firmware *fw;
1042 };
1043
1044 struct qlcnic_info_le {
1045 __le16 pci_func;
1046 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1047 __le16 phys_port;
1048 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1049
1050 __le32 capabilities;
1051 u8 max_mac_filters;
1052 u8 reserved1;
1053 __le16 max_mtu;
1054
1055 __le16 max_tx_ques;
1056 __le16 max_rx_ques;
1057 __le16 min_tx_bw;
1058 __le16 max_tx_bw;
1059 __le32 op_type;
1060 __le16 max_bw_reg_offset;
1061 __le16 max_linkspeed_reg_offset;
1062 __le32 capability1;
1063 __le32 capability2;
1064 __le32 capability3;
1065 __le16 max_tx_mac_filters;
1066 __le16 max_rx_mcast_mac_filters;
1067 __le16 max_rx_ucast_mac_filters;
1068 __le16 max_rx_ip_addr;
1069 __le16 max_rx_lro_flow;
1070 __le16 max_rx_status_rings;
1071 __le16 max_rx_buf_rings;
1072 __le16 max_tx_vlan_keys;
1073 u8 total_pf;
1074 u8 total_rss_engines;
1075 __le16 max_vports;
1076 __le16 linkstate_reg_offset;
1077 __le16 bit_offsets;
1078 __le16 max_local_ipv6_addrs;
1079 __le16 max_remote_ipv6_addrs;
1080 u8 reserved2[56];
1081 } __packed;
1082
1083 struct qlcnic_info {
1084 u16 pci_func;
1085 u16 op_mode;
1086 u16 phys_port;
1087 u16 switch_mode;
1088 u32 capabilities;
1089 u8 max_mac_filters;
1090 u16 max_mtu;
1091 u16 max_tx_ques;
1092 u16 max_rx_ques;
1093 u16 min_tx_bw;
1094 u16 max_tx_bw;
1095 u32 op_type;
1096 u16 max_bw_reg_offset;
1097 u16 max_linkspeed_reg_offset;
1098 u32 capability1;
1099 u32 capability2;
1100 u32 capability3;
1101 u16 max_tx_mac_filters;
1102 u16 max_rx_mcast_mac_filters;
1103 u16 max_rx_ucast_mac_filters;
1104 u16 max_rx_ip_addr;
1105 u16 max_rx_lro_flow;
1106 u16 max_rx_status_rings;
1107 u16 max_rx_buf_rings;
1108 u16 max_tx_vlan_keys;
1109 u8 total_pf;
1110 u8 total_rss_engines;
1111 u16 max_vports;
1112 u16 linkstate_reg_offset;
1113 u16 bit_offsets;
1114 u16 max_local_ipv6_addrs;
1115 u16 max_remote_ipv6_addrs;
1116 };
1117
1118 struct qlcnic_pci_info_le {
1119 __le16 id; /* pci function id */
1120 __le16 active; /* 1 = Enabled */
1121 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1122 __le16 default_port; /* default port number */
1123
1124 __le16 tx_min_bw; /* Multiple of 100mbpc */
1125 __le16 tx_max_bw;
1126 __le16 reserved1[2];
1127
1128 u8 mac[ETH_ALEN];
1129 __le16 func_count;
1130 u8 reserved2[104];
1131
1132 } __packed;
1133
1134 struct qlcnic_pci_info {
1135 u16 id;
1136 u16 active;
1137 u16 type;
1138 u16 default_port;
1139 u16 tx_min_bw;
1140 u16 tx_max_bw;
1141 u8 mac[ETH_ALEN];
1142 u16 func_count;
1143 };
1144
1145 struct qlcnic_npar_info {
1146 u16 pvid;
1147 u16 min_bw;
1148 u16 max_bw;
1149 u8 phy_port;
1150 u8 type;
1151 u8 active;
1152 u8 enable_pm;
1153 u8 dest_npar;
1154 u8 discard_tagged;
1155 u8 mac_override;
1156 u8 mac_anti_spoof;
1157 u8 promisc_mode;
1158 u8 offload_flags;
1159 u8 pci_func;
1160 };
1161
1162 struct qlcnic_eswitch {
1163 u8 port;
1164 u8 active_vports;
1165 u8 active_vlans;
1166 u8 active_ucast_filters;
1167 u8 max_ucast_filters;
1168 u8 max_active_vlans;
1169
1170 u32 flags;
1171 #define QLCNIC_SWITCH_ENABLE BIT_1
1172 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1173 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1174 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1175 };
1176
1177
1178 /* Return codes for Error handling */
1179 #define QL_STATUS_INVALID_PARAM -1
1180
1181 #define MAX_BW 100 /* % of link speed */
1182 #define MAX_VLAN_ID 4095
1183 #define MIN_VLAN_ID 2
1184 #define DEFAULT_MAC_LEARN 1
1185
1186 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1187 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1188
1189 struct qlcnic_pci_func_cfg {
1190 u16 func_type;
1191 u16 min_bw;
1192 u16 max_bw;
1193 u16 port_num;
1194 u8 pci_func;
1195 u8 func_state;
1196 u8 def_mac_addr[6];
1197 };
1198
1199 struct qlcnic_npar_func_cfg {
1200 u32 fw_capab;
1201 u16 port_num;
1202 u16 min_bw;
1203 u16 max_bw;
1204 u16 max_tx_queues;
1205 u16 max_rx_queues;
1206 u8 pci_func;
1207 u8 op_mode;
1208 };
1209
1210 struct qlcnic_pm_func_cfg {
1211 u8 pci_func;
1212 u8 action;
1213 u8 dest_npar;
1214 u8 reserved[5];
1215 };
1216
1217 struct qlcnic_esw_func_cfg {
1218 u16 vlan_id;
1219 u8 op_mode;
1220 u8 op_type;
1221 u8 pci_func;
1222 u8 host_vlan_tag;
1223 u8 promisc_mode;
1224 u8 discard_tagged;
1225 u8 mac_override;
1226 u8 mac_anti_spoof;
1227 u8 offload_flags;
1228 u8 reserved[5];
1229 };
1230
1231 #define QLCNIC_STATS_VERSION 1
1232 #define QLCNIC_STATS_PORT 1
1233 #define QLCNIC_STATS_ESWITCH 2
1234 #define QLCNIC_QUERY_RX_COUNTER 0
1235 #define QLCNIC_QUERY_TX_COUNTER 1
1236 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL
1237 #define QLCNIC_FILL_STATS(VAL1) \
1238 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1)
1239 #define QLCNIC_MAC_STATS 1
1240 #define QLCNIC_ESW_STATS 2
1241
1242 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1243 do { \
1244 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \
1245 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1246 (VAL1) = (VAL2); \
1247 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \
1248 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1249 (VAL1) += (VAL2); \
1250 } while (0)
1251
1252 struct qlcnic_mac_statistics_le {
1253 __le64 mac_tx_frames;
1254 __le64 mac_tx_bytes;
1255 __le64 mac_tx_mcast_pkts;
1256 __le64 mac_tx_bcast_pkts;
1257 __le64 mac_tx_pause_cnt;
1258 __le64 mac_tx_ctrl_pkt;
1259 __le64 mac_tx_lt_64b_pkts;
1260 __le64 mac_tx_lt_127b_pkts;
1261 __le64 mac_tx_lt_255b_pkts;
1262 __le64 mac_tx_lt_511b_pkts;
1263 __le64 mac_tx_lt_1023b_pkts;
1264 __le64 mac_tx_lt_1518b_pkts;
1265 __le64 mac_tx_gt_1518b_pkts;
1266 __le64 rsvd1[3];
1267
1268 __le64 mac_rx_frames;
1269 __le64 mac_rx_bytes;
1270 __le64 mac_rx_mcast_pkts;
1271 __le64 mac_rx_bcast_pkts;
1272 __le64 mac_rx_pause_cnt;
1273 __le64 mac_rx_ctrl_pkt;
1274 __le64 mac_rx_lt_64b_pkts;
1275 __le64 mac_rx_lt_127b_pkts;
1276 __le64 mac_rx_lt_255b_pkts;
1277 __le64 mac_rx_lt_511b_pkts;
1278 __le64 mac_rx_lt_1023b_pkts;
1279 __le64 mac_rx_lt_1518b_pkts;
1280 __le64 mac_rx_gt_1518b_pkts;
1281 __le64 rsvd2[3];
1282
1283 __le64 mac_rx_length_error;
1284 __le64 mac_rx_length_small;
1285 __le64 mac_rx_length_large;
1286 __le64 mac_rx_jabber;
1287 __le64 mac_rx_dropped;
1288 __le64 mac_rx_crc_error;
1289 __le64 mac_align_error;
1290 } __packed;
1291
1292 struct qlcnic_mac_statistics {
1293 u64 mac_tx_frames;
1294 u64 mac_tx_bytes;
1295 u64 mac_tx_mcast_pkts;
1296 u64 mac_tx_bcast_pkts;
1297 u64 mac_tx_pause_cnt;
1298 u64 mac_tx_ctrl_pkt;
1299 u64 mac_tx_lt_64b_pkts;
1300 u64 mac_tx_lt_127b_pkts;
1301 u64 mac_tx_lt_255b_pkts;
1302 u64 mac_tx_lt_511b_pkts;
1303 u64 mac_tx_lt_1023b_pkts;
1304 u64 mac_tx_lt_1518b_pkts;
1305 u64 mac_tx_gt_1518b_pkts;
1306 u64 rsvd1[3];
1307 u64 mac_rx_frames;
1308 u64 mac_rx_bytes;
1309 u64 mac_rx_mcast_pkts;
1310 u64 mac_rx_bcast_pkts;
1311 u64 mac_rx_pause_cnt;
1312 u64 mac_rx_ctrl_pkt;
1313 u64 mac_rx_lt_64b_pkts;
1314 u64 mac_rx_lt_127b_pkts;
1315 u64 mac_rx_lt_255b_pkts;
1316 u64 mac_rx_lt_511b_pkts;
1317 u64 mac_rx_lt_1023b_pkts;
1318 u64 mac_rx_lt_1518b_pkts;
1319 u64 mac_rx_gt_1518b_pkts;
1320 u64 rsvd2[3];
1321 u64 mac_rx_length_error;
1322 u64 mac_rx_length_small;
1323 u64 mac_rx_length_large;
1324 u64 mac_rx_jabber;
1325 u64 mac_rx_dropped;
1326 u64 mac_rx_crc_error;
1327 u64 mac_align_error;
1328 };
1329
1330 struct qlcnic_esw_stats_le {
1331 __le16 context_id;
1332 __le16 version;
1333 __le16 size;
1334 __le16 unused;
1335 __le64 unicast_frames;
1336 __le64 multicast_frames;
1337 __le64 broadcast_frames;
1338 __le64 dropped_frames;
1339 __le64 errors;
1340 __le64 local_frames;
1341 __le64 numbytes;
1342 __le64 rsvd[3];
1343 } __packed;
1344
1345 struct __qlcnic_esw_statistics {
1346 u16 context_id;
1347 u16 version;
1348 u16 size;
1349 u16 unused;
1350 u64 unicast_frames;
1351 u64 multicast_frames;
1352 u64 broadcast_frames;
1353 u64 dropped_frames;
1354 u64 errors;
1355 u64 local_frames;
1356 u64 numbytes;
1357 u64 rsvd[3];
1358 };
1359
1360 struct qlcnic_esw_statistics {
1361 struct __qlcnic_esw_statistics rx;
1362 struct __qlcnic_esw_statistics tx;
1363 };
1364
1365 #define QLCNIC_DUMP_MASK_DEF 0x1f
1366 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1367 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed
1368 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed
1369 #define QLCNIC_FORCE_FW_RESET 0xdeaddead
1370 #define QLCNIC_SET_QUIESCENT 0xadd00010
1371 #define QLCNIC_RESET_QUIESCENT 0xadd00020
1372
1373 struct _cdrp_cmd {
1374 u32 num;
1375 u32 *arg;
1376 };
1377
1378 struct qlcnic_cmd_args {
1379 struct _cdrp_cmd req;
1380 struct _cdrp_cmd rsp;
1381 int op_type;
1382 };
1383
1384 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
1385 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);
1386 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1387 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1388 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1389 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1390
1391 #define ADDR_IN_RANGE(addr, low, high) \
1392 (((addr) < (high)) && ((addr) >= (low)))
1393
1394 #define QLCRD32(adapter, off) \
1395 (adapter->ahw->hw_ops->read_reg)(adapter, off)
1396
1397 #define QLCWR32(adapter, off, val) \
1398 adapter->ahw->hw_ops->write_reg(adapter, off, val)
1399
1400 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1401 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1402
1403 #define qlcnic_rom_lock(a) \
1404 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1405 #define qlcnic_rom_unlock(a) \
1406 qlcnic_pcie_sem_unlock((a), 2)
1407 #define qlcnic_phy_lock(a) \
1408 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1409 #define qlcnic_phy_unlock(a) \
1410 qlcnic_pcie_sem_unlock((a), 3)
1411 #define qlcnic_sw_lock(a) \
1412 qlcnic_pcie_sem_lock((a), 6, 0)
1413 #define qlcnic_sw_unlock(a) \
1414 qlcnic_pcie_sem_unlock((a), 6)
1415 #define crb_win_lock(a) \
1416 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1417 #define crb_win_unlock(a) \
1418 qlcnic_pcie_sem_unlock((a), 7)
1419
1420 #define __QLCNIC_MAX_LED_RATE 0xf
1421 #define __QLCNIC_MAX_LED_STATE 0x2
1422
1423 #define MAX_CTL_CHECK 1000
1424
1425 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1426 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1427 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1428 int qlcnic_dump_fw(struct qlcnic_adapter *);
1429
1430 /* Functions from qlcnic_init.c */
1431 void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int);
1432 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1433 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1434 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1435 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1436 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1437 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1438 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1439
1440 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp);
1441 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1442 u8 *bytes, size_t size);
1443 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1444 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1445
1446 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32);
1447
1448 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1449 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1450
1451 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1452 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1453
1454 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1455 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1456 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1457
1458 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1459 void qlcnic_watchdog_task(struct work_struct *work);
1460 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1461 struct qlcnic_host_rds_ring *rds_ring, u8 ring_id);
1462 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1463 void qlcnic_set_multi(struct net_device *netdev);
1464 void __qlcnic_set_multi(struct net_device *, u16);
1465 int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16);
1466 int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *);
1467 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter);
1468
1469 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1470 int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *);
1471 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1472 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1473 netdev_features_t features);
1474 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features);
1475 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1476 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1477 void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *);
1478
1479 /* Functions from qlcnic_ethtool.c */
1480 int qlcnic_check_loopback_buff(unsigned char *, u8 []);
1481 int qlcnic_do_lb_test(struct qlcnic_adapter *, u8);
1482 int qlcnic_loopback_test(struct net_device *, u8);
1483
1484 /* Functions from qlcnic_main.c */
1485 int qlcnic_reset_context(struct qlcnic_adapter *);
1486 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1487 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1488 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1489 int qlcnic_set_max_rss(struct qlcnic_adapter *, u8, size_t);
1490 int qlcnic_validate_max_rss(struct qlcnic_adapter *, __u32);
1491 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter);
1492 int qlcnic_enable_msix(struct qlcnic_adapter *, u32);
1493
1494 /* eSwitch management functions */
1495 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1496 struct qlcnic_esw_func_cfg *);
1497
1498 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1499 struct qlcnic_esw_func_cfg *);
1500 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1501 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1502 struct __qlcnic_esw_statistics *);
1503 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1504 struct __qlcnic_esw_statistics *);
1505 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1506 int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *);
1507
1508 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd);
1509
1510 int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int);
1511 void qlcnic_free_sds_rings(struct qlcnic_recv_context *);
1512 void qlcnic_advert_link_change(struct qlcnic_adapter *, int);
1513 void qlcnic_free_tx_rings(struct qlcnic_adapter *);
1514 int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *);
1515
1516 void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter);
1517 void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter);
1518 void qlcnic_create_diag_entries(struct qlcnic_adapter *adapter);
1519 void qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter);
1520 void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter);
1521 void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter);
1522 int qlcnic_82xx_get_settings(struct qlcnic_adapter *, struct ethtool_cmd *);
1523
1524 int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32);
1525 int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32);
1526 void qlcnic_set_vlan_config(struct qlcnic_adapter *,
1527 struct qlcnic_esw_func_cfg *);
1528 void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *,
1529 struct qlcnic_esw_func_cfg *);
1530
1531 void qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1532 int qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1533 void __qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1534 void qlcnic_detach(struct qlcnic_adapter *);
1535 void qlcnic_teardown_intr(struct qlcnic_adapter *);
1536 int qlcnic_attach(struct qlcnic_adapter *);
1537 int __qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1538 void qlcnic_restore_indev_addr(struct net_device *, unsigned long);
1539
1540 int qlcnic_check_temp(struct qlcnic_adapter *);
1541 int qlcnic_init_pci_info(struct qlcnic_adapter *);
1542 int qlcnic_set_default_offload_settings(struct qlcnic_adapter *);
1543 int qlcnic_reset_npar_config(struct qlcnic_adapter *);
1544 int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *);
1545 void qlcnic_add_lb_filter(struct qlcnic_adapter *, struct sk_buff *, int, u16);
1546 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter);
1547 int qlcnic_read_mac_addr(struct qlcnic_adapter *);
1548 int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int);
1549 void qlcnic_set_netdev_features(struct qlcnic_adapter *,
1550 struct qlcnic_esw_func_cfg *);
1551 void qlcnic_sriov_vf_schedule_multi(struct net_device *);
1552 void qlcnic_vf_add_mc_list(struct net_device *, u16);
1553
1554 /*
1555 * QLOGIC Board information
1556 */
1557
1558 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1559 struct qlcnic_board_info {
1560 unsigned short vendor;
1561 unsigned short device;
1562 unsigned short sub_vendor;
1563 unsigned short sub_device;
1564 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1565 };
1566
1567 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1568 {
1569 if (likely(tx_ring->producer < tx_ring->sw_consumer))
1570 return tx_ring->sw_consumer - tx_ring->producer;
1571 else
1572 return tx_ring->sw_consumer + tx_ring->num_desc -
1573 tx_ring->producer;
1574 }
1575
1576 struct qlcnic_nic_template {
1577 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1578 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1579 int (*start_firmware) (struct qlcnic_adapter *);
1580 int (*init_driver) (struct qlcnic_adapter *);
1581 void (*request_reset) (struct qlcnic_adapter *, u32);
1582 void (*cancel_idc_work) (struct qlcnic_adapter *);
1583 int (*napi_add)(struct qlcnic_adapter *, struct net_device *);
1584 void (*napi_del)(struct qlcnic_adapter *);
1585 void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int);
1586 irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *);
1587 };
1588
1589 /* Adapter hardware abstraction */
1590 struct qlcnic_hardware_ops {
1591 void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1592 void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1593 int (*read_reg) (struct qlcnic_adapter *, ulong);
1594 int (*write_reg) (struct qlcnic_adapter *, ulong, u32);
1595 void (*get_ocm_win) (struct qlcnic_hardware_context *);
1596 int (*get_mac_address) (struct qlcnic_adapter *, u8 *);
1597 int (*setup_intr) (struct qlcnic_adapter *, u8);
1598 int (*alloc_mbx_args)(struct qlcnic_cmd_args *,
1599 struct qlcnic_adapter *, u32);
1600 int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1601 void (*get_func_no) (struct qlcnic_adapter *);
1602 int (*api_lock) (struct qlcnic_adapter *);
1603 void (*api_unlock) (struct qlcnic_adapter *);
1604 void (*add_sysfs) (struct qlcnic_adapter *);
1605 void (*remove_sysfs) (struct qlcnic_adapter *);
1606 void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *);
1607 int (*create_rx_ctx) (struct qlcnic_adapter *);
1608 int (*create_tx_ctx) (struct qlcnic_adapter *,
1609 struct qlcnic_host_tx_ring *, int);
1610 void (*del_rx_ctx) (struct qlcnic_adapter *);
1611 void (*del_tx_ctx) (struct qlcnic_adapter *,
1612 struct qlcnic_host_tx_ring *);
1613 int (*setup_link_event) (struct qlcnic_adapter *, int);
1614 int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8);
1615 int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *);
1616 int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *);
1617 int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8);
1618 void (*napi_enable) (struct qlcnic_adapter *);
1619 void (*napi_disable) (struct qlcnic_adapter *);
1620 void (*config_intr_coal) (struct qlcnic_adapter *);
1621 int (*config_rss) (struct qlcnic_adapter *, int);
1622 int (*config_hw_lro) (struct qlcnic_adapter *, int);
1623 int (*config_loopback) (struct qlcnic_adapter *, u8);
1624 int (*clear_loopback) (struct qlcnic_adapter *, u8);
1625 int (*config_promisc_mode) (struct qlcnic_adapter *, u32);
1626 void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, u16);
1627 int (*get_board_info) (struct qlcnic_adapter *);
1628 void (*free_mac_list) (struct qlcnic_adapter *);
1629 };
1630
1631 extern struct qlcnic_nic_template qlcnic_vf_ops;
1632
1633 static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter)
1634 {
1635 return adapter->nic_ops->start_firmware(adapter);
1636 }
1637
1638 static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf,
1639 loff_t offset, size_t size)
1640 {
1641 adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size);
1642 }
1643
1644 static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf,
1645 loff_t offset, size_t size)
1646 {
1647 adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size);
1648 }
1649
1650 static inline int qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter,
1651 ulong off)
1652 {
1653 return adapter->ahw->hw_ops->read_reg(adapter, off);
1654 }
1655
1656 static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter,
1657 ulong off, u32 data)
1658 {
1659 return adapter->ahw->hw_ops->write_reg(adapter, off, data);
1660 }
1661
1662 static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter,
1663 u8 *mac)
1664 {
1665 return adapter->ahw->hw_ops->get_mac_address(adapter, mac);
1666 }
1667
1668 static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr)
1669 {
1670 return adapter->ahw->hw_ops->setup_intr(adapter, num_intr);
1671 }
1672
1673 static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
1674 struct qlcnic_adapter *adapter, u32 arg)
1675 {
1676 return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg);
1677 }
1678
1679 static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1680 struct qlcnic_cmd_args *cmd)
1681 {
1682 if (adapter->ahw->hw_ops->mbx_cmd)
1683 return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd);
1684
1685 return -EIO;
1686 }
1687
1688 static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter)
1689 {
1690 adapter->ahw->hw_ops->get_func_no(adapter);
1691 }
1692
1693 static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter)
1694 {
1695 return adapter->ahw->hw_ops->api_lock(adapter);
1696 }
1697
1698 static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter)
1699 {
1700 adapter->ahw->hw_ops->api_unlock(adapter);
1701 }
1702
1703 static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter)
1704 {
1705 if (adapter->ahw->hw_ops->add_sysfs)
1706 adapter->ahw->hw_ops->add_sysfs(adapter);
1707 }
1708
1709 static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter)
1710 {
1711 if (adapter->ahw->hw_ops->remove_sysfs)
1712 adapter->ahw->hw_ops->remove_sysfs(adapter);
1713 }
1714
1715 static inline void
1716 qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring)
1717 {
1718 sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring);
1719 }
1720
1721 static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
1722 {
1723 return adapter->ahw->hw_ops->create_rx_ctx(adapter);
1724 }
1725
1726 static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
1727 struct qlcnic_host_tx_ring *ptr,
1728 int ring)
1729 {
1730 return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring);
1731 }
1732
1733 static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
1734 {
1735 return adapter->ahw->hw_ops->del_rx_ctx(adapter);
1736 }
1737
1738 static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
1739 struct qlcnic_host_tx_ring *ptr)
1740 {
1741 return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr);
1742 }
1743
1744 static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter,
1745 int enable)
1746 {
1747 return adapter->ahw->hw_ops->setup_link_event(adapter, enable);
1748 }
1749
1750 static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter,
1751 struct qlcnic_info *info, u8 id)
1752 {
1753 return adapter->ahw->hw_ops->get_nic_info(adapter, info, id);
1754 }
1755
1756 static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter,
1757 struct qlcnic_pci_info *info)
1758 {
1759 return adapter->ahw->hw_ops->get_pci_info(adapter, info);
1760 }
1761
1762 static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter,
1763 struct qlcnic_info *info)
1764 {
1765 return adapter->ahw->hw_ops->set_nic_info(adapter, info);
1766 }
1767
1768 static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter,
1769 u8 *addr, u16 id, u8 cmd)
1770 {
1771 return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd);
1772 }
1773
1774 static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter,
1775 struct net_device *netdev)
1776 {
1777 return adapter->nic_ops->napi_add(adapter, netdev);
1778 }
1779
1780 static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter)
1781 {
1782 adapter->nic_ops->napi_del(adapter);
1783 }
1784
1785 static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter)
1786 {
1787 adapter->ahw->hw_ops->napi_enable(adapter);
1788 }
1789
1790 static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter)
1791 {
1792 adapter->ahw->hw_ops->napi_disable(adapter);
1793 }
1794
1795 static inline void qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
1796 {
1797 adapter->ahw->hw_ops->config_intr_coal(adapter);
1798 }
1799
1800 static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
1801 {
1802 return adapter->ahw->hw_ops->config_rss(adapter, enable);
1803 }
1804
1805 static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter,
1806 int enable)
1807 {
1808 return adapter->ahw->hw_ops->config_hw_lro(adapter, enable);
1809 }
1810
1811 static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1812 {
1813 return adapter->ahw->hw_ops->config_loopback(adapter, mode);
1814 }
1815
1816 static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1817 {
1818 return adapter->ahw->hw_ops->clear_loopback(adapter, mode);
1819 }
1820
1821 static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter,
1822 u32 mode)
1823 {
1824 return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode);
1825 }
1826
1827 static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter,
1828 u64 *addr, u16 id)
1829 {
1830 adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id);
1831 }
1832
1833 static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1834 {
1835 return adapter->ahw->hw_ops->get_board_info(adapter);
1836 }
1837
1838 static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
1839 {
1840 return adapter->ahw->hw_ops->free_mac_list(adapter);
1841 }
1842
1843 static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter,
1844 u32 key)
1845 {
1846 if (adapter->nic_ops->request_reset)
1847 adapter->nic_ops->request_reset(adapter, key);
1848 }
1849
1850 static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter)
1851 {
1852 if (adapter->nic_ops->cancel_idc_work)
1853 adapter->nic_ops->cancel_idc_work(adapter);
1854 }
1855
1856 static inline irqreturn_t
1857 qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter)
1858 {
1859 return adapter->nic_ops->clear_legacy_intr(adapter);
1860 }
1861
1862 static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state,
1863 u32 rate)
1864 {
1865 return adapter->nic_ops->config_led(adapter, state, rate);
1866 }
1867
1868 static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter,
1869 __be32 ip, int cmd)
1870 {
1871 adapter->nic_ops->config_ipaddr(adapter, ip, cmd);
1872 }
1873
1874 static inline void qlcnic_disable_int(struct qlcnic_host_sds_ring *sds_ring)
1875 {
1876 writel(0, sds_ring->crb_intr_mask);
1877 }
1878
1879 static inline void qlcnic_enable_int(struct qlcnic_host_sds_ring *sds_ring)
1880 {
1881 struct qlcnic_adapter *adapter = sds_ring->adapter;
1882
1883 writel(0x1, sds_ring->crb_intr_mask);
1884
1885 if (!QLCNIC_IS_MSI_FAMILY(adapter))
1886 writel(0xfbff, adapter->tgt_mask_reg);
1887 }
1888
1889 extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops;
1890 extern const struct ethtool_ops qlcnic_ethtool_ops;
1891 extern const struct ethtool_ops qlcnic_ethtool_failed_ops;
1892
1893 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1894 if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \
1895 printk(KERN_INFO "%s: %s: " _fmt, \
1896 dev_name(&adapter->pdev->dev), \
1897 __func__, ##_args); \
1898 } while (0)
1899
1900 #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030
1901 #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430
1902 #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020
1903
1904 static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter)
1905 {
1906 unsigned short device = adapter->pdev->device;
1907 return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false;
1908 }
1909
1910 static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter)
1911 {
1912 unsigned short device = adapter->pdev->device;
1913 bool status;
1914
1915 status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) ||
1916 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X)) ? true : false;
1917
1918 return status;
1919 }
1920
1921 static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter)
1922 {
1923 return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false;
1924 }
1925
1926 static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter)
1927 {
1928 unsigned short device = adapter->pdev->device;
1929
1930 return (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ? true : false;
1931 }
1932 #endif /* __QLCNIC_H_ */
kernel source for telekom puls (alcatel/mediatek)