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mlxsw: Make system port to local port mapping explicit
[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / net / ethernet / mellanox / mlxsw / switchx2.c
1 /*
2 * drivers/net/ethernet/mellanox/mlxsw/switchx2.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/netdevice.h>
41 #include <linux/etherdevice.h>
42 #include <linux/slab.h>
43 #include <linux/device.h>
44 #include <linux/skbuff.h>
45 #include <linux/if_vlan.h>
46 #include <net/switchdev.h>
47 #include <generated/utsrelease.h>
48
49 #include "core.h"
50 #include "reg.h"
51 #include "port.h"
52 #include "trap.h"
53 #include "txheader.h"
54
55 static const char mlxsw_sx_driver_name[] = "mlxsw_switchx2";
56 static const char mlxsw_sx_driver_version[] = "1.0";
57
58 struct mlxsw_sx_port;
59
60 #define MLXSW_SW_HW_ID_LEN 6
61
62 struct mlxsw_sx {
63 struct mlxsw_sx_port **ports;
64 struct mlxsw_core *core;
65 const struct mlxsw_bus_info *bus_info;
66 u8 hw_id[MLXSW_SW_HW_ID_LEN];
67 };
68
69 struct mlxsw_sx_port_pcpu_stats {
70 u64 rx_packets;
71 u64 rx_bytes;
72 u64 tx_packets;
73 u64 tx_bytes;
74 struct u64_stats_sync syncp;
75 u32 tx_dropped;
76 };
77
78 struct mlxsw_sx_port {
79 struct net_device *dev;
80 struct mlxsw_sx_port_pcpu_stats __percpu *pcpu_stats;
81 struct mlxsw_sx *mlxsw_sx;
82 u8 local_port;
83 };
84
85 /* tx_hdr_version
86 * Tx header version.
87 * Must be set to 0.
88 */
89 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
90
91 /* tx_hdr_ctl
92 * Packet control type.
93 * 0 - Ethernet control (e.g. EMADs, LACP)
94 * 1 - Ethernet data
95 */
96 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
97
98 /* tx_hdr_proto
99 * Packet protocol type. Must be set to 1 (Ethernet).
100 */
101 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
102
103 /* tx_hdr_etclass
104 * Egress TClass to be used on the egress device on the egress port.
105 * The MSB is specified in the 'ctclass3' field.
106 * Range is 0-15, where 15 is the highest priority.
107 */
108 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
109
110 /* tx_hdr_swid
111 * Switch partition ID.
112 */
113 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
114
115 /* tx_hdr_port_mid
116 * Destination local port for unicast packets.
117 * Destination multicast ID for multicast packets.
118 *
119 * Control packets are directed to a specific egress port, while data
120 * packets are transmitted through the CPU port (0) into the switch partition,
121 * where forwarding rules are applied.
122 */
123 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
124
125 /* tx_hdr_ctclass3
126 * See field 'etclass'.
127 */
128 MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
129
130 /* tx_hdr_rdq
131 * RDQ for control packets sent to remote CPU.
132 * Must be set to 0x1F for EMADs, otherwise 0.
133 */
134 MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
135
136 /* tx_hdr_cpu_sig
137 * Signature control for packets going to CPU. Must be set to 0.
138 */
139 MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
140
141 /* tx_hdr_sig
142 * Stacking protocl signature. Must be set to 0xE0E0.
143 */
144 MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
145
146 /* tx_hdr_stclass
147 * Stacking TClass.
148 */
149 MLXSW_ITEM32(tx, hdr, stclass, 0x0C, 13, 3);
150
151 /* tx_hdr_emad
152 * EMAD bit. Must be set for EMADs.
153 */
154 MLXSW_ITEM32(tx, hdr, emad, 0x0C, 5, 1);
155
156 /* tx_hdr_type
157 * 0 - Data packets
158 * 6 - Control packets
159 */
160 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
161
162 static void mlxsw_sx_txhdr_construct(struct sk_buff *skb,
163 const struct mlxsw_tx_info *tx_info)
164 {
165 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
166 bool is_emad = tx_info->is_emad;
167
168 memset(txhdr, 0, MLXSW_TXHDR_LEN);
169
170 /* We currently set default values for the egress tclass (QoS). */
171 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_0);
172 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
173 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
174 mlxsw_tx_hdr_etclass_set(txhdr, is_emad ? MLXSW_TXHDR_ETCLASS_6 :
175 MLXSW_TXHDR_ETCLASS_5);
176 mlxsw_tx_hdr_swid_set(txhdr, 0);
177 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
178 mlxsw_tx_hdr_ctclass3_set(txhdr, MLXSW_TXHDR_CTCLASS3);
179 mlxsw_tx_hdr_rdq_set(txhdr, is_emad ? MLXSW_TXHDR_RDQ_EMAD :
180 MLXSW_TXHDR_RDQ_OTHER);
181 mlxsw_tx_hdr_cpu_sig_set(txhdr, MLXSW_TXHDR_CPU_SIG);
182 mlxsw_tx_hdr_sig_set(txhdr, MLXSW_TXHDR_SIG);
183 mlxsw_tx_hdr_stclass_set(txhdr, MLXSW_TXHDR_STCLASS_NONE);
184 mlxsw_tx_hdr_emad_set(txhdr, is_emad ? MLXSW_TXHDR_EMAD :
185 MLXSW_TXHDR_NOT_EMAD);
186 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
187 }
188
189 static int mlxsw_sx_port_admin_status_set(struct mlxsw_sx_port *mlxsw_sx_port,
190 bool is_up)
191 {
192 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
193 char paos_pl[MLXSW_REG_PAOS_LEN];
194
195 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port,
196 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
197 MLXSW_PORT_ADMIN_STATUS_DOWN);
198 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
199 }
200
201 static int mlxsw_sx_port_oper_status_get(struct mlxsw_sx_port *mlxsw_sx_port,
202 bool *p_is_up)
203 {
204 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
205 char paos_pl[MLXSW_REG_PAOS_LEN];
206 u8 oper_status;
207 int err;
208
209 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port, 0);
210 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
211 if (err)
212 return err;
213 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
214 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
215 return 0;
216 }
217
218 static int mlxsw_sx_port_mtu_set(struct mlxsw_sx_port *mlxsw_sx_port, u16 mtu)
219 {
220 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
221 char pmtu_pl[MLXSW_REG_PMTU_LEN];
222 int max_mtu;
223 int err;
224
225 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
226 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, 0);
227 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
228 if (err)
229 return err;
230 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
231
232 if (mtu > max_mtu)
233 return -EINVAL;
234
235 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, mtu);
236 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
237 }
238
239 static int mlxsw_sx_port_swid_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 swid)
240 {
241 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
242 char pspa_pl[MLXSW_REG_PSPA_LEN];
243
244 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sx_port->local_port);
245 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pspa), pspa_pl);
246 }
247
248 static int
249 mlxsw_sx_port_system_port_mapping_set(struct mlxsw_sx_port *mlxsw_sx_port)
250 {
251 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
252 char sspr_pl[MLXSW_REG_SSPR_LEN];
253
254 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sx_port->local_port);
255 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sspr), sspr_pl);
256 }
257
258 static int mlxsw_sx_port_module_check(struct mlxsw_sx_port *mlxsw_sx_port,
259 bool *p_usable)
260 {
261 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
262 char pmlp_pl[MLXSW_REG_PMLP_LEN];
263 int err;
264
265 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sx_port->local_port);
266 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmlp), pmlp_pl);
267 if (err)
268 return err;
269 *p_usable = mlxsw_reg_pmlp_width_get(pmlp_pl) ? true : false;
270 return 0;
271 }
272
273 static int mlxsw_sx_port_open(struct net_device *dev)
274 {
275 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
276 int err;
277
278 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
279 if (err)
280 return err;
281 netif_start_queue(dev);
282 return 0;
283 }
284
285 static int mlxsw_sx_port_stop(struct net_device *dev)
286 {
287 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
288
289 netif_stop_queue(dev);
290 return mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
291 }
292
293 static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
294 struct net_device *dev)
295 {
296 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
297 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
298 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
299 const struct mlxsw_tx_info tx_info = {
300 .local_port = mlxsw_sx_port->local_port,
301 .is_emad = false,
302 };
303 struct sk_buff *skb_old = NULL;
304 int err;
305
306 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
307 struct sk_buff *skb_new;
308
309 skb_old = skb;
310 skb_new = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
311 if (!skb_new) {
312 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
313 dev_kfree_skb_any(skb_old);
314 return NETDEV_TX_OK;
315 }
316 skb = skb_new;
317 }
318 mlxsw_sx_txhdr_construct(skb, &tx_info);
319 err = mlxsw_core_skb_transmit(mlxsw_sx, skb, &tx_info);
320 if (err == -EAGAIN) {
321 if (skb_old)
322 dev_kfree_skb_any(skb);
323 return NETDEV_TX_BUSY;
324 }
325
326 if (skb_old)
327 dev_kfree_skb_any(skb_old);
328
329 if (!err) {
330 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
331 u64_stats_update_begin(&pcpu_stats->syncp);
332 pcpu_stats->tx_packets++;
333 pcpu_stats->tx_bytes += skb->len;
334 u64_stats_update_end(&pcpu_stats->syncp);
335 } else {
336 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
337 dev_kfree_skb_any(skb);
338 }
339 return NETDEV_TX_OK;
340 }
341
342 static int mlxsw_sx_port_change_mtu(struct net_device *dev, int mtu)
343 {
344 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
345 int err;
346
347 err = mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
348 if (err)
349 return err;
350 dev->mtu = mtu;
351 return 0;
352 }
353
354 static struct rtnl_link_stats64 *
355 mlxsw_sx_port_get_stats64(struct net_device *dev,
356 struct rtnl_link_stats64 *stats)
357 {
358 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
359 struct mlxsw_sx_port_pcpu_stats *p;
360 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
361 u32 tx_dropped = 0;
362 unsigned int start;
363 int i;
364
365 for_each_possible_cpu(i) {
366 p = per_cpu_ptr(mlxsw_sx_port->pcpu_stats, i);
367 do {
368 start = u64_stats_fetch_begin_irq(&p->syncp);
369 rx_packets = p->rx_packets;
370 rx_bytes = p->rx_bytes;
371 tx_packets = p->tx_packets;
372 tx_bytes = p->tx_bytes;
373 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
374
375 stats->rx_packets += rx_packets;
376 stats->rx_bytes += rx_bytes;
377 stats->tx_packets += tx_packets;
378 stats->tx_bytes += tx_bytes;
379 /* tx_dropped is u32, updated without syncp protection. */
380 tx_dropped += p->tx_dropped;
381 }
382 stats->tx_dropped = tx_dropped;
383 return stats;
384 }
385
386 static const struct net_device_ops mlxsw_sx_port_netdev_ops = {
387 .ndo_open = mlxsw_sx_port_open,
388 .ndo_stop = mlxsw_sx_port_stop,
389 .ndo_start_xmit = mlxsw_sx_port_xmit,
390 .ndo_change_mtu = mlxsw_sx_port_change_mtu,
391 .ndo_get_stats64 = mlxsw_sx_port_get_stats64,
392 };
393
394 static void mlxsw_sx_port_get_drvinfo(struct net_device *dev,
395 struct ethtool_drvinfo *drvinfo)
396 {
397 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
398 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
399
400 strlcpy(drvinfo->driver, mlxsw_sx_driver_name, sizeof(drvinfo->driver));
401 strlcpy(drvinfo->version, mlxsw_sx_driver_version,
402 sizeof(drvinfo->version));
403 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
404 "%d.%d.%d",
405 mlxsw_sx->bus_info->fw_rev.major,
406 mlxsw_sx->bus_info->fw_rev.minor,
407 mlxsw_sx->bus_info->fw_rev.subminor);
408 strlcpy(drvinfo->bus_info, mlxsw_sx->bus_info->device_name,
409 sizeof(drvinfo->bus_info));
410 }
411
412 struct mlxsw_sx_port_hw_stats {
413 char str[ETH_GSTRING_LEN];
414 u64 (*getter)(char *payload);
415 };
416
417 static const struct mlxsw_sx_port_hw_stats mlxsw_sx_port_hw_stats[] = {
418 {
419 .str = "a_frames_transmitted_ok",
420 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
421 },
422 {
423 .str = "a_frames_received_ok",
424 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
425 },
426 {
427 .str = "a_frame_check_sequence_errors",
428 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
429 },
430 {
431 .str = "a_alignment_errors",
432 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
433 },
434 {
435 .str = "a_octets_transmitted_ok",
436 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
437 },
438 {
439 .str = "a_octets_received_ok",
440 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
441 },
442 {
443 .str = "a_multicast_frames_xmitted_ok",
444 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
445 },
446 {
447 .str = "a_broadcast_frames_xmitted_ok",
448 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
449 },
450 {
451 .str = "a_multicast_frames_received_ok",
452 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
453 },
454 {
455 .str = "a_broadcast_frames_received_ok",
456 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
457 },
458 {
459 .str = "a_in_range_length_errors",
460 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
461 },
462 {
463 .str = "a_out_of_range_length_field",
464 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
465 },
466 {
467 .str = "a_frame_too_long_errors",
468 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
469 },
470 {
471 .str = "a_symbol_error_during_carrier",
472 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
473 },
474 {
475 .str = "a_mac_control_frames_transmitted",
476 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
477 },
478 {
479 .str = "a_mac_control_frames_received",
480 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
481 },
482 {
483 .str = "a_unsupported_opcodes_received",
484 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
485 },
486 {
487 .str = "a_pause_mac_ctrl_frames_received",
488 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
489 },
490 {
491 .str = "a_pause_mac_ctrl_frames_xmitted",
492 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
493 },
494 };
495
496 #define MLXSW_SX_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sx_port_hw_stats)
497
498 static void mlxsw_sx_port_get_strings(struct net_device *dev,
499 u32 stringset, u8 *data)
500 {
501 u8 *p = data;
502 int i;
503
504 switch (stringset) {
505 case ETH_SS_STATS:
506 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++) {
507 memcpy(p, mlxsw_sx_port_hw_stats[i].str,
508 ETH_GSTRING_LEN);
509 p += ETH_GSTRING_LEN;
510 }
511 break;
512 }
513 }
514
515 static void mlxsw_sx_port_get_stats(struct net_device *dev,
516 struct ethtool_stats *stats, u64 *data)
517 {
518 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
519 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
520 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
521 int i;
522 int err;
523
524 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sx_port->local_port);
525 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppcnt), ppcnt_pl);
526 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++)
527 data[i] = !err ? mlxsw_sx_port_hw_stats[i].getter(ppcnt_pl) : 0;
528 }
529
530 static int mlxsw_sx_port_get_sset_count(struct net_device *dev, int sset)
531 {
532 switch (sset) {
533 case ETH_SS_STATS:
534 return MLXSW_SX_PORT_HW_STATS_LEN;
535 default:
536 return -EOPNOTSUPP;
537 }
538 }
539
540 struct mlxsw_sx_port_link_mode {
541 u32 mask;
542 u32 supported;
543 u32 advertised;
544 u32 speed;
545 };
546
547 static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {
548 {
549 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
550 .supported = SUPPORTED_100baseT_Full,
551 .advertised = ADVERTISED_100baseT_Full,
552 .speed = 100,
553 },
554 {
555 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
556 .speed = 100,
557 },
558 {
559 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
560 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
561 .supported = SUPPORTED_1000baseKX_Full,
562 .advertised = ADVERTISED_1000baseKX_Full,
563 .speed = 1000,
564 },
565 {
566 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
567 .supported = SUPPORTED_10000baseT_Full,
568 .advertised = ADVERTISED_10000baseT_Full,
569 .speed = 10000,
570 },
571 {
572 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
573 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
574 .supported = SUPPORTED_10000baseKX4_Full,
575 .advertised = ADVERTISED_10000baseKX4_Full,
576 .speed = 10000,
577 },
578 {
579 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
580 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
581 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
582 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
583 .supported = SUPPORTED_10000baseKR_Full,
584 .advertised = ADVERTISED_10000baseKR_Full,
585 .speed = 10000,
586 },
587 {
588 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
589 .supported = SUPPORTED_20000baseKR2_Full,
590 .advertised = ADVERTISED_20000baseKR2_Full,
591 .speed = 20000,
592 },
593 {
594 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
595 .supported = SUPPORTED_40000baseCR4_Full,
596 .advertised = ADVERTISED_40000baseCR4_Full,
597 .speed = 40000,
598 },
599 {
600 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
601 .supported = SUPPORTED_40000baseKR4_Full,
602 .advertised = ADVERTISED_40000baseKR4_Full,
603 .speed = 40000,
604 },
605 {
606 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
607 .supported = SUPPORTED_40000baseSR4_Full,
608 .advertised = ADVERTISED_40000baseSR4_Full,
609 .speed = 40000,
610 },
611 {
612 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
613 .supported = SUPPORTED_40000baseLR4_Full,
614 .advertised = ADVERTISED_40000baseLR4_Full,
615 .speed = 40000,
616 },
617 {
618 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
619 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
620 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
621 .speed = 25000,
622 },
623 {
624 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
625 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
626 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
627 .speed = 50000,
628 },
629 {
630 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
631 .supported = SUPPORTED_56000baseKR4_Full,
632 .advertised = ADVERTISED_56000baseKR4_Full,
633 .speed = 56000,
634 },
635 {
636 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
637 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
638 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
639 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
640 .speed = 100000,
641 },
642 };
643
644 #define MLXSW_SX_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sx_port_link_mode)
645
646 static u32 mlxsw_sx_from_ptys_supported_port(u32 ptys_eth_proto)
647 {
648 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
649 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
650 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
651 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
652 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
653 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
654 return SUPPORTED_FIBRE;
655
656 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
657 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
658 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
659 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
660 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
661 return SUPPORTED_Backplane;
662 return 0;
663 }
664
665 static u32 mlxsw_sx_from_ptys_supported_link(u32 ptys_eth_proto)
666 {
667 u32 modes = 0;
668 int i;
669
670 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
671 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
672 modes |= mlxsw_sx_port_link_mode[i].supported;
673 }
674 return modes;
675 }
676
677 static u32 mlxsw_sx_from_ptys_advert_link(u32 ptys_eth_proto)
678 {
679 u32 modes = 0;
680 int i;
681
682 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
683 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
684 modes |= mlxsw_sx_port_link_mode[i].advertised;
685 }
686 return modes;
687 }
688
689 static void mlxsw_sx_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
690 struct ethtool_cmd *cmd)
691 {
692 u32 speed = SPEED_UNKNOWN;
693 u8 duplex = DUPLEX_UNKNOWN;
694 int i;
695
696 if (!carrier_ok)
697 goto out;
698
699 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
700 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) {
701 speed = mlxsw_sx_port_link_mode[i].speed;
702 duplex = DUPLEX_FULL;
703 break;
704 }
705 }
706 out:
707 ethtool_cmd_speed_set(cmd, speed);
708 cmd->duplex = duplex;
709 }
710
711 static u8 mlxsw_sx_port_connector_port(u32 ptys_eth_proto)
712 {
713 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
714 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
715 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
716 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
717 return PORT_FIBRE;
718
719 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
720 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
721 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
722 return PORT_DA;
723
724 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
725 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
726 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
727 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
728 return PORT_NONE;
729
730 return PORT_OTHER;
731 }
732
733 static int mlxsw_sx_port_get_settings(struct net_device *dev,
734 struct ethtool_cmd *cmd)
735 {
736 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
737 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
738 char ptys_pl[MLXSW_REG_PTYS_LEN];
739 u32 eth_proto_cap;
740 u32 eth_proto_admin;
741 u32 eth_proto_oper;
742 int err;
743
744 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
745 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
746 if (err) {
747 netdev_err(dev, "Failed to get proto");
748 return err;
749 }
750 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap,
751 &eth_proto_admin, &eth_proto_oper);
752
753 cmd->supported = mlxsw_sx_from_ptys_supported_port(eth_proto_cap) |
754 mlxsw_sx_from_ptys_supported_link(eth_proto_cap) |
755 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
756 cmd->advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_admin);
757 mlxsw_sx_from_ptys_speed_duplex(netif_carrier_ok(dev),
758 eth_proto_oper, cmd);
759
760 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
761 cmd->port = mlxsw_sx_port_connector_port(eth_proto_oper);
762 cmd->lp_advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_oper);
763
764 cmd->transceiver = XCVR_INTERNAL;
765 return 0;
766 }
767
768 static u32 mlxsw_sx_to_ptys_advert_link(u32 advertising)
769 {
770 u32 ptys_proto = 0;
771 int i;
772
773 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
774 if (advertising & mlxsw_sx_port_link_mode[i].advertised)
775 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
776 }
777 return ptys_proto;
778 }
779
780 static u32 mlxsw_sx_to_ptys_speed(u32 speed)
781 {
782 u32 ptys_proto = 0;
783 int i;
784
785 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
786 if (speed == mlxsw_sx_port_link_mode[i].speed)
787 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
788 }
789 return ptys_proto;
790 }
791
792 static int mlxsw_sx_port_set_settings(struct net_device *dev,
793 struct ethtool_cmd *cmd)
794 {
795 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
796 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
797 char ptys_pl[MLXSW_REG_PTYS_LEN];
798 u32 speed;
799 u32 eth_proto_new;
800 u32 eth_proto_cap;
801 u32 eth_proto_admin;
802 bool is_up;
803 int err;
804
805 speed = ethtool_cmd_speed(cmd);
806
807 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
808 mlxsw_sx_to_ptys_advert_link(cmd->advertising) :
809 mlxsw_sx_to_ptys_speed(speed);
810
811 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
812 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
813 if (err) {
814 netdev_err(dev, "Failed to get proto");
815 return err;
816 }
817 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin, NULL);
818
819 eth_proto_new = eth_proto_new & eth_proto_cap;
820 if (!eth_proto_new) {
821 netdev_err(dev, "Not supported proto admin requested");
822 return -EINVAL;
823 }
824 if (eth_proto_new == eth_proto_admin)
825 return 0;
826
827 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, eth_proto_new);
828 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
829 if (err) {
830 netdev_err(dev, "Failed to set proto admin");
831 return err;
832 }
833
834 err = mlxsw_sx_port_oper_status_get(mlxsw_sx_port, &is_up);
835 if (err) {
836 netdev_err(dev, "Failed to get oper status");
837 return err;
838 }
839 if (!is_up)
840 return 0;
841
842 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
843 if (err) {
844 netdev_err(dev, "Failed to set admin status");
845 return err;
846 }
847
848 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
849 if (err) {
850 netdev_err(dev, "Failed to set admin status");
851 return err;
852 }
853
854 return 0;
855 }
856
857 static const struct ethtool_ops mlxsw_sx_port_ethtool_ops = {
858 .get_drvinfo = mlxsw_sx_port_get_drvinfo,
859 .get_link = ethtool_op_get_link,
860 .get_strings = mlxsw_sx_port_get_strings,
861 .get_ethtool_stats = mlxsw_sx_port_get_stats,
862 .get_sset_count = mlxsw_sx_port_get_sset_count,
863 .get_settings = mlxsw_sx_port_get_settings,
864 .set_settings = mlxsw_sx_port_set_settings,
865 };
866
867 static int mlxsw_sx_port_attr_get(struct net_device *dev,
868 struct switchdev_attr *attr)
869 {
870 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
871 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
872
873 switch (attr->id) {
874 case SWITCHDEV_ATTR_PORT_PARENT_ID:
875 attr->u.ppid.id_len = sizeof(mlxsw_sx->hw_id);
876 memcpy(&attr->u.ppid.id, &mlxsw_sx->hw_id, attr->u.ppid.id_len);
877 break;
878 default:
879 return -EOPNOTSUPP;
880 }
881
882 return 0;
883 }
884
885 static const struct switchdev_ops mlxsw_sx_port_switchdev_ops = {
886 .switchdev_port_attr_get = mlxsw_sx_port_attr_get,
887 };
888
889 static int mlxsw_sx_hw_id_get(struct mlxsw_sx *mlxsw_sx)
890 {
891 char spad_pl[MLXSW_REG_SPAD_LEN];
892 int err;
893
894 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(spad), spad_pl);
895 if (err)
896 return err;
897 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sx->hw_id);
898 return 0;
899 }
900
901 static int mlxsw_sx_port_dev_addr_get(struct mlxsw_sx_port *mlxsw_sx_port)
902 {
903 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
904 struct net_device *dev = mlxsw_sx_port->dev;
905 char ppad_pl[MLXSW_REG_PPAD_LEN];
906 int err;
907
908 mlxsw_reg_ppad_pack(ppad_pl, false, 0);
909 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppad), ppad_pl);
910 if (err)
911 return err;
912 mlxsw_reg_ppad_mac_memcpy_from(ppad_pl, dev->dev_addr);
913 /* The last byte value in base mac address is guaranteed
914 * to be such it does not overflow when adding local_port
915 * value.
916 */
917 dev->dev_addr[ETH_ALEN - 1] += mlxsw_sx_port->local_port;
918 return 0;
919 }
920
921 static int mlxsw_sx_port_stp_state_set(struct mlxsw_sx_port *mlxsw_sx_port,
922 u16 vid, enum mlxsw_reg_spms_state state)
923 {
924 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
925 char *spms_pl;
926 int err;
927
928 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
929 if (!spms_pl)
930 return -ENOMEM;
931 mlxsw_reg_spms_pack(spms_pl, mlxsw_sx_port->local_port, vid, state);
932 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spms), spms_pl);
933 kfree(spms_pl);
934 return err;
935 }
936
937 static int mlxsw_sx_port_speed_set(struct mlxsw_sx_port *mlxsw_sx_port,
938 u32 speed)
939 {
940 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
941 char ptys_pl[MLXSW_REG_PTYS_LEN];
942
943 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, speed);
944 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
945 }
946
947 static int
948 mlxsw_sx_port_mac_learning_mode_set(struct mlxsw_sx_port *mlxsw_sx_port,
949 enum mlxsw_reg_spmlr_learn_mode mode)
950 {
951 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
952 char spmlr_pl[MLXSW_REG_SPMLR_LEN];
953
954 mlxsw_reg_spmlr_pack(spmlr_pl, mlxsw_sx_port->local_port, mode);
955 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spmlr), spmlr_pl);
956 }
957
958 static int mlxsw_sx_port_create(struct mlxsw_sx *mlxsw_sx, u8 local_port)
959 {
960 struct mlxsw_sx_port *mlxsw_sx_port;
961 struct net_device *dev;
962 bool usable;
963 int err;
964
965 dev = alloc_etherdev(sizeof(struct mlxsw_sx_port));
966 if (!dev)
967 return -ENOMEM;
968 mlxsw_sx_port = netdev_priv(dev);
969 mlxsw_sx_port->dev = dev;
970 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
971 mlxsw_sx_port->local_port = local_port;
972
973 mlxsw_sx_port->pcpu_stats =
974 netdev_alloc_pcpu_stats(struct mlxsw_sx_port_pcpu_stats);
975 if (!mlxsw_sx_port->pcpu_stats) {
976 err = -ENOMEM;
977 goto err_alloc_stats;
978 }
979
980 dev->netdev_ops = &mlxsw_sx_port_netdev_ops;
981 dev->ethtool_ops = &mlxsw_sx_port_ethtool_ops;
982 dev->switchdev_ops = &mlxsw_sx_port_switchdev_ops;
983
984 err = mlxsw_sx_port_dev_addr_get(mlxsw_sx_port);
985 if (err) {
986 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Unable to get port mac address\n",
987 mlxsw_sx_port->local_port);
988 goto err_dev_addr_get;
989 }
990
991 netif_carrier_off(dev);
992
993 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
994 NETIF_F_VLAN_CHALLENGED;
995
996 /* Each packet needs to have a Tx header (metadata) on top all other
997 * headers.
998 */
999 dev->hard_header_len += MLXSW_TXHDR_LEN;
1000
1001 err = mlxsw_sx_port_module_check(mlxsw_sx_port, &usable);
1002 if (err) {
1003 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to check module\n",
1004 mlxsw_sx_port->local_port);
1005 goto err_port_module_check;
1006 }
1007
1008 if (!usable) {
1009 dev_dbg(mlxsw_sx->bus_info->dev, "Port %d: Not usable, skipping initialization\n",
1010 mlxsw_sx_port->local_port);
1011 goto port_not_usable;
1012 }
1013
1014 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1015 if (err) {
1016 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1017 mlxsw_sx_port->local_port);
1018 goto err_port_system_port_mapping_set;
1019 }
1020
1021 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 0);
1022 if (err) {
1023 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1024 mlxsw_sx_port->local_port);
1025 goto err_port_swid_set;
1026 }
1027
1028 err = mlxsw_sx_port_speed_set(mlxsw_sx_port,
1029 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4);
1030 if (err) {
1031 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1032 mlxsw_sx_port->local_port);
1033 goto err_port_speed_set;
1034 }
1035
1036 err = mlxsw_sx_port_mtu_set(mlxsw_sx_port, ETH_DATA_LEN);
1037 if (err) {
1038 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1039 mlxsw_sx_port->local_port);
1040 goto err_port_mtu_set;
1041 }
1042
1043 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1044 if (err)
1045 goto err_port_admin_status_set;
1046
1047 err = mlxsw_sx_port_stp_state_set(mlxsw_sx_port,
1048 MLXSW_PORT_DEFAULT_VID,
1049 MLXSW_REG_SPMS_STATE_FORWARDING);
1050 if (err) {
1051 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set STP state\n",
1052 mlxsw_sx_port->local_port);
1053 goto err_port_stp_state_set;
1054 }
1055
1056 err = mlxsw_sx_port_mac_learning_mode_set(mlxsw_sx_port,
1057 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE);
1058 if (err) {
1059 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MAC learning mode\n",
1060 mlxsw_sx_port->local_port);
1061 goto err_port_mac_learning_mode_set;
1062 }
1063
1064 err = register_netdev(dev);
1065 if (err) {
1066 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to register netdev\n",
1067 mlxsw_sx_port->local_port);
1068 goto err_register_netdev;
1069 }
1070
1071 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1072 return 0;
1073
1074 err_register_netdev:
1075 err_port_admin_status_set:
1076 err_port_mac_learning_mode_set:
1077 err_port_stp_state_set:
1078 err_port_mtu_set:
1079 err_port_speed_set:
1080 err_port_swid_set:
1081 err_port_system_port_mapping_set:
1082 port_not_usable:
1083 err_port_module_check:
1084 err_dev_addr_get:
1085 free_percpu(mlxsw_sx_port->pcpu_stats);
1086 err_alloc_stats:
1087 free_netdev(dev);
1088 return err;
1089 }
1090
1091 static void mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1092 {
1093 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1094
1095 if (!mlxsw_sx_port)
1096 return;
1097 unregister_netdev(mlxsw_sx_port->dev); /* This calls ndo_stop */
1098 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1099 free_percpu(mlxsw_sx_port->pcpu_stats);
1100 free_netdev(mlxsw_sx_port->dev);
1101 }
1102
1103 static void mlxsw_sx_ports_remove(struct mlxsw_sx *mlxsw_sx)
1104 {
1105 int i;
1106
1107 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1108 mlxsw_sx_port_remove(mlxsw_sx, i);
1109 kfree(mlxsw_sx->ports);
1110 }
1111
1112 static int mlxsw_sx_ports_create(struct mlxsw_sx *mlxsw_sx)
1113 {
1114 size_t alloc_size;
1115 int i;
1116 int err;
1117
1118 alloc_size = sizeof(struct mlxsw_sx_port *) * MLXSW_PORT_MAX_PORTS;
1119 mlxsw_sx->ports = kzalloc(alloc_size, GFP_KERNEL);
1120 if (!mlxsw_sx->ports)
1121 return -ENOMEM;
1122
1123 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
1124 err = mlxsw_sx_port_create(mlxsw_sx, i);
1125 if (err)
1126 goto err_port_create;
1127 }
1128 return 0;
1129
1130 err_port_create:
1131 for (i--; i >= 1; i--)
1132 mlxsw_sx_port_remove(mlxsw_sx, i);
1133 kfree(mlxsw_sx->ports);
1134 return err;
1135 }
1136
1137 static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg,
1138 char *pude_pl, void *priv)
1139 {
1140 struct mlxsw_sx *mlxsw_sx = priv;
1141 struct mlxsw_sx_port *mlxsw_sx_port;
1142 enum mlxsw_reg_pude_oper_status status;
1143 u8 local_port;
1144
1145 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
1146 mlxsw_sx_port = mlxsw_sx->ports[local_port];
1147 if (!mlxsw_sx_port) {
1148 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: Link event received for non-existent port\n",
1149 local_port);
1150 return;
1151 }
1152
1153 status = mlxsw_reg_pude_oper_status_get(pude_pl);
1154 if (MLXSW_PORT_OPER_STATUS_UP == status) {
1155 netdev_info(mlxsw_sx_port->dev, "link up\n");
1156 netif_carrier_on(mlxsw_sx_port->dev);
1157 } else {
1158 netdev_info(mlxsw_sx_port->dev, "link down\n");
1159 netif_carrier_off(mlxsw_sx_port->dev);
1160 }
1161 }
1162
1163 static struct mlxsw_event_listener mlxsw_sx_pude_event = {
1164 .func = mlxsw_sx_pude_event_func,
1165 .trap_id = MLXSW_TRAP_ID_PUDE,
1166 };
1167
1168 static int mlxsw_sx_event_register(struct mlxsw_sx *mlxsw_sx,
1169 enum mlxsw_event_trap_id trap_id)
1170 {
1171 struct mlxsw_event_listener *el;
1172 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1173 int err;
1174
1175 switch (trap_id) {
1176 case MLXSW_TRAP_ID_PUDE:
1177 el = &mlxsw_sx_pude_event;
1178 break;
1179 }
1180 err = mlxsw_core_event_listener_register(mlxsw_sx->core, el, mlxsw_sx);
1181 if (err)
1182 return err;
1183
1184 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1185 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, trap_id);
1186 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1187 if (err)
1188 goto err_event_trap_set;
1189
1190 return 0;
1191
1192 err_event_trap_set:
1193 mlxsw_core_event_listener_unregister(mlxsw_sx->core, el, mlxsw_sx);
1194 return err;
1195 }
1196
1197 static void mlxsw_sx_event_unregister(struct mlxsw_sx *mlxsw_sx,
1198 enum mlxsw_event_trap_id trap_id)
1199 {
1200 struct mlxsw_event_listener *el;
1201
1202 switch (trap_id) {
1203 case MLXSW_TRAP_ID_PUDE:
1204 el = &mlxsw_sx_pude_event;
1205 break;
1206 }
1207 mlxsw_core_event_listener_unregister(mlxsw_sx->core, el, mlxsw_sx);
1208 }
1209
1210 static void mlxsw_sx_rx_listener_func(struct sk_buff *skb, u8 local_port,
1211 void *priv)
1212 {
1213 struct mlxsw_sx *mlxsw_sx = priv;
1214 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1215 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
1216
1217 if (unlikely(!mlxsw_sx_port)) {
1218 if (net_ratelimit())
1219 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: skb received for non-existent port\n",
1220 local_port);
1221 return;
1222 }
1223
1224 skb->dev = mlxsw_sx_port->dev;
1225
1226 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
1227 u64_stats_update_begin(&pcpu_stats->syncp);
1228 pcpu_stats->rx_packets++;
1229 pcpu_stats->rx_bytes += skb->len;
1230 u64_stats_update_end(&pcpu_stats->syncp);
1231
1232 skb->protocol = eth_type_trans(skb, skb->dev);
1233 netif_receive_skb(skb);
1234 }
1235
1236 static const struct mlxsw_rx_listener mlxsw_sx_rx_listener[] = {
1237 {
1238 .func = mlxsw_sx_rx_listener_func,
1239 .local_port = MLXSW_PORT_DONT_CARE,
1240 .trap_id = MLXSW_TRAP_ID_FDB_MC,
1241 },
1242 /* Traps for specific L2 packet types, not trapped as FDB MC */
1243 {
1244 .func = mlxsw_sx_rx_listener_func,
1245 .local_port = MLXSW_PORT_DONT_CARE,
1246 .trap_id = MLXSW_TRAP_ID_STP,
1247 },
1248 {
1249 .func = mlxsw_sx_rx_listener_func,
1250 .local_port = MLXSW_PORT_DONT_CARE,
1251 .trap_id = MLXSW_TRAP_ID_LACP,
1252 },
1253 {
1254 .func = mlxsw_sx_rx_listener_func,
1255 .local_port = MLXSW_PORT_DONT_CARE,
1256 .trap_id = MLXSW_TRAP_ID_EAPOL,
1257 },
1258 {
1259 .func = mlxsw_sx_rx_listener_func,
1260 .local_port = MLXSW_PORT_DONT_CARE,
1261 .trap_id = MLXSW_TRAP_ID_LLDP,
1262 },
1263 {
1264 .func = mlxsw_sx_rx_listener_func,
1265 .local_port = MLXSW_PORT_DONT_CARE,
1266 .trap_id = MLXSW_TRAP_ID_MMRP,
1267 },
1268 {
1269 .func = mlxsw_sx_rx_listener_func,
1270 .local_port = MLXSW_PORT_DONT_CARE,
1271 .trap_id = MLXSW_TRAP_ID_MVRP,
1272 },
1273 {
1274 .func = mlxsw_sx_rx_listener_func,
1275 .local_port = MLXSW_PORT_DONT_CARE,
1276 .trap_id = MLXSW_TRAP_ID_RPVST,
1277 },
1278 {
1279 .func = mlxsw_sx_rx_listener_func,
1280 .local_port = MLXSW_PORT_DONT_CARE,
1281 .trap_id = MLXSW_TRAP_ID_DHCP,
1282 },
1283 {
1284 .func = mlxsw_sx_rx_listener_func,
1285 .local_port = MLXSW_PORT_DONT_CARE,
1286 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
1287 },
1288 {
1289 .func = mlxsw_sx_rx_listener_func,
1290 .local_port = MLXSW_PORT_DONT_CARE,
1291 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
1292 },
1293 {
1294 .func = mlxsw_sx_rx_listener_func,
1295 .local_port = MLXSW_PORT_DONT_CARE,
1296 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
1297 },
1298 {
1299 .func = mlxsw_sx_rx_listener_func,
1300 .local_port = MLXSW_PORT_DONT_CARE,
1301 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
1302 },
1303 {
1304 .func = mlxsw_sx_rx_listener_func,
1305 .local_port = MLXSW_PORT_DONT_CARE,
1306 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
1307 },
1308 };
1309
1310 static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1311 {
1312 char htgt_pl[MLXSW_REG_HTGT_LEN];
1313 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1314 int i;
1315 int err;
1316
1317 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
1318 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1319 if (err)
1320 return err;
1321
1322 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) {
1323 err = mlxsw_core_rx_listener_register(mlxsw_sx->core,
1324 &mlxsw_sx_rx_listener[i],
1325 mlxsw_sx);
1326 if (err)
1327 goto err_rx_listener_register;
1328
1329 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
1330 MLXSW_REG_HTGT_TRAP_GROUP_RX,
1331 mlxsw_sx_rx_listener[i].trap_id);
1332 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1333 if (err)
1334 goto err_rx_trap_set;
1335 }
1336 return 0;
1337
1338 err_rx_trap_set:
1339 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1340 &mlxsw_sx_rx_listener[i],
1341 mlxsw_sx);
1342 err_rx_listener_register:
1343 for (i--; i >= 0; i--) {
1344 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1345 MLXSW_REG_HTGT_TRAP_GROUP_RX,
1346 mlxsw_sx_rx_listener[i].trap_id);
1347 mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1348
1349 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1350 &mlxsw_sx_rx_listener[i],
1351 mlxsw_sx);
1352 }
1353 return err;
1354 }
1355
1356 static void mlxsw_sx_traps_fini(struct mlxsw_sx *mlxsw_sx)
1357 {
1358 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1359 int i;
1360
1361 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) {
1362 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1363 MLXSW_REG_HTGT_TRAP_GROUP_RX,
1364 mlxsw_sx_rx_listener[i].trap_id);
1365 mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1366
1367 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1368 &mlxsw_sx_rx_listener[i],
1369 mlxsw_sx);
1370 }
1371 }
1372
1373 static int mlxsw_sx_flood_init(struct mlxsw_sx *mlxsw_sx)
1374 {
1375 char sfgc_pl[MLXSW_REG_SFGC_LEN];
1376 char sgcr_pl[MLXSW_REG_SGCR_LEN];
1377 char *smid_pl;
1378 char *sftr_pl;
1379 int err;
1380
1381 /* Due to FW bug, we must configure SMID. */
1382 smid_pl = kmalloc(MLXSW_REG_SMID_LEN, GFP_KERNEL);
1383 if (!smid_pl)
1384 return -ENOMEM;
1385 mlxsw_reg_smid_pack(smid_pl, MLXSW_PORT_MID);
1386 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(smid), smid_pl);
1387 kfree(smid_pl);
1388 if (err)
1389 return err;
1390
1391 /* Configure a flooding table, which includes only CPU port. */
1392 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
1393 if (!sftr_pl)
1394 return -ENOMEM;
1395 mlxsw_reg_sftr_pack(sftr_pl, 0, 0, MLXSW_REG_SFGC_TABLE_TYPE_SINGLE, 0);
1396 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sftr), sftr_pl);
1397 kfree(sftr_pl);
1398 if (err)
1399 return err;
1400
1401 /* Flood different packet types using the flooding table. */
1402 mlxsw_reg_sfgc_pack(sfgc_pl,
1403 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1404 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1405 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1406 0);
1407 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1408 if (err)
1409 return err;
1410
1411 mlxsw_reg_sfgc_pack(sfgc_pl,
1412 MLXSW_REG_SFGC_TYPE_BROADCAST,
1413 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1414 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1415 0);
1416 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1417 if (err)
1418 return err;
1419
1420 mlxsw_reg_sfgc_pack(sfgc_pl,
1421 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1422 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1423 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1424 0);
1425 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1426 if (err)
1427 return err;
1428
1429 mlxsw_reg_sfgc_pack(sfgc_pl,
1430 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1431 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1432 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1433 0);
1434 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1435 if (err)
1436 return err;
1437
1438 mlxsw_reg_sfgc_pack(sfgc_pl,
1439 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1440 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1441 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1442 0);
1443 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1444 if (err)
1445 return err;
1446
1447 mlxsw_reg_sgcr_pack(sgcr_pl, true);
1448 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sgcr), sgcr_pl);
1449 }
1450
1451 static int mlxsw_sx_init(void *priv, struct mlxsw_core *mlxsw_core,
1452 const struct mlxsw_bus_info *mlxsw_bus_info)
1453 {
1454 struct mlxsw_sx *mlxsw_sx = priv;
1455 int err;
1456
1457 mlxsw_sx->core = mlxsw_core;
1458 mlxsw_sx->bus_info = mlxsw_bus_info;
1459
1460 err = mlxsw_sx_hw_id_get(mlxsw_sx);
1461 if (err) {
1462 dev_err(mlxsw_sx->bus_info->dev, "Failed to get switch HW ID\n");
1463 return err;
1464 }
1465
1466 err = mlxsw_sx_ports_create(mlxsw_sx);
1467 if (err) {
1468 dev_err(mlxsw_sx->bus_info->dev, "Failed to create ports\n");
1469 return err;
1470 }
1471
1472 err = mlxsw_sx_event_register(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1473 if (err) {
1474 dev_err(mlxsw_sx->bus_info->dev, "Failed to register for PUDE events\n");
1475 goto err_event_register;
1476 }
1477
1478 err = mlxsw_sx_traps_init(mlxsw_sx);
1479 if (err) {
1480 dev_err(mlxsw_sx->bus_info->dev, "Failed to set traps for RX\n");
1481 goto err_rx_listener_register;
1482 }
1483
1484 err = mlxsw_sx_flood_init(mlxsw_sx);
1485 if (err) {
1486 dev_err(mlxsw_sx->bus_info->dev, "Failed to initialize flood tables\n");
1487 goto err_flood_init;
1488 }
1489
1490 return 0;
1491
1492 err_flood_init:
1493 mlxsw_sx_traps_fini(mlxsw_sx);
1494 err_rx_listener_register:
1495 mlxsw_sx_event_unregister(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1496 err_event_register:
1497 mlxsw_sx_ports_remove(mlxsw_sx);
1498 return err;
1499 }
1500
1501 static void mlxsw_sx_fini(void *priv)
1502 {
1503 struct mlxsw_sx *mlxsw_sx = priv;
1504
1505 mlxsw_sx_traps_fini(mlxsw_sx);
1506 mlxsw_sx_event_unregister(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1507 mlxsw_sx_ports_remove(mlxsw_sx);
1508 }
1509
1510 static struct mlxsw_config_profile mlxsw_sx_config_profile = {
1511 .used_max_vepa_channels = 1,
1512 .max_vepa_channels = 0,
1513 .used_max_lag = 1,
1514 .max_lag = 64,
1515 .used_max_port_per_lag = 1,
1516 .max_port_per_lag = 16,
1517 .used_max_mid = 1,
1518 .max_mid = 7000,
1519 .used_max_pgt = 1,
1520 .max_pgt = 0,
1521 .used_max_system_port = 1,
1522 .max_system_port = 48000,
1523 .used_max_vlan_groups = 1,
1524 .max_vlan_groups = 127,
1525 .used_max_regions = 1,
1526 .max_regions = 400,
1527 .used_flood_tables = 1,
1528 .max_flood_tables = 2,
1529 .max_vid_flood_tables = 1,
1530 .used_flood_mode = 1,
1531 .flood_mode = 3,
1532 .used_max_ib_mc = 1,
1533 .max_ib_mc = 0,
1534 .used_max_pkey = 1,
1535 .max_pkey = 0,
1536 .swid_config = {
1537 {
1538 .used_type = 1,
1539 .type = MLXSW_PORT_SWID_TYPE_ETH,
1540 }
1541 },
1542 };
1543
1544 static struct mlxsw_driver mlxsw_sx_driver = {
1545 .kind = MLXSW_DEVICE_KIND_SWITCHX2,
1546 .owner = THIS_MODULE,
1547 .priv_size = sizeof(struct mlxsw_sx),
1548 .init = mlxsw_sx_init,
1549 .fini = mlxsw_sx_fini,
1550 .txhdr_construct = mlxsw_sx_txhdr_construct,
1551 .txhdr_len = MLXSW_TXHDR_LEN,
1552 .profile = &mlxsw_sx_config_profile,
1553 };
1554
1555 static int __init mlxsw_sx_module_init(void)
1556 {
1557 return mlxsw_core_driver_register(&mlxsw_sx_driver);
1558 }
1559
1560 static void __exit mlxsw_sx_module_exit(void)
1561 {
1562 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1563 }
1564
1565 module_init(mlxsw_sx_module_init);
1566 module_exit(mlxsw_sx_module_exit);
1567
1568 MODULE_LICENSE("Dual BSD/GPL");
1569 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1570 MODULE_DESCRIPTION("Mellanox SwitchX-2 driver");
1571 MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SWITCHX2);