drivers/net/ethernet/mellanox/mlxsw/reg.h

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/reg.h
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
   5  * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
   6  * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. Neither the names of the copyright holders nor the names of its
  17  *    contributors may be used to endorse or promote products derived from
  18  *    this software without specific prior written permission.
  19  *
  20  * Alternatively, this software may be distributed under the terms of the
  21  * GNU General Public License ("GPL") version 2 as published by the Free
  22  * Software Foundation.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  28  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  34  * POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #ifndef _MLXSW_REG_H
  38 #define _MLXSW_REG_H
  39
  40 #include <linux/string.h>
  41 #include <linux/bitops.h>
  42 #include <linux/if_vlan.h>
  43
  44 #include "item.h"
  45 #include "port.h"
  46
  47 struct mlxsw_reg_info {
  48         u16 id;
  49         u16 len; /* In u8 */
  50 };
  51
  52 #define MLXSW_REG(type) (&mlxsw_reg_##type)
  53 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
  54 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
  55
  56 /* SGCR - Switch General Configuration Register
  57  * --------------------------------------------
  58  * This register is used for configuration of the switch capabilities.
  59  */
  60 #define MLXSW_REG_SGCR_ID 0x2000
  61 #define MLXSW_REG_SGCR_LEN 0x10
  62
  63 static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
  64         .id = MLXSW_REG_SGCR_ID,
  65         .len = MLXSW_REG_SGCR_LEN,
  66 };
  67
  68 /* reg_sgcr_llb
  69  * Link Local Broadcast (Default=0)
  70  * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
  71  * packets and ignore the IGMP snooping entries.
  72  * Access: RW
  73  */
  74 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
  75
  76 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
  77 {
  78         MLXSW_REG_ZERO(sgcr, payload);
  79         mlxsw_reg_sgcr_llb_set(payload, !!llb);
  80 }
  81
  82 /* SPAD - Switch Physical Address Register
  83  * ---------------------------------------
  84  * The SPAD register configures the switch physical MAC address.
  85  */
  86 #define MLXSW_REG_SPAD_ID 0x2002
  87 #define MLXSW_REG_SPAD_LEN 0x10
  88
  89 static const struct mlxsw_reg_info mlxsw_reg_spad = {
  90         .id = MLXSW_REG_SPAD_ID,
  91         .len = MLXSW_REG_SPAD_LEN,
  92 };
  93
  94 /* reg_spad_base_mac
  95  * Base MAC address for the switch partitions.
  96  * Per switch partition MAC address is equal to:
  97  * base_mac + swid
  98  * Access: RW
  99  */
 100 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
 101
 102 /* SMID - Switch Multicast ID
 103  * --------------------------
 104  * In multi-chip configuration, each device should maintain mapping between
 105  * Multicast ID (MID) into a list of local ports. This mapping is used in all
 106  * the devices other than the ingress device, and is implemented as part of the
 107  * FDB. The MID record maps from a MID, which is a unique identi- fier of the
 108  * multicast group within the stacking domain, into a list of local ports into
 109  * which the packet is replicated.
 110  */
 111 #define MLXSW_REG_SMID_ID 0x2007
 112 #define MLXSW_REG_SMID_LEN 0x420
 113
 114 static const struct mlxsw_reg_info mlxsw_reg_smid = {
 115         .id = MLXSW_REG_SMID_ID,
 116         .len = MLXSW_REG_SMID_LEN,
 117 };
 118
 119 /* reg_smid_swid
 120  * Switch partition ID.
 121  * Access: Index
 122  */
 123 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
 124
 125 /* reg_smid_mid
 126  * Multicast identifier - global identifier that represents the multicast group
 127  * across all devices
 128  * Access: Index
 129  */
 130 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
 131
 132 /* reg_smid_port
 133  * Local port memebership (1 bit per port).
 134  * Access: RW
 135  */
 136 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
 137
 138 /* reg_smid_port_mask
 139  * Local port mask (1 bit per port).
 140  * Access: W
 141  */
 142 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
 143
 144 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid)
 145 {
 146         MLXSW_REG_ZERO(smid, payload);
 147         mlxsw_reg_smid_swid_set(payload, 0);
 148         mlxsw_reg_smid_mid_set(payload, mid);
 149         mlxsw_reg_smid_port_set(payload, MLXSW_PORT_CPU_PORT, 1);
 150         mlxsw_reg_smid_port_mask_set(payload, MLXSW_PORT_CPU_PORT, 1);
 151 }
 152
 153 /* SSPR - Switch System Port Record Register
 154  * -----------------------------------------
 155  * Configures the system port to local port mapping.
 156  */
 157 #define MLXSW_REG_SSPR_ID 0x2008
 158 #define MLXSW_REG_SSPR_LEN 0x8
 159
 160 static const struct mlxsw_reg_info mlxsw_reg_sspr = {
 161         .id = MLXSW_REG_SSPR_ID,
 162         .len = MLXSW_REG_SSPR_LEN,
 163 };
 164
 165 /* reg_sspr_m
 166  * Master - if set, then the record describes the master system port.
 167  * This is needed in case a local port is mapped into several system ports
 168  * (for multipathing). That number will be reported as the source system
 169  * port when packets are forwarded to the CPU. Only one master port is allowed
 170  * per local port.
 171  *
 172  * Note: Must be set for Spectrum.
 173  * Access: RW
 174  */
 175 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
 176
 177 /* reg_sspr_local_port
 178  * Local port number.
 179  *
 180  * Access: RW
 181  */
 182 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
 183
 184 /* reg_sspr_sub_port
 185  * Virtual port within the physical port.
 186  * Should be set to 0 when virtual ports are not enabled on the port.
 187  *
 188  * Access: RW
 189  */
 190 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
 191
 192 /* reg_sspr_system_port
 193  * Unique identifier within the stacking domain that represents all the ports
 194  * that are available in the system (external ports).
 195  *
 196  * Currently, only single-ASIC configurations are supported, so we default to
 197  * 1:1 mapping between system ports and local ports.
 198  * Access: Index
 199  */
 200 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
 201
 202 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
 203 {
 204         MLXSW_REG_ZERO(sspr, payload);
 205         mlxsw_reg_sspr_m_set(payload, 1);
 206         mlxsw_reg_sspr_local_port_set(payload, local_port);
 207         mlxsw_reg_sspr_sub_port_set(payload, 0);
 208         mlxsw_reg_sspr_system_port_set(payload, local_port);
 209 }
 210
 211 /* SPMS - Switch Port MSTP/RSTP State Register
 212  * -------------------------------------------
 213  * Configures the spanning tree state of a physical port.
 214  */
 215 #define MLXSW_REG_SPMS_ID 0x200d
 216 #define MLXSW_REG_SPMS_LEN 0x404
 217
 218 static const struct mlxsw_reg_info mlxsw_reg_spms = {
 219         .id = MLXSW_REG_SPMS_ID,
 220         .len = MLXSW_REG_SPMS_LEN,
 221 };
 222
 223 /* reg_spms_local_port
 224  * Local port number.
 225  * Access: Index
 226  */
 227 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
 228
 229 enum mlxsw_reg_spms_state {
 230         MLXSW_REG_SPMS_STATE_NO_CHANGE,
 231         MLXSW_REG_SPMS_STATE_DISCARDING,
 232         MLXSW_REG_SPMS_STATE_LEARNING,
 233         MLXSW_REG_SPMS_STATE_FORWARDING,
 234 };
 235
 236 /* reg_spms_state
 237  * Spanning tree state of each VLAN ID (VID) of the local port.
 238  * 0 - Do not change spanning tree state (used only when writing).
 239  * 1 - Discarding. No learning or forwarding to/from this port (default).
 240  * 2 - Learning. Port is learning, but not forwarding.
 241  * 3 - Forwarding. Port is learning and forwarding.
 242  * Access: RW
 243  */
 244 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
 245
 246 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port, u16 vid,
 247                                        enum mlxsw_reg_spms_state state)
 248 {
 249         MLXSW_REG_ZERO(spms, payload);
 250         mlxsw_reg_spms_local_port_set(payload, local_port);
 251         mlxsw_reg_spms_state_set(payload, vid, state);
 252 }
 253
 254 /* SFGC - Switch Flooding Group Configuration
 255  * ------------------------------------------
 256  * The following register controls the association of flooding tables and MIDs
 257  * to packet types used for flooding.
 258  */
 259 #define MLXSW_REG_SFGC_ID  0x2011
 260 #define MLXSW_REG_SFGC_LEN 0x10
 261
 262 static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
 263         .id = MLXSW_REG_SFGC_ID,
 264         .len = MLXSW_REG_SFGC_LEN,
 265 };
 266
 267 enum mlxsw_reg_sfgc_type {
 268         MLXSW_REG_SFGC_TYPE_BROADCAST = 0,
 269         MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST = 1,
 270         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4 = 2,
 271         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6 = 3,
 272         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP = 5,
 273         MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL = 6,
 274         MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST = 7,
 275 };
 276
 277 /* reg_sfgc_type
 278  * The traffic type to reach the flooding table.
 279  * Access: Index
 280  */
 281 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
 282
 283 enum mlxsw_reg_sfgc_bridge_type {
 284         MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
 285         MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
 286 };
 287
 288 /* reg_sfgc_bridge_type
 289  * Access: Index
 290  *
 291  * Note: SwitchX-2 only supports 802.1Q mode.
 292  */
 293 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
 294
 295 enum mlxsw_flood_table_type {
 296         MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
 297         MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
 298         MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
 299         MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
 300         MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
 301 };
 302
 303 /* reg_sfgc_table_type
 304  * See mlxsw_flood_table_type
 305  * Access: RW
 306  *
 307  * Note: FID offset and FID types are not supported in SwitchX-2.
 308  */
 309 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
 310
 311 /* reg_sfgc_flood_table
 312  * Flooding table index to associate with the specific type on the specific
 313  * switch partition.
 314  * Access: RW
 315  */
 316 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
 317
 318 /* reg_sfgc_mid
 319  * The multicast ID for the swid. Not supported for Spectrum
 320  * Access: RW
 321  */
 322 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
 323
 324 /* reg_sfgc_counter_set_type
 325  * Counter Set Type for flow counters.
 326  * Access: RW
 327  */
 328 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
 329
 330 /* reg_sfgc_counter_index
 331  * Counter Index for flow counters.
 332  * Access: RW
 333  */
 334 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
 335
 336 static inline void
 337 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
 338                     enum mlxsw_reg_sfgc_bridge_type bridge_type,
 339                     enum mlxsw_flood_table_type table_type,
 340                     unsigned int flood_table)
 341 {
 342         MLXSW_REG_ZERO(sfgc, payload);
 343         mlxsw_reg_sfgc_type_set(payload, type);
 344         mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
 345         mlxsw_reg_sfgc_table_type_set(payload, table_type);
 346         mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
 347         mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
 348 }
 349
 350 /* SFTR - Switch Flooding Table Register
 351  * -------------------------------------
 352  * The switch flooding table is used for flooding packet replication. The table
 353  * defines a bit mask of ports for packet replication.
 354  */
 355 #define MLXSW_REG_SFTR_ID 0x2012
 356 #define MLXSW_REG_SFTR_LEN 0x420
 357
 358 static const struct mlxsw_reg_info mlxsw_reg_sftr = {
 359         .id = MLXSW_REG_SFTR_ID,
 360         .len = MLXSW_REG_SFTR_LEN,
 361 };
 362
 363 /* reg_sftr_swid
 364  * Switch partition ID with which to associate the port.
 365  * Access: Index
 366  */
 367 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
 368
 369 /* reg_sftr_flood_table
 370  * Flooding table index to associate with the specific type on the specific
 371  * switch partition.
 372  * Access: Index
 373  */
 374 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
 375
 376 /* reg_sftr_index
 377  * Index. Used as an index into the Flooding Table in case the table is
 378  * configured to use VID / FID or FID Offset.
 379  * Access: Index
 380  */
 381 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
 382
 383 /* reg_sftr_table_type
 384  * See mlxsw_flood_table_type
 385  * Access: RW
 386  */
 387 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
 388
 389 /* reg_sftr_range
 390  * Range of entries to update
 391  * Access: Index
 392  */
 393 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
 394
 395 /* reg_sftr_port
 396  * Local port membership (1 bit per port).
 397  * Access: RW
 398  */
 399 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
 400
 401 /* reg_sftr_cpu_port_mask
 402  * CPU port mask (1 bit per port).
 403  * Access: W
 404  */
 405 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
 406
 407 static inline void mlxsw_reg_sftr_pack(char *payload,
 408                                        unsigned int flood_table,
 409                                        unsigned int index,
 410                                        enum mlxsw_flood_table_type table_type,
 411                                        unsigned int range)
 412 {
 413         MLXSW_REG_ZERO(sftr, payload);
 414         mlxsw_reg_sftr_swid_set(payload, 0);
 415         mlxsw_reg_sftr_flood_table_set(payload, flood_table);
 416         mlxsw_reg_sftr_index_set(payload, index);
 417         mlxsw_reg_sftr_table_type_set(payload, table_type);
 418         mlxsw_reg_sftr_range_set(payload, range);
 419         mlxsw_reg_sftr_port_set(payload, MLXSW_PORT_CPU_PORT, 1);
 420         mlxsw_reg_sftr_port_mask_set(payload, MLXSW_PORT_CPU_PORT, 1);
 421 }
 422
 423 /* SPMLR - Switch Port MAC Learning Register
 424  * -----------------------------------------
 425  * Controls the Switch MAC learning policy per port.
 426  */
 427 #define MLXSW_REG_SPMLR_ID 0x2018
 428 #define MLXSW_REG_SPMLR_LEN 0x8
 429
 430 static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
 431         .id = MLXSW_REG_SPMLR_ID,
 432         .len = MLXSW_REG_SPMLR_LEN,
 433 };
 434
 435 /* reg_spmlr_local_port
 436  * Local port number.
 437  * Access: Index
 438  */
 439 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
 440
 441 /* reg_spmlr_sub_port
 442  * Virtual port within the physical port.
 443  * Should be set to 0 when virtual ports are not enabled on the port.
 444  * Access: Index
 445  */
 446 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
 447
 448 enum mlxsw_reg_spmlr_learn_mode {
 449         MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
 450         MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
 451         MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
 452 };
 453
 454 /* reg_spmlr_learn_mode
 455  * Learning mode on the port.
 456  * 0 - Learning disabled.
 457  * 2 - Learning enabled.
 458  * 3 - Security mode.
 459  *
 460  * In security mode the switch does not learn MACs on the port, but uses the
 461  * SMAC to see if it exists on another ingress port. If so, the packet is
 462  * classified as a bad packet and is discarded unless the software registers
 463  * to receive port security error packets usign HPKT.
 464  */
 465 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
 466
 467 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
 468                                         enum mlxsw_reg_spmlr_learn_mode mode)
 469 {
 470         MLXSW_REG_ZERO(spmlr, payload);
 471         mlxsw_reg_spmlr_local_port_set(payload, local_port);
 472         mlxsw_reg_spmlr_sub_port_set(payload, 0);
 473         mlxsw_reg_spmlr_learn_mode_set(payload, mode);
 474 }
 475
 476 /* PMLP - Ports Module to Local Port Register
 477  * ------------------------------------------
 478  * Configures the assignment of modules to local ports.
 479  */
 480 #define MLXSW_REG_PMLP_ID 0x5002
 481 #define MLXSW_REG_PMLP_LEN 0x40
 482
 483 static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
 484         .id = MLXSW_REG_PMLP_ID,
 485         .len = MLXSW_REG_PMLP_LEN,
 486 };
 487
 488 /* reg_pmlp_rxtx
 489  * 0 - Tx value is used for both Tx and Rx.
 490  * 1 - Rx value is taken from a separte field.
 491  * Access: RW
 492  */
 493 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
 494
 495 /* reg_pmlp_local_port
 496  * Local port number.
 497  * Access: Index
 498  */
 499 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
 500
 501 /* reg_pmlp_width
 502  * 0 - Unmap local port.
 503  * 1 - Lane 0 is used.
 504  * 2 - Lanes 0 and 1 are used.
 505  * 4 - Lanes 0, 1, 2 and 3 are used.
 506  * Access: RW
 507  */
 508 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
 509
 510 /* reg_pmlp_module
 511  * Module number.
 512  * Access: RW
 513  */
 514 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0, false);
 515
 516 /* reg_pmlp_tx_lane
 517  * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
 518  * Access: RW
 519  */
 520 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 16, false);
 521
 522 /* reg_pmlp_rx_lane
 523  * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
 524  * equal to Tx lane.
 525  * Access: RW
 526  */
 527 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 24, false);
 528
 529 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
 530 {
 531         MLXSW_REG_ZERO(pmlp, payload);
 532         mlxsw_reg_pmlp_local_port_set(payload, local_port);
 533 }
 534
 535 /* PMTU - Port MTU Register
 536  * ------------------------
 537  * Configures and reports the port MTU.
 538  */
 539 #define MLXSW_REG_PMTU_ID 0x5003
 540 #define MLXSW_REG_PMTU_LEN 0x10
 541
 542 static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
 543         .id = MLXSW_REG_PMTU_ID,
 544         .len = MLXSW_REG_PMTU_LEN,
 545 };
 546
 547 /* reg_pmtu_local_port
 548  * Local port number.
 549  * Access: Index
 550  */
 551 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
 552
 553 /* reg_pmtu_max_mtu
 554  * Maximum MTU.
 555  * When port type (e.g. Ethernet) is configured, the relevant MTU is
 556  * reported, otherwise the minimum between the max_mtu of the different
 557  * types is reported.
 558  * Access: RO
 559  */
 560 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
 561
 562 /* reg_pmtu_admin_mtu
 563  * MTU value to set port to. Must be smaller or equal to max_mtu.
 564  * Note: If port type is Infiniband, then port must be disabled, when its
 565  * MTU is set.
 566  * Access: RW
 567  */
 568 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
 569
 570 /* reg_pmtu_oper_mtu
 571  * The actual MTU configured on the port. Packets exceeding this size
 572  * will be dropped.
 573  * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
 574  * oper_mtu might be smaller than admin_mtu.
 575  * Access: RO
 576  */
 577 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
 578
 579 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
 580                                        u16 new_mtu)
 581 {
 582         MLXSW_REG_ZERO(pmtu, payload);
 583         mlxsw_reg_pmtu_local_port_set(payload, local_port);
 584         mlxsw_reg_pmtu_max_mtu_set(payload, 0);
 585         mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
 586         mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
 587 }
 588
 589 /* PTYS - Port Type and Speed Register
 590  * -----------------------------------
 591  * Configures and reports the port speed type.
 592  *
 593  * Note: When set while the link is up, the changes will not take effect
 594  * until the port transitions from down to up state.
 595  */
 596 #define MLXSW_REG_PTYS_ID 0x5004
 597 #define MLXSW_REG_PTYS_LEN 0x40
 598
 599 static const struct mlxsw_reg_info mlxsw_reg_ptys = {
 600         .id = MLXSW_REG_PTYS_ID,
 601         .len = MLXSW_REG_PTYS_LEN,
 602 };
 603
 604 /* reg_ptys_local_port
 605  * Local port number.
 606  * Access: Index
 607  */
 608 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
 609
 610 #define MLXSW_REG_PTYS_PROTO_MASK_ETH   BIT(2)
 611
 612 /* reg_ptys_proto_mask
 613  * Protocol mask. Indicates which protocol is used.
 614  * 0 - Infiniband.
 615  * 1 - Fibre Channel.
 616  * 2 - Ethernet.
 617  * Access: Index
 618  */
 619 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
 620
 621 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII                  BIT(0)
 622 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX            BIT(1)
 623 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4            BIT(2)
 624 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4            BIT(3)
 625 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR             BIT(4)
 626 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2            BIT(5)
 627 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4            BIT(6)
 628 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4            BIT(7)
 629 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4             BIT(8)
 630 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR             BIT(12)
 631 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR             BIT(13)
 632 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR          BIT(14)
 633 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4            BIT(15)
 634 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4        BIT(16)
 635 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4            BIT(19)
 636 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4           BIT(20)
 637 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4           BIT(21)
 638 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4           BIT(22)
 639 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4       BIT(23)
 640 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX             BIT(24)
 641 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T              BIT(25)
 642 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T              BIT(26)
 643 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR             BIT(27)
 644 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR             BIT(28)
 645 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR             BIT(29)
 646 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2            BIT(30)
 647 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2            BIT(31)
 648
 649 /* reg_ptys_eth_proto_cap
 650  * Ethernet port supported speeds and protocols.
 651  * Access: RO
 652  */
 653 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
 654
 655 /* reg_ptys_eth_proto_admin
 656  * Speed and protocol to set port to.
 657  * Access: RW
 658  */
 659 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
 660
 661 /* reg_ptys_eth_proto_oper
 662  * The current speed and protocol configured for the port.
 663  * Access: RO
 664  */
 665 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
 666
 667 static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
 668                                        u32 proto_admin)
 669 {
 670         MLXSW_REG_ZERO(ptys, payload);
 671         mlxsw_reg_ptys_local_port_set(payload, local_port);
 672         mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
 673         mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
 674 }
 675
 676 static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
 677                                          u32 *p_eth_proto_adm,
 678                                          u32 *p_eth_proto_oper)
 679 {
 680         if (p_eth_proto_cap)
 681                 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
 682         if (p_eth_proto_adm)
 683                 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
 684         if (p_eth_proto_oper)
 685                 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
 686 }
 687
 688 /* PPAD - Port Physical Address Register
 689  * -------------------------------------
 690  * The PPAD register configures the per port physical MAC address.
 691  */
 692 #define MLXSW_REG_PPAD_ID 0x5005
 693 #define MLXSW_REG_PPAD_LEN 0x10
 694
 695 static const struct mlxsw_reg_info mlxsw_reg_ppad = {
 696         .id = MLXSW_REG_PPAD_ID,
 697         .len = MLXSW_REG_PPAD_LEN,
 698 };
 699
 700 /* reg_ppad_single_base_mac
 701  * 0: base_mac, local port should be 0 and mac[7:0] is
 702  * reserved. HW will set incremental
 703  * 1: single_mac - mac of the local_port
 704  * Access: RW
 705  */
 706 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
 707
 708 /* reg_ppad_local_port
 709  * port number, if single_base_mac = 0 then local_port is reserved
 710  * Access: RW
 711  */
 712 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
 713
 714 /* reg_ppad_mac
 715  * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
 716  * If single_base_mac = 1 - the per port MAC address
 717  * Access: RW
 718  */
 719 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
 720
 721 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
 722                                        u8 local_port)
 723 {
 724         MLXSW_REG_ZERO(ppad, payload);
 725         mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
 726         mlxsw_reg_ppad_local_port_set(payload, local_port);
 727 }
 728
 729 /* PAOS - Ports Administrative and Operational Status Register
 730  * -----------------------------------------------------------
 731  * Configures and retrieves per port administrative and operational status.
 732  */
 733 #define MLXSW_REG_PAOS_ID 0x5006
 734 #define MLXSW_REG_PAOS_LEN 0x10
 735
 736 static const struct mlxsw_reg_info mlxsw_reg_paos = {
 737         .id = MLXSW_REG_PAOS_ID,
 738         .len = MLXSW_REG_PAOS_LEN,
 739 };
 740
 741 /* reg_paos_swid
 742  * Switch partition ID with which to associate the port.
 743  * Note: while external ports uses unique local port numbers (and thus swid is
 744  * redundant), router ports use the same local port number where swid is the
 745  * only indication for the relevant port.
 746  * Access: Index
 747  */
 748 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
 749
 750 /* reg_paos_local_port
 751  * Local port number.
 752  * Access: Index
 753  */
 754 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
 755
 756 /* reg_paos_admin_status
 757  * Port administrative state (the desired state of the port):
 758  * 1 - Up.
 759  * 2 - Down.
 760  * 3 - Up once. This means that in case of link failure, the port won't go
 761  *     into polling mode, but will wait to be re-enabled by software.
 762  * 4 - Disabled by system. Can only be set by hardware.
 763  * Access: RW
 764  */
 765 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
 766
 767 /* reg_paos_oper_status
 768  * Port operational state (the current state):
 769  * 1 - Up.
 770  * 2 - Down.
 771  * 3 - Down by port failure. This means that the device will not let the
 772  *     port up again until explicitly specified by software.
 773  * Access: RO
 774  */
 775 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
 776
 777 /* reg_paos_ase
 778  * Admin state update enabled.
 779  * Access: WO
 780  */
 781 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
 782
 783 /* reg_paos_ee
 784  * Event update enable. If this bit is set, event generation will be
 785  * updated based on the e field.
 786  * Access: WO
 787  */
 788 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
 789
 790 /* reg_paos_e
 791  * Event generation on operational state change:
 792  * 0 - Do not generate event.
 793  * 1 - Generate Event.
 794  * 2 - Generate Single Event.
 795  * Access: RW
 796  */
 797 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
 798
 799 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
 800                                        enum mlxsw_port_admin_status status)
 801 {
 802         MLXSW_REG_ZERO(paos, payload);
 803         mlxsw_reg_paos_swid_set(payload, 0);
 804         mlxsw_reg_paos_local_port_set(payload, local_port);
 805         mlxsw_reg_paos_admin_status_set(payload, status);
 806         mlxsw_reg_paos_oper_status_set(payload, 0);
 807         mlxsw_reg_paos_ase_set(payload, 1);
 808         mlxsw_reg_paos_ee_set(payload, 1);
 809         mlxsw_reg_paos_e_set(payload, 1);
 810 }
 811
 812 /* PPCNT - Ports Performance Counters Register
 813  * -------------------------------------------
 814  * The PPCNT register retrieves per port performance counters.
 815  */
 816 #define MLXSW_REG_PPCNT_ID 0x5008
 817 #define MLXSW_REG_PPCNT_LEN 0x100
 818
 819 static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
 820         .id = MLXSW_REG_PPCNT_ID,
 821         .len = MLXSW_REG_PPCNT_LEN,
 822 };
 823
 824 /* reg_ppcnt_swid
 825  * For HCA: must be always 0.
 826  * Switch partition ID to associate port with.
 827  * Switch partitions are numbered from 0 to 7 inclusively.
 828  * Switch partition 254 indicates stacking ports.
 829  * Switch partition 255 indicates all switch partitions.
 830  * Only valid on Set() operation with local_port=255.
 831  * Access: Index
 832  */
 833 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
 834
 835 /* reg_ppcnt_local_port
 836  * Local port number.
 837  * 255 indicates all ports on the device, and is only allowed
 838  * for Set() operation.
 839  * Access: Index
 840  */
 841 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
 842
 843 /* reg_ppcnt_pnat
 844  * Port number access type:
 845  * 0 - Local port number
 846  * 1 - IB port number
 847  * Access: Index
 848  */
 849 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
 850
 851 /* reg_ppcnt_grp
 852  * Performance counter group.
 853  * Group 63 indicates all groups. Only valid on Set() operation with
 854  * clr bit set.
 855  * 0x0: IEEE 802.3 Counters
 856  * 0x1: RFC 2863 Counters
 857  * 0x2: RFC 2819 Counters
 858  * 0x3: RFC 3635 Counters
 859  * 0x5: Ethernet Extended Counters
 860  * 0x8: Link Level Retransmission Counters
 861  * 0x10: Per Priority Counters
 862  * 0x11: Per Traffic Class Counters
 863  * 0x12: Physical Layer Counters
 864  * Access: Index
 865  */
 866 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
 867
 868 /* reg_ppcnt_clr
 869  * Clear counters. Setting the clr bit will reset the counter value
 870  * for all counters in the counter group. This bit can be set
 871  * for both Set() and Get() operation.
 872  * Access: OP
 873  */
 874 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
 875
 876 /* reg_ppcnt_prio_tc
 877  * Priority for counter set that support per priority, valid values: 0-7.
 878  * Traffic class for counter set that support per traffic class,
 879  * valid values: 0- cap_max_tclass-1 .
 880  * For HCA: cap_max_tclass is always 8.
 881  * Otherwise must be 0.
 882  * Access: Index
 883  */
 884 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
 885
 886 /* reg_ppcnt_a_frames_transmitted_ok
 887  * Access: RO
 888  */
 889 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
 890              0x08 + 0x00, 0, 64);
 891
 892 /* reg_ppcnt_a_frames_received_ok
 893  * Access: RO
 894  */
 895 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
 896              0x08 + 0x08, 0, 64);
 897
 898 /* reg_ppcnt_a_frame_check_sequence_errors
 899  * Access: RO
 900  */
 901 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
 902              0x08 + 0x10, 0, 64);
 903
 904 /* reg_ppcnt_a_alignment_errors
 905  * Access: RO
 906  */
 907 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
 908              0x08 + 0x18, 0, 64);
 909
 910 /* reg_ppcnt_a_octets_transmitted_ok
 911  * Access: RO
 912  */
 913 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
 914              0x08 + 0x20, 0, 64);
 915
 916 /* reg_ppcnt_a_octets_received_ok
 917  * Access: RO
 918  */
 919 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
 920              0x08 + 0x28, 0, 64);
 921
 922 /* reg_ppcnt_a_multicast_frames_xmitted_ok
 923  * Access: RO
 924  */
 925 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
 926              0x08 + 0x30, 0, 64);
 927
 928 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
 929  * Access: RO
 930  */
 931 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
 932              0x08 + 0x38, 0, 64);
 933
 934 /* reg_ppcnt_a_multicast_frames_received_ok
 935  * Access: RO
 936  */
 937 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
 938              0x08 + 0x40, 0, 64);
 939
 940 /* reg_ppcnt_a_broadcast_frames_received_ok
 941  * Access: RO
 942  */
 943 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
 944              0x08 + 0x48, 0, 64);
 945
 946 /* reg_ppcnt_a_in_range_length_errors
 947  * Access: RO
 948  */
 949 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
 950              0x08 + 0x50, 0, 64);
 951
 952 /* reg_ppcnt_a_out_of_range_length_field
 953  * Access: RO
 954  */
 955 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
 956              0x08 + 0x58, 0, 64);
 957
 958 /* reg_ppcnt_a_frame_too_long_errors
 959  * Access: RO
 960  */
 961 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
 962              0x08 + 0x60, 0, 64);
 963
 964 /* reg_ppcnt_a_symbol_error_during_carrier
 965  * Access: RO
 966  */
 967 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
 968              0x08 + 0x68, 0, 64);
 969
 970 /* reg_ppcnt_a_mac_control_frames_transmitted
 971  * Access: RO
 972  */
 973 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
 974              0x08 + 0x70, 0, 64);
 975
 976 /* reg_ppcnt_a_mac_control_frames_received
 977  * Access: RO
 978  */
 979 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
 980              0x08 + 0x78, 0, 64);
 981
 982 /* reg_ppcnt_a_unsupported_opcodes_received
 983  * Access: RO
 984  */
 985 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
 986              0x08 + 0x80, 0, 64);
 987
 988 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
 989  * Access: RO
 990  */
 991 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
 992              0x08 + 0x88, 0, 64);
 993
 994 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
 995  * Access: RO
 996  */
 997 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
 998              0x08 + 0x90, 0, 64);
 999
1000 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port)
1001 {
1002         MLXSW_REG_ZERO(ppcnt, payload);
1003         mlxsw_reg_ppcnt_swid_set(payload, 0);
1004         mlxsw_reg_ppcnt_local_port_set(payload, local_port);
1005         mlxsw_reg_ppcnt_pnat_set(payload, 0);
1006         mlxsw_reg_ppcnt_grp_set(payload, 0);
1007         mlxsw_reg_ppcnt_clr_set(payload, 0);
1008         mlxsw_reg_ppcnt_prio_tc_set(payload, 0);
1009 }
1010
1011 /* PSPA - Port Switch Partition Allocation
1012  * ---------------------------------------
1013  * Controls the association of a port with a switch partition and enables
1014  * configuring ports as stacking ports.
1015  */
1016 #define MLXSW_REG_PSPA_ID 0x500d
1017 #define MLXSW_REG_PSPA_LEN 0x8
1018
1019 static const struct mlxsw_reg_info mlxsw_reg_pspa = {
1020         .id = MLXSW_REG_PSPA_ID,
1021         .len = MLXSW_REG_PSPA_LEN,
1022 };
1023
1024 /* reg_pspa_swid
1025  * Switch partition ID.
1026  * Access: RW
1027  */
1028 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
1029
1030 /* reg_pspa_local_port
1031  * Local port number.
1032  * Access: Index
1033  */
1034 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
1035
1036 /* reg_pspa_sub_port
1037  * Virtual port within the local port. Set to 0 when virtual ports are
1038  * disabled on the local port.
1039  * Access: Index
1040  */
1041 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
1042
1043 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
1044 {
1045         MLXSW_REG_ZERO(pspa, payload);
1046         mlxsw_reg_pspa_swid_set(payload, swid);
1047         mlxsw_reg_pspa_local_port_set(payload, local_port);
1048         mlxsw_reg_pspa_sub_port_set(payload, 0);
1049 }
1050
1051 /* HTGT - Host Trap Group Table
1052  * ----------------------------
1053  * Configures the properties for forwarding to CPU.
1054  */
1055 #define MLXSW_REG_HTGT_ID 0x7002
1056 #define MLXSW_REG_HTGT_LEN 0x100
1057
1058 static const struct mlxsw_reg_info mlxsw_reg_htgt = {
1059         .id = MLXSW_REG_HTGT_ID,
1060         .len = MLXSW_REG_HTGT_LEN,
1061 };
1062
1063 /* reg_htgt_swid
1064  * Switch partition ID.
1065  * Access: Index
1066  */
1067 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
1068
1069 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0      /* For locally attached CPU */
1070
1071 /* reg_htgt_type
1072  * CPU path type.
1073  * Access: RW
1074  */
1075 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
1076
1077 #define MLXSW_REG_HTGT_TRAP_GROUP_EMAD  0x0
1078 #define MLXSW_REG_HTGT_TRAP_GROUP_RX    0x1
1079
1080 /* reg_htgt_trap_group
1081  * Trap group number. User defined number specifying which trap groups
1082  * should be forwarded to the CPU. The mapping between trap IDs and trap
1083  * groups is configured using HPKT register.
1084  * Access: Index
1085  */
1086 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
1087
1088 enum {
1089         MLXSW_REG_HTGT_POLICER_DISABLE,
1090         MLXSW_REG_HTGT_POLICER_ENABLE,
1091 };
1092
1093 /* reg_htgt_pide
1094  * Enable policer ID specified using 'pid' field.
1095  * Access: RW
1096  */
1097 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
1098
1099 /* reg_htgt_pid
1100  * Policer ID for the trap group.
1101  * Access: RW
1102  */
1103 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
1104
1105 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
1106
1107 /* reg_htgt_mirror_action
1108  * Mirror action to use.
1109  * 0 - Trap to CPU.
1110  * 1 - Trap to CPU and mirror to a mirroring agent.
1111  * 2 - Mirror to a mirroring agent and do not trap to CPU.
1112  * Access: RW
1113  *
1114  * Note: Mirroring to a mirroring agent is only supported in Spectrum.
1115  */
1116 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
1117
1118 /* reg_htgt_mirroring_agent
1119  * Mirroring agent.
1120  * Access: RW
1121  */
1122 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
1123
1124 /* reg_htgt_priority
1125  * Trap group priority.
1126  * In case a packet matches multiple classification rules, the packet will
1127  * only be trapped once, based on the trap ID associated with the group (via
1128  * register HPKT) with the highest priority.
1129  * Supported values are 0-7, with 7 represnting the highest priority.
1130  * Access: RW
1131  *
1132  * Note: In SwitchX-2 this field is ignored and the priority value is replaced
1133  * by the 'trap_group' field.
1134  */
1135 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
1136
1137 /* reg_htgt_local_path_cpu_tclass
1138  * CPU ingress traffic class for the trap group.
1139  * Access: RW
1140  */
1141 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
1142
1143 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD      0x15
1144 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX        0x14
1145
1146 /* reg_htgt_local_path_rdq
1147  * Receive descriptor queue (RDQ) to use for the trap group.
1148  * Access: RW
1149  */
1150 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
1151
1152 static inline void mlxsw_reg_htgt_pack(char *payload, u8 trap_group)
1153 {
1154         u8 swid, rdq;
1155
1156         MLXSW_REG_ZERO(htgt, payload);
1157         if (MLXSW_REG_HTGT_TRAP_GROUP_EMAD == trap_group) {
1158                 swid = MLXSW_PORT_SWID_ALL_SWIDS;
1159                 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
1160         } else {
1161                 swid = 0;
1162                 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
1163         }
1164         mlxsw_reg_htgt_swid_set(payload, swid);
1165         mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
1166         mlxsw_reg_htgt_trap_group_set(payload, trap_group);
1167         mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
1168         mlxsw_reg_htgt_pid_set(payload, 0);
1169         mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
1170         mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
1171         mlxsw_reg_htgt_priority_set(payload, 0);
1172         mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
1173         mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
1174 }
1175
1176 /* HPKT - Host Packet Trap
1177  * -----------------------
1178  * Configures trap IDs inside trap groups.
1179  */
1180 #define MLXSW_REG_HPKT_ID 0x7003
1181 #define MLXSW_REG_HPKT_LEN 0x10
1182
1183 static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
1184         .id = MLXSW_REG_HPKT_ID,
1185         .len = MLXSW_REG_HPKT_LEN,
1186 };
1187
1188 enum {
1189         MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
1190         MLXSW_REG_HPKT_ACK_REQUIRED,
1191 };
1192
1193 /* reg_hpkt_ack
1194  * Require acknowledgements from the host for events.
1195  * If set, then the device will wait for the event it sent to be acknowledged
1196  * by the host. This option is only relevant for event trap IDs.
1197  * Access: RW
1198  *
1199  * Note: Currently not supported by firmware.
1200  */
1201 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
1202
1203 enum mlxsw_reg_hpkt_action {
1204         MLXSW_REG_HPKT_ACTION_FORWARD,
1205         MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
1206         MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
1207         MLXSW_REG_HPKT_ACTION_DISCARD,
1208         MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
1209         MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
1210 };
1211
1212 /* reg_hpkt_action
1213  * Action to perform on packet when trapped.
1214  * 0 - No action. Forward to CPU based on switching rules.
1215  * 1 - Trap to CPU (CPU receives sole copy).
1216  * 2 - Mirror to CPU (CPU receives a replica of the packet).
1217  * 3 - Discard.
1218  * 4 - Soft discard (allow other traps to act on the packet).
1219  * 5 - Trap and soft discard (allow other traps to overwrite this trap).
1220  * Access: RW
1221  *
1222  * Note: Must be set to 0 (forward) for event trap IDs, as they are already
1223  * addressed to the CPU.
1224  */
1225 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
1226
1227 /* reg_hpkt_trap_group
1228  * Trap group to associate the trap with.
1229  * Access: RW
1230  */
1231 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
1232
1233 /* reg_hpkt_trap_id
1234  * Trap ID.
1235  * Access: Index
1236  *
1237  * Note: A trap ID can only be associated with a single trap group. The device
1238  * will associate the trap ID with the last trap group configured.
1239  */
1240 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
1241
1242 enum {
1243         MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
1244         MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
1245         MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
1246 };
1247
1248 /* reg_hpkt_ctrl
1249  * Configure dedicated buffer resources for control packets.
1250  * 0 - Keep factory defaults.
1251  * 1 - Do not use control buffer for this trap ID.
1252  * 2 - Use control buffer for this trap ID.
1253  * Access: RW
1254  */
1255 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
1256
1257 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action,
1258                                        u8 trap_group, u16 trap_id)
1259 {
1260         MLXSW_REG_ZERO(hpkt, payload);
1261         mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
1262         mlxsw_reg_hpkt_action_set(payload, action);
1263         mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
1264         mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
1265         mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
1266 }
1267
1268 static inline const char *mlxsw_reg_id_str(u16 reg_id)
1269 {
1270         switch (reg_id) {
1271         case MLXSW_REG_SGCR_ID:
1272                 return "SGCR";
1273         case MLXSW_REG_SPAD_ID:
1274                 return "SPAD";
1275         case MLXSW_REG_SMID_ID:
1276                 return "SMID";
1277         case MLXSW_REG_SSPR_ID:
1278                 return "SSPR";
1279         case MLXSW_REG_SPMS_ID:
1280                 return "SPMS";
1281         case MLXSW_REG_SFGC_ID:
1282                 return "SFGC";
1283         case MLXSW_REG_SFTR_ID:
1284                 return "SFTR";
1285         case MLXSW_REG_SPMLR_ID:
1286                 return "SPMLR";
1287         case MLXSW_REG_PMLP_ID:
1288                 return "PMLP";
1289         case MLXSW_REG_PMTU_ID:
1290                 return "PMTU";
1291         case MLXSW_REG_PTYS_ID:
1292                 return "PTYS";
1293         case MLXSW_REG_PPAD_ID:
1294                 return "PPAD";
1295         case MLXSW_REG_PAOS_ID:
1296                 return "PAOS";
1297         case MLXSW_REG_PPCNT_ID:
1298                 return "PPCNT";
1299         case MLXSW_REG_PSPA_ID:
1300                 return "PSPA";
1301         case MLXSW_REG_HTGT_ID:
1302                 return "HTGT";
1303         case MLXSW_REG_HPKT_ID:
1304                 return "HPKT";
1305         default:
1306                 return "*UNKNOWN*";
1307         }
1308 }
1309
1310 /* PUDE - Port Up / Down Event
1311  * ---------------------------
1312  * Reports the operational state change of a port.
1313  */
1314 #define MLXSW_REG_PUDE_LEN 0x10
1315
1316 /* reg_pude_swid
1317  * Switch partition ID with which to associate the port.
1318  * Access: Index
1319  */
1320 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
1321
1322 /* reg_pude_local_port
1323  * Local port number.
1324  * Access: Index
1325  */
1326 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
1327
1328 /* reg_pude_admin_status
1329  * Port administrative state (the desired state).
1330  * 1 - Up.
1331  * 2 - Down.
1332  * 3 - Up once. This means that in case of link failure, the port won't go
1333  *     into polling mode, but will wait to be re-enabled by software.
1334  * 4 - Disabled by system. Can only be set by hardware.
1335  * Access: RO
1336  */
1337 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
1338
1339 /* reg_pude_oper_status
1340  * Port operatioanl state.
1341  * 1 - Up.
1342  * 2 - Down.
1343  * 3 - Down by port failure. This means that the device will not let the
1344  *     port up again until explicitly specified by software.
1345  * Access: RO
1346  */
1347 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
1348
1349 #endif