projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'bind_unbind' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include "eswitch.h"
39 #include "en.h"
40 #include "en_tc.h"
41 #include "en_rep.h"
42 #include "vxlan.h"
43
44 struct mlx5e_rq_param {
45 u32 rqc[MLX5_ST_SZ_DW(rqc)];
46 struct mlx5_wq_param wq;
47 };
48
49 struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
52 };
53
54 struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
57 u16 eq_ix;
58 u8 cq_period_mode;
59 };
60
61 struct mlx5e_channel_param {
62 struct mlx5e_rq_param rq;
63 struct mlx5e_sq_param sq;
64 struct mlx5e_sq_param xdp_sq;
65 struct mlx5e_sq_param icosq;
66 struct mlx5e_cq_param rx_cq;
67 struct mlx5e_cq_param tx_cq;
68 struct mlx5e_cq_param icosq_cq;
69 };
70
71 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
72 {
73 return MLX5_CAP_GEN(mdev, striding_rq) &&
74 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
75 MLX5_CAP_ETH(mdev, reg_umr_sq);
76 }
77
78 void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
79 struct mlx5e_params *params, u8 rq_type)
80 {
81 params->rq_wq_type = rq_type;
82 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
83 switch (params->rq_wq_type) {
84 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
85 params->log_rq_size = is_kdump_kernel() ?
86 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
87 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
88 params->mpwqe_log_stride_sz =
89 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
90 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
91 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
92 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
93 params->mpwqe_log_stride_sz;
94 break;
95 default: /* MLX5_WQ_TYPE_LINKED_LIST */
96 params->log_rq_size = is_kdump_kernel() ?
97 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
98 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
99
100 /* Extra room needed for build_skb */
101 params->lro_wqe_sz -= MLX5_RX_HEADROOM +
102 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
103 }
104
105 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
106 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
107 BIT(params->log_rq_size),
108 BIT(params->mpwqe_log_stride_sz),
109 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
110 }
111
112 static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
113 {
114 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
115 !params->xdp_prog ?
116 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
117 MLX5_WQ_TYPE_LINKED_LIST;
118 mlx5e_set_rq_type_params(mdev, params, rq_type);
119 }
120
121 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
122 {
123 struct mlx5_core_dev *mdev = priv->mdev;
124 u8 port_state;
125
126 port_state = mlx5_query_vport_state(mdev,
127 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
128
129 if (port_state == VPORT_STATE_UP) {
130 netdev_info(priv->netdev, "Link up\n");
131 netif_carrier_on(priv->netdev);
132 } else {
133 netdev_info(priv->netdev, "Link down\n");
134 netif_carrier_off(priv->netdev);
135 }
136 }
137
138 static void mlx5e_update_carrier_work(struct work_struct *work)
139 {
140 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
141 update_carrier_work);
142
143 mutex_lock(&priv->state_lock);
144 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
145 mlx5e_update_carrier(priv);
146 mutex_unlock(&priv->state_lock);
147 }
148
149 static void mlx5e_tx_timeout_work(struct work_struct *work)
150 {
151 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
152 tx_timeout_work);
153 int err;
154
155 rtnl_lock();
156 mutex_lock(&priv->state_lock);
157 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
158 goto unlock;
159 mlx5e_close_locked(priv->netdev);
160 err = mlx5e_open_locked(priv->netdev);
161 if (err)
162 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
163 err);
164 unlock:
165 mutex_unlock(&priv->state_lock);
166 rtnl_unlock();
167 }
168
169 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
170 {
171 struct mlx5e_sw_stats temp, *s = &temp;
172 struct mlx5e_rq_stats *rq_stats;
173 struct mlx5e_sq_stats *sq_stats;
174 u64 tx_offload_none = 0;
175 int i, j;
176
177 memset(s, 0, sizeof(*s));
178 for (i = 0; i < priv->channels.num; i++) {
179 struct mlx5e_channel *c = priv->channels.c[i];
180
181 rq_stats = &c->rq.stats;
182
183 s->rx_packets += rq_stats->packets;
184 s->rx_bytes += rq_stats->bytes;
185 s->rx_lro_packets += rq_stats->lro_packets;
186 s->rx_lro_bytes += rq_stats->lro_bytes;
187 s->rx_csum_none += rq_stats->csum_none;
188 s->rx_csum_complete += rq_stats->csum_complete;
189 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
190 s->rx_xdp_drop += rq_stats->xdp_drop;
191 s->rx_xdp_tx += rq_stats->xdp_tx;
192 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
193 s->rx_wqe_err += rq_stats->wqe_err;
194 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
195 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
196 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
197 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
198 s->rx_cache_reuse += rq_stats->cache_reuse;
199 s->rx_cache_full += rq_stats->cache_full;
200 s->rx_cache_empty += rq_stats->cache_empty;
201 s->rx_cache_busy += rq_stats->cache_busy;
202
203 for (j = 0; j < priv->channels.params.num_tc; j++) {
204 sq_stats = &c->sq[j].stats;
205
206 s->tx_packets += sq_stats->packets;
207 s->tx_bytes += sq_stats->bytes;
208 s->tx_tso_packets += sq_stats->tso_packets;
209 s->tx_tso_bytes += sq_stats->tso_bytes;
210 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
211 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
212 s->tx_queue_stopped += sq_stats->stopped;
213 s->tx_queue_wake += sq_stats->wake;
214 s->tx_queue_dropped += sq_stats->dropped;
215 s->tx_xmit_more += sq_stats->xmit_more;
216 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
217 tx_offload_none += sq_stats->csum_none;
218 }
219 }
220
221 /* Update calculated offload counters */
222 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
223 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
224
225 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
226 priv->stats.pport.phy_counters,
227 counter_set.phys_layer_cntrs.link_down_events);
228 memcpy(&priv->stats.sw, s, sizeof(*s));
229 }
230
231 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
232 {
233 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
234 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
235 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
236 struct mlx5_core_dev *mdev = priv->mdev;
237
238 MLX5_SET(query_vport_counter_in, in, opcode,
239 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
240 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
241 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
242
243 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
244 }
245
246 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
247 {
248 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
249 struct mlx5_core_dev *mdev = priv->mdev;
250 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
251 int prio;
252 void *out;
253 u32 *in;
254
255 in = mlx5_vzalloc(sz);
256 if (!in)
257 goto free_out;
258
259 MLX5_SET(ppcnt_reg, in, local_port, 1);
260
261 out = pstats->IEEE_802_3_counters;
262 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
263 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
264
265 out = pstats->RFC_2863_counters;
266 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
267 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
268
269 out = pstats->RFC_2819_counters;
270 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
271 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
272
273 out = pstats->phy_counters;
274 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
275 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
276
277 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
278 out = pstats->phy_statistical_counters;
279 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
280 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
281 }
282
283 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
284 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
285 out = pstats->per_prio_counters[prio];
286 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
287 mlx5_core_access_reg(mdev, in, sz, out, sz,
288 MLX5_REG_PPCNT, 0, 0);
289 }
290
291 free_out:
292 kvfree(in);
293 }
294
295 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
296 {
297 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
298
299 if (!priv->q_counter)
300 return;
301
302 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
303 &qcnt->rx_out_of_buffer);
304 }
305
306 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
307 {
308 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
309 struct mlx5_core_dev *mdev = priv->mdev;
310 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
311 void *out;
312 u32 *in;
313
314 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
315 return;
316
317 in = mlx5_vzalloc(sz);
318 if (!in)
319 return;
320
321 out = pcie_stats->pcie_perf_counters;
322 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
323 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
324
325 kvfree(in);
326 }
327
328 void mlx5e_update_stats(struct mlx5e_priv *priv)
329 {
330 mlx5e_update_pcie_counters(priv);
331 mlx5e_update_pport_counters(priv);
332 mlx5e_update_vport_counters(priv);
333 mlx5e_update_q_counter(priv);
334 mlx5e_update_sw_counters(priv);
335 }
336
337 void mlx5e_update_stats_work(struct work_struct *work)
338 {
339 struct delayed_work *dwork = to_delayed_work(work);
340 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
341 update_stats_work);
342 mutex_lock(&priv->state_lock);
343 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
344 priv->profile->update_stats(priv);
345 queue_delayed_work(priv->wq, dwork,
346 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
347 }
348 mutex_unlock(&priv->state_lock);
349 }
350
351 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
352 enum mlx5_dev_event event, unsigned long param)
353 {
354 struct mlx5e_priv *priv = vpriv;
355 struct ptp_clock_event ptp_event;
356 struct mlx5_eqe *eqe = NULL;
357
358 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
359 return;
360
361 switch (event) {
362 case MLX5_DEV_EVENT_PORT_UP:
363 case MLX5_DEV_EVENT_PORT_DOWN:
364 queue_work(priv->wq, &priv->update_carrier_work);
365 break;
366 case MLX5_DEV_EVENT_PPS:
367 eqe = (struct mlx5_eqe *)param;
368 ptp_event.type = PTP_CLOCK_EXTTS;
369 ptp_event.index = eqe->data.pps.pin;
370 ptp_event.timestamp =
371 timecounter_cyc2time(&priv->tstamp.clock,
372 be64_to_cpu(eqe->data.pps.time_stamp));
373 mlx5e_pps_event_handler(vpriv, &ptp_event);
374 break;
375 default:
376 break;
377 }
378 }
379
380 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
381 {
382 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
383 }
384
385 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
386 {
387 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
388 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
389 }
390
391 static inline int mlx5e_get_wqe_mtt_sz(void)
392 {
393 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
394 * To avoid copying garbage after the mtt array, we allocate
395 * a little more.
396 */
397 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
398 MLX5_UMR_MTT_ALIGNMENT);
399 }
400
401 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
402 struct mlx5e_icosq *sq,
403 struct mlx5e_umr_wqe *wqe,
404 u16 ix)
405 {
406 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
407 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
408 struct mlx5_wqe_data_seg *dseg = &wqe->data;
409 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
410 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
411 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
412
413 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
414 ds_cnt);
415 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
416 cseg->imm = rq->mkey_be;
417
418 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
419 ucseg->xlt_octowords =
420 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
421 ucseg->bsf_octowords =
422 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
423 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
424
425 dseg->lkey = sq->mkey_be;
426 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
427 }
428
429 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
430 struct mlx5e_channel *c)
431 {
432 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
433 int mtt_sz = mlx5e_get_wqe_mtt_sz();
434 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
435 int i;
436
437 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
438 GFP_KERNEL, cpu_to_node(c->cpu));
439 if (!rq->mpwqe.info)
440 goto err_out;
441
442 /* We allocate more than mtt_sz as we will align the pointer */
443 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
444 cpu_to_node(c->cpu));
445 if (unlikely(!rq->mpwqe.mtt_no_align))
446 goto err_free_wqe_info;
447
448 for (i = 0; i < wq_sz; i++) {
449 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
450
451 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
452 MLX5_UMR_ALIGN);
453 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
454 PCI_DMA_TODEVICE);
455 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
456 goto err_unmap_mtts;
457
458 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
459 }
460
461 return 0;
462
463 err_unmap_mtts:
464 while (--i >= 0) {
465 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
466
467 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
468 PCI_DMA_TODEVICE);
469 }
470 kfree(rq->mpwqe.mtt_no_align);
471 err_free_wqe_info:
472 kfree(rq->mpwqe.info);
473
474 err_out:
475 return -ENOMEM;
476 }
477
478 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
479 {
480 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
481 int mtt_sz = mlx5e_get_wqe_mtt_sz();
482 int i;
483
484 for (i = 0; i < wq_sz; i++) {
485 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
486
487 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
488 PCI_DMA_TODEVICE);
489 }
490 kfree(rq->mpwqe.mtt_no_align);
491 kfree(rq->mpwqe.info);
492 }
493
494 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
495 u64 npages, u8 page_shift,
496 struct mlx5_core_mkey *umr_mkey)
497 {
498 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
499 void *mkc;
500 u32 *in;
501 int err;
502
503 if (!MLX5E_VALID_NUM_MTTS(npages))
504 return -EINVAL;
505
506 in = mlx5_vzalloc(inlen);
507 if (!in)
508 return -ENOMEM;
509
510 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
511
512 MLX5_SET(mkc, mkc, free, 1);
513 MLX5_SET(mkc, mkc, umr_en, 1);
514 MLX5_SET(mkc, mkc, lw, 1);
515 MLX5_SET(mkc, mkc, lr, 1);
516 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
517
518 MLX5_SET(mkc, mkc, qpn, 0xffffff);
519 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
520 MLX5_SET64(mkc, mkc, len, npages << page_shift);
521 MLX5_SET(mkc, mkc, translations_octword_size,
522 MLX5_MTT_OCTW(npages));
523 MLX5_SET(mkc, mkc, log_page_size, page_shift);
524
525 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
526
527 kvfree(in);
528 return err;
529 }
530
531 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
532 {
533 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
534
535 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
536 }
537
538 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
539 struct mlx5e_params *params,
540 struct mlx5e_rq_param *rqp,
541 struct mlx5e_rq *rq)
542 {
543 struct mlx5_core_dev *mdev = c->mdev;
544 void *rqc = rqp->rqc;
545 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
546 u32 byte_count;
547 u32 frag_sz;
548 int npages;
549 int wq_sz;
550 int err;
551 int i;
552
553 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
554
555 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
556 &rq->wq_ctrl);
557 if (err)
558 return err;
559
560 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
561
562 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
563
564 rq->wq_type = params->rq_wq_type;
565 rq->pdev = c->pdev;
566 rq->netdev = c->netdev;
567 rq->tstamp = c->tstamp;
568 rq->channel = c;
569 rq->ix = c->ix;
570 rq->mdev = mdev;
571
572 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
573 if (IS_ERR(rq->xdp_prog)) {
574 err = PTR_ERR(rq->xdp_prog);
575 rq->xdp_prog = NULL;
576 goto err_rq_wq_destroy;
577 }
578
579 if (rq->xdp_prog) {
580 rq->buff.map_dir = DMA_BIDIRECTIONAL;
581 rq->rx_headroom = XDP_PACKET_HEADROOM;
582 } else {
583 rq->buff.map_dir = DMA_FROM_DEVICE;
584 rq->rx_headroom = MLX5_RX_HEADROOM;
585 }
586
587 switch (rq->wq_type) {
588 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
589
590 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
591 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
592
593 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
594 if (!rq->handle_rx_cqe) {
595 err = -EINVAL;
596 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
597 goto err_rq_wq_destroy;
598 }
599
600 rq->mpwqe_stride_sz = BIT(params->mpwqe_log_stride_sz);
601 rq->mpwqe_num_strides = BIT(params->mpwqe_log_num_strides);
602
603 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
604 byte_count = rq->buff.wqe_sz;
605
606 err = mlx5e_create_rq_umr_mkey(mdev, rq);
607 if (err)
608 goto err_rq_wq_destroy;
609 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
610
611 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
612 if (err)
613 goto err_destroy_umr_mkey;
614 break;
615 default: /* MLX5_WQ_TYPE_LINKED_LIST */
616 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
617 GFP_KERNEL, cpu_to_node(c->cpu));
618 if (!rq->dma_info) {
619 err = -ENOMEM;
620 goto err_rq_wq_destroy;
621 }
622 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
623 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
624
625 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
626 if (!rq->handle_rx_cqe) {
627 kfree(rq->dma_info);
628 err = -EINVAL;
629 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
630 goto err_rq_wq_destroy;
631 }
632
633 rq->buff.wqe_sz = params->lro_en ?
634 params->lro_wqe_sz :
635 MLX5E_SW2HW_MTU(c->netdev->mtu);
636 byte_count = rq->buff.wqe_sz;
637
638 /* calc the required page order */
639 frag_sz = rq->rx_headroom +
640 byte_count /* packet data */ +
641 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
642 frag_sz = SKB_DATA_ALIGN(frag_sz);
643
644 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
645 rq->buff.page_order = order_base_2(npages);
646
647 byte_count |= MLX5_HW_START_PADDING;
648 rq->mkey_be = c->mkey_be;
649 }
650
651 for (i = 0; i < wq_sz; i++) {
652 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
653
654 wqe->data.byte_count = cpu_to_be32(byte_count);
655 wqe->data.lkey = rq->mkey_be;
656 }
657
658 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
659 rq->am.mode = params->rx_cq_period_mode;
660 rq->page_cache.head = 0;
661 rq->page_cache.tail = 0;
662
663 return 0;
664
665 err_destroy_umr_mkey:
666 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
667
668 err_rq_wq_destroy:
669 if (rq->xdp_prog)
670 bpf_prog_put(rq->xdp_prog);
671 mlx5_wq_destroy(&rq->wq_ctrl);
672
673 return err;
674 }
675
676 static void mlx5e_free_rq(struct mlx5e_rq *rq)
677 {
678 int i;
679
680 if (rq->xdp_prog)
681 bpf_prog_put(rq->xdp_prog);
682
683 switch (rq->wq_type) {
684 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
685 mlx5e_rq_free_mpwqe_info(rq);
686 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
687 break;
688 default: /* MLX5_WQ_TYPE_LINKED_LIST */
689 kfree(rq->dma_info);
690 }
691
692 for (i = rq->page_cache.head; i != rq->page_cache.tail;
693 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
694 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
695
696 mlx5e_page_release(rq, dma_info, false);
697 }
698 mlx5_wq_destroy(&rq->wq_ctrl);
699 }
700
701 static int mlx5e_create_rq(struct mlx5e_rq *rq,
702 struct mlx5e_rq_param *param)
703 {
704 struct mlx5_core_dev *mdev = rq->mdev;
705
706 void *in;
707 void *rqc;
708 void *wq;
709 int inlen;
710 int err;
711
712 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
713 sizeof(u64) * rq->wq_ctrl.buf.npages;
714 in = mlx5_vzalloc(inlen);
715 if (!in)
716 return -ENOMEM;
717
718 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
719 wq = MLX5_ADDR_OF(rqc, rqc, wq);
720
721 memcpy(rqc, param->rqc, sizeof(param->rqc));
722
723 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
724 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
725 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
726 MLX5_ADAPTER_PAGE_SHIFT);
727 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
728
729 mlx5_fill_page_array(&rq->wq_ctrl.buf,
730 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
731
732 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
733
734 kvfree(in);
735
736 return err;
737 }
738
739 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
740 int next_state)
741 {
742 struct mlx5e_channel *c = rq->channel;
743 struct mlx5_core_dev *mdev = c->mdev;
744
745 void *in;
746 void *rqc;
747 int inlen;
748 int err;
749
750 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
751 in = mlx5_vzalloc(inlen);
752 if (!in)
753 return -ENOMEM;
754
755 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
756
757 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
758 MLX5_SET(rqc, rqc, state, next_state);
759
760 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
761
762 kvfree(in);
763
764 return err;
765 }
766
767 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
768 {
769 struct mlx5e_channel *c = rq->channel;
770 struct mlx5e_priv *priv = c->priv;
771 struct mlx5_core_dev *mdev = priv->mdev;
772
773 void *in;
774 void *rqc;
775 int inlen;
776 int err;
777
778 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
779 in = mlx5_vzalloc(inlen);
780 if (!in)
781 return -ENOMEM;
782
783 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
784
785 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
786 MLX5_SET64(modify_rq_in, in, modify_bitmask,
787 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
788 MLX5_SET(rqc, rqc, scatter_fcs, enable);
789 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
790
791 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
792
793 kvfree(in);
794
795 return err;
796 }
797
798 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
799 {
800 struct mlx5e_channel *c = rq->channel;
801 struct mlx5_core_dev *mdev = c->mdev;
802 void *in;
803 void *rqc;
804 int inlen;
805 int err;
806
807 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
808 in = mlx5_vzalloc(inlen);
809 if (!in)
810 return -ENOMEM;
811
812 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
813
814 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
815 MLX5_SET64(modify_rq_in, in, modify_bitmask,
816 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
817 MLX5_SET(rqc, rqc, vsd, vsd);
818 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
819
820 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
821
822 kvfree(in);
823
824 return err;
825 }
826
827 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
828 {
829 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
830 }
831
832 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
833 {
834 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
835 struct mlx5e_channel *c = rq->channel;
836
837 struct mlx5_wq_ll *wq = &rq->wq;
838 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
839
840 while (time_before(jiffies, exp_time)) {
841 if (wq->cur_sz >= min_wqes)
842 return 0;
843
844 msleep(20);
845 }
846
847 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
848 rq->rqn, wq->cur_sz, min_wqes);
849 return -ETIMEDOUT;
850 }
851
852 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
853 {
854 struct mlx5_wq_ll *wq = &rq->wq;
855 struct mlx5e_rx_wqe *wqe;
856 __be16 wqe_ix_be;
857 u16 wqe_ix;
858
859 /* UMR WQE (if in progress) is always at wq->head */
860 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
861 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
862
863 while (!mlx5_wq_ll_is_empty(wq)) {
864 wqe_ix_be = *wq->tail_next;
865 wqe_ix = be16_to_cpu(wqe_ix_be);
866 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
867 rq->dealloc_wqe(rq, wqe_ix);
868 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
869 &wqe->next.next_wqe_index);
870 }
871 }
872
873 static int mlx5e_open_rq(struct mlx5e_channel *c,
874 struct mlx5e_params *params,
875 struct mlx5e_rq_param *param,
876 struct mlx5e_rq *rq)
877 {
878 int err;
879
880 err = mlx5e_alloc_rq(c, params, param, rq);
881 if (err)
882 return err;
883
884 err = mlx5e_create_rq(rq, param);
885 if (err)
886 goto err_free_rq;
887
888 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
889 if (err)
890 goto err_destroy_rq;
891
892 if (params->rx_am_enabled)
893 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
894
895 return 0;
896
897 err_destroy_rq:
898 mlx5e_destroy_rq(rq);
899 err_free_rq:
900 mlx5e_free_rq(rq);
901
902 return err;
903 }
904
905 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
906 {
907 struct mlx5e_icosq *sq = &rq->channel->icosq;
908 u16 pi = sq->pc & sq->wq.sz_m1;
909 struct mlx5e_tx_wqe *nopwqe;
910
911 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
912 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
913 sq->db.ico_wqe[pi].num_wqebbs = 1;
914 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
915 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
916 }
917
918 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
919 {
920 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
921 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
922 }
923
924 static void mlx5e_close_rq(struct mlx5e_rq *rq)
925 {
926 cancel_work_sync(&rq->am.work);
927 mlx5e_destroy_rq(rq);
928 mlx5e_free_rx_descs(rq);
929 mlx5e_free_rq(rq);
930 }
931
932 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
933 {
934 kfree(sq->db.di);
935 }
936
937 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
938 {
939 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
940
941 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
942 GFP_KERNEL, numa);
943 if (!sq->db.di) {
944 mlx5e_free_xdpsq_db(sq);
945 return -ENOMEM;
946 }
947
948 return 0;
949 }
950
951 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
952 struct mlx5e_params *params,
953 struct mlx5e_sq_param *param,
954 struct mlx5e_xdpsq *sq)
955 {
956 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
957 struct mlx5_core_dev *mdev = c->mdev;
958 int err;
959
960 sq->pdev = c->pdev;
961 sq->mkey_be = c->mkey_be;
962 sq->channel = c;
963 sq->uar_map = mdev->mlx5e_res.bfreg.map;
964 sq->min_inline_mode = params->tx_min_inline_mode;
965
966 param->wq.db_numa_node = cpu_to_node(c->cpu);
967 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
968 if (err)
969 return err;
970 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
971
972 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
973 if (err)
974 goto err_sq_wq_destroy;
975
976 return 0;
977
978 err_sq_wq_destroy:
979 mlx5_wq_destroy(&sq->wq_ctrl);
980
981 return err;
982 }
983
984 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
985 {
986 mlx5e_free_xdpsq_db(sq);
987 mlx5_wq_destroy(&sq->wq_ctrl);
988 }
989
990 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
991 {
992 kfree(sq->db.ico_wqe);
993 }
994
995 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
996 {
997 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
998
999 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1000 GFP_KERNEL, numa);
1001 if (!sq->db.ico_wqe)
1002 return -ENOMEM;
1003
1004 return 0;
1005 }
1006
1007 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1008 struct mlx5e_sq_param *param,
1009 struct mlx5e_icosq *sq)
1010 {
1011 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1012 struct mlx5_core_dev *mdev = c->mdev;
1013 int err;
1014
1015 sq->pdev = c->pdev;
1016 sq->mkey_be = c->mkey_be;
1017 sq->channel = c;
1018 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1019
1020 param->wq.db_numa_node = cpu_to_node(c->cpu);
1021 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1022 if (err)
1023 return err;
1024 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1025
1026 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1027 if (err)
1028 goto err_sq_wq_destroy;
1029
1030 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
1031
1032 return 0;
1033
1034 err_sq_wq_destroy:
1035 mlx5_wq_destroy(&sq->wq_ctrl);
1036
1037 return err;
1038 }
1039
1040 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1041 {
1042 mlx5e_free_icosq_db(sq);
1043 mlx5_wq_destroy(&sq->wq_ctrl);
1044 }
1045
1046 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1047 {
1048 kfree(sq->db.wqe_info);
1049 kfree(sq->db.dma_fifo);
1050 }
1051
1052 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1053 {
1054 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1055 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1056
1057 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1058 GFP_KERNEL, numa);
1059 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1060 GFP_KERNEL, numa);
1061 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1062 mlx5e_free_txqsq_db(sq);
1063 return -ENOMEM;
1064 }
1065
1066 sq->dma_fifo_mask = df_sz - 1;
1067
1068 return 0;
1069 }
1070
1071 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1072 int txq_ix,
1073 struct mlx5e_params *params,
1074 struct mlx5e_sq_param *param,
1075 struct mlx5e_txqsq *sq)
1076 {
1077 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1078 struct mlx5_core_dev *mdev = c->mdev;
1079 int err;
1080
1081 sq->pdev = c->pdev;
1082 sq->tstamp = c->tstamp;
1083 sq->mkey_be = c->mkey_be;
1084 sq->channel = c;
1085 sq->txq_ix = txq_ix;
1086 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1087 sq->max_inline = params->tx_max_inline;
1088 sq->min_inline_mode = params->tx_min_inline_mode;
1089
1090 param->wq.db_numa_node = cpu_to_node(c->cpu);
1091 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1092 if (err)
1093 return err;
1094 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1095
1096 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1097 if (err)
1098 goto err_sq_wq_destroy;
1099
1100 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
1101
1102 return 0;
1103
1104 err_sq_wq_destroy:
1105 mlx5_wq_destroy(&sq->wq_ctrl);
1106
1107 return err;
1108 }
1109
1110 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1111 {
1112 mlx5e_free_txqsq_db(sq);
1113 mlx5_wq_destroy(&sq->wq_ctrl);
1114 }
1115
1116 struct mlx5e_create_sq_param {
1117 struct mlx5_wq_ctrl *wq_ctrl;
1118 u32 cqn;
1119 u32 tisn;
1120 u8 tis_lst_sz;
1121 u8 min_inline_mode;
1122 };
1123
1124 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1125 struct mlx5e_sq_param *param,
1126 struct mlx5e_create_sq_param *csp,
1127 u32 *sqn)
1128 {
1129 void *in;
1130 void *sqc;
1131 void *wq;
1132 int inlen;
1133 int err;
1134
1135 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1136 sizeof(u64) * csp->wq_ctrl->buf.npages;
1137 in = mlx5_vzalloc(inlen);
1138 if (!in)
1139 return -ENOMEM;
1140
1141 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1142 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1143
1144 memcpy(sqc, param->sqc, sizeof(param->sqc));
1145 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1146 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1147 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1148
1149 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1150 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1151
1152 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1153
1154 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1155 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1156 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1157 MLX5_ADAPTER_PAGE_SHIFT);
1158 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1159
1160 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1161
1162 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1163
1164 kvfree(in);
1165
1166 return err;
1167 }
1168
1169 struct mlx5e_modify_sq_param {
1170 int curr_state;
1171 int next_state;
1172 bool rl_update;
1173 int rl_index;
1174 };
1175
1176 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1177 struct mlx5e_modify_sq_param *p)
1178 {
1179 void *in;
1180 void *sqc;
1181 int inlen;
1182 int err;
1183
1184 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1185 in = mlx5_vzalloc(inlen);
1186 if (!in)
1187 return -ENOMEM;
1188
1189 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1190
1191 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1192 MLX5_SET(sqc, sqc, state, p->next_state);
1193 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1194 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1195 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1196 }
1197
1198 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1199
1200 kvfree(in);
1201
1202 return err;
1203 }
1204
1205 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1206 {
1207 mlx5_core_destroy_sq(mdev, sqn);
1208 }
1209
1210 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1211 struct mlx5e_sq_param *param,
1212 struct mlx5e_create_sq_param *csp,
1213 u32 *sqn)
1214 {
1215 struct mlx5e_modify_sq_param msp = {0};
1216 int err;
1217
1218 err = mlx5e_create_sq(mdev, param, csp, sqn);
1219 if (err)
1220 return err;
1221
1222 msp.curr_state = MLX5_SQC_STATE_RST;
1223 msp.next_state = MLX5_SQC_STATE_RDY;
1224 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1225 if (err)
1226 mlx5e_destroy_sq(mdev, *sqn);
1227
1228 return err;
1229 }
1230
1231 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1232 struct mlx5e_txqsq *sq, u32 rate);
1233
1234 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1235 u32 tisn,
1236 int txq_ix,
1237 struct mlx5e_params *params,
1238 struct mlx5e_sq_param *param,
1239 struct mlx5e_txqsq *sq)
1240 {
1241 struct mlx5e_create_sq_param csp = {};
1242 u32 tx_rate;
1243 int err;
1244
1245 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1246 if (err)
1247 return err;
1248
1249 csp.tisn = tisn;
1250 csp.tis_lst_sz = 1;
1251 csp.cqn = sq->cq.mcq.cqn;
1252 csp.wq_ctrl = &sq->wq_ctrl;
1253 csp.min_inline_mode = sq->min_inline_mode;
1254 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1255 if (err)
1256 goto err_free_txqsq;
1257
1258 tx_rate = c->priv->tx_rates[sq->txq_ix];
1259 if (tx_rate)
1260 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1261
1262 return 0;
1263
1264 err_free_txqsq:
1265 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1266 mlx5e_free_txqsq(sq);
1267
1268 return err;
1269 }
1270
1271 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1272 {
1273 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1274 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1275 netdev_tx_reset_queue(sq->txq);
1276 netif_tx_start_queue(sq->txq);
1277 }
1278
1279 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1280 {
1281 __netif_tx_lock_bh(txq);
1282 netif_tx_stop_queue(txq);
1283 __netif_tx_unlock_bh(txq);
1284 }
1285
1286 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1287 {
1288 struct mlx5e_channel *c = sq->channel;
1289
1290 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1291 /* prevent netif_tx_wake_queue */
1292 napi_synchronize(&c->napi);
1293
1294 netif_tx_disable_queue(sq->txq);
1295
1296 /* last doorbell out, godspeed .. */
1297 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1298 struct mlx5e_tx_wqe *nop;
1299
1300 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1301 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1302 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1303 }
1304 }
1305
1306 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1307 {
1308 struct mlx5e_channel *c = sq->channel;
1309 struct mlx5_core_dev *mdev = c->mdev;
1310
1311 mlx5e_destroy_sq(mdev, sq->sqn);
1312 if (sq->rate_limit)
1313 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1314 mlx5e_free_txqsq_descs(sq);
1315 mlx5e_free_txqsq(sq);
1316 }
1317
1318 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1319 struct mlx5e_params *params,
1320 struct mlx5e_sq_param *param,
1321 struct mlx5e_icosq *sq)
1322 {
1323 struct mlx5e_create_sq_param csp = {};
1324 int err;
1325
1326 err = mlx5e_alloc_icosq(c, param, sq);
1327 if (err)
1328 return err;
1329
1330 csp.cqn = sq->cq.mcq.cqn;
1331 csp.wq_ctrl = &sq->wq_ctrl;
1332 csp.min_inline_mode = params->tx_min_inline_mode;
1333 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1334 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1335 if (err)
1336 goto err_free_icosq;
1337
1338 return 0;
1339
1340 err_free_icosq:
1341 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1342 mlx5e_free_icosq(sq);
1343
1344 return err;
1345 }
1346
1347 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1348 {
1349 struct mlx5e_channel *c = sq->channel;
1350
1351 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1352 napi_synchronize(&c->napi);
1353
1354 mlx5e_destroy_sq(c->mdev, sq->sqn);
1355 mlx5e_free_icosq(sq);
1356 }
1357
1358 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1359 struct mlx5e_params *params,
1360 struct mlx5e_sq_param *param,
1361 struct mlx5e_xdpsq *sq)
1362 {
1363 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1364 struct mlx5e_create_sq_param csp = {};
1365 unsigned int inline_hdr_sz = 0;
1366 int err;
1367 int i;
1368
1369 err = mlx5e_alloc_xdpsq(c, params, param, sq);
1370 if (err)
1371 return err;
1372
1373 csp.tis_lst_sz = 1;
1374 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
1375 csp.cqn = sq->cq.mcq.cqn;
1376 csp.wq_ctrl = &sq->wq_ctrl;
1377 csp.min_inline_mode = sq->min_inline_mode;
1378 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1379 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1380 if (err)
1381 goto err_free_xdpsq;
1382
1383 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1384 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1385 ds_cnt++;
1386 }
1387
1388 /* Pre initialize fixed WQE fields */
1389 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1390 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1391 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1392 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1393 struct mlx5_wqe_data_seg *dseg;
1394
1395 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1396 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1397
1398 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1399 dseg->lkey = sq->mkey_be;
1400 }
1401
1402 return 0;
1403
1404 err_free_xdpsq:
1405 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1406 mlx5e_free_xdpsq(sq);
1407
1408 return err;
1409 }
1410
1411 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1412 {
1413 struct mlx5e_channel *c = sq->channel;
1414
1415 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1416 napi_synchronize(&c->napi);
1417
1418 mlx5e_destroy_sq(c->mdev, sq->sqn);
1419 mlx5e_free_xdpsq_descs(sq);
1420 mlx5e_free_xdpsq(sq);
1421 }
1422
1423 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1424 struct mlx5e_cq_param *param,
1425 struct mlx5e_cq *cq)
1426 {
1427 struct mlx5_core_cq *mcq = &cq->mcq;
1428 int eqn_not_used;
1429 unsigned int irqn;
1430 int err;
1431 u32 i;
1432
1433 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1434 &cq->wq_ctrl);
1435 if (err)
1436 return err;
1437
1438 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1439
1440 mcq->cqe_sz = 64;
1441 mcq->set_ci_db = cq->wq_ctrl.db.db;
1442 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1443 *mcq->set_ci_db = 0;
1444 *mcq->arm_db = 0;
1445 mcq->vector = param->eq_ix;
1446 mcq->comp = mlx5e_completion_event;
1447 mcq->event = mlx5e_cq_error_event;
1448 mcq->irqn = irqn;
1449
1450 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1451 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1452
1453 cqe->op_own = 0xf1;
1454 }
1455
1456 cq->mdev = mdev;
1457
1458 return 0;
1459 }
1460
1461 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1462 struct mlx5e_cq_param *param,
1463 struct mlx5e_cq *cq)
1464 {
1465 struct mlx5_core_dev *mdev = c->priv->mdev;
1466 int err;
1467
1468 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1469 param->wq.db_numa_node = cpu_to_node(c->cpu);
1470 param->eq_ix = c->ix;
1471
1472 err = mlx5e_alloc_cq_common(mdev, param, cq);
1473
1474 cq->napi = &c->napi;
1475 cq->channel = c;
1476
1477 return err;
1478 }
1479
1480 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1481 {
1482 mlx5_cqwq_destroy(&cq->wq_ctrl);
1483 }
1484
1485 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1486 {
1487 struct mlx5_core_dev *mdev = cq->mdev;
1488 struct mlx5_core_cq *mcq = &cq->mcq;
1489
1490 void *in;
1491 void *cqc;
1492 int inlen;
1493 unsigned int irqn_not_used;
1494 int eqn;
1495 int err;
1496
1497 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1498 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1499 in = mlx5_vzalloc(inlen);
1500 if (!in)
1501 return -ENOMEM;
1502
1503 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1504
1505 memcpy(cqc, param->cqc, sizeof(param->cqc));
1506
1507 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1508 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1509
1510 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1511
1512 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1513 MLX5_SET(cqc, cqc, c_eqn, eqn);
1514 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1515 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1516 MLX5_ADAPTER_PAGE_SHIFT);
1517 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1518
1519 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1520
1521 kvfree(in);
1522
1523 if (err)
1524 return err;
1525
1526 mlx5e_cq_arm(cq);
1527
1528 return 0;
1529 }
1530
1531 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1532 {
1533 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1534 }
1535
1536 static int mlx5e_open_cq(struct mlx5e_channel *c,
1537 struct mlx5e_cq_moder moder,
1538 struct mlx5e_cq_param *param,
1539 struct mlx5e_cq *cq)
1540 {
1541 struct mlx5_core_dev *mdev = c->mdev;
1542 int err;
1543
1544 err = mlx5e_alloc_cq(c, param, cq);
1545 if (err)
1546 return err;
1547
1548 err = mlx5e_create_cq(cq, param);
1549 if (err)
1550 goto err_free_cq;
1551
1552 if (MLX5_CAP_GEN(mdev, cq_moderation))
1553 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1554 return 0;
1555
1556 err_free_cq:
1557 mlx5e_free_cq(cq);
1558
1559 return err;
1560 }
1561
1562 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1563 {
1564 mlx5e_destroy_cq(cq);
1565 mlx5e_free_cq(cq);
1566 }
1567
1568 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1569 {
1570 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1571 }
1572
1573 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1574 struct mlx5e_params *params,
1575 struct mlx5e_channel_param *cparam)
1576 {
1577 int err;
1578 int tc;
1579
1580 for (tc = 0; tc < c->num_tc; tc++) {
1581 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1582 &cparam->tx_cq, &c->sq[tc].cq);
1583 if (err)
1584 goto err_close_tx_cqs;
1585 }
1586
1587 return 0;
1588
1589 err_close_tx_cqs:
1590 for (tc--; tc >= 0; tc--)
1591 mlx5e_close_cq(&c->sq[tc].cq);
1592
1593 return err;
1594 }
1595
1596 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1597 {
1598 int tc;
1599
1600 for (tc = 0; tc < c->num_tc; tc++)
1601 mlx5e_close_cq(&c->sq[tc].cq);
1602 }
1603
1604 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1605 struct mlx5e_params *params,
1606 struct mlx5e_channel_param *cparam)
1607 {
1608 int err;
1609 int tc;
1610
1611 for (tc = 0; tc < params->num_tc; tc++) {
1612 int txq_ix = c->ix + tc * params->num_channels;
1613
1614 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1615 params, &cparam->sq, &c->sq[tc]);
1616 if (err)
1617 goto err_close_sqs;
1618 }
1619
1620 return 0;
1621
1622 err_close_sqs:
1623 for (tc--; tc >= 0; tc--)
1624 mlx5e_close_txqsq(&c->sq[tc]);
1625
1626 return err;
1627 }
1628
1629 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1630 {
1631 int tc;
1632
1633 for (tc = 0; tc < c->num_tc; tc++)
1634 mlx5e_close_txqsq(&c->sq[tc]);
1635 }
1636
1637 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1638 struct mlx5e_txqsq *sq, u32 rate)
1639 {
1640 struct mlx5e_priv *priv = netdev_priv(dev);
1641 struct mlx5_core_dev *mdev = priv->mdev;
1642 struct mlx5e_modify_sq_param msp = {0};
1643 u16 rl_index = 0;
1644 int err;
1645
1646 if (rate == sq->rate_limit)
1647 /* nothing to do */
1648 return 0;
1649
1650 if (sq->rate_limit)
1651 /* remove current rl index to free space to next ones */
1652 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1653
1654 sq->rate_limit = 0;
1655
1656 if (rate) {
1657 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1658 if (err) {
1659 netdev_err(dev, "Failed configuring rate %u: %d\n",
1660 rate, err);
1661 return err;
1662 }
1663 }
1664
1665 msp.curr_state = MLX5_SQC_STATE_RDY;
1666 msp.next_state = MLX5_SQC_STATE_RDY;
1667 msp.rl_index = rl_index;
1668 msp.rl_update = true;
1669 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1670 if (err) {
1671 netdev_err(dev, "Failed configuring rate %u: %d\n",
1672 rate, err);
1673 /* remove the rate from the table */
1674 if (rate)
1675 mlx5_rl_remove_rate(mdev, rate);
1676 return err;
1677 }
1678
1679 sq->rate_limit = rate;
1680 return 0;
1681 }
1682
1683 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1684 {
1685 struct mlx5e_priv *priv = netdev_priv(dev);
1686 struct mlx5_core_dev *mdev = priv->mdev;
1687 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1688 int err = 0;
1689
1690 if (!mlx5_rl_is_supported(mdev)) {
1691 netdev_err(dev, "Rate limiting is not supported on this device\n");
1692 return -EINVAL;
1693 }
1694
1695 /* rate is given in Mb/sec, HW config is in Kb/sec */
1696 rate = rate << 10;
1697
1698 /* Check whether rate in valid range, 0 is always valid */
1699 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1700 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1701 return -ERANGE;
1702 }
1703
1704 mutex_lock(&priv->state_lock);
1705 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1706 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1707 if (!err)
1708 priv->tx_rates[index] = rate;
1709 mutex_unlock(&priv->state_lock);
1710
1711 return err;
1712 }
1713
1714 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1715 struct mlx5e_params *params,
1716 struct mlx5e_channel_param *cparam,
1717 struct mlx5e_channel **cp)
1718 {
1719 struct mlx5e_cq_moder icocq_moder = {0, 0};
1720 struct net_device *netdev = priv->netdev;
1721 int cpu = mlx5e_get_cpu(priv, ix);
1722 struct mlx5e_channel *c;
1723 int err;
1724
1725 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1726 if (!c)
1727 return -ENOMEM;
1728
1729 c->priv = priv;
1730 c->mdev = priv->mdev;
1731 c->tstamp = &priv->tstamp;
1732 c->ix = ix;
1733 c->cpu = cpu;
1734 c->pdev = &priv->mdev->pdev->dev;
1735 c->netdev = priv->netdev;
1736 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1737 c->num_tc = params->num_tc;
1738 c->xdp = !!params->xdp_prog;
1739
1740 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1741
1742 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1743 if (err)
1744 goto err_napi_del;
1745
1746 err = mlx5e_open_tx_cqs(c, params, cparam);
1747 if (err)
1748 goto err_close_icosq_cq;
1749
1750 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1751 if (err)
1752 goto err_close_tx_cqs;
1753
1754 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1755 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1756 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1757 if (err)
1758 goto err_close_rx_cq;
1759
1760 napi_enable(&c->napi);
1761
1762 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1763 if (err)
1764 goto err_disable_napi;
1765
1766 err = mlx5e_open_sqs(c, params, cparam);
1767 if (err)
1768 goto err_close_icosq;
1769
1770 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1771 if (err)
1772 goto err_close_sqs;
1773
1774 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1775 if (err)
1776 goto err_close_xdp_sq;
1777
1778 *cp = c;
1779
1780 return 0;
1781 err_close_xdp_sq:
1782 if (c->xdp)
1783 mlx5e_close_xdpsq(&c->rq.xdpsq);
1784
1785 err_close_sqs:
1786 mlx5e_close_sqs(c);
1787
1788 err_close_icosq:
1789 mlx5e_close_icosq(&c->icosq);
1790
1791 err_disable_napi:
1792 napi_disable(&c->napi);
1793 if (c->xdp)
1794 mlx5e_close_cq(&c->rq.xdpsq.cq);
1795
1796 err_close_rx_cq:
1797 mlx5e_close_cq(&c->rq.cq);
1798
1799 err_close_tx_cqs:
1800 mlx5e_close_tx_cqs(c);
1801
1802 err_close_icosq_cq:
1803 mlx5e_close_cq(&c->icosq.cq);
1804
1805 err_napi_del:
1806 netif_napi_del(&c->napi);
1807 kfree(c);
1808
1809 return err;
1810 }
1811
1812 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1813 {
1814 int tc;
1815
1816 for (tc = 0; tc < c->num_tc; tc++)
1817 mlx5e_activate_txqsq(&c->sq[tc]);
1818 mlx5e_activate_rq(&c->rq);
1819 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1820 }
1821
1822 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1823 {
1824 int tc;
1825
1826 mlx5e_deactivate_rq(&c->rq);
1827 for (tc = 0; tc < c->num_tc; tc++)
1828 mlx5e_deactivate_txqsq(&c->sq[tc]);
1829 }
1830
1831 static void mlx5e_close_channel(struct mlx5e_channel *c)
1832 {
1833 mlx5e_close_rq(&c->rq);
1834 if (c->xdp)
1835 mlx5e_close_xdpsq(&c->rq.xdpsq);
1836 mlx5e_close_sqs(c);
1837 mlx5e_close_icosq(&c->icosq);
1838 napi_disable(&c->napi);
1839 if (c->xdp)
1840 mlx5e_close_cq(&c->rq.xdpsq.cq);
1841 mlx5e_close_cq(&c->rq.cq);
1842 mlx5e_close_tx_cqs(c);
1843 mlx5e_close_cq(&c->icosq.cq);
1844 netif_napi_del(&c->napi);
1845
1846 kfree(c);
1847 }
1848
1849 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1850 struct mlx5e_params *params,
1851 struct mlx5e_rq_param *param)
1852 {
1853 void *rqc = param->rqc;
1854 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1855
1856 switch (params->rq_wq_type) {
1857 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1858 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1859 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
1860 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1861 break;
1862 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1863 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1864 }
1865
1866 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1867 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1868 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
1869 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1870 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1871 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
1872 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
1873
1874 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1875 param->wq.linear = 1;
1876 }
1877
1878 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1879 {
1880 void *rqc = param->rqc;
1881 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1882
1883 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1884 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1885 }
1886
1887 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1888 struct mlx5e_sq_param *param)
1889 {
1890 void *sqc = param->sqc;
1891 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1892
1893 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1894 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1895
1896 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1897 }
1898
1899 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1900 struct mlx5e_params *params,
1901 struct mlx5e_sq_param *param)
1902 {
1903 void *sqc = param->sqc;
1904 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1905
1906 mlx5e_build_sq_param_common(priv, param);
1907 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1908 }
1909
1910 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1911 struct mlx5e_cq_param *param)
1912 {
1913 void *cqc = param->cqc;
1914
1915 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1916 }
1917
1918 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1919 struct mlx5e_params *params,
1920 struct mlx5e_cq_param *param)
1921 {
1922 void *cqc = param->cqc;
1923 u8 log_cq_size;
1924
1925 switch (params->rq_wq_type) {
1926 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1927 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
1928 break;
1929 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1930 log_cq_size = params->log_rq_size;
1931 }
1932
1933 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1934 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1935 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1936 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1937 }
1938
1939 mlx5e_build_common_cq_param(priv, param);
1940 }
1941
1942 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1943 struct mlx5e_params *params,
1944 struct mlx5e_cq_param *param)
1945 {
1946 void *cqc = param->cqc;
1947
1948 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1949
1950 mlx5e_build_common_cq_param(priv, param);
1951
1952 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1953 }
1954
1955 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1956 u8 log_wq_size,
1957 struct mlx5e_cq_param *param)
1958 {
1959 void *cqc = param->cqc;
1960
1961 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1962
1963 mlx5e_build_common_cq_param(priv, param);
1964
1965 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1966 }
1967
1968 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1969 u8 log_wq_size,
1970 struct mlx5e_sq_param *param)
1971 {
1972 void *sqc = param->sqc;
1973 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1974
1975 mlx5e_build_sq_param_common(priv, param);
1976
1977 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1978 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1979 }
1980
1981 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1982 struct mlx5e_params *params,
1983 struct mlx5e_sq_param *param)
1984 {
1985 void *sqc = param->sqc;
1986 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1987
1988 mlx5e_build_sq_param_common(priv, param);
1989 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1990 }
1991
1992 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1993 struct mlx5e_params *params,
1994 struct mlx5e_channel_param *cparam)
1995 {
1996 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1997
1998 mlx5e_build_rq_param(priv, params, &cparam->rq);
1999 mlx5e_build_sq_param(priv, params, &cparam->sq);
2000 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2001 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2002 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2003 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2004 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2005 }
2006
2007 int mlx5e_open_channels(struct mlx5e_priv *priv,
2008 struct mlx5e_channels *chs)
2009 {
2010 struct mlx5e_channel_param *cparam;
2011 int err = -ENOMEM;
2012 int i;
2013
2014 chs->num = chs->params.num_channels;
2015
2016 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2017 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2018 if (!chs->c || !cparam)
2019 goto err_free;
2020
2021 mlx5e_build_channel_param(priv, &chs->params, cparam);
2022 for (i = 0; i < chs->num; i++) {
2023 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2024 if (err)
2025 goto err_close_channels;
2026 }
2027
2028 kfree(cparam);
2029 return 0;
2030
2031 err_close_channels:
2032 for (i--; i >= 0; i--)
2033 mlx5e_close_channel(chs->c[i]);
2034
2035 err_free:
2036 kfree(chs->c);
2037 kfree(cparam);
2038 chs->num = 0;
2039 return err;
2040 }
2041
2042 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2043 {
2044 int i;
2045
2046 for (i = 0; i < chs->num; i++)
2047 mlx5e_activate_channel(chs->c[i]);
2048 }
2049
2050 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2051 {
2052 int err = 0;
2053 int i;
2054
2055 for (i = 0; i < chs->num; i++) {
2056 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2057 if (err)
2058 break;
2059 }
2060
2061 return err;
2062 }
2063
2064 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2065 {
2066 int i;
2067
2068 for (i = 0; i < chs->num; i++)
2069 mlx5e_deactivate_channel(chs->c[i]);
2070 }
2071
2072 void mlx5e_close_channels(struct mlx5e_channels *chs)
2073 {
2074 int i;
2075
2076 for (i = 0; i < chs->num; i++)
2077 mlx5e_close_channel(chs->c[i]);
2078
2079 kfree(chs->c);
2080 chs->num = 0;
2081 }
2082
2083 static int
2084 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2085 {
2086 struct mlx5_core_dev *mdev = priv->mdev;
2087 void *rqtc;
2088 int inlen;
2089 int err;
2090 u32 *in;
2091 int i;
2092
2093 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2094 in = mlx5_vzalloc(inlen);
2095 if (!in)
2096 return -ENOMEM;
2097
2098 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2099
2100 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2101 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2102
2103 for (i = 0; i < sz; i++)
2104 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2105
2106 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2107 if (!err)
2108 rqt->enabled = true;
2109
2110 kvfree(in);
2111 return err;
2112 }
2113
2114 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2115 {
2116 rqt->enabled = false;
2117 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2118 }
2119
2120 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2121 {
2122 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2123 int err;
2124
2125 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2126 if (err)
2127 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2128 return err;
2129 }
2130
2131 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2132 {
2133 struct mlx5e_rqt *rqt;
2134 int err;
2135 int ix;
2136
2137 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2138 rqt = &priv->direct_tir[ix].rqt;
2139 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2140 if (err)
2141 goto err_destroy_rqts;
2142 }
2143
2144 return 0;
2145
2146 err_destroy_rqts:
2147 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2148 for (ix--; ix >= 0; ix--)
2149 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2150
2151 return err;
2152 }
2153
2154 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2155 {
2156 int i;
2157
2158 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2159 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2160 }
2161
2162 static int mlx5e_rx_hash_fn(int hfunc)
2163 {
2164 return (hfunc == ETH_RSS_HASH_TOP) ?
2165 MLX5_RX_HASH_FN_TOEPLITZ :
2166 MLX5_RX_HASH_FN_INVERTED_XOR8;
2167 }
2168
2169 static int mlx5e_bits_invert(unsigned long a, int size)
2170 {
2171 int inv = 0;
2172 int i;
2173
2174 for (i = 0; i < size; i++)
2175 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2176
2177 return inv;
2178 }
2179
2180 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2181 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2182 {
2183 int i;
2184
2185 for (i = 0; i < sz; i++) {
2186 u32 rqn;
2187
2188 if (rrp.is_rss) {
2189 int ix = i;
2190
2191 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2192 ix = mlx5e_bits_invert(i, ilog2(sz));
2193
2194 ix = priv->channels.params.indirection_rqt[ix];
2195 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2196 } else {
2197 rqn = rrp.rqn;
2198 }
2199 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2200 }
2201 }
2202
2203 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2204 struct mlx5e_redirect_rqt_param rrp)
2205 {
2206 struct mlx5_core_dev *mdev = priv->mdev;
2207 void *rqtc;
2208 int inlen;
2209 u32 *in;
2210 int err;
2211
2212 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2213 in = mlx5_vzalloc(inlen);
2214 if (!in)
2215 return -ENOMEM;
2216
2217 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2218
2219 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2220 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2221 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2222 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2223
2224 kvfree(in);
2225 return err;
2226 }
2227
2228 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2229 struct mlx5e_redirect_rqt_param rrp)
2230 {
2231 if (!rrp.is_rss)
2232 return rrp.rqn;
2233
2234 if (ix >= rrp.rss.channels->num)
2235 return priv->drop_rq.rqn;
2236
2237 return rrp.rss.channels->c[ix]->rq.rqn;
2238 }
2239
2240 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2241 struct mlx5e_redirect_rqt_param rrp)
2242 {
2243 u32 rqtn;
2244 int ix;
2245
2246 if (priv->indir_rqt.enabled) {
2247 /* RSS RQ table */
2248 rqtn = priv->indir_rqt.rqtn;
2249 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2250 }
2251
2252 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2253 struct mlx5e_redirect_rqt_param direct_rrp = {
2254 .is_rss = false,
2255 {
2256 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2257 },
2258 };
2259
2260 /* Direct RQ Tables */
2261 if (!priv->direct_tir[ix].rqt.enabled)
2262 continue;
2263
2264 rqtn = priv->direct_tir[ix].rqt.rqtn;
2265 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2266 }
2267 }
2268
2269 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2270 struct mlx5e_channels *chs)
2271 {
2272 struct mlx5e_redirect_rqt_param rrp = {
2273 .is_rss = true,
2274 {
2275 .rss = {
2276 .channels = chs,
2277 .hfunc = chs->params.rss_hfunc,
2278 }
2279 },
2280 };
2281
2282 mlx5e_redirect_rqts(priv, rrp);
2283 }
2284
2285 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2286 {
2287 struct mlx5e_redirect_rqt_param drop_rrp = {
2288 .is_rss = false,
2289 {
2290 .rqn = priv->drop_rq.rqn,
2291 },
2292 };
2293
2294 mlx5e_redirect_rqts(priv, drop_rrp);
2295 }
2296
2297 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2298 {
2299 if (!params->lro_en)
2300 return;
2301
2302 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2303
2304 MLX5_SET(tirc, tirc, lro_enable_mask,
2305 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2306 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2307 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2308 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2309 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2310 }
2311
2312 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2313 enum mlx5e_traffic_types tt,
2314 void *tirc)
2315 {
2316 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2317
2318 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2319 MLX5_HASH_FIELD_SEL_DST_IP)
2320
2321 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2322 MLX5_HASH_FIELD_SEL_DST_IP |\
2323 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2324 MLX5_HASH_FIELD_SEL_L4_DPORT)
2325
2326 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2327 MLX5_HASH_FIELD_SEL_DST_IP |\
2328 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2329
2330 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2331 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2332 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2333 rx_hash_toeplitz_key);
2334 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2335 rx_hash_toeplitz_key);
2336
2337 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2338 memcpy(rss_key, params->toeplitz_hash_key, len);
2339 }
2340
2341 switch (tt) {
2342 case MLX5E_TT_IPV4_TCP:
2343 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2344 MLX5_L3_PROT_TYPE_IPV4);
2345 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2346 MLX5_L4_PROT_TYPE_TCP);
2347 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2348 MLX5_HASH_IP_L4PORTS);
2349 break;
2350
2351 case MLX5E_TT_IPV6_TCP:
2352 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2353 MLX5_L3_PROT_TYPE_IPV6);
2354 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2355 MLX5_L4_PROT_TYPE_TCP);
2356 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2357 MLX5_HASH_IP_L4PORTS);
2358 break;
2359
2360 case MLX5E_TT_IPV4_UDP:
2361 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2362 MLX5_L3_PROT_TYPE_IPV4);
2363 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2364 MLX5_L4_PROT_TYPE_UDP);
2365 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2366 MLX5_HASH_IP_L4PORTS);
2367 break;
2368
2369 case MLX5E_TT_IPV6_UDP:
2370 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2371 MLX5_L3_PROT_TYPE_IPV6);
2372 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2373 MLX5_L4_PROT_TYPE_UDP);
2374 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2375 MLX5_HASH_IP_L4PORTS);
2376 break;
2377
2378 case MLX5E_TT_IPV4_IPSEC_AH:
2379 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2380 MLX5_L3_PROT_TYPE_IPV4);
2381 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2382 MLX5_HASH_IP_IPSEC_SPI);
2383 break;
2384
2385 case MLX5E_TT_IPV6_IPSEC_AH:
2386 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2387 MLX5_L3_PROT_TYPE_IPV6);
2388 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2389 MLX5_HASH_IP_IPSEC_SPI);
2390 break;
2391
2392 case MLX5E_TT_IPV4_IPSEC_ESP:
2393 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2394 MLX5_L3_PROT_TYPE_IPV4);
2395 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2396 MLX5_HASH_IP_IPSEC_SPI);
2397 break;
2398
2399 case MLX5E_TT_IPV6_IPSEC_ESP:
2400 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2401 MLX5_L3_PROT_TYPE_IPV6);
2402 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2403 MLX5_HASH_IP_IPSEC_SPI);
2404 break;
2405
2406 case MLX5E_TT_IPV4:
2407 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2408 MLX5_L3_PROT_TYPE_IPV4);
2409 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2410 MLX5_HASH_IP);
2411 break;
2412
2413 case MLX5E_TT_IPV6:
2414 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2415 MLX5_L3_PROT_TYPE_IPV6);
2416 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2417 MLX5_HASH_IP);
2418 break;
2419 default:
2420 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2421 }
2422 }
2423
2424 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2425 {
2426 struct mlx5_core_dev *mdev = priv->mdev;
2427
2428 void *in;
2429 void *tirc;
2430 int inlen;
2431 int err;
2432 int tt;
2433 int ix;
2434
2435 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2436 in = mlx5_vzalloc(inlen);
2437 if (!in)
2438 return -ENOMEM;
2439
2440 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2441 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2442
2443 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2444
2445 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2446 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2447 inlen);
2448 if (err)
2449 goto free_in;
2450 }
2451
2452 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2453 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2454 in, inlen);
2455 if (err)
2456 goto free_in;
2457 }
2458
2459 free_in:
2460 kvfree(in);
2461
2462 return err;
2463 }
2464
2465 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2466 {
2467 struct mlx5_core_dev *mdev = priv->mdev;
2468 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
2469 int err;
2470
2471 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2472 if (err)
2473 return err;
2474
2475 /* Update vport context MTU */
2476 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2477 return 0;
2478 }
2479
2480 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2481 {
2482 struct mlx5_core_dev *mdev = priv->mdev;
2483 u16 hw_mtu = 0;
2484 int err;
2485
2486 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2487 if (err || !hw_mtu) /* fallback to port oper mtu */
2488 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2489
2490 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2491 }
2492
2493 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2494 {
2495 struct net_device *netdev = priv->netdev;
2496 u16 mtu;
2497 int err;
2498
2499 err = mlx5e_set_mtu(priv, netdev->mtu);
2500 if (err)
2501 return err;
2502
2503 mlx5e_query_mtu(priv, &mtu);
2504 if (mtu != netdev->mtu)
2505 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2506 __func__, mtu, netdev->mtu);
2507
2508 netdev->mtu = mtu;
2509 return 0;
2510 }
2511
2512 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2513 {
2514 struct mlx5e_priv *priv = netdev_priv(netdev);
2515 int nch = priv->channels.params.num_channels;
2516 int ntc = priv->channels.params.num_tc;
2517 int tc;
2518
2519 netdev_reset_tc(netdev);
2520
2521 if (ntc == 1)
2522 return;
2523
2524 netdev_set_num_tc(netdev, ntc);
2525
2526 /* Map netdev TCs to offset 0
2527 * We have our own UP to TXQ mapping for QoS
2528 */
2529 for (tc = 0; tc < ntc; tc++)
2530 netdev_set_tc_queue(netdev, tc, nch, 0);
2531 }
2532
2533 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2534 {
2535 struct mlx5e_channel *c;
2536 struct mlx5e_txqsq *sq;
2537 int i, tc;
2538
2539 for (i = 0; i < priv->channels.num; i++)
2540 for (tc = 0; tc < priv->profile->max_tc; tc++)
2541 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2542
2543 for (i = 0; i < priv->channels.num; i++) {
2544 c = priv->channels.c[i];
2545 for (tc = 0; tc < c->num_tc; tc++) {
2546 sq = &c->sq[tc];
2547 priv->txq2sq[sq->txq_ix] = sq;
2548 }
2549 }
2550 }
2551
2552 static bool mlx5e_is_eswitch_vport_mngr(struct mlx5_core_dev *mdev)
2553 {
2554 return (MLX5_CAP_GEN(mdev, vport_group_manager) &&
2555 MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH);
2556 }
2557
2558 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2559 {
2560 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2561 struct net_device *netdev = priv->netdev;
2562
2563 mlx5e_netdev_set_tcs(netdev);
2564 netif_set_real_num_tx_queues(netdev, num_txqs);
2565 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2566
2567 mlx5e_build_channels_tx_maps(priv);
2568 mlx5e_activate_channels(&priv->channels);
2569 netif_tx_start_all_queues(priv->netdev);
2570
2571 if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
2572 mlx5e_add_sqs_fwd_rules(priv);
2573
2574 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2575 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2576 }
2577
2578 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2579 {
2580 mlx5e_redirect_rqts_to_drop(priv);
2581
2582 if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
2583 mlx5e_remove_sqs_fwd_rules(priv);
2584
2585 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2586 * polling for inactive tx queues.
2587 */
2588 netif_tx_stop_all_queues(priv->netdev);
2589 netif_tx_disable(priv->netdev);
2590 mlx5e_deactivate_channels(&priv->channels);
2591 }
2592
2593 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2594 struct mlx5e_channels *new_chs,
2595 mlx5e_fp_hw_modify hw_modify)
2596 {
2597 struct net_device *netdev = priv->netdev;
2598 int new_num_txqs;
2599
2600 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2601
2602 netif_carrier_off(netdev);
2603
2604 if (new_num_txqs < netdev->real_num_tx_queues)
2605 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2606
2607 mlx5e_deactivate_priv_channels(priv);
2608 mlx5e_close_channels(&priv->channels);
2609
2610 priv->channels = *new_chs;
2611
2612 /* New channels are ready to roll, modify HW settings if needed */
2613 if (hw_modify)
2614 hw_modify(priv);
2615
2616 mlx5e_refresh_tirs(priv, false);
2617 mlx5e_activate_priv_channels(priv);
2618
2619 mlx5e_update_carrier(priv);
2620 }
2621
2622 int mlx5e_open_locked(struct net_device *netdev)
2623 {
2624 struct mlx5e_priv *priv = netdev_priv(netdev);
2625 int err;
2626
2627 set_bit(MLX5E_STATE_OPENED, &priv->state);
2628
2629 err = mlx5e_open_channels(priv, &priv->channels);
2630 if (err)
2631 goto err_clear_state_opened_flag;
2632
2633 mlx5e_refresh_tirs(priv, false);
2634 mlx5e_activate_priv_channels(priv);
2635 mlx5e_update_carrier(priv);
2636 mlx5e_timestamp_init(priv);
2637
2638 if (priv->profile->update_stats)
2639 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2640
2641 return 0;
2642
2643 err_clear_state_opened_flag:
2644 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2645 return err;
2646 }
2647
2648 int mlx5e_open(struct net_device *netdev)
2649 {
2650 struct mlx5e_priv *priv = netdev_priv(netdev);
2651 int err;
2652
2653 mutex_lock(&priv->state_lock);
2654 err = mlx5e_open_locked(netdev);
2655 mutex_unlock(&priv->state_lock);
2656
2657 return err;
2658 }
2659
2660 int mlx5e_close_locked(struct net_device *netdev)
2661 {
2662 struct mlx5e_priv *priv = netdev_priv(netdev);
2663
2664 /* May already be CLOSED in case a previous configuration operation
2665 * (e.g RX/TX queue size change) that involves close&open failed.
2666 */
2667 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2668 return 0;
2669
2670 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2671
2672 mlx5e_timestamp_cleanup(priv);
2673 netif_carrier_off(priv->netdev);
2674 mlx5e_deactivate_priv_channels(priv);
2675 mlx5e_close_channels(&priv->channels);
2676
2677 return 0;
2678 }
2679
2680 int mlx5e_close(struct net_device *netdev)
2681 {
2682 struct mlx5e_priv *priv = netdev_priv(netdev);
2683 int err;
2684
2685 if (!netif_device_present(netdev))
2686 return -ENODEV;
2687
2688 mutex_lock(&priv->state_lock);
2689 err = mlx5e_close_locked(netdev);
2690 mutex_unlock(&priv->state_lock);
2691
2692 return err;
2693 }
2694
2695 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2696 struct mlx5e_rq *rq,
2697 struct mlx5e_rq_param *param)
2698 {
2699 void *rqc = param->rqc;
2700 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2701 int err;
2702
2703 param->wq.db_numa_node = param->wq.buf_numa_node;
2704
2705 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2706 &rq->wq_ctrl);
2707 if (err)
2708 return err;
2709
2710 rq->mdev = mdev;
2711
2712 return 0;
2713 }
2714
2715 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2716 struct mlx5e_cq *cq,
2717 struct mlx5e_cq_param *param)
2718 {
2719 return mlx5e_alloc_cq_common(mdev, param, cq);
2720 }
2721
2722 static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2723 struct mlx5e_rq *drop_rq)
2724 {
2725 struct mlx5e_cq_param cq_param = {};
2726 struct mlx5e_rq_param rq_param = {};
2727 struct mlx5e_cq *cq = &drop_rq->cq;
2728 int err;
2729
2730 mlx5e_build_drop_rq_param(&rq_param);
2731
2732 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2733 if (err)
2734 return err;
2735
2736 err = mlx5e_create_cq(cq, &cq_param);
2737 if (err)
2738 goto err_free_cq;
2739
2740 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2741 if (err)
2742 goto err_destroy_cq;
2743
2744 err = mlx5e_create_rq(drop_rq, &rq_param);
2745 if (err)
2746 goto err_free_rq;
2747
2748 return 0;
2749
2750 err_free_rq:
2751 mlx5e_free_rq(drop_rq);
2752
2753 err_destroy_cq:
2754 mlx5e_destroy_cq(cq);
2755
2756 err_free_cq:
2757 mlx5e_free_cq(cq);
2758
2759 return err;
2760 }
2761
2762 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2763 {
2764 mlx5e_destroy_rq(drop_rq);
2765 mlx5e_free_rq(drop_rq);
2766 mlx5e_destroy_cq(&drop_rq->cq);
2767 mlx5e_free_cq(&drop_rq->cq);
2768 }
2769
2770 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2771 u32 underlay_qpn, u32 *tisn)
2772 {
2773 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2774 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2775
2776 MLX5_SET(tisc, tisc, prio, tc << 1);
2777 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2778 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2779
2780 if (mlx5_lag_is_lacp_owner(mdev))
2781 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2782
2783 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2784 }
2785
2786 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2787 {
2788 mlx5_core_destroy_tis(mdev, tisn);
2789 }
2790
2791 int mlx5e_create_tises(struct mlx5e_priv *priv)
2792 {
2793 int err;
2794 int tc;
2795
2796 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2797 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2798 if (err)
2799 goto err_close_tises;
2800 }
2801
2802 return 0;
2803
2804 err_close_tises:
2805 for (tc--; tc >= 0; tc--)
2806 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2807
2808 return err;
2809 }
2810
2811 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2812 {
2813 int tc;
2814
2815 for (tc = 0; tc < priv->profile->max_tc; tc++)
2816 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2817 }
2818
2819 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2820 enum mlx5e_traffic_types tt,
2821 u32 *tirc)
2822 {
2823 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2824
2825 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2826
2827 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2828 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2829 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
2830 }
2831
2832 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2833 {
2834 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2835
2836 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2837
2838 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2839 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2840 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2841 }
2842
2843 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2844 {
2845 struct mlx5e_tir *tir;
2846 void *tirc;
2847 int inlen;
2848 int err;
2849 u32 *in;
2850 int tt;
2851
2852 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2853 in = mlx5_vzalloc(inlen);
2854 if (!in)
2855 return -ENOMEM;
2856
2857 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2858 memset(in, 0, inlen);
2859 tir = &priv->indir_tir[tt];
2860 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2861 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2862 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2863 if (err)
2864 goto err_destroy_tirs;
2865 }
2866
2867 kvfree(in);
2868
2869 return 0;
2870
2871 err_destroy_tirs:
2872 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2873 for (tt--; tt >= 0; tt--)
2874 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2875
2876 kvfree(in);
2877
2878 return err;
2879 }
2880
2881 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2882 {
2883 int nch = priv->profile->max_nch(priv->mdev);
2884 struct mlx5e_tir *tir;
2885 void *tirc;
2886 int inlen;
2887 int err;
2888 u32 *in;
2889 int ix;
2890
2891 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2892 in = mlx5_vzalloc(inlen);
2893 if (!in)
2894 return -ENOMEM;
2895
2896 for (ix = 0; ix < nch; ix++) {
2897 memset(in, 0, inlen);
2898 tir = &priv->direct_tir[ix];
2899 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2900 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2901 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2902 if (err)
2903 goto err_destroy_ch_tirs;
2904 }
2905
2906 kvfree(in);
2907
2908 return 0;
2909
2910 err_destroy_ch_tirs:
2911 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
2912 for (ix--; ix >= 0; ix--)
2913 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2914
2915 kvfree(in);
2916
2917 return err;
2918 }
2919
2920 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2921 {
2922 int i;
2923
2924 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2925 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2926 }
2927
2928 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2929 {
2930 int nch = priv->profile->max_nch(priv->mdev);
2931 int i;
2932
2933 for (i = 0; i < nch; i++)
2934 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2935 }
2936
2937 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2938 {
2939 int err = 0;
2940 int i;
2941
2942 for (i = 0; i < chs->num; i++) {
2943 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2944 if (err)
2945 return err;
2946 }
2947
2948 return 0;
2949 }
2950
2951 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
2952 {
2953 int err = 0;
2954 int i;
2955
2956 for (i = 0; i < chs->num; i++) {
2957 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
2958 if (err)
2959 return err;
2960 }
2961
2962 return 0;
2963 }
2964
2965 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2966 {
2967 struct mlx5e_priv *priv = netdev_priv(netdev);
2968 struct mlx5e_channels new_channels = {};
2969 int err = 0;
2970
2971 if (tc && tc != MLX5E_MAX_NUM_TC)
2972 return -EINVAL;
2973
2974 mutex_lock(&priv->state_lock);
2975
2976 new_channels.params = priv->channels.params;
2977 new_channels.params.num_tc = tc ? tc : 1;
2978
2979 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
2980 priv->channels.params = new_channels.params;
2981 goto out;
2982 }
2983
2984 err = mlx5e_open_channels(priv, &new_channels);
2985 if (err)
2986 goto out;
2987
2988 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
2989 out:
2990 mutex_unlock(&priv->state_lock);
2991 return err;
2992 }
2993
2994 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2995 __be16 proto, struct tc_to_netdev *tc)
2996 {
2997 struct mlx5e_priv *priv = netdev_priv(dev);
2998
2999 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
3000 goto mqprio;
3001
3002 switch (tc->type) {
3003 case TC_SETUP_CLSFLOWER:
3004 switch (tc->cls_flower->command) {
3005 case TC_CLSFLOWER_REPLACE:
3006 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
3007 case TC_CLSFLOWER_DESTROY:
3008 return mlx5e_delete_flower(priv, tc->cls_flower);
3009 case TC_CLSFLOWER_STATS:
3010 return mlx5e_stats_flower(priv, tc->cls_flower);
3011 }
3012 default:
3013 return -EOPNOTSUPP;
3014 }
3015
3016 mqprio:
3017 if (tc->type != TC_SETUP_MQPRIO)
3018 return -EINVAL;
3019
3020 tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3021
3022 return mlx5e_setup_tc(dev, tc->mqprio->num_tc);
3023 }
3024
3025 static void
3026 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3027 {
3028 struct mlx5e_priv *priv = netdev_priv(dev);
3029 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3030 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3031 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3032
3033 if (mlx5e_is_uplink_rep(priv)) {
3034 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3035 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3036 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3037 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3038 } else {
3039 stats->rx_packets = sstats->rx_packets;
3040 stats->rx_bytes = sstats->rx_bytes;
3041 stats->tx_packets = sstats->tx_packets;
3042 stats->tx_bytes = sstats->tx_bytes;
3043 stats->tx_dropped = sstats->tx_queue_dropped;
3044 }
3045
3046 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3047
3048 stats->rx_length_errors =
3049 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3050 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3051 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3052 stats->rx_crc_errors =
3053 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3054 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3055 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3056 stats->tx_carrier_errors =
3057 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
3058 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3059 stats->rx_frame_errors;
3060 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3061
3062 /* vport multicast also counts packets that are dropped due to steering
3063 * or rx out of buffer
3064 */
3065 stats->multicast =
3066 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3067
3068 }
3069
3070 static void mlx5e_set_rx_mode(struct net_device *dev)
3071 {
3072 struct mlx5e_priv *priv = netdev_priv(dev);
3073
3074 queue_work(priv->wq, &priv->set_rx_mode_work);
3075 }
3076
3077 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3078 {
3079 struct mlx5e_priv *priv = netdev_priv(netdev);
3080 struct sockaddr *saddr = addr;
3081
3082 if (!is_valid_ether_addr(saddr->sa_data))
3083 return -EADDRNOTAVAIL;
3084
3085 netif_addr_lock_bh(netdev);
3086 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3087 netif_addr_unlock_bh(netdev);
3088
3089 queue_work(priv->wq, &priv->set_rx_mode_work);
3090
3091 return 0;
3092 }
3093
3094 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
3095 do { \
3096 if (enable) \
3097 netdev->features |= feature; \
3098 else \
3099 netdev->features &= ~feature; \
3100 } while (0)
3101
3102 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3103
3104 static int set_feature_lro(struct net_device *netdev, bool enable)
3105 {
3106 struct mlx5e_priv *priv = netdev_priv(netdev);
3107 struct mlx5e_channels new_channels = {};
3108 int err = 0;
3109 bool reset;
3110
3111 mutex_lock(&priv->state_lock);
3112
3113 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3114 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3115
3116 new_channels.params = priv->channels.params;
3117 new_channels.params.lro_en = enable;
3118
3119 if (!reset) {
3120 priv->channels.params = new_channels.params;
3121 err = mlx5e_modify_tirs_lro(priv);
3122 goto out;
3123 }
3124
3125 err = mlx5e_open_channels(priv, &new_channels);
3126 if (err)
3127 goto out;
3128
3129 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3130 out:
3131 mutex_unlock(&priv->state_lock);
3132 return err;
3133 }
3134
3135 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3136 {
3137 struct mlx5e_priv *priv = netdev_priv(netdev);
3138
3139 if (enable)
3140 mlx5e_enable_vlan_filter(priv);
3141 else
3142 mlx5e_disable_vlan_filter(priv);
3143
3144 return 0;
3145 }
3146
3147 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3148 {
3149 struct mlx5e_priv *priv = netdev_priv(netdev);
3150
3151 if (!enable && mlx5e_tc_num_filters(priv)) {
3152 netdev_err(netdev,
3153 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3154 return -EINVAL;
3155 }
3156
3157 return 0;
3158 }
3159
3160 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3161 {
3162 struct mlx5e_priv *priv = netdev_priv(netdev);
3163 struct mlx5_core_dev *mdev = priv->mdev;
3164
3165 return mlx5_set_port_fcs(mdev, !enable);
3166 }
3167
3168 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3169 {
3170 struct mlx5e_priv *priv = netdev_priv(netdev);
3171 int err;
3172
3173 mutex_lock(&priv->state_lock);
3174
3175 priv->channels.params.scatter_fcs_en = enable;
3176 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3177 if (err)
3178 priv->channels.params.scatter_fcs_en = !enable;
3179
3180 mutex_unlock(&priv->state_lock);
3181
3182 return err;
3183 }
3184
3185 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3186 {
3187 struct mlx5e_priv *priv = netdev_priv(netdev);
3188 int err = 0;
3189
3190 mutex_lock(&priv->state_lock);
3191
3192 priv->channels.params.vlan_strip_disable = !enable;
3193 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3194 goto unlock;
3195
3196 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3197 if (err)
3198 priv->channels.params.vlan_strip_disable = enable;
3199
3200 unlock:
3201 mutex_unlock(&priv->state_lock);
3202
3203 return err;
3204 }
3205
3206 #ifdef CONFIG_RFS_ACCEL
3207 static int set_feature_arfs(struct net_device *netdev, bool enable)
3208 {
3209 struct mlx5e_priv *priv = netdev_priv(netdev);
3210 int err;
3211
3212 if (enable)
3213 err = mlx5e_arfs_enable(priv);
3214 else
3215 err = mlx5e_arfs_disable(priv);
3216
3217 return err;
3218 }
3219 #endif
3220
3221 static int mlx5e_handle_feature(struct net_device *netdev,
3222 netdev_features_t wanted_features,
3223 netdev_features_t feature,
3224 mlx5e_feature_handler feature_handler)
3225 {
3226 netdev_features_t changes = wanted_features ^ netdev->features;
3227 bool enable = !!(wanted_features & feature);
3228 int err;
3229
3230 if (!(changes & feature))
3231 return 0;
3232
3233 err = feature_handler(netdev, enable);
3234 if (err) {
3235 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
3236 enable ? "Enable" : "Disable", feature, err);
3237 return err;
3238 }
3239
3240 MLX5E_SET_FEATURE(netdev, feature, enable);
3241 return 0;
3242 }
3243
3244 static int mlx5e_set_features(struct net_device *netdev,
3245 netdev_features_t features)
3246 {
3247 int err;
3248
3249 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3250 set_feature_lro);
3251 err |= mlx5e_handle_feature(netdev, features,
3252 NETIF_F_HW_VLAN_CTAG_FILTER,
3253 set_feature_vlan_filter);
3254 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3255 set_feature_tc_num_filters);
3256 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3257 set_feature_rx_all);
3258 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3259 set_feature_rx_fcs);
3260 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3261 set_feature_rx_vlan);
3262 #ifdef CONFIG_RFS_ACCEL
3263 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3264 set_feature_arfs);
3265 #endif
3266
3267 return err ? -EINVAL : 0;
3268 }
3269
3270 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3271 {
3272 struct mlx5e_priv *priv = netdev_priv(netdev);
3273 struct mlx5e_channels new_channels = {};
3274 int curr_mtu;
3275 int err = 0;
3276 bool reset;
3277
3278 mutex_lock(&priv->state_lock);
3279
3280 reset = !priv->channels.params.lro_en &&
3281 (priv->channels.params.rq_wq_type !=
3282 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3283
3284 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3285
3286 curr_mtu = netdev->mtu;
3287 netdev->mtu = new_mtu;
3288
3289 if (!reset) {
3290 mlx5e_set_dev_port_mtu(priv);
3291 goto out;
3292 }
3293
3294 new_channels.params = priv->channels.params;
3295 err = mlx5e_open_channels(priv, &new_channels);
3296 if (err) {
3297 netdev->mtu = curr_mtu;
3298 goto out;
3299 }
3300
3301 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3302
3303 out:
3304 mutex_unlock(&priv->state_lock);
3305 return err;
3306 }
3307
3308 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3309 {
3310 switch (cmd) {
3311 case SIOCSHWTSTAMP:
3312 return mlx5e_hwstamp_set(dev, ifr);
3313 case SIOCGHWTSTAMP:
3314 return mlx5e_hwstamp_get(dev, ifr);
3315 default:
3316 return -EOPNOTSUPP;
3317 }
3318 }
3319
3320 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3321 {
3322 struct mlx5e_priv *priv = netdev_priv(dev);
3323 struct mlx5_core_dev *mdev = priv->mdev;
3324
3325 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3326 }
3327
3328 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3329 __be16 vlan_proto)
3330 {
3331 struct mlx5e_priv *priv = netdev_priv(dev);
3332 struct mlx5_core_dev *mdev = priv->mdev;
3333
3334 if (vlan_proto != htons(ETH_P_8021Q))
3335 return -EPROTONOSUPPORT;
3336
3337 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3338 vlan, qos);
3339 }
3340
3341 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3342 {
3343 struct mlx5e_priv *priv = netdev_priv(dev);
3344 struct mlx5_core_dev *mdev = priv->mdev;
3345
3346 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3347 }
3348
3349 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3350 {
3351 struct mlx5e_priv *priv = netdev_priv(dev);
3352 struct mlx5_core_dev *mdev = priv->mdev;
3353
3354 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3355 }
3356
3357 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3358 int max_tx_rate)
3359 {
3360 struct mlx5e_priv *priv = netdev_priv(dev);
3361 struct mlx5_core_dev *mdev = priv->mdev;
3362
3363 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3364 max_tx_rate, min_tx_rate);
3365 }
3366
3367 static int mlx5_vport_link2ifla(u8 esw_link)
3368 {
3369 switch (esw_link) {
3370 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3371 return IFLA_VF_LINK_STATE_DISABLE;
3372 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3373 return IFLA_VF_LINK_STATE_ENABLE;
3374 }
3375 return IFLA_VF_LINK_STATE_AUTO;
3376 }
3377
3378 static int mlx5_ifla_link2vport(u8 ifla_link)
3379 {
3380 switch (ifla_link) {
3381 case IFLA_VF_LINK_STATE_DISABLE:
3382 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3383 case IFLA_VF_LINK_STATE_ENABLE:
3384 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3385 }
3386 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3387 }
3388
3389 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3390 int link_state)
3391 {
3392 struct mlx5e_priv *priv = netdev_priv(dev);
3393 struct mlx5_core_dev *mdev = priv->mdev;
3394
3395 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3396 mlx5_ifla_link2vport(link_state));
3397 }
3398
3399 static int mlx5e_get_vf_config(struct net_device *dev,
3400 int vf, struct ifla_vf_info *ivi)
3401 {
3402 struct mlx5e_priv *priv = netdev_priv(dev);
3403 struct mlx5_core_dev *mdev = priv->mdev;
3404 int err;
3405
3406 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3407 if (err)
3408 return err;
3409 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3410 return 0;
3411 }
3412
3413 static int mlx5e_get_vf_stats(struct net_device *dev,
3414 int vf, struct ifla_vf_stats *vf_stats)
3415 {
3416 struct mlx5e_priv *priv = netdev_priv(dev);
3417 struct mlx5_core_dev *mdev = priv->mdev;
3418
3419 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3420 vf_stats);
3421 }
3422
3423 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3424 struct udp_tunnel_info *ti)
3425 {
3426 struct mlx5e_priv *priv = netdev_priv(netdev);
3427
3428 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3429 return;
3430
3431 if (!mlx5e_vxlan_allowed(priv->mdev))
3432 return;
3433
3434 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3435 }
3436
3437 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3438 struct udp_tunnel_info *ti)
3439 {
3440 struct mlx5e_priv *priv = netdev_priv(netdev);
3441
3442 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3443 return;
3444
3445 if (!mlx5e_vxlan_allowed(priv->mdev))
3446 return;
3447
3448 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3449 }
3450
3451 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3452 struct sk_buff *skb,
3453 netdev_features_t features)
3454 {
3455 struct udphdr *udph;
3456 u16 proto;
3457 u16 port = 0;
3458
3459 switch (vlan_get_protocol(skb)) {
3460 case htons(ETH_P_IP):
3461 proto = ip_hdr(skb)->protocol;
3462 break;
3463 case htons(ETH_P_IPV6):
3464 proto = ipv6_hdr(skb)->nexthdr;
3465 break;
3466 default:
3467 goto out;
3468 }
3469
3470 if (proto == IPPROTO_UDP) {
3471 udph = udp_hdr(skb);
3472 port = be16_to_cpu(udph->dest);
3473 }
3474
3475 /* Verify if UDP port is being offloaded by HW */
3476 if (port && mlx5e_vxlan_lookup_port(priv, port))
3477 return features;
3478
3479 out:
3480 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3481 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3482 }
3483
3484 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3485 struct net_device *netdev,
3486 netdev_features_t features)
3487 {
3488 struct mlx5e_priv *priv = netdev_priv(netdev);
3489
3490 features = vlan_features_check(skb, features);
3491 features = vxlan_features_check(skb, features);
3492
3493 /* Validate if the tunneled packet is being offloaded by HW */
3494 if (skb->encapsulation &&
3495 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3496 return mlx5e_vxlan_features_check(priv, skb, features);
3497
3498 return features;
3499 }
3500
3501 static void mlx5e_tx_timeout(struct net_device *dev)
3502 {
3503 struct mlx5e_priv *priv = netdev_priv(dev);
3504 bool sched_work = false;
3505 int i;
3506
3507 netdev_err(dev, "TX timeout detected\n");
3508
3509 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
3510 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3511
3512 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3513 continue;
3514 sched_work = true;
3515 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3516 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3517 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3518 }
3519
3520 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3521 schedule_work(&priv->tx_timeout_work);
3522 }
3523
3524 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3525 {
3526 struct mlx5e_priv *priv = netdev_priv(netdev);
3527 struct bpf_prog *old_prog;
3528 int err = 0;
3529 bool reset, was_opened;
3530 int i;
3531
3532 mutex_lock(&priv->state_lock);
3533
3534 if ((netdev->features & NETIF_F_LRO) && prog) {
3535 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3536 err = -EINVAL;
3537 goto unlock;
3538 }
3539
3540 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3541 /* no need for full reset when exchanging programs */
3542 reset = (!priv->channels.params.xdp_prog || !prog);
3543
3544 if (was_opened && reset)
3545 mlx5e_close_locked(netdev);
3546 if (was_opened && !reset) {
3547 /* num_channels is invariant here, so we can take the
3548 * batched reference right upfront.
3549 */
3550 prog = bpf_prog_add(prog, priv->channels.num);
3551 if (IS_ERR(prog)) {
3552 err = PTR_ERR(prog);
3553 goto unlock;
3554 }
3555 }
3556
3557 /* exchange programs, extra prog reference we got from caller
3558 * as long as we don't fail from this point onwards.
3559 */
3560 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
3561 if (old_prog)
3562 bpf_prog_put(old_prog);
3563
3564 if (reset) /* change RQ type according to priv->xdp_prog */
3565 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
3566
3567 if (was_opened && reset)
3568 mlx5e_open_locked(netdev);
3569
3570 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3571 goto unlock;
3572
3573 /* exchanging programs w/o reset, we update ref counts on behalf
3574 * of the channels RQs here.
3575 */
3576 for (i = 0; i < priv->channels.num; i++) {
3577 struct mlx5e_channel *c = priv->channels.c[i];
3578
3579 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3580 napi_synchronize(&c->napi);
3581 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3582
3583 old_prog = xchg(&c->rq.xdp_prog, prog);
3584
3585 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3586 /* napi_schedule in case we have missed anything */
3587 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3588 napi_schedule(&c->napi);
3589
3590 if (old_prog)
3591 bpf_prog_put(old_prog);
3592 }
3593
3594 unlock:
3595 mutex_unlock(&priv->state_lock);
3596 return err;
3597 }
3598
3599 static bool mlx5e_xdp_attached(struct net_device *dev)
3600 {
3601 struct mlx5e_priv *priv = netdev_priv(dev);
3602
3603 return !!priv->channels.params.xdp_prog;
3604 }
3605
3606 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3607 {
3608 switch (xdp->command) {
3609 case XDP_SETUP_PROG:
3610 return mlx5e_xdp_set(dev, xdp->prog);
3611 case XDP_QUERY_PROG:
3612 xdp->prog_attached = mlx5e_xdp_attached(dev);
3613 return 0;
3614 default:
3615 return -EINVAL;
3616 }
3617 }
3618
3619 #ifdef CONFIG_NET_POLL_CONTROLLER
3620 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3621 * reenabling interrupts.
3622 */
3623 static void mlx5e_netpoll(struct net_device *dev)
3624 {
3625 struct mlx5e_priv *priv = netdev_priv(dev);
3626 struct mlx5e_channels *chs = &priv->channels;
3627
3628 int i;
3629
3630 for (i = 0; i < chs->num; i++)
3631 napi_schedule(&chs->c[i]->napi);
3632 }
3633 #endif
3634
3635 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3636 .ndo_open = mlx5e_open,
3637 .ndo_stop = mlx5e_close,
3638 .ndo_start_xmit = mlx5e_xmit,
3639 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3640 .ndo_select_queue = mlx5e_select_queue,
3641 .ndo_get_stats64 = mlx5e_get_stats,
3642 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3643 .ndo_set_mac_address = mlx5e_set_mac,
3644 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3645 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3646 .ndo_set_features = mlx5e_set_features,
3647 .ndo_change_mtu = mlx5e_change_mtu,
3648 .ndo_do_ioctl = mlx5e_ioctl,
3649 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3650 #ifdef CONFIG_RFS_ACCEL
3651 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3652 #endif
3653 .ndo_tx_timeout = mlx5e_tx_timeout,
3654 .ndo_xdp = mlx5e_xdp,
3655 #ifdef CONFIG_NET_POLL_CONTROLLER
3656 .ndo_poll_controller = mlx5e_netpoll,
3657 #endif
3658 };
3659
3660 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3661 .ndo_open = mlx5e_open,
3662 .ndo_stop = mlx5e_close,
3663 .ndo_start_xmit = mlx5e_xmit,
3664 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3665 .ndo_select_queue = mlx5e_select_queue,
3666 .ndo_get_stats64 = mlx5e_get_stats,
3667 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3668 .ndo_set_mac_address = mlx5e_set_mac,
3669 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3670 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3671 .ndo_set_features = mlx5e_set_features,
3672 .ndo_change_mtu = mlx5e_change_mtu,
3673 .ndo_do_ioctl = mlx5e_ioctl,
3674 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3675 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3676 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3677 .ndo_features_check = mlx5e_features_check,
3678 #ifdef CONFIG_RFS_ACCEL
3679 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3680 #endif
3681 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3682 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
3683 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
3684 .ndo_set_vf_trust = mlx5e_set_vf_trust,
3685 .ndo_set_vf_rate = mlx5e_set_vf_rate,
3686 .ndo_get_vf_config = mlx5e_get_vf_config,
3687 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3688 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3689 .ndo_tx_timeout = mlx5e_tx_timeout,
3690 .ndo_xdp = mlx5e_xdp,
3691 #ifdef CONFIG_NET_POLL_CONTROLLER
3692 .ndo_poll_controller = mlx5e_netpoll,
3693 #endif
3694 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3695 .ndo_get_offload_stats = mlx5e_get_offload_stats,
3696 };
3697
3698 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3699 {
3700 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3701 return -EOPNOTSUPP;
3702 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3703 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3704 !MLX5_CAP_ETH(mdev, csum_cap) ||
3705 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3706 !MLX5_CAP_ETH(mdev, vlan_cap) ||
3707 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3708 MLX5_CAP_FLOWTABLE(mdev,
3709 flow_table_properties_nic_receive.max_ft_level)
3710 < 3) {
3711 mlx5_core_warn(mdev,
3712 "Not creating net device, some required device capabilities are missing\n");
3713 return -EOPNOTSUPP;
3714 }
3715 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3716 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3717 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3718 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
3719
3720 return 0;
3721 }
3722
3723 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3724 {
3725 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3726
3727 return bf_buf_size -
3728 sizeof(struct mlx5e_tx_wqe) +
3729 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3730 }
3731
3732 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3733 u32 *indirection_rqt, int len,
3734 int num_channels)
3735 {
3736 int node = mdev->priv.numa_node;
3737 int node_num_of_cores;
3738 int i;
3739
3740 if (node == -1)
3741 node = first_online_node;
3742
3743 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3744
3745 if (node_num_of_cores)
3746 num_channels = min_t(int, num_channels, node_num_of_cores);
3747
3748 for (i = 0; i < len; i++)
3749 indirection_rqt[i] = i % num_channels;
3750 }
3751
3752 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3753 {
3754 enum pcie_link_width width;
3755 enum pci_bus_speed speed;
3756 int err = 0;
3757
3758 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3759 if (err)
3760 return err;
3761
3762 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3763 return -EINVAL;
3764
3765 switch (speed) {
3766 case PCIE_SPEED_2_5GT:
3767 *pci_bw = 2500 * width;
3768 break;
3769 case PCIE_SPEED_5_0GT:
3770 *pci_bw = 5000 * width;
3771 break;
3772 case PCIE_SPEED_8_0GT:
3773 *pci_bw = 8000 * width;
3774 break;
3775 default:
3776 return -EINVAL;
3777 }
3778
3779 return 0;
3780 }
3781
3782 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3783 {
3784 return (link_speed && pci_bw &&
3785 (pci_bw < 40000) && (pci_bw < link_speed));
3786 }
3787
3788 static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
3789 {
3790 return !(link_speed && pci_bw &&
3791 (pci_bw <= 16000) && (pci_bw < link_speed));
3792 }
3793
3794 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3795 {
3796 params->rx_cq_period_mode = cq_period_mode;
3797
3798 params->rx_cq_moderation.pkts =
3799 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3800 params->rx_cq_moderation.usec =
3801 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3802
3803 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3804 params->rx_cq_moderation.usec =
3805 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3806
3807 if (params->rx_am_enabled)
3808 params->rx_cq_moderation =
3809 mlx5e_am_get_def_profile(params->rx_cq_period_mode);
3810
3811 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3812 params->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3813 }
3814
3815 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3816 {
3817 int i;
3818
3819 /* The supported periods are organized in ascending order */
3820 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3821 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3822 break;
3823
3824 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3825 }
3826
3827 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3828 struct mlx5e_params *params,
3829 u16 max_channels)
3830 {
3831 u8 cq_period_mode = 0;
3832 u32 link_speed = 0;
3833 u32 pci_bw = 0;
3834
3835 params->num_channels = max_channels;
3836 params->num_tc = 1;
3837
3838 mlx5e_get_max_linkspeed(mdev, &link_speed);
3839 mlx5e_get_pci_bw(mdev, &pci_bw);
3840 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3841 link_speed, pci_bw);
3842
3843 /* SQ */
3844 params->log_sq_size = is_kdump_kernel() ?
3845 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3846 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3847
3848 /* set CQE compression */
3849 params->rx_cqe_compress_def = false;
3850 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3851 MLX5_CAP_GEN(mdev, vport_group_manager))
3852 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
3853
3854 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
3855
3856 /* RQ */
3857 mlx5e_set_rq_params(mdev, params);
3858
3859 /* HW LRO */
3860 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
3861 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3862 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
3863 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3864
3865 /* CQ moderation params */
3866 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3867 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3868 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3869 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3870 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
3871
3872 params->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3873 params->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3874
3875 /* TX inline */
3876 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3877 mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
3878 if (params->tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
3879 !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
3880 params->tx_min_inline_mode = MLX5_INLINE_MODE_L2;
3881
3882 /* RSS */
3883 params->rss_hfunc = ETH_RSS_HASH_XOR;
3884 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
3885 mlx5e_build_default_indir_rqt(mdev, params->indirection_rqt,
3886 MLX5E_INDIR_RQT_SIZE, max_channels);
3887 }
3888
3889 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3890 struct net_device *netdev,
3891 const struct mlx5e_profile *profile,
3892 void *ppriv)
3893 {
3894 struct mlx5e_priv *priv = netdev_priv(netdev);
3895
3896 priv->mdev = mdev;
3897 priv->netdev = netdev;
3898 priv->profile = profile;
3899 priv->ppriv = ppriv;
3900
3901 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
3902
3903 mutex_init(&priv->state_lock);
3904
3905 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3906 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3907 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3908 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3909 }
3910
3911 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3912 {
3913 struct mlx5e_priv *priv = netdev_priv(netdev);
3914
3915 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3916 if (is_zero_ether_addr(netdev->dev_addr) &&
3917 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3918 eth_hw_addr_random(netdev);
3919 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3920 }
3921 }
3922
3923 static const struct switchdev_ops mlx5e_switchdev_ops = {
3924 .switchdev_port_attr_get = mlx5e_attr_get,
3925 };
3926
3927 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3928 {
3929 struct mlx5e_priv *priv = netdev_priv(netdev);
3930 struct mlx5_core_dev *mdev = priv->mdev;
3931 bool fcs_supported;
3932 bool fcs_enabled;
3933
3934 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3935
3936 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3937 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3938 #ifdef CONFIG_MLX5_CORE_EN_DCB
3939 if (MLX5_CAP_GEN(mdev, qos))
3940 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3941 #endif
3942 } else {
3943 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3944 }
3945
3946 netdev->watchdog_timeo = 15 * HZ;
3947
3948 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3949
3950 netdev->vlan_features |= NETIF_F_SG;
3951 netdev->vlan_features |= NETIF_F_IP_CSUM;
3952 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3953 netdev->vlan_features |= NETIF_F_GRO;
3954 netdev->vlan_features |= NETIF_F_TSO;
3955 netdev->vlan_features |= NETIF_F_TSO6;
3956 netdev->vlan_features |= NETIF_F_RXCSUM;
3957 netdev->vlan_features |= NETIF_F_RXHASH;
3958
3959 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3960 netdev->vlan_features |= NETIF_F_LRO;
3961
3962 netdev->hw_features = netdev->vlan_features;
3963 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
3964 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3965 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3966
3967 if (mlx5e_vxlan_allowed(mdev)) {
3968 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3969 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3970 NETIF_F_GSO_PARTIAL;
3971 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3972 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3973 netdev->hw_enc_features |= NETIF_F_TSO;
3974 netdev->hw_enc_features |= NETIF_F_TSO6;
3975 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3976 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3977 NETIF_F_GSO_PARTIAL;
3978 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3979 }
3980
3981 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3982
3983 if (fcs_supported)
3984 netdev->hw_features |= NETIF_F_RXALL;
3985
3986 if (MLX5_CAP_ETH(mdev, scatter_fcs))
3987 netdev->hw_features |= NETIF_F_RXFCS;
3988
3989 netdev->features = netdev->hw_features;
3990 if (!priv->channels.params.lro_en)
3991 netdev->features &= ~NETIF_F_LRO;
3992
3993 if (fcs_enabled)
3994 netdev->features &= ~NETIF_F_RXALL;
3995
3996 if (!priv->channels.params.scatter_fcs_en)
3997 netdev->features &= ~NETIF_F_RXFCS;
3998
3999 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4000 if (FT_CAP(flow_modify_en) &&
4001 FT_CAP(modify_root) &&
4002 FT_CAP(identified_miss_table_mode) &&
4003 FT_CAP(flow_table_modify)) {
4004 netdev->hw_features |= NETIF_F_HW_TC;
4005 #ifdef CONFIG_RFS_ACCEL
4006 netdev->hw_features |= NETIF_F_NTUPLE;
4007 #endif
4008 }
4009
4010 netdev->features |= NETIF_F_HIGHDMA;
4011
4012 netdev->priv_flags |= IFF_UNICAST_FLT;
4013
4014 mlx5e_set_netdev_dev_addr(netdev);
4015
4016 #ifdef CONFIG_NET_SWITCHDEV
4017 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4018 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4019 #endif
4020 }
4021
4022 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4023 {
4024 struct mlx5_core_dev *mdev = priv->mdev;
4025 int err;
4026
4027 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4028 if (err) {
4029 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4030 priv->q_counter = 0;
4031 }
4032 }
4033
4034 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4035 {
4036 if (!priv->q_counter)
4037 return;
4038
4039 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4040 }
4041
4042 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4043 struct net_device *netdev,
4044 const struct mlx5e_profile *profile,
4045 void *ppriv)
4046 {
4047 struct mlx5e_priv *priv = netdev_priv(netdev);
4048
4049 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4050 mlx5e_build_nic_netdev(netdev);
4051 mlx5e_vxlan_init(priv);
4052 }
4053
4054 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4055 {
4056 mlx5e_vxlan_cleanup(priv);
4057
4058 if (priv->channels.params.xdp_prog)
4059 bpf_prog_put(priv->channels.params.xdp_prog);
4060 }
4061
4062 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4063 {
4064 struct mlx5_core_dev *mdev = priv->mdev;
4065 int err;
4066
4067 err = mlx5e_create_indirect_rqt(priv);
4068 if (err)
4069 return err;
4070
4071 err = mlx5e_create_direct_rqts(priv);
4072 if (err)
4073 goto err_destroy_indirect_rqts;
4074
4075 err = mlx5e_create_indirect_tirs(priv);
4076 if (err)
4077 goto err_destroy_direct_rqts;
4078
4079 err = mlx5e_create_direct_tirs(priv);
4080 if (err)
4081 goto err_destroy_indirect_tirs;
4082
4083 err = mlx5e_create_flow_steering(priv);
4084 if (err) {
4085 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4086 goto err_destroy_direct_tirs;
4087 }
4088
4089 err = mlx5e_tc_init(priv);
4090 if (err)
4091 goto err_destroy_flow_steering;
4092
4093 return 0;
4094
4095 err_destroy_flow_steering:
4096 mlx5e_destroy_flow_steering(priv);
4097 err_destroy_direct_tirs:
4098 mlx5e_destroy_direct_tirs(priv);
4099 err_destroy_indirect_tirs:
4100 mlx5e_destroy_indirect_tirs(priv);
4101 err_destroy_direct_rqts:
4102 mlx5e_destroy_direct_rqts(priv);
4103 err_destroy_indirect_rqts:
4104 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4105 return err;
4106 }
4107
4108 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4109 {
4110 mlx5e_tc_cleanup(priv);
4111 mlx5e_destroy_flow_steering(priv);
4112 mlx5e_destroy_direct_tirs(priv);
4113 mlx5e_destroy_indirect_tirs(priv);
4114 mlx5e_destroy_direct_rqts(priv);
4115 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4116 }
4117
4118 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4119 {
4120 int err;
4121
4122 err = mlx5e_create_tises(priv);
4123 if (err) {
4124 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4125 return err;
4126 }
4127
4128 #ifdef CONFIG_MLX5_CORE_EN_DCB
4129 mlx5e_dcbnl_initialize(priv);
4130 #endif
4131 return 0;
4132 }
4133
4134 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4135 {
4136 struct net_device *netdev = priv->netdev;
4137 struct mlx5_core_dev *mdev = priv->mdev;
4138 u16 max_mtu;
4139
4140 mlx5e_init_l2_addr(priv);
4141
4142 /* MTU range: 68 - hw-specific max */
4143 netdev->min_mtu = ETH_MIN_MTU;
4144 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4145 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
4146 mlx5e_set_dev_port_mtu(priv);
4147
4148 mlx5_lag_add(mdev, netdev);
4149
4150 mlx5e_enable_async_events(priv);
4151
4152 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4153 mlx5e_register_vport_reps(priv);
4154
4155 if (netdev->reg_state != NETREG_REGISTERED)
4156 return;
4157
4158 /* Device already registered: sync netdev system state */
4159 if (mlx5e_vxlan_allowed(mdev)) {
4160 rtnl_lock();
4161 udp_tunnel_get_rx_info(netdev);
4162 rtnl_unlock();
4163 }
4164
4165 queue_work(priv->wq, &priv->set_rx_mode_work);
4166
4167 rtnl_lock();
4168 if (netif_running(netdev))
4169 mlx5e_open(netdev);
4170 netif_device_attach(netdev);
4171 rtnl_unlock();
4172 }
4173
4174 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4175 {
4176 struct mlx5_core_dev *mdev = priv->mdev;
4177
4178 rtnl_lock();
4179 if (netif_running(priv->netdev))
4180 mlx5e_close(priv->netdev);
4181 netif_device_detach(priv->netdev);
4182 rtnl_unlock();
4183
4184 queue_work(priv->wq, &priv->set_rx_mode_work);
4185
4186 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4187 mlx5e_unregister_vport_reps(priv);
4188
4189 mlx5e_disable_async_events(priv);
4190 mlx5_lag_remove(mdev);
4191 }
4192
4193 static const struct mlx5e_profile mlx5e_nic_profile = {
4194 .init = mlx5e_nic_init,
4195 .cleanup = mlx5e_nic_cleanup,
4196 .init_rx = mlx5e_init_nic_rx,
4197 .cleanup_rx = mlx5e_cleanup_nic_rx,
4198 .init_tx = mlx5e_init_nic_tx,
4199 .cleanup_tx = mlx5e_cleanup_nic_tx,
4200 .enable = mlx5e_nic_enable,
4201 .disable = mlx5e_nic_disable,
4202 .update_stats = mlx5e_update_stats,
4203 .max_nch = mlx5e_get_max_num_channels,
4204 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4205 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4206 .max_tc = MLX5E_MAX_NUM_TC,
4207 };
4208
4209 /* mlx5e generic netdev management API (move to en_common.c) */
4210
4211 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4212 const struct mlx5e_profile *profile,
4213 void *ppriv)
4214 {
4215 int nch = profile->max_nch(mdev);
4216 struct net_device *netdev;
4217 struct mlx5e_priv *priv;
4218
4219 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4220 nch * profile->max_tc,
4221 nch);
4222 if (!netdev) {
4223 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4224 return NULL;
4225 }
4226
4227 #ifdef CONFIG_RFS_ACCEL
4228 netdev->rx_cpu_rmap = mdev->rmap;
4229 #endif
4230
4231 profile->init(mdev, netdev, profile, ppriv);
4232
4233 netif_carrier_off(netdev);
4234
4235 priv = netdev_priv(netdev);
4236
4237 priv->wq = create_singlethread_workqueue("mlx5e");
4238 if (!priv->wq)
4239 goto err_cleanup_nic;
4240
4241 return netdev;
4242
4243 err_cleanup_nic:
4244 if (profile->cleanup)
4245 profile->cleanup(priv);
4246 free_netdev(netdev);
4247
4248 return NULL;
4249 }
4250
4251 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4252 {
4253 struct mlx5_core_dev *mdev = priv->mdev;
4254 const struct mlx5e_profile *profile;
4255 int err;
4256
4257 profile = priv->profile;
4258 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4259
4260 err = profile->init_tx(priv);
4261 if (err)
4262 goto out;
4263
4264 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
4265 if (err) {
4266 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4267 goto err_cleanup_tx;
4268 }
4269
4270 err = profile->init_rx(priv);
4271 if (err)
4272 goto err_close_drop_rq;
4273
4274 mlx5e_create_q_counter(priv);
4275
4276 if (profile->enable)
4277 profile->enable(priv);
4278
4279 return 0;
4280
4281 err_close_drop_rq:
4282 mlx5e_close_drop_rq(&priv->drop_rq);
4283
4284 err_cleanup_tx:
4285 profile->cleanup_tx(priv);
4286
4287 out:
4288 return err;
4289 }
4290
4291 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4292 {
4293 const struct mlx5e_profile *profile = priv->profile;
4294
4295 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4296
4297 if (profile->disable)
4298 profile->disable(priv);
4299 flush_workqueue(priv->wq);
4300
4301 mlx5e_destroy_q_counter(priv);
4302 profile->cleanup_rx(priv);
4303 mlx5e_close_drop_rq(&priv->drop_rq);
4304 profile->cleanup_tx(priv);
4305 cancel_delayed_work_sync(&priv->update_stats_work);
4306 }
4307
4308 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4309 {
4310 const struct mlx5e_profile *profile = priv->profile;
4311 struct net_device *netdev = priv->netdev;
4312
4313 destroy_workqueue(priv->wq);
4314 if (profile->cleanup)
4315 profile->cleanup(priv);
4316 free_netdev(netdev);
4317 }
4318
4319 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4320 * hardware contexts and to connect it to the current netdev.
4321 */
4322 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4323 {
4324 struct mlx5e_priv *priv = vpriv;
4325 struct net_device *netdev = priv->netdev;
4326 int err;
4327
4328 if (netif_device_present(netdev))
4329 return 0;
4330
4331 err = mlx5e_create_mdev_resources(mdev);
4332 if (err)
4333 return err;
4334
4335 err = mlx5e_attach_netdev(priv);
4336 if (err) {
4337 mlx5e_destroy_mdev_resources(mdev);
4338 return err;
4339 }
4340
4341 return 0;
4342 }
4343
4344 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4345 {
4346 struct mlx5e_priv *priv = vpriv;
4347 struct net_device *netdev = priv->netdev;
4348
4349 if (!netif_device_present(netdev))
4350 return;
4351
4352 mlx5e_detach_netdev(priv);
4353 mlx5e_destroy_mdev_resources(mdev);
4354 }
4355
4356 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4357 {
4358 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4359 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4360 struct mlx5e_rep_priv *rpriv = NULL;
4361 void *priv;
4362 int vport;
4363 int err;
4364 struct net_device *netdev;
4365
4366 err = mlx5e_check_required_hca_cap(mdev);
4367 if (err)
4368 return NULL;
4369
4370 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
4371 rpriv = kzalloc(sizeof(*rpriv), GFP_KERNEL);
4372 if (!rpriv) {
4373 mlx5_core_warn(mdev,
4374 "Not creating net device, Failed to alloc rep priv data\n");
4375 return NULL;
4376 }
4377 rpriv->rep = &esw->offloads.vport_reps[0];
4378 }
4379
4380 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4381 if (!netdev) {
4382 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4383 goto err_unregister_reps;
4384 }
4385
4386 priv = netdev_priv(netdev);
4387
4388 err = mlx5e_attach(mdev, priv);
4389 if (err) {
4390 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4391 goto err_destroy_netdev;
4392 }
4393
4394 err = register_netdev(netdev);
4395 if (err) {
4396 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4397 goto err_detach;
4398 }
4399
4400 return priv;
4401
4402 err_detach:
4403 mlx5e_detach(mdev, priv);
4404
4405 err_destroy_netdev:
4406 mlx5e_destroy_netdev(priv);
4407
4408 err_unregister_reps:
4409 for (vport = 1; vport < total_vfs; vport++)
4410 mlx5_eswitch_unregister_vport_rep(esw, vport);
4411
4412 kfree(rpriv);
4413 return NULL;
4414 }
4415
4416 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4417 {
4418 struct mlx5e_priv *priv = vpriv;
4419 void *ppriv = priv->ppriv;
4420
4421 unregister_netdev(priv->netdev);
4422 mlx5e_detach(mdev, vpriv);
4423 mlx5e_destroy_netdev(priv);
4424 kfree(ppriv);
4425 }
4426
4427 static void *mlx5e_get_netdev(void *vpriv)
4428 {
4429 struct mlx5e_priv *priv = vpriv;
4430
4431 return priv->netdev;
4432 }
4433
4434 static struct mlx5_interface mlx5e_interface = {
4435 .add = mlx5e_add,
4436 .remove = mlx5e_remove,
4437 .attach = mlx5e_attach,
4438 .detach = mlx5e_detach,
4439 .event = mlx5e_async_event,
4440 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4441 .get_dev = mlx5e_get_netdev,
4442 };
4443
4444 void mlx5e_init(void)
4445 {
4446 mlx5e_build_ptys2ethtool_map();
4447 mlx5_register_interface(&mlx5e_interface);
4448 }
4449
4450 void mlx5e_cleanup(void)
4451 {
4452 mlx5_unregister_interface(&mlx5e_interface);
4453 }