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Merge 4.14.23 into android-4.14
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_dcbnl.c
1 /*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #include <linux/device.h>
33 #include <linux/netdevice.h>
34 #include "en.h"
35
36 #define MLX5E_MAX_PRIORITY 8
37
38 #define MLX5E_100MB (100000)
39 #define MLX5E_1GB (1000000)
40
41 #define MLX5E_CEE_STATE_UP 1
42 #define MLX5E_CEE_STATE_DOWN 0
43
44 enum {
45 MLX5E_VENDOR_TC_GROUP_NUM = 7,
46 MLX5E_LOWEST_PRIO_GROUP = 0,
47 };
48
49 /* If dcbx mode is non-host set the dcbx mode to host.
50 */
51 static int mlx5e_dcbnl_set_dcbx_mode(struct mlx5e_priv *priv,
52 enum mlx5_dcbx_oper_mode mode)
53 {
54 struct mlx5_core_dev *mdev = priv->mdev;
55 u32 param[MLX5_ST_SZ_DW(dcbx_param)];
56 int err;
57
58 err = mlx5_query_port_dcbx_param(mdev, param);
59 if (err)
60 return err;
61
62 MLX5_SET(dcbx_param, param, version_admin, mode);
63 if (mode != MLX5E_DCBX_PARAM_VER_OPER_HOST)
64 MLX5_SET(dcbx_param, param, willing_admin, 1);
65
66 return mlx5_set_port_dcbx_param(mdev, param);
67 }
68
69 static int mlx5e_dcbnl_switch_to_host_mode(struct mlx5e_priv *priv)
70 {
71 struct mlx5e_dcbx *dcbx = &priv->dcbx;
72 int err;
73
74 if (!MLX5_CAP_GEN(priv->mdev, dcbx))
75 return 0;
76
77 if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
78 return 0;
79
80 err = mlx5e_dcbnl_set_dcbx_mode(priv, MLX5E_DCBX_PARAM_VER_OPER_HOST);
81 if (err)
82 return err;
83
84 dcbx->mode = MLX5E_DCBX_PARAM_VER_OPER_HOST;
85 return 0;
86 }
87
88 static int mlx5e_dcbnl_ieee_getets(struct net_device *netdev,
89 struct ieee_ets *ets)
90 {
91 struct mlx5e_priv *priv = netdev_priv(netdev);
92 struct mlx5_core_dev *mdev = priv->mdev;
93 u8 tc_group[IEEE_8021QAZ_MAX_TCS];
94 bool is_tc_group_6_exist = false;
95 bool is_zero_bw_ets_tc = false;
96 int err = 0;
97 int i;
98
99 if (!MLX5_CAP_GEN(priv->mdev, ets))
100 return -EOPNOTSUPP;
101
102 ets->ets_cap = mlx5_max_tc(priv->mdev) + 1;
103 for (i = 0; i < ets->ets_cap; i++) {
104 err = mlx5_query_port_prio_tc(mdev, i, &ets->prio_tc[i]);
105 if (err)
106 return err;
107
108 err = mlx5_query_port_tc_group(mdev, i, &tc_group[i]);
109 if (err)
110 return err;
111
112 err = mlx5_query_port_tc_bw_alloc(mdev, i, &ets->tc_tx_bw[i]);
113 if (err)
114 return err;
115
116 if (ets->tc_tx_bw[i] < MLX5E_MAX_BW_ALLOC &&
117 tc_group[i] == (MLX5E_LOWEST_PRIO_GROUP + 1))
118 is_zero_bw_ets_tc = true;
119
120 if (tc_group[i] == (MLX5E_VENDOR_TC_GROUP_NUM - 1))
121 is_tc_group_6_exist = true;
122 }
123
124 /* Report 0% ets tc if exits*/
125 if (is_zero_bw_ets_tc) {
126 for (i = 0; i < ets->ets_cap; i++)
127 if (tc_group[i] == MLX5E_LOWEST_PRIO_GROUP)
128 ets->tc_tx_bw[i] = 0;
129 }
130
131 /* Update tc_tsa based on fw setting*/
132 for (i = 0; i < ets->ets_cap; i++) {
133 if (ets->tc_tx_bw[i] < MLX5E_MAX_BW_ALLOC)
134 priv->dcbx.tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
135 else if (tc_group[i] == MLX5E_VENDOR_TC_GROUP_NUM &&
136 !is_tc_group_6_exist)
137 priv->dcbx.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
138 }
139 memcpy(ets->tc_tsa, priv->dcbx.tc_tsa, sizeof(ets->tc_tsa));
140
141 return err;
142 }
143
144 static void mlx5e_build_tc_group(struct ieee_ets *ets, u8 *tc_group, int max_tc)
145 {
146 bool any_tc_mapped_to_ets = false;
147 bool ets_zero_bw = false;
148 int strict_group;
149 int i;
150
151 for (i = 0; i <= max_tc; i++) {
152 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) {
153 any_tc_mapped_to_ets = true;
154 if (!ets->tc_tx_bw[i])
155 ets_zero_bw = true;
156 }
157 }
158
159 /* strict group has higher priority than ets group */
160 strict_group = MLX5E_LOWEST_PRIO_GROUP;
161 if (any_tc_mapped_to_ets)
162 strict_group++;
163 if (ets_zero_bw)
164 strict_group++;
165
166 for (i = 0; i <= max_tc; i++) {
167 switch (ets->tc_tsa[i]) {
168 case IEEE_8021QAZ_TSA_VENDOR:
169 tc_group[i] = MLX5E_VENDOR_TC_GROUP_NUM;
170 break;
171 case IEEE_8021QAZ_TSA_STRICT:
172 tc_group[i] = strict_group++;
173 break;
174 case IEEE_8021QAZ_TSA_ETS:
175 tc_group[i] = MLX5E_LOWEST_PRIO_GROUP;
176 if (ets->tc_tx_bw[i] && ets_zero_bw)
177 tc_group[i] = MLX5E_LOWEST_PRIO_GROUP + 1;
178 break;
179 }
180 }
181 }
182
183 static void mlx5e_build_tc_tx_bw(struct ieee_ets *ets, u8 *tc_tx_bw,
184 u8 *tc_group, int max_tc)
185 {
186 int bw_for_ets_zero_bw_tc = 0;
187 int last_ets_zero_bw_tc = -1;
188 int num_ets_zero_bw = 0;
189 int i;
190
191 for (i = 0; i <= max_tc; i++) {
192 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS &&
193 !ets->tc_tx_bw[i]) {
194 num_ets_zero_bw++;
195 last_ets_zero_bw_tc = i;
196 }
197 }
198
199 if (num_ets_zero_bw)
200 bw_for_ets_zero_bw_tc = MLX5E_MAX_BW_ALLOC / num_ets_zero_bw;
201
202 for (i = 0; i <= max_tc; i++) {
203 switch (ets->tc_tsa[i]) {
204 case IEEE_8021QAZ_TSA_VENDOR:
205 tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
206 break;
207 case IEEE_8021QAZ_TSA_STRICT:
208 tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
209 break;
210 case IEEE_8021QAZ_TSA_ETS:
211 tc_tx_bw[i] = ets->tc_tx_bw[i] ?
212 ets->tc_tx_bw[i] :
213 bw_for_ets_zero_bw_tc;
214 break;
215 }
216 }
217
218 /* Make sure the total bw for ets zero bw group is 100% */
219 if (last_ets_zero_bw_tc != -1)
220 tc_tx_bw[last_ets_zero_bw_tc] +=
221 MLX5E_MAX_BW_ALLOC % num_ets_zero_bw;
222 }
223
224 /* If there are ETS BW 0,
225 * Set ETS group # to 1 for all ETS non zero BW tcs. Their sum must be 100%.
226 * Set group #0 to all the ETS BW 0 tcs and
227 * equally splits the 100% BW between them
228 * Report both group #0 and #1 as ETS type.
229 * All the tcs in group #0 will be reported with 0% BW.
230 */
231 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets)
232 {
233 struct mlx5_core_dev *mdev = priv->mdev;
234 u8 tc_tx_bw[IEEE_8021QAZ_MAX_TCS];
235 u8 tc_group[IEEE_8021QAZ_MAX_TCS];
236 int max_tc = mlx5_max_tc(mdev);
237 int err;
238
239 mlx5e_build_tc_group(ets, tc_group, max_tc);
240 mlx5e_build_tc_tx_bw(ets, tc_tx_bw, tc_group, max_tc);
241
242 err = mlx5_set_port_prio_tc(mdev, ets->prio_tc);
243 if (err)
244 return err;
245
246 err = mlx5_set_port_tc_group(mdev, tc_group);
247 if (err)
248 return err;
249
250 err = mlx5_set_port_tc_bw_alloc(mdev, tc_tx_bw);
251
252 if (err)
253 return err;
254
255 memcpy(priv->dcbx.tc_tsa, ets->tc_tsa, sizeof(ets->tc_tsa));
256 return err;
257 }
258
259 static int mlx5e_dbcnl_validate_ets(struct net_device *netdev,
260 struct ieee_ets *ets)
261 {
262 int bw_sum = 0;
263 int i;
264
265 /* Validate Priority */
266 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
267 if (ets->prio_tc[i] >= MLX5E_MAX_PRIORITY) {
268 netdev_err(netdev,
269 "Failed to validate ETS: priority value greater than max(%d)\n",
270 MLX5E_MAX_PRIORITY);
271 return -EINVAL;
272 }
273 }
274
275 /* Validate Bandwidth Sum */
276 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
277 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS)
278 bw_sum += ets->tc_tx_bw[i];
279
280 if (bw_sum != 0 && bw_sum != 100) {
281 netdev_err(netdev,
282 "Failed to validate ETS: BW sum is illegal\n");
283 return -EINVAL;
284 }
285 return 0;
286 }
287
288 static int mlx5e_dcbnl_ieee_setets(struct net_device *netdev,
289 struct ieee_ets *ets)
290 {
291 struct mlx5e_priv *priv = netdev_priv(netdev);
292 int err;
293
294 if (!MLX5_CAP_GEN(priv->mdev, ets))
295 return -EOPNOTSUPP;
296
297 err = mlx5e_dbcnl_validate_ets(netdev, ets);
298 if (err)
299 return err;
300
301 err = mlx5e_dcbnl_ieee_setets_core(priv, ets);
302 if (err)
303 return err;
304
305 return 0;
306 }
307
308 static int mlx5e_dcbnl_ieee_getpfc(struct net_device *dev,
309 struct ieee_pfc *pfc)
310 {
311 struct mlx5e_priv *priv = netdev_priv(dev);
312 struct mlx5_core_dev *mdev = priv->mdev;
313 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
314 int i;
315
316 pfc->pfc_cap = mlx5_max_tc(mdev) + 1;
317 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
318 pfc->requests[i] = PPORT_PER_PRIO_GET(pstats, i, tx_pause);
319 pfc->indications[i] = PPORT_PER_PRIO_GET(pstats, i, rx_pause);
320 }
321
322 return mlx5_query_port_pfc(mdev, &pfc->pfc_en, NULL);
323 }
324
325 static int mlx5e_dcbnl_ieee_setpfc(struct net_device *dev,
326 struct ieee_pfc *pfc)
327 {
328 struct mlx5e_priv *priv = netdev_priv(dev);
329 struct mlx5_core_dev *mdev = priv->mdev;
330 u8 curr_pfc_en;
331 int ret;
332
333 mlx5_query_port_pfc(mdev, &curr_pfc_en, NULL);
334
335 if (pfc->pfc_en == curr_pfc_en)
336 return 0;
337
338 ret = mlx5_set_port_pfc(mdev, pfc->pfc_en, pfc->pfc_en);
339 mlx5_toggle_port_link(mdev);
340
341 return ret;
342 }
343
344 static u8 mlx5e_dcbnl_getdcbx(struct net_device *dev)
345 {
346 struct mlx5e_priv *priv = netdev_priv(dev);
347
348 return priv->dcbx.cap;
349 }
350
351 static u8 mlx5e_dcbnl_setdcbx(struct net_device *dev, u8 mode)
352 {
353 struct mlx5e_priv *priv = netdev_priv(dev);
354 struct mlx5e_dcbx *dcbx = &priv->dcbx;
355
356 if (mode & DCB_CAP_DCBX_LLD_MANAGED)
357 return 1;
358
359 if ((!mode) && MLX5_CAP_GEN(priv->mdev, dcbx)) {
360 if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_AUTO)
361 return 0;
362
363 /* set dcbx to fw controlled */
364 if (!mlx5e_dcbnl_set_dcbx_mode(priv, MLX5E_DCBX_PARAM_VER_OPER_AUTO)) {
365 dcbx->mode = MLX5E_DCBX_PARAM_VER_OPER_AUTO;
366 dcbx->cap &= ~DCB_CAP_DCBX_HOST;
367 return 0;
368 }
369
370 return 1;
371 }
372
373 if (!(mode & DCB_CAP_DCBX_HOST))
374 return 1;
375
376 if (mlx5e_dcbnl_switch_to_host_mode(netdev_priv(dev)))
377 return 1;
378
379 dcbx->cap = mode;
380
381 return 0;
382 }
383
384 static int mlx5e_dcbnl_ieee_getmaxrate(struct net_device *netdev,
385 struct ieee_maxrate *maxrate)
386 {
387 struct mlx5e_priv *priv = netdev_priv(netdev);
388 struct mlx5_core_dev *mdev = priv->mdev;
389 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
390 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
391 int err;
392 int i;
393
394 err = mlx5_query_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit);
395 if (err)
396 return err;
397
398 memset(maxrate->tc_maxrate, 0, sizeof(maxrate->tc_maxrate));
399
400 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
401 switch (max_bw_unit[i]) {
402 case MLX5_100_MBPS_UNIT:
403 maxrate->tc_maxrate[i] = max_bw_value[i] * MLX5E_100MB;
404 break;
405 case MLX5_GBPS_UNIT:
406 maxrate->tc_maxrate[i] = max_bw_value[i] * MLX5E_1GB;
407 break;
408 case MLX5_BW_NO_LIMIT:
409 break;
410 default:
411 WARN(true, "non-supported BW unit");
412 break;
413 }
414 }
415
416 return 0;
417 }
418
419 static int mlx5e_dcbnl_ieee_setmaxrate(struct net_device *netdev,
420 struct ieee_maxrate *maxrate)
421 {
422 struct mlx5e_priv *priv = netdev_priv(netdev);
423 struct mlx5_core_dev *mdev = priv->mdev;
424 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
425 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
426 __u64 upper_limit_mbps = roundup(255 * MLX5E_100MB, MLX5E_1GB);
427 int i;
428
429 memset(max_bw_value, 0, sizeof(max_bw_value));
430 memset(max_bw_unit, 0, sizeof(max_bw_unit));
431
432 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
433 if (!maxrate->tc_maxrate[i]) {
434 max_bw_unit[i] = MLX5_BW_NO_LIMIT;
435 continue;
436 }
437 if (maxrate->tc_maxrate[i] < upper_limit_mbps) {
438 max_bw_value[i] = div_u64(maxrate->tc_maxrate[i],
439 MLX5E_100MB);
440 max_bw_value[i] = max_bw_value[i] ? max_bw_value[i] : 1;
441 max_bw_unit[i] = MLX5_100_MBPS_UNIT;
442 } else {
443 max_bw_value[i] = div_u64(maxrate->tc_maxrate[i],
444 MLX5E_1GB);
445 max_bw_unit[i] = MLX5_GBPS_UNIT;
446 }
447 }
448
449 return mlx5_modify_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit);
450 }
451
452 static u8 mlx5e_dcbnl_setall(struct net_device *netdev)
453 {
454 struct mlx5e_priv *priv = netdev_priv(netdev);
455 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
456 struct mlx5_core_dev *mdev = priv->mdev;
457 struct ieee_ets ets;
458 struct ieee_pfc pfc;
459 int err = -EOPNOTSUPP;
460 int i;
461
462 if (!MLX5_CAP_GEN(mdev, ets))
463 goto out;
464
465 memset(&ets, 0, sizeof(ets));
466 memset(&pfc, 0, sizeof(pfc));
467
468 ets.ets_cap = IEEE_8021QAZ_MAX_TCS;
469 for (i = 0; i < CEE_DCBX_MAX_PGS; i++) {
470 ets.tc_tx_bw[i] = cee_cfg->pg_bw_pct[i];
471 ets.tc_rx_bw[i] = cee_cfg->pg_bw_pct[i];
472 ets.tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
473 ets.prio_tc[i] = cee_cfg->prio_to_pg_map[i];
474 }
475
476 err = mlx5e_dbcnl_validate_ets(netdev, &ets);
477 if (err) {
478 netdev_err(netdev,
479 "%s, Failed to validate ETS: %d\n", __func__, err);
480 goto out;
481 }
482
483 err = mlx5e_dcbnl_ieee_setets_core(priv, &ets);
484 if (err) {
485 netdev_err(netdev,
486 "%s, Failed to set ETS: %d\n", __func__, err);
487 goto out;
488 }
489
490 /* Set PFC */
491 pfc.pfc_cap = mlx5_max_tc(mdev) + 1;
492 if (!cee_cfg->pfc_enable)
493 pfc.pfc_en = 0;
494 else
495 for (i = 0; i < CEE_DCBX_MAX_PRIO; i++)
496 pfc.pfc_en |= cee_cfg->pfc_setting[i] << i;
497
498 err = mlx5e_dcbnl_ieee_setpfc(netdev, &pfc);
499 if (err) {
500 netdev_err(netdev,
501 "%s, Failed to set PFC: %d\n", __func__, err);
502 goto out;
503 }
504 out:
505 return err ? MLX5_DCB_NO_CHG : MLX5_DCB_CHG_RESET;
506 }
507
508 static u8 mlx5e_dcbnl_getstate(struct net_device *netdev)
509 {
510 return MLX5E_CEE_STATE_UP;
511 }
512
513 static void mlx5e_dcbnl_getpermhwaddr(struct net_device *netdev,
514 u8 *perm_addr)
515 {
516 struct mlx5e_priv *priv = netdev_priv(netdev);
517
518 if (!perm_addr)
519 return;
520
521 memset(perm_addr, 0xff, MAX_ADDR_LEN);
522
523 mlx5_query_nic_vport_mac_address(priv->mdev, 0, perm_addr);
524 }
525
526 static void mlx5e_dcbnl_setpgtccfgtx(struct net_device *netdev,
527 int priority, u8 prio_type,
528 u8 pgid, u8 bw_pct, u8 up_map)
529 {
530 struct mlx5e_priv *priv = netdev_priv(netdev);
531 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
532
533 if (priority >= CEE_DCBX_MAX_PRIO) {
534 netdev_err(netdev,
535 "%s, priority is out of range\n", __func__);
536 return;
537 }
538
539 if (pgid >= CEE_DCBX_MAX_PGS) {
540 netdev_err(netdev,
541 "%s, priority group is out of range\n", __func__);
542 return;
543 }
544
545 cee_cfg->prio_to_pg_map[priority] = pgid;
546 }
547
548 static void mlx5e_dcbnl_setpgbwgcfgtx(struct net_device *netdev,
549 int pgid, u8 bw_pct)
550 {
551 struct mlx5e_priv *priv = netdev_priv(netdev);
552 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
553
554 if (pgid >= CEE_DCBX_MAX_PGS) {
555 netdev_err(netdev,
556 "%s, priority group is out of range\n", __func__);
557 return;
558 }
559
560 cee_cfg->pg_bw_pct[pgid] = bw_pct;
561 }
562
563 static void mlx5e_dcbnl_getpgtccfgtx(struct net_device *netdev,
564 int priority, u8 *prio_type,
565 u8 *pgid, u8 *bw_pct, u8 *up_map)
566 {
567 struct mlx5e_priv *priv = netdev_priv(netdev);
568 struct mlx5_core_dev *mdev = priv->mdev;
569
570 if (!MLX5_CAP_GEN(priv->mdev, ets)) {
571 netdev_err(netdev, "%s, ets is not supported\n", __func__);
572 return;
573 }
574
575 if (priority >= CEE_DCBX_MAX_PRIO) {
576 netdev_err(netdev,
577 "%s, priority is out of range\n", __func__);
578 return;
579 }
580
581 *prio_type = 0;
582 *bw_pct = 0;
583 *up_map = 0;
584
585 if (mlx5_query_port_prio_tc(mdev, priority, pgid))
586 *pgid = 0;
587 }
588
589 static void mlx5e_dcbnl_getpgbwgcfgtx(struct net_device *netdev,
590 int pgid, u8 *bw_pct)
591 {
592 struct ieee_ets ets;
593
594 if (pgid >= CEE_DCBX_MAX_PGS) {
595 netdev_err(netdev,
596 "%s, priority group is out of range\n", __func__);
597 return;
598 }
599
600 mlx5e_dcbnl_ieee_getets(netdev, &ets);
601 *bw_pct = ets.tc_tx_bw[pgid];
602 }
603
604 static void mlx5e_dcbnl_setpfccfg(struct net_device *netdev,
605 int priority, u8 setting)
606 {
607 struct mlx5e_priv *priv = netdev_priv(netdev);
608 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
609
610 if (priority >= CEE_DCBX_MAX_PRIO) {
611 netdev_err(netdev,
612 "%s, priority is out of range\n", __func__);
613 return;
614 }
615
616 if (setting > 1)
617 return;
618
619 cee_cfg->pfc_setting[priority] = setting;
620 }
621
622 static int
623 mlx5e_dcbnl_get_priority_pfc(struct net_device *netdev,
624 int priority, u8 *setting)
625 {
626 struct ieee_pfc pfc;
627 int err;
628
629 err = mlx5e_dcbnl_ieee_getpfc(netdev, &pfc);
630
631 if (err)
632 *setting = 0;
633 else
634 *setting = (pfc.pfc_en >> priority) & 0x01;
635
636 return err;
637 }
638
639 static void mlx5e_dcbnl_getpfccfg(struct net_device *netdev,
640 int priority, u8 *setting)
641 {
642 if (priority >= CEE_DCBX_MAX_PRIO) {
643 netdev_err(netdev,
644 "%s, priority is out of range\n", __func__);
645 return;
646 }
647
648 if (!setting)
649 return;
650
651 mlx5e_dcbnl_get_priority_pfc(netdev, priority, setting);
652 }
653
654 static u8 mlx5e_dcbnl_getcap(struct net_device *netdev,
655 int capid, u8 *cap)
656 {
657 struct mlx5e_priv *priv = netdev_priv(netdev);
658 struct mlx5_core_dev *mdev = priv->mdev;
659 u8 rval = 0;
660
661 switch (capid) {
662 case DCB_CAP_ATTR_PG:
663 *cap = true;
664 break;
665 case DCB_CAP_ATTR_PFC:
666 *cap = true;
667 break;
668 case DCB_CAP_ATTR_UP2TC:
669 *cap = false;
670 break;
671 case DCB_CAP_ATTR_PG_TCS:
672 *cap = 1 << mlx5_max_tc(mdev);
673 break;
674 case DCB_CAP_ATTR_PFC_TCS:
675 *cap = 1 << mlx5_max_tc(mdev);
676 break;
677 case DCB_CAP_ATTR_GSP:
678 *cap = false;
679 break;
680 case DCB_CAP_ATTR_BCN:
681 *cap = false;
682 break;
683 case DCB_CAP_ATTR_DCBX:
684 *cap = priv->dcbx.cap |
685 DCB_CAP_DCBX_VER_CEE |
686 DCB_CAP_DCBX_VER_IEEE;
687 break;
688 default:
689 *cap = 0;
690 rval = 1;
691 break;
692 }
693
694 return rval;
695 }
696
697 static int mlx5e_dcbnl_getnumtcs(struct net_device *netdev,
698 int tcs_id, u8 *num)
699 {
700 struct mlx5e_priv *priv = netdev_priv(netdev);
701 struct mlx5_core_dev *mdev = priv->mdev;
702
703 switch (tcs_id) {
704 case DCB_NUMTCS_ATTR_PG:
705 case DCB_NUMTCS_ATTR_PFC:
706 *num = mlx5_max_tc(mdev) + 1;
707 break;
708 default:
709 return -EINVAL;
710 }
711
712 return 0;
713 }
714
715 static u8 mlx5e_dcbnl_getpfcstate(struct net_device *netdev)
716 {
717 struct ieee_pfc pfc;
718
719 if (mlx5e_dcbnl_ieee_getpfc(netdev, &pfc))
720 return MLX5E_CEE_STATE_DOWN;
721
722 return pfc.pfc_en ? MLX5E_CEE_STATE_UP : MLX5E_CEE_STATE_DOWN;
723 }
724
725 static void mlx5e_dcbnl_setpfcstate(struct net_device *netdev, u8 state)
726 {
727 struct mlx5e_priv *priv = netdev_priv(netdev);
728 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
729
730 if ((state != MLX5E_CEE_STATE_UP) && (state != MLX5E_CEE_STATE_DOWN))
731 return;
732
733 cee_cfg->pfc_enable = state;
734 }
735
736 const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops = {
737 .ieee_getets = mlx5e_dcbnl_ieee_getets,
738 .ieee_setets = mlx5e_dcbnl_ieee_setets,
739 .ieee_getmaxrate = mlx5e_dcbnl_ieee_getmaxrate,
740 .ieee_setmaxrate = mlx5e_dcbnl_ieee_setmaxrate,
741 .ieee_getpfc = mlx5e_dcbnl_ieee_getpfc,
742 .ieee_setpfc = mlx5e_dcbnl_ieee_setpfc,
743 .getdcbx = mlx5e_dcbnl_getdcbx,
744 .setdcbx = mlx5e_dcbnl_setdcbx,
745
746 /* CEE interfaces */
747 .setall = mlx5e_dcbnl_setall,
748 .getstate = mlx5e_dcbnl_getstate,
749 .getpermhwaddr = mlx5e_dcbnl_getpermhwaddr,
750
751 .setpgtccfgtx = mlx5e_dcbnl_setpgtccfgtx,
752 .setpgbwgcfgtx = mlx5e_dcbnl_setpgbwgcfgtx,
753 .getpgtccfgtx = mlx5e_dcbnl_getpgtccfgtx,
754 .getpgbwgcfgtx = mlx5e_dcbnl_getpgbwgcfgtx,
755
756 .setpfccfg = mlx5e_dcbnl_setpfccfg,
757 .getpfccfg = mlx5e_dcbnl_getpfccfg,
758 .getcap = mlx5e_dcbnl_getcap,
759 .getnumtcs = mlx5e_dcbnl_getnumtcs,
760 .getpfcstate = mlx5e_dcbnl_getpfcstate,
761 .setpfcstate = mlx5e_dcbnl_setpfcstate,
762 };
763
764 static void mlx5e_dcbnl_query_dcbx_mode(struct mlx5e_priv *priv,
765 enum mlx5_dcbx_oper_mode *mode)
766 {
767 u32 out[MLX5_ST_SZ_DW(dcbx_param)];
768
769 *mode = MLX5E_DCBX_PARAM_VER_OPER_HOST;
770
771 if (!mlx5_query_port_dcbx_param(priv->mdev, out))
772 *mode = MLX5_GET(dcbx_param, out, version_oper);
773
774 /* From driver's point of view, we only care if the mode
775 * is host (HOST) or non-host (AUTO)
776 */
777 if (*mode != MLX5E_DCBX_PARAM_VER_OPER_HOST)
778 *mode = MLX5E_DCBX_PARAM_VER_OPER_AUTO;
779 }
780
781 static void mlx5e_ets_init(struct mlx5e_priv *priv)
782 {
783 int i;
784 struct ieee_ets ets;
785
786 if (!MLX5_CAP_GEN(priv->mdev, ets))
787 return;
788
789 memset(&ets, 0, sizeof(ets));
790 ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
791 for (i = 0; i < ets.ets_cap; i++) {
792 ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
793 ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
794 ets.prio_tc[i] = i;
795 }
796
797 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
798 ets.prio_tc[0] = 1;
799 ets.prio_tc[1] = 0;
800
801 mlx5e_dcbnl_ieee_setets_core(priv, &ets);
802 }
803
804 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv)
805 {
806 struct mlx5e_dcbx *dcbx = &priv->dcbx;
807
808 if (!MLX5_CAP_GEN(priv->mdev, qos))
809 return;
810
811 if (MLX5_CAP_GEN(priv->mdev, dcbx))
812 mlx5e_dcbnl_query_dcbx_mode(priv, &dcbx->mode);
813
814 priv->dcbx.cap = DCB_CAP_DCBX_VER_CEE |
815 DCB_CAP_DCBX_VER_IEEE;
816 if (priv->dcbx.mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
817 priv->dcbx.cap |= DCB_CAP_DCBX_HOST;
818
819 mlx5e_ets_init(priv);
820 }