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Merge tag 'blackfin-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/realm...
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
39
40 #include "fw.h"
41 #include "icm.h"
42
43 enum {
44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
47 };
48
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
51
52 static bool enable_qos;
53 module_param(enable_qos, bool, 0444);
54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
56 #define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68 #define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
81 {
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
86 [ 3] = "XRC transport",
87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
94 [12] = "Dual Port Different Protocol (DPDP) support",
95 [15] = "Big LSO headers",
96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
103 [25] = "Router support",
104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
106 [34] = "FCS header control",
107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
112 [53] = "Port ETS Scheduler support",
113 [55] = "Port link type sensing support",
114 [59] = "Port management change event support",
115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
122 if (fname[i] && (flags & (1LL << i)))
123 mlx4_dbg(dev, " %s\n", fname[i]);
124 }
125
126 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127 {
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
131 [2] = "RSS XOR Hash Function support",
132 [3] = "Device manage flow steering support",
133 [4] = "Automatic MAC reassignment support",
134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
136 [7] = "FSM (MAC anti-spoofing) support",
137 [8] = "Dynamic QP updates support"
138 };
139 int i;
140
141 for (i = 0; i < ARRAY_SIZE(fname); ++i)
142 if (fname[i] && (flags & (1LL << i)))
143 mlx4_dbg(dev, " %s\n", fname[i]);
144 }
145
146 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
147 {
148 struct mlx4_cmd_mailbox *mailbox;
149 u32 *inbox;
150 int err = 0;
151
152 #define MOD_STAT_CFG_IN_SIZE 0x100
153
154 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
155 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
156
157 mailbox = mlx4_alloc_cmd_mailbox(dev);
158 if (IS_ERR(mailbox))
159 return PTR_ERR(mailbox);
160 inbox = mailbox->buf;
161
162 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
163 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
164
165 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
166 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
167
168 mlx4_free_cmd_mailbox(dev, mailbox);
169 return err;
170 }
171
172 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
173 struct mlx4_vhcr *vhcr,
174 struct mlx4_cmd_mailbox *inbox,
175 struct mlx4_cmd_mailbox *outbox,
176 struct mlx4_cmd_info *cmd)
177 {
178 struct mlx4_priv *priv = mlx4_priv(dev);
179 u8 field;
180 u32 size;
181 int err = 0;
182
183 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
184 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
185 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
186 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
187 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
188 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
189 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
190 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
191 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
192 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
193 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
194 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
195
196 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
197 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
198 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
199 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
200 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
201 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
202
203 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
204 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
205 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
206 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
207
208 /* when opcode modifier = 1 */
209 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
210 #define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8
211 #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
212
213 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
214 #define QUERY_FUNC_CAP_QP0_PROXY 0x14
215 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
216 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c
217
218 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40
219 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80
220
221 #define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80
222
223 if (vhcr->op_modifier == 1) {
224 field = 0;
225 /* ensure force vlan and force mac bits are not set */
226 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
227 /* ensure that phy_wqe_gid bit is not set */
228 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
229
230 field = vhcr->in_modifier; /* phys-port = logical-port */
231 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
232
233 /* size is now the QP number */
234 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1;
235 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
236
237 size += 2;
238 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
239
240 size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1;
241 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY);
242
243 size += 2;
244 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY);
245
246 } else if (vhcr->op_modifier == 0) {
247 /* enable rdma and ethernet interfaces, and new quota locations */
248 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
249 QUERY_FUNC_CAP_FLAG_QUOTAS);
250 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
251
252 field = dev->caps.num_ports;
253 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
254
255 size = dev->caps.function_caps; /* set PF behaviours */
256 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
257
258 field = 0; /* protected FMR support not available as yet */
259 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
260
261 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
262 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
263 size = dev->caps.num_qps;
264 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
265
266 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
267 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
268 size = dev->caps.num_srqs;
269 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
270
271 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
272 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
273 size = dev->caps.num_cqs;
274 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
275
276 size = dev->caps.num_eqs;
277 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
278
279 size = dev->caps.reserved_eqs;
280 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
281
282 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
283 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
284 size = dev->caps.num_mpts;
285 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
286
287 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
288 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
289 size = dev->caps.num_mtts;
290 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
291
292 size = dev->caps.num_mgms + dev->caps.num_amgms;
293 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
294 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
295
296 } else
297 err = -EINVAL;
298
299 return err;
300 }
301
302 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
303 struct mlx4_func_cap *func_cap)
304 {
305 struct mlx4_cmd_mailbox *mailbox;
306 u32 *outbox;
307 u8 field, op_modifier;
308 u32 size;
309 int err = 0, quotas = 0;
310
311 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
312
313 mailbox = mlx4_alloc_cmd_mailbox(dev);
314 if (IS_ERR(mailbox))
315 return PTR_ERR(mailbox);
316
317 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier,
318 MLX4_CMD_QUERY_FUNC_CAP,
319 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
320 if (err)
321 goto out;
322
323 outbox = mailbox->buf;
324
325 if (!op_modifier) {
326 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
327 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
328 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
329 err = -EPROTONOSUPPORT;
330 goto out;
331 }
332 func_cap->flags = field;
333 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
334
335 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
336 func_cap->num_ports = field;
337
338 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
339 func_cap->pf_context_behaviour = size;
340
341 if (quotas) {
342 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
343 func_cap->qp_quota = size & 0xFFFFFF;
344
345 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
346 func_cap->srq_quota = size & 0xFFFFFF;
347
348 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
349 func_cap->cq_quota = size & 0xFFFFFF;
350
351 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
352 func_cap->mpt_quota = size & 0xFFFFFF;
353
354 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
355 func_cap->mtt_quota = size & 0xFFFFFF;
356
357 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
358 func_cap->mcg_quota = size & 0xFFFFFF;
359
360 } else {
361 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
362 func_cap->qp_quota = size & 0xFFFFFF;
363
364 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
365 func_cap->srq_quota = size & 0xFFFFFF;
366
367 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
368 func_cap->cq_quota = size & 0xFFFFFF;
369
370 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
371 func_cap->mpt_quota = size & 0xFFFFFF;
372
373 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
374 func_cap->mtt_quota = size & 0xFFFFFF;
375
376 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
377 func_cap->mcg_quota = size & 0xFFFFFF;
378 }
379 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
380 func_cap->max_eq = size & 0xFFFFFF;
381
382 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
383 func_cap->reserved_eq = size & 0xFFFFFF;
384
385 goto out;
386 }
387
388 /* logical port query */
389 if (gen_or_port > dev->caps.num_ports) {
390 err = -EINVAL;
391 goto out;
392 }
393
394 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
395 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
396 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) {
397 mlx4_err(dev, "VLAN is enforced on this port\n");
398 err = -EPROTONOSUPPORT;
399 goto out;
400 }
401
402 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) {
403 mlx4_err(dev, "Force mac is enabled on this port\n");
404 err = -EPROTONOSUPPORT;
405 goto out;
406 }
407 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
408 MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
409 if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) {
410 mlx4_err(dev, "phy_wqe_gid is "
411 "enforced on this ib port\n");
412 err = -EPROTONOSUPPORT;
413 goto out;
414 }
415 }
416
417 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
418 func_cap->physical_port = field;
419 if (func_cap->physical_port != gen_or_port) {
420 err = -ENOSYS;
421 goto out;
422 }
423
424 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
425 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
426
427 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
428 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
429
430 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
431 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
432
433 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
434 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
435
436 /* All other resources are allocated by the master, but we still report
437 * 'num' and 'reserved' capabilities as follows:
438 * - num remains the maximum resource index
439 * - 'num - reserved' is the total available objects of a resource, but
440 * resource indices may be less than 'reserved'
441 * TODO: set per-resource quotas */
442
443 out:
444 mlx4_free_cmd_mailbox(dev, mailbox);
445
446 return err;
447 }
448
449 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
450 {
451 struct mlx4_cmd_mailbox *mailbox;
452 u32 *outbox;
453 u8 field;
454 u32 field32, flags, ext_flags;
455 u16 size;
456 u16 stat_rate;
457 int err;
458 int i;
459
460 #define QUERY_DEV_CAP_OUT_SIZE 0x100
461 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
462 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
463 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
464 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
465 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
466 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
467 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
468 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
469 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
470 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
471 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
472 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
473 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
474 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
475 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
476 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
477 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
478 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
479 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
480 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
481 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
482 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
483 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
484 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
485 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
486 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
487 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
488 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
489 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
490 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
491 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
492 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
493 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
494 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
495 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
496 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
497 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
498 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
499 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
500 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
501 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
502 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
503 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
504 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
505 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
506 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
507 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
508 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
509 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
510 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
511 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
512 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
513 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
514 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
515 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
516 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
517 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
518 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
519 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
520 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
521 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
522 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
523 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
524 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
525 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
526 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
527 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
528 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
529 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
530 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
531 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
532
533 dev_cap->flags2 = 0;
534 mailbox = mlx4_alloc_cmd_mailbox(dev);
535 if (IS_ERR(mailbox))
536 return PTR_ERR(mailbox);
537 outbox = mailbox->buf;
538
539 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
540 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
541 if (err)
542 goto out;
543
544 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
545 dev_cap->reserved_qps = 1 << (field & 0xf);
546 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
547 dev_cap->max_qps = 1 << (field & 0x1f);
548 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
549 dev_cap->reserved_srqs = 1 << (field >> 4);
550 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
551 dev_cap->max_srqs = 1 << (field & 0x1f);
552 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
553 dev_cap->max_cq_sz = 1 << field;
554 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
555 dev_cap->reserved_cqs = 1 << (field & 0xf);
556 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
557 dev_cap->max_cqs = 1 << (field & 0x1f);
558 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
559 dev_cap->max_mpts = 1 << (field & 0x3f);
560 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
561 dev_cap->reserved_eqs = field & 0xf;
562 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
563 dev_cap->max_eqs = 1 << (field & 0xf);
564 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
565 dev_cap->reserved_mtts = 1 << (field >> 4);
566 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
567 dev_cap->max_mrw_sz = 1 << field;
568 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
569 dev_cap->reserved_mrws = 1 << (field & 0xf);
570 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
571 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
572 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
573 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
574 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
575 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
576 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
577 field &= 0x1f;
578 if (!field)
579 dev_cap->max_gso_sz = 0;
580 else
581 dev_cap->max_gso_sz = 1 << field;
582
583 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
584 if (field & 0x20)
585 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
586 if (field & 0x10)
587 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
588 field &= 0xf;
589 if (field) {
590 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
591 dev_cap->max_rss_tbl_sz = 1 << field;
592 } else
593 dev_cap->max_rss_tbl_sz = 0;
594 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
595 dev_cap->max_rdma_global = 1 << (field & 0x3f);
596 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
597 dev_cap->local_ca_ack_delay = field & 0x1f;
598 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
599 dev_cap->num_ports = field & 0xf;
600 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
601 dev_cap->max_msg_sz = 1 << (field & 0x1f);
602 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
603 if (field & 0x80)
604 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
605 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
606 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
607 dev_cap->fs_max_num_qp_per_entry = field;
608 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
609 dev_cap->stat_rate_support = stat_rate;
610 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
611 if (field & 0x80)
612 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
613 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
614 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
615 dev_cap->flags = flags | (u64)ext_flags << 32;
616 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
617 dev_cap->reserved_uars = field >> 4;
618 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
619 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
620 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
621 dev_cap->min_page_sz = 1 << field;
622
623 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
624 if (field & 0x80) {
625 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
626 dev_cap->bf_reg_size = 1 << (field & 0x1f);
627 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
628 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
629 field = 3;
630 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
631 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
632 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
633 } else {
634 dev_cap->bf_reg_size = 0;
635 mlx4_dbg(dev, "BlueFlame not available\n");
636 }
637
638 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
639 dev_cap->max_sq_sg = field;
640 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
641 dev_cap->max_sq_desc_sz = size;
642
643 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
644 dev_cap->max_qp_per_mcg = 1 << field;
645 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
646 dev_cap->reserved_mgms = field & 0xf;
647 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
648 dev_cap->max_mcgs = 1 << field;
649 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
650 dev_cap->reserved_pds = field >> 4;
651 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
652 dev_cap->max_pds = 1 << (field & 0x3f);
653 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
654 dev_cap->reserved_xrcds = field >> 4;
655 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
656 dev_cap->max_xrcds = 1 << (field & 0x1f);
657
658 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
659 dev_cap->rdmarc_entry_sz = size;
660 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
661 dev_cap->qpc_entry_sz = size;
662 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
663 dev_cap->aux_entry_sz = size;
664 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
665 dev_cap->altc_entry_sz = size;
666 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
667 dev_cap->eqc_entry_sz = size;
668 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
669 dev_cap->cqc_entry_sz = size;
670 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
671 dev_cap->srq_entry_sz = size;
672 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
673 dev_cap->cmpt_entry_sz = size;
674 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
675 dev_cap->mtt_entry_sz = size;
676 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
677 dev_cap->dmpt_entry_sz = size;
678
679 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
680 dev_cap->max_srq_sz = 1 << field;
681 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
682 dev_cap->max_qp_sz = 1 << field;
683 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
684 dev_cap->resize_srq = field & 1;
685 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
686 dev_cap->max_rq_sg = field;
687 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
688 dev_cap->max_rq_desc_sz = size;
689
690 MLX4_GET(dev_cap->bmme_flags, outbox,
691 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
692 MLX4_GET(dev_cap->reserved_lkey, outbox,
693 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
694 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
695 if (field & 1<<6)
696 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
697 MLX4_GET(dev_cap->max_icm_sz, outbox,
698 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
699 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
700 MLX4_GET(dev_cap->max_counters, outbox,
701 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
702
703 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
704 if (field32 & (1 << 16))
705 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
706 if (field32 & (1 << 26))
707 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
708 if (field32 & (1 << 20))
709 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
710
711 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
712 for (i = 1; i <= dev_cap->num_ports; ++i) {
713 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
714 dev_cap->max_vl[i] = field >> 4;
715 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
716 dev_cap->ib_mtu[i] = field >> 4;
717 dev_cap->max_port_width[i] = field & 0xf;
718 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
719 dev_cap->max_gids[i] = 1 << (field & 0xf);
720 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
721 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
722 }
723 } else {
724 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
725 #define QUERY_PORT_MTU_OFFSET 0x01
726 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
727 #define QUERY_PORT_WIDTH_OFFSET 0x06
728 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
729 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
730 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
731 #define QUERY_PORT_MAC_OFFSET 0x10
732 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
733 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
734 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
735
736 for (i = 1; i <= dev_cap->num_ports; ++i) {
737 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
738 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
739 if (err)
740 goto out;
741
742 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
743 dev_cap->supported_port_types[i] = field & 3;
744 dev_cap->suggested_type[i] = (field >> 3) & 1;
745 dev_cap->default_sense[i] = (field >> 4) & 1;
746 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
747 dev_cap->ib_mtu[i] = field & 0xf;
748 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
749 dev_cap->max_port_width[i] = field & 0xf;
750 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
751 dev_cap->max_gids[i] = 1 << (field >> 4);
752 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
753 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
754 dev_cap->max_vl[i] = field & 0xf;
755 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
756 dev_cap->log_max_macs[i] = field & 0xf;
757 dev_cap->log_max_vlans[i] = field >> 4;
758 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
759 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
760 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
761 dev_cap->trans_type[i] = field32 >> 24;
762 dev_cap->vendor_oui[i] = field32 & 0xffffff;
763 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
764 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
765 }
766 }
767
768 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
769 dev_cap->bmme_flags, dev_cap->reserved_lkey);
770
771 /*
772 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
773 * we can't use any EQs whose doorbell falls on that page,
774 * even if the EQ itself isn't reserved.
775 */
776 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
777 dev_cap->reserved_eqs);
778
779 mlx4_dbg(dev, "Max ICM size %lld MB\n",
780 (unsigned long long) dev_cap->max_icm_sz >> 20);
781 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
782 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
783 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
784 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
785 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
786 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
787 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
788 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
789 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
790 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
791 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
792 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
793 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
794 dev_cap->max_pds, dev_cap->reserved_mgms);
795 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
796 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
797 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
798 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
799 dev_cap->max_port_width[1]);
800 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
801 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
802 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
803 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
804 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
805 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
806 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
807
808 dump_dev_cap_flags(dev, dev_cap->flags);
809 dump_dev_cap_flags2(dev, dev_cap->flags2);
810
811 out:
812 mlx4_free_cmd_mailbox(dev, mailbox);
813 return err;
814 }
815
816 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
817 struct mlx4_vhcr *vhcr,
818 struct mlx4_cmd_mailbox *inbox,
819 struct mlx4_cmd_mailbox *outbox,
820 struct mlx4_cmd_info *cmd)
821 {
822 u64 flags;
823 int err = 0;
824 u8 field;
825 u32 bmme_flags;
826
827 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
828 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
829 if (err)
830 return err;
831
832 /* add port mng change event capability and disable mw type 1
833 * unconditionally to slaves
834 */
835 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
836 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
837 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
838 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
839
840 /* For guests, disable timestamp */
841 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
842 field &= 0x7f;
843 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
844
845 /* For guests, report Blueflame disabled */
846 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
847 field &= 0x7f;
848 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
849
850 /* For guests, disable mw type 2 */
851 MLX4_GET(bmme_flags, outbox, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
852 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
853 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
854
855 /* turn off device-managed steering capability if not enabled */
856 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
857 MLX4_GET(field, outbox->buf,
858 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
859 field &= 0x7f;
860 MLX4_PUT(outbox->buf, field,
861 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
862 }
863 return 0;
864 }
865
866 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
867 struct mlx4_vhcr *vhcr,
868 struct mlx4_cmd_mailbox *inbox,
869 struct mlx4_cmd_mailbox *outbox,
870 struct mlx4_cmd_info *cmd)
871 {
872 struct mlx4_priv *priv = mlx4_priv(dev);
873 u64 def_mac;
874 u8 port_type;
875 u16 short_field;
876 int err;
877 int admin_link_state;
878
879 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
880 #define MLX4_PORT_LINK_UP_MASK 0x80
881 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
882 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
883
884 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
885 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
886 MLX4_CMD_NATIVE);
887
888 if (!err && dev->caps.function != slave) {
889 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
890 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
891
892 /* get port type - currently only eth is enabled */
893 MLX4_GET(port_type, outbox->buf,
894 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
895
896 /* No link sensing allowed */
897 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
898 /* set port type to currently operating port type */
899 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
900
901 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
902 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
903 port_type |= MLX4_PORT_LINK_UP_MASK;
904 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
905 port_type &= ~MLX4_PORT_LINK_UP_MASK;
906
907 MLX4_PUT(outbox->buf, port_type,
908 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
909
910 short_field = 1; /* slave max gids */
911 MLX4_PUT(outbox->buf, short_field,
912 QUERY_PORT_CUR_MAX_GID_OFFSET);
913
914 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
915 MLX4_PUT(outbox->buf, short_field,
916 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
917 }
918
919 return err;
920 }
921
922 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
923 int *gid_tbl_len, int *pkey_tbl_len)
924 {
925 struct mlx4_cmd_mailbox *mailbox;
926 u32 *outbox;
927 u16 field;
928 int err;
929
930 mailbox = mlx4_alloc_cmd_mailbox(dev);
931 if (IS_ERR(mailbox))
932 return PTR_ERR(mailbox);
933
934 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
935 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
936 MLX4_CMD_WRAPPED);
937 if (err)
938 goto out;
939
940 outbox = mailbox->buf;
941
942 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
943 *gid_tbl_len = field;
944
945 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
946 *pkey_tbl_len = field;
947
948 out:
949 mlx4_free_cmd_mailbox(dev, mailbox);
950 return err;
951 }
952 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
953
954 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
955 {
956 struct mlx4_cmd_mailbox *mailbox;
957 struct mlx4_icm_iter iter;
958 __be64 *pages;
959 int lg;
960 int nent = 0;
961 int i;
962 int err = 0;
963 int ts = 0, tc = 0;
964
965 mailbox = mlx4_alloc_cmd_mailbox(dev);
966 if (IS_ERR(mailbox))
967 return PTR_ERR(mailbox);
968 pages = mailbox->buf;
969
970 for (mlx4_icm_first(icm, &iter);
971 !mlx4_icm_last(&iter);
972 mlx4_icm_next(&iter)) {
973 /*
974 * We have to pass pages that are aligned to their
975 * size, so find the least significant 1 in the
976 * address or size and use that as our log2 size.
977 */
978 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
979 if (lg < MLX4_ICM_PAGE_SHIFT) {
980 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
981 MLX4_ICM_PAGE_SIZE,
982 (unsigned long long) mlx4_icm_addr(&iter),
983 mlx4_icm_size(&iter));
984 err = -EINVAL;
985 goto out;
986 }
987
988 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
989 if (virt != -1) {
990 pages[nent * 2] = cpu_to_be64(virt);
991 virt += 1 << lg;
992 }
993
994 pages[nent * 2 + 1] =
995 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
996 (lg - MLX4_ICM_PAGE_SHIFT));
997 ts += 1 << (lg - 10);
998 ++tc;
999
1000 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1001 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1002 MLX4_CMD_TIME_CLASS_B,
1003 MLX4_CMD_NATIVE);
1004 if (err)
1005 goto out;
1006 nent = 0;
1007 }
1008 }
1009 }
1010
1011 if (nent)
1012 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1013 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1014 if (err)
1015 goto out;
1016
1017 switch (op) {
1018 case MLX4_CMD_MAP_FA:
1019 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
1020 break;
1021 case MLX4_CMD_MAP_ICM_AUX:
1022 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
1023 break;
1024 case MLX4_CMD_MAP_ICM:
1025 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
1026 tc, ts, (unsigned long long) virt - (ts << 10));
1027 break;
1028 }
1029
1030 out:
1031 mlx4_free_cmd_mailbox(dev, mailbox);
1032 return err;
1033 }
1034
1035 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1036 {
1037 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1038 }
1039
1040 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1041 {
1042 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1043 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1044 }
1045
1046
1047 int mlx4_RUN_FW(struct mlx4_dev *dev)
1048 {
1049 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1050 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1051 }
1052
1053 int mlx4_QUERY_FW(struct mlx4_dev *dev)
1054 {
1055 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1056 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1057 struct mlx4_cmd_mailbox *mailbox;
1058 u32 *outbox;
1059 int err = 0;
1060 u64 fw_ver;
1061 u16 cmd_if_rev;
1062 u8 lg;
1063
1064 #define QUERY_FW_OUT_SIZE 0x100
1065 #define QUERY_FW_VER_OFFSET 0x00
1066 #define QUERY_FW_PPF_ID 0x09
1067 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
1068 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
1069 #define QUERY_FW_ERR_START_OFFSET 0x30
1070 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
1071 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
1072
1073 #define QUERY_FW_SIZE_OFFSET 0x00
1074 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1075 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1076
1077 #define QUERY_FW_COMM_BASE_OFFSET 0x40
1078 #define QUERY_FW_COMM_BAR_OFFSET 0x48
1079
1080 #define QUERY_FW_CLOCK_OFFSET 0x50
1081 #define QUERY_FW_CLOCK_BAR 0x58
1082
1083 mailbox = mlx4_alloc_cmd_mailbox(dev);
1084 if (IS_ERR(mailbox))
1085 return PTR_ERR(mailbox);
1086 outbox = mailbox->buf;
1087
1088 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1089 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1090 if (err)
1091 goto out;
1092
1093 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1094 /*
1095 * FW subminor version is at more significant bits than minor
1096 * version, so swap here.
1097 */
1098 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1099 ((fw_ver & 0xffff0000ull) >> 16) |
1100 ((fw_ver & 0x0000ffffull) << 16);
1101
1102 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1103 dev->caps.function = lg;
1104
1105 if (mlx4_is_slave(dev))
1106 goto out;
1107
1108
1109 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
1110 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1111 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1112 mlx4_err(dev, "Installed FW has unsupported "
1113 "command interface revision %d.\n",
1114 cmd_if_rev);
1115 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1116 (int) (dev->caps.fw_ver >> 32),
1117 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1118 (int) dev->caps.fw_ver & 0xffff);
1119 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
1120 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
1121 err = -ENODEV;
1122 goto out;
1123 }
1124
1125 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1126 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1127
1128 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1129 cmd->max_cmds = 1 << lg;
1130
1131 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
1132 (int) (dev->caps.fw_ver >> 32),
1133 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1134 (int) dev->caps.fw_ver & 0xffff,
1135 cmd_if_rev, cmd->max_cmds);
1136
1137 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1138 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1139 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1140 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1141
1142 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1143 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1144
1145 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1146 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1147 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1148 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1149
1150 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1151 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1152 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1153 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1154 fw->comm_bar, fw->comm_base);
1155 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1156
1157 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1158 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1159 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1160 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1161 fw->clock_bar, fw->clock_offset);
1162
1163 /*
1164 * Round up number of system pages needed in case
1165 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1166 */
1167 fw->fw_pages =
1168 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1169 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1170
1171 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1172 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1173
1174 out:
1175 mlx4_free_cmd_mailbox(dev, mailbox);
1176 return err;
1177 }
1178
1179 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1180 struct mlx4_vhcr *vhcr,
1181 struct mlx4_cmd_mailbox *inbox,
1182 struct mlx4_cmd_mailbox *outbox,
1183 struct mlx4_cmd_info *cmd)
1184 {
1185 u8 *outbuf;
1186 int err;
1187
1188 outbuf = outbox->buf;
1189 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1190 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1191 if (err)
1192 return err;
1193
1194 /* for slaves, set pci PPF ID to invalid and zero out everything
1195 * else except FW version */
1196 outbuf[0] = outbuf[1] = 0;
1197 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
1198 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1199
1200 return 0;
1201 }
1202
1203 static void get_board_id(void *vsd, char *board_id)
1204 {
1205 int i;
1206
1207 #define VSD_OFFSET_SIG1 0x00
1208 #define VSD_OFFSET_SIG2 0xde
1209 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1210 #define VSD_OFFSET_TS_BOARD_ID 0x20
1211
1212 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1213
1214 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1215
1216 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1217 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1218 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1219 } else {
1220 /*
1221 * The board ID is a string but the firmware byte
1222 * swaps each 4-byte word before passing it back to
1223 * us. Therefore we need to swab it before printing.
1224 */
1225 for (i = 0; i < 4; ++i)
1226 ((u32 *) board_id)[i] =
1227 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1228 }
1229 }
1230
1231 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1232 {
1233 struct mlx4_cmd_mailbox *mailbox;
1234 u32 *outbox;
1235 int err;
1236
1237 #define QUERY_ADAPTER_OUT_SIZE 0x100
1238 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1239 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1240
1241 mailbox = mlx4_alloc_cmd_mailbox(dev);
1242 if (IS_ERR(mailbox))
1243 return PTR_ERR(mailbox);
1244 outbox = mailbox->buf;
1245
1246 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
1247 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1248 if (err)
1249 goto out;
1250
1251 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1252
1253 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1254 adapter->board_id);
1255
1256 out:
1257 mlx4_free_cmd_mailbox(dev, mailbox);
1258 return err;
1259 }
1260
1261 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1262 {
1263 struct mlx4_cmd_mailbox *mailbox;
1264 __be32 *inbox;
1265 int err;
1266
1267 #define INIT_HCA_IN_SIZE 0x200
1268 #define INIT_HCA_VERSION_OFFSET 0x000
1269 #define INIT_HCA_VERSION 2
1270 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1271 #define INIT_HCA_FLAGS_OFFSET 0x014
1272 #define INIT_HCA_QPC_OFFSET 0x020
1273 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1274 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1275 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1276 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1277 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1278 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1279 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1280 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1281 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1282 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1283 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1284 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1285 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1286 #define INIT_HCA_MCAST_OFFSET 0x0c0
1287 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1288 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1289 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1290 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1291 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1292 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1293 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1294 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1295 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1296 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1297 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1298 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1299 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1300 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
1301 #define INIT_HCA_TPT_OFFSET 0x0f0
1302 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1303 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
1304 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1305 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1306 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1307 #define INIT_HCA_UAR_OFFSET 0x120
1308 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1309 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1310
1311 mailbox = mlx4_alloc_cmd_mailbox(dev);
1312 if (IS_ERR(mailbox))
1313 return PTR_ERR(mailbox);
1314 inbox = mailbox->buf;
1315
1316 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1317
1318 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1319 (ilog2(cache_line_size()) - 4) << 5;
1320
1321 #if defined(__LITTLE_ENDIAN)
1322 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1323 #elif defined(__BIG_ENDIAN)
1324 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1325 #else
1326 #error Host endianness not defined
1327 #endif
1328 /* Check port for UD address vector: */
1329 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1330
1331 /* Enable IPoIB checksumming if we can: */
1332 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1333 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1334
1335 /* Enable QoS support if module parameter set */
1336 if (enable_qos)
1337 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1338
1339 /* enable counters */
1340 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1341 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1342
1343 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1344 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1345 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1346 dev->caps.eqe_size = 64;
1347 dev->caps.eqe_factor = 1;
1348 } else {
1349 dev->caps.eqe_size = 32;
1350 dev->caps.eqe_factor = 0;
1351 }
1352
1353 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1354 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1355 dev->caps.cqe_size = 64;
1356 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
1357 } else {
1358 dev->caps.cqe_size = 32;
1359 }
1360
1361 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1362
1363 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1364 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1365 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1366 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1367 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1368 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1369 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1370 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1371 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1372 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1373 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1374 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1375
1376 /* steering attributes */
1377 if (dev->caps.steering_mode ==
1378 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1379 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1380 cpu_to_be32(1 <<
1381 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1382
1383 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1384 MLX4_PUT(inbox, param->log_mc_entry_sz,
1385 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1386 MLX4_PUT(inbox, param->log_mc_table_sz,
1387 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1388 /* Enable Ethernet flow steering
1389 * with udp unicast and tcp unicast
1390 */
1391 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1392 INIT_HCA_FS_ETH_BITS_OFFSET);
1393 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1394 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1395 /* Enable IPoIB flow steering
1396 * with udp unicast and tcp unicast
1397 */
1398 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1399 INIT_HCA_FS_IB_BITS_OFFSET);
1400 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1401 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1402 } else {
1403 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1404 MLX4_PUT(inbox, param->log_mc_entry_sz,
1405 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1406 MLX4_PUT(inbox, param->log_mc_hash_sz,
1407 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1408 MLX4_PUT(inbox, param->log_mc_table_sz,
1409 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1410 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1411 MLX4_PUT(inbox, (u8) (1 << 3),
1412 INIT_HCA_UC_STEERING_OFFSET);
1413 }
1414
1415 /* TPT attributes */
1416
1417 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1418 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
1419 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1420 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1421 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1422
1423 /* UAR attributes */
1424
1425 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1426 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1427
1428 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1429 MLX4_CMD_NATIVE);
1430
1431 if (err)
1432 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1433
1434 mlx4_free_cmd_mailbox(dev, mailbox);
1435 return err;
1436 }
1437
1438 int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1439 struct mlx4_init_hca_param *param)
1440 {
1441 struct mlx4_cmd_mailbox *mailbox;
1442 __be32 *outbox;
1443 u32 dword_field;
1444 int err;
1445 u8 byte_field;
1446
1447 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1448 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
1449
1450 mailbox = mlx4_alloc_cmd_mailbox(dev);
1451 if (IS_ERR(mailbox))
1452 return PTR_ERR(mailbox);
1453 outbox = mailbox->buf;
1454
1455 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1456 MLX4_CMD_QUERY_HCA,
1457 MLX4_CMD_TIME_CLASS_B,
1458 !mlx4_is_slave(dev));
1459 if (err)
1460 goto out;
1461
1462 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1463 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
1464
1465 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1466
1467 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1468 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1469 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1470 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1471 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1472 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1473 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1474 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1475 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1476 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1477 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1478 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1479
1480 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1481 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1482 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1483 } else {
1484 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1485 if (byte_field & 0x8)
1486 param->steering_mode = MLX4_STEERING_MODE_B0;
1487 else
1488 param->steering_mode = MLX4_STEERING_MODE_A0;
1489 }
1490 /* steering attributes */
1491 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
1492 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1493 MLX4_GET(param->log_mc_entry_sz, outbox,
1494 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1495 MLX4_GET(param->log_mc_table_sz, outbox,
1496 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1497 } else {
1498 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1499 MLX4_GET(param->log_mc_entry_sz, outbox,
1500 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1501 MLX4_GET(param->log_mc_hash_sz, outbox,
1502 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1503 MLX4_GET(param->log_mc_table_sz, outbox,
1504 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1505 }
1506
1507 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1508 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1509 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1510 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1511 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1512 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1513
1514 /* TPT attributes */
1515
1516 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1517 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
1518 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1519 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1520 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1521
1522 /* UAR attributes */
1523
1524 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1525 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1526
1527 out:
1528 mlx4_free_cmd_mailbox(dev, mailbox);
1529
1530 return err;
1531 }
1532
1533 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1534 * and real QP0 are active, so that the paravirtualized QP0 is ready
1535 * to operate */
1536 static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1537 {
1538 struct mlx4_priv *priv = mlx4_priv(dev);
1539 /* irrelevant if not infiniband */
1540 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1541 priv->mfunc.master.qp0_state[port].qp0_active)
1542 return 1;
1543 return 0;
1544 }
1545
1546 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1547 struct mlx4_vhcr *vhcr,
1548 struct mlx4_cmd_mailbox *inbox,
1549 struct mlx4_cmd_mailbox *outbox,
1550 struct mlx4_cmd_info *cmd)
1551 {
1552 struct mlx4_priv *priv = mlx4_priv(dev);
1553 int port = vhcr->in_modifier;
1554 int err;
1555
1556 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1557 return 0;
1558
1559 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1560 /* Enable port only if it was previously disabled */
1561 if (!priv->mfunc.master.init_port_ref[port]) {
1562 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1563 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1564 if (err)
1565 return err;
1566 }
1567 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1568 } else {
1569 if (slave == mlx4_master_func_num(dev)) {
1570 if (check_qp0_state(dev, slave, port) &&
1571 !priv->mfunc.master.qp0_state[port].port_active) {
1572 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1573 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1574 if (err)
1575 return err;
1576 priv->mfunc.master.qp0_state[port].port_active = 1;
1577 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1578 }
1579 } else
1580 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1581 }
1582 ++priv->mfunc.master.init_port_ref[port];
1583 return 0;
1584 }
1585
1586 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
1587 {
1588 struct mlx4_cmd_mailbox *mailbox;
1589 u32 *inbox;
1590 int err;
1591 u32 flags;
1592 u16 field;
1593
1594 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1595 #define INIT_PORT_IN_SIZE 256
1596 #define INIT_PORT_FLAGS_OFFSET 0x00
1597 #define INIT_PORT_FLAG_SIG (1 << 18)
1598 #define INIT_PORT_FLAG_NG (1 << 17)
1599 #define INIT_PORT_FLAG_G0 (1 << 16)
1600 #define INIT_PORT_VL_SHIFT 4
1601 #define INIT_PORT_PORT_WIDTH_SHIFT 8
1602 #define INIT_PORT_MTU_OFFSET 0x04
1603 #define INIT_PORT_MAX_GID_OFFSET 0x06
1604 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1605 #define INIT_PORT_GUID0_OFFSET 0x10
1606 #define INIT_PORT_NODE_GUID_OFFSET 0x18
1607 #define INIT_PORT_SI_GUID_OFFSET 0x20
1608
1609 mailbox = mlx4_alloc_cmd_mailbox(dev);
1610 if (IS_ERR(mailbox))
1611 return PTR_ERR(mailbox);
1612 inbox = mailbox->buf;
1613
1614 flags = 0;
1615 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1616 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1617 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
1618
1619 field = 128 << dev->caps.ib_mtu_cap[port];
1620 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1621 field = dev->caps.gid_table_len[port];
1622 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1623 field = dev->caps.pkey_table_len[port];
1624 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
1625
1626 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
1627 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1628
1629 mlx4_free_cmd_mailbox(dev, mailbox);
1630 } else
1631 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1632 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1633
1634 return err;
1635 }
1636 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1637
1638 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1639 struct mlx4_vhcr *vhcr,
1640 struct mlx4_cmd_mailbox *inbox,
1641 struct mlx4_cmd_mailbox *outbox,
1642 struct mlx4_cmd_info *cmd)
1643 {
1644 struct mlx4_priv *priv = mlx4_priv(dev);
1645 int port = vhcr->in_modifier;
1646 int err;
1647
1648 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1649 (1 << port)))
1650 return 0;
1651
1652 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1653 if (priv->mfunc.master.init_port_ref[port] == 1) {
1654 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1655 1000, MLX4_CMD_NATIVE);
1656 if (err)
1657 return err;
1658 }
1659 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1660 } else {
1661 /* infiniband port */
1662 if (slave == mlx4_master_func_num(dev)) {
1663 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1664 priv->mfunc.master.qp0_state[port].port_active) {
1665 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1666 1000, MLX4_CMD_NATIVE);
1667 if (err)
1668 return err;
1669 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1670 priv->mfunc.master.qp0_state[port].port_active = 0;
1671 }
1672 } else
1673 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1674 }
1675 --priv->mfunc.master.init_port_ref[port];
1676 return 0;
1677 }
1678
1679 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1680 {
1681 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1682 MLX4_CMD_WRAPPED);
1683 }
1684 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1685
1686 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1687 {
1688 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1689 MLX4_CMD_NATIVE);
1690 }
1691
1692 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1693 {
1694 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1695 MLX4_CMD_SET_ICM_SIZE,
1696 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1697 if (ret)
1698 return ret;
1699
1700 /*
1701 * Round up number of system pages needed in case
1702 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1703 */
1704 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1705 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1706
1707 return 0;
1708 }
1709
1710 int mlx4_NOP(struct mlx4_dev *dev)
1711 {
1712 /* Input modifier of 0x1f means "finish as soon as possible." */
1713 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
1714 }
1715
1716 #define MLX4_WOL_SETUP_MODE (5 << 28)
1717 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1718 {
1719 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1720
1721 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
1722 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1723 MLX4_CMD_NATIVE);
1724 }
1725 EXPORT_SYMBOL_GPL(mlx4_wol_read);
1726
1727 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1728 {
1729 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1730
1731 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
1732 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1733 }
1734 EXPORT_SYMBOL_GPL(mlx4_wol_write);
1735
1736 enum {
1737 ADD_TO_MCG = 0x26,
1738 };
1739
1740
1741 void mlx4_opreq_action(struct work_struct *work)
1742 {
1743 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
1744 opreq_task);
1745 struct mlx4_dev *dev = &priv->dev;
1746 int num_tasks = atomic_read(&priv->opreq_count);
1747 struct mlx4_cmd_mailbox *mailbox;
1748 struct mlx4_mgm *mgm;
1749 u32 *outbox;
1750 u32 modifier;
1751 u16 token;
1752 u16 type;
1753 int err;
1754 u32 num_qps;
1755 struct mlx4_qp qp;
1756 int i;
1757 u8 rem_mcg;
1758 u8 prot;
1759
1760 #define GET_OP_REQ_MODIFIER_OFFSET 0x08
1761 #define GET_OP_REQ_TOKEN_OFFSET 0x14
1762 #define GET_OP_REQ_TYPE_OFFSET 0x1a
1763 #define GET_OP_REQ_DATA_OFFSET 0x20
1764
1765 mailbox = mlx4_alloc_cmd_mailbox(dev);
1766 if (IS_ERR(mailbox)) {
1767 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
1768 return;
1769 }
1770 outbox = mailbox->buf;
1771
1772 while (num_tasks) {
1773 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1774 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1775 MLX4_CMD_NATIVE);
1776 if (err) {
1777 mlx4_err(dev, "Failed to retreive required operation: %d\n",
1778 err);
1779 return;
1780 }
1781 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
1782 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
1783 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
1784 type &= 0xfff;
1785
1786 switch (type) {
1787 case ADD_TO_MCG:
1788 if (dev->caps.steering_mode ==
1789 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1790 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
1791 err = EPERM;
1792 break;
1793 }
1794 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
1795 GET_OP_REQ_DATA_OFFSET);
1796 num_qps = be32_to_cpu(mgm->members_count) &
1797 MGM_QPN_MASK;
1798 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
1799 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
1800
1801 for (i = 0; i < num_qps; i++) {
1802 qp.qpn = be32_to_cpu(mgm->qp[i]);
1803 if (rem_mcg)
1804 err = mlx4_multicast_detach(dev, &qp,
1805 mgm->gid,
1806 prot, 0);
1807 else
1808 err = mlx4_multicast_attach(dev, &qp,
1809 mgm->gid,
1810 mgm->gid[5]
1811 , 0, prot,
1812 NULL);
1813 if (err)
1814 break;
1815 }
1816 break;
1817 default:
1818 mlx4_warn(dev, "Bad type for required operation\n");
1819 err = EINVAL;
1820 break;
1821 }
1822 err = mlx4_cmd(dev, 0, ((u32) err | cpu_to_be32(token) << 16),
1823 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1824 MLX4_CMD_NATIVE);
1825 if (err) {
1826 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
1827 err);
1828 goto out;
1829 }
1830 memset(outbox, 0, 0xffc);
1831 num_tasks = atomic_dec_return(&priv->opreq_count);
1832 }
1833
1834 out:
1835 mlx4_free_cmd_mailbox(dev, mailbox);
1836 }