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Merge 4.14.23 into android-4.14
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/if_vlan.h>
23 #include <linux/reset.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26
27 #include "mtk_eth_soc.h"
28
29 static int mtk_msg_level = -1;
30 module_param_named(msg_level, mtk_msg_level, int, 0);
31 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
32
33 #define MTK_ETHTOOL_STAT(x) { #x, \
34 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
35
36 /* strings used by ethtool */
37 static const struct mtk_ethtool_stats {
38 char str[ETH_GSTRING_LEN];
39 u32 offset;
40 } mtk_ethtool_stats[] = {
41 MTK_ETHTOOL_STAT(tx_bytes),
42 MTK_ETHTOOL_STAT(tx_packets),
43 MTK_ETHTOOL_STAT(tx_skip),
44 MTK_ETHTOOL_STAT(tx_collisions),
45 MTK_ETHTOOL_STAT(rx_bytes),
46 MTK_ETHTOOL_STAT(rx_packets),
47 MTK_ETHTOOL_STAT(rx_overflow),
48 MTK_ETHTOOL_STAT(rx_fcs_errors),
49 MTK_ETHTOOL_STAT(rx_short_errors),
50 MTK_ETHTOOL_STAT(rx_long_errors),
51 MTK_ETHTOOL_STAT(rx_checksum_errors),
52 MTK_ETHTOOL_STAT(rx_flow_control_packets),
53 };
54
55 static const char * const mtk_clks_source_name[] = {
56 "ethif", "esw", "gp0", "gp1", "gp2", "trgpll", "sgmii_tx250m",
57 "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll"
58 };
59
60 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
61 {
62 __raw_writel(val, eth->base + reg);
63 }
64
65 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
66 {
67 return __raw_readl(eth->base + reg);
68 }
69
70 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
71 {
72 unsigned long t_start = jiffies;
73
74 while (1) {
75 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
76 return 0;
77 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
78 break;
79 usleep_range(10, 20);
80 }
81
82 dev_err(eth->dev, "mdio: MDIO timeout\n");
83 return -1;
84 }
85
86 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
87 u32 phy_register, u32 write_data)
88 {
89 if (mtk_mdio_busy_wait(eth))
90 return -1;
91
92 write_data &= 0xffff;
93
94 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
95 (phy_register << PHY_IAC_REG_SHIFT) |
96 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
97 MTK_PHY_IAC);
98
99 if (mtk_mdio_busy_wait(eth))
100 return -1;
101
102 return 0;
103 }
104
105 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
106 {
107 u32 d;
108
109 if (mtk_mdio_busy_wait(eth))
110 return 0xffff;
111
112 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
113 (phy_reg << PHY_IAC_REG_SHIFT) |
114 (phy_addr << PHY_IAC_ADDR_SHIFT),
115 MTK_PHY_IAC);
116
117 if (mtk_mdio_busy_wait(eth))
118 return 0xffff;
119
120 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
121
122 return d;
123 }
124
125 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
126 int phy_reg, u16 val)
127 {
128 struct mtk_eth *eth = bus->priv;
129
130 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
131 }
132
133 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
134 {
135 struct mtk_eth *eth = bus->priv;
136
137 return _mtk_mdio_read(eth, phy_addr, phy_reg);
138 }
139
140 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
141 {
142 u32 val;
143 int ret;
144
145 val = (speed == SPEED_1000) ?
146 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
147 mtk_w32(eth, val, INTF_MODE);
148
149 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
150 ETHSYS_TRGMII_CLK_SEL362_5,
151 ETHSYS_TRGMII_CLK_SEL362_5);
152
153 val = (speed == SPEED_1000) ? 250000000 : 500000000;
154 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
155 if (ret)
156 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
157
158 val = (speed == SPEED_1000) ?
159 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
160 mtk_w32(eth, val, TRGMII_RCK_CTRL);
161
162 val = (speed == SPEED_1000) ?
163 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
164 mtk_w32(eth, val, TRGMII_TCK_CTRL);
165 }
166
167 static void mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id)
168 {
169 u32 val;
170
171 /* Setup the link timer and QPHY power up inside SGMIISYS */
172 regmap_write(eth->sgmiisys, SGMSYS_PCS_LINK_TIMER,
173 SGMII_LINK_TIMER_DEFAULT);
174
175 regmap_read(eth->sgmiisys, SGMSYS_SGMII_MODE, &val);
176 val |= SGMII_REMOTE_FAULT_DIS;
177 regmap_write(eth->sgmiisys, SGMSYS_SGMII_MODE, val);
178
179 regmap_read(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, &val);
180 val |= SGMII_AN_RESTART;
181 regmap_write(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, val);
182
183 regmap_read(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
184 val &= ~SGMII_PHYA_PWD;
185 regmap_write(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, val);
186
187 /* Determine MUX for which GMAC uses the SGMII interface */
188 if (MTK_HAS_CAPS(eth->soc->caps, MTK_DUAL_GMAC_SHARED_SGMII)) {
189 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
190 val &= ~SYSCFG0_SGMII_MASK;
191 val |= !mac_id ? SYSCFG0_SGMII_GMAC1 : SYSCFG0_SGMII_GMAC2;
192 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
193
194 dev_info(eth->dev, "setup shared sgmii for gmac=%d\n",
195 mac_id);
196 }
197
198 /* Setup the GMAC1 going through SGMII path when SoC also support
199 * ESW on GMAC1
200 */
201 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC1_ESW | MTK_GMAC1_SGMII) &&
202 !mac_id) {
203 mtk_w32(eth, 0, MTK_MAC_MISC);
204 dev_info(eth->dev, "setup gmac1 going through sgmii");
205 }
206 }
207
208 static void mtk_phy_link_adjust(struct net_device *dev)
209 {
210 struct mtk_mac *mac = netdev_priv(dev);
211 u16 lcl_adv = 0, rmt_adv = 0;
212 u8 flowctrl;
213 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
214 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
215 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
216 MAC_MCR_BACKPR_EN;
217
218 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
219 return;
220
221 switch (dev->phydev->speed) {
222 case SPEED_1000:
223 mcr |= MAC_MCR_SPEED_1000;
224 break;
225 case SPEED_100:
226 mcr |= MAC_MCR_SPEED_100;
227 break;
228 };
229
230 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) &&
231 !mac->id && !mac->trgmii)
232 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed);
233
234 if (dev->phydev->link)
235 mcr |= MAC_MCR_FORCE_LINK;
236
237 if (dev->phydev->duplex) {
238 mcr |= MAC_MCR_FORCE_DPX;
239
240 if (dev->phydev->pause)
241 rmt_adv = LPA_PAUSE_CAP;
242 if (dev->phydev->asym_pause)
243 rmt_adv |= LPA_PAUSE_ASYM;
244
245 if (dev->phydev->advertising & ADVERTISED_Pause)
246 lcl_adv |= ADVERTISE_PAUSE_CAP;
247 if (dev->phydev->advertising & ADVERTISED_Asym_Pause)
248 lcl_adv |= ADVERTISE_PAUSE_ASYM;
249
250 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
251
252 if (flowctrl & FLOW_CTRL_TX)
253 mcr |= MAC_MCR_FORCE_TX_FC;
254 if (flowctrl & FLOW_CTRL_RX)
255 mcr |= MAC_MCR_FORCE_RX_FC;
256
257 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
258 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
259 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
260 }
261
262 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
263
264 if (dev->phydev->link)
265 netif_carrier_on(dev);
266 else
267 netif_carrier_off(dev);
268
269 if (!of_phy_is_fixed_link(mac->of_node))
270 phy_print_status(dev->phydev);
271 }
272
273 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
274 struct device_node *phy_node)
275 {
276 struct phy_device *phydev;
277 int phy_mode;
278
279 phy_mode = of_get_phy_mode(phy_node);
280 if (phy_mode < 0) {
281 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
282 return -EINVAL;
283 }
284
285 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
286 mtk_phy_link_adjust, 0, phy_mode);
287 if (!phydev) {
288 dev_err(eth->dev, "could not connect to PHY\n");
289 return -ENODEV;
290 }
291
292 dev_info(eth->dev,
293 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
294 mac->id, phydev_name(phydev), phydev->phy_id,
295 phydev->drv->name);
296
297 return 0;
298 }
299
300 static int mtk_phy_connect(struct net_device *dev)
301 {
302 struct mtk_mac *mac = netdev_priv(dev);
303 struct mtk_eth *eth;
304 struct device_node *np;
305 u32 val;
306
307 eth = mac->hw;
308 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
309 if (!np && of_phy_is_fixed_link(mac->of_node))
310 if (!of_phy_register_fixed_link(mac->of_node))
311 np = of_node_get(mac->of_node);
312 if (!np)
313 return -ENODEV;
314
315 mac->ge_mode = 0;
316 switch (of_get_phy_mode(np)) {
317 case PHY_INTERFACE_MODE_TRGMII:
318 mac->trgmii = true;
319 case PHY_INTERFACE_MODE_RGMII_TXID:
320 case PHY_INTERFACE_MODE_RGMII_RXID:
321 case PHY_INTERFACE_MODE_RGMII_ID:
322 case PHY_INTERFACE_MODE_RGMII:
323 break;
324 case PHY_INTERFACE_MODE_SGMII:
325 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII))
326 mtk_gmac_sgmii_hw_setup(eth, mac->id);
327 break;
328 case PHY_INTERFACE_MODE_MII:
329 mac->ge_mode = 1;
330 break;
331 case PHY_INTERFACE_MODE_REVMII:
332 mac->ge_mode = 2;
333 break;
334 case PHY_INTERFACE_MODE_RMII:
335 if (!mac->id)
336 goto err_phy;
337 mac->ge_mode = 3;
338 break;
339 default:
340 goto err_phy;
341 }
342
343 /* put the gmac into the right mode */
344 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
345 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
346 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
347 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
348
349 /* couple phydev to net_device */
350 if (mtk_phy_connect_node(eth, mac, np))
351 goto err_phy;
352
353 dev->phydev->autoneg = AUTONEG_ENABLE;
354 dev->phydev->speed = 0;
355 dev->phydev->duplex = 0;
356
357 if (of_phy_is_fixed_link(mac->of_node))
358 dev->phydev->supported |=
359 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
360
361 dev->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
362 SUPPORTED_Asym_Pause;
363 dev->phydev->advertising = dev->phydev->supported |
364 ADVERTISED_Autoneg;
365 phy_start_aneg(dev->phydev);
366
367 of_node_put(np);
368
369 return 0;
370
371 err_phy:
372 if (of_phy_is_fixed_link(mac->of_node))
373 of_phy_deregister_fixed_link(mac->of_node);
374 of_node_put(np);
375 dev_err(eth->dev, "%s: invalid phy\n", __func__);
376 return -EINVAL;
377 }
378
379 static int mtk_mdio_init(struct mtk_eth *eth)
380 {
381 struct device_node *mii_np;
382 int ret;
383
384 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
385 if (!mii_np) {
386 dev_err(eth->dev, "no %s child node found", "mdio-bus");
387 return -ENODEV;
388 }
389
390 if (!of_device_is_available(mii_np)) {
391 ret = -ENODEV;
392 goto err_put_node;
393 }
394
395 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
396 if (!eth->mii_bus) {
397 ret = -ENOMEM;
398 goto err_put_node;
399 }
400
401 eth->mii_bus->name = "mdio";
402 eth->mii_bus->read = mtk_mdio_read;
403 eth->mii_bus->write = mtk_mdio_write;
404 eth->mii_bus->priv = eth;
405 eth->mii_bus->parent = eth->dev;
406
407 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
408 ret = of_mdiobus_register(eth->mii_bus, mii_np);
409
410 err_put_node:
411 of_node_put(mii_np);
412 return ret;
413 }
414
415 static void mtk_mdio_cleanup(struct mtk_eth *eth)
416 {
417 if (!eth->mii_bus)
418 return;
419
420 mdiobus_unregister(eth->mii_bus);
421 }
422
423 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
424 {
425 unsigned long flags;
426 u32 val;
427
428 spin_lock_irqsave(&eth->tx_irq_lock, flags);
429 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
430 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
431 spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
432 }
433
434 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
435 {
436 unsigned long flags;
437 u32 val;
438
439 spin_lock_irqsave(&eth->tx_irq_lock, flags);
440 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
441 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
442 spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
443 }
444
445 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
446 {
447 unsigned long flags;
448 u32 val;
449
450 spin_lock_irqsave(&eth->rx_irq_lock, flags);
451 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
452 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK);
453 spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
454 }
455
456 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
457 {
458 unsigned long flags;
459 u32 val;
460
461 spin_lock_irqsave(&eth->rx_irq_lock, flags);
462 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
463 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK);
464 spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
465 }
466
467 static int mtk_set_mac_address(struct net_device *dev, void *p)
468 {
469 int ret = eth_mac_addr(dev, p);
470 struct mtk_mac *mac = netdev_priv(dev);
471 const char *macaddr = dev->dev_addr;
472
473 if (ret)
474 return ret;
475
476 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
477 return -EBUSY;
478
479 spin_lock_bh(&mac->hw->page_lock);
480 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
481 MTK_GDMA_MAC_ADRH(mac->id));
482 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
483 (macaddr[4] << 8) | macaddr[5],
484 MTK_GDMA_MAC_ADRL(mac->id));
485 spin_unlock_bh(&mac->hw->page_lock);
486
487 return 0;
488 }
489
490 void mtk_stats_update_mac(struct mtk_mac *mac)
491 {
492 struct mtk_hw_stats *hw_stats = mac->hw_stats;
493 unsigned int base = MTK_GDM1_TX_GBCNT;
494 u64 stats;
495
496 base += hw_stats->reg_offset;
497
498 u64_stats_update_begin(&hw_stats->syncp);
499
500 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
501 stats = mtk_r32(mac->hw, base + 0x04);
502 if (stats)
503 hw_stats->rx_bytes += (stats << 32);
504 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
505 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
506 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
507 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
508 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
509 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
510 hw_stats->rx_flow_control_packets +=
511 mtk_r32(mac->hw, base + 0x24);
512 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
513 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
514 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
515 stats = mtk_r32(mac->hw, base + 0x34);
516 if (stats)
517 hw_stats->tx_bytes += (stats << 32);
518 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
519 u64_stats_update_end(&hw_stats->syncp);
520 }
521
522 static void mtk_stats_update(struct mtk_eth *eth)
523 {
524 int i;
525
526 for (i = 0; i < MTK_MAC_COUNT; i++) {
527 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
528 continue;
529 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
530 mtk_stats_update_mac(eth->mac[i]);
531 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
532 }
533 }
534 }
535
536 static void mtk_get_stats64(struct net_device *dev,
537 struct rtnl_link_stats64 *storage)
538 {
539 struct mtk_mac *mac = netdev_priv(dev);
540 struct mtk_hw_stats *hw_stats = mac->hw_stats;
541 unsigned int start;
542
543 if (netif_running(dev) && netif_device_present(dev)) {
544 if (spin_trylock_bh(&hw_stats->stats_lock)) {
545 mtk_stats_update_mac(mac);
546 spin_unlock_bh(&hw_stats->stats_lock);
547 }
548 }
549
550 do {
551 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
552 storage->rx_packets = hw_stats->rx_packets;
553 storage->tx_packets = hw_stats->tx_packets;
554 storage->rx_bytes = hw_stats->rx_bytes;
555 storage->tx_bytes = hw_stats->tx_bytes;
556 storage->collisions = hw_stats->tx_collisions;
557 storage->rx_length_errors = hw_stats->rx_short_errors +
558 hw_stats->rx_long_errors;
559 storage->rx_over_errors = hw_stats->rx_overflow;
560 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
561 storage->rx_errors = hw_stats->rx_checksum_errors;
562 storage->tx_aborted_errors = hw_stats->tx_skip;
563 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
564
565 storage->tx_errors = dev->stats.tx_errors;
566 storage->rx_dropped = dev->stats.rx_dropped;
567 storage->tx_dropped = dev->stats.tx_dropped;
568 }
569
570 static inline int mtk_max_frag_size(int mtu)
571 {
572 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
573 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
574 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
575
576 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
577 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
578 }
579
580 static inline int mtk_max_buf_size(int frag_size)
581 {
582 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
583 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
584
585 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
586
587 return buf_size;
588 }
589
590 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
591 struct mtk_rx_dma *dma_rxd)
592 {
593 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
594 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
595 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
596 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
597 }
598
599 /* the qdma core needs scratch memory to be setup */
600 static int mtk_init_fq_dma(struct mtk_eth *eth)
601 {
602 dma_addr_t phy_ring_tail;
603 int cnt = MTK_DMA_SIZE;
604 dma_addr_t dma_addr;
605 int i;
606
607 eth->scratch_ring = dma_alloc_coherent(eth->dev,
608 cnt * sizeof(struct mtk_tx_dma),
609 &eth->phy_scratch_ring,
610 GFP_ATOMIC | __GFP_ZERO);
611 if (unlikely(!eth->scratch_ring))
612 return -ENOMEM;
613
614 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
615 GFP_KERNEL);
616 if (unlikely(!eth->scratch_head))
617 return -ENOMEM;
618
619 dma_addr = dma_map_single(eth->dev,
620 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
621 DMA_FROM_DEVICE);
622 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
623 return -ENOMEM;
624
625 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
626 phy_ring_tail = eth->phy_scratch_ring +
627 (sizeof(struct mtk_tx_dma) * (cnt - 1));
628
629 for (i = 0; i < cnt; i++) {
630 eth->scratch_ring[i].txd1 =
631 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
632 if (i < cnt - 1)
633 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
634 ((i + 1) * sizeof(struct mtk_tx_dma)));
635 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
636 }
637
638 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
639 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
640 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
641 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
642
643 return 0;
644 }
645
646 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
647 {
648 void *ret = ring->dma;
649
650 return ret + (desc - ring->phys);
651 }
652
653 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
654 struct mtk_tx_dma *txd)
655 {
656 int idx = txd - ring->dma;
657
658 return &ring->buf[idx];
659 }
660
661 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
662 {
663 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
664 dma_unmap_single(eth->dev,
665 dma_unmap_addr(tx_buf, dma_addr0),
666 dma_unmap_len(tx_buf, dma_len0),
667 DMA_TO_DEVICE);
668 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
669 dma_unmap_page(eth->dev,
670 dma_unmap_addr(tx_buf, dma_addr0),
671 dma_unmap_len(tx_buf, dma_len0),
672 DMA_TO_DEVICE);
673 }
674 tx_buf->flags = 0;
675 if (tx_buf->skb &&
676 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
677 dev_kfree_skb_any(tx_buf->skb);
678 tx_buf->skb = NULL;
679 }
680
681 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
682 int tx_num, struct mtk_tx_ring *ring, bool gso)
683 {
684 struct mtk_mac *mac = netdev_priv(dev);
685 struct mtk_eth *eth = mac->hw;
686 struct mtk_tx_dma *itxd, *txd;
687 struct mtk_tx_buf *itx_buf, *tx_buf;
688 dma_addr_t mapped_addr;
689 unsigned int nr_frags;
690 int i, n_desc = 1;
691 u32 txd4 = 0, fport;
692
693 itxd = ring->next_free;
694 if (itxd == ring->last_free)
695 return -ENOMEM;
696
697 /* set the forward port */
698 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
699 txd4 |= fport;
700
701 itx_buf = mtk_desc_to_tx_buf(ring, itxd);
702 memset(itx_buf, 0, sizeof(*itx_buf));
703
704 if (gso)
705 txd4 |= TX_DMA_TSO;
706
707 /* TX Checksum offload */
708 if (skb->ip_summed == CHECKSUM_PARTIAL)
709 txd4 |= TX_DMA_CHKSUM;
710
711 /* VLAN header offload */
712 if (skb_vlan_tag_present(skb))
713 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
714
715 mapped_addr = dma_map_single(eth->dev, skb->data,
716 skb_headlen(skb), DMA_TO_DEVICE);
717 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
718 return -ENOMEM;
719
720 WRITE_ONCE(itxd->txd1, mapped_addr);
721 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
722 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
723 MTK_TX_FLAGS_FPORT1;
724 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr);
725 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb));
726
727 /* TX SG offload */
728 txd = itxd;
729 nr_frags = skb_shinfo(skb)->nr_frags;
730 for (i = 0; i < nr_frags; i++) {
731 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
732 unsigned int offset = 0;
733 int frag_size = skb_frag_size(frag);
734
735 while (frag_size) {
736 bool last_frag = false;
737 unsigned int frag_map_size;
738
739 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
740 if (txd == ring->last_free)
741 goto err_dma;
742
743 n_desc++;
744 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
745 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
746 frag_map_size,
747 DMA_TO_DEVICE);
748 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
749 goto err_dma;
750
751 if (i == nr_frags - 1 &&
752 (frag_size - frag_map_size) == 0)
753 last_frag = true;
754
755 WRITE_ONCE(txd->txd1, mapped_addr);
756 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
757 TX_DMA_PLEN0(frag_map_size) |
758 last_frag * TX_DMA_LS0));
759 WRITE_ONCE(txd->txd4, fport);
760
761 tx_buf = mtk_desc_to_tx_buf(ring, txd);
762 memset(tx_buf, 0, sizeof(*tx_buf));
763 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
764 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
765 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
766 MTK_TX_FLAGS_FPORT1;
767
768 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
769 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
770 frag_size -= frag_map_size;
771 offset += frag_map_size;
772 }
773 }
774
775 /* store skb to cleanup */
776 itx_buf->skb = skb;
777
778 WRITE_ONCE(itxd->txd4, txd4);
779 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
780 (!nr_frags * TX_DMA_LS0)));
781
782 netdev_sent_queue(dev, skb->len);
783 skb_tx_timestamp(skb);
784
785 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
786 atomic_sub(n_desc, &ring->free_count);
787
788 /* make sure that all changes to the dma ring are flushed before we
789 * continue
790 */
791 wmb();
792
793 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
794 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
795
796 return 0;
797
798 err_dma:
799 do {
800 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
801
802 /* unmap dma */
803 mtk_tx_unmap(eth, tx_buf);
804
805 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
806 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
807 } while (itxd != txd);
808
809 return -ENOMEM;
810 }
811
812 static inline int mtk_cal_txd_req(struct sk_buff *skb)
813 {
814 int i, nfrags;
815 struct skb_frag_struct *frag;
816
817 nfrags = 1;
818 if (skb_is_gso(skb)) {
819 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
820 frag = &skb_shinfo(skb)->frags[i];
821 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
822 }
823 } else {
824 nfrags += skb_shinfo(skb)->nr_frags;
825 }
826
827 return nfrags;
828 }
829
830 static int mtk_queue_stopped(struct mtk_eth *eth)
831 {
832 int i;
833
834 for (i = 0; i < MTK_MAC_COUNT; i++) {
835 if (!eth->netdev[i])
836 continue;
837 if (netif_queue_stopped(eth->netdev[i]))
838 return 1;
839 }
840
841 return 0;
842 }
843
844 static void mtk_wake_queue(struct mtk_eth *eth)
845 {
846 int i;
847
848 for (i = 0; i < MTK_MAC_COUNT; i++) {
849 if (!eth->netdev[i])
850 continue;
851 netif_wake_queue(eth->netdev[i]);
852 }
853 }
854
855 static void mtk_stop_queue(struct mtk_eth *eth)
856 {
857 int i;
858
859 for (i = 0; i < MTK_MAC_COUNT; i++) {
860 if (!eth->netdev[i])
861 continue;
862 netif_stop_queue(eth->netdev[i]);
863 }
864 }
865
866 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
867 {
868 struct mtk_mac *mac = netdev_priv(dev);
869 struct mtk_eth *eth = mac->hw;
870 struct mtk_tx_ring *ring = &eth->tx_ring;
871 struct net_device_stats *stats = &dev->stats;
872 bool gso = false;
873 int tx_num;
874
875 /* normally we can rely on the stack not calling this more than once,
876 * however we have 2 queues running on the same ring so we need to lock
877 * the ring access
878 */
879 spin_lock(&eth->page_lock);
880
881 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
882 goto drop;
883
884 tx_num = mtk_cal_txd_req(skb);
885 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
886 mtk_stop_queue(eth);
887 netif_err(eth, tx_queued, dev,
888 "Tx Ring full when queue awake!\n");
889 spin_unlock(&eth->page_lock);
890 return NETDEV_TX_BUSY;
891 }
892
893 /* TSO: fill MSS info in tcp checksum field */
894 if (skb_is_gso(skb)) {
895 if (skb_cow_head(skb, 0)) {
896 netif_warn(eth, tx_err, dev,
897 "GSO expand head fail.\n");
898 goto drop;
899 }
900
901 if (skb_shinfo(skb)->gso_type &
902 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
903 gso = true;
904 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
905 }
906 }
907
908 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
909 goto drop;
910
911 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
912 mtk_stop_queue(eth);
913
914 spin_unlock(&eth->page_lock);
915
916 return NETDEV_TX_OK;
917
918 drop:
919 spin_unlock(&eth->page_lock);
920 stats->tx_dropped++;
921 dev_kfree_skb_any(skb);
922 return NETDEV_TX_OK;
923 }
924
925 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
926 {
927 int i;
928 struct mtk_rx_ring *ring;
929 int idx;
930
931 if (!eth->hwlro)
932 return &eth->rx_ring[0];
933
934 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
935 ring = &eth->rx_ring[i];
936 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
937 if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
938 ring->calc_idx_update = true;
939 return ring;
940 }
941 }
942
943 return NULL;
944 }
945
946 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
947 {
948 struct mtk_rx_ring *ring;
949 int i;
950
951 if (!eth->hwlro) {
952 ring = &eth->rx_ring[0];
953 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
954 } else {
955 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
956 ring = &eth->rx_ring[i];
957 if (ring->calc_idx_update) {
958 ring->calc_idx_update = false;
959 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
960 }
961 }
962 }
963 }
964
965 static int mtk_poll_rx(struct napi_struct *napi, int budget,
966 struct mtk_eth *eth)
967 {
968 struct mtk_rx_ring *ring;
969 int idx;
970 struct sk_buff *skb;
971 u8 *data, *new_data;
972 struct mtk_rx_dma *rxd, trxd;
973 int done = 0;
974
975 while (done < budget) {
976 struct net_device *netdev;
977 unsigned int pktlen;
978 dma_addr_t dma_addr;
979 int mac = 0;
980
981 ring = mtk_get_rx_ring(eth);
982 if (unlikely(!ring))
983 goto rx_done;
984
985 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
986 rxd = &ring->dma[idx];
987 data = ring->data[idx];
988
989 mtk_rx_get_desc(&trxd, rxd);
990 if (!(trxd.rxd2 & RX_DMA_DONE))
991 break;
992
993 /* find out which mac the packet come from. values start at 1 */
994 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
995 RX_DMA_FPORT_MASK;
996 mac--;
997
998 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
999 !eth->netdev[mac]))
1000 goto release_desc;
1001
1002 netdev = eth->netdev[mac];
1003
1004 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
1005 goto release_desc;
1006
1007 /* alloc new buffer */
1008 new_data = napi_alloc_frag(ring->frag_size);
1009 if (unlikely(!new_data)) {
1010 netdev->stats.rx_dropped++;
1011 goto release_desc;
1012 }
1013 dma_addr = dma_map_single(eth->dev,
1014 new_data + NET_SKB_PAD,
1015 ring->buf_size,
1016 DMA_FROM_DEVICE);
1017 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
1018 skb_free_frag(new_data);
1019 netdev->stats.rx_dropped++;
1020 goto release_desc;
1021 }
1022
1023 /* receive data */
1024 skb = build_skb(data, ring->frag_size);
1025 if (unlikely(!skb)) {
1026 skb_free_frag(new_data);
1027 netdev->stats.rx_dropped++;
1028 goto release_desc;
1029 }
1030 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1031
1032 dma_unmap_single(eth->dev, trxd.rxd1,
1033 ring->buf_size, DMA_FROM_DEVICE);
1034 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1035 skb->dev = netdev;
1036 skb_put(skb, pktlen);
1037 if (trxd.rxd4 & RX_DMA_L4_VALID)
1038 skb->ip_summed = CHECKSUM_UNNECESSARY;
1039 else
1040 skb_checksum_none_assert(skb);
1041 skb->protocol = eth_type_trans(skb, netdev);
1042
1043 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
1044 RX_DMA_VID(trxd.rxd3))
1045 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1046 RX_DMA_VID(trxd.rxd3));
1047 skb_record_rx_queue(skb, 0);
1048 napi_gro_receive(napi, skb);
1049
1050 ring->data[idx] = new_data;
1051 rxd->rxd1 = (unsigned int)dma_addr;
1052
1053 release_desc:
1054 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
1055
1056 ring->calc_idx = idx;
1057
1058 done++;
1059 }
1060
1061 rx_done:
1062 if (done) {
1063 /* make sure that all changes to the dma ring are flushed before
1064 * we continue
1065 */
1066 wmb();
1067 mtk_update_rx_cpu_idx(eth);
1068 }
1069
1070 return done;
1071 }
1072
1073 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
1074 {
1075 struct mtk_tx_ring *ring = &eth->tx_ring;
1076 struct mtk_tx_dma *desc;
1077 struct sk_buff *skb;
1078 struct mtk_tx_buf *tx_buf;
1079 unsigned int done[MTK_MAX_DEVS];
1080 unsigned int bytes[MTK_MAX_DEVS];
1081 u32 cpu, dma;
1082 int total = 0, i;
1083
1084 memset(done, 0, sizeof(done));
1085 memset(bytes, 0, sizeof(bytes));
1086
1087 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
1088 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1089
1090 desc = mtk_qdma_phys_to_virt(ring, cpu);
1091
1092 while ((cpu != dma) && budget) {
1093 u32 next_cpu = desc->txd2;
1094 int mac = 0;
1095
1096 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
1097 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
1098 break;
1099
1100 tx_buf = mtk_desc_to_tx_buf(ring, desc);
1101 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
1102 mac = 1;
1103
1104 skb = tx_buf->skb;
1105 if (!skb)
1106 break;
1107
1108 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1109 bytes[mac] += skb->len;
1110 done[mac]++;
1111 budget--;
1112 }
1113 mtk_tx_unmap(eth, tx_buf);
1114
1115 ring->last_free = desc;
1116 atomic_inc(&ring->free_count);
1117
1118 cpu = next_cpu;
1119 }
1120
1121 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1122
1123 for (i = 0; i < MTK_MAC_COUNT; i++) {
1124 if (!eth->netdev[i] || !done[i])
1125 continue;
1126 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1127 total += done[i];
1128 }
1129
1130 if (mtk_queue_stopped(eth) &&
1131 (atomic_read(&ring->free_count) > ring->thresh))
1132 mtk_wake_queue(eth);
1133
1134 return total;
1135 }
1136
1137 static void mtk_handle_status_irq(struct mtk_eth *eth)
1138 {
1139 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
1140
1141 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
1142 mtk_stats_update(eth);
1143 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1144 MTK_INT_STATUS2);
1145 }
1146 }
1147
1148 static int mtk_napi_tx(struct napi_struct *napi, int budget)
1149 {
1150 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
1151 u32 status, mask;
1152 int tx_done = 0;
1153
1154 mtk_handle_status_irq(eth);
1155 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
1156 tx_done = mtk_poll_tx(eth, budget);
1157
1158 if (unlikely(netif_msg_intr(eth))) {
1159 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1160 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1161 dev_info(eth->dev,
1162 "done tx %d, intr 0x%08x/0x%x\n",
1163 tx_done, status, mask);
1164 }
1165
1166 if (tx_done == budget)
1167 return budget;
1168
1169 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1170 if (status & MTK_TX_DONE_INT)
1171 return budget;
1172
1173 napi_complete(napi);
1174 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1175
1176 return tx_done;
1177 }
1178
1179 static int mtk_napi_rx(struct napi_struct *napi, int budget)
1180 {
1181 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1182 u32 status, mask;
1183 int rx_done = 0;
1184 int remain_budget = budget;
1185
1186 mtk_handle_status_irq(eth);
1187
1188 poll_again:
1189 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
1190 rx_done = mtk_poll_rx(napi, remain_budget, eth);
1191
1192 if (unlikely(netif_msg_intr(eth))) {
1193 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1194 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
1195 dev_info(eth->dev,
1196 "done rx %d, intr 0x%08x/0x%x\n",
1197 rx_done, status, mask);
1198 }
1199 if (rx_done == remain_budget)
1200 return budget;
1201
1202 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1203 if (status & MTK_RX_DONE_INT) {
1204 remain_budget -= rx_done;
1205 goto poll_again;
1206 }
1207 napi_complete(napi);
1208 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1209
1210 return rx_done + budget - remain_budget;
1211 }
1212
1213 static int mtk_tx_alloc(struct mtk_eth *eth)
1214 {
1215 struct mtk_tx_ring *ring = &eth->tx_ring;
1216 int i, sz = sizeof(*ring->dma);
1217
1218 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1219 GFP_KERNEL);
1220 if (!ring->buf)
1221 goto no_tx_mem;
1222
1223 ring->dma = dma_alloc_coherent(eth->dev,
1224 MTK_DMA_SIZE * sz,
1225 &ring->phys,
1226 GFP_ATOMIC | __GFP_ZERO);
1227 if (!ring->dma)
1228 goto no_tx_mem;
1229
1230 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1231 for (i = 0; i < MTK_DMA_SIZE; i++) {
1232 int next = (i + 1) % MTK_DMA_SIZE;
1233 u32 next_ptr = ring->phys + next * sz;
1234
1235 ring->dma[i].txd2 = next_ptr;
1236 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1237 }
1238
1239 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1240 ring->next_free = &ring->dma[0];
1241 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1242 ring->thresh = MAX_SKB_FRAGS;
1243
1244 /* make sure that all changes to the dma ring are flushed before we
1245 * continue
1246 */
1247 wmb();
1248
1249 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1250 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1251 mtk_w32(eth,
1252 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1253 MTK_QTX_CRX_PTR);
1254 mtk_w32(eth,
1255 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1256 MTK_QTX_DRX_PTR);
1257 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1258
1259 return 0;
1260
1261 no_tx_mem:
1262 return -ENOMEM;
1263 }
1264
1265 static void mtk_tx_clean(struct mtk_eth *eth)
1266 {
1267 struct mtk_tx_ring *ring = &eth->tx_ring;
1268 int i;
1269
1270 if (ring->buf) {
1271 for (i = 0; i < MTK_DMA_SIZE; i++)
1272 mtk_tx_unmap(eth, &ring->buf[i]);
1273 kfree(ring->buf);
1274 ring->buf = NULL;
1275 }
1276
1277 if (ring->dma) {
1278 dma_free_coherent(eth->dev,
1279 MTK_DMA_SIZE * sizeof(*ring->dma),
1280 ring->dma,
1281 ring->phys);
1282 ring->dma = NULL;
1283 }
1284 }
1285
1286 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
1287 {
1288 struct mtk_rx_ring *ring;
1289 int rx_data_len, rx_dma_size;
1290 int i;
1291 u32 offset = 0;
1292
1293 if (rx_flag == MTK_RX_FLAGS_QDMA) {
1294 if (ring_no)
1295 return -EINVAL;
1296 ring = &eth->rx_ring_qdma;
1297 offset = 0x1000;
1298 } else {
1299 ring = &eth->rx_ring[ring_no];
1300 }
1301
1302 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1303 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1304 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1305 } else {
1306 rx_data_len = ETH_DATA_LEN;
1307 rx_dma_size = MTK_DMA_SIZE;
1308 }
1309
1310 ring->frag_size = mtk_max_frag_size(rx_data_len);
1311 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1312 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
1313 GFP_KERNEL);
1314 if (!ring->data)
1315 return -ENOMEM;
1316
1317 for (i = 0; i < rx_dma_size; i++) {
1318 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1319 if (!ring->data[i])
1320 return -ENOMEM;
1321 }
1322
1323 ring->dma = dma_alloc_coherent(eth->dev,
1324 rx_dma_size * sizeof(*ring->dma),
1325 &ring->phys,
1326 GFP_ATOMIC | __GFP_ZERO);
1327 if (!ring->dma)
1328 return -ENOMEM;
1329
1330 for (i = 0; i < rx_dma_size; i++) {
1331 dma_addr_t dma_addr = dma_map_single(eth->dev,
1332 ring->data[i] + NET_SKB_PAD,
1333 ring->buf_size,
1334 DMA_FROM_DEVICE);
1335 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1336 return -ENOMEM;
1337 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1338
1339 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1340 }
1341 ring->dma_size = rx_dma_size;
1342 ring->calc_idx_update = false;
1343 ring->calc_idx = rx_dma_size - 1;
1344 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
1345 /* make sure that all changes to the dma ring are flushed before we
1346 * continue
1347 */
1348 wmb();
1349
1350 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
1351 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
1352 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
1353 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
1354
1355 return 0;
1356 }
1357
1358 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
1359 {
1360 int i;
1361
1362 if (ring->data && ring->dma) {
1363 for (i = 0; i < ring->dma_size; i++) {
1364 if (!ring->data[i])
1365 continue;
1366 if (!ring->dma[i].rxd1)
1367 continue;
1368 dma_unmap_single(eth->dev,
1369 ring->dma[i].rxd1,
1370 ring->buf_size,
1371 DMA_FROM_DEVICE);
1372 skb_free_frag(ring->data[i]);
1373 }
1374 kfree(ring->data);
1375 ring->data = NULL;
1376 }
1377
1378 if (ring->dma) {
1379 dma_free_coherent(eth->dev,
1380 ring->dma_size * sizeof(*ring->dma),
1381 ring->dma,
1382 ring->phys);
1383 ring->dma = NULL;
1384 }
1385 }
1386
1387 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1388 {
1389 int i;
1390 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1391 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1392
1393 /* set LRO rings to auto-learn modes */
1394 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1395
1396 /* validate LRO ring */
1397 ring_ctrl_dw2 |= MTK_RING_VLD;
1398
1399 /* set AGE timer (unit: 20us) */
1400 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1401 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1402
1403 /* set max AGG timer (unit: 20us) */
1404 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1405
1406 /* set max LRO AGG count */
1407 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1408 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1409
1410 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1411 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1412 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1413 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1414 }
1415
1416 /* IPv4 checksum update enable */
1417 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1418
1419 /* switch priority comparison to packet count mode */
1420 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1421
1422 /* bandwidth threshold setting */
1423 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1424
1425 /* auto-learn score delta setting */
1426 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1427
1428 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1429 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1430 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1431
1432 /* set HW LRO mode & the max aggregation count for rx packets */
1433 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1434
1435 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1436 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1437
1438 /* enable HW LRO */
1439 lro_ctrl_dw0 |= MTK_LRO_EN;
1440
1441 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1442 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1443
1444 return 0;
1445 }
1446
1447 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1448 {
1449 int i;
1450 u32 val;
1451
1452 /* relinquish lro rings, flush aggregated packets */
1453 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1454
1455 /* wait for relinquishments done */
1456 for (i = 0; i < 10; i++) {
1457 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1458 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1459 msleep(20);
1460 continue;
1461 }
1462 break;
1463 }
1464
1465 /* invalidate lro rings */
1466 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1467 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1468
1469 /* disable HW LRO */
1470 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1471 }
1472
1473 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1474 {
1475 u32 reg_val;
1476
1477 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1478
1479 /* invalidate the IP setting */
1480 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1481
1482 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1483
1484 /* validate the IP setting */
1485 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1486 }
1487
1488 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1489 {
1490 u32 reg_val;
1491
1492 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1493
1494 /* invalidate the IP setting */
1495 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1496
1497 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1498 }
1499
1500 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1501 {
1502 int cnt = 0;
1503 int i;
1504
1505 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1506 if (mac->hwlro_ip[i])
1507 cnt++;
1508 }
1509
1510 return cnt;
1511 }
1512
1513 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1514 struct ethtool_rxnfc *cmd)
1515 {
1516 struct ethtool_rx_flow_spec *fsp =
1517 (struct ethtool_rx_flow_spec *)&cmd->fs;
1518 struct mtk_mac *mac = netdev_priv(dev);
1519 struct mtk_eth *eth = mac->hw;
1520 int hwlro_idx;
1521
1522 if ((fsp->flow_type != TCP_V4_FLOW) ||
1523 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1524 (fsp->location > 1))
1525 return -EINVAL;
1526
1527 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1528 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1529
1530 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1531
1532 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1533
1534 return 0;
1535 }
1536
1537 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1538 struct ethtool_rxnfc *cmd)
1539 {
1540 struct ethtool_rx_flow_spec *fsp =
1541 (struct ethtool_rx_flow_spec *)&cmd->fs;
1542 struct mtk_mac *mac = netdev_priv(dev);
1543 struct mtk_eth *eth = mac->hw;
1544 int hwlro_idx;
1545
1546 if (fsp->location > 1)
1547 return -EINVAL;
1548
1549 mac->hwlro_ip[fsp->location] = 0;
1550 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1551
1552 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1553
1554 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1555
1556 return 0;
1557 }
1558
1559 static void mtk_hwlro_netdev_disable(struct net_device *dev)
1560 {
1561 struct mtk_mac *mac = netdev_priv(dev);
1562 struct mtk_eth *eth = mac->hw;
1563 int i, hwlro_idx;
1564
1565 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1566 mac->hwlro_ip[i] = 0;
1567 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1568
1569 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1570 }
1571
1572 mac->hwlro_ip_cnt = 0;
1573 }
1574
1575 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1576 struct ethtool_rxnfc *cmd)
1577 {
1578 struct mtk_mac *mac = netdev_priv(dev);
1579 struct ethtool_rx_flow_spec *fsp =
1580 (struct ethtool_rx_flow_spec *)&cmd->fs;
1581
1582 /* only tcp dst ipv4 is meaningful, others are meaningless */
1583 fsp->flow_type = TCP_V4_FLOW;
1584 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1585 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1586
1587 fsp->h_u.tcp_ip4_spec.ip4src = 0;
1588 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1589 fsp->h_u.tcp_ip4_spec.psrc = 0;
1590 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1591 fsp->h_u.tcp_ip4_spec.pdst = 0;
1592 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
1593 fsp->h_u.tcp_ip4_spec.tos = 0;
1594 fsp->m_u.tcp_ip4_spec.tos = 0xff;
1595
1596 return 0;
1597 }
1598
1599 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
1600 struct ethtool_rxnfc *cmd,
1601 u32 *rule_locs)
1602 {
1603 struct mtk_mac *mac = netdev_priv(dev);
1604 int cnt = 0;
1605 int i;
1606
1607 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1608 if (mac->hwlro_ip[i]) {
1609 rule_locs[cnt] = i;
1610 cnt++;
1611 }
1612 }
1613
1614 cmd->rule_cnt = cnt;
1615
1616 return 0;
1617 }
1618
1619 static netdev_features_t mtk_fix_features(struct net_device *dev,
1620 netdev_features_t features)
1621 {
1622 if (!(features & NETIF_F_LRO)) {
1623 struct mtk_mac *mac = netdev_priv(dev);
1624 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1625
1626 if (ip_cnt) {
1627 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
1628
1629 features |= NETIF_F_LRO;
1630 }
1631 }
1632
1633 return features;
1634 }
1635
1636 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
1637 {
1638 int err = 0;
1639
1640 if (!((dev->features ^ features) & NETIF_F_LRO))
1641 return 0;
1642
1643 if (!(features & NETIF_F_LRO))
1644 mtk_hwlro_netdev_disable(dev);
1645
1646 return err;
1647 }
1648
1649 /* wait for DMA to finish whatever it is doing before we start using it again */
1650 static int mtk_dma_busy_wait(struct mtk_eth *eth)
1651 {
1652 unsigned long t_start = jiffies;
1653
1654 while (1) {
1655 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1656 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1657 return 0;
1658 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1659 break;
1660 }
1661
1662 dev_err(eth->dev, "DMA init timeout\n");
1663 return -1;
1664 }
1665
1666 static int mtk_dma_init(struct mtk_eth *eth)
1667 {
1668 int err;
1669 u32 i;
1670
1671 if (mtk_dma_busy_wait(eth))
1672 return -EBUSY;
1673
1674 /* QDMA needs scratch memory for internal reordering of the
1675 * descriptors
1676 */
1677 err = mtk_init_fq_dma(eth);
1678 if (err)
1679 return err;
1680
1681 err = mtk_tx_alloc(eth);
1682 if (err)
1683 return err;
1684
1685 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
1686 if (err)
1687 return err;
1688
1689 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
1690 if (err)
1691 return err;
1692
1693 if (eth->hwlro) {
1694 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1695 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
1696 if (err)
1697 return err;
1698 }
1699 err = mtk_hwlro_rx_init(eth);
1700 if (err)
1701 return err;
1702 }
1703
1704 /* Enable random early drop and set drop threshold automatically */
1705 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1706 MTK_QDMA_FC_THRES);
1707 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1708
1709 return 0;
1710 }
1711
1712 static void mtk_dma_free(struct mtk_eth *eth)
1713 {
1714 int i;
1715
1716 for (i = 0; i < MTK_MAC_COUNT; i++)
1717 if (eth->netdev[i])
1718 netdev_reset_queue(eth->netdev[i]);
1719 if (eth->scratch_ring) {
1720 dma_free_coherent(eth->dev,
1721 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1722 eth->scratch_ring,
1723 eth->phy_scratch_ring);
1724 eth->scratch_ring = NULL;
1725 eth->phy_scratch_ring = 0;
1726 }
1727 mtk_tx_clean(eth);
1728 mtk_rx_clean(eth, &eth->rx_ring[0]);
1729 mtk_rx_clean(eth, &eth->rx_ring_qdma);
1730
1731 if (eth->hwlro) {
1732 mtk_hwlro_rx_uninit(eth);
1733 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1734 mtk_rx_clean(eth, &eth->rx_ring[i]);
1735 }
1736
1737 kfree(eth->scratch_head);
1738 }
1739
1740 static void mtk_tx_timeout(struct net_device *dev)
1741 {
1742 struct mtk_mac *mac = netdev_priv(dev);
1743 struct mtk_eth *eth = mac->hw;
1744
1745 eth->netdev[mac->id]->stats.tx_errors++;
1746 netif_err(eth, tx_err, dev,
1747 "transmit timed out\n");
1748 schedule_work(&eth->pending_work);
1749 }
1750
1751 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
1752 {
1753 struct mtk_eth *eth = _eth;
1754
1755 if (likely(napi_schedule_prep(&eth->rx_napi))) {
1756 __napi_schedule(&eth->rx_napi);
1757 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
1758 }
1759
1760 return IRQ_HANDLED;
1761 }
1762
1763 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1764 {
1765 struct mtk_eth *eth = _eth;
1766
1767 if (likely(napi_schedule_prep(&eth->tx_napi))) {
1768 __napi_schedule(&eth->tx_napi);
1769 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1770 }
1771
1772 return IRQ_HANDLED;
1773 }
1774
1775 #ifdef CONFIG_NET_POLL_CONTROLLER
1776 static void mtk_poll_controller(struct net_device *dev)
1777 {
1778 struct mtk_mac *mac = netdev_priv(dev);
1779 struct mtk_eth *eth = mac->hw;
1780
1781 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1782 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
1783 mtk_handle_irq_rx(eth->irq[2], dev);
1784 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1785 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1786 }
1787 #endif
1788
1789 static int mtk_start_dma(struct mtk_eth *eth)
1790 {
1791 int err;
1792
1793 err = mtk_dma_init(eth);
1794 if (err) {
1795 mtk_dma_free(eth);
1796 return err;
1797 }
1798
1799 mtk_w32(eth,
1800 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
1801 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |
1802 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1803 MTK_RX_BT_32DWORDS,
1804 MTK_QDMA_GLO_CFG);
1805
1806 mtk_w32(eth,
1807 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1808 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
1809 MTK_PDMA_GLO_CFG);
1810
1811 return 0;
1812 }
1813
1814 static int mtk_open(struct net_device *dev)
1815 {
1816 struct mtk_mac *mac = netdev_priv(dev);
1817 struct mtk_eth *eth = mac->hw;
1818
1819 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1820 if (!atomic_read(&eth->dma_refcnt)) {
1821 int err = mtk_start_dma(eth);
1822
1823 if (err)
1824 return err;
1825
1826 napi_enable(&eth->tx_napi);
1827 napi_enable(&eth->rx_napi);
1828 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1829 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1830 }
1831 atomic_inc(&eth->dma_refcnt);
1832
1833 phy_start(dev->phydev);
1834 netif_start_queue(dev);
1835
1836 return 0;
1837 }
1838
1839 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1840 {
1841 u32 val;
1842 int i;
1843
1844 /* stop the dma engine */
1845 spin_lock_bh(&eth->page_lock);
1846 val = mtk_r32(eth, glo_cfg);
1847 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1848 glo_cfg);
1849 spin_unlock_bh(&eth->page_lock);
1850
1851 /* wait for dma stop */
1852 for (i = 0; i < 10; i++) {
1853 val = mtk_r32(eth, glo_cfg);
1854 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1855 msleep(20);
1856 continue;
1857 }
1858 break;
1859 }
1860 }
1861
1862 static int mtk_stop(struct net_device *dev)
1863 {
1864 struct mtk_mac *mac = netdev_priv(dev);
1865 struct mtk_eth *eth = mac->hw;
1866
1867 netif_tx_disable(dev);
1868 phy_stop(dev->phydev);
1869
1870 /* only shutdown DMA if this is the last user */
1871 if (!atomic_dec_and_test(&eth->dma_refcnt))
1872 return 0;
1873
1874 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1875 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
1876 napi_disable(&eth->tx_napi);
1877 napi_disable(&eth->rx_napi);
1878
1879 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1880 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG);
1881
1882 mtk_dma_free(eth);
1883
1884 return 0;
1885 }
1886
1887 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
1888 {
1889 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1890 reset_bits,
1891 reset_bits);
1892
1893 usleep_range(1000, 1100);
1894 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1895 reset_bits,
1896 ~reset_bits);
1897 mdelay(10);
1898 }
1899
1900 static void mtk_clk_disable(struct mtk_eth *eth)
1901 {
1902 int clk;
1903
1904 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
1905 clk_disable_unprepare(eth->clks[clk]);
1906 }
1907
1908 static int mtk_clk_enable(struct mtk_eth *eth)
1909 {
1910 int clk, ret;
1911
1912 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
1913 ret = clk_prepare_enable(eth->clks[clk]);
1914 if (ret)
1915 goto err_disable_clks;
1916 }
1917
1918 return 0;
1919
1920 err_disable_clks:
1921 while (--clk >= 0)
1922 clk_disable_unprepare(eth->clks[clk]);
1923
1924 return ret;
1925 }
1926
1927 static int mtk_hw_init(struct mtk_eth *eth)
1928 {
1929 int i, val, ret;
1930
1931 if (test_and_set_bit(MTK_HW_INIT, &eth->state))
1932 return 0;
1933
1934 pm_runtime_enable(eth->dev);
1935 pm_runtime_get_sync(eth->dev);
1936
1937 ret = mtk_clk_enable(eth);
1938 if (ret)
1939 goto err_disable_pm;
1940
1941 ethsys_reset(eth, RSTCTRL_FE);
1942 ethsys_reset(eth, RSTCTRL_PPE);
1943
1944 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
1945 for (i = 0; i < MTK_MAC_COUNT; i++) {
1946 if (!eth->mac[i])
1947 continue;
1948 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id);
1949 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id);
1950 }
1951 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
1952
1953 /* Set GE2 driving and slew rate */
1954 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1955
1956 /* set GE2 TDSEL */
1957 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1958
1959 /* set GE2 TUNE */
1960 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1961
1962 /* GE1, Force 1000M/FD, FC ON */
1963 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1964
1965 /* GE2, Force 1000M/FD, FC ON */
1966 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1967
1968 /* Indicates CDM to parse the MTK special tag from CPU
1969 * which also is working out for untag packets.
1970 */
1971 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
1972 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
1973
1974 /* Enable RX VLan Offloading */
1975 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1976
1977 /* enable interrupt delay for RX */
1978 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
1979
1980 /* disable delay and normal interrupt */
1981 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1982 mtk_tx_irq_disable(eth, ~0);
1983 mtk_rx_irq_disable(eth, ~0);
1984 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1985 mtk_w32(eth, 0, MTK_RST_GL);
1986
1987 /* FE int grouping */
1988 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1989 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1990 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1991 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1992 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
1993
1994 for (i = 0; i < 2; i++) {
1995 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1996
1997 /* setup the forward port to send frame to PDMA */
1998 val &= ~0xffff;
1999
2000 /* Enable RX checksum */
2001 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
2002
2003 /* setup the mac dma */
2004 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
2005 }
2006
2007 return 0;
2008
2009 err_disable_pm:
2010 pm_runtime_put_sync(eth->dev);
2011 pm_runtime_disable(eth->dev);
2012
2013 return ret;
2014 }
2015
2016 static int mtk_hw_deinit(struct mtk_eth *eth)
2017 {
2018 if (!test_and_clear_bit(MTK_HW_INIT, &eth->state))
2019 return 0;
2020
2021 mtk_clk_disable(eth);
2022
2023 pm_runtime_put_sync(eth->dev);
2024 pm_runtime_disable(eth->dev);
2025
2026 return 0;
2027 }
2028
2029 static int __init mtk_init(struct net_device *dev)
2030 {
2031 struct mtk_mac *mac = netdev_priv(dev);
2032 struct mtk_eth *eth = mac->hw;
2033 const char *mac_addr;
2034
2035 mac_addr = of_get_mac_address(mac->of_node);
2036 if (mac_addr)
2037 ether_addr_copy(dev->dev_addr, mac_addr);
2038
2039 /* If the mac address is invalid, use random mac address */
2040 if (!is_valid_ether_addr(dev->dev_addr)) {
2041 eth_hw_addr_random(dev);
2042 dev_err(eth->dev, "generated random MAC address %pM\n",
2043 dev->dev_addr);
2044 }
2045
2046 return mtk_phy_connect(dev);
2047 }
2048
2049 static void mtk_uninit(struct net_device *dev)
2050 {
2051 struct mtk_mac *mac = netdev_priv(dev);
2052 struct mtk_eth *eth = mac->hw;
2053
2054 phy_disconnect(dev->phydev);
2055 if (of_phy_is_fixed_link(mac->of_node))
2056 of_phy_deregister_fixed_link(mac->of_node);
2057 mtk_tx_irq_disable(eth, ~0);
2058 mtk_rx_irq_disable(eth, ~0);
2059 }
2060
2061 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2062 {
2063 switch (cmd) {
2064 case SIOCGMIIPHY:
2065 case SIOCGMIIREG:
2066 case SIOCSMIIREG:
2067 return phy_mii_ioctl(dev->phydev, ifr, cmd);
2068 default:
2069 break;
2070 }
2071
2072 return -EOPNOTSUPP;
2073 }
2074
2075 static void mtk_pending_work(struct work_struct *work)
2076 {
2077 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
2078 int err, i;
2079 unsigned long restart = 0;
2080
2081 rtnl_lock();
2082
2083 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
2084
2085 while (test_and_set_bit_lock(MTK_RESETTING, &eth->state))
2086 cpu_relax();
2087
2088 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
2089 /* stop all devices to make sure that dma is properly shut down */
2090 for (i = 0; i < MTK_MAC_COUNT; i++) {
2091 if (!eth->netdev[i])
2092 continue;
2093 mtk_stop(eth->netdev[i]);
2094 __set_bit(i, &restart);
2095 }
2096 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
2097
2098 /* restart underlying hardware such as power, clock, pin mux
2099 * and the connected phy
2100 */
2101 mtk_hw_deinit(eth);
2102
2103 if (eth->dev->pins)
2104 pinctrl_select_state(eth->dev->pins->p,
2105 eth->dev->pins->default_state);
2106 mtk_hw_init(eth);
2107
2108 for (i = 0; i < MTK_MAC_COUNT; i++) {
2109 if (!eth->mac[i] ||
2110 of_phy_is_fixed_link(eth->mac[i]->of_node))
2111 continue;
2112 err = phy_init_hw(eth->netdev[i]->phydev);
2113 if (err)
2114 dev_err(eth->dev, "%s: PHY init failed.\n",
2115 eth->netdev[i]->name);
2116 }
2117
2118 /* restart DMA and enable IRQs */
2119 for (i = 0; i < MTK_MAC_COUNT; i++) {
2120 if (!test_bit(i, &restart))
2121 continue;
2122 err = mtk_open(eth->netdev[i]);
2123 if (err) {
2124 netif_alert(eth, ifup, eth->netdev[i],
2125 "Driver up/down cycle failed, closing device.\n");
2126 dev_close(eth->netdev[i]);
2127 }
2128 }
2129
2130 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
2131
2132 clear_bit_unlock(MTK_RESETTING, &eth->state);
2133
2134 rtnl_unlock();
2135 }
2136
2137 static int mtk_free_dev(struct mtk_eth *eth)
2138 {
2139 int i;
2140
2141 for (i = 0; i < MTK_MAC_COUNT; i++) {
2142 if (!eth->netdev[i])
2143 continue;
2144 free_netdev(eth->netdev[i]);
2145 }
2146
2147 return 0;
2148 }
2149
2150 static int mtk_unreg_dev(struct mtk_eth *eth)
2151 {
2152 int i;
2153
2154 for (i = 0; i < MTK_MAC_COUNT; i++) {
2155 if (!eth->netdev[i])
2156 continue;
2157 unregister_netdev(eth->netdev[i]);
2158 }
2159
2160 return 0;
2161 }
2162
2163 static int mtk_cleanup(struct mtk_eth *eth)
2164 {
2165 mtk_unreg_dev(eth);
2166 mtk_free_dev(eth);
2167 cancel_work_sync(&eth->pending_work);
2168
2169 return 0;
2170 }
2171
2172 static int mtk_get_link_ksettings(struct net_device *ndev,
2173 struct ethtool_link_ksettings *cmd)
2174 {
2175 struct mtk_mac *mac = netdev_priv(ndev);
2176
2177 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2178 return -EBUSY;
2179
2180 phy_ethtool_ksettings_get(ndev->phydev, cmd);
2181
2182 return 0;
2183 }
2184
2185 static int mtk_set_link_ksettings(struct net_device *ndev,
2186 const struct ethtool_link_ksettings *cmd)
2187 {
2188 struct mtk_mac *mac = netdev_priv(ndev);
2189
2190 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2191 return -EBUSY;
2192
2193 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
2194 }
2195
2196 static void mtk_get_drvinfo(struct net_device *dev,
2197 struct ethtool_drvinfo *info)
2198 {
2199 struct mtk_mac *mac = netdev_priv(dev);
2200
2201 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2202 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2203 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2204 }
2205
2206 static u32 mtk_get_msglevel(struct net_device *dev)
2207 {
2208 struct mtk_mac *mac = netdev_priv(dev);
2209
2210 return mac->hw->msg_enable;
2211 }
2212
2213 static void mtk_set_msglevel(struct net_device *dev, u32 value)
2214 {
2215 struct mtk_mac *mac = netdev_priv(dev);
2216
2217 mac->hw->msg_enable = value;
2218 }
2219
2220 static int mtk_nway_reset(struct net_device *dev)
2221 {
2222 struct mtk_mac *mac = netdev_priv(dev);
2223
2224 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2225 return -EBUSY;
2226
2227 return genphy_restart_aneg(dev->phydev);
2228 }
2229
2230 static u32 mtk_get_link(struct net_device *dev)
2231 {
2232 struct mtk_mac *mac = netdev_priv(dev);
2233 int err;
2234
2235 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2236 return -EBUSY;
2237
2238 err = genphy_update_link(dev->phydev);
2239 if (err)
2240 return ethtool_op_get_link(dev);
2241
2242 return dev->phydev->link;
2243 }
2244
2245 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2246 {
2247 int i;
2248
2249 switch (stringset) {
2250 case ETH_SS_STATS:
2251 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2252 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2253 data += ETH_GSTRING_LEN;
2254 }
2255 break;
2256 }
2257 }
2258
2259 static int mtk_get_sset_count(struct net_device *dev, int sset)
2260 {
2261 switch (sset) {
2262 case ETH_SS_STATS:
2263 return ARRAY_SIZE(mtk_ethtool_stats);
2264 default:
2265 return -EOPNOTSUPP;
2266 }
2267 }
2268
2269 static void mtk_get_ethtool_stats(struct net_device *dev,
2270 struct ethtool_stats *stats, u64 *data)
2271 {
2272 struct mtk_mac *mac = netdev_priv(dev);
2273 struct mtk_hw_stats *hwstats = mac->hw_stats;
2274 u64 *data_src, *data_dst;
2275 unsigned int start;
2276 int i;
2277
2278 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2279 return;
2280
2281 if (netif_running(dev) && netif_device_present(dev)) {
2282 if (spin_trylock_bh(&hwstats->stats_lock)) {
2283 mtk_stats_update_mac(mac);
2284 spin_unlock_bh(&hwstats->stats_lock);
2285 }
2286 }
2287
2288 data_src = (u64 *)hwstats;
2289
2290 do {
2291 data_dst = data;
2292 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2293
2294 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2295 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2296 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2297 }
2298
2299 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2300 u32 *rule_locs)
2301 {
2302 int ret = -EOPNOTSUPP;
2303
2304 switch (cmd->cmd) {
2305 case ETHTOOL_GRXRINGS:
2306 if (dev->features & NETIF_F_LRO) {
2307 cmd->data = MTK_MAX_RX_RING_NUM;
2308 ret = 0;
2309 }
2310 break;
2311 case ETHTOOL_GRXCLSRLCNT:
2312 if (dev->features & NETIF_F_LRO) {
2313 struct mtk_mac *mac = netdev_priv(dev);
2314
2315 cmd->rule_cnt = mac->hwlro_ip_cnt;
2316 ret = 0;
2317 }
2318 break;
2319 case ETHTOOL_GRXCLSRULE:
2320 if (dev->features & NETIF_F_LRO)
2321 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2322 break;
2323 case ETHTOOL_GRXCLSRLALL:
2324 if (dev->features & NETIF_F_LRO)
2325 ret = mtk_hwlro_get_fdir_all(dev, cmd,
2326 rule_locs);
2327 break;
2328 default:
2329 break;
2330 }
2331
2332 return ret;
2333 }
2334
2335 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2336 {
2337 int ret = -EOPNOTSUPP;
2338
2339 switch (cmd->cmd) {
2340 case ETHTOOL_SRXCLSRLINS:
2341 if (dev->features & NETIF_F_LRO)
2342 ret = mtk_hwlro_add_ipaddr(dev, cmd);
2343 break;
2344 case ETHTOOL_SRXCLSRLDEL:
2345 if (dev->features & NETIF_F_LRO)
2346 ret = mtk_hwlro_del_ipaddr(dev, cmd);
2347 break;
2348 default:
2349 break;
2350 }
2351
2352 return ret;
2353 }
2354
2355 static const struct ethtool_ops mtk_ethtool_ops = {
2356 .get_link_ksettings = mtk_get_link_ksettings,
2357 .set_link_ksettings = mtk_set_link_ksettings,
2358 .get_drvinfo = mtk_get_drvinfo,
2359 .get_msglevel = mtk_get_msglevel,
2360 .set_msglevel = mtk_set_msglevel,
2361 .nway_reset = mtk_nway_reset,
2362 .get_link = mtk_get_link,
2363 .get_strings = mtk_get_strings,
2364 .get_sset_count = mtk_get_sset_count,
2365 .get_ethtool_stats = mtk_get_ethtool_stats,
2366 .get_rxnfc = mtk_get_rxnfc,
2367 .set_rxnfc = mtk_set_rxnfc,
2368 };
2369
2370 static const struct net_device_ops mtk_netdev_ops = {
2371 .ndo_init = mtk_init,
2372 .ndo_uninit = mtk_uninit,
2373 .ndo_open = mtk_open,
2374 .ndo_stop = mtk_stop,
2375 .ndo_start_xmit = mtk_start_xmit,
2376 .ndo_set_mac_address = mtk_set_mac_address,
2377 .ndo_validate_addr = eth_validate_addr,
2378 .ndo_do_ioctl = mtk_do_ioctl,
2379 .ndo_tx_timeout = mtk_tx_timeout,
2380 .ndo_get_stats64 = mtk_get_stats64,
2381 .ndo_fix_features = mtk_fix_features,
2382 .ndo_set_features = mtk_set_features,
2383 #ifdef CONFIG_NET_POLL_CONTROLLER
2384 .ndo_poll_controller = mtk_poll_controller,
2385 #endif
2386 };
2387
2388 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2389 {
2390 struct mtk_mac *mac;
2391 const __be32 *_id = of_get_property(np, "reg", NULL);
2392 int id, err;
2393
2394 if (!_id) {
2395 dev_err(eth->dev, "missing mac id\n");
2396 return -EINVAL;
2397 }
2398
2399 id = be32_to_cpup(_id);
2400 if (id >= MTK_MAC_COUNT) {
2401 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2402 return -EINVAL;
2403 }
2404
2405 if (eth->netdev[id]) {
2406 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2407 return -EINVAL;
2408 }
2409
2410 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2411 if (!eth->netdev[id]) {
2412 dev_err(eth->dev, "alloc_etherdev failed\n");
2413 return -ENOMEM;
2414 }
2415 mac = netdev_priv(eth->netdev[id]);
2416 eth->mac[id] = mac;
2417 mac->id = id;
2418 mac->hw = eth;
2419 mac->of_node = np;
2420
2421 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2422 mac->hwlro_ip_cnt = 0;
2423
2424 mac->hw_stats = devm_kzalloc(eth->dev,
2425 sizeof(*mac->hw_stats),
2426 GFP_KERNEL);
2427 if (!mac->hw_stats) {
2428 dev_err(eth->dev, "failed to allocate counter memory\n");
2429 err = -ENOMEM;
2430 goto free_netdev;
2431 }
2432 spin_lock_init(&mac->hw_stats->stats_lock);
2433 u64_stats_init(&mac->hw_stats->syncp);
2434 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2435
2436 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
2437 eth->netdev[id]->watchdog_timeo = 5 * HZ;
2438 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2439 eth->netdev[id]->base_addr = (unsigned long)eth->base;
2440
2441 eth->netdev[id]->hw_features = MTK_HW_FEATURES;
2442 if (eth->hwlro)
2443 eth->netdev[id]->hw_features |= NETIF_F_LRO;
2444
2445 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
2446 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2447 eth->netdev[id]->features |= MTK_HW_FEATURES;
2448 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
2449
2450 eth->netdev[id]->irq = eth->irq[0];
2451 eth->netdev[id]->dev.of_node = np;
2452
2453 return 0;
2454
2455 free_netdev:
2456 free_netdev(eth->netdev[id]);
2457 return err;
2458 }
2459
2460 static int mtk_get_chip_id(struct mtk_eth *eth, u32 *chip_id)
2461 {
2462 u32 val[2], id[4];
2463
2464 regmap_read(eth->ethsys, ETHSYS_CHIPID0_3, &val[0]);
2465 regmap_read(eth->ethsys, ETHSYS_CHIPID4_7, &val[1]);
2466
2467 id[3] = ((val[0] >> 16) & 0xff) - '0';
2468 id[2] = ((val[0] >> 24) & 0xff) - '0';
2469 id[1] = (val[1] & 0xff) - '0';
2470 id[0] = ((val[1] >> 8) & 0xff) - '0';
2471
2472 *chip_id = (id[3] * 1000) + (id[2] * 100) +
2473 (id[1] * 10) + id[0];
2474
2475 if (!(*chip_id)) {
2476 dev_err(eth->dev, "failed to get chip id\n");
2477 return -ENODEV;
2478 }
2479
2480 dev_info(eth->dev, "chip id = %d\n", *chip_id);
2481
2482 return 0;
2483 }
2484
2485 static bool mtk_is_hwlro_supported(struct mtk_eth *eth)
2486 {
2487 switch (eth->chip_id) {
2488 case MT7622_ETH:
2489 case MT7623_ETH:
2490 return true;
2491 }
2492
2493 return false;
2494 }
2495
2496 static int mtk_probe(struct platform_device *pdev)
2497 {
2498 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2499 struct device_node *mac_np;
2500 const struct of_device_id *match;
2501 struct mtk_eth *eth;
2502 int err;
2503 int i;
2504
2505 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2506 if (!eth)
2507 return -ENOMEM;
2508
2509 match = of_match_device(of_mtk_match, &pdev->dev);
2510 eth->soc = (struct mtk_soc_data *)match->data;
2511
2512 eth->dev = &pdev->dev;
2513 eth->base = devm_ioremap_resource(&pdev->dev, res);
2514 if (IS_ERR(eth->base))
2515 return PTR_ERR(eth->base);
2516
2517 spin_lock_init(&eth->page_lock);
2518 spin_lock_init(&eth->tx_irq_lock);
2519 spin_lock_init(&eth->rx_irq_lock);
2520
2521 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2522 "mediatek,ethsys");
2523 if (IS_ERR(eth->ethsys)) {
2524 dev_err(&pdev->dev, "no ethsys regmap found\n");
2525 return PTR_ERR(eth->ethsys);
2526 }
2527
2528 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
2529 eth->sgmiisys =
2530 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2531 "mediatek,sgmiisys");
2532 if (IS_ERR(eth->sgmiisys)) {
2533 dev_err(&pdev->dev, "no sgmiisys regmap found\n");
2534 return PTR_ERR(eth->sgmiisys);
2535 }
2536 }
2537
2538 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2539 "mediatek,pctl");
2540 if (IS_ERR(eth->pctl)) {
2541 dev_err(&pdev->dev, "no pctl regmap found\n");
2542 return PTR_ERR(eth->pctl);
2543 }
2544
2545 for (i = 0; i < 3; i++) {
2546 eth->irq[i] = platform_get_irq(pdev, i);
2547 if (eth->irq[i] < 0) {
2548 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
2549 return -ENXIO;
2550 }
2551 }
2552 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
2553 eth->clks[i] = devm_clk_get(eth->dev,
2554 mtk_clks_source_name[i]);
2555 if (IS_ERR(eth->clks[i])) {
2556 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
2557 return -EPROBE_DEFER;
2558 if (eth->soc->required_clks & BIT(i)) {
2559 dev_err(&pdev->dev, "clock %s not found\n",
2560 mtk_clks_source_name[i]);
2561 return -EINVAL;
2562 }
2563 eth->clks[i] = NULL;
2564 }
2565 }
2566
2567 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
2568 INIT_WORK(&eth->pending_work, mtk_pending_work);
2569
2570 err = mtk_hw_init(eth);
2571 if (err)
2572 return err;
2573
2574 err = mtk_get_chip_id(eth, &eth->chip_id);
2575 if (err)
2576 return err;
2577
2578 eth->hwlro = mtk_is_hwlro_supported(eth);
2579
2580 for_each_child_of_node(pdev->dev.of_node, mac_np) {
2581 if (!of_device_is_compatible(mac_np,
2582 "mediatek,eth-mac"))
2583 continue;
2584
2585 if (!of_device_is_available(mac_np))
2586 continue;
2587
2588 err = mtk_add_mac(eth, mac_np);
2589 if (err)
2590 goto err_deinit_hw;
2591 }
2592
2593 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
2594 dev_name(eth->dev), eth);
2595 if (err)
2596 goto err_free_dev;
2597
2598 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
2599 dev_name(eth->dev), eth);
2600 if (err)
2601 goto err_free_dev;
2602
2603 err = mtk_mdio_init(eth);
2604 if (err)
2605 goto err_free_dev;
2606
2607 for (i = 0; i < MTK_MAX_DEVS; i++) {
2608 if (!eth->netdev[i])
2609 continue;
2610
2611 err = register_netdev(eth->netdev[i]);
2612 if (err) {
2613 dev_err(eth->dev, "error bringing up device\n");
2614 goto err_deinit_mdio;
2615 } else
2616 netif_info(eth, probe, eth->netdev[i],
2617 "mediatek frame engine at 0x%08lx, irq %d\n",
2618 eth->netdev[i]->base_addr, eth->irq[0]);
2619 }
2620
2621 /* we run 2 devices on the same DMA ring so we need a dummy device
2622 * for NAPI to work
2623 */
2624 init_dummy_netdev(&eth->dummy_dev);
2625 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
2626 MTK_NAPI_WEIGHT);
2627 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
2628 MTK_NAPI_WEIGHT);
2629
2630 platform_set_drvdata(pdev, eth);
2631
2632 return 0;
2633
2634 err_deinit_mdio:
2635 mtk_mdio_cleanup(eth);
2636 err_free_dev:
2637 mtk_free_dev(eth);
2638 err_deinit_hw:
2639 mtk_hw_deinit(eth);
2640
2641 return err;
2642 }
2643
2644 static int mtk_remove(struct platform_device *pdev)
2645 {
2646 struct mtk_eth *eth = platform_get_drvdata(pdev);
2647 int i;
2648
2649 /* stop all devices to make sure that dma is properly shut down */
2650 for (i = 0; i < MTK_MAC_COUNT; i++) {
2651 if (!eth->netdev[i])
2652 continue;
2653 mtk_stop(eth->netdev[i]);
2654 }
2655
2656 mtk_hw_deinit(eth);
2657
2658 netif_napi_del(&eth->tx_napi);
2659 netif_napi_del(&eth->rx_napi);
2660 mtk_cleanup(eth);
2661 mtk_mdio_cleanup(eth);
2662
2663 return 0;
2664 }
2665
2666 static const struct mtk_soc_data mt2701_data = {
2667 .caps = MTK_GMAC1_TRGMII,
2668 .required_clks = MT7623_CLKS_BITMAP
2669 };
2670
2671 static const struct mtk_soc_data mt7622_data = {
2672 .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW,
2673 .required_clks = MT7622_CLKS_BITMAP
2674 };
2675
2676 static const struct mtk_soc_data mt7623_data = {
2677 .caps = MTK_GMAC1_TRGMII,
2678 .required_clks = MT7623_CLKS_BITMAP
2679 };
2680
2681 const struct of_device_id of_mtk_match[] = {
2682 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
2683 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
2684 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
2685 {},
2686 };
2687 MODULE_DEVICE_TABLE(of, of_mtk_match);
2688
2689 static struct platform_driver mtk_driver = {
2690 .probe = mtk_probe,
2691 .remove = mtk_remove,
2692 .driver = {
2693 .name = "mtk_soc_eth",
2694 .of_match_table = of_mtk_match,
2695 },
2696 };
2697
2698 module_platform_driver(mtk_driver);
2699
2700 MODULE_LICENSE("GPL");
2701 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2702 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");