2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
37 #include <linux/slab.h>
39 #include <linux/tcp.h>
41 #include <linux/delay.h>
42 #include <linux/workqueue.h>
43 #include <linux/if_vlan.h>
44 #include <linux/prefetch.h>
45 #include <linux/debugfs.h>
46 #include <linux/mii.h>
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.30"
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
66 /* This is the worst case number of transmit list elements for a single skb:
67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
68 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
69 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
70 #define TX_MAX_PENDING 1024
71 #define TX_DEF_PENDING 63
73 #define TX_WATCHDOG (5 * HZ)
74 #define NAPI_WEIGHT 64
75 #define PHY_RETRIES 1000
77 #define SKY2_EEPROM_MAGIC 0x9955aabb
79 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
81 static const u32 default_msg
=
82 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
83 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
86 static int debug
= -1; /* defaults above */
87 module_param(debug
, int, 0);
88 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
90 static int copybreak __read_mostly
= 128;
91 module_param(copybreak
, int, 0);
92 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
94 static int disable_msi
= 0;
95 module_param(disable_msi
, int, 0);
96 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
98 static int legacy_pme
= 0;
99 module_param(legacy_pme
, int, 0);
100 MODULE_PARM_DESC(legacy_pme
, "Legacy power management");
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table
) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E01) }, /* SK-9E21M */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4355) }, /* 88E8040T */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4357) }, /* 88E8042 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x435A) }, /* 88E8048 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4365) }, /* 88E8070 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436B) }, /* 88E8071 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436C) }, /* 88E8072 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4381) }, /* 88E8059 */
147 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
149 /* Avoid conditionals by using array */
150 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
151 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
152 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
154 static void sky2_set_multicast(struct net_device
*dev
);
155 static irqreturn_t
sky2_intr(int irq
, void *dev_id
);
157 /* Access to PHY via serial interconnect */
158 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
162 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
163 gma_write16(hw
, port
, GM_SMI_CTRL
,
164 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
166 for (i
= 0; i
< PHY_RETRIES
; i
++) {
167 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
171 if (!(ctrl
& GM_SMI_CT_BUSY
))
177 dev_warn(&hw
->pdev
->dev
, "%s: phy write timeout\n", hw
->dev
[port
]->name
);
181 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
185 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
189 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
190 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
192 for (i
= 0; i
< PHY_RETRIES
; i
++) {
193 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
197 if (ctrl
& GM_SMI_CT_RD_VAL
) {
198 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
205 dev_warn(&hw
->pdev
->dev
, "%s: phy read timeout\n", hw
->dev
[port
]->name
);
208 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
212 static inline u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
215 __gm_phy_read(hw
, port
, reg
, &v
);
220 static void sky2_power_on(struct sky2_hw
*hw
)
222 /* switch power to VCC (WA for VAUX problem) */
223 sky2_write8(hw
, B0_POWER_CTRL
,
224 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
226 /* disable Core Clock Division, */
227 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
229 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> CHIP_REV_YU_XL_A1
)
230 /* enable bits are inverted */
231 sky2_write8(hw
, B2_Y2_CLK_GATE
,
232 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
233 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
234 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
236 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
238 if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
) {
241 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
243 reg
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
244 /* set all bits to 0 except bits 15..12 and 8 */
245 reg
&= P_ASPM_CONTROL_MSK
;
246 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg
);
248 reg
= sky2_pci_read32(hw
, PCI_DEV_REG5
);
249 /* set all bits to 0 except bits 28 & 27 */
250 reg
&= P_CTL_TIM_VMAIN_AV_MSK
;
251 sky2_pci_write32(hw
, PCI_DEV_REG5
, reg
);
253 sky2_pci_write32(hw
, PCI_CFG_REG_1
, 0);
255 sky2_write16(hw
, B0_CTST
, Y2_HW_WOL_ON
);
257 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
258 reg
= sky2_read32(hw
, B2_GP_IO
);
259 reg
|= GLB_GPIO_STAT_RACE_DIS
;
260 sky2_write32(hw
, B2_GP_IO
, reg
);
262 sky2_read32(hw
, B2_GP_IO
);
265 /* Turn on "driver loaded" LED */
266 sky2_write16(hw
, B0_CTST
, Y2_LED_STAT_ON
);
269 static void sky2_power_aux(struct sky2_hw
*hw
)
271 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> CHIP_REV_YU_XL_A1
)
272 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
274 /* enable bits are inverted */
275 sky2_write8(hw
, B2_Y2_CLK_GATE
,
276 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
277 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
278 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
280 /* switch power to VAUX if supported and PME from D3cold */
281 if ( (sky2_read32(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
282 pci_pme_capable(hw
->pdev
, PCI_D3cold
))
283 sky2_write8(hw
, B0_POWER_CTRL
,
284 (PC_VAUX_ENA
| PC_VCC_ENA
|
285 PC_VAUX_ON
| PC_VCC_OFF
));
287 /* turn off "driver loaded LED" */
288 sky2_write16(hw
, B0_CTST
, Y2_LED_STAT_OFF
);
291 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
295 /* disable all GMAC IRQ's */
296 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
298 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
299 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
300 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
301 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
303 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
304 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
305 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
308 /* flow control to advertise bits */
309 static const u16 copper_fc_adv
[] = {
311 [FC_TX
] = PHY_M_AN_ASP
,
312 [FC_RX
] = PHY_M_AN_PC
,
313 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
316 /* flow control to advertise bits when using 1000BaseX */
317 static const u16 fiber_fc_adv
[] = {
318 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
319 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
320 [FC_RX
] = PHY_M_P_SYM_MD_X
,
321 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
324 /* flow control to GMA disable bits */
325 static const u16 gm_fc_disable
[] = {
326 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
327 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
328 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
333 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
335 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
336 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
338 if ( (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) &&
339 !(hw
->flags
& SKY2_HW_NEWER_PHY
)) {
340 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
342 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
344 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
346 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
347 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
348 /* set downshift counter to 3x and enable downshift */
349 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
351 /* set master & slave downshift counter to 1x */
352 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
354 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
357 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
358 if (sky2_is_copper(hw
)) {
359 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
360 /* enable automatic crossover */
361 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
363 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
364 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
367 /* Enable Class A driver for FE+ A0 */
368 spec
= gm_phy_read(hw
, port
, PHY_MARV_FE_SPEC_2
);
369 spec
|= PHY_M_FESC_SEL_CL_A
;
370 gm_phy_write(hw
, port
, PHY_MARV_FE_SPEC_2
, spec
);
373 /* disable energy detect */
374 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
376 /* enable automatic crossover */
377 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
379 /* downshift on PHY 88E1112 and 88E1149 is changed */
380 if ( (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) &&
381 (hw
->flags
& SKY2_HW_NEWER_PHY
)) {
382 /* set downshift counter to 3x and enable downshift */
383 ctrl
&= ~PHY_M_PC_DSC_MSK
;
384 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
388 /* workaround for deviation #4.88 (CRC errors) */
389 /* disable Automatic Crossover */
391 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
394 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
396 /* special setup for PHY 88E1112 Fiber */
397 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& (hw
->flags
& SKY2_HW_FIBRE_PHY
)) {
398 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
400 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
401 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
402 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
403 ctrl
&= ~PHY_M_MAC_MD_MSK
;
404 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
405 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
407 if (hw
->pmd_type
== 'P') {
408 /* select page 1 to access Fiber registers */
409 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
411 /* for SFP-module set SIGDET polarity to low */
412 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
413 ctrl
|= PHY_M_FIB_SIGD_POL
;
414 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
417 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
425 if (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) {
426 if (sky2_is_copper(hw
)) {
427 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
428 ct1000
|= PHY_M_1000C_AFD
;
429 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
430 ct1000
|= PHY_M_1000C_AHD
;
431 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
432 adv
|= PHY_M_AN_100_FD
;
433 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
434 adv
|= PHY_M_AN_100_HD
;
435 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
436 adv
|= PHY_M_AN_10_FD
;
437 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
438 adv
|= PHY_M_AN_10_HD
;
440 } else { /* special defines for FIBER (88E1040S only) */
441 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
442 adv
|= PHY_M_AN_1000X_AFD
;
443 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
444 adv
|= PHY_M_AN_1000X_AHD
;
447 /* Restart Auto-negotiation */
448 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
450 /* forced speed/duplex settings */
451 ct1000
= PHY_M_1000C_MSE
;
453 /* Disable auto update for duplex flow control and duplex */
454 reg
|= GM_GPCR_AU_DUP_DIS
| GM_GPCR_AU_SPD_DIS
;
456 switch (sky2
->speed
) {
458 ctrl
|= PHY_CT_SP1000
;
459 reg
|= GM_GPCR_SPEED_1000
;
462 ctrl
|= PHY_CT_SP100
;
463 reg
|= GM_GPCR_SPEED_100
;
467 if (sky2
->duplex
== DUPLEX_FULL
) {
468 reg
|= GM_GPCR_DUP_FULL
;
469 ctrl
|= PHY_CT_DUP_MD
;
470 } else if (sky2
->speed
< SPEED_1000
)
471 sky2
->flow_mode
= FC_NONE
;
474 if (sky2
->flags
& SKY2_FLAG_AUTO_PAUSE
) {
475 if (sky2_is_copper(hw
))
476 adv
|= copper_fc_adv
[sky2
->flow_mode
];
478 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
480 reg
|= GM_GPCR_AU_FCT_DIS
;
481 reg
|= gm_fc_disable
[sky2
->flow_mode
];
483 /* Forward pause packets to GMAC? */
484 if (sky2
->flow_mode
& FC_RX
)
485 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
487 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
490 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
492 if (hw
->flags
& SKY2_HW_GIGABIT
)
493 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
495 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
496 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
498 /* Setup Phy LED's */
499 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
502 switch (hw
->chip_id
) {
503 case CHIP_ID_YUKON_FE
:
504 /* on 88E3082 these bits are at 11..9 (shifted left) */
505 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
507 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
509 /* delete ACT LED control bits */
510 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
511 /* change ACT LED control to blink mode */
512 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
513 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
516 case CHIP_ID_YUKON_FE_P
:
517 /* Enable Link Partner Next Page */
518 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
519 ctrl
|= PHY_M_PC_ENA_LIP_NP
;
521 /* disable Energy Detect and enable scrambler */
522 ctrl
&= ~(PHY_M_PC_ENA_ENE_DT
| PHY_M_PC_DIS_SCRAMB
);
523 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
525 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
526 ctrl
= PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL
) |
527 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK
) |
528 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED
);
530 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
533 case CHIP_ID_YUKON_XL
:
534 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
536 /* select page 3 to access LED control register */
537 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
539 /* set LED Function Control register */
540 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
541 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
542 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
543 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
544 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
546 /* set Polarity Control register */
547 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
548 (PHY_M_POLC_LS1_P_MIX(4) |
549 PHY_M_POLC_IS0_P_MIX(4) |
550 PHY_M_POLC_LOS_CTRL(2) |
551 PHY_M_POLC_INIT_CTRL(2) |
552 PHY_M_POLC_STA1_CTRL(2) |
553 PHY_M_POLC_STA0_CTRL(2)));
555 /* restore page register */
556 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
559 case CHIP_ID_YUKON_EC_U
:
560 case CHIP_ID_YUKON_EX
:
561 case CHIP_ID_YUKON_SUPR
:
562 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
564 /* select page 3 to access LED control register */
565 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
567 /* set LED Function Control register */
568 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
569 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
570 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
571 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
572 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
574 /* set Blink Rate in LED Timer Control Register */
575 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
576 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
577 /* restore page register */
578 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
582 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
583 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
585 /* turn off the Rx LED (LED_RX) */
586 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
589 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_UL_2
) {
590 /* apply fixes in PHY AFE */
591 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
593 /* increase differential signal amplitude in 10BASE-T */
594 gm_phy_write(hw
, port
, 0x18, 0xaa99);
595 gm_phy_write(hw
, port
, 0x17, 0x2011);
597 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
598 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
599 gm_phy_write(hw
, port
, 0x18, 0xa204);
600 gm_phy_write(hw
, port
, 0x17, 0x2002);
603 /* set page register to 0 */
604 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
605 } else if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
606 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
607 /* apply workaround for integrated resistors calibration */
608 gm_phy_write(hw
, port
, PHY_MARV_PAGE_ADDR
, 17);
609 gm_phy_write(hw
, port
, PHY_MARV_PAGE_DATA
, 0x3f60);
610 } else if (hw
->chip_id
== CHIP_ID_YUKON_OPT
&& hw
->chip_rev
== 0) {
611 /* apply fixes in PHY AFE */
612 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0x00ff);
614 /* apply RDAC termination workaround */
615 gm_phy_write(hw
, port
, 24, 0x2800);
616 gm_phy_write(hw
, port
, 23, 0x2001);
618 /* set page register back to 0 */
619 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
620 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
&&
621 hw
->chip_id
< CHIP_ID_YUKON_SUPR
) {
622 /* no effect on Yukon-XL */
623 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
625 if (!(sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) ||
626 sky2
->speed
== SPEED_100
) {
627 /* turn on 100 Mbps LED (LED_LINK100) */
628 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
632 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
634 } else if (hw
->chip_id
== CHIP_ID_YUKON_PRM
&&
635 (sky2_read8(hw
, B2_MAC_CFG
) & 0xf) == 0x7) {
637 /* This a phy register setup workaround copied from vendor driver. */
638 static const struct {
644 /* { 0x155, 0x130b },*/
650 /* { 0x154, 0x2f39 },*/
654 /* { 0x158, 0x1223 },*/
661 /* Start Workaround for OptimaEEE Rev.Z0 */
662 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0x00fb);
664 gm_phy_write(hw
, port
, 1, 0x4099);
665 gm_phy_write(hw
, port
, 3, 0x1120);
666 gm_phy_write(hw
, port
, 11, 0x113c);
667 gm_phy_write(hw
, port
, 14, 0x8100);
668 gm_phy_write(hw
, port
, 15, 0x112a);
669 gm_phy_write(hw
, port
, 17, 0x1008);
671 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0x00fc);
672 gm_phy_write(hw
, port
, 1, 0x20b0);
674 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0x00ff);
676 for (i
= 0; i
< ARRAY_SIZE(eee_afe
); i
++) {
677 /* apply AFE settings */
678 gm_phy_write(hw
, port
, 17, eee_afe
[i
].val
);
679 gm_phy_write(hw
, port
, 16, eee_afe
[i
].reg
| 1u<<13);
682 /* End Workaround for OptimaEEE */
683 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
685 /* Enable 10Base-Te (EEE) */
686 if (hw
->chip_id
>= CHIP_ID_YUKON_PRM
) {
687 reg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
688 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
,
689 reg
| PHY_M_10B_TE_ENABLE
);
693 /* Enable phy interrupt on auto-negotiation complete (or link up) */
694 if (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
695 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
697 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
700 static const u32 phy_power
[] = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
701 static const u32 coma_mode
[] = { PCI_Y2_PHY1_COMA
, PCI_Y2_PHY2_COMA
};
703 static void sky2_phy_power_up(struct sky2_hw
*hw
, unsigned port
)
707 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
708 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
709 reg1
&= ~phy_power
[port
];
711 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> CHIP_REV_YU_XL_A1
)
712 reg1
|= coma_mode
[port
];
714 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
715 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
716 sky2_pci_read32(hw
, PCI_DEV_REG1
);
718 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
719 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_ANE
);
720 else if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
)
721 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
724 static void sky2_phy_power_down(struct sky2_hw
*hw
, unsigned port
)
729 /* release GPHY Control reset */
730 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
732 /* release GMAC reset */
733 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
735 if (hw
->flags
& SKY2_HW_NEWER_PHY
) {
736 /* select page 2 to access MAC control register */
737 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
739 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
740 /* allow GMII Power Down */
741 ctrl
&= ~PHY_M_MAC_GMIF_PUP
;
742 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
744 /* set page register back to 0 */
745 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
748 /* setup General Purpose Control Register */
749 gma_write16(hw
, port
, GM_GP_CTRL
,
750 GM_GPCR_FL_PASS
| GM_GPCR_SPEED_100
|
751 GM_GPCR_AU_DUP_DIS
| GM_GPCR_AU_FCT_DIS
|
754 if (hw
->chip_id
!= CHIP_ID_YUKON_EC
) {
755 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
756 /* select page 2 to access MAC control register */
757 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
759 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
760 /* enable Power Down */
761 ctrl
|= PHY_M_PC_POW_D_ENA
;
762 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
764 /* set page register back to 0 */
765 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
768 /* set IEEE compatible Power Down Mode (dev. #4.99) */
769 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_PDOWN
);
772 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
773 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
774 reg1
|= phy_power
[port
]; /* set PHY to PowerDown/COMA Mode */
775 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
776 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
779 /* configure IPG according to used link speed */
780 static void sky2_set_ipg(struct sky2_port
*sky2
)
784 reg
= gma_read16(sky2
->hw
, sky2
->port
, GM_SERIAL_MODE
);
785 reg
&= ~GM_SMOD_IPG_MSK
;
786 if (sky2
->speed
> SPEED_100
)
787 reg
|= IPG_DATA_VAL(IPG_DATA_DEF_1000
);
789 reg
|= IPG_DATA_VAL(IPG_DATA_DEF_10_100
);
790 gma_write16(sky2
->hw
, sky2
->port
, GM_SERIAL_MODE
, reg
);
794 static void sky2_enable_rx_tx(struct sky2_port
*sky2
)
796 struct sky2_hw
*hw
= sky2
->hw
;
797 unsigned port
= sky2
->port
;
800 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
801 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
802 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
805 /* Force a renegotiation */
806 static void sky2_phy_reinit(struct sky2_port
*sky2
)
808 spin_lock_bh(&sky2
->phy_lock
);
809 sky2_phy_init(sky2
->hw
, sky2
->port
);
810 sky2_enable_rx_tx(sky2
);
811 spin_unlock_bh(&sky2
->phy_lock
);
814 /* Put device in state to listen for Wake On Lan */
815 static void sky2_wol_init(struct sky2_port
*sky2
)
817 struct sky2_hw
*hw
= sky2
->hw
;
818 unsigned port
= sky2
->port
;
819 enum flow_control save_mode
;
822 /* Bring hardware out of reset */
823 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
824 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
826 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
827 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
830 * sky2_reset will re-enable on resume
832 save_mode
= sky2
->flow_mode
;
833 ctrl
= sky2
->advertising
;
835 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
836 sky2
->flow_mode
= FC_NONE
;
838 spin_lock_bh(&sky2
->phy_lock
);
839 sky2_phy_power_up(hw
, port
);
840 sky2_phy_init(hw
, port
);
841 spin_unlock_bh(&sky2
->phy_lock
);
843 sky2
->flow_mode
= save_mode
;
844 sky2
->advertising
= ctrl
;
846 /* Set GMAC to no flow control and auto update for speed/duplex */
847 gma_write16(hw
, port
, GM_GP_CTRL
,
848 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
849 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
851 /* Set WOL address */
852 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
853 sky2
->netdev
->dev_addr
, ETH_ALEN
);
855 /* Turn on appropriate WOL control bits */
856 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
858 if (sky2
->wol
& WAKE_PHY
)
859 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
861 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
863 if (sky2
->wol
& WAKE_MAGIC
)
864 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
866 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;
868 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
869 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
871 /* Disable PiG firmware */
872 sky2_write16(hw
, B0_CTST
, Y2_HW_WOL_OFF
);
874 /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */
876 u32 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
877 reg1
|= PCI_Y2_PME_LEGACY
;
878 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
882 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
883 sky2_read32(hw
, B0_CTST
);
886 static void sky2_set_tx_stfwd(struct sky2_hw
*hw
, unsigned port
)
888 struct net_device
*dev
= hw
->dev
[port
];
890 if ( (hw
->chip_id
== CHIP_ID_YUKON_EX
&&
891 hw
->chip_rev
!= CHIP_REV_YU_EX_A0
) ||
892 hw
->chip_id
>= CHIP_ID_YUKON_FE_P
) {
893 /* Yukon-Extreme B0 and further Extreme devices */
894 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_ENA
);
895 } else if (dev
->mtu
> ETH_DATA_LEN
) {
896 /* set Tx GMAC FIFO Almost Empty Threshold */
897 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
898 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
900 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
902 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_ENA
);
905 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
907 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
911 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
913 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
914 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
916 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
918 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&&
919 hw
->chip_rev
== CHIP_REV_YU_XL_A0
&&
921 /* WA DEV_472 -- looks like crossed wires on port 2 */
922 /* clear GMAC 1 Control reset */
923 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
925 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
926 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
927 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
928 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
929 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
932 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
934 /* Enable Transmit FIFO Underrun */
935 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
937 spin_lock_bh(&sky2
->phy_lock
);
938 sky2_phy_power_up(hw
, port
);
939 sky2_phy_init(hw
, port
);
940 spin_unlock_bh(&sky2
->phy_lock
);
943 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
944 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
946 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
947 gma_read16(hw
, port
, i
);
948 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
950 /* transmit control */
951 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
953 /* receive control reg: unicast + multicast + no FCS */
954 gma_write16(hw
, port
, GM_RX_CTRL
,
955 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
957 /* transmit flow control */
958 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
960 /* transmit parameter */
961 gma_write16(hw
, port
, GM_TX_PARAM
,
962 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
963 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
964 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
965 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
967 /* serial mode register */
968 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
969 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF_1000
);
971 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
972 reg
|= GM_SMOD_JUMBO_ENA
;
974 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
975 hw
->chip_rev
== CHIP_REV_YU_EC_U_B1
)
976 reg
|= GM_NEW_FLOW_CTRL
;
978 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
980 /* virtual address for data */
981 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
983 /* physical address: used for pause frames */
984 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
986 /* ignore counter overflows */
987 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
988 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
989 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
991 /* Configure Rx MAC FIFO */
992 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
993 rx_reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
994 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
995 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
996 rx_reg
|= GMF_RX_OVER_ON
;
998 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), rx_reg
);
1000 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
1001 /* Hardware errata - clear flush mask */
1002 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), 0);
1004 /* Flush Rx MAC FIFO on any flow control or error */
1005 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
1008 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
1009 reg
= RX_GMF_FL_THR_DEF
+ 1;
1010 /* Another magic mystery workaround from sk98lin */
1011 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
1012 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
1014 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), reg
);
1016 /* Configure Tx MAC FIFO */
1017 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
1018 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
1020 /* On chips without ram buffer, pause is controlled by MAC level */
1021 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
)) {
1022 /* Pause threshold is scaled by 8 in bytes */
1023 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
1024 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
1028 sky2_write16(hw
, SK_REG(port
, RX_GMF_UP_THR
), reg
);
1029 sky2_write16(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768 / 8);
1031 sky2_set_tx_stfwd(hw
, port
);
1034 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
1035 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
1036 /* disable dynamic watermark */
1037 reg
= sky2_read16(hw
, SK_REG(port
, TX_GMF_EA
));
1038 reg
&= ~TX_DYN_WM_ENA
;
1039 sky2_write16(hw
, SK_REG(port
, TX_GMF_EA
), reg
);
1043 /* Assign Ram Buffer allocation to queue */
1044 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
1048 /* convert from K bytes to qwords used for hw register */
1051 end
= start
+ space
- 1;
1053 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
1054 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
1055 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
1056 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
1057 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
1059 if (q
== Q_R1
|| q
== Q_R2
) {
1060 u32 tp
= space
- space
/4;
1062 /* On receive queue's set the thresholds
1063 * give receiver priority when > 3/4 full
1064 * send pause when down to 2K
1066 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
1067 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
1069 tp
= space
- 2048/8;
1070 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
1071 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
1073 /* Enable store & forward on Tx queue's because
1074 * Tx FIFO is only 1K on Yukon
1076 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
1079 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
1080 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
1083 /* Setup Bus Memory Interface */
1084 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
1086 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
1087 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
1088 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
1089 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
1092 /* Setup prefetch unit registers. This is the interface between
1093 * hardware and driver list elements
1095 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
1096 dma_addr_t addr
, u32 last
)
1098 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1099 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
1100 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), upper_32_bits(addr
));
1101 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), lower_32_bits(addr
));
1102 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
1103 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
1105 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
1108 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
, u16
*slot
)
1110 struct sky2_tx_le
*le
= sky2
->tx_le
+ *slot
;
1112 *slot
= RING_NEXT(*slot
, sky2
->tx_ring_size
);
1117 static void tx_init(struct sky2_port
*sky2
)
1119 struct sky2_tx_le
*le
;
1121 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1122 sky2
->tx_tcpsum
= 0;
1123 sky2
->tx_last_mss
= 0;
1124 netdev_reset_queue(sky2
->netdev
);
1126 le
= get_tx_le(sky2
, &sky2
->tx_prod
);
1128 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1129 sky2
->tx_last_upper
= 0;
1132 /* Update chip's next pointer */
1133 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
1135 /* Make sure write' to descriptors are complete before we tell hardware */
1137 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
1139 /* Synchronize I/O on since next processor may write to tail */
1144 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
1146 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
1147 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
1152 static unsigned sky2_get_rx_threshold(struct sky2_port
*sky2
)
1156 /* Space needed for frame data + headers rounded up */
1157 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1159 /* Stopping point for hardware truncation */
1160 return (size
- 8) / sizeof(u32
);
1163 static unsigned sky2_get_rx_data_size(struct sky2_port
*sky2
)
1165 struct rx_ring_info
*re
;
1168 /* Space needed for frame data + headers rounded up */
1169 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1171 sky2
->rx_nfrags
= size
>> PAGE_SHIFT
;
1172 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1174 /* Compute residue after pages */
1175 size
-= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1177 /* Optimize to handle small packets and headers */
1178 if (size
< copybreak
)
1180 if (size
< ETH_HLEN
)
1186 /* Build description to hardware for one receive segment */
1187 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
1188 dma_addr_t map
, unsigned len
)
1190 struct sky2_rx_le
*le
;
1192 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
1193 le
= sky2_next_rx(sky2
);
1194 le
->addr
= cpu_to_le32(upper_32_bits(map
));
1195 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1198 le
= sky2_next_rx(sky2
);
1199 le
->addr
= cpu_to_le32(lower_32_bits(map
));
1200 le
->length
= cpu_to_le16(len
);
1201 le
->opcode
= op
| HW_OWNER
;
1204 /* Build description to hardware for one possibly fragmented skb */
1205 static void sky2_rx_submit(struct sky2_port
*sky2
,
1206 const struct rx_ring_info
*re
)
1210 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
1212 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
1213 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
1217 static int sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
1220 struct sk_buff
*skb
= re
->skb
;
1223 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
1224 if (pci_dma_mapping_error(pdev
, re
->data_addr
))
1227 dma_unmap_len_set(re
, data_size
, size
);
1229 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1230 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1232 re
->frag_addr
[i
] = skb_frag_dma_map(&pdev
->dev
, frag
, 0,
1233 skb_frag_size(frag
),
1236 if (dma_mapping_error(&pdev
->dev
, re
->frag_addr
[i
]))
1237 goto map_page_error
;
1243 pci_unmap_page(pdev
, re
->frag_addr
[i
],
1244 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
1245 PCI_DMA_FROMDEVICE
);
1248 pci_unmap_single(pdev
, re
->data_addr
, dma_unmap_len(re
, data_size
),
1249 PCI_DMA_FROMDEVICE
);
1252 if (net_ratelimit())
1253 dev_warn(&pdev
->dev
, "%s: rx mapping error\n",
1258 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
1260 struct sk_buff
*skb
= re
->skb
;
1263 pci_unmap_single(pdev
, re
->data_addr
, dma_unmap_len(re
, data_size
),
1264 PCI_DMA_FROMDEVICE
);
1266 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
1267 pci_unmap_page(pdev
, re
->frag_addr
[i
],
1268 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
1269 PCI_DMA_FROMDEVICE
);
1272 /* Tell chip where to start receive checksum.
1273 * Actually has two checksums, but set both same to avoid possible byte
1276 static void rx_set_checksum(struct sky2_port
*sky2
)
1278 struct sky2_rx_le
*le
= sky2_next_rx(sky2
);
1280 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
1282 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
1284 sky2_write32(sky2
->hw
,
1285 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
1286 (sky2
->netdev
->features
& NETIF_F_RXCSUM
)
1287 ? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
1291 * Fixed initial key as seed to RSS.
1293 static const uint32_t rss_init_key
[10] = {
1294 0x7c3351da, 0x51c5cf4e, 0x44adbdd1, 0xe8d38d18, 0x48897c43,
1295 0xb1d60e7e, 0x6a3dd760, 0x01a2e453, 0x16f46f13, 0x1a0e7b30
1298 /* Enable/disable receive hash calculation (RSS) */
1299 static void rx_set_rss(struct net_device
*dev
, netdev_features_t features
)
1301 struct sky2_port
*sky2
= netdev_priv(dev
);
1302 struct sky2_hw
*hw
= sky2
->hw
;
1305 /* Supports IPv6 and other modes */
1306 if (hw
->flags
& SKY2_HW_NEW_LE
) {
1308 sky2_write32(hw
, SK_REG(sky2
->port
, RSS_CFG
), HASH_ALL
);
1311 /* Program RSS initial values */
1312 if (features
& NETIF_F_RXHASH
) {
1313 for (i
= 0; i
< nkeys
; i
++)
1314 sky2_write32(hw
, SK_REG(sky2
->port
, RSS_KEY
+ i
* 4),
1317 /* Need to turn on (undocumented) flag to make hashing work */
1318 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
),
1321 sky2_write32(hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
1322 BMU_ENA_RX_RSS_HASH
);
1324 sky2_write32(hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
1325 BMU_DIS_RX_RSS_HASH
);
1329 * The RX Stop command will not work for Yukon-2 if the BMU does not
1330 * reach the end of packet and since we can't make sure that we have
1331 * incoming data, we must reset the BMU while it is not doing a DMA
1332 * transfer. Since it is possible that the RX path is still active,
1333 * the RX RAM buffer will be stopped first, so any possible incoming
1334 * data will not trigger a DMA. After the RAM buffer is stopped, the
1335 * BMU is polled until any DMA in progress is ended and only then it
1338 static void sky2_rx_stop(struct sky2_port
*sky2
)
1340 struct sky2_hw
*hw
= sky2
->hw
;
1341 unsigned rxq
= rxqaddr
[sky2
->port
];
1344 /* disable the RAM Buffer receive queue */
1345 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
1347 for (i
= 0; i
< 0xffff; i
++)
1348 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
1349 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
1352 netdev_warn(sky2
->netdev
, "receiver stop failed\n");
1354 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
1356 /* reset the Rx prefetch unit */
1357 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1361 /* Clean out receive buffer area, assumes receiver hardware stopped */
1362 static void sky2_rx_clean(struct sky2_port
*sky2
)
1366 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1367 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1368 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1371 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1378 /* Basic MII support */
1379 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1381 struct mii_ioctl_data
*data
= if_mii(ifr
);
1382 struct sky2_port
*sky2
= netdev_priv(dev
);
1383 struct sky2_hw
*hw
= sky2
->hw
;
1384 int err
= -EOPNOTSUPP
;
1386 if (!netif_running(dev
))
1387 return -ENODEV
; /* Phy still in reset */
1391 data
->phy_id
= PHY_ADDR_MARV
;
1397 spin_lock_bh(&sky2
->phy_lock
);
1398 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1399 spin_unlock_bh(&sky2
->phy_lock
);
1401 data
->val_out
= val
;
1406 spin_lock_bh(&sky2
->phy_lock
);
1407 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1409 spin_unlock_bh(&sky2
->phy_lock
);
1415 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1417 static void sky2_vlan_mode(struct net_device
*dev
, netdev_features_t features
)
1419 struct sky2_port
*sky2
= netdev_priv(dev
);
1420 struct sky2_hw
*hw
= sky2
->hw
;
1421 u16 port
= sky2
->port
;
1423 if (features
& NETIF_F_HW_VLAN_RX
)
1424 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1427 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1430 if (features
& NETIF_F_HW_VLAN_TX
) {
1431 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1434 dev
->vlan_features
|= SKY2_VLAN_OFFLOADS
;
1436 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1439 /* Can't do transmit offload of vlan without hw vlan */
1440 dev
->vlan_features
&= ~SKY2_VLAN_OFFLOADS
;
1444 /* Amount of required worst case padding in rx buffer */
1445 static inline unsigned sky2_rx_pad(const struct sky2_hw
*hw
)
1447 return (hw
->flags
& SKY2_HW_RAM_BUFFER
) ? 8 : 2;
1451 * Allocate an skb for receiving. If the MTU is large enough
1452 * make the skb non-linear with a fragment list of pages.
1454 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
, gfp_t gfp
)
1456 struct sk_buff
*skb
;
1459 skb
= __netdev_alloc_skb(sky2
->netdev
,
1460 sky2
->rx_data_size
+ sky2_rx_pad(sky2
->hw
),
1465 if (sky2
->hw
->flags
& SKY2_HW_RAM_BUFFER
) {
1466 unsigned char *start
;
1468 * Workaround for a bug in FIFO that cause hang
1469 * if the FIFO if the receive buffer is not 64 byte aligned.
1470 * The buffer returned from netdev_alloc_skb is
1471 * aligned except if slab debugging is enabled.
1473 start
= PTR_ALIGN(skb
->data
, 8);
1474 skb_reserve(skb
, start
- skb
->data
);
1476 skb_reserve(skb
, NET_IP_ALIGN
);
1478 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1479 struct page
*page
= alloc_page(gfp
);
1483 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1493 static inline void sky2_rx_update(struct sky2_port
*sky2
, unsigned rxq
)
1495 sky2_put_idx(sky2
->hw
, rxq
, sky2
->rx_put
);
1498 static int sky2_alloc_rx_skbs(struct sky2_port
*sky2
)
1500 struct sky2_hw
*hw
= sky2
->hw
;
1503 sky2
->rx_data_size
= sky2_get_rx_data_size(sky2
);
1506 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1507 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1509 re
->skb
= sky2_rx_alloc(sky2
, GFP_KERNEL
);
1513 if (sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
)) {
1514 dev_kfree_skb(re
->skb
);
1523 * Setup receiver buffer pool.
1524 * Normal case this ends up creating one list element for skb
1525 * in the receive ring. Worst case if using large MTU and each
1526 * allocation falls on a different 64 bit region, that results
1527 * in 6 list elements per ring entry.
1528 * One element is used for checksum enable/disable, and one
1529 * extra to avoid wrap.
1531 static void sky2_rx_start(struct sky2_port
*sky2
)
1533 struct sky2_hw
*hw
= sky2
->hw
;
1534 struct rx_ring_info
*re
;
1535 unsigned rxq
= rxqaddr
[sky2
->port
];
1538 sky2
->rx_put
= sky2
->rx_next
= 0;
1541 /* On PCI express lowering the watermark gives better performance */
1542 if (pci_is_pcie(hw
->pdev
))
1543 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1545 /* These chips have no ram buffer?
1546 * MAC Rx RAM Read is controlled by hardware */
1547 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1548 hw
->chip_rev
> CHIP_REV_YU_EC_U_A0
)
1549 sky2_write32(hw
, Q_ADDR(rxq
, Q_TEST
), F_M_RX_RAM_DIS
);
1551 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1553 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1554 rx_set_checksum(sky2
);
1556 if (!(hw
->flags
& SKY2_HW_RSS_BROKEN
))
1557 rx_set_rss(sky2
->netdev
, sky2
->netdev
->features
);
1559 /* submit Rx ring */
1560 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1561 re
= sky2
->rx_ring
+ i
;
1562 sky2_rx_submit(sky2
, re
);
1566 * The receiver hangs if it receives frames larger than the
1567 * packet buffer. As a workaround, truncate oversize frames, but
1568 * the register is limited to 9 bits, so if you do frames > 2052
1569 * you better get the MTU right!
1571 thresh
= sky2_get_rx_threshold(sky2
);
1573 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1575 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1576 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1579 /* Tell chip about available buffers */
1580 sky2_rx_update(sky2
, rxq
);
1582 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
1583 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
1585 * Disable flushing of non ASF packets;
1586 * must be done after initializing the BMUs;
1587 * drivers without ASF support should do this too, otherwise
1588 * it may happen that they cannot run on ASF devices;
1589 * remember that the MAC FIFO isn't reset during initialization.
1591 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_MACSEC_FLUSH_OFF
);
1594 if (hw
->chip_id
>= CHIP_ID_YUKON_SUPR
) {
1595 /* Enable RX Home Address & Routing Header checksum fix */
1596 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_FL_CTRL
),
1597 RX_IPV6_SA_MOB_ENA
| RX_IPV6_DA_MOB_ENA
);
1599 /* Enable TX Home Address & Routing Header checksum fix */
1600 sky2_write32(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_TEST
),
1601 TBMU_TEST_HOME_ADD_FIX_EN
| TBMU_TEST_ROUTING_ADD_FIX_EN
);
1605 static int sky2_alloc_buffers(struct sky2_port
*sky2
)
1607 struct sky2_hw
*hw
= sky2
->hw
;
1609 /* must be power of 2 */
1610 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1611 sky2
->tx_ring_size
*
1612 sizeof(struct sky2_tx_le
),
1617 sky2
->tx_ring
= kcalloc(sky2
->tx_ring_size
, sizeof(struct tx_ring_info
),
1622 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1626 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1628 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1633 return sky2_alloc_rx_skbs(sky2
);
1638 static void sky2_free_buffers(struct sky2_port
*sky2
)
1640 struct sky2_hw
*hw
= sky2
->hw
;
1642 sky2_rx_clean(sky2
);
1645 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1646 sky2
->rx_le
, sky2
->rx_le_map
);
1650 pci_free_consistent(hw
->pdev
,
1651 sky2
->tx_ring_size
* sizeof(struct sky2_tx_le
),
1652 sky2
->tx_le
, sky2
->tx_le_map
);
1655 kfree(sky2
->tx_ring
);
1656 kfree(sky2
->rx_ring
);
1658 sky2
->tx_ring
= NULL
;
1659 sky2
->rx_ring
= NULL
;
1662 static void sky2_hw_up(struct sky2_port
*sky2
)
1664 struct sky2_hw
*hw
= sky2
->hw
;
1665 unsigned port
= sky2
->port
;
1668 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1673 * On dual port PCI-X card, there is an problem where status
1674 * can be received out of order due to split transactions
1676 if (otherdev
&& netif_running(otherdev
) &&
1677 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1680 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1681 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1682 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1685 sky2_mac_init(hw
, port
);
1687 /* Register is number of 4K blocks on internal RAM buffer. */
1688 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1692 netdev_dbg(sky2
->netdev
, "ram buffer %dK\n", ramsize
);
1694 rxspace
= ramsize
/ 2;
1696 rxspace
= 8 + (2*(ramsize
- 16))/3;
1698 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1699 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1701 /* Make sure SyncQ is disabled */
1702 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1706 sky2_qset(hw
, txqaddr
[port
]);
1708 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1709 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
== CHIP_REV_YU_EX_B0
)
1710 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_TEST
), F_TX_CHK_AUTO_OFF
);
1712 /* Set almost empty threshold */
1713 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1714 hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1715 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1717 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1718 sky2
->tx_ring_size
- 1);
1720 sky2_vlan_mode(sky2
->netdev
, sky2
->netdev
->features
);
1721 netdev_update_features(sky2
->netdev
);
1723 sky2_rx_start(sky2
);
1726 /* Setup device IRQ and enable napi to process */
1727 static int sky2_setup_irq(struct sky2_hw
*hw
, const char *name
)
1729 struct pci_dev
*pdev
= hw
->pdev
;
1732 err
= request_irq(pdev
->irq
, sky2_intr
,
1733 (hw
->flags
& SKY2_HW_USE_MSI
) ? 0 : IRQF_SHARED
,
1736 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
1738 hw
->flags
|= SKY2_HW_IRQ_SETUP
;
1740 napi_enable(&hw
->napi
);
1741 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
1742 sky2_read32(hw
, B0_IMSK
);
1749 /* Bring up network interface. */
1750 static int sky2_open(struct net_device
*dev
)
1752 struct sky2_port
*sky2
= netdev_priv(dev
);
1753 struct sky2_hw
*hw
= sky2
->hw
;
1754 unsigned port
= sky2
->port
;
1758 netif_carrier_off(dev
);
1760 err
= sky2_alloc_buffers(sky2
);
1764 /* With single port, IRQ is setup when device is brought up */
1765 if (hw
->ports
== 1 && (err
= sky2_setup_irq(hw
, dev
->name
)))
1770 /* Enable interrupts from phy/mac for port */
1771 imask
= sky2_read32(hw
, B0_IMSK
);
1773 if (hw
->chip_id
== CHIP_ID_YUKON_OPT
||
1774 hw
->chip_id
== CHIP_ID_YUKON_PRM
||
1775 hw
->chip_id
== CHIP_ID_YUKON_OP_2
)
1776 imask
|= Y2_IS_PHY_QLNK
; /* enable PHY Quick Link */
1778 imask
|= portirq_msk
[port
];
1779 sky2_write32(hw
, B0_IMSK
, imask
);
1780 sky2_read32(hw
, B0_IMSK
);
1782 netif_info(sky2
, ifup
, dev
, "enabling interface\n");
1787 sky2_free_buffers(sky2
);
1791 /* Modular subtraction in ring */
1792 static inline int tx_inuse(const struct sky2_port
*sky2
)
1794 return (sky2
->tx_prod
- sky2
->tx_cons
) & (sky2
->tx_ring_size
- 1);
1797 /* Number of list elements available for next tx */
1798 static inline int tx_avail(const struct sky2_port
*sky2
)
1800 return sky2
->tx_pending
- tx_inuse(sky2
);
1803 /* Estimate of number of transmit list elements required */
1804 static unsigned tx_le_req(const struct sk_buff
*skb
)
1808 count
= (skb_shinfo(skb
)->nr_frags
+ 1)
1809 * (sizeof(dma_addr_t
) / sizeof(u32
));
1811 if (skb_is_gso(skb
))
1813 else if (sizeof(dma_addr_t
) == sizeof(u32
))
1814 ++count
; /* possible vlan */
1816 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1822 static void sky2_tx_unmap(struct pci_dev
*pdev
, struct tx_ring_info
*re
)
1824 if (re
->flags
& TX_MAP_SINGLE
)
1825 pci_unmap_single(pdev
, dma_unmap_addr(re
, mapaddr
),
1826 dma_unmap_len(re
, maplen
),
1828 else if (re
->flags
& TX_MAP_PAGE
)
1829 pci_unmap_page(pdev
, dma_unmap_addr(re
, mapaddr
),
1830 dma_unmap_len(re
, maplen
),
1836 * Put one packet in ring for transmit.
1837 * A single packet can generate multiple list elements, and
1838 * the number of ring elements will probably be less than the number
1839 * of list elements used.
1841 static netdev_tx_t
sky2_xmit_frame(struct sk_buff
*skb
,
1842 struct net_device
*dev
)
1844 struct sky2_port
*sky2
= netdev_priv(dev
);
1845 struct sky2_hw
*hw
= sky2
->hw
;
1846 struct sky2_tx_le
*le
= NULL
;
1847 struct tx_ring_info
*re
;
1855 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1856 return NETDEV_TX_BUSY
;
1858 len
= skb_headlen(skb
);
1859 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1861 if (pci_dma_mapping_error(hw
->pdev
, mapping
))
1864 slot
= sky2
->tx_prod
;
1865 netif_printk(sky2
, tx_queued
, KERN_DEBUG
, dev
,
1866 "tx queued, slot %u, len %d\n", slot
, skb
->len
);
1868 /* Send high bits if needed */
1869 upper
= upper_32_bits(mapping
);
1870 if (upper
!= sky2
->tx_last_upper
) {
1871 le
= get_tx_le(sky2
, &slot
);
1872 le
->addr
= cpu_to_le32(upper
);
1873 sky2
->tx_last_upper
= upper
;
1874 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1877 /* Check for TCP Segmentation Offload */
1878 mss
= skb_shinfo(skb
)->gso_size
;
1881 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1882 mss
+= ETH_HLEN
+ ip_hdrlen(skb
) + tcp_hdrlen(skb
);
1884 if (mss
!= sky2
->tx_last_mss
) {
1885 le
= get_tx_le(sky2
, &slot
);
1886 le
->addr
= cpu_to_le32(mss
);
1888 if (hw
->flags
& SKY2_HW_NEW_LE
)
1889 le
->opcode
= OP_MSS
| HW_OWNER
;
1891 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1892 sky2
->tx_last_mss
= mss
;
1898 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1899 if (vlan_tx_tag_present(skb
)) {
1901 le
= get_tx_le(sky2
, &slot
);
1903 le
->opcode
= OP_VLAN
|HW_OWNER
;
1905 le
->opcode
|= OP_VLAN
;
1906 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1910 /* Handle TCP checksum offload */
1911 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1912 /* On Yukon EX (some versions) encoding change. */
1913 if (hw
->flags
& SKY2_HW_AUTO_TX_SUM
)
1914 ctrl
|= CALSUM
; /* auto checksum */
1916 const unsigned offset
= skb_transport_offset(skb
);
1919 tcpsum
= offset
<< 16; /* sum start */
1920 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1922 ctrl
|= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1923 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1926 if (tcpsum
!= sky2
->tx_tcpsum
) {
1927 sky2
->tx_tcpsum
= tcpsum
;
1929 le
= get_tx_le(sky2
, &slot
);
1930 le
->addr
= cpu_to_le32(tcpsum
);
1931 le
->length
= 0; /* initial checksum value */
1932 le
->ctrl
= 1; /* one packet */
1933 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1938 re
= sky2
->tx_ring
+ slot
;
1939 re
->flags
= TX_MAP_SINGLE
;
1940 dma_unmap_addr_set(re
, mapaddr
, mapping
);
1941 dma_unmap_len_set(re
, maplen
, len
);
1943 le
= get_tx_le(sky2
, &slot
);
1944 le
->addr
= cpu_to_le32(lower_32_bits(mapping
));
1945 le
->length
= cpu_to_le16(len
);
1947 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1950 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1951 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1953 mapping
= skb_frag_dma_map(&hw
->pdev
->dev
, frag
, 0,
1954 skb_frag_size(frag
), DMA_TO_DEVICE
);
1956 if (dma_mapping_error(&hw
->pdev
->dev
, mapping
))
1957 goto mapping_unwind
;
1959 upper
= upper_32_bits(mapping
);
1960 if (upper
!= sky2
->tx_last_upper
) {
1961 le
= get_tx_le(sky2
, &slot
);
1962 le
->addr
= cpu_to_le32(upper
);
1963 sky2
->tx_last_upper
= upper
;
1964 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1967 re
= sky2
->tx_ring
+ slot
;
1968 re
->flags
= TX_MAP_PAGE
;
1969 dma_unmap_addr_set(re
, mapaddr
, mapping
);
1970 dma_unmap_len_set(re
, maplen
, skb_frag_size(frag
));
1972 le
= get_tx_le(sky2
, &slot
);
1973 le
->addr
= cpu_to_le32(lower_32_bits(mapping
));
1974 le
->length
= cpu_to_le16(skb_frag_size(frag
));
1976 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1982 sky2
->tx_prod
= slot
;
1984 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1985 netif_stop_queue(dev
);
1987 netdev_sent_queue(dev
, skb
->len
);
1988 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1990 return NETDEV_TX_OK
;
1993 for (i
= sky2
->tx_prod
; i
!= slot
; i
= RING_NEXT(i
, sky2
->tx_ring_size
)) {
1994 re
= sky2
->tx_ring
+ i
;
1996 sky2_tx_unmap(hw
->pdev
, re
);
2000 if (net_ratelimit())
2001 dev_warn(&hw
->pdev
->dev
, "%s: tx mapping error\n", dev
->name
);
2003 return NETDEV_TX_OK
;
2007 * Free ring elements from starting at tx_cons until "done"
2010 * 1. The hardware will tell us about partial completion of multi-part
2011 * buffers so make sure not to free skb to early.
2012 * 2. This may run in parallel start_xmit because the it only
2013 * looks at the tail of the queue of FIFO (tx_cons), not
2014 * the head (tx_prod)
2016 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
2018 struct net_device
*dev
= sky2
->netdev
;
2020 unsigned int bytes_compl
= 0, pkts_compl
= 0;
2022 BUG_ON(done
>= sky2
->tx_ring_size
);
2024 for (idx
= sky2
->tx_cons
; idx
!= done
;
2025 idx
= RING_NEXT(idx
, sky2
->tx_ring_size
)) {
2026 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
2027 struct sk_buff
*skb
= re
->skb
;
2029 sky2_tx_unmap(sky2
->hw
->pdev
, re
);
2032 netif_printk(sky2
, tx_done
, KERN_DEBUG
, dev
,
2033 "tx done %u\n", idx
);
2036 bytes_compl
+= skb
->len
;
2039 dev_kfree_skb_any(skb
);
2041 sky2
->tx_next
= RING_NEXT(idx
, sky2
->tx_ring_size
);
2045 sky2
->tx_cons
= idx
;
2048 netdev_completed_queue(dev
, pkts_compl
, bytes_compl
);
2050 u64_stats_update_begin(&sky2
->tx_stats
.syncp
);
2051 sky2
->tx_stats
.packets
+= pkts_compl
;
2052 sky2
->tx_stats
.bytes
+= bytes_compl
;
2053 u64_stats_update_end(&sky2
->tx_stats
.syncp
);
2056 static void sky2_tx_reset(struct sky2_hw
*hw
, unsigned port
)
2058 /* Disable Force Sync bit and Enable Alloc bit */
2059 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
2060 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
2062 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2063 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
2064 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
2066 /* Reset the PCI FIFO of the async Tx queue */
2067 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
2068 BMU_RST_SET
| BMU_FIFO_RST
);
2070 /* Reset the Tx prefetch units */
2071 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
2074 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
2075 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
2077 sky2_read32(hw
, B0_CTST
);
2080 static void sky2_hw_down(struct sky2_port
*sky2
)
2082 struct sky2_hw
*hw
= sky2
->hw
;
2083 unsigned port
= sky2
->port
;
2086 /* Force flow control off */
2087 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2089 /* Stop transmitter */
2090 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
2091 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
2093 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
2094 RB_RST_SET
| RB_DIS_OP_MD
);
2096 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2097 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
2098 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
2100 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
2102 /* Workaround shared GMAC reset */
2103 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 &&
2104 port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
2105 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
2107 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
2109 /* Force any delayed status interrupt and NAPI */
2110 sky2_write32(hw
, STAT_LEV_TIMER_CNT
, 0);
2111 sky2_write32(hw
, STAT_TX_TIMER_CNT
, 0);
2112 sky2_write32(hw
, STAT_ISR_TIMER_CNT
, 0);
2113 sky2_read8(hw
, STAT_ISR_TIMER_CTRL
);
2117 spin_lock_bh(&sky2
->phy_lock
);
2118 sky2_phy_power_down(hw
, port
);
2119 spin_unlock_bh(&sky2
->phy_lock
);
2121 sky2_tx_reset(hw
, port
);
2123 /* Free any pending frames stuck in HW queue */
2124 sky2_tx_complete(sky2
, sky2
->tx_prod
);
2127 /* Network shutdown */
2128 static int sky2_close(struct net_device
*dev
)
2130 struct sky2_port
*sky2
= netdev_priv(dev
);
2131 struct sky2_hw
*hw
= sky2
->hw
;
2133 /* Never really got started! */
2137 netif_info(sky2
, ifdown
, dev
, "disabling interface\n");
2139 if (hw
->ports
== 1) {
2140 sky2_write32(hw
, B0_IMSK
, 0);
2141 sky2_read32(hw
, B0_IMSK
);
2143 napi_disable(&hw
->napi
);
2144 free_irq(hw
->pdev
->irq
, hw
);
2145 hw
->flags
&= ~SKY2_HW_IRQ_SETUP
;
2149 /* Disable port IRQ */
2150 imask
= sky2_read32(hw
, B0_IMSK
);
2151 imask
&= ~portirq_msk
[sky2
->port
];
2152 sky2_write32(hw
, B0_IMSK
, imask
);
2153 sky2_read32(hw
, B0_IMSK
);
2155 synchronize_irq(hw
->pdev
->irq
);
2156 napi_synchronize(&hw
->napi
);
2161 sky2_free_buffers(sky2
);
2166 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
2168 if (hw
->flags
& SKY2_HW_FIBRE_PHY
)
2171 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
2172 if (aux
& PHY_M_PS_SPEED_100
)
2178 switch (aux
& PHY_M_PS_SPEED_MSK
) {
2179 case PHY_M_PS_SPEED_1000
:
2181 case PHY_M_PS_SPEED_100
:
2188 static void sky2_link_up(struct sky2_port
*sky2
)
2190 struct sky2_hw
*hw
= sky2
->hw
;
2191 unsigned port
= sky2
->port
;
2192 static const char *fc_name
[] = {
2201 sky2_enable_rx_tx(sky2
);
2203 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
2205 netif_carrier_on(sky2
->netdev
);
2207 mod_timer(&hw
->watchdog_timer
, jiffies
+ 1);
2209 /* Turn on link LED */
2210 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
2211 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
2213 netif_info(sky2
, link
, sky2
->netdev
,
2214 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2216 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
2217 fc_name
[sky2
->flow_status
]);
2220 static void sky2_link_down(struct sky2_port
*sky2
)
2222 struct sky2_hw
*hw
= sky2
->hw
;
2223 unsigned port
= sky2
->port
;
2226 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
2228 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
2229 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
2230 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
2232 netif_carrier_off(sky2
->netdev
);
2234 /* Turn off link LED */
2235 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
2237 netif_info(sky2
, link
, sky2
->netdev
, "Link is down\n");
2239 sky2_phy_init(hw
, port
);
2242 static enum flow_control
sky2_flow(int rx
, int tx
)
2245 return tx
? FC_BOTH
: FC_RX
;
2247 return tx
? FC_TX
: FC_NONE
;
2250 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
2252 struct sky2_hw
*hw
= sky2
->hw
;
2253 unsigned port
= sky2
->port
;
2256 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
2257 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
2258 if (lpa
& PHY_M_AN_RF
) {
2259 netdev_err(sky2
->netdev
, "remote fault\n");
2263 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
2264 netdev_err(sky2
->netdev
, "speed/duplex mismatch\n");
2268 sky2
->speed
= sky2_phy_speed(hw
, aux
);
2269 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2271 /* Since the pause result bits seem to in different positions on
2272 * different chips. look at registers.
2274 if (hw
->flags
& SKY2_HW_FIBRE_PHY
) {
2275 /* Shift for bits in fiber PHY */
2276 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
2277 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
2279 if (advert
& ADVERTISE_1000XPAUSE
)
2280 advert
|= ADVERTISE_PAUSE_CAP
;
2281 if (advert
& ADVERTISE_1000XPSE_ASYM
)
2282 advert
|= ADVERTISE_PAUSE_ASYM
;
2283 if (lpa
& LPA_1000XPAUSE
)
2284 lpa
|= LPA_PAUSE_CAP
;
2285 if (lpa
& LPA_1000XPAUSE_ASYM
)
2286 lpa
|= LPA_PAUSE_ASYM
;
2289 sky2
->flow_status
= FC_NONE
;
2290 if (advert
& ADVERTISE_PAUSE_CAP
) {
2291 if (lpa
& LPA_PAUSE_CAP
)
2292 sky2
->flow_status
= FC_BOTH
;
2293 else if (advert
& ADVERTISE_PAUSE_ASYM
)
2294 sky2
->flow_status
= FC_RX
;
2295 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
2296 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
2297 sky2
->flow_status
= FC_TX
;
2300 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
&&
2301 !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
2302 sky2
->flow_status
= FC_NONE
;
2304 if (sky2
->flow_status
& FC_TX
)
2305 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
2307 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2312 /* Interrupt from PHY */
2313 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
2315 struct net_device
*dev
= hw
->dev
[port
];
2316 struct sky2_port
*sky2
= netdev_priv(dev
);
2317 u16 istatus
, phystat
;
2319 if (!netif_running(dev
))
2322 spin_lock(&sky2
->phy_lock
);
2323 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
2324 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
2326 netif_info(sky2
, intr
, sky2
->netdev
, "phy interrupt status 0x%x 0x%x\n",
2329 if (istatus
& PHY_M_IS_AN_COMPL
) {
2330 if (sky2_autoneg_done(sky2
, phystat
) == 0 &&
2331 !netif_carrier_ok(dev
))
2336 if (istatus
& PHY_M_IS_LSP_CHANGE
)
2337 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
2339 if (istatus
& PHY_M_IS_DUP_CHANGE
)
2341 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2343 if (istatus
& PHY_M_IS_LST_CHANGE
) {
2344 if (phystat
& PHY_M_PS_LINK_UP
)
2347 sky2_link_down(sky2
);
2350 spin_unlock(&sky2
->phy_lock
);
2353 /* Special quick link interrupt (Yukon-2 Optima only) */
2354 static void sky2_qlink_intr(struct sky2_hw
*hw
)
2356 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[0]);
2361 imask
= sky2_read32(hw
, B0_IMSK
);
2362 imask
&= ~Y2_IS_PHY_QLNK
;
2363 sky2_write32(hw
, B0_IMSK
, imask
);
2365 /* reset PHY Link Detect */
2366 phy
= sky2_pci_read16(hw
, PSM_CONFIG_REG4
);
2367 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2368 sky2_pci_write16(hw
, PSM_CONFIG_REG4
, phy
| 1);
2369 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2374 /* Transmit timeout is only called if we are running, carrier is up
2375 * and tx queue is full (stopped).
2377 static void sky2_tx_timeout(struct net_device
*dev
)
2379 struct sky2_port
*sky2
= netdev_priv(dev
);
2380 struct sky2_hw
*hw
= sky2
->hw
;
2382 netif_err(sky2
, timer
, dev
, "tx timeout\n");
2384 netdev_printk(KERN_DEBUG
, dev
, "transmit ring %u .. %u report=%u done=%u\n",
2385 sky2
->tx_cons
, sky2
->tx_prod
,
2386 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
2387 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
2389 /* can't restart safely under softirq */
2390 schedule_work(&hw
->restart_work
);
2393 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
2395 struct sky2_port
*sky2
= netdev_priv(dev
);
2396 struct sky2_hw
*hw
= sky2
->hw
;
2397 unsigned port
= sky2
->port
;
2402 /* MTU size outside the spec */
2403 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2406 /* MTU > 1500 on yukon FE and FE+ not allowed */
2407 if (new_mtu
> ETH_DATA_LEN
&&
2408 (hw
->chip_id
== CHIP_ID_YUKON_FE
||
2409 hw
->chip_id
== CHIP_ID_YUKON_FE_P
))
2412 if (!netif_running(dev
)) {
2414 netdev_update_features(dev
);
2418 imask
= sky2_read32(hw
, B0_IMSK
);
2419 sky2_write32(hw
, B0_IMSK
, 0);
2421 dev
->trans_start
= jiffies
; /* prevent tx timeout */
2422 napi_disable(&hw
->napi
);
2423 netif_tx_disable(dev
);
2425 synchronize_irq(hw
->pdev
->irq
);
2427 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
))
2428 sky2_set_tx_stfwd(hw
, port
);
2430 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2431 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
2433 sky2_rx_clean(sky2
);
2436 netdev_update_features(dev
);
2438 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) | GM_SMOD_VLAN_ENA
;
2439 if (sky2
->speed
> SPEED_100
)
2440 mode
|= IPG_DATA_VAL(IPG_DATA_DEF_1000
);
2442 mode
|= IPG_DATA_VAL(IPG_DATA_DEF_10_100
);
2444 if (dev
->mtu
> ETH_DATA_LEN
)
2445 mode
|= GM_SMOD_JUMBO_ENA
;
2447 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
2449 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
2451 err
= sky2_alloc_rx_skbs(sky2
);
2453 sky2_rx_start(sky2
);
2455 sky2_rx_clean(sky2
);
2456 sky2_write32(hw
, B0_IMSK
, imask
);
2458 sky2_read32(hw
, B0_Y2_SP_LISR
);
2459 napi_enable(&hw
->napi
);
2464 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
2466 netif_wake_queue(dev
);
2472 static inline bool needs_copy(const struct rx_ring_info
*re
,
2475 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2476 /* Some architectures need the IP header to be aligned */
2477 if (!IS_ALIGNED(re
->data_addr
+ ETH_HLEN
, sizeof(u32
)))
2480 return length
< copybreak
;
2483 /* For small just reuse existing skb for next receive */
2484 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
2485 const struct rx_ring_info
*re
,
2488 struct sk_buff
*skb
;
2490 skb
= netdev_alloc_skb_ip_align(sky2
->netdev
, length
);
2492 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
2493 length
, PCI_DMA_FROMDEVICE
);
2494 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
2495 skb
->ip_summed
= re
->skb
->ip_summed
;
2496 skb
->csum
= re
->skb
->csum
;
2497 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
2498 length
, PCI_DMA_FROMDEVICE
);
2499 re
->skb
->ip_summed
= CHECKSUM_NONE
;
2500 skb_put(skb
, length
);
2505 /* Adjust length of skb with fragments to match received data */
2506 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
2507 unsigned int length
)
2512 /* put header into skb */
2513 size
= min(length
, hdr_space
);
2518 num_frags
= skb_shinfo(skb
)->nr_frags
;
2519 for (i
= 0; i
< num_frags
; i
++) {
2520 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2523 /* don't need this page */
2524 __skb_frag_unref(frag
);
2525 --skb_shinfo(skb
)->nr_frags
;
2527 size
= min(length
, (unsigned) PAGE_SIZE
);
2529 skb_frag_size_set(frag
, size
);
2530 skb
->data_len
+= size
;
2531 skb
->truesize
+= PAGE_SIZE
;
2538 /* Normal packet - take skb from ring element and put in a new one */
2539 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2540 struct rx_ring_info
*re
,
2541 unsigned int length
)
2543 struct sk_buff
*skb
;
2544 struct rx_ring_info nre
;
2545 unsigned hdr_space
= sky2
->rx_data_size
;
2547 nre
.skb
= sky2_rx_alloc(sky2
, GFP_ATOMIC
);
2548 if (unlikely(!nre
.skb
))
2551 if (sky2_rx_map_skb(sky2
->hw
->pdev
, &nre
, hdr_space
))
2555 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2556 prefetch(skb
->data
);
2559 if (skb_shinfo(skb
)->nr_frags
)
2560 skb_put_frags(skb
, hdr_space
, length
);
2562 skb_put(skb
, length
);
2566 dev_kfree_skb(nre
.skb
);
2572 * Receive one packet.
2573 * For larger packets, get new buffer.
2575 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2576 u16 length
, u32 status
)
2578 struct sky2_port
*sky2
= netdev_priv(dev
);
2579 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2580 struct sk_buff
*skb
= NULL
;
2581 u16 count
= (status
& GMR_FS_LEN
) >> 16;
2583 if (status
& GMR_FS_VLAN
)
2584 count
-= VLAN_HLEN
; /* Account for vlan tag */
2586 netif_printk(sky2
, rx_status
, KERN_DEBUG
, dev
,
2587 "rx slot %u status 0x%x len %d\n",
2588 sky2
->rx_next
, status
, length
);
2590 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2591 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2593 /* This chip has hardware problems that generates bogus status.
2594 * So do only marginal checking and expect higher level protocols
2595 * to handle crap frames.
2597 if (sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
2598 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
&&
2602 if (status
& GMR_FS_ANY_ERR
)
2605 if (!(status
& GMR_FS_RX_OK
))
2608 /* if length reported by DMA does not match PHY, packet was truncated */
2609 if (length
!= count
)
2613 if (needs_copy(re
, length
))
2614 skb
= receive_copy(sky2
, re
, length
);
2616 skb
= receive_new(sky2
, re
, length
);
2618 dev
->stats
.rx_dropped
+= (skb
== NULL
);
2621 sky2_rx_submit(sky2
, re
);
2626 ++dev
->stats
.rx_errors
;
2628 if (net_ratelimit())
2629 netif_info(sky2
, rx_err
, dev
,
2630 "rx error, status 0x%x length %d\n", status
, length
);
2635 /* Transmit complete */
2636 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2638 struct sky2_port
*sky2
= netdev_priv(dev
);
2640 if (netif_running(dev
)) {
2641 sky2_tx_complete(sky2
, last
);
2643 /* Wake unless it's detached, and called e.g. from sky2_close() */
2644 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
2645 netif_wake_queue(dev
);
2649 static inline void sky2_skb_rx(const struct sky2_port
*sky2
,
2650 u32 status
, struct sk_buff
*skb
)
2652 if (status
& GMR_FS_VLAN
)
2653 __vlan_hwaccel_put_tag(skb
, be16_to_cpu(sky2
->rx_tag
));
2655 if (skb
->ip_summed
== CHECKSUM_NONE
)
2656 netif_receive_skb(skb
);
2658 napi_gro_receive(&sky2
->hw
->napi
, skb
);
2661 static inline void sky2_rx_done(struct sky2_hw
*hw
, unsigned port
,
2662 unsigned packets
, unsigned bytes
)
2664 struct net_device
*dev
= hw
->dev
[port
];
2665 struct sky2_port
*sky2
= netdev_priv(dev
);
2670 u64_stats_update_begin(&sky2
->rx_stats
.syncp
);
2671 sky2
->rx_stats
.packets
+= packets
;
2672 sky2
->rx_stats
.bytes
+= bytes
;
2673 u64_stats_update_end(&sky2
->rx_stats
.syncp
);
2675 dev
->last_rx
= jiffies
;
2676 sky2_rx_update(netdev_priv(dev
), rxqaddr
[port
]);
2679 static void sky2_rx_checksum(struct sky2_port
*sky2
, u32 status
)
2681 /* If this happens then driver assuming wrong format for chip type */
2682 BUG_ON(sky2
->hw
->flags
& SKY2_HW_NEW_LE
);
2684 /* Both checksum counters are programmed to start at
2685 * the same offset, so unless there is a problem they
2686 * should match. This failure is an early indication that
2687 * hardware receive checksumming won't work.
2689 if (likely((u16
)(status
>> 16) == (u16
)status
)) {
2690 struct sk_buff
*skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2691 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2692 skb
->csum
= le16_to_cpu(status
);
2694 dev_notice(&sky2
->hw
->pdev
->dev
,
2695 "%s: receive checksum problem (status = %#x)\n",
2696 sky2
->netdev
->name
, status
);
2698 /* Disable checksum offload
2699 * It will be reenabled on next ndo_set_features, but if it's
2700 * really broken, will get disabled again
2702 sky2
->netdev
->features
&= ~NETIF_F_RXCSUM
;
2703 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2708 static void sky2_rx_hash(struct sky2_port
*sky2
, u32 status
)
2710 struct sk_buff
*skb
;
2712 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2713 skb
->rxhash
= le32_to_cpu(status
);
2716 /* Process status response ring */
2717 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
, u16 idx
)
2720 unsigned int total_bytes
[2] = { 0 };
2721 unsigned int total_packets
[2] = { 0 };
2725 struct sky2_port
*sky2
;
2726 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2728 struct net_device
*dev
;
2729 struct sk_buff
*skb
;
2732 u8 opcode
= le
->opcode
;
2734 if (!(opcode
& HW_OWNER
))
2737 hw
->st_idx
= RING_NEXT(hw
->st_idx
, hw
->st_size
);
2739 port
= le
->css
& CSS_LINK_BIT
;
2740 dev
= hw
->dev
[port
];
2741 sky2
= netdev_priv(dev
);
2742 length
= le16_to_cpu(le
->length
);
2743 status
= le32_to_cpu(le
->status
);
2746 switch (opcode
& ~HW_OWNER
) {
2748 total_packets
[port
]++;
2749 total_bytes
[port
] += length
;
2751 skb
= sky2_receive(dev
, length
, status
);
2755 /* This chip reports checksum status differently */
2756 if (hw
->flags
& SKY2_HW_NEW_LE
) {
2757 if ((dev
->features
& NETIF_F_RXCSUM
) &&
2758 (le
->css
& (CSS_ISIPV4
| CSS_ISIPV6
)) &&
2759 (le
->css
& CSS_TCPUDPCSOK
))
2760 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2762 skb
->ip_summed
= CHECKSUM_NONE
;
2765 skb
->protocol
= eth_type_trans(skb
, dev
);
2767 sky2_skb_rx(sky2
, status
, skb
);
2769 /* Stop after net poll weight */
2770 if (++work_done
>= to_do
)
2775 sky2
->rx_tag
= length
;
2779 sky2
->rx_tag
= length
;
2782 if (likely(dev
->features
& NETIF_F_RXCSUM
))
2783 sky2_rx_checksum(sky2
, status
);
2787 sky2_rx_hash(sky2
, status
);
2791 /* TX index reports status for both ports */
2792 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2794 sky2_tx_done(hw
->dev
[1],
2795 ((status
>> 24) & 0xff)
2796 | (u16
)(length
& 0xf) << 8);
2800 if (net_ratelimit())
2801 pr_warning("unknown status opcode 0x%x\n", opcode
);
2803 } while (hw
->st_idx
!= idx
);
2805 /* Fully processed status ring so clear irq */
2806 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2809 sky2_rx_done(hw
, 0, total_packets
[0], total_bytes
[0]);
2810 sky2_rx_done(hw
, 1, total_packets
[1], total_bytes
[1]);
2815 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2817 struct net_device
*dev
= hw
->dev
[port
];
2819 if (net_ratelimit())
2820 netdev_info(dev
, "hw error interrupt status 0x%x\n", status
);
2822 if (status
& Y2_IS_PAR_RD1
) {
2823 if (net_ratelimit())
2824 netdev_err(dev
, "ram data read parity error\n");
2826 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2829 if (status
& Y2_IS_PAR_WR1
) {
2830 if (net_ratelimit())
2831 netdev_err(dev
, "ram data write parity error\n");
2833 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2836 if (status
& Y2_IS_PAR_MAC1
) {
2837 if (net_ratelimit())
2838 netdev_err(dev
, "MAC parity error\n");
2839 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2842 if (status
& Y2_IS_PAR_RX1
) {
2843 if (net_ratelimit())
2844 netdev_err(dev
, "RX parity error\n");
2845 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2848 if (status
& Y2_IS_TCP_TXA1
) {
2849 if (net_ratelimit())
2850 netdev_err(dev
, "TCP segmentation error\n");
2851 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2855 static void sky2_hw_intr(struct sky2_hw
*hw
)
2857 struct pci_dev
*pdev
= hw
->pdev
;
2858 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2859 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2863 if (status
& Y2_IS_TIST_OV
)
2864 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2866 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2869 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2870 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2871 if (net_ratelimit())
2872 dev_err(&pdev
->dev
, "PCI hardware error (0x%x)\n",
2875 sky2_pci_write16(hw
, PCI_STATUS
,
2876 pci_err
| PCI_STATUS_ERROR_BITS
);
2877 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2880 if (status
& Y2_IS_PCI_EXP
) {
2881 /* PCI-Express uncorrectable Error occurred */
2884 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2885 err
= sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2886 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
2888 if (net_ratelimit())
2889 dev_err(&pdev
->dev
, "PCI Express error (0x%x)\n", err
);
2891 sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2892 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2895 if (status
& Y2_HWE_L1_MASK
)
2896 sky2_hw_error(hw
, 0, status
);
2898 if (status
& Y2_HWE_L1_MASK
)
2899 sky2_hw_error(hw
, 1, status
);
2902 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2904 struct net_device
*dev
= hw
->dev
[port
];
2905 struct sky2_port
*sky2
= netdev_priv(dev
);
2906 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2908 netif_info(sky2
, intr
, dev
, "mac interrupt status 0x%x\n", status
);
2910 if (status
& GM_IS_RX_CO_OV
)
2911 gma_read16(hw
, port
, GM_RX_IRQ_SRC
);
2913 if (status
& GM_IS_TX_CO_OV
)
2914 gma_read16(hw
, port
, GM_TX_IRQ_SRC
);
2916 if (status
& GM_IS_RX_FF_OR
) {
2917 ++dev
->stats
.rx_fifo_errors
;
2918 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2921 if (status
& GM_IS_TX_FF_UR
) {
2922 ++dev
->stats
.tx_fifo_errors
;
2923 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2927 /* This should never happen it is a bug. */
2928 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
, u16 q
)
2930 struct net_device
*dev
= hw
->dev
[port
];
2931 u16 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2933 dev_err(&hw
->pdev
->dev
, "%s: descriptor error q=%#x get=%u put=%u\n",
2934 dev
->name
, (unsigned) q
, (unsigned) idx
,
2935 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2937 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2940 static int sky2_rx_hung(struct net_device
*dev
)
2942 struct sky2_port
*sky2
= netdev_priv(dev
);
2943 struct sky2_hw
*hw
= sky2
->hw
;
2944 unsigned port
= sky2
->port
;
2945 unsigned rxq
= rxqaddr
[port
];
2946 u32 mac_rp
= sky2_read32(hw
, SK_REG(port
, RX_GMF_RP
));
2947 u8 mac_lev
= sky2_read8(hw
, SK_REG(port
, RX_GMF_RLEV
));
2948 u8 fifo_rp
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RP
));
2949 u8 fifo_lev
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RL
));
2951 /* If idle and MAC or PCI is stuck */
2952 if (sky2
->check
.last
== dev
->last_rx
&&
2953 ((mac_rp
== sky2
->check
.mac_rp
&&
2954 mac_lev
!= 0 && mac_lev
>= sky2
->check
.mac_lev
) ||
2955 /* Check if the PCI RX hang */
2956 (fifo_rp
== sky2
->check
.fifo_rp
&&
2957 fifo_lev
!= 0 && fifo_lev
>= sky2
->check
.fifo_lev
))) {
2958 netdev_printk(KERN_DEBUG
, dev
,
2959 "hung mac %d:%d fifo %d (%d:%d)\n",
2960 mac_lev
, mac_rp
, fifo_lev
,
2961 fifo_rp
, sky2_read8(hw
, Q_ADDR(rxq
, Q_WP
)));
2964 sky2
->check
.last
= dev
->last_rx
;
2965 sky2
->check
.mac_rp
= mac_rp
;
2966 sky2
->check
.mac_lev
= mac_lev
;
2967 sky2
->check
.fifo_rp
= fifo_rp
;
2968 sky2
->check
.fifo_lev
= fifo_lev
;
2973 static void sky2_watchdog(unsigned long arg
)
2975 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2977 /* Check for lost IRQ once a second */
2978 if (sky2_read32(hw
, B0_ISRC
)) {
2979 napi_schedule(&hw
->napi
);
2983 for (i
= 0; i
< hw
->ports
; i
++) {
2984 struct net_device
*dev
= hw
->dev
[i
];
2985 if (!netif_running(dev
))
2989 /* For chips with Rx FIFO, check if stuck */
2990 if ((hw
->flags
& SKY2_HW_RAM_BUFFER
) &&
2991 sky2_rx_hung(dev
)) {
2992 netdev_info(dev
, "receiver hang detected\n");
2993 schedule_work(&hw
->restart_work
);
3002 mod_timer(&hw
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
3005 /* Hardware/software error handling */
3006 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
3008 if (net_ratelimit())
3009 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
3011 if (status
& Y2_IS_HW_ERR
)
3014 if (status
& Y2_IS_IRQ_MAC1
)
3015 sky2_mac_intr(hw
, 0);
3017 if (status
& Y2_IS_IRQ_MAC2
)
3018 sky2_mac_intr(hw
, 1);
3020 if (status
& Y2_IS_CHK_RX1
)
3021 sky2_le_error(hw
, 0, Q_R1
);
3023 if (status
& Y2_IS_CHK_RX2
)
3024 sky2_le_error(hw
, 1, Q_R2
);
3026 if (status
& Y2_IS_CHK_TXA1
)
3027 sky2_le_error(hw
, 0, Q_XA1
);
3029 if (status
& Y2_IS_CHK_TXA2
)
3030 sky2_le_error(hw
, 1, Q_XA2
);
3033 static int sky2_poll(struct napi_struct
*napi
, int work_limit
)
3035 struct sky2_hw
*hw
= container_of(napi
, struct sky2_hw
, napi
);
3036 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
3040 if (unlikely(status
& Y2_IS_ERROR
))
3041 sky2_err_intr(hw
, status
);
3043 if (status
& Y2_IS_IRQ_PHY1
)
3044 sky2_phy_intr(hw
, 0);
3046 if (status
& Y2_IS_IRQ_PHY2
)
3047 sky2_phy_intr(hw
, 1);
3049 if (status
& Y2_IS_PHY_QLNK
)
3050 sky2_qlink_intr(hw
);
3052 while ((idx
= sky2_read16(hw
, STAT_PUT_IDX
)) != hw
->st_idx
) {
3053 work_done
+= sky2_status_intr(hw
, work_limit
- work_done
, idx
);
3055 if (work_done
>= work_limit
)
3059 napi_complete(napi
);
3060 sky2_read32(hw
, B0_Y2_SP_LISR
);
3066 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
3068 struct sky2_hw
*hw
= dev_id
;
3071 /* Reading this mask interrupts as side effect */
3072 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3073 if (status
== 0 || status
== ~0)
3076 prefetch(&hw
->st_le
[hw
->st_idx
]);
3078 napi_schedule(&hw
->napi
);
3083 #ifdef CONFIG_NET_POLL_CONTROLLER
3084 static void sky2_netpoll(struct net_device
*dev
)
3086 struct sky2_port
*sky2
= netdev_priv(dev
);
3088 napi_schedule(&sky2
->hw
->napi
);
3092 /* Chip internal frequency for clock calculations */
3093 static u32
sky2_mhz(const struct sky2_hw
*hw
)
3095 switch (hw
->chip_id
) {
3096 case CHIP_ID_YUKON_EC
:
3097 case CHIP_ID_YUKON_EC_U
:
3098 case CHIP_ID_YUKON_EX
:
3099 case CHIP_ID_YUKON_SUPR
:
3100 case CHIP_ID_YUKON_UL_2
:
3101 case CHIP_ID_YUKON_OPT
:
3102 case CHIP_ID_YUKON_PRM
:
3103 case CHIP_ID_YUKON_OP_2
:
3106 case CHIP_ID_YUKON_FE
:
3109 case CHIP_ID_YUKON_FE_P
:
3112 case CHIP_ID_YUKON_XL
:
3120 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
3122 return sky2_mhz(hw
) * us
;
3125 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
3127 return clk
/ sky2_mhz(hw
);
3131 static int __devinit
sky2_init(struct sky2_hw
*hw
)
3135 /* Enable all clocks and check for bad PCI access */
3136 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
3138 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
3140 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
3141 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
3143 switch (hw
->chip_id
) {
3144 case CHIP_ID_YUKON_XL
:
3145 hw
->flags
= SKY2_HW_GIGABIT
| SKY2_HW_NEWER_PHY
;
3146 if (hw
->chip_rev
< CHIP_REV_YU_XL_A2
)
3147 hw
->flags
|= SKY2_HW_RSS_BROKEN
;
3150 case CHIP_ID_YUKON_EC_U
:
3151 hw
->flags
= SKY2_HW_GIGABIT
3153 | SKY2_HW_ADV_POWER_CTL
;
3156 case CHIP_ID_YUKON_EX
:
3157 hw
->flags
= SKY2_HW_GIGABIT
3160 | SKY2_HW_ADV_POWER_CTL
3161 | SKY2_HW_RSS_CHKSUM
;
3163 /* New transmit checksum */
3164 if (hw
->chip_rev
!= CHIP_REV_YU_EX_B0
)
3165 hw
->flags
|= SKY2_HW_AUTO_TX_SUM
;
3168 case CHIP_ID_YUKON_EC
:
3169 /* This rev is really old, and requires untested workarounds */
3170 if (hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
3171 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-EC rev A1\n");
3174 hw
->flags
= SKY2_HW_GIGABIT
| SKY2_HW_RSS_BROKEN
;
3177 case CHIP_ID_YUKON_FE
:
3178 hw
->flags
= SKY2_HW_RSS_BROKEN
;
3181 case CHIP_ID_YUKON_FE_P
:
3182 hw
->flags
= SKY2_HW_NEWER_PHY
3184 | SKY2_HW_AUTO_TX_SUM
3185 | SKY2_HW_ADV_POWER_CTL
;
3187 /* The workaround for status conflicts VLAN tag detection. */
3188 if (hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
3189 hw
->flags
|= SKY2_HW_VLAN_BROKEN
| SKY2_HW_RSS_CHKSUM
;
3192 case CHIP_ID_YUKON_SUPR
:
3193 hw
->flags
= SKY2_HW_GIGABIT
3196 | SKY2_HW_AUTO_TX_SUM
3197 | SKY2_HW_ADV_POWER_CTL
;
3199 if (hw
->chip_rev
== CHIP_REV_YU_SU_A0
)
3200 hw
->flags
|= SKY2_HW_RSS_CHKSUM
;
3203 case CHIP_ID_YUKON_UL_2
:
3204 hw
->flags
= SKY2_HW_GIGABIT
3205 | SKY2_HW_ADV_POWER_CTL
;
3208 case CHIP_ID_YUKON_OPT
:
3209 case CHIP_ID_YUKON_PRM
:
3210 case CHIP_ID_YUKON_OP_2
:
3211 hw
->flags
= SKY2_HW_GIGABIT
3213 | SKY2_HW_ADV_POWER_CTL
;
3217 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
3222 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
3223 if (hw
->pmd_type
== 'L' || hw
->pmd_type
== 'S' || hw
->pmd_type
== 'P')
3224 hw
->flags
|= SKY2_HW_FIBRE_PHY
;
3227 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
3228 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
3229 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
3233 if (sky2_read8(hw
, B2_E_0
))
3234 hw
->flags
|= SKY2_HW_RAM_BUFFER
;
3239 static void sky2_reset(struct sky2_hw
*hw
)
3241 struct pci_dev
*pdev
= hw
->pdev
;
3244 u32 hwe_mask
= Y2_HWE_ALL_MASK
;
3247 if (hw
->chip_id
== CHIP_ID_YUKON_EX
3248 || hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
3249 sky2_write32(hw
, CPU_WDOG
, 0);
3250 status
= sky2_read16(hw
, HCU_CCSR
);
3251 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
3252 HCU_CCSR_UC_STATE_MSK
);
3254 * CPU clock divider shouldn't be used because
3255 * - ASF firmware may malfunction
3256 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3258 status
&= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK
;
3259 sky2_write16(hw
, HCU_CCSR
, status
);
3260 sky2_write32(hw
, CPU_WDOG
, 0);
3262 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
3263 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
3266 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3267 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
3269 /* allow writes to PCI config */
3270 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3272 /* clear PCI errors, if any */
3273 status
= sky2_pci_read16(hw
, PCI_STATUS
);
3274 status
|= PCI_STATUS_ERROR_BITS
;
3275 sky2_pci_write16(hw
, PCI_STATUS
, status
);
3277 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
3279 if (pci_is_pcie(pdev
)) {
3280 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
3283 /* If error bit is stuck on ignore it */
3284 if (sky2_read32(hw
, B0_HWE_ISRC
) & Y2_IS_PCI_EXP
)
3285 dev_info(&pdev
->dev
, "ignoring stuck error report bit\n");
3287 hwe_mask
|= Y2_IS_PCI_EXP
;
3291 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3293 for (i
= 0; i
< hw
->ports
; i
++) {
3294 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
3295 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
3297 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
3298 hw
->chip_id
== CHIP_ID_YUKON_SUPR
)
3299 sky2_write16(hw
, SK_REG(i
, GMAC_CTRL
),
3300 GMC_BYP_MACSECRX_ON
| GMC_BYP_MACSECTX_ON
3305 if (hw
->chip_id
== CHIP_ID_YUKON_SUPR
&& hw
->chip_rev
> CHIP_REV_YU_SU_B0
) {
3306 /* enable MACSec clock gating */
3307 sky2_pci_write32(hw
, PCI_DEV_REG3
, P_CLK_MACSEC_DIS
);
3310 if (hw
->chip_id
== CHIP_ID_YUKON_OPT
||
3311 hw
->chip_id
== CHIP_ID_YUKON_PRM
||
3312 hw
->chip_id
== CHIP_ID_YUKON_OP_2
) {
3315 if (hw
->chip_id
== CHIP_ID_YUKON_OPT
&& hw
->chip_rev
== 0) {
3316 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3317 sky2_write32(hw
, Y2_PEX_PHY_DATA
, (0x80UL
<< 16) | (1 << 7));
3319 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3322 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3323 sky2_write32(hw
, Y2_PEX_PHY_DATA
, PEX_DB_ACCESS
| (0x08UL
<< 16));
3325 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3329 reg
<<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE
;
3330 reg
|= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT
;
3332 /* reset PHY Link Detect */
3333 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3334 sky2_pci_write16(hw
, PSM_CONFIG_REG4
, reg
);
3336 /* check if PSMv2 was running before */
3337 reg
= sky2_pci_read16(hw
, PSM_CONFIG_REG3
);
3338 if (reg
& PCI_EXP_LNKCTL_ASPMC
)
3339 /* restore the PCIe Link Control register */
3340 sky2_pci_write16(hw
, pdev
->pcie_cap
+ PCI_EXP_LNKCTL
,
3343 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3345 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3346 sky2_write32(hw
, Y2_PEX_PHY_DATA
, PEX_DB_ACCESS
| (0x08UL
<< 16));
3349 /* Clear I2C IRQ noise */
3350 sky2_write32(hw
, B2_I2C_IRQ
, 1);
3352 /* turn off hardware timer (unused) */
3353 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
3354 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
3356 /* Turn off descriptor polling */
3357 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
3359 /* Turn off receive timestamp */
3360 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
3361 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
3363 /* enable the Tx Arbiters */
3364 for (i
= 0; i
< hw
->ports
; i
++)
3365 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
3367 /* Initialize ram interface */
3368 for (i
= 0; i
< hw
->ports
; i
++) {
3369 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
3371 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
3372 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
3373 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
3374 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
3375 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
3376 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
3377 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
3378 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
3379 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
3380 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
3381 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
3382 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
3385 sky2_write32(hw
, B0_HWE_IMSK
, hwe_mask
);
3387 for (i
= 0; i
< hw
->ports
; i
++)
3388 sky2_gmac_reset(hw
, i
);
3390 memset(hw
->st_le
, 0, hw
->st_size
* sizeof(struct sky2_status_le
));
3393 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
3394 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
3396 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
3397 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
3399 /* Set the list last index */
3400 sky2_write16(hw
, STAT_LAST_IDX
, hw
->st_size
- 1);
3402 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
3403 sky2_write8(hw
, STAT_FIFO_WM
, 16);
3405 /* set Status-FIFO ISR watermark */
3406 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
3407 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
3409 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
3411 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
3412 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
3413 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
3415 /* enable status unit */
3416 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
3418 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3419 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3420 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3423 /* Take device down (offline).
3424 * Equivalent to doing dev_stop() but this does not
3425 * inform upper layers of the transition.
3427 static void sky2_detach(struct net_device
*dev
)
3429 if (netif_running(dev
)) {
3431 netif_device_detach(dev
); /* stop txq */
3432 netif_tx_unlock(dev
);
3437 /* Bring device back after doing sky2_detach */
3438 static int sky2_reattach(struct net_device
*dev
)
3442 if (netif_running(dev
)) {
3443 err
= sky2_open(dev
);
3445 netdev_info(dev
, "could not restart %d\n", err
);
3448 netif_device_attach(dev
);
3449 sky2_set_multicast(dev
);
3456 static void sky2_all_down(struct sky2_hw
*hw
)
3460 if (hw
->flags
& SKY2_HW_IRQ_SETUP
) {
3461 sky2_read32(hw
, B0_IMSK
);
3462 sky2_write32(hw
, B0_IMSK
, 0);
3464 synchronize_irq(hw
->pdev
->irq
);
3465 napi_disable(&hw
->napi
);
3468 for (i
= 0; i
< hw
->ports
; i
++) {
3469 struct net_device
*dev
= hw
->dev
[i
];
3470 struct sky2_port
*sky2
= netdev_priv(dev
);
3472 if (!netif_running(dev
))
3475 netif_carrier_off(dev
);
3476 netif_tx_disable(dev
);
3481 static void sky2_all_up(struct sky2_hw
*hw
)
3483 u32 imask
= Y2_IS_BASE
;
3486 for (i
= 0; i
< hw
->ports
; i
++) {
3487 struct net_device
*dev
= hw
->dev
[i
];
3488 struct sky2_port
*sky2
= netdev_priv(dev
);
3490 if (!netif_running(dev
))
3494 sky2_set_multicast(dev
);
3495 imask
|= portirq_msk
[i
];
3496 netif_wake_queue(dev
);
3499 if (hw
->flags
& SKY2_HW_IRQ_SETUP
) {
3500 sky2_write32(hw
, B0_IMSK
, imask
);
3501 sky2_read32(hw
, B0_IMSK
);
3502 sky2_read32(hw
, B0_Y2_SP_LISR
);
3503 napi_enable(&hw
->napi
);
3507 static void sky2_restart(struct work_struct
*work
)
3509 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
3520 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
3522 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
3525 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3527 const struct sky2_port
*sky2
= netdev_priv(dev
);
3529 wol
->supported
= sky2_wol_supported(sky2
->hw
);
3530 wol
->wolopts
= sky2
->wol
;
3533 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3535 struct sky2_port
*sky2
= netdev_priv(dev
);
3536 struct sky2_hw
*hw
= sky2
->hw
;
3537 bool enable_wakeup
= false;
3540 if ((wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
)) ||
3541 !device_can_wakeup(&hw
->pdev
->dev
))
3544 sky2
->wol
= wol
->wolopts
;
3546 for (i
= 0; i
< hw
->ports
; i
++) {
3547 struct net_device
*dev
= hw
->dev
[i
];
3548 struct sky2_port
*sky2
= netdev_priv(dev
);
3551 enable_wakeup
= true;
3553 device_set_wakeup_enable(&hw
->pdev
->dev
, enable_wakeup
);
3558 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
3560 if (sky2_is_copper(hw
)) {
3561 u32 modes
= SUPPORTED_10baseT_Half
3562 | SUPPORTED_10baseT_Full
3563 | SUPPORTED_100baseT_Half
3564 | SUPPORTED_100baseT_Full
;
3566 if (hw
->flags
& SKY2_HW_GIGABIT
)
3567 modes
|= SUPPORTED_1000baseT_Half
3568 | SUPPORTED_1000baseT_Full
;
3571 return SUPPORTED_1000baseT_Half
3572 | SUPPORTED_1000baseT_Full
;
3575 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3577 struct sky2_port
*sky2
= netdev_priv(dev
);
3578 struct sky2_hw
*hw
= sky2
->hw
;
3580 ecmd
->transceiver
= XCVR_INTERNAL
;
3581 ecmd
->supported
= sky2_supported_modes(hw
);
3582 ecmd
->phy_address
= PHY_ADDR_MARV
;
3583 if (sky2_is_copper(hw
)) {
3584 ecmd
->port
= PORT_TP
;
3585 ethtool_cmd_speed_set(ecmd
, sky2
->speed
);
3586 ecmd
->supported
|= SUPPORTED_Autoneg
| SUPPORTED_TP
;
3588 ethtool_cmd_speed_set(ecmd
, SPEED_1000
);
3589 ecmd
->port
= PORT_FIBRE
;
3590 ecmd
->supported
|= SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
3593 ecmd
->advertising
= sky2
->advertising
;
3594 ecmd
->autoneg
= (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
3595 ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
3596 ecmd
->duplex
= sky2
->duplex
;
3600 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3602 struct sky2_port
*sky2
= netdev_priv(dev
);
3603 const struct sky2_hw
*hw
= sky2
->hw
;
3604 u32 supported
= sky2_supported_modes(hw
);
3606 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
3607 if (ecmd
->advertising
& ~supported
)
3610 if (sky2_is_copper(hw
))
3611 sky2
->advertising
= ecmd
->advertising
|
3615 sky2
->advertising
= ecmd
->advertising
|
3619 sky2
->flags
|= SKY2_FLAG_AUTO_SPEED
;
3624 u32 speed
= ethtool_cmd_speed(ecmd
);
3628 if (ecmd
->duplex
== DUPLEX_FULL
)
3629 setting
= SUPPORTED_1000baseT_Full
;
3630 else if (ecmd
->duplex
== DUPLEX_HALF
)
3631 setting
= SUPPORTED_1000baseT_Half
;
3636 if (ecmd
->duplex
== DUPLEX_FULL
)
3637 setting
= SUPPORTED_100baseT_Full
;
3638 else if (ecmd
->duplex
== DUPLEX_HALF
)
3639 setting
= SUPPORTED_100baseT_Half
;
3645 if (ecmd
->duplex
== DUPLEX_FULL
)
3646 setting
= SUPPORTED_10baseT_Full
;
3647 else if (ecmd
->duplex
== DUPLEX_HALF
)
3648 setting
= SUPPORTED_10baseT_Half
;
3656 if ((setting
& supported
) == 0)
3659 sky2
->speed
= speed
;
3660 sky2
->duplex
= ecmd
->duplex
;
3661 sky2
->flags
&= ~SKY2_FLAG_AUTO_SPEED
;
3664 if (netif_running(dev
)) {
3665 sky2_phy_reinit(sky2
);
3666 sky2_set_multicast(dev
);
3672 static void sky2_get_drvinfo(struct net_device
*dev
,
3673 struct ethtool_drvinfo
*info
)
3675 struct sky2_port
*sky2
= netdev_priv(dev
);
3677 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
3678 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
3679 strlcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
),
3680 sizeof(info
->bus_info
));
3683 static const struct sky2_stat
{
3684 char name
[ETH_GSTRING_LEN
];
3687 { "tx_bytes", GM_TXO_OK_HI
},
3688 { "rx_bytes", GM_RXO_OK_HI
},
3689 { "tx_broadcast", GM_TXF_BC_OK
},
3690 { "rx_broadcast", GM_RXF_BC_OK
},
3691 { "tx_multicast", GM_TXF_MC_OK
},
3692 { "rx_multicast", GM_RXF_MC_OK
},
3693 { "tx_unicast", GM_TXF_UC_OK
},
3694 { "rx_unicast", GM_RXF_UC_OK
},
3695 { "tx_mac_pause", GM_TXF_MPAUSE
},
3696 { "rx_mac_pause", GM_RXF_MPAUSE
},
3697 { "collisions", GM_TXF_COL
},
3698 { "late_collision",GM_TXF_LAT_COL
},
3699 { "aborted", GM_TXF_ABO_COL
},
3700 { "single_collisions", GM_TXF_SNG_COL
},
3701 { "multi_collisions", GM_TXF_MUL_COL
},
3703 { "rx_short", GM_RXF_SHT
},
3704 { "rx_runt", GM_RXE_FRAG
},
3705 { "rx_64_byte_packets", GM_RXF_64B
},
3706 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
3707 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
3708 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
3709 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
3710 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
3711 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
3712 { "rx_too_long", GM_RXF_LNG_ERR
},
3713 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
3714 { "rx_jabber", GM_RXF_JAB_PKT
},
3715 { "rx_fcs_error", GM_RXF_FCS_ERR
},
3717 { "tx_64_byte_packets", GM_TXF_64B
},
3718 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
3719 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
3720 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
3721 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
3722 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
3723 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
3724 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
3727 static u32
sky2_get_msglevel(struct net_device
*netdev
)
3729 struct sky2_port
*sky2
= netdev_priv(netdev
);
3730 return sky2
->msg_enable
;
3733 static int sky2_nway_reset(struct net_device
*dev
)
3735 struct sky2_port
*sky2
= netdev_priv(dev
);
3737 if (!netif_running(dev
) || !(sky2
->flags
& SKY2_FLAG_AUTO_SPEED
))
3740 sky2_phy_reinit(sky2
);
3741 sky2_set_multicast(dev
);
3746 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
3748 struct sky2_hw
*hw
= sky2
->hw
;
3749 unsigned port
= sky2
->port
;
3752 data
[0] = get_stats64(hw
, port
, GM_TXO_OK_LO
);
3753 data
[1] = get_stats64(hw
, port
, GM_RXO_OK_LO
);
3755 for (i
= 2; i
< count
; i
++)
3756 data
[i
] = get_stats32(hw
, port
, sky2_stats
[i
].offset
);
3759 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
3761 struct sky2_port
*sky2
= netdev_priv(netdev
);
3762 sky2
->msg_enable
= value
;
3765 static int sky2_get_sset_count(struct net_device
*dev
, int sset
)
3769 return ARRAY_SIZE(sky2_stats
);
3775 static void sky2_get_ethtool_stats(struct net_device
*dev
,
3776 struct ethtool_stats
*stats
, u64
* data
)
3778 struct sky2_port
*sky2
= netdev_priv(dev
);
3780 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
3783 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
3787 switch (stringset
) {
3789 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
3790 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3791 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
3796 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
3798 struct sky2_port
*sky2
= netdev_priv(dev
);
3799 struct sky2_hw
*hw
= sky2
->hw
;
3800 unsigned port
= sky2
->port
;
3801 const struct sockaddr
*addr
= p
;
3803 if (!is_valid_ether_addr(addr
->sa_data
))
3804 return -EADDRNOTAVAIL
;
3806 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3807 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3808 dev
->dev_addr
, ETH_ALEN
);
3809 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3810 dev
->dev_addr
, ETH_ALEN
);
3812 /* virtual address for data */
3813 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3815 /* physical address: used for pause frames */
3816 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3821 static inline void sky2_add_filter(u8 filter
[8], const u8
*addr
)
3825 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3826 filter
[bit
>> 3] |= 1 << (bit
& 7);
3829 static void sky2_set_multicast(struct net_device
*dev
)
3831 struct sky2_port
*sky2
= netdev_priv(dev
);
3832 struct sky2_hw
*hw
= sky2
->hw
;
3833 unsigned port
= sky2
->port
;
3834 struct netdev_hw_addr
*ha
;
3838 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3840 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3841 memset(filter
, 0, sizeof(filter
));
3843 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3844 reg
|= GM_RXCR_UCF_ENA
;
3846 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3847 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3848 else if (dev
->flags
& IFF_ALLMULTI
)
3849 memset(filter
, 0xff, sizeof(filter
));
3850 else if (netdev_mc_empty(dev
) && !rx_pause
)
3851 reg
&= ~GM_RXCR_MCF_ENA
;
3853 reg
|= GM_RXCR_MCF_ENA
;
3856 sky2_add_filter(filter
, pause_mc_addr
);
3858 netdev_for_each_mc_addr(ha
, dev
)
3859 sky2_add_filter(filter
, ha
->addr
);
3862 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3863 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3864 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3865 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3866 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3867 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3868 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3869 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3871 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3874 static struct rtnl_link_stats64
*sky2_get_stats(struct net_device
*dev
,
3875 struct rtnl_link_stats64
*stats
)
3877 struct sky2_port
*sky2
= netdev_priv(dev
);
3878 struct sky2_hw
*hw
= sky2
->hw
;
3879 unsigned port
= sky2
->port
;
3881 u64 _bytes
, _packets
;
3884 start
= u64_stats_fetch_begin_bh(&sky2
->rx_stats
.syncp
);
3885 _bytes
= sky2
->rx_stats
.bytes
;
3886 _packets
= sky2
->rx_stats
.packets
;
3887 } while (u64_stats_fetch_retry_bh(&sky2
->rx_stats
.syncp
, start
));
3889 stats
->rx_packets
= _packets
;
3890 stats
->rx_bytes
= _bytes
;
3893 start
= u64_stats_fetch_begin_bh(&sky2
->tx_stats
.syncp
);
3894 _bytes
= sky2
->tx_stats
.bytes
;
3895 _packets
= sky2
->tx_stats
.packets
;
3896 } while (u64_stats_fetch_retry_bh(&sky2
->tx_stats
.syncp
, start
));
3898 stats
->tx_packets
= _packets
;
3899 stats
->tx_bytes
= _bytes
;
3901 stats
->multicast
= get_stats32(hw
, port
, GM_RXF_MC_OK
)
3902 + get_stats32(hw
, port
, GM_RXF_BC_OK
);
3904 stats
->collisions
= get_stats32(hw
, port
, GM_TXF_COL
);
3906 stats
->rx_length_errors
= get_stats32(hw
, port
, GM_RXF_LNG_ERR
);
3907 stats
->rx_crc_errors
= get_stats32(hw
, port
, GM_RXF_FCS_ERR
);
3908 stats
->rx_frame_errors
= get_stats32(hw
, port
, GM_RXF_SHT
)
3909 + get_stats32(hw
, port
, GM_RXE_FRAG
);
3910 stats
->rx_over_errors
= get_stats32(hw
, port
, GM_RXE_FIFO_OV
);
3912 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
3913 stats
->rx_fifo_errors
= dev
->stats
.rx_fifo_errors
;
3914 stats
->tx_fifo_errors
= dev
->stats
.tx_fifo_errors
;
3919 /* Can have one global because blinking is controlled by
3920 * ethtool and that is always under RTNL mutex
3922 static void sky2_led(struct sky2_port
*sky2
, enum led_mode mode
)
3924 struct sky2_hw
*hw
= sky2
->hw
;
3925 unsigned port
= sky2
->port
;
3927 spin_lock_bh(&sky2
->phy_lock
);
3928 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
3929 hw
->chip_id
== CHIP_ID_YUKON_EX
||
3930 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
3932 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3933 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3937 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3938 PHY_M_LEDC_LOS_CTRL(8) |
3939 PHY_M_LEDC_INIT_CTRL(8) |
3940 PHY_M_LEDC_STA1_CTRL(8) |
3941 PHY_M_LEDC_STA0_CTRL(8));
3944 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3945 PHY_M_LEDC_LOS_CTRL(9) |
3946 PHY_M_LEDC_INIT_CTRL(9) |
3947 PHY_M_LEDC_STA1_CTRL(9) |
3948 PHY_M_LEDC_STA0_CTRL(9));
3951 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3952 PHY_M_LEDC_LOS_CTRL(0xa) |
3953 PHY_M_LEDC_INIT_CTRL(0xa) |
3954 PHY_M_LEDC_STA1_CTRL(0xa) |
3955 PHY_M_LEDC_STA0_CTRL(0xa));
3958 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3959 PHY_M_LEDC_LOS_CTRL(1) |
3960 PHY_M_LEDC_INIT_CTRL(8) |
3961 PHY_M_LEDC_STA1_CTRL(7) |
3962 PHY_M_LEDC_STA0_CTRL(7));
3965 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3967 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3968 PHY_M_LED_MO_DUP(mode
) |
3969 PHY_M_LED_MO_10(mode
) |
3970 PHY_M_LED_MO_100(mode
) |
3971 PHY_M_LED_MO_1000(mode
) |
3972 PHY_M_LED_MO_RX(mode
) |
3973 PHY_M_LED_MO_TX(mode
));
3975 spin_unlock_bh(&sky2
->phy_lock
);
3978 /* blink LED's for finding board */
3979 static int sky2_set_phys_id(struct net_device
*dev
,
3980 enum ethtool_phys_id_state state
)
3982 struct sky2_port
*sky2
= netdev_priv(dev
);
3985 case ETHTOOL_ID_ACTIVE
:
3986 return 1; /* cycle on/off once per second */
3987 case ETHTOOL_ID_INACTIVE
:
3988 sky2_led(sky2
, MO_LED_NORM
);
3991 sky2_led(sky2
, MO_LED_ON
);
3993 case ETHTOOL_ID_OFF
:
3994 sky2_led(sky2
, MO_LED_OFF
);
4001 static void sky2_get_pauseparam(struct net_device
*dev
,
4002 struct ethtool_pauseparam
*ecmd
)
4004 struct sky2_port
*sky2
= netdev_priv(dev
);
4006 switch (sky2
->flow_mode
) {
4008 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
4011 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
4014 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
4017 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
4020 ecmd
->autoneg
= (sky2
->flags
& SKY2_FLAG_AUTO_PAUSE
)
4021 ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
4024 static int sky2_set_pauseparam(struct net_device
*dev
,
4025 struct ethtool_pauseparam
*ecmd
)
4027 struct sky2_port
*sky2
= netdev_priv(dev
);
4029 if (ecmd
->autoneg
== AUTONEG_ENABLE
)
4030 sky2
->flags
|= SKY2_FLAG_AUTO_PAUSE
;
4032 sky2
->flags
&= ~SKY2_FLAG_AUTO_PAUSE
;
4034 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
4036 if (netif_running(dev
))
4037 sky2_phy_reinit(sky2
);
4042 static int sky2_get_coalesce(struct net_device
*dev
,
4043 struct ethtool_coalesce
*ecmd
)
4045 struct sky2_port
*sky2
= netdev_priv(dev
);
4046 struct sky2_hw
*hw
= sky2
->hw
;
4048 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
4049 ecmd
->tx_coalesce_usecs
= 0;
4051 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
4052 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
4054 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
4056 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
4057 ecmd
->rx_coalesce_usecs
= 0;
4059 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
4060 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
4062 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
4064 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
4065 ecmd
->rx_coalesce_usecs_irq
= 0;
4067 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
4068 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
4071 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
4076 /* Note: this affect both ports */
4077 static int sky2_set_coalesce(struct net_device
*dev
,
4078 struct ethtool_coalesce
*ecmd
)
4080 struct sky2_port
*sky2
= netdev_priv(dev
);
4081 struct sky2_hw
*hw
= sky2
->hw
;
4082 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
4084 if (ecmd
->tx_coalesce_usecs
> tmax
||
4085 ecmd
->rx_coalesce_usecs
> tmax
||
4086 ecmd
->rx_coalesce_usecs_irq
> tmax
)
4089 if (ecmd
->tx_max_coalesced_frames
>= sky2
->tx_ring_size
-1)
4091 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
4093 if (ecmd
->rx_max_coalesced_frames_irq
> RX_MAX_PENDING
)
4096 if (ecmd
->tx_coalesce_usecs
== 0)
4097 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
4099 sky2_write32(hw
, STAT_TX_TIMER_INI
,
4100 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
4101 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
4103 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
4105 if (ecmd
->rx_coalesce_usecs
== 0)
4106 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
4108 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
4109 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
4110 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
4112 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
4114 if (ecmd
->rx_coalesce_usecs_irq
== 0)
4115 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
4117 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
4118 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
4119 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
4121 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
4126 * Hardware is limited to min of 128 and max of 2048 for ring size
4127 * and rounded up to next power of two
4128 * to avoid division in modulus calclation
4130 static unsigned long roundup_ring_size(unsigned long pending
)
4132 return max(128ul, roundup_pow_of_two(pending
+1));
4135 static void sky2_get_ringparam(struct net_device
*dev
,
4136 struct ethtool_ringparam
*ering
)
4138 struct sky2_port
*sky2
= netdev_priv(dev
);
4140 ering
->rx_max_pending
= RX_MAX_PENDING
;
4141 ering
->tx_max_pending
= TX_MAX_PENDING
;
4143 ering
->rx_pending
= sky2
->rx_pending
;
4144 ering
->tx_pending
= sky2
->tx_pending
;
4147 static int sky2_set_ringparam(struct net_device
*dev
,
4148 struct ethtool_ringparam
*ering
)
4150 struct sky2_port
*sky2
= netdev_priv(dev
);
4152 if (ering
->rx_pending
> RX_MAX_PENDING
||
4153 ering
->rx_pending
< 8 ||
4154 ering
->tx_pending
< TX_MIN_PENDING
||
4155 ering
->tx_pending
> TX_MAX_PENDING
)
4160 sky2
->rx_pending
= ering
->rx_pending
;
4161 sky2
->tx_pending
= ering
->tx_pending
;
4162 sky2
->tx_ring_size
= roundup_ring_size(sky2
->tx_pending
);
4164 return sky2_reattach(dev
);
4167 static int sky2_get_regs_len(struct net_device
*dev
)
4172 static int sky2_reg_access_ok(struct sky2_hw
*hw
, unsigned int b
)
4174 /* This complicated switch statement is to make sure and
4175 * only access regions that are unreserved.
4176 * Some blocks are only valid on dual port cards.
4180 case 5: /* Tx Arbiter 2 */
4182 case 14 ... 15: /* TX2 */
4183 case 17: case 19: /* Ram Buffer 2 */
4184 case 22 ... 23: /* Tx Ram Buffer 2 */
4185 case 25: /* Rx MAC Fifo 1 */
4186 case 27: /* Tx MAC Fifo 2 */
4187 case 31: /* GPHY 2 */
4188 case 40 ... 47: /* Pattern Ram 2 */
4189 case 52: case 54: /* TCP Segmentation 2 */
4190 case 112 ... 116: /* GMAC 2 */
4191 return hw
->ports
> 1;
4193 case 0: /* Control */
4194 case 2: /* Mac address */
4195 case 4: /* Tx Arbiter 1 */
4196 case 7: /* PCI express reg */
4198 case 12 ... 13: /* TX1 */
4199 case 16: case 18:/* Rx Ram Buffer 1 */
4200 case 20 ... 21: /* Tx Ram Buffer 1 */
4201 case 24: /* Rx MAC Fifo 1 */
4202 case 26: /* Tx MAC Fifo 1 */
4203 case 28 ... 29: /* Descriptor and status unit */
4204 case 30: /* GPHY 1*/
4205 case 32 ... 39: /* Pattern Ram 1 */
4206 case 48: case 50: /* TCP Segmentation 1 */
4207 case 56 ... 60: /* PCI space */
4208 case 80 ... 84: /* GMAC 1 */
4217 * Returns copy of control register region
4218 * Note: ethtool_get_regs always provides full size (16k) buffer
4220 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
4223 const struct sky2_port
*sky2
= netdev_priv(dev
);
4224 const void __iomem
*io
= sky2
->hw
->regs
;
4229 for (b
= 0; b
< 128; b
++) {
4230 /* skip poisonous diagnostic ram region in block 3 */
4232 memcpy_fromio(p
+ 0x10, io
+ 0x10, 128 - 0x10);
4233 else if (sky2_reg_access_ok(sky2
->hw
, b
))
4234 memcpy_fromio(p
, io
, 128);
4243 static int sky2_get_eeprom_len(struct net_device
*dev
)
4245 struct sky2_port
*sky2
= netdev_priv(dev
);
4246 struct sky2_hw
*hw
= sky2
->hw
;
4249 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
4250 return 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
4253 static int sky2_vpd_wait(const struct sky2_hw
*hw
, int cap
, u16 busy
)
4255 unsigned long start
= jiffies
;
4257 while ( (sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
) & PCI_VPD_ADDR_F
) == busy
) {
4258 /* Can take up to 10.6 ms for write */
4259 if (time_after(jiffies
, start
+ HZ
/4)) {
4260 dev_err(&hw
->pdev
->dev
, "VPD cycle timed out\n");
4269 static int sky2_vpd_read(struct sky2_hw
*hw
, int cap
, void *data
,
4270 u16 offset
, size_t length
)
4274 while (length
> 0) {
4277 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
);
4278 rc
= sky2_vpd_wait(hw
, cap
, 0);
4282 val
= sky2_pci_read32(hw
, cap
+ PCI_VPD_DATA
);
4284 memcpy(data
, &val
, min(sizeof(val
), length
));
4285 offset
+= sizeof(u32
);
4286 data
+= sizeof(u32
);
4287 length
-= sizeof(u32
);
4293 static int sky2_vpd_write(struct sky2_hw
*hw
, int cap
, const void *data
,
4294 u16 offset
, unsigned int length
)
4299 for (i
= 0; i
< length
; i
+= sizeof(u32
)) {
4300 u32 val
= *(u32
*)(data
+ i
);
4302 sky2_pci_write32(hw
, cap
+ PCI_VPD_DATA
, val
);
4303 sky2_pci_write32(hw
, cap
+ PCI_VPD_ADDR
, offset
| PCI_VPD_ADDR_F
);
4305 rc
= sky2_vpd_wait(hw
, cap
, PCI_VPD_ADDR_F
);
4312 static int sky2_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
4315 struct sky2_port
*sky2
= netdev_priv(dev
);
4316 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
4321 eeprom
->magic
= SKY2_EEPROM_MAGIC
;
4323 return sky2_vpd_read(sky2
->hw
, cap
, data
, eeprom
->offset
, eeprom
->len
);
4326 static int sky2_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
4329 struct sky2_port
*sky2
= netdev_priv(dev
);
4330 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
4335 if (eeprom
->magic
!= SKY2_EEPROM_MAGIC
)
4338 /* Partial writes not supported */
4339 if ((eeprom
->offset
& 3) || (eeprom
->len
& 3))
4342 return sky2_vpd_write(sky2
->hw
, cap
, data
, eeprom
->offset
, eeprom
->len
);
4345 static netdev_features_t
sky2_fix_features(struct net_device
*dev
,
4346 netdev_features_t features
)
4348 const struct sky2_port
*sky2
= netdev_priv(dev
);
4349 const struct sky2_hw
*hw
= sky2
->hw
;
4351 /* In order to do Jumbo packets on these chips, need to turn off the
4352 * transmit store/forward. Therefore checksum offload won't work.
4354 if (dev
->mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
4355 netdev_info(dev
, "checksum offload not possible with jumbo frames\n");
4356 features
&= ~(NETIF_F_TSO
|NETIF_F_SG
|NETIF_F_ALL_CSUM
);
4359 /* Some hardware requires receive checksum for RSS to work. */
4360 if ( (features
& NETIF_F_RXHASH
) &&
4361 !(features
& NETIF_F_RXCSUM
) &&
4362 (sky2
->hw
->flags
& SKY2_HW_RSS_CHKSUM
)) {
4363 netdev_info(dev
, "receive hashing forces receive checksum\n");
4364 features
|= NETIF_F_RXCSUM
;
4370 static int sky2_set_features(struct net_device
*dev
, netdev_features_t features
)
4372 struct sky2_port
*sky2
= netdev_priv(dev
);
4373 netdev_features_t changed
= dev
->features
^ features
;
4375 if (changed
& NETIF_F_RXCSUM
) {
4376 bool on
= features
& NETIF_F_RXCSUM
;
4377 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
4378 on
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
4381 if (changed
& NETIF_F_RXHASH
)
4382 rx_set_rss(dev
, features
);
4384 if (changed
& (NETIF_F_HW_VLAN_TX
|NETIF_F_HW_VLAN_RX
))
4385 sky2_vlan_mode(dev
, features
);
4390 static const struct ethtool_ops sky2_ethtool_ops
= {
4391 .get_settings
= sky2_get_settings
,
4392 .set_settings
= sky2_set_settings
,
4393 .get_drvinfo
= sky2_get_drvinfo
,
4394 .get_wol
= sky2_get_wol
,
4395 .set_wol
= sky2_set_wol
,
4396 .get_msglevel
= sky2_get_msglevel
,
4397 .set_msglevel
= sky2_set_msglevel
,
4398 .nway_reset
= sky2_nway_reset
,
4399 .get_regs_len
= sky2_get_regs_len
,
4400 .get_regs
= sky2_get_regs
,
4401 .get_link
= ethtool_op_get_link
,
4402 .get_eeprom_len
= sky2_get_eeprom_len
,
4403 .get_eeprom
= sky2_get_eeprom
,
4404 .set_eeprom
= sky2_set_eeprom
,
4405 .get_strings
= sky2_get_strings
,
4406 .get_coalesce
= sky2_get_coalesce
,
4407 .set_coalesce
= sky2_set_coalesce
,
4408 .get_ringparam
= sky2_get_ringparam
,
4409 .set_ringparam
= sky2_set_ringparam
,
4410 .get_pauseparam
= sky2_get_pauseparam
,
4411 .set_pauseparam
= sky2_set_pauseparam
,
4412 .set_phys_id
= sky2_set_phys_id
,
4413 .get_sset_count
= sky2_get_sset_count
,
4414 .get_ethtool_stats
= sky2_get_ethtool_stats
,
4417 #ifdef CONFIG_SKY2_DEBUG
4419 static struct dentry
*sky2_debug
;
4423 * Read and parse the first part of Vital Product Data
4425 #define VPD_SIZE 128
4426 #define VPD_MAGIC 0x82
4428 static const struct vpd_tag
{
4432 { "PN", "Part Number" },
4433 { "EC", "Engineering Level" },
4434 { "MN", "Manufacturer" },
4435 { "SN", "Serial Number" },
4436 { "YA", "Asset Tag" },
4437 { "VL", "First Error Log Message" },
4438 { "VF", "Second Error Log Message" },
4439 { "VB", "Boot Agent ROM Configuration" },
4440 { "VE", "EFI UNDI Configuration" },
4443 static void sky2_show_vpd(struct seq_file
*seq
, struct sky2_hw
*hw
)
4451 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
4452 vpd_size
= 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
4454 seq_printf(seq
, "%s Product Data\n", pci_name(hw
->pdev
));
4455 buf
= kmalloc(vpd_size
, GFP_KERNEL
);
4457 seq_puts(seq
, "no memory!\n");
4461 if (pci_read_vpd(hw
->pdev
, 0, vpd_size
, buf
) < 0) {
4462 seq_puts(seq
, "VPD read failed\n");
4466 if (buf
[0] != VPD_MAGIC
) {
4467 seq_printf(seq
, "VPD tag mismatch: %#x\n", buf
[0]);
4471 if (len
== 0 || len
> vpd_size
- 4) {
4472 seq_printf(seq
, "Invalid id length: %d\n", len
);
4476 seq_printf(seq
, "%.*s\n", len
, buf
+ 3);
4479 while (offs
< vpd_size
- 4) {
4482 if (!memcmp("RW", buf
+ offs
, 2)) /* end marker */
4484 len
= buf
[offs
+ 2];
4485 if (offs
+ len
+ 3 >= vpd_size
)
4488 for (i
= 0; i
< ARRAY_SIZE(vpd_tags
); i
++) {
4489 if (!memcmp(vpd_tags
[i
].tag
, buf
+ offs
, 2)) {
4490 seq_printf(seq
, " %s: %.*s\n",
4491 vpd_tags
[i
].label
, len
, buf
+ offs
+ 3);
4501 static int sky2_debug_show(struct seq_file
*seq
, void *v
)
4503 struct net_device
*dev
= seq
->private;
4504 const struct sky2_port
*sky2
= netdev_priv(dev
);
4505 struct sky2_hw
*hw
= sky2
->hw
;
4506 unsigned port
= sky2
->port
;
4510 sky2_show_vpd(seq
, hw
);
4512 seq_printf(seq
, "\nIRQ src=%x mask=%x control=%x\n",
4513 sky2_read32(hw
, B0_ISRC
),
4514 sky2_read32(hw
, B0_IMSK
),
4515 sky2_read32(hw
, B0_Y2_SP_ICR
));
4517 if (!netif_running(dev
)) {
4518 seq_printf(seq
, "network not running\n");
4522 napi_disable(&hw
->napi
);
4523 last
= sky2_read16(hw
, STAT_PUT_IDX
);
4525 seq_printf(seq
, "Status ring %u\n", hw
->st_size
);
4526 if (hw
->st_idx
== last
)
4527 seq_puts(seq
, "Status ring (empty)\n");
4529 seq_puts(seq
, "Status ring\n");
4530 for (idx
= hw
->st_idx
; idx
!= last
&& idx
< hw
->st_size
;
4531 idx
= RING_NEXT(idx
, hw
->st_size
)) {
4532 const struct sky2_status_le
*le
= hw
->st_le
+ idx
;
4533 seq_printf(seq
, "[%d] %#x %d %#x\n",
4534 idx
, le
->opcode
, le
->length
, le
->status
);
4536 seq_puts(seq
, "\n");
4539 seq_printf(seq
, "Tx ring pending=%u...%u report=%d done=%d\n",
4540 sky2
->tx_cons
, sky2
->tx_prod
,
4541 sky2_read16(hw
, port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
4542 sky2_read16(hw
, Q_ADDR(txqaddr
[port
], Q_DONE
)));
4544 /* Dump contents of tx ring */
4546 for (idx
= sky2
->tx_next
; idx
!= sky2
->tx_prod
&& idx
< sky2
->tx_ring_size
;
4547 idx
= RING_NEXT(idx
, sky2
->tx_ring_size
)) {
4548 const struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
4549 u32 a
= le32_to_cpu(le
->addr
);
4552 seq_printf(seq
, "%u:", idx
);
4555 switch (le
->opcode
& ~HW_OWNER
) {
4557 seq_printf(seq
, " %#x:", a
);
4560 seq_printf(seq
, " mtu=%d", a
);
4563 seq_printf(seq
, " vlan=%d", be16_to_cpu(le
->length
));
4566 seq_printf(seq
, " csum=%#x", a
);
4569 seq_printf(seq
, " tso=%#x(%d)", a
, le16_to_cpu(le
->length
));
4572 seq_printf(seq
, " %#x(%d)", a
, le16_to_cpu(le
->length
));
4575 seq_printf(seq
, " frag=%#x(%d)", a
, le16_to_cpu(le
->length
));
4578 seq_printf(seq
, " op=%#x,%#x(%d)", le
->opcode
,
4579 a
, le16_to_cpu(le
->length
));
4582 if (le
->ctrl
& EOP
) {
4583 seq_putc(seq
, '\n');
4588 seq_printf(seq
, "\nRx ring hw get=%d put=%d last=%d\n",
4589 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_GET_IDX
)),
4590 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_PUT_IDX
)),
4591 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_LAST_IDX
)));
4593 sky2_read32(hw
, B0_Y2_SP_LISR
);
4594 napi_enable(&hw
->napi
);
4598 static int sky2_debug_open(struct inode
*inode
, struct file
*file
)
4600 return single_open(file
, sky2_debug_show
, inode
->i_private
);
4603 static const struct file_operations sky2_debug_fops
= {
4604 .owner
= THIS_MODULE
,
4605 .open
= sky2_debug_open
,
4607 .llseek
= seq_lseek
,
4608 .release
= single_release
,
4612 * Use network device events to create/remove/rename
4613 * debugfs file entries
4615 static int sky2_device_event(struct notifier_block
*unused
,
4616 unsigned long event
, void *ptr
)
4618 struct net_device
*dev
= ptr
;
4619 struct sky2_port
*sky2
= netdev_priv(dev
);
4621 if (dev
->netdev_ops
->ndo_open
!= sky2_open
|| !sky2_debug
)
4625 case NETDEV_CHANGENAME
:
4626 if (sky2
->debugfs
) {
4627 sky2
->debugfs
= debugfs_rename(sky2_debug
, sky2
->debugfs
,
4628 sky2_debug
, dev
->name
);
4632 case NETDEV_GOING_DOWN
:
4633 if (sky2
->debugfs
) {
4634 netdev_printk(KERN_DEBUG
, dev
, "remove debugfs\n");
4635 debugfs_remove(sky2
->debugfs
);
4636 sky2
->debugfs
= NULL
;
4641 sky2
->debugfs
= debugfs_create_file(dev
->name
, S_IRUGO
,
4644 if (IS_ERR(sky2
->debugfs
))
4645 sky2
->debugfs
= NULL
;
4651 static struct notifier_block sky2_notifier
= {
4652 .notifier_call
= sky2_device_event
,
4656 static __init
void sky2_debug_init(void)
4660 ent
= debugfs_create_dir("sky2", NULL
);
4661 if (!ent
|| IS_ERR(ent
))
4665 register_netdevice_notifier(&sky2_notifier
);
4668 static __exit
void sky2_debug_cleanup(void)
4671 unregister_netdevice_notifier(&sky2_notifier
);
4672 debugfs_remove(sky2_debug
);
4678 #define sky2_debug_init()
4679 #define sky2_debug_cleanup()
4682 /* Two copies of network device operations to handle special case of
4683 not allowing netpoll on second port */
4684 static const struct net_device_ops sky2_netdev_ops
[2] = {
4686 .ndo_open
= sky2_open
,
4687 .ndo_stop
= sky2_close
,
4688 .ndo_start_xmit
= sky2_xmit_frame
,
4689 .ndo_do_ioctl
= sky2_ioctl
,
4690 .ndo_validate_addr
= eth_validate_addr
,
4691 .ndo_set_mac_address
= sky2_set_mac_address
,
4692 .ndo_set_rx_mode
= sky2_set_multicast
,
4693 .ndo_change_mtu
= sky2_change_mtu
,
4694 .ndo_fix_features
= sky2_fix_features
,
4695 .ndo_set_features
= sky2_set_features
,
4696 .ndo_tx_timeout
= sky2_tx_timeout
,
4697 .ndo_get_stats64
= sky2_get_stats
,
4698 #ifdef CONFIG_NET_POLL_CONTROLLER
4699 .ndo_poll_controller
= sky2_netpoll
,
4703 .ndo_open
= sky2_open
,
4704 .ndo_stop
= sky2_close
,
4705 .ndo_start_xmit
= sky2_xmit_frame
,
4706 .ndo_do_ioctl
= sky2_ioctl
,
4707 .ndo_validate_addr
= eth_validate_addr
,
4708 .ndo_set_mac_address
= sky2_set_mac_address
,
4709 .ndo_set_rx_mode
= sky2_set_multicast
,
4710 .ndo_change_mtu
= sky2_change_mtu
,
4711 .ndo_fix_features
= sky2_fix_features
,
4712 .ndo_set_features
= sky2_set_features
,
4713 .ndo_tx_timeout
= sky2_tx_timeout
,
4714 .ndo_get_stats64
= sky2_get_stats
,
4718 /* Initialize network device */
4719 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
4721 int highmem
, int wol
)
4723 struct sky2_port
*sky2
;
4724 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
4729 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
4730 dev
->irq
= hw
->pdev
->irq
;
4731 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
4732 dev
->watchdog_timeo
= TX_WATCHDOG
;
4733 dev
->netdev_ops
= &sky2_netdev_ops
[port
];
4735 sky2
= netdev_priv(dev
);
4738 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
4740 /* Auto speed and flow control */
4741 sky2
->flags
= SKY2_FLAG_AUTO_SPEED
| SKY2_FLAG_AUTO_PAUSE
;
4742 if (hw
->chip_id
!= CHIP_ID_YUKON_XL
)
4743 dev
->hw_features
|= NETIF_F_RXCSUM
;
4745 sky2
->flow_mode
= FC_BOTH
;
4749 sky2
->advertising
= sky2_supported_modes(hw
);
4752 spin_lock_init(&sky2
->phy_lock
);
4754 sky2
->tx_pending
= TX_DEF_PENDING
;
4755 sky2
->tx_ring_size
= roundup_ring_size(TX_DEF_PENDING
);
4756 sky2
->rx_pending
= RX_DEF_PENDING
;
4758 hw
->dev
[port
] = dev
;
4762 dev
->hw_features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_TSO
;
4765 dev
->features
|= NETIF_F_HIGHDMA
;
4767 /* Enable receive hashing unless hardware is known broken */
4768 if (!(hw
->flags
& SKY2_HW_RSS_BROKEN
))
4769 dev
->hw_features
|= NETIF_F_RXHASH
;
4771 if (!(hw
->flags
& SKY2_HW_VLAN_BROKEN
)) {
4772 dev
->hw_features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
4773 dev
->vlan_features
|= SKY2_VLAN_OFFLOADS
;
4776 dev
->features
|= dev
->hw_features
;
4778 /* read the mac address */
4779 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
4780 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
4785 static void __devinit
sky2_show_addr(struct net_device
*dev
)
4787 const struct sky2_port
*sky2
= netdev_priv(dev
);
4789 netif_info(sky2
, probe
, dev
, "addr %pM\n", dev
->dev_addr
);
4792 /* Handle software interrupt used during MSI test */
4793 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
4795 struct sky2_hw
*hw
= dev_id
;
4796 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
4801 if (status
& Y2_IS_IRQ_SW
) {
4802 hw
->flags
|= SKY2_HW_USE_MSI
;
4803 wake_up(&hw
->msi_wait
);
4804 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4806 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
4811 /* Test interrupt path by forcing a a software IRQ */
4812 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
4814 struct pci_dev
*pdev
= hw
->pdev
;
4817 init_waitqueue_head(&hw
->msi_wait
);
4819 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
4821 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
4823 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4827 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
4828 sky2_read8(hw
, B0_CTST
);
4830 wait_event_timeout(hw
->msi_wait
, (hw
->flags
& SKY2_HW_USE_MSI
), HZ
/10);
4832 if (!(hw
->flags
& SKY2_HW_USE_MSI
)) {
4833 /* MSI test failed, go back to INTx mode */
4834 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
4835 "switching to INTx mode.\n");
4838 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4841 sky2_write32(hw
, B0_IMSK
, 0);
4842 sky2_read32(hw
, B0_IMSK
);
4844 free_irq(pdev
->irq
, hw
);
4849 /* This driver supports yukon2 chipset only */
4850 static const char *sky2_name(u8 chipid
, char *buf
, int sz
)
4852 const char *name
[] = {
4854 "EC Ultra", /* 0xb4 */
4855 "Extreme", /* 0xb5 */
4859 "Supreme", /* 0xb9 */
4861 "Unknown", /* 0xbb */
4862 "Optima", /* 0xbc */
4863 "Optima Prime", /* 0xbd */
4864 "Optima 2", /* 0xbe */
4867 if (chipid
>= CHIP_ID_YUKON_XL
&& chipid
<= CHIP_ID_YUKON_OP_2
)
4868 strncpy(buf
, name
[chipid
- CHIP_ID_YUKON_XL
], sz
);
4870 snprintf(buf
, sz
, "(chip %#x)", chipid
);
4874 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
4875 const struct pci_device_id
*ent
)
4877 struct net_device
*dev
, *dev1
;
4879 int err
, using_dac
= 0, wol_default
;
4883 err
= pci_enable_device(pdev
);
4885 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
4889 /* Get configuration information
4890 * Note: only regular PCI config access once to test for HW issues
4891 * other PCI access through shared memory for speed and to
4892 * avoid MMCONFIG problems.
4894 err
= pci_read_config_dword(pdev
, PCI_DEV_REG2
, ®
);
4896 dev_err(&pdev
->dev
, "PCI read config failed\n");
4901 dev_err(&pdev
->dev
, "PCI configuration read error\n");
4905 err
= pci_request_regions(pdev
, DRV_NAME
);
4907 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
4908 goto err_out_disable
;
4911 pci_set_master(pdev
);
4913 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
4914 !(err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)))) {
4916 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
4918 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
4919 "for consistent allocations\n");
4920 goto err_out_free_regions
;
4923 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
4925 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
4926 goto err_out_free_regions
;
4932 /* The sk98lin vendor driver uses hardware byte swapping but
4933 * this driver uses software swapping.
4935 reg
&= ~PCI_REV_DESC
;
4936 err
= pci_write_config_dword(pdev
, PCI_DEV_REG2
, reg
);
4938 dev_err(&pdev
->dev
, "PCI write config failed\n");
4939 goto err_out_free_regions
;
4943 wol_default
= device_may_wakeup(&pdev
->dev
) ? WAKE_MAGIC
: 0;
4947 hw
= kzalloc(sizeof(*hw
) + strlen(DRV_NAME
"@pci:")
4948 + strlen(pci_name(pdev
)) + 1, GFP_KERNEL
);
4950 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
4951 goto err_out_free_regions
;
4955 sprintf(hw
->irq_name
, DRV_NAME
"@pci:%s", pci_name(pdev
));
4957 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
4959 dev_err(&pdev
->dev
, "cannot map device registers\n");
4960 goto err_out_free_hw
;
4963 err
= sky2_init(hw
);
4965 goto err_out_iounmap
;
4967 /* ring for status responses */
4968 hw
->st_size
= hw
->ports
* roundup_pow_of_two(3*RX_MAX_PENDING
+ TX_MAX_PENDING
);
4969 hw
->st_le
= pci_alloc_consistent(pdev
, hw
->st_size
* sizeof(struct sky2_status_le
),
4974 dev_info(&pdev
->dev
, "Yukon-2 %s chip revision %d\n",
4975 sky2_name(hw
->chip_id
, buf1
, sizeof(buf1
)), hw
->chip_rev
);
4979 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
4982 goto err_out_free_pci
;
4985 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
4986 err
= sky2_test_msi(hw
);
4987 if (err
== -EOPNOTSUPP
)
4988 pci_disable_msi(pdev
);
4990 goto err_out_free_netdev
;
4993 err
= register_netdev(dev
);
4995 dev_err(&pdev
->dev
, "cannot register net device\n");
4996 goto err_out_free_netdev
;
4999 netif_carrier_off(dev
);
5001 netif_napi_add(dev
, &hw
->napi
, sky2_poll
, NAPI_WEIGHT
);
5003 sky2_show_addr(dev
);
5005 if (hw
->ports
> 1) {
5006 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
5009 goto err_out_unregister
;
5012 err
= register_netdev(dev1
);
5014 dev_err(&pdev
->dev
, "cannot register second net device\n");
5015 goto err_out_free_dev1
;
5018 err
= sky2_setup_irq(hw
, hw
->irq_name
);
5020 goto err_out_unregister_dev1
;
5022 sky2_show_addr(dev1
);
5025 setup_timer(&hw
->watchdog_timer
, sky2_watchdog
, (unsigned long) hw
);
5026 INIT_WORK(&hw
->restart_work
, sky2_restart
);
5028 pci_set_drvdata(pdev
, hw
);
5029 pdev
->d3_delay
= 150;
5033 err_out_unregister_dev1
:
5034 unregister_netdev(dev1
);
5038 if (hw
->flags
& SKY2_HW_USE_MSI
)
5039 pci_disable_msi(pdev
);
5040 unregister_netdev(dev
);
5041 err_out_free_netdev
:
5044 pci_free_consistent(pdev
, hw
->st_size
* sizeof(struct sky2_status_le
),
5045 hw
->st_le
, hw
->st_dma
);
5047 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
5052 err_out_free_regions
:
5053 pci_release_regions(pdev
);
5055 pci_disable_device(pdev
);
5057 pci_set_drvdata(pdev
, NULL
);
5061 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
5063 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
5069 del_timer_sync(&hw
->watchdog_timer
);
5070 cancel_work_sync(&hw
->restart_work
);
5072 for (i
= hw
->ports
-1; i
>= 0; --i
)
5073 unregister_netdev(hw
->dev
[i
]);
5075 sky2_write32(hw
, B0_IMSK
, 0);
5076 sky2_read32(hw
, B0_IMSK
);
5080 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
5081 sky2_read8(hw
, B0_CTST
);
5083 if (hw
->ports
> 1) {
5084 napi_disable(&hw
->napi
);
5085 free_irq(pdev
->irq
, hw
);
5088 if (hw
->flags
& SKY2_HW_USE_MSI
)
5089 pci_disable_msi(pdev
);
5090 pci_free_consistent(pdev
, hw
->st_size
* sizeof(struct sky2_status_le
),
5091 hw
->st_le
, hw
->st_dma
);
5092 pci_release_regions(pdev
);
5093 pci_disable_device(pdev
);
5095 for (i
= hw
->ports
-1; i
>= 0; --i
)
5096 free_netdev(hw
->dev
[i
]);
5101 pci_set_drvdata(pdev
, NULL
);
5104 static int sky2_suspend(struct device
*dev
)
5106 struct pci_dev
*pdev
= to_pci_dev(dev
);
5107 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
5113 del_timer_sync(&hw
->watchdog_timer
);
5114 cancel_work_sync(&hw
->restart_work
);
5119 for (i
= 0; i
< hw
->ports
; i
++) {
5120 struct net_device
*dev
= hw
->dev
[i
];
5121 struct sky2_port
*sky2
= netdev_priv(dev
);
5124 sky2_wol_init(sky2
);
5133 #ifdef CONFIG_PM_SLEEP
5134 static int sky2_resume(struct device
*dev
)
5136 struct pci_dev
*pdev
= to_pci_dev(dev
);
5137 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
5143 /* Re-enable all clocks */
5144 err
= pci_write_config_dword(pdev
, PCI_DEV_REG3
, 0);
5146 dev_err(&pdev
->dev
, "PCI write config failed\n");
5158 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
5159 pci_disable_device(pdev
);
5163 static SIMPLE_DEV_PM_OPS(sky2_pm_ops
, sky2_suspend
, sky2_resume
);
5164 #define SKY2_PM_OPS (&sky2_pm_ops)
5168 #define SKY2_PM_OPS NULL
5171 static void sky2_shutdown(struct pci_dev
*pdev
)
5173 sky2_suspend(&pdev
->dev
);
5174 pci_wake_from_d3(pdev
, device_may_wakeup(&pdev
->dev
));
5175 pci_set_power_state(pdev
, PCI_D3hot
);
5178 static struct pci_driver sky2_driver
= {
5180 .id_table
= sky2_id_table
,
5181 .probe
= sky2_probe
,
5182 .remove
= __devexit_p(sky2_remove
),
5183 .shutdown
= sky2_shutdown
,
5184 .driver
.pm
= SKY2_PM_OPS
,
5187 static int __init
sky2_init_module(void)
5189 pr_info("driver version " DRV_VERSION
"\n");
5192 return pci_register_driver(&sky2_driver
);
5195 static void __exit
sky2_cleanup_module(void)
5197 pci_unregister_driver(&sky2_driver
);
5198 sky2_debug_cleanup();
5201 module_init(sky2_init_module
);
5202 module_exit(sky2_cleanup_module
);
5204 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5205 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5206 MODULE_LICENSE("GPL");
5207 MODULE_VERSION(DRV_VERSION
);