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Merge tag 'for-linus-v3.10-rc3' of git://oss.sgi.com/xfs/xfs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / marvell / mv643xx_eth.c
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
24 *
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 */
39
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41
42 #include <linux/init.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/in.h>
45 #include <linux/ip.h>
46 #include <linux/tcp.h>
47 #include <linux/udp.h>
48 #include <linux/etherdevice.h>
49 #include <linux/delay.h>
50 #include <linux/ethtool.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/kernel.h>
54 #include <linux/spinlock.h>
55 #include <linux/workqueue.h>
56 #include <linux/phy.h>
57 #include <linux/mv643xx_eth.h>
58 #include <linux/io.h>
59 #include <linux/interrupt.h>
60 #include <linux/types.h>
61 #include <linux/slab.h>
62 #include <linux/clk.h>
63
64 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
65 static char mv643xx_eth_driver_version[] = "1.4";
66
67
68 /*
69 * Registers shared between all ports.
70 */
71 #define PHY_ADDR 0x0000
72 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
73 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
74 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
75 #define WINDOW_BAR_ENABLE 0x0290
76 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
77
78 /*
79 * Main per-port registers. These live at offset 0x0400 for
80 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
81 */
82 #define PORT_CONFIG 0x0000
83 #define UNICAST_PROMISCUOUS_MODE 0x00000001
84 #define PORT_CONFIG_EXT 0x0004
85 #define MAC_ADDR_LOW 0x0014
86 #define MAC_ADDR_HIGH 0x0018
87 #define SDMA_CONFIG 0x001c
88 #define TX_BURST_SIZE_16_64BIT 0x01000000
89 #define TX_BURST_SIZE_4_64BIT 0x00800000
90 #define BLM_TX_NO_SWAP 0x00000020
91 #define BLM_RX_NO_SWAP 0x00000010
92 #define RX_BURST_SIZE_16_64BIT 0x00000008
93 #define RX_BURST_SIZE_4_64BIT 0x00000004
94 #define PORT_SERIAL_CONTROL 0x003c
95 #define SET_MII_SPEED_TO_100 0x01000000
96 #define SET_GMII_SPEED_TO_1000 0x00800000
97 #define SET_FULL_DUPLEX_MODE 0x00200000
98 #define MAX_RX_PACKET_9700BYTE 0x000a0000
99 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
100 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
101 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
102 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
103 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
104 #define FORCE_LINK_PASS 0x00000002
105 #define SERIAL_PORT_ENABLE 0x00000001
106 #define PORT_STATUS 0x0044
107 #define TX_FIFO_EMPTY 0x00000400
108 #define TX_IN_PROGRESS 0x00000080
109 #define PORT_SPEED_MASK 0x00000030
110 #define PORT_SPEED_1000 0x00000010
111 #define PORT_SPEED_100 0x00000020
112 #define PORT_SPEED_10 0x00000000
113 #define FLOW_CONTROL_ENABLED 0x00000008
114 #define FULL_DUPLEX 0x00000004
115 #define LINK_UP 0x00000002
116 #define TXQ_COMMAND 0x0048
117 #define TXQ_FIX_PRIO_CONF 0x004c
118 #define TX_BW_RATE 0x0050
119 #define TX_BW_MTU 0x0058
120 #define TX_BW_BURST 0x005c
121 #define INT_CAUSE 0x0060
122 #define INT_TX_END 0x07f80000
123 #define INT_TX_END_0 0x00080000
124 #define INT_RX 0x000003fc
125 #define INT_RX_0 0x00000004
126 #define INT_EXT 0x00000002
127 #define INT_CAUSE_EXT 0x0064
128 #define INT_EXT_LINK_PHY 0x00110000
129 #define INT_EXT_TX 0x000000ff
130 #define INT_MASK 0x0068
131 #define INT_MASK_EXT 0x006c
132 #define TX_FIFO_URGENT_THRESHOLD 0x0074
133 #define RX_DISCARD_FRAME_CNT 0x0084
134 #define RX_OVERRUN_FRAME_CNT 0x0088
135 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
136 #define TX_BW_RATE_MOVED 0x00e0
137 #define TX_BW_MTU_MOVED 0x00e8
138 #define TX_BW_BURST_MOVED 0x00ec
139 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
140 #define RXQ_COMMAND 0x0280
141 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
142 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
143 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
144 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
145
146 /*
147 * Misc per-port registers.
148 */
149 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
150 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
151 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
152 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
153
154
155 /*
156 * SDMA configuration register default value.
157 */
158 #if defined(__BIG_ENDIAN)
159 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
160 (RX_BURST_SIZE_4_64BIT | \
161 TX_BURST_SIZE_4_64BIT)
162 #elif defined(__LITTLE_ENDIAN)
163 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
164 (RX_BURST_SIZE_4_64BIT | \
165 BLM_RX_NO_SWAP | \
166 BLM_TX_NO_SWAP | \
167 TX_BURST_SIZE_4_64BIT)
168 #else
169 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
170 #endif
171
172
173 /*
174 * Misc definitions.
175 */
176 #define DEFAULT_RX_QUEUE_SIZE 128
177 #define DEFAULT_TX_QUEUE_SIZE 256
178 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
179
180
181 /*
182 * RX/TX descriptors.
183 */
184 #if defined(__BIG_ENDIAN)
185 struct rx_desc {
186 u16 byte_cnt; /* Descriptor buffer byte count */
187 u16 buf_size; /* Buffer size */
188 u32 cmd_sts; /* Descriptor command status */
189 u32 next_desc_ptr; /* Next descriptor pointer */
190 u32 buf_ptr; /* Descriptor buffer pointer */
191 };
192
193 struct tx_desc {
194 u16 byte_cnt; /* buffer byte count */
195 u16 l4i_chk; /* CPU provided TCP checksum */
196 u32 cmd_sts; /* Command/status field */
197 u32 next_desc_ptr; /* Pointer to next descriptor */
198 u32 buf_ptr; /* pointer to buffer for this descriptor*/
199 };
200 #elif defined(__LITTLE_ENDIAN)
201 struct rx_desc {
202 u32 cmd_sts; /* Descriptor command status */
203 u16 buf_size; /* Buffer size */
204 u16 byte_cnt; /* Descriptor buffer byte count */
205 u32 buf_ptr; /* Descriptor buffer pointer */
206 u32 next_desc_ptr; /* Next descriptor pointer */
207 };
208
209 struct tx_desc {
210 u32 cmd_sts; /* Command/status field */
211 u16 l4i_chk; /* CPU provided TCP checksum */
212 u16 byte_cnt; /* buffer byte count */
213 u32 buf_ptr; /* pointer to buffer for this descriptor*/
214 u32 next_desc_ptr; /* Pointer to next descriptor */
215 };
216 #else
217 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
218 #endif
219
220 /* RX & TX descriptor command */
221 #define BUFFER_OWNED_BY_DMA 0x80000000
222
223 /* RX & TX descriptor status */
224 #define ERROR_SUMMARY 0x00000001
225
226 /* RX descriptor status */
227 #define LAYER_4_CHECKSUM_OK 0x40000000
228 #define RX_ENABLE_INTERRUPT 0x20000000
229 #define RX_FIRST_DESC 0x08000000
230 #define RX_LAST_DESC 0x04000000
231 #define RX_IP_HDR_OK 0x02000000
232 #define RX_PKT_IS_IPV4 0x01000000
233 #define RX_PKT_IS_ETHERNETV2 0x00800000
234 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
235 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
236 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
237
238 /* TX descriptor command */
239 #define TX_ENABLE_INTERRUPT 0x00800000
240 #define GEN_CRC 0x00400000
241 #define TX_FIRST_DESC 0x00200000
242 #define TX_LAST_DESC 0x00100000
243 #define ZERO_PADDING 0x00080000
244 #define GEN_IP_V4_CHECKSUM 0x00040000
245 #define GEN_TCP_UDP_CHECKSUM 0x00020000
246 #define UDP_FRAME 0x00010000
247 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
248 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
249
250 #define TX_IHL_SHIFT 11
251
252
253 /* global *******************************************************************/
254 struct mv643xx_eth_shared_private {
255 /*
256 * Ethernet controller base address.
257 */
258 void __iomem *base;
259
260 /*
261 * Per-port MBUS window access register value.
262 */
263 u32 win_protect;
264
265 /*
266 * Hardware-specific parameters.
267 */
268 int extended_rx_coal_limit;
269 int tx_bw_control;
270 int tx_csum_limit;
271 struct clk *clk;
272 };
273
274 #define TX_BW_CONTROL_ABSENT 0
275 #define TX_BW_CONTROL_OLD_LAYOUT 1
276 #define TX_BW_CONTROL_NEW_LAYOUT 2
277
278 static int mv643xx_eth_open(struct net_device *dev);
279 static int mv643xx_eth_stop(struct net_device *dev);
280
281
282 /* per-port *****************************************************************/
283 struct mib_counters {
284 u64 good_octets_received;
285 u32 bad_octets_received;
286 u32 internal_mac_transmit_err;
287 u32 good_frames_received;
288 u32 bad_frames_received;
289 u32 broadcast_frames_received;
290 u32 multicast_frames_received;
291 u32 frames_64_octets;
292 u32 frames_65_to_127_octets;
293 u32 frames_128_to_255_octets;
294 u32 frames_256_to_511_octets;
295 u32 frames_512_to_1023_octets;
296 u32 frames_1024_to_max_octets;
297 u64 good_octets_sent;
298 u32 good_frames_sent;
299 u32 excessive_collision;
300 u32 multicast_frames_sent;
301 u32 broadcast_frames_sent;
302 u32 unrec_mac_control_received;
303 u32 fc_sent;
304 u32 good_fc_received;
305 u32 bad_fc_received;
306 u32 undersize_received;
307 u32 fragments_received;
308 u32 oversize_received;
309 u32 jabber_received;
310 u32 mac_receive_error;
311 u32 bad_crc_event;
312 u32 collision;
313 u32 late_collision;
314 /* Non MIB hardware counters */
315 u32 rx_discard;
316 u32 rx_overrun;
317 };
318
319 struct rx_queue {
320 int index;
321
322 int rx_ring_size;
323
324 int rx_desc_count;
325 int rx_curr_desc;
326 int rx_used_desc;
327
328 struct rx_desc *rx_desc_area;
329 dma_addr_t rx_desc_dma;
330 int rx_desc_area_size;
331 struct sk_buff **rx_skb;
332 };
333
334 struct tx_queue {
335 int index;
336
337 int tx_ring_size;
338
339 int tx_desc_count;
340 int tx_curr_desc;
341 int tx_used_desc;
342
343 struct tx_desc *tx_desc_area;
344 dma_addr_t tx_desc_dma;
345 int tx_desc_area_size;
346
347 struct sk_buff_head tx_skb;
348
349 unsigned long tx_packets;
350 unsigned long tx_bytes;
351 unsigned long tx_dropped;
352 };
353
354 struct mv643xx_eth_private {
355 struct mv643xx_eth_shared_private *shared;
356 void __iomem *base;
357 int port_num;
358
359 struct net_device *dev;
360
361 struct phy_device *phy;
362
363 struct timer_list mib_counters_timer;
364 spinlock_t mib_counters_lock;
365 struct mib_counters mib_counters;
366
367 struct work_struct tx_timeout_task;
368
369 struct napi_struct napi;
370 u32 int_mask;
371 u8 oom;
372 u8 work_link;
373 u8 work_tx;
374 u8 work_tx_end;
375 u8 work_rx;
376 u8 work_rx_refill;
377
378 int skb_size;
379
380 /*
381 * RX state.
382 */
383 int rx_ring_size;
384 unsigned long rx_desc_sram_addr;
385 int rx_desc_sram_size;
386 int rxq_count;
387 struct timer_list rx_oom;
388 struct rx_queue rxq[8];
389
390 /*
391 * TX state.
392 */
393 int tx_ring_size;
394 unsigned long tx_desc_sram_addr;
395 int tx_desc_sram_size;
396 int txq_count;
397 struct tx_queue txq[8];
398
399 /*
400 * Hardware-specific parameters.
401 */
402 struct clk *clk;
403 unsigned int t_clk;
404 };
405
406
407 /* port register accessors **************************************************/
408 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
409 {
410 return readl(mp->shared->base + offset);
411 }
412
413 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
414 {
415 return readl(mp->base + offset);
416 }
417
418 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
419 {
420 writel(data, mp->shared->base + offset);
421 }
422
423 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
424 {
425 writel(data, mp->base + offset);
426 }
427
428
429 /* rxq/txq helper functions *************************************************/
430 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
431 {
432 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
433 }
434
435 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
436 {
437 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
438 }
439
440 static void rxq_enable(struct rx_queue *rxq)
441 {
442 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
443 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
444 }
445
446 static void rxq_disable(struct rx_queue *rxq)
447 {
448 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
449 u8 mask = 1 << rxq->index;
450
451 wrlp(mp, RXQ_COMMAND, mask << 8);
452 while (rdlp(mp, RXQ_COMMAND) & mask)
453 udelay(10);
454 }
455
456 static void txq_reset_hw_ptr(struct tx_queue *txq)
457 {
458 struct mv643xx_eth_private *mp = txq_to_mp(txq);
459 u32 addr;
460
461 addr = (u32)txq->tx_desc_dma;
462 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
463 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
464 }
465
466 static void txq_enable(struct tx_queue *txq)
467 {
468 struct mv643xx_eth_private *mp = txq_to_mp(txq);
469 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
470 }
471
472 static void txq_disable(struct tx_queue *txq)
473 {
474 struct mv643xx_eth_private *mp = txq_to_mp(txq);
475 u8 mask = 1 << txq->index;
476
477 wrlp(mp, TXQ_COMMAND, mask << 8);
478 while (rdlp(mp, TXQ_COMMAND) & mask)
479 udelay(10);
480 }
481
482 static void txq_maybe_wake(struct tx_queue *txq)
483 {
484 struct mv643xx_eth_private *mp = txq_to_mp(txq);
485 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
486
487 if (netif_tx_queue_stopped(nq)) {
488 __netif_tx_lock(nq, smp_processor_id());
489 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
490 netif_tx_wake_queue(nq);
491 __netif_tx_unlock(nq);
492 }
493 }
494
495 static int rxq_process(struct rx_queue *rxq, int budget)
496 {
497 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
498 struct net_device_stats *stats = &mp->dev->stats;
499 int rx;
500
501 rx = 0;
502 while (rx < budget && rxq->rx_desc_count) {
503 struct rx_desc *rx_desc;
504 unsigned int cmd_sts;
505 struct sk_buff *skb;
506 u16 byte_cnt;
507
508 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
509
510 cmd_sts = rx_desc->cmd_sts;
511 if (cmd_sts & BUFFER_OWNED_BY_DMA)
512 break;
513 rmb();
514
515 skb = rxq->rx_skb[rxq->rx_curr_desc];
516 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
517
518 rxq->rx_curr_desc++;
519 if (rxq->rx_curr_desc == rxq->rx_ring_size)
520 rxq->rx_curr_desc = 0;
521
522 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
523 rx_desc->buf_size, DMA_FROM_DEVICE);
524 rxq->rx_desc_count--;
525 rx++;
526
527 mp->work_rx_refill |= 1 << rxq->index;
528
529 byte_cnt = rx_desc->byte_cnt;
530
531 /*
532 * Update statistics.
533 *
534 * Note that the descriptor byte count includes 2 dummy
535 * bytes automatically inserted by the hardware at the
536 * start of the packet (which we don't count), and a 4
537 * byte CRC at the end of the packet (which we do count).
538 */
539 stats->rx_packets++;
540 stats->rx_bytes += byte_cnt - 2;
541
542 /*
543 * In case we received a packet without first / last bits
544 * on, or the error summary bit is set, the packet needs
545 * to be dropped.
546 */
547 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
548 != (RX_FIRST_DESC | RX_LAST_DESC))
549 goto err;
550
551 /*
552 * The -4 is for the CRC in the trailer of the
553 * received packet
554 */
555 skb_put(skb, byte_cnt - 2 - 4);
556
557 if (cmd_sts & LAYER_4_CHECKSUM_OK)
558 skb->ip_summed = CHECKSUM_UNNECESSARY;
559 skb->protocol = eth_type_trans(skb, mp->dev);
560
561 napi_gro_receive(&mp->napi, skb);
562
563 continue;
564
565 err:
566 stats->rx_dropped++;
567
568 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
569 (RX_FIRST_DESC | RX_LAST_DESC)) {
570 if (net_ratelimit())
571 netdev_err(mp->dev,
572 "received packet spanning multiple descriptors\n");
573 }
574
575 if (cmd_sts & ERROR_SUMMARY)
576 stats->rx_errors++;
577
578 dev_kfree_skb(skb);
579 }
580
581 if (rx < budget)
582 mp->work_rx &= ~(1 << rxq->index);
583
584 return rx;
585 }
586
587 static int rxq_refill(struct rx_queue *rxq, int budget)
588 {
589 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
590 int refilled;
591
592 refilled = 0;
593 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
594 struct sk_buff *skb;
595 int rx;
596 struct rx_desc *rx_desc;
597 int size;
598
599 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
600
601 if (skb == NULL) {
602 mp->oom = 1;
603 goto oom;
604 }
605
606 if (SKB_DMA_REALIGN)
607 skb_reserve(skb, SKB_DMA_REALIGN);
608
609 refilled++;
610 rxq->rx_desc_count++;
611
612 rx = rxq->rx_used_desc++;
613 if (rxq->rx_used_desc == rxq->rx_ring_size)
614 rxq->rx_used_desc = 0;
615
616 rx_desc = rxq->rx_desc_area + rx;
617
618 size = skb->end - skb->data;
619 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
620 skb->data, size,
621 DMA_FROM_DEVICE);
622 rx_desc->buf_size = size;
623 rxq->rx_skb[rx] = skb;
624 wmb();
625 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
626 wmb();
627
628 /*
629 * The hardware automatically prepends 2 bytes of
630 * dummy data to each received packet, so that the
631 * IP header ends up 16-byte aligned.
632 */
633 skb_reserve(skb, 2);
634 }
635
636 if (refilled < budget)
637 mp->work_rx_refill &= ~(1 << rxq->index);
638
639 oom:
640 return refilled;
641 }
642
643
644 /* tx ***********************************************************************/
645 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
646 {
647 int frag;
648
649 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
650 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
651
652 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
653 return 1;
654 }
655
656 return 0;
657 }
658
659 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
660 {
661 struct mv643xx_eth_private *mp = txq_to_mp(txq);
662 int nr_frags = skb_shinfo(skb)->nr_frags;
663 int frag;
664
665 for (frag = 0; frag < nr_frags; frag++) {
666 skb_frag_t *this_frag;
667 int tx_index;
668 struct tx_desc *desc;
669
670 this_frag = &skb_shinfo(skb)->frags[frag];
671 tx_index = txq->tx_curr_desc++;
672 if (txq->tx_curr_desc == txq->tx_ring_size)
673 txq->tx_curr_desc = 0;
674 desc = &txq->tx_desc_area[tx_index];
675
676 /*
677 * The last fragment will generate an interrupt
678 * which will free the skb on TX completion.
679 */
680 if (frag == nr_frags - 1) {
681 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
682 ZERO_PADDING | TX_LAST_DESC |
683 TX_ENABLE_INTERRUPT;
684 } else {
685 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
686 }
687
688 desc->l4i_chk = 0;
689 desc->byte_cnt = skb_frag_size(this_frag);
690 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
691 this_frag, 0,
692 skb_frag_size(this_frag),
693 DMA_TO_DEVICE);
694 }
695 }
696
697 static inline __be16 sum16_as_be(__sum16 sum)
698 {
699 return (__force __be16)sum;
700 }
701
702 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
703 {
704 struct mv643xx_eth_private *mp = txq_to_mp(txq);
705 int nr_frags = skb_shinfo(skb)->nr_frags;
706 int tx_index;
707 struct tx_desc *desc;
708 u32 cmd_sts;
709 u16 l4i_chk;
710 int length;
711
712 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
713 l4i_chk = 0;
714
715 if (skb->ip_summed == CHECKSUM_PARTIAL) {
716 int hdr_len;
717 int tag_bytes;
718
719 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
720 skb->protocol != htons(ETH_P_8021Q));
721
722 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
723 tag_bytes = hdr_len - ETH_HLEN;
724 if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
725 unlikely(tag_bytes & ~12)) {
726 if (skb_checksum_help(skb) == 0)
727 goto no_csum;
728 kfree_skb(skb);
729 return 1;
730 }
731
732 if (tag_bytes & 4)
733 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
734 if (tag_bytes & 8)
735 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
736
737 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
738 GEN_IP_V4_CHECKSUM |
739 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
740
741 switch (ip_hdr(skb)->protocol) {
742 case IPPROTO_UDP:
743 cmd_sts |= UDP_FRAME;
744 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
745 break;
746 case IPPROTO_TCP:
747 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
748 break;
749 default:
750 BUG();
751 }
752 } else {
753 no_csum:
754 /* Errata BTS #50, IHL must be 5 if no HW checksum */
755 cmd_sts |= 5 << TX_IHL_SHIFT;
756 }
757
758 tx_index = txq->tx_curr_desc++;
759 if (txq->tx_curr_desc == txq->tx_ring_size)
760 txq->tx_curr_desc = 0;
761 desc = &txq->tx_desc_area[tx_index];
762
763 if (nr_frags) {
764 txq_submit_frag_skb(txq, skb);
765 length = skb_headlen(skb);
766 } else {
767 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
768 length = skb->len;
769 }
770
771 desc->l4i_chk = l4i_chk;
772 desc->byte_cnt = length;
773 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
774 length, DMA_TO_DEVICE);
775
776 __skb_queue_tail(&txq->tx_skb, skb);
777
778 skb_tx_timestamp(skb);
779
780 /* ensure all other descriptors are written before first cmd_sts */
781 wmb();
782 desc->cmd_sts = cmd_sts;
783
784 /* clear TX_END status */
785 mp->work_tx_end &= ~(1 << txq->index);
786
787 /* ensure all descriptors are written before poking hardware */
788 wmb();
789 txq_enable(txq);
790
791 txq->tx_desc_count += nr_frags + 1;
792
793 return 0;
794 }
795
796 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
797 {
798 struct mv643xx_eth_private *mp = netdev_priv(dev);
799 int length, queue;
800 struct tx_queue *txq;
801 struct netdev_queue *nq;
802
803 queue = skb_get_queue_mapping(skb);
804 txq = mp->txq + queue;
805 nq = netdev_get_tx_queue(dev, queue);
806
807 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
808 txq->tx_dropped++;
809 netdev_printk(KERN_DEBUG, dev,
810 "failed to linearize skb with tiny unaligned fragment\n");
811 return NETDEV_TX_BUSY;
812 }
813
814 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
815 if (net_ratelimit())
816 netdev_err(dev, "tx queue full?!\n");
817 kfree_skb(skb);
818 return NETDEV_TX_OK;
819 }
820
821 length = skb->len;
822
823 if (!txq_submit_skb(txq, skb)) {
824 int entries_left;
825
826 txq->tx_bytes += length;
827 txq->tx_packets++;
828
829 entries_left = txq->tx_ring_size - txq->tx_desc_count;
830 if (entries_left < MAX_SKB_FRAGS + 1)
831 netif_tx_stop_queue(nq);
832 }
833
834 return NETDEV_TX_OK;
835 }
836
837
838 /* tx napi ******************************************************************/
839 static void txq_kick(struct tx_queue *txq)
840 {
841 struct mv643xx_eth_private *mp = txq_to_mp(txq);
842 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
843 u32 hw_desc_ptr;
844 u32 expected_ptr;
845
846 __netif_tx_lock(nq, smp_processor_id());
847
848 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
849 goto out;
850
851 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
852 expected_ptr = (u32)txq->tx_desc_dma +
853 txq->tx_curr_desc * sizeof(struct tx_desc);
854
855 if (hw_desc_ptr != expected_ptr)
856 txq_enable(txq);
857
858 out:
859 __netif_tx_unlock(nq);
860
861 mp->work_tx_end &= ~(1 << txq->index);
862 }
863
864 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
865 {
866 struct mv643xx_eth_private *mp = txq_to_mp(txq);
867 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
868 int reclaimed;
869
870 __netif_tx_lock_bh(nq);
871
872 reclaimed = 0;
873 while (reclaimed < budget && txq->tx_desc_count > 0) {
874 int tx_index;
875 struct tx_desc *desc;
876 u32 cmd_sts;
877 struct sk_buff *skb;
878
879 tx_index = txq->tx_used_desc;
880 desc = &txq->tx_desc_area[tx_index];
881 cmd_sts = desc->cmd_sts;
882
883 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
884 if (!force)
885 break;
886 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
887 }
888
889 txq->tx_used_desc = tx_index + 1;
890 if (txq->tx_used_desc == txq->tx_ring_size)
891 txq->tx_used_desc = 0;
892
893 reclaimed++;
894 txq->tx_desc_count--;
895
896 skb = NULL;
897 if (cmd_sts & TX_LAST_DESC)
898 skb = __skb_dequeue(&txq->tx_skb);
899
900 if (cmd_sts & ERROR_SUMMARY) {
901 netdev_info(mp->dev, "tx error\n");
902 mp->dev->stats.tx_errors++;
903 }
904
905 if (cmd_sts & TX_FIRST_DESC) {
906 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
907 desc->byte_cnt, DMA_TO_DEVICE);
908 } else {
909 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
910 desc->byte_cnt, DMA_TO_DEVICE);
911 }
912
913 dev_kfree_skb(skb);
914 }
915
916 __netif_tx_unlock_bh(nq);
917
918 if (reclaimed < budget)
919 mp->work_tx &= ~(1 << txq->index);
920
921 return reclaimed;
922 }
923
924
925 /* tx rate control **********************************************************/
926 /*
927 * Set total maximum TX rate (shared by all TX queues for this port)
928 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
929 */
930 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
931 {
932 int token_rate;
933 int mtu;
934 int bucket_size;
935
936 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
937 if (token_rate > 1023)
938 token_rate = 1023;
939
940 mtu = (mp->dev->mtu + 255) >> 8;
941 if (mtu > 63)
942 mtu = 63;
943
944 bucket_size = (burst + 255) >> 8;
945 if (bucket_size > 65535)
946 bucket_size = 65535;
947
948 switch (mp->shared->tx_bw_control) {
949 case TX_BW_CONTROL_OLD_LAYOUT:
950 wrlp(mp, TX_BW_RATE, token_rate);
951 wrlp(mp, TX_BW_MTU, mtu);
952 wrlp(mp, TX_BW_BURST, bucket_size);
953 break;
954 case TX_BW_CONTROL_NEW_LAYOUT:
955 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
956 wrlp(mp, TX_BW_MTU_MOVED, mtu);
957 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
958 break;
959 }
960 }
961
962 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
963 {
964 struct mv643xx_eth_private *mp = txq_to_mp(txq);
965 int token_rate;
966 int bucket_size;
967
968 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
969 if (token_rate > 1023)
970 token_rate = 1023;
971
972 bucket_size = (burst + 255) >> 8;
973 if (bucket_size > 65535)
974 bucket_size = 65535;
975
976 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
977 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
978 }
979
980 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
981 {
982 struct mv643xx_eth_private *mp = txq_to_mp(txq);
983 int off;
984 u32 val;
985
986 /*
987 * Turn on fixed priority mode.
988 */
989 off = 0;
990 switch (mp->shared->tx_bw_control) {
991 case TX_BW_CONTROL_OLD_LAYOUT:
992 off = TXQ_FIX_PRIO_CONF;
993 break;
994 case TX_BW_CONTROL_NEW_LAYOUT:
995 off = TXQ_FIX_PRIO_CONF_MOVED;
996 break;
997 }
998
999 if (off) {
1000 val = rdlp(mp, off);
1001 val |= 1 << txq->index;
1002 wrlp(mp, off, val);
1003 }
1004 }
1005
1006
1007 /* mii management interface *************************************************/
1008 static void mv643xx_adjust_pscr(struct mv643xx_eth_private *mp)
1009 {
1010 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1011 u32 autoneg_disable = FORCE_LINK_PASS |
1012 DISABLE_AUTO_NEG_SPEED_GMII |
1013 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1014 DISABLE_AUTO_NEG_FOR_DUPLEX;
1015
1016 if (mp->phy->autoneg == AUTONEG_ENABLE) {
1017 /* enable auto negotiation */
1018 pscr &= ~autoneg_disable;
1019 goto out_write;
1020 }
1021
1022 pscr |= autoneg_disable;
1023
1024 if (mp->phy->speed == SPEED_1000) {
1025 /* force gigabit, half duplex not supported */
1026 pscr |= SET_GMII_SPEED_TO_1000;
1027 pscr |= SET_FULL_DUPLEX_MODE;
1028 goto out_write;
1029 }
1030
1031 pscr &= ~SET_GMII_SPEED_TO_1000;
1032
1033 if (mp->phy->speed == SPEED_100)
1034 pscr |= SET_MII_SPEED_TO_100;
1035 else
1036 pscr &= ~SET_MII_SPEED_TO_100;
1037
1038 if (mp->phy->duplex == DUPLEX_FULL)
1039 pscr |= SET_FULL_DUPLEX_MODE;
1040 else
1041 pscr &= ~SET_FULL_DUPLEX_MODE;
1042
1043 out_write:
1044 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1045 }
1046
1047 /* statistics ***************************************************************/
1048 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1049 {
1050 struct mv643xx_eth_private *mp = netdev_priv(dev);
1051 struct net_device_stats *stats = &dev->stats;
1052 unsigned long tx_packets = 0;
1053 unsigned long tx_bytes = 0;
1054 unsigned long tx_dropped = 0;
1055 int i;
1056
1057 for (i = 0; i < mp->txq_count; i++) {
1058 struct tx_queue *txq = mp->txq + i;
1059
1060 tx_packets += txq->tx_packets;
1061 tx_bytes += txq->tx_bytes;
1062 tx_dropped += txq->tx_dropped;
1063 }
1064
1065 stats->tx_packets = tx_packets;
1066 stats->tx_bytes = tx_bytes;
1067 stats->tx_dropped = tx_dropped;
1068
1069 return stats;
1070 }
1071
1072 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1073 {
1074 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1075 }
1076
1077 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1078 {
1079 int i;
1080
1081 for (i = 0; i < 0x80; i += 4)
1082 mib_read(mp, i);
1083
1084 /* Clear non MIB hw counters also */
1085 rdlp(mp, RX_DISCARD_FRAME_CNT);
1086 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1087 }
1088
1089 static void mib_counters_update(struct mv643xx_eth_private *mp)
1090 {
1091 struct mib_counters *p = &mp->mib_counters;
1092
1093 spin_lock_bh(&mp->mib_counters_lock);
1094 p->good_octets_received += mib_read(mp, 0x00);
1095 p->bad_octets_received += mib_read(mp, 0x08);
1096 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1097 p->good_frames_received += mib_read(mp, 0x10);
1098 p->bad_frames_received += mib_read(mp, 0x14);
1099 p->broadcast_frames_received += mib_read(mp, 0x18);
1100 p->multicast_frames_received += mib_read(mp, 0x1c);
1101 p->frames_64_octets += mib_read(mp, 0x20);
1102 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1103 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1104 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1105 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1106 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1107 p->good_octets_sent += mib_read(mp, 0x38);
1108 p->good_frames_sent += mib_read(mp, 0x40);
1109 p->excessive_collision += mib_read(mp, 0x44);
1110 p->multicast_frames_sent += mib_read(mp, 0x48);
1111 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1112 p->unrec_mac_control_received += mib_read(mp, 0x50);
1113 p->fc_sent += mib_read(mp, 0x54);
1114 p->good_fc_received += mib_read(mp, 0x58);
1115 p->bad_fc_received += mib_read(mp, 0x5c);
1116 p->undersize_received += mib_read(mp, 0x60);
1117 p->fragments_received += mib_read(mp, 0x64);
1118 p->oversize_received += mib_read(mp, 0x68);
1119 p->jabber_received += mib_read(mp, 0x6c);
1120 p->mac_receive_error += mib_read(mp, 0x70);
1121 p->bad_crc_event += mib_read(mp, 0x74);
1122 p->collision += mib_read(mp, 0x78);
1123 p->late_collision += mib_read(mp, 0x7c);
1124 /* Non MIB hardware counters */
1125 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1126 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1127 spin_unlock_bh(&mp->mib_counters_lock);
1128
1129 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1130 }
1131
1132 static void mib_counters_timer_wrapper(unsigned long _mp)
1133 {
1134 struct mv643xx_eth_private *mp = (void *)_mp;
1135
1136 mib_counters_update(mp);
1137 }
1138
1139
1140 /* interrupt coalescing *****************************************************/
1141 /*
1142 * Hardware coalescing parameters are set in units of 64 t_clk
1143 * cycles. I.e.:
1144 *
1145 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1146 *
1147 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1148 *
1149 * In the ->set*() methods, we round the computed register value
1150 * to the nearest integer.
1151 */
1152 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1153 {
1154 u32 val = rdlp(mp, SDMA_CONFIG);
1155 u64 temp;
1156
1157 if (mp->shared->extended_rx_coal_limit)
1158 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1159 else
1160 temp = (val & 0x003fff00) >> 8;
1161
1162 temp *= 64000000;
1163 do_div(temp, mp->t_clk);
1164
1165 return (unsigned int)temp;
1166 }
1167
1168 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1169 {
1170 u64 temp;
1171 u32 val;
1172
1173 temp = (u64)usec * mp->t_clk;
1174 temp += 31999999;
1175 do_div(temp, 64000000);
1176
1177 val = rdlp(mp, SDMA_CONFIG);
1178 if (mp->shared->extended_rx_coal_limit) {
1179 if (temp > 0xffff)
1180 temp = 0xffff;
1181 val &= ~0x023fff80;
1182 val |= (temp & 0x8000) << 10;
1183 val |= (temp & 0x7fff) << 7;
1184 } else {
1185 if (temp > 0x3fff)
1186 temp = 0x3fff;
1187 val &= ~0x003fff00;
1188 val |= (temp & 0x3fff) << 8;
1189 }
1190 wrlp(mp, SDMA_CONFIG, val);
1191 }
1192
1193 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1194 {
1195 u64 temp;
1196
1197 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1198 temp *= 64000000;
1199 do_div(temp, mp->t_clk);
1200
1201 return (unsigned int)temp;
1202 }
1203
1204 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1205 {
1206 u64 temp;
1207
1208 temp = (u64)usec * mp->t_clk;
1209 temp += 31999999;
1210 do_div(temp, 64000000);
1211
1212 if (temp > 0x3fff)
1213 temp = 0x3fff;
1214
1215 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1216 }
1217
1218
1219 /* ethtool ******************************************************************/
1220 struct mv643xx_eth_stats {
1221 char stat_string[ETH_GSTRING_LEN];
1222 int sizeof_stat;
1223 int netdev_off;
1224 int mp_off;
1225 };
1226
1227 #define SSTAT(m) \
1228 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1229 offsetof(struct net_device, stats.m), -1 }
1230
1231 #define MIBSTAT(m) \
1232 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1233 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1234
1235 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1236 SSTAT(rx_packets),
1237 SSTAT(tx_packets),
1238 SSTAT(rx_bytes),
1239 SSTAT(tx_bytes),
1240 SSTAT(rx_errors),
1241 SSTAT(tx_errors),
1242 SSTAT(rx_dropped),
1243 SSTAT(tx_dropped),
1244 MIBSTAT(good_octets_received),
1245 MIBSTAT(bad_octets_received),
1246 MIBSTAT(internal_mac_transmit_err),
1247 MIBSTAT(good_frames_received),
1248 MIBSTAT(bad_frames_received),
1249 MIBSTAT(broadcast_frames_received),
1250 MIBSTAT(multicast_frames_received),
1251 MIBSTAT(frames_64_octets),
1252 MIBSTAT(frames_65_to_127_octets),
1253 MIBSTAT(frames_128_to_255_octets),
1254 MIBSTAT(frames_256_to_511_octets),
1255 MIBSTAT(frames_512_to_1023_octets),
1256 MIBSTAT(frames_1024_to_max_octets),
1257 MIBSTAT(good_octets_sent),
1258 MIBSTAT(good_frames_sent),
1259 MIBSTAT(excessive_collision),
1260 MIBSTAT(multicast_frames_sent),
1261 MIBSTAT(broadcast_frames_sent),
1262 MIBSTAT(unrec_mac_control_received),
1263 MIBSTAT(fc_sent),
1264 MIBSTAT(good_fc_received),
1265 MIBSTAT(bad_fc_received),
1266 MIBSTAT(undersize_received),
1267 MIBSTAT(fragments_received),
1268 MIBSTAT(oversize_received),
1269 MIBSTAT(jabber_received),
1270 MIBSTAT(mac_receive_error),
1271 MIBSTAT(bad_crc_event),
1272 MIBSTAT(collision),
1273 MIBSTAT(late_collision),
1274 MIBSTAT(rx_discard),
1275 MIBSTAT(rx_overrun),
1276 };
1277
1278 static int
1279 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1280 struct ethtool_cmd *cmd)
1281 {
1282 int err;
1283
1284 err = phy_read_status(mp->phy);
1285 if (err == 0)
1286 err = phy_ethtool_gset(mp->phy, cmd);
1287
1288 /*
1289 * The MAC does not support 1000baseT_Half.
1290 */
1291 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1292 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1293
1294 return err;
1295 }
1296
1297 static int
1298 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1299 struct ethtool_cmd *cmd)
1300 {
1301 u32 port_status;
1302
1303 port_status = rdlp(mp, PORT_STATUS);
1304
1305 cmd->supported = SUPPORTED_MII;
1306 cmd->advertising = ADVERTISED_MII;
1307 switch (port_status & PORT_SPEED_MASK) {
1308 case PORT_SPEED_10:
1309 ethtool_cmd_speed_set(cmd, SPEED_10);
1310 break;
1311 case PORT_SPEED_100:
1312 ethtool_cmd_speed_set(cmd, SPEED_100);
1313 break;
1314 case PORT_SPEED_1000:
1315 ethtool_cmd_speed_set(cmd, SPEED_1000);
1316 break;
1317 default:
1318 cmd->speed = -1;
1319 break;
1320 }
1321 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1322 cmd->port = PORT_MII;
1323 cmd->phy_address = 0;
1324 cmd->transceiver = XCVR_INTERNAL;
1325 cmd->autoneg = AUTONEG_DISABLE;
1326 cmd->maxtxpkt = 1;
1327 cmd->maxrxpkt = 1;
1328
1329 return 0;
1330 }
1331
1332 static void
1333 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1334 {
1335 struct mv643xx_eth_private *mp = netdev_priv(dev);
1336 wol->supported = 0;
1337 wol->wolopts = 0;
1338 if (mp->phy)
1339 phy_ethtool_get_wol(mp->phy, wol);
1340 }
1341
1342 static int
1343 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1344 {
1345 struct mv643xx_eth_private *mp = netdev_priv(dev);
1346 int err;
1347
1348 if (mp->phy == NULL)
1349 return -EOPNOTSUPP;
1350
1351 err = phy_ethtool_set_wol(mp->phy, wol);
1352 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1353 * this debugging hint is useful to have.
1354 */
1355 if (err == -EOPNOTSUPP)
1356 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1357 return err;
1358 }
1359
1360 static int
1361 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1362 {
1363 struct mv643xx_eth_private *mp = netdev_priv(dev);
1364
1365 if (mp->phy != NULL)
1366 return mv643xx_eth_get_settings_phy(mp, cmd);
1367 else
1368 return mv643xx_eth_get_settings_phyless(mp, cmd);
1369 }
1370
1371 static int
1372 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1373 {
1374 struct mv643xx_eth_private *mp = netdev_priv(dev);
1375 int ret;
1376
1377 if (mp->phy == NULL)
1378 return -EINVAL;
1379
1380 /*
1381 * The MAC does not support 1000baseT_Half.
1382 */
1383 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1384
1385 ret = phy_ethtool_sset(mp->phy, cmd);
1386 if (!ret)
1387 mv643xx_adjust_pscr(mp);
1388 return ret;
1389 }
1390
1391 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1392 struct ethtool_drvinfo *drvinfo)
1393 {
1394 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1395 sizeof(drvinfo->driver));
1396 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1397 sizeof(drvinfo->version));
1398 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1399 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1400 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1401 }
1402
1403 static int mv643xx_eth_nway_reset(struct net_device *dev)
1404 {
1405 struct mv643xx_eth_private *mp = netdev_priv(dev);
1406
1407 if (mp->phy == NULL)
1408 return -EINVAL;
1409
1410 return genphy_restart_aneg(mp->phy);
1411 }
1412
1413 static int
1414 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1415 {
1416 struct mv643xx_eth_private *mp = netdev_priv(dev);
1417
1418 ec->rx_coalesce_usecs = get_rx_coal(mp);
1419 ec->tx_coalesce_usecs = get_tx_coal(mp);
1420
1421 return 0;
1422 }
1423
1424 static int
1425 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1426 {
1427 struct mv643xx_eth_private *mp = netdev_priv(dev);
1428
1429 set_rx_coal(mp, ec->rx_coalesce_usecs);
1430 set_tx_coal(mp, ec->tx_coalesce_usecs);
1431
1432 return 0;
1433 }
1434
1435 static void
1436 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1437 {
1438 struct mv643xx_eth_private *mp = netdev_priv(dev);
1439
1440 er->rx_max_pending = 4096;
1441 er->tx_max_pending = 4096;
1442
1443 er->rx_pending = mp->rx_ring_size;
1444 er->tx_pending = mp->tx_ring_size;
1445 }
1446
1447 static int
1448 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1449 {
1450 struct mv643xx_eth_private *mp = netdev_priv(dev);
1451
1452 if (er->rx_mini_pending || er->rx_jumbo_pending)
1453 return -EINVAL;
1454
1455 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1456 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1457
1458 if (netif_running(dev)) {
1459 mv643xx_eth_stop(dev);
1460 if (mv643xx_eth_open(dev)) {
1461 netdev_err(dev,
1462 "fatal error on re-opening device after ring param change\n");
1463 return -ENOMEM;
1464 }
1465 }
1466
1467 return 0;
1468 }
1469
1470
1471 static int
1472 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1473 {
1474 struct mv643xx_eth_private *mp = netdev_priv(dev);
1475 bool rx_csum = features & NETIF_F_RXCSUM;
1476
1477 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1478
1479 return 0;
1480 }
1481
1482 static void mv643xx_eth_get_strings(struct net_device *dev,
1483 uint32_t stringset, uint8_t *data)
1484 {
1485 int i;
1486
1487 if (stringset == ETH_SS_STATS) {
1488 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1489 memcpy(data + i * ETH_GSTRING_LEN,
1490 mv643xx_eth_stats[i].stat_string,
1491 ETH_GSTRING_LEN);
1492 }
1493 }
1494 }
1495
1496 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1497 struct ethtool_stats *stats,
1498 uint64_t *data)
1499 {
1500 struct mv643xx_eth_private *mp = netdev_priv(dev);
1501 int i;
1502
1503 mv643xx_eth_get_stats(dev);
1504 mib_counters_update(mp);
1505
1506 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1507 const struct mv643xx_eth_stats *stat;
1508 void *p;
1509
1510 stat = mv643xx_eth_stats + i;
1511
1512 if (stat->netdev_off >= 0)
1513 p = ((void *)mp->dev) + stat->netdev_off;
1514 else
1515 p = ((void *)mp) + stat->mp_off;
1516
1517 data[i] = (stat->sizeof_stat == 8) ?
1518 *(uint64_t *)p : *(uint32_t *)p;
1519 }
1520 }
1521
1522 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1523 {
1524 if (sset == ETH_SS_STATS)
1525 return ARRAY_SIZE(mv643xx_eth_stats);
1526
1527 return -EOPNOTSUPP;
1528 }
1529
1530 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1531 .get_settings = mv643xx_eth_get_settings,
1532 .set_settings = mv643xx_eth_set_settings,
1533 .get_drvinfo = mv643xx_eth_get_drvinfo,
1534 .nway_reset = mv643xx_eth_nway_reset,
1535 .get_link = ethtool_op_get_link,
1536 .get_coalesce = mv643xx_eth_get_coalesce,
1537 .set_coalesce = mv643xx_eth_set_coalesce,
1538 .get_ringparam = mv643xx_eth_get_ringparam,
1539 .set_ringparam = mv643xx_eth_set_ringparam,
1540 .get_strings = mv643xx_eth_get_strings,
1541 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1542 .get_sset_count = mv643xx_eth_get_sset_count,
1543 .get_ts_info = ethtool_op_get_ts_info,
1544 .get_wol = mv643xx_eth_get_wol,
1545 .set_wol = mv643xx_eth_set_wol,
1546 };
1547
1548
1549 /* address handling *********************************************************/
1550 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1551 {
1552 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1553 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1554
1555 addr[0] = (mac_h >> 24) & 0xff;
1556 addr[1] = (mac_h >> 16) & 0xff;
1557 addr[2] = (mac_h >> 8) & 0xff;
1558 addr[3] = mac_h & 0xff;
1559 addr[4] = (mac_l >> 8) & 0xff;
1560 addr[5] = mac_l & 0xff;
1561 }
1562
1563 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1564 {
1565 wrlp(mp, MAC_ADDR_HIGH,
1566 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1567 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1568 }
1569
1570 static u32 uc_addr_filter_mask(struct net_device *dev)
1571 {
1572 struct netdev_hw_addr *ha;
1573 u32 nibbles;
1574
1575 if (dev->flags & IFF_PROMISC)
1576 return 0;
1577
1578 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1579 netdev_for_each_uc_addr(ha, dev) {
1580 if (memcmp(dev->dev_addr, ha->addr, 5))
1581 return 0;
1582 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1583 return 0;
1584
1585 nibbles |= 1 << (ha->addr[5] & 0x0f);
1586 }
1587
1588 return nibbles;
1589 }
1590
1591 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1592 {
1593 struct mv643xx_eth_private *mp = netdev_priv(dev);
1594 u32 port_config;
1595 u32 nibbles;
1596 int i;
1597
1598 uc_addr_set(mp, dev->dev_addr);
1599
1600 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1601
1602 nibbles = uc_addr_filter_mask(dev);
1603 if (!nibbles) {
1604 port_config |= UNICAST_PROMISCUOUS_MODE;
1605 nibbles = 0xffff;
1606 }
1607
1608 for (i = 0; i < 16; i += 4) {
1609 int off = UNICAST_TABLE(mp->port_num) + i;
1610 u32 v;
1611
1612 v = 0;
1613 if (nibbles & 1)
1614 v |= 0x00000001;
1615 if (nibbles & 2)
1616 v |= 0x00000100;
1617 if (nibbles & 4)
1618 v |= 0x00010000;
1619 if (nibbles & 8)
1620 v |= 0x01000000;
1621 nibbles >>= 4;
1622
1623 wrl(mp, off, v);
1624 }
1625
1626 wrlp(mp, PORT_CONFIG, port_config);
1627 }
1628
1629 static int addr_crc(unsigned char *addr)
1630 {
1631 int crc = 0;
1632 int i;
1633
1634 for (i = 0; i < 6; i++) {
1635 int j;
1636
1637 crc = (crc ^ addr[i]) << 8;
1638 for (j = 7; j >= 0; j--) {
1639 if (crc & (0x100 << j))
1640 crc ^= 0x107 << j;
1641 }
1642 }
1643
1644 return crc;
1645 }
1646
1647 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1648 {
1649 struct mv643xx_eth_private *mp = netdev_priv(dev);
1650 u32 *mc_spec;
1651 u32 *mc_other;
1652 struct netdev_hw_addr *ha;
1653 int i;
1654
1655 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1656 int port_num;
1657 u32 accept;
1658
1659 oom:
1660 port_num = mp->port_num;
1661 accept = 0x01010101;
1662 for (i = 0; i < 0x100; i += 4) {
1663 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1664 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1665 }
1666 return;
1667 }
1668
1669 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1670 if (mc_spec == NULL)
1671 goto oom;
1672 mc_other = mc_spec + (0x100 >> 2);
1673
1674 memset(mc_spec, 0, 0x100);
1675 memset(mc_other, 0, 0x100);
1676
1677 netdev_for_each_mc_addr(ha, dev) {
1678 u8 *a = ha->addr;
1679 u32 *table;
1680 int entry;
1681
1682 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1683 table = mc_spec;
1684 entry = a[5];
1685 } else {
1686 table = mc_other;
1687 entry = addr_crc(a);
1688 }
1689
1690 table[entry >> 2] |= 1 << (8 * (entry & 3));
1691 }
1692
1693 for (i = 0; i < 0x100; i += 4) {
1694 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1695 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1696 }
1697
1698 kfree(mc_spec);
1699 }
1700
1701 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1702 {
1703 mv643xx_eth_program_unicast_filter(dev);
1704 mv643xx_eth_program_multicast_filter(dev);
1705 }
1706
1707 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1708 {
1709 struct sockaddr *sa = addr;
1710
1711 if (!is_valid_ether_addr(sa->sa_data))
1712 return -EADDRNOTAVAIL;
1713
1714 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1715
1716 netif_addr_lock_bh(dev);
1717 mv643xx_eth_program_unicast_filter(dev);
1718 netif_addr_unlock_bh(dev);
1719
1720 return 0;
1721 }
1722
1723
1724 /* rx/tx queue initialisation ***********************************************/
1725 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1726 {
1727 struct rx_queue *rxq = mp->rxq + index;
1728 struct rx_desc *rx_desc;
1729 int size;
1730 int i;
1731
1732 rxq->index = index;
1733
1734 rxq->rx_ring_size = mp->rx_ring_size;
1735
1736 rxq->rx_desc_count = 0;
1737 rxq->rx_curr_desc = 0;
1738 rxq->rx_used_desc = 0;
1739
1740 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1741
1742 if (index == 0 && size <= mp->rx_desc_sram_size) {
1743 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1744 mp->rx_desc_sram_size);
1745 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1746 } else {
1747 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1748 size, &rxq->rx_desc_dma,
1749 GFP_KERNEL);
1750 }
1751
1752 if (rxq->rx_desc_area == NULL) {
1753 netdev_err(mp->dev,
1754 "can't allocate rx ring (%d bytes)\n", size);
1755 goto out;
1756 }
1757 memset(rxq->rx_desc_area, 0, size);
1758
1759 rxq->rx_desc_area_size = size;
1760 rxq->rx_skb = kmalloc_array(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1761 GFP_KERNEL);
1762 if (rxq->rx_skb == NULL)
1763 goto out_free;
1764
1765 rx_desc = rxq->rx_desc_area;
1766 for (i = 0; i < rxq->rx_ring_size; i++) {
1767 int nexti;
1768
1769 nexti = i + 1;
1770 if (nexti == rxq->rx_ring_size)
1771 nexti = 0;
1772
1773 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1774 nexti * sizeof(struct rx_desc);
1775 }
1776
1777 return 0;
1778
1779
1780 out_free:
1781 if (index == 0 && size <= mp->rx_desc_sram_size)
1782 iounmap(rxq->rx_desc_area);
1783 else
1784 dma_free_coherent(mp->dev->dev.parent, size,
1785 rxq->rx_desc_area,
1786 rxq->rx_desc_dma);
1787
1788 out:
1789 return -ENOMEM;
1790 }
1791
1792 static void rxq_deinit(struct rx_queue *rxq)
1793 {
1794 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1795 int i;
1796
1797 rxq_disable(rxq);
1798
1799 for (i = 0; i < rxq->rx_ring_size; i++) {
1800 if (rxq->rx_skb[i]) {
1801 dev_kfree_skb(rxq->rx_skb[i]);
1802 rxq->rx_desc_count--;
1803 }
1804 }
1805
1806 if (rxq->rx_desc_count) {
1807 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
1808 rxq->rx_desc_count);
1809 }
1810
1811 if (rxq->index == 0 &&
1812 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1813 iounmap(rxq->rx_desc_area);
1814 else
1815 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
1816 rxq->rx_desc_area, rxq->rx_desc_dma);
1817
1818 kfree(rxq->rx_skb);
1819 }
1820
1821 static int txq_init(struct mv643xx_eth_private *mp, int index)
1822 {
1823 struct tx_queue *txq = mp->txq + index;
1824 struct tx_desc *tx_desc;
1825 int size;
1826 int i;
1827
1828 txq->index = index;
1829
1830 txq->tx_ring_size = mp->tx_ring_size;
1831
1832 txq->tx_desc_count = 0;
1833 txq->tx_curr_desc = 0;
1834 txq->tx_used_desc = 0;
1835
1836 size = txq->tx_ring_size * sizeof(struct tx_desc);
1837
1838 if (index == 0 && size <= mp->tx_desc_sram_size) {
1839 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1840 mp->tx_desc_sram_size);
1841 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1842 } else {
1843 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1844 size, &txq->tx_desc_dma,
1845 GFP_KERNEL);
1846 }
1847
1848 if (txq->tx_desc_area == NULL) {
1849 netdev_err(mp->dev,
1850 "can't allocate tx ring (%d bytes)\n", size);
1851 return -ENOMEM;
1852 }
1853 memset(txq->tx_desc_area, 0, size);
1854
1855 txq->tx_desc_area_size = size;
1856
1857 tx_desc = txq->tx_desc_area;
1858 for (i = 0; i < txq->tx_ring_size; i++) {
1859 struct tx_desc *txd = tx_desc + i;
1860 int nexti;
1861
1862 nexti = i + 1;
1863 if (nexti == txq->tx_ring_size)
1864 nexti = 0;
1865
1866 txd->cmd_sts = 0;
1867 txd->next_desc_ptr = txq->tx_desc_dma +
1868 nexti * sizeof(struct tx_desc);
1869 }
1870
1871 skb_queue_head_init(&txq->tx_skb);
1872
1873 return 0;
1874 }
1875
1876 static void txq_deinit(struct tx_queue *txq)
1877 {
1878 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1879
1880 txq_disable(txq);
1881 txq_reclaim(txq, txq->tx_ring_size, 1);
1882
1883 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1884
1885 if (txq->index == 0 &&
1886 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1887 iounmap(txq->tx_desc_area);
1888 else
1889 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
1890 txq->tx_desc_area, txq->tx_desc_dma);
1891 }
1892
1893
1894 /* netdev ops and related ***************************************************/
1895 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1896 {
1897 u32 int_cause;
1898 u32 int_cause_ext;
1899
1900 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1901 if (int_cause == 0)
1902 return 0;
1903
1904 int_cause_ext = 0;
1905 if (int_cause & INT_EXT) {
1906 int_cause &= ~INT_EXT;
1907 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1908 }
1909
1910 if (int_cause) {
1911 wrlp(mp, INT_CAUSE, ~int_cause);
1912 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1913 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1914 mp->work_rx |= (int_cause & INT_RX) >> 2;
1915 }
1916
1917 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1918 if (int_cause_ext) {
1919 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1920 if (int_cause_ext & INT_EXT_LINK_PHY)
1921 mp->work_link = 1;
1922 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1923 }
1924
1925 return 1;
1926 }
1927
1928 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1929 {
1930 struct net_device *dev = (struct net_device *)dev_id;
1931 struct mv643xx_eth_private *mp = netdev_priv(dev);
1932
1933 if (unlikely(!mv643xx_eth_collect_events(mp)))
1934 return IRQ_NONE;
1935
1936 wrlp(mp, INT_MASK, 0);
1937 napi_schedule(&mp->napi);
1938
1939 return IRQ_HANDLED;
1940 }
1941
1942 static void handle_link_event(struct mv643xx_eth_private *mp)
1943 {
1944 struct net_device *dev = mp->dev;
1945 u32 port_status;
1946 int speed;
1947 int duplex;
1948 int fc;
1949
1950 port_status = rdlp(mp, PORT_STATUS);
1951 if (!(port_status & LINK_UP)) {
1952 if (netif_carrier_ok(dev)) {
1953 int i;
1954
1955 netdev_info(dev, "link down\n");
1956
1957 netif_carrier_off(dev);
1958
1959 for (i = 0; i < mp->txq_count; i++) {
1960 struct tx_queue *txq = mp->txq + i;
1961
1962 txq_reclaim(txq, txq->tx_ring_size, 1);
1963 txq_reset_hw_ptr(txq);
1964 }
1965 }
1966 return;
1967 }
1968
1969 switch (port_status & PORT_SPEED_MASK) {
1970 case PORT_SPEED_10:
1971 speed = 10;
1972 break;
1973 case PORT_SPEED_100:
1974 speed = 100;
1975 break;
1976 case PORT_SPEED_1000:
1977 speed = 1000;
1978 break;
1979 default:
1980 speed = -1;
1981 break;
1982 }
1983 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1984 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1985
1986 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
1987 speed, duplex ? "full" : "half", fc ? "en" : "dis");
1988
1989 if (!netif_carrier_ok(dev))
1990 netif_carrier_on(dev);
1991 }
1992
1993 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1994 {
1995 struct mv643xx_eth_private *mp;
1996 int work_done;
1997
1998 mp = container_of(napi, struct mv643xx_eth_private, napi);
1999
2000 if (unlikely(mp->oom)) {
2001 mp->oom = 0;
2002 del_timer(&mp->rx_oom);
2003 }
2004
2005 work_done = 0;
2006 while (work_done < budget) {
2007 u8 queue_mask;
2008 int queue;
2009 int work_tbd;
2010
2011 if (mp->work_link) {
2012 mp->work_link = 0;
2013 handle_link_event(mp);
2014 work_done++;
2015 continue;
2016 }
2017
2018 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2019 if (likely(!mp->oom))
2020 queue_mask |= mp->work_rx_refill;
2021
2022 if (!queue_mask) {
2023 if (mv643xx_eth_collect_events(mp))
2024 continue;
2025 break;
2026 }
2027
2028 queue = fls(queue_mask) - 1;
2029 queue_mask = 1 << queue;
2030
2031 work_tbd = budget - work_done;
2032 if (work_tbd > 16)
2033 work_tbd = 16;
2034
2035 if (mp->work_tx_end & queue_mask) {
2036 txq_kick(mp->txq + queue);
2037 } else if (mp->work_tx & queue_mask) {
2038 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2039 txq_maybe_wake(mp->txq + queue);
2040 } else if (mp->work_rx & queue_mask) {
2041 work_done += rxq_process(mp->rxq + queue, work_tbd);
2042 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2043 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2044 } else {
2045 BUG();
2046 }
2047 }
2048
2049 if (work_done < budget) {
2050 if (mp->oom)
2051 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2052 napi_complete(napi);
2053 wrlp(mp, INT_MASK, mp->int_mask);
2054 }
2055
2056 return work_done;
2057 }
2058
2059 static inline void oom_timer_wrapper(unsigned long data)
2060 {
2061 struct mv643xx_eth_private *mp = (void *)data;
2062
2063 napi_schedule(&mp->napi);
2064 }
2065
2066 static void phy_reset(struct mv643xx_eth_private *mp)
2067 {
2068 int data;
2069
2070 data = phy_read(mp->phy, MII_BMCR);
2071 if (data < 0)
2072 return;
2073
2074 data |= BMCR_RESET;
2075 if (phy_write(mp->phy, MII_BMCR, data) < 0)
2076 return;
2077
2078 do {
2079 data = phy_read(mp->phy, MII_BMCR);
2080 } while (data >= 0 && data & BMCR_RESET);
2081 }
2082
2083 static void port_start(struct mv643xx_eth_private *mp)
2084 {
2085 u32 pscr;
2086 int i;
2087
2088 /*
2089 * Perform PHY reset, if there is a PHY.
2090 */
2091 if (mp->phy != NULL) {
2092 struct ethtool_cmd cmd;
2093
2094 mv643xx_eth_get_settings(mp->dev, &cmd);
2095 phy_reset(mp);
2096 mv643xx_eth_set_settings(mp->dev, &cmd);
2097 }
2098
2099 /*
2100 * Configure basic link parameters.
2101 */
2102 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2103
2104 pscr |= SERIAL_PORT_ENABLE;
2105 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2106
2107 pscr |= DO_NOT_FORCE_LINK_FAIL;
2108 if (mp->phy == NULL)
2109 pscr |= FORCE_LINK_PASS;
2110 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2111
2112 /*
2113 * Configure TX path and queues.
2114 */
2115 tx_set_rate(mp, 1000000000, 16777216);
2116 for (i = 0; i < mp->txq_count; i++) {
2117 struct tx_queue *txq = mp->txq + i;
2118
2119 txq_reset_hw_ptr(txq);
2120 txq_set_rate(txq, 1000000000, 16777216);
2121 txq_set_fixed_prio_mode(txq);
2122 }
2123
2124 /*
2125 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2126 * frames to RX queue #0, and include the pseudo-header when
2127 * calculating receive checksums.
2128 */
2129 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2130
2131 /*
2132 * Treat BPDUs as normal multicasts, and disable partition mode.
2133 */
2134 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2135
2136 /*
2137 * Add configured unicast addresses to address filter table.
2138 */
2139 mv643xx_eth_program_unicast_filter(mp->dev);
2140
2141 /*
2142 * Enable the receive queues.
2143 */
2144 for (i = 0; i < mp->rxq_count; i++) {
2145 struct rx_queue *rxq = mp->rxq + i;
2146 u32 addr;
2147
2148 addr = (u32)rxq->rx_desc_dma;
2149 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2150 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2151
2152 rxq_enable(rxq);
2153 }
2154 }
2155
2156 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2157 {
2158 int skb_size;
2159
2160 /*
2161 * Reserve 2+14 bytes for an ethernet header (the hardware
2162 * automatically prepends 2 bytes of dummy data to each
2163 * received packet), 16 bytes for up to four VLAN tags, and
2164 * 4 bytes for the trailing FCS -- 36 bytes total.
2165 */
2166 skb_size = mp->dev->mtu + 36;
2167
2168 /*
2169 * Make sure that the skb size is a multiple of 8 bytes, as
2170 * the lower three bits of the receive descriptor's buffer
2171 * size field are ignored by the hardware.
2172 */
2173 mp->skb_size = (skb_size + 7) & ~7;
2174
2175 /*
2176 * If NET_SKB_PAD is smaller than a cache line,
2177 * netdev_alloc_skb() will cause skb->data to be misaligned
2178 * to a cache line boundary. If this is the case, include
2179 * some extra space to allow re-aligning the data area.
2180 */
2181 mp->skb_size += SKB_DMA_REALIGN;
2182 }
2183
2184 static int mv643xx_eth_open(struct net_device *dev)
2185 {
2186 struct mv643xx_eth_private *mp = netdev_priv(dev);
2187 int err;
2188 int i;
2189
2190 wrlp(mp, INT_CAUSE, 0);
2191 wrlp(mp, INT_CAUSE_EXT, 0);
2192 rdlp(mp, INT_CAUSE_EXT);
2193
2194 err = request_irq(dev->irq, mv643xx_eth_irq,
2195 IRQF_SHARED, dev->name, dev);
2196 if (err) {
2197 netdev_err(dev, "can't assign irq\n");
2198 return -EAGAIN;
2199 }
2200
2201 mv643xx_eth_recalc_skb_size(mp);
2202
2203 napi_enable(&mp->napi);
2204
2205 mp->int_mask = INT_EXT;
2206
2207 for (i = 0; i < mp->rxq_count; i++) {
2208 err = rxq_init(mp, i);
2209 if (err) {
2210 while (--i >= 0)
2211 rxq_deinit(mp->rxq + i);
2212 goto out;
2213 }
2214
2215 rxq_refill(mp->rxq + i, INT_MAX);
2216 mp->int_mask |= INT_RX_0 << i;
2217 }
2218
2219 if (mp->oom) {
2220 mp->rx_oom.expires = jiffies + (HZ / 10);
2221 add_timer(&mp->rx_oom);
2222 }
2223
2224 for (i = 0; i < mp->txq_count; i++) {
2225 err = txq_init(mp, i);
2226 if (err) {
2227 while (--i >= 0)
2228 txq_deinit(mp->txq + i);
2229 goto out_free;
2230 }
2231 mp->int_mask |= INT_TX_END_0 << i;
2232 }
2233
2234 port_start(mp);
2235
2236 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2237 wrlp(mp, INT_MASK, mp->int_mask);
2238
2239 return 0;
2240
2241
2242 out_free:
2243 for (i = 0; i < mp->rxq_count; i++)
2244 rxq_deinit(mp->rxq + i);
2245 out:
2246 free_irq(dev->irq, dev);
2247
2248 return err;
2249 }
2250
2251 static void port_reset(struct mv643xx_eth_private *mp)
2252 {
2253 unsigned int data;
2254 int i;
2255
2256 for (i = 0; i < mp->rxq_count; i++)
2257 rxq_disable(mp->rxq + i);
2258 for (i = 0; i < mp->txq_count; i++)
2259 txq_disable(mp->txq + i);
2260
2261 while (1) {
2262 u32 ps = rdlp(mp, PORT_STATUS);
2263
2264 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2265 break;
2266 udelay(10);
2267 }
2268
2269 /* Reset the Enable bit in the Configuration Register */
2270 data = rdlp(mp, PORT_SERIAL_CONTROL);
2271 data &= ~(SERIAL_PORT_ENABLE |
2272 DO_NOT_FORCE_LINK_FAIL |
2273 FORCE_LINK_PASS);
2274 wrlp(mp, PORT_SERIAL_CONTROL, data);
2275 }
2276
2277 static int mv643xx_eth_stop(struct net_device *dev)
2278 {
2279 struct mv643xx_eth_private *mp = netdev_priv(dev);
2280 int i;
2281
2282 wrlp(mp, INT_MASK_EXT, 0x00000000);
2283 wrlp(mp, INT_MASK, 0x00000000);
2284 rdlp(mp, INT_MASK);
2285
2286 napi_disable(&mp->napi);
2287
2288 del_timer_sync(&mp->rx_oom);
2289
2290 netif_carrier_off(dev);
2291
2292 free_irq(dev->irq, dev);
2293
2294 port_reset(mp);
2295 mv643xx_eth_get_stats(dev);
2296 mib_counters_update(mp);
2297 del_timer_sync(&mp->mib_counters_timer);
2298
2299 for (i = 0; i < mp->rxq_count; i++)
2300 rxq_deinit(mp->rxq + i);
2301 for (i = 0; i < mp->txq_count; i++)
2302 txq_deinit(mp->txq + i);
2303
2304 return 0;
2305 }
2306
2307 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2308 {
2309 struct mv643xx_eth_private *mp = netdev_priv(dev);
2310 int ret;
2311
2312 if (mp->phy == NULL)
2313 return -ENOTSUPP;
2314
2315 ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2316 if (!ret)
2317 mv643xx_adjust_pscr(mp);
2318 return ret;
2319 }
2320
2321 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2322 {
2323 struct mv643xx_eth_private *mp = netdev_priv(dev);
2324
2325 if (new_mtu < 64 || new_mtu > 9500)
2326 return -EINVAL;
2327
2328 dev->mtu = new_mtu;
2329 mv643xx_eth_recalc_skb_size(mp);
2330 tx_set_rate(mp, 1000000000, 16777216);
2331
2332 if (!netif_running(dev))
2333 return 0;
2334
2335 /*
2336 * Stop and then re-open the interface. This will allocate RX
2337 * skbs of the new MTU.
2338 * There is a possible danger that the open will not succeed,
2339 * due to memory being full.
2340 */
2341 mv643xx_eth_stop(dev);
2342 if (mv643xx_eth_open(dev)) {
2343 netdev_err(dev,
2344 "fatal error on re-opening device after MTU change\n");
2345 }
2346
2347 return 0;
2348 }
2349
2350 static void tx_timeout_task(struct work_struct *ugly)
2351 {
2352 struct mv643xx_eth_private *mp;
2353
2354 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2355 if (netif_running(mp->dev)) {
2356 netif_tx_stop_all_queues(mp->dev);
2357 port_reset(mp);
2358 port_start(mp);
2359 netif_tx_wake_all_queues(mp->dev);
2360 }
2361 }
2362
2363 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2364 {
2365 struct mv643xx_eth_private *mp = netdev_priv(dev);
2366
2367 netdev_info(dev, "tx timeout\n");
2368
2369 schedule_work(&mp->tx_timeout_task);
2370 }
2371
2372 #ifdef CONFIG_NET_POLL_CONTROLLER
2373 static void mv643xx_eth_netpoll(struct net_device *dev)
2374 {
2375 struct mv643xx_eth_private *mp = netdev_priv(dev);
2376
2377 wrlp(mp, INT_MASK, 0x00000000);
2378 rdlp(mp, INT_MASK);
2379
2380 mv643xx_eth_irq(dev->irq, dev);
2381
2382 wrlp(mp, INT_MASK, mp->int_mask);
2383 }
2384 #endif
2385
2386
2387 /* platform glue ************************************************************/
2388 static void
2389 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2390 const struct mbus_dram_target_info *dram)
2391 {
2392 void __iomem *base = msp->base;
2393 u32 win_enable;
2394 u32 win_protect;
2395 int i;
2396
2397 for (i = 0; i < 6; i++) {
2398 writel(0, base + WINDOW_BASE(i));
2399 writel(0, base + WINDOW_SIZE(i));
2400 if (i < 4)
2401 writel(0, base + WINDOW_REMAP_HIGH(i));
2402 }
2403
2404 win_enable = 0x3f;
2405 win_protect = 0;
2406
2407 for (i = 0; i < dram->num_cs; i++) {
2408 const struct mbus_dram_window *cs = dram->cs + i;
2409
2410 writel((cs->base & 0xffff0000) |
2411 (cs->mbus_attr << 8) |
2412 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2413 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2414
2415 win_enable &= ~(1 << i);
2416 win_protect |= 3 << (2 * i);
2417 }
2418
2419 writel(win_enable, base + WINDOW_BAR_ENABLE);
2420 msp->win_protect = win_protect;
2421 }
2422
2423 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2424 {
2425 /*
2426 * Check whether we have a 14-bit coal limit field in bits
2427 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2428 * SDMA config register.
2429 */
2430 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2431 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2432 msp->extended_rx_coal_limit = 1;
2433 else
2434 msp->extended_rx_coal_limit = 0;
2435
2436 /*
2437 * Check whether the MAC supports TX rate control, and if
2438 * yes, whether its associated registers are in the old or
2439 * the new place.
2440 */
2441 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2442 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2443 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2444 } else {
2445 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2446 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2447 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2448 else
2449 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2450 }
2451 }
2452
2453 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2454 {
2455 static int mv643xx_eth_version_printed;
2456 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2457 struct mv643xx_eth_shared_private *msp;
2458 const struct mbus_dram_target_info *dram;
2459 struct resource *res;
2460
2461 if (!mv643xx_eth_version_printed++)
2462 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2463 mv643xx_eth_driver_version);
2464
2465 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2466 if (res == NULL)
2467 return -EINVAL;
2468
2469 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2470 if (msp == NULL)
2471 return -ENOMEM;
2472
2473 msp->base = ioremap(res->start, resource_size(res));
2474 if (msp->base == NULL)
2475 return -ENOMEM;
2476
2477 msp->clk = devm_clk_get(&pdev->dev, NULL);
2478 if (!IS_ERR(msp->clk))
2479 clk_prepare_enable(msp->clk);
2480
2481 /*
2482 * (Re-)program MBUS remapping windows if we are asked to.
2483 */
2484 dram = mv_mbus_dram_info();
2485 if (dram)
2486 mv643xx_eth_conf_mbus_windows(msp, dram);
2487
2488 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2489 pd->tx_csum_limit : 9 * 1024;
2490 infer_hw_params(msp);
2491
2492 platform_set_drvdata(pdev, msp);
2493
2494 return 0;
2495 }
2496
2497 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2498 {
2499 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2500
2501 iounmap(msp->base);
2502 if (!IS_ERR(msp->clk))
2503 clk_disable_unprepare(msp->clk);
2504
2505 return 0;
2506 }
2507
2508 static struct platform_driver mv643xx_eth_shared_driver = {
2509 .probe = mv643xx_eth_shared_probe,
2510 .remove = mv643xx_eth_shared_remove,
2511 .driver = {
2512 .name = MV643XX_ETH_SHARED_NAME,
2513 .owner = THIS_MODULE,
2514 },
2515 };
2516
2517 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2518 {
2519 int addr_shift = 5 * mp->port_num;
2520 u32 data;
2521
2522 data = rdl(mp, PHY_ADDR);
2523 data &= ~(0x1f << addr_shift);
2524 data |= (phy_addr & 0x1f) << addr_shift;
2525 wrl(mp, PHY_ADDR, data);
2526 }
2527
2528 static int phy_addr_get(struct mv643xx_eth_private *mp)
2529 {
2530 unsigned int data;
2531
2532 data = rdl(mp, PHY_ADDR);
2533
2534 return (data >> (5 * mp->port_num)) & 0x1f;
2535 }
2536
2537 static void set_params(struct mv643xx_eth_private *mp,
2538 struct mv643xx_eth_platform_data *pd)
2539 {
2540 struct net_device *dev = mp->dev;
2541
2542 if (is_valid_ether_addr(pd->mac_addr))
2543 memcpy(dev->dev_addr, pd->mac_addr, 6);
2544 else
2545 uc_addr_get(mp, dev->dev_addr);
2546
2547 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2548 if (pd->rx_queue_size)
2549 mp->rx_ring_size = pd->rx_queue_size;
2550 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2551 mp->rx_desc_sram_size = pd->rx_sram_size;
2552
2553 mp->rxq_count = pd->rx_queue_count ? : 1;
2554
2555 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2556 if (pd->tx_queue_size)
2557 mp->tx_ring_size = pd->tx_queue_size;
2558 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2559 mp->tx_desc_sram_size = pd->tx_sram_size;
2560
2561 mp->txq_count = pd->tx_queue_count ? : 1;
2562 }
2563
2564 static void mv643xx_eth_adjust_link(struct net_device *dev)
2565 {
2566 struct mv643xx_eth_private *mp = netdev_priv(dev);
2567
2568 mv643xx_adjust_pscr(mp);
2569 }
2570
2571 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2572 int phy_addr)
2573 {
2574 struct phy_device *phydev;
2575 int start;
2576 int num;
2577 int i;
2578 char phy_id[MII_BUS_ID_SIZE + 3];
2579
2580 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2581 start = phy_addr_get(mp) & 0x1f;
2582 num = 32;
2583 } else {
2584 start = phy_addr & 0x1f;
2585 num = 1;
2586 }
2587
2588 /* Attempt to connect to the PHY using orion-mdio */
2589 phydev = ERR_PTR(-ENODEV);
2590 for (i = 0; i < num; i++) {
2591 int addr = (start + i) & 0x1f;
2592
2593 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2594 "orion-mdio-mii", addr);
2595
2596 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
2597 PHY_INTERFACE_MODE_GMII);
2598 if (!IS_ERR(phydev)) {
2599 phy_addr_set(mp, addr);
2600 break;
2601 }
2602 }
2603
2604 return phydev;
2605 }
2606
2607 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2608 {
2609 struct phy_device *phy = mp->phy;
2610
2611 phy_reset(mp);
2612
2613 if (speed == 0) {
2614 phy->autoneg = AUTONEG_ENABLE;
2615 phy->speed = 0;
2616 phy->duplex = 0;
2617 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2618 } else {
2619 phy->autoneg = AUTONEG_DISABLE;
2620 phy->advertising = 0;
2621 phy->speed = speed;
2622 phy->duplex = duplex;
2623 }
2624 phy_start_aneg(phy);
2625 }
2626
2627 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2628 {
2629 u32 pscr;
2630
2631 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2632 if (pscr & SERIAL_PORT_ENABLE) {
2633 pscr &= ~SERIAL_PORT_ENABLE;
2634 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2635 }
2636
2637 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2638 if (mp->phy == NULL) {
2639 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2640 if (speed == SPEED_1000)
2641 pscr |= SET_GMII_SPEED_TO_1000;
2642 else if (speed == SPEED_100)
2643 pscr |= SET_MII_SPEED_TO_100;
2644
2645 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2646
2647 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2648 if (duplex == DUPLEX_FULL)
2649 pscr |= SET_FULL_DUPLEX_MODE;
2650 }
2651
2652 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2653 }
2654
2655 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2656 .ndo_open = mv643xx_eth_open,
2657 .ndo_stop = mv643xx_eth_stop,
2658 .ndo_start_xmit = mv643xx_eth_xmit,
2659 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2660 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2661 .ndo_validate_addr = eth_validate_addr,
2662 .ndo_do_ioctl = mv643xx_eth_ioctl,
2663 .ndo_change_mtu = mv643xx_eth_change_mtu,
2664 .ndo_set_features = mv643xx_eth_set_features,
2665 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2666 .ndo_get_stats = mv643xx_eth_get_stats,
2667 #ifdef CONFIG_NET_POLL_CONTROLLER
2668 .ndo_poll_controller = mv643xx_eth_netpoll,
2669 #endif
2670 };
2671
2672 static int mv643xx_eth_probe(struct platform_device *pdev)
2673 {
2674 struct mv643xx_eth_platform_data *pd;
2675 struct mv643xx_eth_private *mp;
2676 struct net_device *dev;
2677 struct resource *res;
2678 int err;
2679
2680 pd = pdev->dev.platform_data;
2681 if (pd == NULL) {
2682 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
2683 return -ENODEV;
2684 }
2685
2686 if (pd->shared == NULL) {
2687 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
2688 return -ENODEV;
2689 }
2690
2691 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2692 if (!dev)
2693 return -ENOMEM;
2694
2695 mp = netdev_priv(dev);
2696 platform_set_drvdata(pdev, mp);
2697
2698 mp->shared = platform_get_drvdata(pd->shared);
2699 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2700 mp->port_num = pd->port_number;
2701
2702 mp->dev = dev;
2703
2704 /*
2705 * Start with a default rate, and if there is a clock, allow
2706 * it to override the default.
2707 */
2708 mp->t_clk = 133000000;
2709 mp->clk = devm_clk_get(&pdev->dev, NULL);
2710 if (!IS_ERR(mp->clk)) {
2711 clk_prepare_enable(mp->clk);
2712 mp->t_clk = clk_get_rate(mp->clk);
2713 }
2714
2715 set_params(mp, pd);
2716 netif_set_real_num_tx_queues(dev, mp->txq_count);
2717 netif_set_real_num_rx_queues(dev, mp->rxq_count);
2718
2719 if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
2720 mp->phy = phy_scan(mp, pd->phy_addr);
2721
2722 if (IS_ERR(mp->phy)) {
2723 err = PTR_ERR(mp->phy);
2724 if (err == -ENODEV)
2725 err = -EPROBE_DEFER;
2726 goto out;
2727 }
2728 phy_init(mp, pd->speed, pd->duplex);
2729 }
2730
2731 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2732
2733 init_pscr(mp, pd->speed, pd->duplex);
2734
2735
2736 mib_counters_clear(mp);
2737
2738 init_timer(&mp->mib_counters_timer);
2739 mp->mib_counters_timer.data = (unsigned long)mp;
2740 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2741 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2742 add_timer(&mp->mib_counters_timer);
2743
2744 spin_lock_init(&mp->mib_counters_lock);
2745
2746 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2747
2748 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
2749
2750 init_timer(&mp->rx_oom);
2751 mp->rx_oom.data = (unsigned long)mp;
2752 mp->rx_oom.function = oom_timer_wrapper;
2753
2754
2755 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2756 BUG_ON(!res);
2757 dev->irq = res->start;
2758
2759 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2760
2761 dev->watchdog_timeo = 2 * HZ;
2762 dev->base_addr = 0;
2763
2764 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
2765 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
2766 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2767
2768 dev->priv_flags |= IFF_UNICAST_FLT;
2769
2770 SET_NETDEV_DEV(dev, &pdev->dev);
2771
2772 if (mp->shared->win_protect)
2773 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2774
2775 netif_carrier_off(dev);
2776
2777 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2778
2779 set_rx_coal(mp, 250);
2780 set_tx_coal(mp, 0);
2781
2782 err = register_netdev(dev);
2783 if (err)
2784 goto out;
2785
2786 netdev_notice(dev, "port %d with MAC address %pM\n",
2787 mp->port_num, dev->dev_addr);
2788
2789 if (mp->tx_desc_sram_size > 0)
2790 netdev_notice(dev, "configured with sram\n");
2791
2792 return 0;
2793
2794 out:
2795 if (!IS_ERR(mp->clk))
2796 clk_disable_unprepare(mp->clk);
2797 free_netdev(dev);
2798
2799 return err;
2800 }
2801
2802 static int mv643xx_eth_remove(struct platform_device *pdev)
2803 {
2804 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2805
2806 unregister_netdev(mp->dev);
2807 if (mp->phy != NULL)
2808 phy_detach(mp->phy);
2809 cancel_work_sync(&mp->tx_timeout_task);
2810
2811 if (!IS_ERR(mp->clk))
2812 clk_disable_unprepare(mp->clk);
2813
2814 free_netdev(mp->dev);
2815
2816 platform_set_drvdata(pdev, NULL);
2817
2818 return 0;
2819 }
2820
2821 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2822 {
2823 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2824
2825 /* Mask all interrupts on ethernet port */
2826 wrlp(mp, INT_MASK, 0);
2827 rdlp(mp, INT_MASK);
2828
2829 if (netif_running(mp->dev))
2830 port_reset(mp);
2831 }
2832
2833 static struct platform_driver mv643xx_eth_driver = {
2834 .probe = mv643xx_eth_probe,
2835 .remove = mv643xx_eth_remove,
2836 .shutdown = mv643xx_eth_shutdown,
2837 .driver = {
2838 .name = MV643XX_ETH_NAME,
2839 .owner = THIS_MODULE,
2840 },
2841 };
2842
2843 static int __init mv643xx_eth_init_module(void)
2844 {
2845 int rc;
2846
2847 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2848 if (!rc) {
2849 rc = platform_driver_register(&mv643xx_eth_driver);
2850 if (rc)
2851 platform_driver_unregister(&mv643xx_eth_shared_driver);
2852 }
2853
2854 return rc;
2855 }
2856 module_init(mv643xx_eth_init_module);
2857
2858 static void __exit mv643xx_eth_cleanup_module(void)
2859 {
2860 platform_driver_unregister(&mv643xx_eth_driver);
2861 platform_driver_unregister(&mv643xx_eth_shared_driver);
2862 }
2863 module_exit(mv643xx_eth_cleanup_module);
2864
2865 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2866 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2867 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2868 MODULE_LICENSE("GPL");
2869 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2870 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
kernel source for telekom puls (alcatel/mediatek)