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[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2015 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/types.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/vmalloc.h>
34 #include <linux/string.h>
35 #include <linux/in.h>
36 #include <linux/interrupt.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/sctp.h>
40 #include <linux/pkt_sched.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/etherdevice.h>
46 #include <linux/ethtool.h>
47 #include <linux/if.h>
48 #include <linux/if_vlan.h>
49 #include <linux/if_macvlan.h>
50 #include <linux/if_bridge.h>
51 #include <linux/prefetch.h>
52 #include <scsi/fc/fc_fcoe.h>
53 #include <net/vxlan.h>
54
55 #ifdef CONFIG_OF
56 #include <linux/of_net.h>
57 #endif
58
59 #ifdef CONFIG_SPARC
60 #include <asm/idprom.h>
61 #include <asm/prom.h>
62 #endif
63
64 #include "ixgbe.h"
65 #include "ixgbe_common.h"
66 #include "ixgbe_dcb_82599.h"
67 #include "ixgbe_sriov.h"
68 #ifdef CONFIG_IXGBE_VXLAN
69 #include <net/vxlan.h>
70 #endif
71
72 char ixgbe_driver_name[] = "ixgbe";
73 static const char ixgbe_driver_string[] =
74 "Intel(R) 10 Gigabit PCI Express Network Driver";
75 #ifdef IXGBE_FCOE
76 char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
78 #else
79 static char ixgbe_default_device_descr[] =
80 "Intel(R) 10 Gigabit Network Connection";
81 #endif
82 #define DRV_VERSION "4.2.1-k"
83 const char ixgbe_driver_version[] = DRV_VERSION;
84 static const char ixgbe_copyright[] =
85 "Copyright (c) 1999-2015 Intel Corporation.";
86
87 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
88
89 static const struct ixgbe_info *ixgbe_info_tbl[] = {
90 [board_82598] = &ixgbe_82598_info,
91 [board_82599] = &ixgbe_82599_info,
92 [board_X540] = &ixgbe_X540_info,
93 [board_X550] = &ixgbe_X550_info,
94 [board_X550EM_x] = &ixgbe_X550EM_x_info,
95 };
96
97 /* ixgbe_pci_tbl - PCI Device ID Table
98 *
99 * Wildcard entries (PCI_ANY_ID) should come last
100 * Last entry must be all 0s
101 *
102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
103 * Class, Class Mask, private data (not used) }
104 */
105 static const struct pci_device_id ixgbe_pci_tbl[] = {
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
141 /* required last entry */
142 {0, }
143 };
144 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
145
146 #ifdef CONFIG_IXGBE_DCA
147 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
148 void *p);
149 static struct notifier_block dca_notifier = {
150 .notifier_call = ixgbe_notify_dca,
151 .next = NULL,
152 .priority = 0
153 };
154 #endif
155
156 #ifdef CONFIG_PCI_IOV
157 static unsigned int max_vfs;
158 module_param(max_vfs, uint, 0);
159 MODULE_PARM_DESC(max_vfs,
160 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
161 #endif /* CONFIG_PCI_IOV */
162
163 static unsigned int allow_unsupported_sfp;
164 module_param(allow_unsupported_sfp, uint, 0);
165 MODULE_PARM_DESC(allow_unsupported_sfp,
166 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
167
168 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
169 static int debug = -1;
170 module_param(debug, int, 0);
171 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
172
173 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
174 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
175 MODULE_LICENSE("GPL");
176 MODULE_VERSION(DRV_VERSION);
177
178 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
179
180 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
181 u32 reg, u16 *value)
182 {
183 struct pci_dev *parent_dev;
184 struct pci_bus *parent_bus;
185
186 parent_bus = adapter->pdev->bus->parent;
187 if (!parent_bus)
188 return -1;
189
190 parent_dev = parent_bus->self;
191 if (!parent_dev)
192 return -1;
193
194 if (!pci_is_pcie(parent_dev))
195 return -1;
196
197 pcie_capability_read_word(parent_dev, reg, value);
198 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
199 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
200 return -1;
201 return 0;
202 }
203
204 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
205 {
206 struct ixgbe_hw *hw = &adapter->hw;
207 u16 link_status = 0;
208 int err;
209
210 hw->bus.type = ixgbe_bus_type_pci_express;
211
212 /* Get the negotiated link width and speed from PCI config space of the
213 * parent, as this device is behind a switch
214 */
215 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
216
217 /* assume caller will handle error case */
218 if (err)
219 return err;
220
221 hw->bus.width = ixgbe_convert_bus_width(link_status);
222 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
223
224 return 0;
225 }
226
227 /**
228 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
229 * @hw: hw specific details
230 *
231 * This function is used by probe to determine whether a device's PCI-Express
232 * bandwidth details should be gathered from the parent bus instead of from the
233 * device. Used to ensure that various locations all have the correct device ID
234 * checks.
235 */
236 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
237 {
238 switch (hw->device_id) {
239 case IXGBE_DEV_ID_82599_SFP_SF_QP:
240 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
241 return true;
242 default:
243 return false;
244 }
245 }
246
247 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
248 int expected_gts)
249 {
250 struct ixgbe_hw *hw = &adapter->hw;
251 int max_gts = 0;
252 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
253 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
254 struct pci_dev *pdev;
255
256 /* Some devices are not connected over PCIe and thus do not negotiate
257 * speed. These devices do not have valid bus info, and thus any report
258 * we generate may not be correct.
259 */
260 if (hw->bus.type == ixgbe_bus_type_internal)
261 return;
262
263 /* determine whether to use the parent device */
264 if (ixgbe_pcie_from_parent(&adapter->hw))
265 pdev = adapter->pdev->bus->parent->self;
266 else
267 pdev = adapter->pdev;
268
269 if (pcie_get_minimum_link(pdev, &speed, &width) ||
270 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
271 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
272 return;
273 }
274
275 switch (speed) {
276 case PCIE_SPEED_2_5GT:
277 /* 8b/10b encoding reduces max throughput by 20% */
278 max_gts = 2 * width;
279 break;
280 case PCIE_SPEED_5_0GT:
281 /* 8b/10b encoding reduces max throughput by 20% */
282 max_gts = 4 * width;
283 break;
284 case PCIE_SPEED_8_0GT:
285 /* 128b/130b encoding reduces throughput by less than 2% */
286 max_gts = 8 * width;
287 break;
288 default:
289 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
290 return;
291 }
292
293 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
294 max_gts);
295 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
296 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
297 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
298 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
299 "Unknown"),
300 width,
301 (speed == PCIE_SPEED_2_5GT ? "20%" :
302 speed == PCIE_SPEED_5_0GT ? "20%" :
303 speed == PCIE_SPEED_8_0GT ? "<2%" :
304 "Unknown"));
305
306 if (max_gts < expected_gts) {
307 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
308 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
309 expected_gts);
310 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
311 }
312 }
313
314 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
315 {
316 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
317 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
318 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
319 schedule_work(&adapter->service_task);
320 }
321
322 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
323 {
324 struct ixgbe_adapter *adapter = hw->back;
325
326 if (!hw->hw_addr)
327 return;
328 hw->hw_addr = NULL;
329 e_dev_err("Adapter removed\n");
330 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
331 ixgbe_service_event_schedule(adapter);
332 }
333
334 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
335 {
336 u32 value;
337
338 /* The following check not only optimizes a bit by not
339 * performing a read on the status register when the
340 * register just read was a status register read that
341 * returned IXGBE_FAILED_READ_REG. It also blocks any
342 * potential recursion.
343 */
344 if (reg == IXGBE_STATUS) {
345 ixgbe_remove_adapter(hw);
346 return;
347 }
348 value = ixgbe_read_reg(hw, IXGBE_STATUS);
349 if (value == IXGBE_FAILED_READ_REG)
350 ixgbe_remove_adapter(hw);
351 }
352
353 /**
354 * ixgbe_read_reg - Read from device register
355 * @hw: hw specific details
356 * @reg: offset of register to read
357 *
358 * Returns : value read or IXGBE_FAILED_READ_REG if removed
359 *
360 * This function is used to read device registers. It checks for device
361 * removal by confirming any read that returns all ones by checking the
362 * status register value for all ones. This function avoids reading from
363 * the hardware if a removal was previously detected in which case it
364 * returns IXGBE_FAILED_READ_REG (all ones).
365 */
366 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
367 {
368 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
369 u32 value;
370
371 if (ixgbe_removed(reg_addr))
372 return IXGBE_FAILED_READ_REG;
373 value = readl(reg_addr + reg);
374 if (unlikely(value == IXGBE_FAILED_READ_REG))
375 ixgbe_check_remove(hw, reg);
376 return value;
377 }
378
379 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
380 {
381 u16 value;
382
383 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
384 if (value == IXGBE_FAILED_READ_CFG_WORD) {
385 ixgbe_remove_adapter(hw);
386 return true;
387 }
388 return false;
389 }
390
391 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
392 {
393 struct ixgbe_adapter *adapter = hw->back;
394 u16 value;
395
396 if (ixgbe_removed(hw->hw_addr))
397 return IXGBE_FAILED_READ_CFG_WORD;
398 pci_read_config_word(adapter->pdev, reg, &value);
399 if (value == IXGBE_FAILED_READ_CFG_WORD &&
400 ixgbe_check_cfg_remove(hw, adapter->pdev))
401 return IXGBE_FAILED_READ_CFG_WORD;
402 return value;
403 }
404
405 #ifdef CONFIG_PCI_IOV
406 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
407 {
408 struct ixgbe_adapter *adapter = hw->back;
409 u32 value;
410
411 if (ixgbe_removed(hw->hw_addr))
412 return IXGBE_FAILED_READ_CFG_DWORD;
413 pci_read_config_dword(adapter->pdev, reg, &value);
414 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
415 ixgbe_check_cfg_remove(hw, adapter->pdev))
416 return IXGBE_FAILED_READ_CFG_DWORD;
417 return value;
418 }
419 #endif /* CONFIG_PCI_IOV */
420
421 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
422 {
423 struct ixgbe_adapter *adapter = hw->back;
424
425 if (ixgbe_removed(hw->hw_addr))
426 return;
427 pci_write_config_word(adapter->pdev, reg, value);
428 }
429
430 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
431 {
432 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
433
434 /* flush memory to make sure state is correct before next watchdog */
435 smp_mb__before_atomic();
436 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
437 }
438
439 struct ixgbe_reg_info {
440 u32 ofs;
441 char *name;
442 };
443
444 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
445
446 /* General Registers */
447 {IXGBE_CTRL, "CTRL"},
448 {IXGBE_STATUS, "STATUS"},
449 {IXGBE_CTRL_EXT, "CTRL_EXT"},
450
451 /* Interrupt Registers */
452 {IXGBE_EICR, "EICR"},
453
454 /* RX Registers */
455 {IXGBE_SRRCTL(0), "SRRCTL"},
456 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
457 {IXGBE_RDLEN(0), "RDLEN"},
458 {IXGBE_RDH(0), "RDH"},
459 {IXGBE_RDT(0), "RDT"},
460 {IXGBE_RXDCTL(0), "RXDCTL"},
461 {IXGBE_RDBAL(0), "RDBAL"},
462 {IXGBE_RDBAH(0), "RDBAH"},
463
464 /* TX Registers */
465 {IXGBE_TDBAL(0), "TDBAL"},
466 {IXGBE_TDBAH(0), "TDBAH"},
467 {IXGBE_TDLEN(0), "TDLEN"},
468 {IXGBE_TDH(0), "TDH"},
469 {IXGBE_TDT(0), "TDT"},
470 {IXGBE_TXDCTL(0), "TXDCTL"},
471
472 /* List Terminator */
473 { .name = NULL }
474 };
475
476
477 /*
478 * ixgbe_regdump - register printout routine
479 */
480 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
481 {
482 int i = 0, j = 0;
483 char rname[16];
484 u32 regs[64];
485
486 switch (reginfo->ofs) {
487 case IXGBE_SRRCTL(0):
488 for (i = 0; i < 64; i++)
489 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
490 break;
491 case IXGBE_DCA_RXCTRL(0):
492 for (i = 0; i < 64; i++)
493 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
494 break;
495 case IXGBE_RDLEN(0):
496 for (i = 0; i < 64; i++)
497 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
498 break;
499 case IXGBE_RDH(0):
500 for (i = 0; i < 64; i++)
501 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
502 break;
503 case IXGBE_RDT(0):
504 for (i = 0; i < 64; i++)
505 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
506 break;
507 case IXGBE_RXDCTL(0):
508 for (i = 0; i < 64; i++)
509 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
510 break;
511 case IXGBE_RDBAL(0):
512 for (i = 0; i < 64; i++)
513 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
514 break;
515 case IXGBE_RDBAH(0):
516 for (i = 0; i < 64; i++)
517 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
518 break;
519 case IXGBE_TDBAL(0):
520 for (i = 0; i < 64; i++)
521 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
522 break;
523 case IXGBE_TDBAH(0):
524 for (i = 0; i < 64; i++)
525 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
526 break;
527 case IXGBE_TDLEN(0):
528 for (i = 0; i < 64; i++)
529 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
530 break;
531 case IXGBE_TDH(0):
532 for (i = 0; i < 64; i++)
533 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
534 break;
535 case IXGBE_TDT(0):
536 for (i = 0; i < 64; i++)
537 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
538 break;
539 case IXGBE_TXDCTL(0):
540 for (i = 0; i < 64; i++)
541 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
542 break;
543 default:
544 pr_info("%-15s %08x\n", reginfo->name,
545 IXGBE_READ_REG(hw, reginfo->ofs));
546 return;
547 }
548
549 for (i = 0; i < 8; i++) {
550 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
551 pr_err("%-15s", rname);
552 for (j = 0; j < 8; j++)
553 pr_cont(" %08x", regs[i*8+j]);
554 pr_cont("\n");
555 }
556
557 }
558
559 /*
560 * ixgbe_dump - Print registers, tx-rings and rx-rings
561 */
562 static void ixgbe_dump(struct ixgbe_adapter *adapter)
563 {
564 struct net_device *netdev = adapter->netdev;
565 struct ixgbe_hw *hw = &adapter->hw;
566 struct ixgbe_reg_info *reginfo;
567 int n = 0;
568 struct ixgbe_ring *tx_ring;
569 struct ixgbe_tx_buffer *tx_buffer;
570 union ixgbe_adv_tx_desc *tx_desc;
571 struct my_u0 { u64 a; u64 b; } *u0;
572 struct ixgbe_ring *rx_ring;
573 union ixgbe_adv_rx_desc *rx_desc;
574 struct ixgbe_rx_buffer *rx_buffer_info;
575 u32 staterr;
576 int i = 0;
577
578 if (!netif_msg_hw(adapter))
579 return;
580
581 /* Print netdevice Info */
582 if (netdev) {
583 dev_info(&adapter->pdev->dev, "Net device Info\n");
584 pr_info("Device Name state "
585 "trans_start last_rx\n");
586 pr_info("%-15s %016lX %016lX %016lX\n",
587 netdev->name,
588 netdev->state,
589 netdev->trans_start,
590 netdev->last_rx);
591 }
592
593 /* Print Registers */
594 dev_info(&adapter->pdev->dev, "Register Dump\n");
595 pr_info(" Register Name Value\n");
596 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
597 reginfo->name; reginfo++) {
598 ixgbe_regdump(hw, reginfo);
599 }
600
601 /* Print TX Ring Summary */
602 if (!netdev || !netif_running(netdev))
603 return;
604
605 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
606 pr_info(" %s %s %s %s\n",
607 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
608 "leng", "ntw", "timestamp");
609 for (n = 0; n < adapter->num_tx_queues; n++) {
610 tx_ring = adapter->tx_ring[n];
611 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
612 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
613 n, tx_ring->next_to_use, tx_ring->next_to_clean,
614 (u64)dma_unmap_addr(tx_buffer, dma),
615 dma_unmap_len(tx_buffer, len),
616 tx_buffer->next_to_watch,
617 (u64)tx_buffer->time_stamp);
618 }
619
620 /* Print TX Rings */
621 if (!netif_msg_tx_done(adapter))
622 goto rx_ring_summary;
623
624 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
625
626 /* Transmit Descriptor Formats
627 *
628 * 82598 Advanced Transmit Descriptor
629 * +--------------------------------------------------------------+
630 * 0 | Buffer Address [63:0] |
631 * +--------------------------------------------------------------+
632 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
633 * +--------------------------------------------------------------+
634 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
635 *
636 * 82598 Advanced Transmit Descriptor (Write-Back Format)
637 * +--------------------------------------------------------------+
638 * 0 | RSV [63:0] |
639 * +--------------------------------------------------------------+
640 * 8 | RSV | STA | NXTSEQ |
641 * +--------------------------------------------------------------+
642 * 63 36 35 32 31 0
643 *
644 * 82599+ Advanced Transmit Descriptor
645 * +--------------------------------------------------------------+
646 * 0 | Buffer Address [63:0] |
647 * +--------------------------------------------------------------+
648 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
649 * +--------------------------------------------------------------+
650 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
651 *
652 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
653 * +--------------------------------------------------------------+
654 * 0 | RSV [63:0] |
655 * +--------------------------------------------------------------+
656 * 8 | RSV | STA | RSV |
657 * +--------------------------------------------------------------+
658 * 63 36 35 32 31 0
659 */
660
661 for (n = 0; n < adapter->num_tx_queues; n++) {
662 tx_ring = adapter->tx_ring[n];
663 pr_info("------------------------------------\n");
664 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
665 pr_info("------------------------------------\n");
666 pr_info("%s%s %s %s %s %s\n",
667 "T [desc] [address 63:0 ] ",
668 "[PlPOIdStDDt Ln] [bi->dma ] ",
669 "leng", "ntw", "timestamp", "bi->skb");
670
671 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
672 tx_desc = IXGBE_TX_DESC(tx_ring, i);
673 tx_buffer = &tx_ring->tx_buffer_info[i];
674 u0 = (struct my_u0 *)tx_desc;
675 if (dma_unmap_len(tx_buffer, len) > 0) {
676 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
677 i,
678 le64_to_cpu(u0->a),
679 le64_to_cpu(u0->b),
680 (u64)dma_unmap_addr(tx_buffer, dma),
681 dma_unmap_len(tx_buffer, len),
682 tx_buffer->next_to_watch,
683 (u64)tx_buffer->time_stamp,
684 tx_buffer->skb);
685 if (i == tx_ring->next_to_use &&
686 i == tx_ring->next_to_clean)
687 pr_cont(" NTC/U\n");
688 else if (i == tx_ring->next_to_use)
689 pr_cont(" NTU\n");
690 else if (i == tx_ring->next_to_clean)
691 pr_cont(" NTC\n");
692 else
693 pr_cont("\n");
694
695 if (netif_msg_pktdata(adapter) &&
696 tx_buffer->skb)
697 print_hex_dump(KERN_INFO, "",
698 DUMP_PREFIX_ADDRESS, 16, 1,
699 tx_buffer->skb->data,
700 dma_unmap_len(tx_buffer, len),
701 true);
702 }
703 }
704 }
705
706 /* Print RX Rings Summary */
707 rx_ring_summary:
708 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
709 pr_info("Queue [NTU] [NTC]\n");
710 for (n = 0; n < adapter->num_rx_queues; n++) {
711 rx_ring = adapter->rx_ring[n];
712 pr_info("%5d %5X %5X\n",
713 n, rx_ring->next_to_use, rx_ring->next_to_clean);
714 }
715
716 /* Print RX Rings */
717 if (!netif_msg_rx_status(adapter))
718 return;
719
720 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
721
722 /* Receive Descriptor Formats
723 *
724 * 82598 Advanced Receive Descriptor (Read) Format
725 * 63 1 0
726 * +-----------------------------------------------------+
727 * 0 | Packet Buffer Address [63:1] |A0/NSE|
728 * +----------------------------------------------+------+
729 * 8 | Header Buffer Address [63:1] | DD |
730 * +-----------------------------------------------------+
731 *
732 *
733 * 82598 Advanced Receive Descriptor (Write-Back) Format
734 *
735 * 63 48 47 32 31 30 21 20 16 15 4 3 0
736 * +------------------------------------------------------+
737 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
738 * | Packet | IP | | | | Type | Type |
739 * | Checksum | Ident | | | | | |
740 * +------------------------------------------------------+
741 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
742 * +------------------------------------------------------+
743 * 63 48 47 32 31 20 19 0
744 *
745 * 82599+ Advanced Receive Descriptor (Read) Format
746 * 63 1 0
747 * +-----------------------------------------------------+
748 * 0 | Packet Buffer Address [63:1] |A0/NSE|
749 * +----------------------------------------------+------+
750 * 8 | Header Buffer Address [63:1] | DD |
751 * +-----------------------------------------------------+
752 *
753 *
754 * 82599+ Advanced Receive Descriptor (Write-Back) Format
755 *
756 * 63 48 47 32 31 30 21 20 17 16 4 3 0
757 * +------------------------------------------------------+
758 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
759 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
760 * |/ Flow Dir Flt ID | | | | | |
761 * +------------------------------------------------------+
762 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
763 * +------------------------------------------------------+
764 * 63 48 47 32 31 20 19 0
765 */
766
767 for (n = 0; n < adapter->num_rx_queues; n++) {
768 rx_ring = adapter->rx_ring[n];
769 pr_info("------------------------------------\n");
770 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
771 pr_info("------------------------------------\n");
772 pr_info("%s%s%s",
773 "R [desc] [ PktBuf A0] ",
774 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
775 "<-- Adv Rx Read format\n");
776 pr_info("%s%s%s",
777 "RWB[desc] [PcsmIpSHl PtRs] ",
778 "[vl er S cks ln] ---------------- [bi->skb ] ",
779 "<-- Adv Rx Write-Back format\n");
780
781 for (i = 0; i < rx_ring->count; i++) {
782 rx_buffer_info = &rx_ring->rx_buffer_info[i];
783 rx_desc = IXGBE_RX_DESC(rx_ring, i);
784 u0 = (struct my_u0 *)rx_desc;
785 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
786 if (staterr & IXGBE_RXD_STAT_DD) {
787 /* Descriptor Done */
788 pr_info("RWB[0x%03X] %016llX "
789 "%016llX ---------------- %p", i,
790 le64_to_cpu(u0->a),
791 le64_to_cpu(u0->b),
792 rx_buffer_info->skb);
793 } else {
794 pr_info("R [0x%03X] %016llX "
795 "%016llX %016llX %p", i,
796 le64_to_cpu(u0->a),
797 le64_to_cpu(u0->b),
798 (u64)rx_buffer_info->dma,
799 rx_buffer_info->skb);
800
801 if (netif_msg_pktdata(adapter) &&
802 rx_buffer_info->dma) {
803 print_hex_dump(KERN_INFO, "",
804 DUMP_PREFIX_ADDRESS, 16, 1,
805 page_address(rx_buffer_info->page) +
806 rx_buffer_info->page_offset,
807 ixgbe_rx_bufsz(rx_ring), true);
808 }
809 }
810
811 if (i == rx_ring->next_to_use)
812 pr_cont(" NTU\n");
813 else if (i == rx_ring->next_to_clean)
814 pr_cont(" NTC\n");
815 else
816 pr_cont("\n");
817
818 }
819 }
820 }
821
822 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
823 {
824 u32 ctrl_ext;
825
826 /* Let firmware take over control of h/w */
827 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
828 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
829 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
830 }
831
832 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
833 {
834 u32 ctrl_ext;
835
836 /* Let firmware know the driver has taken over */
837 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
838 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
839 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
840 }
841
842 /**
843 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
844 * @adapter: pointer to adapter struct
845 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
846 * @queue: queue to map the corresponding interrupt to
847 * @msix_vector: the vector to map to the corresponding queue
848 *
849 */
850 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
851 u8 queue, u8 msix_vector)
852 {
853 u32 ivar, index;
854 struct ixgbe_hw *hw = &adapter->hw;
855 switch (hw->mac.type) {
856 case ixgbe_mac_82598EB:
857 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
858 if (direction == -1)
859 direction = 0;
860 index = (((direction * 64) + queue) >> 2) & 0x1F;
861 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
862 ivar &= ~(0xFF << (8 * (queue & 0x3)));
863 ivar |= (msix_vector << (8 * (queue & 0x3)));
864 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
865 break;
866 case ixgbe_mac_82599EB:
867 case ixgbe_mac_X540:
868 case ixgbe_mac_X550:
869 case ixgbe_mac_X550EM_x:
870 if (direction == -1) {
871 /* other causes */
872 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
873 index = ((queue & 1) * 8);
874 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
875 ivar &= ~(0xFF << index);
876 ivar |= (msix_vector << index);
877 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
878 break;
879 } else {
880 /* tx or rx causes */
881 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
882 index = ((16 * (queue & 1)) + (8 * direction));
883 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
884 ivar &= ~(0xFF << index);
885 ivar |= (msix_vector << index);
886 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
887 break;
888 }
889 default:
890 break;
891 }
892 }
893
894 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
895 u64 qmask)
896 {
897 u32 mask;
898
899 switch (adapter->hw.mac.type) {
900 case ixgbe_mac_82598EB:
901 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
902 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
903 break;
904 case ixgbe_mac_82599EB:
905 case ixgbe_mac_X540:
906 case ixgbe_mac_X550:
907 case ixgbe_mac_X550EM_x:
908 mask = (qmask & 0xFFFFFFFF);
909 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
910 mask = (qmask >> 32);
911 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
912 break;
913 default:
914 break;
915 }
916 }
917
918 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
919 struct ixgbe_tx_buffer *tx_buffer)
920 {
921 if (tx_buffer->skb) {
922 dev_kfree_skb_any(tx_buffer->skb);
923 if (dma_unmap_len(tx_buffer, len))
924 dma_unmap_single(ring->dev,
925 dma_unmap_addr(tx_buffer, dma),
926 dma_unmap_len(tx_buffer, len),
927 DMA_TO_DEVICE);
928 } else if (dma_unmap_len(tx_buffer, len)) {
929 dma_unmap_page(ring->dev,
930 dma_unmap_addr(tx_buffer, dma),
931 dma_unmap_len(tx_buffer, len),
932 DMA_TO_DEVICE);
933 }
934 tx_buffer->next_to_watch = NULL;
935 tx_buffer->skb = NULL;
936 dma_unmap_len_set(tx_buffer, len, 0);
937 /* tx_buffer must be completely set up in the transmit path */
938 }
939
940 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
941 {
942 struct ixgbe_hw *hw = &adapter->hw;
943 struct ixgbe_hw_stats *hwstats = &adapter->stats;
944 int i;
945 u32 data;
946
947 if ((hw->fc.current_mode != ixgbe_fc_full) &&
948 (hw->fc.current_mode != ixgbe_fc_rx_pause))
949 return;
950
951 switch (hw->mac.type) {
952 case ixgbe_mac_82598EB:
953 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
954 break;
955 default:
956 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
957 }
958 hwstats->lxoffrxc += data;
959
960 /* refill credits (no tx hang) if we received xoff */
961 if (!data)
962 return;
963
964 for (i = 0; i < adapter->num_tx_queues; i++)
965 clear_bit(__IXGBE_HANG_CHECK_ARMED,
966 &adapter->tx_ring[i]->state);
967 }
968
969 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
970 {
971 struct ixgbe_hw *hw = &adapter->hw;
972 struct ixgbe_hw_stats *hwstats = &adapter->stats;
973 u32 xoff[8] = {0};
974 u8 tc;
975 int i;
976 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
977
978 if (adapter->ixgbe_ieee_pfc)
979 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
980
981 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
982 ixgbe_update_xoff_rx_lfc(adapter);
983 return;
984 }
985
986 /* update stats for each tc, only valid with PFC enabled */
987 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
988 u32 pxoffrxc;
989
990 switch (hw->mac.type) {
991 case ixgbe_mac_82598EB:
992 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
993 break;
994 default:
995 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
996 }
997 hwstats->pxoffrxc[i] += pxoffrxc;
998 /* Get the TC for given UP */
999 tc = netdev_get_prio_tc_map(adapter->netdev, i);
1000 xoff[tc] += pxoffrxc;
1001 }
1002
1003 /* disarm tx queues that have received xoff frames */
1004 for (i = 0; i < adapter->num_tx_queues; i++) {
1005 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
1006
1007 tc = tx_ring->dcb_tc;
1008 if (xoff[tc])
1009 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1010 }
1011 }
1012
1013 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
1014 {
1015 return ring->stats.packets;
1016 }
1017
1018 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1019 {
1020 struct ixgbe_adapter *adapter;
1021 struct ixgbe_hw *hw;
1022 u32 head, tail;
1023
1024 if (ring->l2_accel_priv)
1025 adapter = ring->l2_accel_priv->real_adapter;
1026 else
1027 adapter = netdev_priv(ring->netdev);
1028
1029 hw = &adapter->hw;
1030 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1031 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
1032
1033 if (head != tail)
1034 return (head < tail) ?
1035 tail - head : (tail + ring->count - head);
1036
1037 return 0;
1038 }
1039
1040 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1041 {
1042 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1043 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1044 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1045
1046 clear_check_for_tx_hang(tx_ring);
1047
1048 /*
1049 * Check for a hung queue, but be thorough. This verifies
1050 * that a transmit has been completed since the previous
1051 * check AND there is at least one packet pending. The
1052 * ARMED bit is set to indicate a potential hang. The
1053 * bit is cleared if a pause frame is received to remove
1054 * false hang detection due to PFC or 802.3x frames. By
1055 * requiring this to fail twice we avoid races with
1056 * pfc clearing the ARMED bit and conditions where we
1057 * run the check_tx_hang logic with a transmit completion
1058 * pending but without time to complete it yet.
1059 */
1060 if (tx_done_old == tx_done && tx_pending)
1061 /* make sure it is true for two checks in a row */
1062 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1063 &tx_ring->state);
1064 /* update completed stats and continue */
1065 tx_ring->tx_stats.tx_done_old = tx_done;
1066 /* reset the countdown */
1067 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1068
1069 return false;
1070 }
1071
1072 /**
1073 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1074 * @adapter: driver private struct
1075 **/
1076 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1077 {
1078
1079 /* Do the reset outside of interrupt context */
1080 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1081 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
1082 e_warn(drv, "initiating reset due to tx timeout\n");
1083 ixgbe_service_event_schedule(adapter);
1084 }
1085 }
1086
1087 /**
1088 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1089 * @q_vector: structure containing interrupt and ring information
1090 * @tx_ring: tx ring to clean
1091 **/
1092 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1093 struct ixgbe_ring *tx_ring)
1094 {
1095 struct ixgbe_adapter *adapter = q_vector->adapter;
1096 struct ixgbe_tx_buffer *tx_buffer;
1097 union ixgbe_adv_tx_desc *tx_desc;
1098 unsigned int total_bytes = 0, total_packets = 0;
1099 unsigned int budget = q_vector->tx.work_limit;
1100 unsigned int i = tx_ring->next_to_clean;
1101
1102 if (test_bit(__IXGBE_DOWN, &adapter->state))
1103 return true;
1104
1105 tx_buffer = &tx_ring->tx_buffer_info[i];
1106 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1107 i -= tx_ring->count;
1108
1109 do {
1110 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1111
1112 /* if next_to_watch is not set then there is no work pending */
1113 if (!eop_desc)
1114 break;
1115
1116 /* prevent any other reads prior to eop_desc */
1117 smp_rmb();
1118
1119 /* if DD is not set pending work has not been completed */
1120 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1121 break;
1122
1123 /* clear next_to_watch to prevent false hangs */
1124 tx_buffer->next_to_watch = NULL;
1125
1126 /* update the statistics for this packet */
1127 total_bytes += tx_buffer->bytecount;
1128 total_packets += tx_buffer->gso_segs;
1129
1130 /* free the skb */
1131 dev_consume_skb_any(tx_buffer->skb);
1132
1133 /* unmap skb header data */
1134 dma_unmap_single(tx_ring->dev,
1135 dma_unmap_addr(tx_buffer, dma),
1136 dma_unmap_len(tx_buffer, len),
1137 DMA_TO_DEVICE);
1138
1139 /* clear tx_buffer data */
1140 tx_buffer->skb = NULL;
1141 dma_unmap_len_set(tx_buffer, len, 0);
1142
1143 /* unmap remaining buffers */
1144 while (tx_desc != eop_desc) {
1145 tx_buffer++;
1146 tx_desc++;
1147 i++;
1148 if (unlikely(!i)) {
1149 i -= tx_ring->count;
1150 tx_buffer = tx_ring->tx_buffer_info;
1151 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1152 }
1153
1154 /* unmap any remaining paged data */
1155 if (dma_unmap_len(tx_buffer, len)) {
1156 dma_unmap_page(tx_ring->dev,
1157 dma_unmap_addr(tx_buffer, dma),
1158 dma_unmap_len(tx_buffer, len),
1159 DMA_TO_DEVICE);
1160 dma_unmap_len_set(tx_buffer, len, 0);
1161 }
1162 }
1163
1164 /* move us one more past the eop_desc for start of next pkt */
1165 tx_buffer++;
1166 tx_desc++;
1167 i++;
1168 if (unlikely(!i)) {
1169 i -= tx_ring->count;
1170 tx_buffer = tx_ring->tx_buffer_info;
1171 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1172 }
1173
1174 /* issue prefetch for next Tx descriptor */
1175 prefetch(tx_desc);
1176
1177 /* update budget accounting */
1178 budget--;
1179 } while (likely(budget));
1180
1181 i += tx_ring->count;
1182 tx_ring->next_to_clean = i;
1183 u64_stats_update_begin(&tx_ring->syncp);
1184 tx_ring->stats.bytes += total_bytes;
1185 tx_ring->stats.packets += total_packets;
1186 u64_stats_update_end(&tx_ring->syncp);
1187 q_vector->tx.total_bytes += total_bytes;
1188 q_vector->tx.total_packets += total_packets;
1189
1190 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1191 /* schedule immediate reset if we believe we hung */
1192 struct ixgbe_hw *hw = &adapter->hw;
1193 e_err(drv, "Detected Tx Unit Hang\n"
1194 " Tx Queue <%d>\n"
1195 " TDH, TDT <%x>, <%x>\n"
1196 " next_to_use <%x>\n"
1197 " next_to_clean <%x>\n"
1198 "tx_buffer_info[next_to_clean]\n"
1199 " time_stamp <%lx>\n"
1200 " jiffies <%lx>\n",
1201 tx_ring->queue_index,
1202 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1203 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1204 tx_ring->next_to_use, i,
1205 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1206
1207 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1208
1209 e_info(probe,
1210 "tx hang %d detected on queue %d, resetting adapter\n",
1211 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1212
1213 /* schedule immediate reset if we believe we hung */
1214 ixgbe_tx_timeout_reset(adapter);
1215
1216 /* the adapter is about to reset, no point in enabling stuff */
1217 return true;
1218 }
1219
1220 netdev_tx_completed_queue(txring_txq(tx_ring),
1221 total_packets, total_bytes);
1222
1223 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1224 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1225 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1226 /* Make sure that anybody stopping the queue after this
1227 * sees the new next_to_clean.
1228 */
1229 smp_mb();
1230 if (__netif_subqueue_stopped(tx_ring->netdev,
1231 tx_ring->queue_index)
1232 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1233 netif_wake_subqueue(tx_ring->netdev,
1234 tx_ring->queue_index);
1235 ++tx_ring->tx_stats.restart_queue;
1236 }
1237 }
1238
1239 return !!budget;
1240 }
1241
1242 #ifdef CONFIG_IXGBE_DCA
1243 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1244 struct ixgbe_ring *tx_ring,
1245 int cpu)
1246 {
1247 struct ixgbe_hw *hw = &adapter->hw;
1248 u32 txctrl = 0;
1249 u16 reg_offset;
1250
1251 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1252 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1253
1254 switch (hw->mac.type) {
1255 case ixgbe_mac_82598EB:
1256 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1257 break;
1258 case ixgbe_mac_82599EB:
1259 case ixgbe_mac_X540:
1260 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1261 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1262 break;
1263 default:
1264 /* for unknown hardware do not write register */
1265 return;
1266 }
1267
1268 /*
1269 * We can enable relaxed ordering for reads, but not writes when
1270 * DCA is enabled. This is due to a known issue in some chipsets
1271 * which will cause the DCA tag to be cleared.
1272 */
1273 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1274 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1275 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1276
1277 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1278 }
1279
1280 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1281 struct ixgbe_ring *rx_ring,
1282 int cpu)
1283 {
1284 struct ixgbe_hw *hw = &adapter->hw;
1285 u32 rxctrl = 0;
1286 u8 reg_idx = rx_ring->reg_idx;
1287
1288 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1289 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1290
1291 switch (hw->mac.type) {
1292 case ixgbe_mac_82599EB:
1293 case ixgbe_mac_X540:
1294 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1295 break;
1296 default:
1297 break;
1298 }
1299
1300 /*
1301 * We can enable relaxed ordering for reads, but not writes when
1302 * DCA is enabled. This is due to a known issue in some chipsets
1303 * which will cause the DCA tag to be cleared.
1304 */
1305 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1306 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1307 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1308
1309 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1310 }
1311
1312 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1313 {
1314 struct ixgbe_adapter *adapter = q_vector->adapter;
1315 struct ixgbe_ring *ring;
1316 int cpu = get_cpu();
1317
1318 if (q_vector->cpu == cpu)
1319 goto out_no_update;
1320
1321 ixgbe_for_each_ring(ring, q_vector->tx)
1322 ixgbe_update_tx_dca(adapter, ring, cpu);
1323
1324 ixgbe_for_each_ring(ring, q_vector->rx)
1325 ixgbe_update_rx_dca(adapter, ring, cpu);
1326
1327 q_vector->cpu = cpu;
1328 out_no_update:
1329 put_cpu();
1330 }
1331
1332 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1333 {
1334 int i;
1335
1336 /* always use CB2 mode, difference is masked in the CB driver */
1337 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1338 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1339 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1340 else
1341 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1342 IXGBE_DCA_CTRL_DCA_DISABLE);
1343
1344 for (i = 0; i < adapter->num_q_vectors; i++) {
1345 adapter->q_vector[i]->cpu = -1;
1346 ixgbe_update_dca(adapter->q_vector[i]);
1347 }
1348 }
1349
1350 static int __ixgbe_notify_dca(struct device *dev, void *data)
1351 {
1352 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1353 unsigned long event = *(unsigned long *)data;
1354
1355 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1356 return 0;
1357
1358 switch (event) {
1359 case DCA_PROVIDER_ADD:
1360 /* if we're already enabled, don't do it again */
1361 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1362 break;
1363 if (dca_add_requester(dev) == 0) {
1364 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1365 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1366 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1367 break;
1368 }
1369 /* Fall Through since DCA is disabled. */
1370 case DCA_PROVIDER_REMOVE:
1371 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1372 dca_remove_requester(dev);
1373 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1374 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1375 IXGBE_DCA_CTRL_DCA_DISABLE);
1376 }
1377 break;
1378 }
1379
1380 return 0;
1381 }
1382
1383 #endif /* CONFIG_IXGBE_DCA */
1384
1385 #define IXGBE_RSS_L4_TYPES_MASK \
1386 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1387 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1388 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1389 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1390
1391 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1392 union ixgbe_adv_rx_desc *rx_desc,
1393 struct sk_buff *skb)
1394 {
1395 u16 rss_type;
1396
1397 if (!(ring->netdev->features & NETIF_F_RXHASH))
1398 return;
1399
1400 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1401 IXGBE_RXDADV_RSSTYPE_MASK;
1402
1403 if (!rss_type)
1404 return;
1405
1406 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1407 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1408 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
1409 }
1410
1411 #ifdef IXGBE_FCOE
1412 /**
1413 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1414 * @ring: structure containing ring specific data
1415 * @rx_desc: advanced rx descriptor
1416 *
1417 * Returns : true if it is FCoE pkt
1418 */
1419 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1420 union ixgbe_adv_rx_desc *rx_desc)
1421 {
1422 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1423
1424 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1425 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1426 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1427 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1428 }
1429
1430 #endif /* IXGBE_FCOE */
1431 /**
1432 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1433 * @ring: structure containing ring specific data
1434 * @rx_desc: current Rx descriptor being processed
1435 * @skb: skb currently being received and modified
1436 **/
1437 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1438 union ixgbe_adv_rx_desc *rx_desc,
1439 struct sk_buff *skb)
1440 {
1441 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1442 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1443 bool encap_pkt = false;
1444
1445 skb_checksum_none_assert(skb);
1446
1447 /* Rx csum disabled */
1448 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1449 return;
1450
1451 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1452 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1453 encap_pkt = true;
1454 skb->encapsulation = 1;
1455 }
1456
1457 /* if IP and error */
1458 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1459 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1460 ring->rx_stats.csum_err++;
1461 return;
1462 }
1463
1464 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1465 return;
1466
1467 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1468 /*
1469 * 82599 errata, UDP frames with a 0 checksum can be marked as
1470 * checksum errors.
1471 */
1472 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1473 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1474 return;
1475
1476 ring->rx_stats.csum_err++;
1477 return;
1478 }
1479
1480 /* It must be a TCP or UDP packet with a valid checksum */
1481 skb->ip_summed = CHECKSUM_UNNECESSARY;
1482 if (encap_pkt) {
1483 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1484 return;
1485
1486 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1487 ring->rx_stats.csum_err++;
1488 return;
1489 }
1490 /* If we checked the outer header let the stack know */
1491 skb->csum_level = 1;
1492 }
1493 }
1494
1495 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1496 struct ixgbe_rx_buffer *bi)
1497 {
1498 struct page *page = bi->page;
1499 dma_addr_t dma;
1500
1501 /* since we are recycling buffers we should seldom need to alloc */
1502 if (likely(page))
1503 return true;
1504
1505 /* alloc new page for storage */
1506 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1507 if (unlikely(!page)) {
1508 rx_ring->rx_stats.alloc_rx_page_failed++;
1509 return false;
1510 }
1511
1512 /* map page for use */
1513 dma = dma_map_page(rx_ring->dev, page, 0,
1514 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1515
1516 /*
1517 * if mapping failed free memory back to system since
1518 * there isn't much point in holding memory we can't use
1519 */
1520 if (dma_mapping_error(rx_ring->dev, dma)) {
1521 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1522
1523 rx_ring->rx_stats.alloc_rx_page_failed++;
1524 return false;
1525 }
1526
1527 bi->dma = dma;
1528 bi->page = page;
1529 bi->page_offset = 0;
1530
1531 return true;
1532 }
1533
1534 /**
1535 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1536 * @rx_ring: ring to place buffers on
1537 * @cleaned_count: number of buffers to replace
1538 **/
1539 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1540 {
1541 union ixgbe_adv_rx_desc *rx_desc;
1542 struct ixgbe_rx_buffer *bi;
1543 u16 i = rx_ring->next_to_use;
1544
1545 /* nothing to do */
1546 if (!cleaned_count)
1547 return;
1548
1549 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1550 bi = &rx_ring->rx_buffer_info[i];
1551 i -= rx_ring->count;
1552
1553 do {
1554 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1555 break;
1556
1557 /*
1558 * Refresh the desc even if buffer_addrs didn't change
1559 * because each write-back erases this info.
1560 */
1561 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1562
1563 rx_desc++;
1564 bi++;
1565 i++;
1566 if (unlikely(!i)) {
1567 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1568 bi = rx_ring->rx_buffer_info;
1569 i -= rx_ring->count;
1570 }
1571
1572 /* clear the status bits for the next_to_use descriptor */
1573 rx_desc->wb.upper.status_error = 0;
1574
1575 cleaned_count--;
1576 } while (cleaned_count);
1577
1578 i += rx_ring->count;
1579
1580 if (rx_ring->next_to_use != i) {
1581 rx_ring->next_to_use = i;
1582
1583 /* update next to alloc since we have filled the ring */
1584 rx_ring->next_to_alloc = i;
1585
1586 /* Force memory writes to complete before letting h/w
1587 * know there are new descriptors to fetch. (Only
1588 * applicable for weak-ordered memory model archs,
1589 * such as IA-64).
1590 */
1591 wmb();
1592 writel(i, rx_ring->tail);
1593 }
1594 }
1595
1596 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1597 struct sk_buff *skb)
1598 {
1599 u16 hdr_len = skb_headlen(skb);
1600
1601 /* set gso_size to avoid messing up TCP MSS */
1602 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1603 IXGBE_CB(skb)->append_cnt);
1604 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1605 }
1606
1607 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1608 struct sk_buff *skb)
1609 {
1610 /* if append_cnt is 0 then frame is not RSC */
1611 if (!IXGBE_CB(skb)->append_cnt)
1612 return;
1613
1614 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1615 rx_ring->rx_stats.rsc_flush++;
1616
1617 ixgbe_set_rsc_gso_size(rx_ring, skb);
1618
1619 /* gso_size is computed using append_cnt so always clear it last */
1620 IXGBE_CB(skb)->append_cnt = 0;
1621 }
1622
1623 /**
1624 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1625 * @rx_ring: rx descriptor ring packet is being transacted on
1626 * @rx_desc: pointer to the EOP Rx descriptor
1627 * @skb: pointer to current skb being populated
1628 *
1629 * This function checks the ring, descriptor, and packet information in
1630 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1631 * other fields within the skb.
1632 **/
1633 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1634 union ixgbe_adv_rx_desc *rx_desc,
1635 struct sk_buff *skb)
1636 {
1637 struct net_device *dev = rx_ring->netdev;
1638
1639 ixgbe_update_rsc_stats(rx_ring, skb);
1640
1641 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1642
1643 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1644
1645 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1646 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
1647
1648 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1649 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1650 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1651 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1652 }
1653
1654 skb_record_rx_queue(skb, rx_ring->queue_index);
1655
1656 skb->protocol = eth_type_trans(skb, dev);
1657 }
1658
1659 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1660 struct sk_buff *skb)
1661 {
1662 if (ixgbe_qv_busy_polling(q_vector))
1663 netif_receive_skb(skb);
1664 else
1665 napi_gro_receive(&q_vector->napi, skb);
1666 }
1667
1668 /**
1669 * ixgbe_is_non_eop - process handling of non-EOP buffers
1670 * @rx_ring: Rx ring being processed
1671 * @rx_desc: Rx descriptor for current buffer
1672 * @skb: Current socket buffer containing buffer in progress
1673 *
1674 * This function updates next to clean. If the buffer is an EOP buffer
1675 * this function exits returning false, otherwise it will place the
1676 * sk_buff in the next buffer to be chained and return true indicating
1677 * that this is in fact a non-EOP buffer.
1678 **/
1679 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1680 union ixgbe_adv_rx_desc *rx_desc,
1681 struct sk_buff *skb)
1682 {
1683 u32 ntc = rx_ring->next_to_clean + 1;
1684
1685 /* fetch, update, and store next to clean */
1686 ntc = (ntc < rx_ring->count) ? ntc : 0;
1687 rx_ring->next_to_clean = ntc;
1688
1689 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1690
1691 /* update RSC append count if present */
1692 if (ring_is_rsc_enabled(rx_ring)) {
1693 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1694 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1695
1696 if (unlikely(rsc_enabled)) {
1697 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1698
1699 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1700 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1701
1702 /* update ntc based on RSC value */
1703 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1704 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1705 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1706 }
1707 }
1708
1709 /* if we are the last buffer then there is nothing else to do */
1710 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1711 return false;
1712
1713 /* place skb in next buffer to be received */
1714 rx_ring->rx_buffer_info[ntc].skb = skb;
1715 rx_ring->rx_stats.non_eop_descs++;
1716
1717 return true;
1718 }
1719
1720 /**
1721 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1722 * @rx_ring: rx descriptor ring packet is being transacted on
1723 * @skb: pointer to current skb being adjusted
1724 *
1725 * This function is an ixgbe specific version of __pskb_pull_tail. The
1726 * main difference between this version and the original function is that
1727 * this function can make several assumptions about the state of things
1728 * that allow for significant optimizations versus the standard function.
1729 * As a result we can do things like drop a frag and maintain an accurate
1730 * truesize for the skb.
1731 */
1732 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1733 struct sk_buff *skb)
1734 {
1735 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1736 unsigned char *va;
1737 unsigned int pull_len;
1738
1739 /*
1740 * it is valid to use page_address instead of kmap since we are
1741 * working with pages allocated out of the lomem pool per
1742 * alloc_page(GFP_ATOMIC)
1743 */
1744 va = skb_frag_address(frag);
1745
1746 /*
1747 * we need the header to contain the greater of either ETH_HLEN or
1748 * 60 bytes if the skb->len is less than 60 for skb_pad.
1749 */
1750 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
1751
1752 /* align pull length to size of long to optimize memcpy performance */
1753 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1754
1755 /* update all of the pointers */
1756 skb_frag_size_sub(frag, pull_len);
1757 frag->page_offset += pull_len;
1758 skb->data_len -= pull_len;
1759 skb->tail += pull_len;
1760 }
1761
1762 /**
1763 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1764 * @rx_ring: rx descriptor ring packet is being transacted on
1765 * @skb: pointer to current skb being updated
1766 *
1767 * This function provides a basic DMA sync up for the first fragment of an
1768 * skb. The reason for doing this is that the first fragment cannot be
1769 * unmapped until we have reached the end of packet descriptor for a buffer
1770 * chain.
1771 */
1772 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1773 struct sk_buff *skb)
1774 {
1775 /* if the page was released unmap it, else just sync our portion */
1776 if (unlikely(IXGBE_CB(skb)->page_released)) {
1777 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1778 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1779 IXGBE_CB(skb)->page_released = false;
1780 } else {
1781 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1782
1783 dma_sync_single_range_for_cpu(rx_ring->dev,
1784 IXGBE_CB(skb)->dma,
1785 frag->page_offset,
1786 ixgbe_rx_bufsz(rx_ring),
1787 DMA_FROM_DEVICE);
1788 }
1789 IXGBE_CB(skb)->dma = 0;
1790 }
1791
1792 /**
1793 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1794 * @rx_ring: rx descriptor ring packet is being transacted on
1795 * @rx_desc: pointer to the EOP Rx descriptor
1796 * @skb: pointer to current skb being fixed
1797 *
1798 * Check for corrupted packet headers caused by senders on the local L2
1799 * embedded NIC switch not setting up their Tx Descriptors right. These
1800 * should be very rare.
1801 *
1802 * Also address the case where we are pulling data in on pages only
1803 * and as such no data is present in the skb header.
1804 *
1805 * In addition if skb is not at least 60 bytes we need to pad it so that
1806 * it is large enough to qualify as a valid Ethernet frame.
1807 *
1808 * Returns true if an error was encountered and skb was freed.
1809 **/
1810 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1811 union ixgbe_adv_rx_desc *rx_desc,
1812 struct sk_buff *skb)
1813 {
1814 struct net_device *netdev = rx_ring->netdev;
1815
1816 /* verify that the packet does not have any known errors */
1817 if (unlikely(ixgbe_test_staterr(rx_desc,
1818 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1819 !(netdev->features & NETIF_F_RXALL))) {
1820 dev_kfree_skb_any(skb);
1821 return true;
1822 }
1823
1824 /* place header in linear portion of buffer */
1825 if (skb_is_nonlinear(skb))
1826 ixgbe_pull_tail(rx_ring, skb);
1827
1828 #ifdef IXGBE_FCOE
1829 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1830 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1831 return false;
1832
1833 #endif
1834 /* if eth_skb_pad returns an error the skb was freed */
1835 if (eth_skb_pad(skb))
1836 return true;
1837
1838 return false;
1839 }
1840
1841 /**
1842 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1843 * @rx_ring: rx descriptor ring to store buffers on
1844 * @old_buff: donor buffer to have page reused
1845 *
1846 * Synchronizes page for reuse by the adapter
1847 **/
1848 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1849 struct ixgbe_rx_buffer *old_buff)
1850 {
1851 struct ixgbe_rx_buffer *new_buff;
1852 u16 nta = rx_ring->next_to_alloc;
1853
1854 new_buff = &rx_ring->rx_buffer_info[nta];
1855
1856 /* update, and store next to alloc */
1857 nta++;
1858 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1859
1860 /* transfer page from old buffer to new buffer */
1861 *new_buff = *old_buff;
1862
1863 /* sync the buffer for use by the device */
1864 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1865 new_buff->page_offset,
1866 ixgbe_rx_bufsz(rx_ring),
1867 DMA_FROM_DEVICE);
1868 }
1869
1870 static inline bool ixgbe_page_is_reserved(struct page *page)
1871 {
1872 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1873 }
1874
1875 /**
1876 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1877 * @rx_ring: rx descriptor ring to transact packets on
1878 * @rx_buffer: buffer containing page to add
1879 * @rx_desc: descriptor containing length of buffer written by hardware
1880 * @skb: sk_buff to place the data into
1881 *
1882 * This function will add the data contained in rx_buffer->page to the skb.
1883 * This is done either through a direct copy if the data in the buffer is
1884 * less than the skb header size, otherwise it will just attach the page as
1885 * a frag to the skb.
1886 *
1887 * The function will then update the page offset if necessary and return
1888 * true if the buffer can be reused by the adapter.
1889 **/
1890 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1891 struct ixgbe_rx_buffer *rx_buffer,
1892 union ixgbe_adv_rx_desc *rx_desc,
1893 struct sk_buff *skb)
1894 {
1895 struct page *page = rx_buffer->page;
1896 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1897 #if (PAGE_SIZE < 8192)
1898 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1899 #else
1900 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1901 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1902 ixgbe_rx_bufsz(rx_ring);
1903 #endif
1904
1905 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1906 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1907
1908 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1909
1910 /* page is not reserved, we can reuse buffer as-is */
1911 if (likely(!ixgbe_page_is_reserved(page)))
1912 return true;
1913
1914 /* this page cannot be reused so discard it */
1915 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1916 return false;
1917 }
1918
1919 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1920 rx_buffer->page_offset, size, truesize);
1921
1922 /* avoid re-using remote pages */
1923 if (unlikely(ixgbe_page_is_reserved(page)))
1924 return false;
1925
1926 #if (PAGE_SIZE < 8192)
1927 /* if we are only owner of page we can reuse it */
1928 if (unlikely(page_count(page) != 1))
1929 return false;
1930
1931 /* flip page offset to other buffer */
1932 rx_buffer->page_offset ^= truesize;
1933 #else
1934 /* move offset up to the next cache line */
1935 rx_buffer->page_offset += truesize;
1936
1937 if (rx_buffer->page_offset > last_offset)
1938 return false;
1939 #endif
1940
1941 /* Even if we own the page, we are not allowed to use atomic_set()
1942 * This would break get_page_unless_zero() users.
1943 */
1944 atomic_inc(&page->_count);
1945
1946 return true;
1947 }
1948
1949 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1950 union ixgbe_adv_rx_desc *rx_desc)
1951 {
1952 struct ixgbe_rx_buffer *rx_buffer;
1953 struct sk_buff *skb;
1954 struct page *page;
1955
1956 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1957 page = rx_buffer->page;
1958 prefetchw(page);
1959
1960 skb = rx_buffer->skb;
1961
1962 if (likely(!skb)) {
1963 void *page_addr = page_address(page) +
1964 rx_buffer->page_offset;
1965
1966 /* prefetch first cache line of first page */
1967 prefetch(page_addr);
1968 #if L1_CACHE_BYTES < 128
1969 prefetch(page_addr + L1_CACHE_BYTES);
1970 #endif
1971
1972 /* allocate a skb to store the frags */
1973 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1974 IXGBE_RX_HDR_SIZE);
1975 if (unlikely(!skb)) {
1976 rx_ring->rx_stats.alloc_rx_buff_failed++;
1977 return NULL;
1978 }
1979
1980 /*
1981 * we will be copying header into skb->data in
1982 * pskb_may_pull so it is in our interest to prefetch
1983 * it now to avoid a possible cache miss
1984 */
1985 prefetchw(skb->data);
1986
1987 /*
1988 * Delay unmapping of the first packet. It carries the
1989 * header information, HW may still access the header
1990 * after the writeback. Only unmap it when EOP is
1991 * reached
1992 */
1993 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1994 goto dma_sync;
1995
1996 IXGBE_CB(skb)->dma = rx_buffer->dma;
1997 } else {
1998 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1999 ixgbe_dma_sync_frag(rx_ring, skb);
2000
2001 dma_sync:
2002 /* we are reusing so sync this buffer for CPU use */
2003 dma_sync_single_range_for_cpu(rx_ring->dev,
2004 rx_buffer->dma,
2005 rx_buffer->page_offset,
2006 ixgbe_rx_bufsz(rx_ring),
2007 DMA_FROM_DEVICE);
2008
2009 rx_buffer->skb = NULL;
2010 }
2011
2012 /* pull page into skb */
2013 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2014 /* hand second half of page back to the ring */
2015 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2016 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2017 /* the page has been released from the ring */
2018 IXGBE_CB(skb)->page_released = true;
2019 } else {
2020 /* we are not reusing the buffer so unmap it */
2021 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2022 ixgbe_rx_pg_size(rx_ring),
2023 DMA_FROM_DEVICE);
2024 }
2025
2026 /* clear contents of buffer_info */
2027 rx_buffer->page = NULL;
2028
2029 return skb;
2030 }
2031
2032 /**
2033 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2034 * @q_vector: structure containing interrupt and ring information
2035 * @rx_ring: rx descriptor ring to transact packets on
2036 * @budget: Total limit on number of packets to process
2037 *
2038 * This function provides a "bounce buffer" approach to Rx interrupt
2039 * processing. The advantage to this is that on systems that have
2040 * expensive overhead for IOMMU access this provides a means of avoiding
2041 * it by maintaining the mapping of the page to the syste.
2042 *
2043 * Returns amount of work completed
2044 **/
2045 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2046 struct ixgbe_ring *rx_ring,
2047 const int budget)
2048 {
2049 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2050 #ifdef IXGBE_FCOE
2051 struct ixgbe_adapter *adapter = q_vector->adapter;
2052 int ddp_bytes;
2053 unsigned int mss = 0;
2054 #endif /* IXGBE_FCOE */
2055 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2056
2057 while (likely(total_rx_packets < budget)) {
2058 union ixgbe_adv_rx_desc *rx_desc;
2059 struct sk_buff *skb;
2060
2061 /* return some buffers to hardware, one at a time is too slow */
2062 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2063 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2064 cleaned_count = 0;
2065 }
2066
2067 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2068
2069 if (!rx_desc->wb.upper.status_error)
2070 break;
2071
2072 /* This memory barrier is needed to keep us from reading
2073 * any other fields out of the rx_desc until we know the
2074 * descriptor has been written back
2075 */
2076 dma_rmb();
2077
2078 /* retrieve a buffer from the ring */
2079 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2080
2081 /* exit if we failed to retrieve a buffer */
2082 if (!skb)
2083 break;
2084
2085 cleaned_count++;
2086
2087 /* place incomplete frames back on ring for completion */
2088 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2089 continue;
2090
2091 /* verify the packet layout is correct */
2092 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2093 continue;
2094
2095 /* probably a little skewed due to removing CRC */
2096 total_rx_bytes += skb->len;
2097
2098 /* populate checksum, timestamp, VLAN, and protocol */
2099 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2100
2101 #ifdef IXGBE_FCOE
2102 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2103 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2104 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2105 /* include DDPed FCoE data */
2106 if (ddp_bytes > 0) {
2107 if (!mss) {
2108 mss = rx_ring->netdev->mtu -
2109 sizeof(struct fcoe_hdr) -
2110 sizeof(struct fc_frame_header) -
2111 sizeof(struct fcoe_crc_eof);
2112 if (mss > 512)
2113 mss &= ~511;
2114 }
2115 total_rx_bytes += ddp_bytes;
2116 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2117 mss);
2118 }
2119 if (!ddp_bytes) {
2120 dev_kfree_skb_any(skb);
2121 continue;
2122 }
2123 }
2124
2125 #endif /* IXGBE_FCOE */
2126 skb_mark_napi_id(skb, &q_vector->napi);
2127 ixgbe_rx_skb(q_vector, skb);
2128
2129 /* update budget accounting */
2130 total_rx_packets++;
2131 }
2132
2133 u64_stats_update_begin(&rx_ring->syncp);
2134 rx_ring->stats.packets += total_rx_packets;
2135 rx_ring->stats.bytes += total_rx_bytes;
2136 u64_stats_update_end(&rx_ring->syncp);
2137 q_vector->rx.total_packets += total_rx_packets;
2138 q_vector->rx.total_bytes += total_rx_bytes;
2139
2140 return total_rx_packets;
2141 }
2142
2143 #ifdef CONFIG_NET_RX_BUSY_POLL
2144 /* must be called with local_bh_disable()d */
2145 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2146 {
2147 struct ixgbe_q_vector *q_vector =
2148 container_of(napi, struct ixgbe_q_vector, napi);
2149 struct ixgbe_adapter *adapter = q_vector->adapter;
2150 struct ixgbe_ring *ring;
2151 int found = 0;
2152
2153 if (test_bit(__IXGBE_DOWN, &adapter->state))
2154 return LL_FLUSH_FAILED;
2155
2156 if (!ixgbe_qv_lock_poll(q_vector))
2157 return LL_FLUSH_BUSY;
2158
2159 ixgbe_for_each_ring(ring, q_vector->rx) {
2160 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2161 #ifdef BP_EXTENDED_STATS
2162 if (found)
2163 ring->stats.cleaned += found;
2164 else
2165 ring->stats.misses++;
2166 #endif
2167 if (found)
2168 break;
2169 }
2170
2171 ixgbe_qv_unlock_poll(q_vector);
2172
2173 return found;
2174 }
2175 #endif /* CONFIG_NET_RX_BUSY_POLL */
2176
2177 /**
2178 * ixgbe_configure_msix - Configure MSI-X hardware
2179 * @adapter: board private structure
2180 *
2181 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2182 * interrupts.
2183 **/
2184 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2185 {
2186 struct ixgbe_q_vector *q_vector;
2187 int v_idx;
2188 u32 mask;
2189
2190 /* Populate MSIX to EITR Select */
2191 if (adapter->num_vfs > 32) {
2192 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2194 }
2195
2196 /*
2197 * Populate the IVAR table and set the ITR values to the
2198 * corresponding register.
2199 */
2200 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2201 struct ixgbe_ring *ring;
2202 q_vector = adapter->q_vector[v_idx];
2203
2204 ixgbe_for_each_ring(ring, q_vector->rx)
2205 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2206
2207 ixgbe_for_each_ring(ring, q_vector->tx)
2208 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2209
2210 ixgbe_write_eitr(q_vector);
2211 }
2212
2213 switch (adapter->hw.mac.type) {
2214 case ixgbe_mac_82598EB:
2215 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2216 v_idx);
2217 break;
2218 case ixgbe_mac_82599EB:
2219 case ixgbe_mac_X540:
2220 case ixgbe_mac_X550:
2221 case ixgbe_mac_X550EM_x:
2222 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2223 break;
2224 default:
2225 break;
2226 }
2227 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2228
2229 /* set up to autoclear timer, and the vectors */
2230 mask = IXGBE_EIMS_ENABLE_MASK;
2231 mask &= ~(IXGBE_EIMS_OTHER |
2232 IXGBE_EIMS_MAILBOX |
2233 IXGBE_EIMS_LSC);
2234
2235 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2236 }
2237
2238 enum latency_range {
2239 lowest_latency = 0,
2240 low_latency = 1,
2241 bulk_latency = 2,
2242 latency_invalid = 255
2243 };
2244
2245 /**
2246 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2247 * @q_vector: structure containing interrupt and ring information
2248 * @ring_container: structure containing ring performance data
2249 *
2250 * Stores a new ITR value based on packets and byte
2251 * counts during the last interrupt. The advantage of per interrupt
2252 * computation is faster updates and more accurate ITR for the current
2253 * traffic pattern. Constants in this function were computed
2254 * based on theoretical maximum wire speed and thresholds were set based
2255 * on testing data as well as attempting to minimize response time
2256 * while increasing bulk throughput.
2257 * this functionality is controlled by the InterruptThrottleRate module
2258 * parameter (see ixgbe_param.c)
2259 **/
2260 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2261 struct ixgbe_ring_container *ring_container)
2262 {
2263 int bytes = ring_container->total_bytes;
2264 int packets = ring_container->total_packets;
2265 u32 timepassed_us;
2266 u64 bytes_perint;
2267 u8 itr_setting = ring_container->itr;
2268
2269 if (packets == 0)
2270 return;
2271
2272 /* simple throttlerate management
2273 * 0-10MB/s lowest (100000 ints/s)
2274 * 10-20MB/s low (20000 ints/s)
2275 * 20-1249MB/s bulk (12000 ints/s)
2276 */
2277 /* what was last interrupt timeslice? */
2278 timepassed_us = q_vector->itr >> 2;
2279 if (timepassed_us == 0)
2280 return;
2281
2282 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2283
2284 switch (itr_setting) {
2285 case lowest_latency:
2286 if (bytes_perint > 10)
2287 itr_setting = low_latency;
2288 break;
2289 case low_latency:
2290 if (bytes_perint > 20)
2291 itr_setting = bulk_latency;
2292 else if (bytes_perint <= 10)
2293 itr_setting = lowest_latency;
2294 break;
2295 case bulk_latency:
2296 if (bytes_perint <= 20)
2297 itr_setting = low_latency;
2298 break;
2299 }
2300
2301 /* clear work counters since we have the values we need */
2302 ring_container->total_bytes = 0;
2303 ring_container->total_packets = 0;
2304
2305 /* write updated itr to ring container */
2306 ring_container->itr = itr_setting;
2307 }
2308
2309 /**
2310 * ixgbe_write_eitr - write EITR register in hardware specific way
2311 * @q_vector: structure containing interrupt and ring information
2312 *
2313 * This function is made to be called by ethtool and by the driver
2314 * when it needs to update EITR registers at runtime. Hardware
2315 * specific quirks/differences are taken care of here.
2316 */
2317 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2318 {
2319 struct ixgbe_adapter *adapter = q_vector->adapter;
2320 struct ixgbe_hw *hw = &adapter->hw;
2321 int v_idx = q_vector->v_idx;
2322 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2323
2324 switch (adapter->hw.mac.type) {
2325 case ixgbe_mac_82598EB:
2326 /* must write high and low 16 bits to reset counter */
2327 itr_reg |= (itr_reg << 16);
2328 break;
2329 case ixgbe_mac_82599EB:
2330 case ixgbe_mac_X540:
2331 case ixgbe_mac_X550:
2332 case ixgbe_mac_X550EM_x:
2333 /*
2334 * set the WDIS bit to not clear the timer bits and cause an
2335 * immediate assertion of the interrupt
2336 */
2337 itr_reg |= IXGBE_EITR_CNT_WDIS;
2338 break;
2339 default:
2340 break;
2341 }
2342 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2343 }
2344
2345 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2346 {
2347 u32 new_itr = q_vector->itr;
2348 u8 current_itr;
2349
2350 ixgbe_update_itr(q_vector, &q_vector->tx);
2351 ixgbe_update_itr(q_vector, &q_vector->rx);
2352
2353 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2354
2355 switch (current_itr) {
2356 /* counts and packets in update_itr are dependent on these numbers */
2357 case lowest_latency:
2358 new_itr = IXGBE_100K_ITR;
2359 break;
2360 case low_latency:
2361 new_itr = IXGBE_20K_ITR;
2362 break;
2363 case bulk_latency:
2364 new_itr = IXGBE_12K_ITR;
2365 break;
2366 default:
2367 break;
2368 }
2369
2370 if (new_itr != q_vector->itr) {
2371 /* do an exponential smoothing */
2372 new_itr = (10 * new_itr * q_vector->itr) /
2373 ((9 * new_itr) + q_vector->itr);
2374
2375 /* save the algorithm value here */
2376 q_vector->itr = new_itr;
2377
2378 ixgbe_write_eitr(q_vector);
2379 }
2380 }
2381
2382 /**
2383 * ixgbe_check_overtemp_subtask - check for over temperature
2384 * @adapter: pointer to adapter
2385 **/
2386 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2387 {
2388 struct ixgbe_hw *hw = &adapter->hw;
2389 u32 eicr = adapter->interrupt_event;
2390
2391 if (test_bit(__IXGBE_DOWN, &adapter->state))
2392 return;
2393
2394 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2395 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2396 return;
2397
2398 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2399
2400 switch (hw->device_id) {
2401 case IXGBE_DEV_ID_82599_T3_LOM:
2402 /*
2403 * Since the warning interrupt is for both ports
2404 * we don't have to check if:
2405 * - This interrupt wasn't for our port.
2406 * - We may have missed the interrupt so always have to
2407 * check if we got a LSC
2408 */
2409 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
2410 !(eicr & IXGBE_EICR_LSC))
2411 return;
2412
2413 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2414 u32 speed;
2415 bool link_up = false;
2416
2417 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2418
2419 if (link_up)
2420 return;
2421 }
2422
2423 /* Check if this is not due to overtemp */
2424 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2425 return;
2426
2427 break;
2428 default:
2429 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2430 return;
2431 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
2432 return;
2433 break;
2434 }
2435 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2436
2437 adapter->interrupt_event = 0;
2438 }
2439
2440 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2441 {
2442 struct ixgbe_hw *hw = &adapter->hw;
2443
2444 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2445 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2446 e_crit(probe, "Fan has stopped, replace the adapter\n");
2447 /* write to clear the interrupt */
2448 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2449 }
2450 }
2451
2452 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2453 {
2454 struct ixgbe_hw *hw = &adapter->hw;
2455
2456 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2457 return;
2458
2459 switch (adapter->hw.mac.type) {
2460 case ixgbe_mac_82599EB:
2461 /*
2462 * Need to check link state so complete overtemp check
2463 * on service task
2464 */
2465 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2466 (eicr & IXGBE_EICR_LSC)) &&
2467 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2468 adapter->interrupt_event = eicr;
2469 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2470 ixgbe_service_event_schedule(adapter);
2471 return;
2472 }
2473 return;
2474 case ixgbe_mac_X540:
2475 if (!(eicr & IXGBE_EICR_TS))
2476 return;
2477 break;
2478 default:
2479 return;
2480 }
2481
2482 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2483 }
2484
2485 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2486 {
2487 switch (hw->mac.type) {
2488 case ixgbe_mac_82598EB:
2489 if (hw->phy.type == ixgbe_phy_nl)
2490 return true;
2491 return false;
2492 case ixgbe_mac_82599EB:
2493 case ixgbe_mac_X550EM_x:
2494 switch (hw->mac.ops.get_media_type(hw)) {
2495 case ixgbe_media_type_fiber:
2496 case ixgbe_media_type_fiber_qsfp:
2497 return true;
2498 default:
2499 return false;
2500 }
2501 default:
2502 return false;
2503 }
2504 }
2505
2506 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2507 {
2508 struct ixgbe_hw *hw = &adapter->hw;
2509 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
2510
2511 if (!ixgbe_is_sfp(hw))
2512 return;
2513
2514 /* Later MAC's use different SDP */
2515 if (hw->mac.type >= ixgbe_mac_X540)
2516 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2517
2518 if (eicr & eicr_mask) {
2519 /* Clear the interrupt */
2520 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
2521 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2522 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2523 adapter->sfp_poll_time = 0;
2524 ixgbe_service_event_schedule(adapter);
2525 }
2526 }
2527
2528 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2529 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2530 /* Clear the interrupt */
2531 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2532 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2533 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2534 ixgbe_service_event_schedule(adapter);
2535 }
2536 }
2537 }
2538
2539 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2540 {
2541 struct ixgbe_hw *hw = &adapter->hw;
2542
2543 adapter->lsc_int++;
2544 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2545 adapter->link_check_timeout = jiffies;
2546 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2547 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2548 IXGBE_WRITE_FLUSH(hw);
2549 ixgbe_service_event_schedule(adapter);
2550 }
2551 }
2552
2553 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2554 u64 qmask)
2555 {
2556 u32 mask;
2557 struct ixgbe_hw *hw = &adapter->hw;
2558
2559 switch (hw->mac.type) {
2560 case ixgbe_mac_82598EB:
2561 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2562 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2563 break;
2564 case ixgbe_mac_82599EB:
2565 case ixgbe_mac_X540:
2566 case ixgbe_mac_X550:
2567 case ixgbe_mac_X550EM_x:
2568 mask = (qmask & 0xFFFFFFFF);
2569 if (mask)
2570 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2571 mask = (qmask >> 32);
2572 if (mask)
2573 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2574 break;
2575 default:
2576 break;
2577 }
2578 /* skip the flush */
2579 }
2580
2581 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2582 u64 qmask)
2583 {
2584 u32 mask;
2585 struct ixgbe_hw *hw = &adapter->hw;
2586
2587 switch (hw->mac.type) {
2588 case ixgbe_mac_82598EB:
2589 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2590 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2591 break;
2592 case ixgbe_mac_82599EB:
2593 case ixgbe_mac_X540:
2594 case ixgbe_mac_X550:
2595 case ixgbe_mac_X550EM_x:
2596 mask = (qmask & 0xFFFFFFFF);
2597 if (mask)
2598 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2599 mask = (qmask >> 32);
2600 if (mask)
2601 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2602 break;
2603 default:
2604 break;
2605 }
2606 /* skip the flush */
2607 }
2608
2609 /**
2610 * ixgbe_irq_enable - Enable default interrupt generation settings
2611 * @adapter: board private structure
2612 **/
2613 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2614 bool flush)
2615 {
2616 struct ixgbe_hw *hw = &adapter->hw;
2617 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2618
2619 /* don't reenable LSC while waiting for link */
2620 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2621 mask &= ~IXGBE_EIMS_LSC;
2622
2623 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2624 switch (adapter->hw.mac.type) {
2625 case ixgbe_mac_82599EB:
2626 mask |= IXGBE_EIMS_GPI_SDP0(hw);
2627 break;
2628 case ixgbe_mac_X540:
2629 case ixgbe_mac_X550:
2630 case ixgbe_mac_X550EM_x:
2631 mask |= IXGBE_EIMS_TS;
2632 break;
2633 default:
2634 break;
2635 }
2636 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2637 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2638 switch (adapter->hw.mac.type) {
2639 case ixgbe_mac_82599EB:
2640 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2641 mask |= IXGBE_EIMS_GPI_SDP2(hw);
2642 /* fall through */
2643 case ixgbe_mac_X540:
2644 case ixgbe_mac_X550:
2645 case ixgbe_mac_X550EM_x:
2646 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2647 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
2648 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2649 mask |= IXGBE_EICR_GPI_SDP0_X540;
2650 mask |= IXGBE_EIMS_ECC;
2651 mask |= IXGBE_EIMS_MAILBOX;
2652 break;
2653 default:
2654 break;
2655 }
2656
2657 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2658 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2659 mask |= IXGBE_EIMS_FLOW_DIR;
2660
2661 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2662 if (queues)
2663 ixgbe_irq_enable_queues(adapter, ~0);
2664 if (flush)
2665 IXGBE_WRITE_FLUSH(&adapter->hw);
2666 }
2667
2668 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2669 {
2670 struct ixgbe_adapter *adapter = data;
2671 struct ixgbe_hw *hw = &adapter->hw;
2672 u32 eicr;
2673
2674 /*
2675 * Workaround for Silicon errata. Use clear-by-write instead
2676 * of clear-by-read. Reading with EICS will return the
2677 * interrupt causes without clearing, which later be done
2678 * with the write to EICR.
2679 */
2680 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2681
2682 /* The lower 16bits of the EICR register are for the queue interrupts
2683 * which should be masked here in order to not accidentally clear them if
2684 * the bits are high when ixgbe_msix_other is called. There is a race
2685 * condition otherwise which results in possible performance loss
2686 * especially if the ixgbe_msix_other interrupt is triggering
2687 * consistently (as it would when PPS is turned on for the X540 device)
2688 */
2689 eicr &= 0xFFFF0000;
2690
2691 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2692
2693 if (eicr & IXGBE_EICR_LSC)
2694 ixgbe_check_lsc(adapter);
2695
2696 if (eicr & IXGBE_EICR_MAILBOX)
2697 ixgbe_msg_task(adapter);
2698
2699 switch (hw->mac.type) {
2700 case ixgbe_mac_82599EB:
2701 case ixgbe_mac_X540:
2702 case ixgbe_mac_X550:
2703 case ixgbe_mac_X550EM_x:
2704 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2705 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2706 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2707 ixgbe_service_event_schedule(adapter);
2708 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2709 IXGBE_EICR_GPI_SDP0_X540);
2710 }
2711 if (eicr & IXGBE_EICR_ECC) {
2712 e_info(link, "Received ECC Err, initiating reset\n");
2713 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2714 ixgbe_service_event_schedule(adapter);
2715 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2716 }
2717 /* Handle Flow Director Full threshold interrupt */
2718 if (eicr & IXGBE_EICR_FLOW_DIR) {
2719 int reinit_count = 0;
2720 int i;
2721 for (i = 0; i < adapter->num_tx_queues; i++) {
2722 struct ixgbe_ring *ring = adapter->tx_ring[i];
2723 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2724 &ring->state))
2725 reinit_count++;
2726 }
2727 if (reinit_count) {
2728 /* no more flow director interrupts until after init */
2729 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2730 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2731 ixgbe_service_event_schedule(adapter);
2732 }
2733 }
2734 ixgbe_check_sfp_event(adapter, eicr);
2735 ixgbe_check_overtemp_event(adapter, eicr);
2736 break;
2737 default:
2738 break;
2739 }
2740
2741 ixgbe_check_fan_failure(adapter, eicr);
2742
2743 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2744 ixgbe_ptp_check_pps_event(adapter, eicr);
2745
2746 /* re-enable the original interrupt state, no lsc, no queues */
2747 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2748 ixgbe_irq_enable(adapter, false, false);
2749
2750 return IRQ_HANDLED;
2751 }
2752
2753 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2754 {
2755 struct ixgbe_q_vector *q_vector = data;
2756
2757 /* EIAM disabled interrupts (on this vector) for us */
2758
2759 if (q_vector->rx.ring || q_vector->tx.ring)
2760 napi_schedule(&q_vector->napi);
2761
2762 return IRQ_HANDLED;
2763 }
2764
2765 /**
2766 * ixgbe_poll - NAPI Rx polling callback
2767 * @napi: structure for representing this polling device
2768 * @budget: how many packets driver is allowed to clean
2769 *
2770 * This function is used for legacy and MSI, NAPI mode
2771 **/
2772 int ixgbe_poll(struct napi_struct *napi, int budget)
2773 {
2774 struct ixgbe_q_vector *q_vector =
2775 container_of(napi, struct ixgbe_q_vector, napi);
2776 struct ixgbe_adapter *adapter = q_vector->adapter;
2777 struct ixgbe_ring *ring;
2778 int per_ring_budget, work_done = 0;
2779 bool clean_complete = true;
2780
2781 #ifdef CONFIG_IXGBE_DCA
2782 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2783 ixgbe_update_dca(q_vector);
2784 #endif
2785
2786 ixgbe_for_each_ring(ring, q_vector->tx)
2787 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2788
2789 /* Exit if we are called by netpoll or busy polling is active */
2790 if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector))
2791 return budget;
2792
2793 /* attempt to distribute budget to each queue fairly, but don't allow
2794 * the budget to go below 1 because we'll exit polling */
2795 if (q_vector->rx.count > 1)
2796 per_ring_budget = max(budget/q_vector->rx.count, 1);
2797 else
2798 per_ring_budget = budget;
2799
2800 ixgbe_for_each_ring(ring, q_vector->rx) {
2801 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
2802 per_ring_budget);
2803
2804 work_done += cleaned;
2805 clean_complete &= (cleaned < per_ring_budget);
2806 }
2807
2808 ixgbe_qv_unlock_napi(q_vector);
2809 /* If all work not completed, return budget and keep polling */
2810 if (!clean_complete)
2811 return budget;
2812
2813 /* all work done, exit the polling mode */
2814 napi_complete_done(napi, work_done);
2815 if (adapter->rx_itr_setting & 1)
2816 ixgbe_set_itr(q_vector);
2817 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2818 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2819
2820 return 0;
2821 }
2822
2823 /**
2824 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2825 * @adapter: board private structure
2826 *
2827 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2828 * interrupts from the kernel.
2829 **/
2830 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2831 {
2832 struct net_device *netdev = adapter->netdev;
2833 int vector, err;
2834 int ri = 0, ti = 0;
2835
2836 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2837 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2838 struct msix_entry *entry = &adapter->msix_entries[vector];
2839
2840 if (q_vector->tx.ring && q_vector->rx.ring) {
2841 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2842 "%s-%s-%d", netdev->name, "TxRx", ri++);
2843 ti++;
2844 } else if (q_vector->rx.ring) {
2845 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2846 "%s-%s-%d", netdev->name, "rx", ri++);
2847 } else if (q_vector->tx.ring) {
2848 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2849 "%s-%s-%d", netdev->name, "tx", ti++);
2850 } else {
2851 /* skip this unused q_vector */
2852 continue;
2853 }
2854 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2855 q_vector->name, q_vector);
2856 if (err) {
2857 e_err(probe, "request_irq failed for MSIX interrupt "
2858 "Error: %d\n", err);
2859 goto free_queue_irqs;
2860 }
2861 /* If Flow Director is enabled, set interrupt affinity */
2862 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2863 /* assign the mask for this irq */
2864 irq_set_affinity_hint(entry->vector,
2865 &q_vector->affinity_mask);
2866 }
2867 }
2868
2869 err = request_irq(adapter->msix_entries[vector].vector,
2870 ixgbe_msix_other, 0, netdev->name, adapter);
2871 if (err) {
2872 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2873 goto free_queue_irqs;
2874 }
2875
2876 return 0;
2877
2878 free_queue_irqs:
2879 while (vector) {
2880 vector--;
2881 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2882 NULL);
2883 free_irq(adapter->msix_entries[vector].vector,
2884 adapter->q_vector[vector]);
2885 }
2886 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2887 pci_disable_msix(adapter->pdev);
2888 kfree(adapter->msix_entries);
2889 adapter->msix_entries = NULL;
2890 return err;
2891 }
2892
2893 /**
2894 * ixgbe_intr - legacy mode Interrupt Handler
2895 * @irq: interrupt number
2896 * @data: pointer to a network interface device structure
2897 **/
2898 static irqreturn_t ixgbe_intr(int irq, void *data)
2899 {
2900 struct ixgbe_adapter *adapter = data;
2901 struct ixgbe_hw *hw = &adapter->hw;
2902 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2903 u32 eicr;
2904
2905 /*
2906 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2907 * before the read of EICR.
2908 */
2909 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2910
2911 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2912 * therefore no explicit interrupt disable is necessary */
2913 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2914 if (!eicr) {
2915 /*
2916 * shared interrupt alert!
2917 * make sure interrupts are enabled because the read will
2918 * have disabled interrupts due to EIAM
2919 * finish the workaround of silicon errata on 82598. Unmask
2920 * the interrupt that we masked before the EICR read.
2921 */
2922 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2923 ixgbe_irq_enable(adapter, true, true);
2924 return IRQ_NONE; /* Not our interrupt */
2925 }
2926
2927 if (eicr & IXGBE_EICR_LSC)
2928 ixgbe_check_lsc(adapter);
2929
2930 switch (hw->mac.type) {
2931 case ixgbe_mac_82599EB:
2932 ixgbe_check_sfp_event(adapter, eicr);
2933 /* Fall through */
2934 case ixgbe_mac_X540:
2935 case ixgbe_mac_X550:
2936 case ixgbe_mac_X550EM_x:
2937 if (eicr & IXGBE_EICR_ECC) {
2938 e_info(link, "Received ECC Err, initiating reset\n");
2939 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2940 ixgbe_service_event_schedule(adapter);
2941 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2942 }
2943 ixgbe_check_overtemp_event(adapter, eicr);
2944 break;
2945 default:
2946 break;
2947 }
2948
2949 ixgbe_check_fan_failure(adapter, eicr);
2950 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2951 ixgbe_ptp_check_pps_event(adapter, eicr);
2952
2953 /* would disable interrupts here but EIAM disabled it */
2954 napi_schedule(&q_vector->napi);
2955
2956 /*
2957 * re-enable link(maybe) and non-queue interrupts, no flush.
2958 * ixgbe_poll will re-enable the queue interrupts
2959 */
2960 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2961 ixgbe_irq_enable(adapter, false, false);
2962
2963 return IRQ_HANDLED;
2964 }
2965
2966 /**
2967 * ixgbe_request_irq - initialize interrupts
2968 * @adapter: board private structure
2969 *
2970 * Attempts to configure interrupts using the best available
2971 * capabilities of the hardware and kernel.
2972 **/
2973 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2974 {
2975 struct net_device *netdev = adapter->netdev;
2976 int err;
2977
2978 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2979 err = ixgbe_request_msix_irqs(adapter);
2980 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2981 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2982 netdev->name, adapter);
2983 else
2984 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2985 netdev->name, adapter);
2986
2987 if (err)
2988 e_err(probe, "request_irq failed, Error %d\n", err);
2989
2990 return err;
2991 }
2992
2993 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2994 {
2995 int vector;
2996
2997 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2998 free_irq(adapter->pdev->irq, adapter);
2999 return;
3000 }
3001
3002 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3003 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3004 struct msix_entry *entry = &adapter->msix_entries[vector];
3005
3006 /* free only the irqs that were actually requested */
3007 if (!q_vector->rx.ring && !q_vector->tx.ring)
3008 continue;
3009
3010 /* clear the affinity_mask in the IRQ descriptor */
3011 irq_set_affinity_hint(entry->vector, NULL);
3012
3013 free_irq(entry->vector, q_vector);
3014 }
3015
3016 free_irq(adapter->msix_entries[vector++].vector, adapter);
3017 }
3018
3019 /**
3020 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3021 * @adapter: board private structure
3022 **/
3023 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3024 {
3025 switch (adapter->hw.mac.type) {
3026 case ixgbe_mac_82598EB:
3027 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3028 break;
3029 case ixgbe_mac_82599EB:
3030 case ixgbe_mac_X540:
3031 case ixgbe_mac_X550:
3032 case ixgbe_mac_X550EM_x:
3033 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3034 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3035 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3036 break;
3037 default:
3038 break;
3039 }
3040 IXGBE_WRITE_FLUSH(&adapter->hw);
3041 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3042 int vector;
3043
3044 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3045 synchronize_irq(adapter->msix_entries[vector].vector);
3046
3047 synchronize_irq(adapter->msix_entries[vector++].vector);
3048 } else {
3049 synchronize_irq(adapter->pdev->irq);
3050 }
3051 }
3052
3053 /**
3054 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3055 *
3056 **/
3057 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3058 {
3059 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3060
3061 ixgbe_write_eitr(q_vector);
3062
3063 ixgbe_set_ivar(adapter, 0, 0, 0);
3064 ixgbe_set_ivar(adapter, 1, 0, 0);
3065
3066 e_info(hw, "Legacy interrupt IVAR setup done\n");
3067 }
3068
3069 /**
3070 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3071 * @adapter: board private structure
3072 * @ring: structure containing ring specific data
3073 *
3074 * Configure the Tx descriptor ring after a reset.
3075 **/
3076 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3077 struct ixgbe_ring *ring)
3078 {
3079 struct ixgbe_hw *hw = &adapter->hw;
3080 u64 tdba = ring->dma;
3081 int wait_loop = 10;
3082 u32 txdctl = IXGBE_TXDCTL_ENABLE;
3083 u8 reg_idx = ring->reg_idx;
3084
3085 /* disable queue to avoid issues while updating state */
3086 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3087 IXGBE_WRITE_FLUSH(hw);
3088
3089 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3090 (tdba & DMA_BIT_MASK(32)));
3091 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3092 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3093 ring->count * sizeof(union ixgbe_adv_tx_desc));
3094 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3095 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3096 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3097
3098 /*
3099 * set WTHRESH to encourage burst writeback, it should not be set
3100 * higher than 1 when:
3101 * - ITR is 0 as it could cause false TX hangs
3102 * - ITR is set to > 100k int/sec and BQL is enabled
3103 *
3104 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3105 * to or less than the number of on chip descriptors, which is
3106 * currently 40.
3107 */
3108 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3109 txdctl |= (1 << 16); /* WTHRESH = 1 */
3110 else
3111 txdctl |= (8 << 16); /* WTHRESH = 8 */
3112
3113 /*
3114 * Setting PTHRESH to 32 both improves performance
3115 * and avoids a TX hang with DFP enabled
3116 */
3117 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3118 32; /* PTHRESH = 32 */
3119
3120 /* reinitialize flowdirector state */
3121 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3122 ring->atr_sample_rate = adapter->atr_sample_rate;
3123 ring->atr_count = 0;
3124 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3125 } else {
3126 ring->atr_sample_rate = 0;
3127 }
3128
3129 /* initialize XPS */
3130 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3131 struct ixgbe_q_vector *q_vector = ring->q_vector;
3132
3133 if (q_vector)
3134 netif_set_xps_queue(ring->netdev,
3135 &q_vector->affinity_mask,
3136 ring->queue_index);
3137 }
3138
3139 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3140
3141 /* enable queue */
3142 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3143
3144 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3145 if (hw->mac.type == ixgbe_mac_82598EB &&
3146 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3147 return;
3148
3149 /* poll to verify queue is enabled */
3150 do {
3151 usleep_range(1000, 2000);
3152 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3153 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3154 if (!wait_loop)
3155 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3156 }
3157
3158 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3159 {
3160 struct ixgbe_hw *hw = &adapter->hw;
3161 u32 rttdcs, mtqc;
3162 u8 tcs = netdev_get_num_tc(adapter->netdev);
3163
3164 if (hw->mac.type == ixgbe_mac_82598EB)
3165 return;
3166
3167 /* disable the arbiter while setting MTQC */
3168 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3169 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3170 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3171
3172 /* set transmit pool layout */
3173 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3174 mtqc = IXGBE_MTQC_VT_ENA;
3175 if (tcs > 4)
3176 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3177 else if (tcs > 1)
3178 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3179 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3180 mtqc |= IXGBE_MTQC_32VF;
3181 else
3182 mtqc |= IXGBE_MTQC_64VF;
3183 } else {
3184 if (tcs > 4)
3185 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3186 else if (tcs > 1)
3187 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3188 else
3189 mtqc = IXGBE_MTQC_64Q_1PB;
3190 }
3191
3192 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3193
3194 /* Enable Security TX Buffer IFG for multiple pb */
3195 if (tcs) {
3196 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3197 sectx |= IXGBE_SECTX_DCB;
3198 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3199 }
3200
3201 /* re-enable the arbiter */
3202 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3203 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3204 }
3205
3206 /**
3207 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3208 * @adapter: board private structure
3209 *
3210 * Configure the Tx unit of the MAC after a reset.
3211 **/
3212 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3213 {
3214 struct ixgbe_hw *hw = &adapter->hw;
3215 u32 dmatxctl;
3216 u32 i;
3217
3218 ixgbe_setup_mtqc(adapter);
3219
3220 if (hw->mac.type != ixgbe_mac_82598EB) {
3221 /* DMATXCTL.EN must be before Tx queues are enabled */
3222 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3223 dmatxctl |= IXGBE_DMATXCTL_TE;
3224 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3225 }
3226
3227 /* Setup the HW Tx Head and Tail descriptor pointers */
3228 for (i = 0; i < adapter->num_tx_queues; i++)
3229 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3230 }
3231
3232 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3233 struct ixgbe_ring *ring)
3234 {
3235 struct ixgbe_hw *hw = &adapter->hw;
3236 u8 reg_idx = ring->reg_idx;
3237 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3238
3239 srrctl |= IXGBE_SRRCTL_DROP_EN;
3240
3241 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3242 }
3243
3244 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3245 struct ixgbe_ring *ring)
3246 {
3247 struct ixgbe_hw *hw = &adapter->hw;
3248 u8 reg_idx = ring->reg_idx;
3249 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3250
3251 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3252
3253 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3254 }
3255
3256 #ifdef CONFIG_IXGBE_DCB
3257 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3258 #else
3259 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3260 #endif
3261 {
3262 int i;
3263 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3264
3265 if (adapter->ixgbe_ieee_pfc)
3266 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3267
3268 /*
3269 * We should set the drop enable bit if:
3270 * SR-IOV is enabled
3271 * or
3272 * Number of Rx queues > 1 and flow control is disabled
3273 *
3274 * This allows us to avoid head of line blocking for security
3275 * and performance reasons.
3276 */
3277 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3278 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3279 for (i = 0; i < adapter->num_rx_queues; i++)
3280 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3281 } else {
3282 for (i = 0; i < adapter->num_rx_queues; i++)
3283 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3284 }
3285 }
3286
3287 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3288
3289 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3290 struct ixgbe_ring *rx_ring)
3291 {
3292 struct ixgbe_hw *hw = &adapter->hw;
3293 u32 srrctl;
3294 u8 reg_idx = rx_ring->reg_idx;
3295
3296 if (hw->mac.type == ixgbe_mac_82598EB) {
3297 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3298
3299 /*
3300 * if VMDq is not active we must program one srrctl register
3301 * per RSS queue since we have enabled RDRXCTL.MVMEN
3302 */
3303 reg_idx &= mask;
3304 }
3305
3306 /* configure header buffer length, needed for RSC */
3307 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3308
3309 /* configure the packet buffer length */
3310 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3311
3312 /* configure descriptor type */
3313 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3314
3315 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3316 }
3317
3318 /**
3319 * Return a number of entries in the RSS indirection table
3320 *
3321 * @adapter: device handle
3322 *
3323 * - 82598/82599/X540: 128
3324 * - X550(non-SRIOV mode): 512
3325 * - X550(SRIOV mode): 64
3326 */
3327 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
3328 {
3329 if (adapter->hw.mac.type < ixgbe_mac_X550)
3330 return 128;
3331 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3332 return 64;
3333 else
3334 return 512;
3335 }
3336
3337 /**
3338 * Write the RETA table to HW
3339 *
3340 * @adapter: device handle
3341 *
3342 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3343 */
3344 void ixgbe_store_reta(struct ixgbe_adapter *adapter)
3345 {
3346 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3347 struct ixgbe_hw *hw = &adapter->hw;
3348 u32 reta = 0;
3349 u32 indices_multi;
3350 u8 *indir_tbl = adapter->rss_indir_tbl;
3351
3352 /* Fill out the redirection table as follows:
3353 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3354 * indices.
3355 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3356 * - X550: 8 bit wide entries containing 6 bit RSS index
3357 */
3358 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3359 indices_multi = 0x11;
3360 else
3361 indices_multi = 0x1;
3362
3363 /* Write redirection table to HW */
3364 for (i = 0; i < reta_entries; i++) {
3365 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
3366 if ((i & 3) == 3) {
3367 if (i < 128)
3368 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3369 else
3370 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3371 reta);
3372 reta = 0;
3373 }
3374 }
3375 }
3376
3377 /**
3378 * Write the RETA table to HW (for x550 devices in SRIOV mode)
3379 *
3380 * @adapter: device handle
3381 *
3382 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3383 */
3384 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
3385 {
3386 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3387 struct ixgbe_hw *hw = &adapter->hw;
3388 u32 vfreta = 0;
3389 unsigned int pf_pool = adapter->num_vfs;
3390
3391 /* Write redirection table to HW */
3392 for (i = 0; i < reta_entries; i++) {
3393 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3394 if ((i & 3) == 3) {
3395 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3396 vfreta);
3397 vfreta = 0;
3398 }
3399 }
3400 }
3401
3402 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3403 {
3404 struct ixgbe_hw *hw = &adapter->hw;
3405 u32 i, j;
3406 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3407 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3408
3409 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3410 * make full use of any rings they may have. We will use the
3411 * PSRTYPE register to control how many rings we use within the PF.
3412 */
3413 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3414 rss_i = 2;
3415
3416 /* Fill out hash function seeds */
3417 for (i = 0; i < 10; i++)
3418 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3419
3420 /* Fill out redirection table */
3421 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3422
3423 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3424 if (j == rss_i)
3425 j = 0;
3426
3427 adapter->rss_indir_tbl[i] = j;
3428 }
3429
3430 ixgbe_store_reta(adapter);
3431 }
3432
3433 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3434 {
3435 struct ixgbe_hw *hw = &adapter->hw;
3436 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3437 unsigned int pf_pool = adapter->num_vfs;
3438 int i, j;
3439
3440 /* Fill out hash function seeds */
3441 for (i = 0; i < 10; i++)
3442 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3443 adapter->rss_key[i]);
3444
3445 /* Fill out the redirection table */
3446 for (i = 0, j = 0; i < 64; i++, j++) {
3447 if (j == rss_i)
3448 j = 0;
3449
3450 adapter->rss_indir_tbl[i] = j;
3451 }
3452
3453 ixgbe_store_vfreta(adapter);
3454 }
3455
3456 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3457 {
3458 struct ixgbe_hw *hw = &adapter->hw;
3459 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
3460 u32 rxcsum;
3461
3462 /* Disable indicating checksum in descriptor, enables RSS hash */
3463 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3464 rxcsum |= IXGBE_RXCSUM_PCSD;
3465 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3466
3467 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3468 if (adapter->ring_feature[RING_F_RSS].mask)
3469 mrqc = IXGBE_MRQC_RSSEN;
3470 } else {
3471 u8 tcs = netdev_get_num_tc(adapter->netdev);
3472
3473 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3474 if (tcs > 4)
3475 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3476 else if (tcs > 1)
3477 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3478 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3479 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3480 else
3481 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3482 } else {
3483 if (tcs > 4)
3484 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3485 else if (tcs > 1)
3486 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3487 else
3488 mrqc = IXGBE_MRQC_RSSEN;
3489 }
3490 }
3491
3492 /* Perform hash on these packet types */
3493 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3494 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3495 IXGBE_MRQC_RSS_FIELD_IPV6 |
3496 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3497
3498 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3499 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3500 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3501 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3502
3503 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
3504 if ((hw->mac.type >= ixgbe_mac_X550) &&
3505 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3506 unsigned int pf_pool = adapter->num_vfs;
3507
3508 /* Enable VF RSS mode */
3509 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3510 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3511
3512 /* Setup RSS through the VF registers */
3513 ixgbe_setup_vfreta(adapter);
3514 vfmrqc = IXGBE_MRQC_RSSEN;
3515 vfmrqc |= rss_field;
3516 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3517 } else {
3518 ixgbe_setup_reta(adapter);
3519 mrqc |= rss_field;
3520 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3521 }
3522 }
3523
3524 /**
3525 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3526 * @adapter: address of board private structure
3527 * @index: index of ring to set
3528 **/
3529 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3530 struct ixgbe_ring *ring)
3531 {
3532 struct ixgbe_hw *hw = &adapter->hw;
3533 u32 rscctrl;
3534 u8 reg_idx = ring->reg_idx;
3535
3536 if (!ring_is_rsc_enabled(ring))
3537 return;
3538
3539 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3540 rscctrl |= IXGBE_RSCCTL_RSCEN;
3541 /*
3542 * we must limit the number of descriptors so that the
3543 * total size of max desc * buf_len is not greater
3544 * than 65536
3545 */
3546 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3547 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3548 }
3549
3550 #define IXGBE_MAX_RX_DESC_POLL 10
3551 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3552 struct ixgbe_ring *ring)
3553 {
3554 struct ixgbe_hw *hw = &adapter->hw;
3555 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3556 u32 rxdctl;
3557 u8 reg_idx = ring->reg_idx;
3558
3559 if (ixgbe_removed(hw->hw_addr))
3560 return;
3561 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3562 if (hw->mac.type == ixgbe_mac_82598EB &&
3563 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3564 return;
3565
3566 do {
3567 usleep_range(1000, 2000);
3568 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3569 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3570
3571 if (!wait_loop) {
3572 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3573 "the polling period\n", reg_idx);
3574 }
3575 }
3576
3577 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3578 struct ixgbe_ring *ring)
3579 {
3580 struct ixgbe_hw *hw = &adapter->hw;
3581 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3582 u32 rxdctl;
3583 u8 reg_idx = ring->reg_idx;
3584
3585 if (ixgbe_removed(hw->hw_addr))
3586 return;
3587 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3588 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3589
3590 /* write value back with RXDCTL.ENABLE bit cleared */
3591 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3592
3593 if (hw->mac.type == ixgbe_mac_82598EB &&
3594 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3595 return;
3596
3597 /* the hardware may take up to 100us to really disable the rx queue */
3598 do {
3599 udelay(10);
3600 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3601 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3602
3603 if (!wait_loop) {
3604 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3605 "the polling period\n", reg_idx);
3606 }
3607 }
3608
3609 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3610 struct ixgbe_ring *ring)
3611 {
3612 struct ixgbe_hw *hw = &adapter->hw;
3613 u64 rdba = ring->dma;
3614 u32 rxdctl;
3615 u8 reg_idx = ring->reg_idx;
3616
3617 /* disable queue to avoid issues while updating state */
3618 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3619 ixgbe_disable_rx_queue(adapter, ring);
3620
3621 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3622 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3623 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3624 ring->count * sizeof(union ixgbe_adv_rx_desc));
3625 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3626 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3627 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
3628
3629 ixgbe_configure_srrctl(adapter, ring);
3630 ixgbe_configure_rscctl(adapter, ring);
3631
3632 if (hw->mac.type == ixgbe_mac_82598EB) {
3633 /*
3634 * enable cache line friendly hardware writes:
3635 * PTHRESH=32 descriptors (half the internal cache),
3636 * this also removes ugly rx_no_buffer_count increment
3637 * HTHRESH=4 descriptors (to minimize latency on fetch)
3638 * WTHRESH=8 burst writeback up to two cache lines
3639 */
3640 rxdctl &= ~0x3FFFFF;
3641 rxdctl |= 0x080420;
3642 }
3643
3644 /* enable receive descriptor ring */
3645 rxdctl |= IXGBE_RXDCTL_ENABLE;
3646 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3647
3648 ixgbe_rx_desc_queue_enable(adapter, ring);
3649 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3650 }
3651
3652 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3653 {
3654 struct ixgbe_hw *hw = &adapter->hw;
3655 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3656 u16 pool;
3657
3658 /* PSRTYPE must be initialized in non 82598 adapters */
3659 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3660 IXGBE_PSRTYPE_UDPHDR |
3661 IXGBE_PSRTYPE_IPV4HDR |
3662 IXGBE_PSRTYPE_L2HDR |
3663 IXGBE_PSRTYPE_IPV6HDR;
3664
3665 if (hw->mac.type == ixgbe_mac_82598EB)
3666 return;
3667
3668 if (rss_i > 3)
3669 psrtype |= 2 << 29;
3670 else if (rss_i > 1)
3671 psrtype |= 1 << 29;
3672
3673 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3674 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
3675 }
3676
3677 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3678 {
3679 struct ixgbe_hw *hw = &adapter->hw;
3680 u32 reg_offset, vf_shift;
3681 u32 gcr_ext, vmdctl;
3682 int i;
3683
3684 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3685 return;
3686
3687 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3688 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3689 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3690 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3691 vmdctl |= IXGBE_VT_CTL_REPLEN;
3692 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3693
3694 vf_shift = VMDQ_P(0) % 32;
3695 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3696
3697 /* Enable only the PF's pool for Tx/Rx */
3698 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3699 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3700 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3701 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3702 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
3703 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3704
3705 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3706 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3707
3708 /*
3709 * Set up VF register offsets for selected VT Mode,
3710 * i.e. 32 or 64 VFs for SR-IOV
3711 */
3712 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3713 case IXGBE_82599_VMDQ_8Q_MASK:
3714 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3715 break;
3716 case IXGBE_82599_VMDQ_4Q_MASK:
3717 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3718 break;
3719 default:
3720 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3721 break;
3722 }
3723
3724 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3725
3726
3727 /* Enable MAC Anti-Spoofing */
3728 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3729 adapter->num_vfs);
3730
3731 /* Ensure LLDP and FC is set for Ethertype Antispoofing if we will be
3732 * calling set_ethertype_anti_spoofing for each VF in loop below
3733 */
3734 if (hw->mac.ops.set_ethertype_anti_spoofing) {
3735 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
3736 (IXGBE_ETQF_FILTER_EN |
3737 IXGBE_ETQF_TX_ANTISPOOF |
3738 IXGBE_ETH_P_LLDP));
3739
3740 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC),
3741 (IXGBE_ETQF_FILTER_EN |
3742 IXGBE_ETQF_TX_ANTISPOOF |
3743 ETH_P_PAUSE));
3744 }
3745
3746 /* For VFs that have spoof checking turned off */
3747 for (i = 0; i < adapter->num_vfs; i++) {
3748 if (!adapter->vfinfo[i].spoofchk_enabled)
3749 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3750
3751 /* enable ethertype anti spoofing if hw supports it */
3752 if (hw->mac.ops.set_ethertype_anti_spoofing)
3753 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
3754
3755 /* Enable/Disable RSS query feature */
3756 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3757 adapter->vfinfo[i].rss_query_enabled);
3758 }
3759 }
3760
3761 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3762 {
3763 struct ixgbe_hw *hw = &adapter->hw;
3764 struct net_device *netdev = adapter->netdev;
3765 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3766 struct ixgbe_ring *rx_ring;
3767 int i;
3768 u32 mhadd, hlreg0;
3769
3770 #ifdef IXGBE_FCOE
3771 /* adjust max frame to be able to do baby jumbo for FCoE */
3772 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3773 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3774 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3775
3776 #endif /* IXGBE_FCOE */
3777
3778 /* adjust max frame to be at least the size of a standard frame */
3779 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3780 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3781
3782 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3783 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3784 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3785 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3786
3787 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3788 }
3789
3790 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3791 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3792 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3793 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3794
3795 /*
3796 * Setup the HW Rx Head and Tail Descriptor Pointers and
3797 * the Base and Length of the Rx Descriptor Ring
3798 */
3799 for (i = 0; i < adapter->num_rx_queues; i++) {
3800 rx_ring = adapter->rx_ring[i];
3801 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3802 set_ring_rsc_enabled(rx_ring);
3803 else
3804 clear_ring_rsc_enabled(rx_ring);
3805 }
3806 }
3807
3808 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3809 {
3810 struct ixgbe_hw *hw = &adapter->hw;
3811 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3812
3813 switch (hw->mac.type) {
3814 case ixgbe_mac_82598EB:
3815 /*
3816 * For VMDq support of different descriptor types or
3817 * buffer sizes through the use of multiple SRRCTL
3818 * registers, RDRXCTL.MVMEN must be set to 1
3819 *
3820 * also, the manual doesn't mention it clearly but DCA hints
3821 * will only use queue 0's tags unless this bit is set. Side
3822 * effects of setting this bit are only that SRRCTL must be
3823 * fully programmed [0..15]
3824 */
3825 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3826 break;
3827 case ixgbe_mac_X550:
3828 case ixgbe_mac_X550EM_x:
3829 if (adapter->num_vfs)
3830 rdrxctl |= IXGBE_RDRXCTL_PSP;
3831 /* fall through for older HW */
3832 case ixgbe_mac_82599EB:
3833 case ixgbe_mac_X540:
3834 /* Disable RSC for ACK packets */
3835 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3836 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3837 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3838 /* hardware requires some bits to be set by default */
3839 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3840 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3841 break;
3842 default:
3843 /* We should do nothing since we don't know this hardware */
3844 return;
3845 }
3846
3847 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3848 }
3849
3850 /**
3851 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3852 * @adapter: board private structure
3853 *
3854 * Configure the Rx unit of the MAC after a reset.
3855 **/
3856 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3857 {
3858 struct ixgbe_hw *hw = &adapter->hw;
3859 int i;
3860 u32 rxctrl, rfctl;
3861
3862 /* disable receives while setting up the descriptors */
3863 hw->mac.ops.disable_rx(hw);
3864
3865 ixgbe_setup_psrtype(adapter);
3866 ixgbe_setup_rdrxctl(adapter);
3867
3868 /* RSC Setup */
3869 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3870 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3871 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3872 rfctl |= IXGBE_RFCTL_RSC_DIS;
3873 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3874
3875 /* Program registers for the distribution of queues */
3876 ixgbe_setup_mrqc(adapter);
3877
3878 /* set_rx_buffer_len must be called before ring initialization */
3879 ixgbe_set_rx_buffer_len(adapter);
3880
3881 /*
3882 * Setup the HW Rx Head and Tail Descriptor Pointers and
3883 * the Base and Length of the Rx Descriptor Ring
3884 */
3885 for (i = 0; i < adapter->num_rx_queues; i++)
3886 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3887
3888 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3889 /* disable drop enable for 82598 parts */
3890 if (hw->mac.type == ixgbe_mac_82598EB)
3891 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3892
3893 /* enable all receives */
3894 rxctrl |= IXGBE_RXCTRL_RXEN;
3895 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3896 }
3897
3898 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3899 __be16 proto, u16 vid)
3900 {
3901 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3902 struct ixgbe_hw *hw = &adapter->hw;
3903
3904 /* add VID to filter table */
3905 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3906 set_bit(vid, adapter->active_vlans);
3907
3908 return 0;
3909 }
3910
3911 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3912 __be16 proto, u16 vid)
3913 {
3914 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3915 struct ixgbe_hw *hw = &adapter->hw;
3916
3917 /* remove VID from filter table */
3918 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3919 clear_bit(vid, adapter->active_vlans);
3920
3921 return 0;
3922 }
3923
3924 /**
3925 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3926 * @adapter: driver data
3927 */
3928 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3929 {
3930 struct ixgbe_hw *hw = &adapter->hw;
3931 u32 vlnctrl;
3932 int i, j;
3933
3934 switch (hw->mac.type) {
3935 case ixgbe_mac_82598EB:
3936 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3937 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3938 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3939 break;
3940 case ixgbe_mac_82599EB:
3941 case ixgbe_mac_X540:
3942 case ixgbe_mac_X550:
3943 case ixgbe_mac_X550EM_x:
3944 for (i = 0; i < adapter->num_rx_queues; i++) {
3945 struct ixgbe_ring *ring = adapter->rx_ring[i];
3946
3947 if (ring->l2_accel_priv)
3948 continue;
3949 j = ring->reg_idx;
3950 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3951 vlnctrl &= ~IXGBE_RXDCTL_VME;
3952 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3953 }
3954 break;
3955 default:
3956 break;
3957 }
3958 }
3959
3960 /**
3961 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3962 * @adapter: driver data
3963 */
3964 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3965 {
3966 struct ixgbe_hw *hw = &adapter->hw;
3967 u32 vlnctrl;
3968 int i, j;
3969
3970 switch (hw->mac.type) {
3971 case ixgbe_mac_82598EB:
3972 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3973 vlnctrl |= IXGBE_VLNCTRL_VME;
3974 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3975 break;
3976 case ixgbe_mac_82599EB:
3977 case ixgbe_mac_X540:
3978 case ixgbe_mac_X550:
3979 case ixgbe_mac_X550EM_x:
3980 for (i = 0; i < adapter->num_rx_queues; i++) {
3981 struct ixgbe_ring *ring = adapter->rx_ring[i];
3982
3983 if (ring->l2_accel_priv)
3984 continue;
3985 j = ring->reg_idx;
3986 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3987 vlnctrl |= IXGBE_RXDCTL_VME;
3988 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3989 }
3990 break;
3991 default:
3992 break;
3993 }
3994 }
3995
3996 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3997 {
3998 u16 vid;
3999
4000 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
4001
4002 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
4003 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
4004 }
4005
4006 /**
4007 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4008 * @netdev: network interface device structure
4009 *
4010 * Writes multicast address list to the MTA hash table.
4011 * Returns: -ENOMEM on failure
4012 * 0 on no addresses written
4013 * X on writing X addresses to MTA
4014 **/
4015 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4016 {
4017 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4018 struct ixgbe_hw *hw = &adapter->hw;
4019
4020 if (!netif_running(netdev))
4021 return 0;
4022
4023 if (hw->mac.ops.update_mc_addr_list)
4024 hw->mac.ops.update_mc_addr_list(hw, netdev);
4025 else
4026 return -ENOMEM;
4027
4028 #ifdef CONFIG_PCI_IOV
4029 ixgbe_restore_vf_multicasts(adapter);
4030 #endif
4031
4032 return netdev_mc_count(netdev);
4033 }
4034
4035 #ifdef CONFIG_PCI_IOV
4036 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4037 {
4038 struct ixgbe_hw *hw = &adapter->hw;
4039 int i;
4040 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4041 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4042 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
4043 adapter->mac_table[i].queue,
4044 IXGBE_RAH_AV);
4045 else
4046 hw->mac.ops.clear_rar(hw, i);
4047
4048 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
4049 }
4050 }
4051 #endif
4052
4053 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4054 {
4055 struct ixgbe_hw *hw = &adapter->hw;
4056 int i;
4057 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4058 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
4059 if (adapter->mac_table[i].state &
4060 IXGBE_MAC_STATE_IN_USE)
4061 hw->mac.ops.set_rar(hw, i,
4062 adapter->mac_table[i].addr,
4063 adapter->mac_table[i].queue,
4064 IXGBE_RAH_AV);
4065 else
4066 hw->mac.ops.clear_rar(hw, i);
4067
4068 adapter->mac_table[i].state &=
4069 ~(IXGBE_MAC_STATE_MODIFIED);
4070 }
4071 }
4072 }
4073
4074 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4075 {
4076 int i;
4077 struct ixgbe_hw *hw = &adapter->hw;
4078
4079 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4080 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4081 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
4082 eth_zero_addr(adapter->mac_table[i].addr);
4083 adapter->mac_table[i].queue = 0;
4084 }
4085 ixgbe_sync_mac_table(adapter);
4086 }
4087
4088 static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
4089 {
4090 struct ixgbe_hw *hw = &adapter->hw;
4091 int i, count = 0;
4092
4093 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4094 if (adapter->mac_table[i].state == 0)
4095 count++;
4096 }
4097 return count;
4098 }
4099
4100 /* this function destroys the first RAR entry */
4101 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
4102 u8 *addr)
4103 {
4104 struct ixgbe_hw *hw = &adapter->hw;
4105
4106 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
4107 adapter->mac_table[0].queue = VMDQ_P(0);
4108 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
4109 IXGBE_MAC_STATE_IN_USE);
4110 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
4111 adapter->mac_table[0].queue,
4112 IXGBE_RAH_AV);
4113 }
4114
4115 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4116 {
4117 struct ixgbe_hw *hw = &adapter->hw;
4118 int i;
4119
4120 if (is_zero_ether_addr(addr))
4121 return -EINVAL;
4122
4123 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4124 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4125 continue;
4126 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
4127 IXGBE_MAC_STATE_IN_USE);
4128 ether_addr_copy(adapter->mac_table[i].addr, addr);
4129 adapter->mac_table[i].queue = queue;
4130 ixgbe_sync_mac_table(adapter);
4131 return i;
4132 }
4133 return -ENOMEM;
4134 }
4135
4136 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4137 {
4138 /* search table for addr, if found, set to 0 and sync */
4139 int i;
4140 struct ixgbe_hw *hw = &adapter->hw;
4141
4142 if (is_zero_ether_addr(addr))
4143 return -EINVAL;
4144
4145 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4146 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
4147 adapter->mac_table[i].queue == queue) {
4148 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4149 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
4150 eth_zero_addr(adapter->mac_table[i].addr);
4151 adapter->mac_table[i].queue = 0;
4152 ixgbe_sync_mac_table(adapter);
4153 return 0;
4154 }
4155 }
4156 return -ENOMEM;
4157 }
4158 /**
4159 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4160 * @netdev: network interface device structure
4161 *
4162 * Writes unicast address list to the RAR table.
4163 * Returns: -ENOMEM on failure/insufficient address space
4164 * 0 on no addresses written
4165 * X on writing X addresses to the RAR table
4166 **/
4167 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
4168 {
4169 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4170 int count = 0;
4171
4172 /* return ENOMEM indicating insufficient memory for addresses */
4173 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
4174 return -ENOMEM;
4175
4176 if (!netdev_uc_empty(netdev)) {
4177 struct netdev_hw_addr *ha;
4178 netdev_for_each_uc_addr(ha, netdev) {
4179 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4180 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
4181 count++;
4182 }
4183 }
4184 return count;
4185 }
4186
4187 /**
4188 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4189 * @netdev: network interface device structure
4190 *
4191 * The set_rx_method entry point is called whenever the unicast/multicast
4192 * address list or the network interface flags are updated. This routine is
4193 * responsible for configuring the hardware for proper unicast, multicast and
4194 * promiscuous mode.
4195 **/
4196 void ixgbe_set_rx_mode(struct net_device *netdev)
4197 {
4198 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4199 struct ixgbe_hw *hw = &adapter->hw;
4200 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4201 u32 vlnctrl;
4202 int count;
4203
4204 /* Check for Promiscuous and All Multicast modes */
4205 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4206 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4207
4208 /* set all bits that we expect to always be set */
4209 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4210 fctrl |= IXGBE_FCTRL_BAM;
4211 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4212 fctrl |= IXGBE_FCTRL_PMCF;
4213
4214 /* clear the bits we are changing the status of */
4215 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4216 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4217 if (netdev->flags & IFF_PROMISC) {
4218 hw->addr_ctrl.user_set_promisc = true;
4219 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4220 vmolr |= IXGBE_VMOLR_MPE;
4221 /* Only disable hardware filter vlans in promiscuous mode
4222 * if SR-IOV and VMDQ are disabled - otherwise ensure
4223 * that hardware VLAN filters remain enabled.
4224 */
4225 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4226 IXGBE_FLAG_SRIOV_ENABLED))
4227 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4228 } else {
4229 if (netdev->flags & IFF_ALLMULTI) {
4230 fctrl |= IXGBE_FCTRL_MPE;
4231 vmolr |= IXGBE_VMOLR_MPE;
4232 }
4233 vlnctrl |= IXGBE_VLNCTRL_VFE;
4234 hw->addr_ctrl.user_set_promisc = false;
4235 }
4236
4237 /*
4238 * Write addresses to available RAR registers, if there is not
4239 * sufficient space to store all the addresses then enable
4240 * unicast promiscuous mode
4241 */
4242 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
4243 if (count < 0) {
4244 fctrl |= IXGBE_FCTRL_UPE;
4245 vmolr |= IXGBE_VMOLR_ROPE;
4246 }
4247
4248 /* Write addresses to the MTA, if the attempt fails
4249 * then we should just turn on promiscuous mode so
4250 * that we can at least receive multicast traffic
4251 */
4252 count = ixgbe_write_mc_addr_list(netdev);
4253 if (count < 0) {
4254 fctrl |= IXGBE_FCTRL_MPE;
4255 vmolr |= IXGBE_VMOLR_MPE;
4256 } else if (count) {
4257 vmolr |= IXGBE_VMOLR_ROMPE;
4258 }
4259
4260 if (hw->mac.type != ixgbe_mac_82598EB) {
4261 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4262 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4263 IXGBE_VMOLR_ROPE);
4264 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4265 }
4266
4267 /* This is useful for sniffing bad packets. */
4268 if (adapter->netdev->features & NETIF_F_RXALL) {
4269 /* UPE and MPE will be handled by normal PROMISC logic
4270 * in e1000e_set_rx_mode */
4271 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4272 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4273 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4274
4275 fctrl &= ~(IXGBE_FCTRL_DPF);
4276 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4277 }
4278
4279 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4280 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4281
4282 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
4283 ixgbe_vlan_strip_enable(adapter);
4284 else
4285 ixgbe_vlan_strip_disable(adapter);
4286 }
4287
4288 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4289 {
4290 int q_idx;
4291
4292 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4293 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
4294 napi_enable(&adapter->q_vector[q_idx]->napi);
4295 }
4296 }
4297
4298 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4299 {
4300 int q_idx;
4301
4302 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4303 napi_disable(&adapter->q_vector[q_idx]->napi);
4304 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
4305 pr_info("QV %d locked\n", q_idx);
4306 usleep_range(1000, 20000);
4307 }
4308 }
4309 }
4310
4311 static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4312 {
4313 switch (adapter->hw.mac.type) {
4314 case ixgbe_mac_X550:
4315 case ixgbe_mac_X550EM_x:
4316 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
4317 #ifdef CONFIG_IXGBE_VXLAN
4318 adapter->vxlan_port = 0;
4319 #endif
4320 break;
4321 default:
4322 break;
4323 }
4324 }
4325
4326 #ifdef CONFIG_IXGBE_DCB
4327 /**
4328 * ixgbe_configure_dcb - Configure DCB hardware
4329 * @adapter: ixgbe adapter struct
4330 *
4331 * This is called by the driver on open to configure the DCB hardware.
4332 * This is also called by the gennetlink interface when reconfiguring
4333 * the DCB state.
4334 */
4335 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4336 {
4337 struct ixgbe_hw *hw = &adapter->hw;
4338 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4339
4340 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4341 if (hw->mac.type == ixgbe_mac_82598EB)
4342 netif_set_gso_max_size(adapter->netdev, 65536);
4343 return;
4344 }
4345
4346 if (hw->mac.type == ixgbe_mac_82598EB)
4347 netif_set_gso_max_size(adapter->netdev, 32768);
4348
4349 #ifdef IXGBE_FCOE
4350 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4351 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
4352 #endif
4353
4354 /* reconfigure the hardware */
4355 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
4356 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4357 DCB_TX_CONFIG);
4358 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4359 DCB_RX_CONFIG);
4360 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
4361 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4362 ixgbe_dcb_hw_ets(&adapter->hw,
4363 adapter->ixgbe_ieee_ets,
4364 max_frame);
4365 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4366 adapter->ixgbe_ieee_pfc->pfc_en,
4367 adapter->ixgbe_ieee_ets->prio_tc);
4368 }
4369
4370 /* Enable RSS Hash per TC */
4371 if (hw->mac.type != ixgbe_mac_82598EB) {
4372 u32 msb = 0;
4373 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
4374
4375 while (rss_i) {
4376 msb++;
4377 rss_i >>= 1;
4378 }
4379
4380 /* write msb to all 8 TCs in one write */
4381 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
4382 }
4383 }
4384 #endif
4385
4386 /* Additional bittime to account for IXGBE framing */
4387 #define IXGBE_ETH_FRAMING 20
4388
4389 /**
4390 * ixgbe_hpbthresh - calculate high water mark for flow control
4391 *
4392 * @adapter: board private structure to calculate for
4393 * @pb: packet buffer to calculate
4394 */
4395 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4396 {
4397 struct ixgbe_hw *hw = &adapter->hw;
4398 struct net_device *dev = adapter->netdev;
4399 int link, tc, kb, marker;
4400 u32 dv_id, rx_pba;
4401
4402 /* Calculate max LAN frame size */
4403 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4404
4405 #ifdef IXGBE_FCOE
4406 /* FCoE traffic class uses FCOE jumbo frames */
4407 if ((dev->features & NETIF_F_FCOE_MTU) &&
4408 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4409 (pb == ixgbe_fcoe_get_tc(adapter)))
4410 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4411 #endif
4412
4413 /* Calculate delay value for device */
4414 switch (hw->mac.type) {
4415 case ixgbe_mac_X540:
4416 case ixgbe_mac_X550:
4417 case ixgbe_mac_X550EM_x:
4418 dv_id = IXGBE_DV_X540(link, tc);
4419 break;
4420 default:
4421 dv_id = IXGBE_DV(link, tc);
4422 break;
4423 }
4424
4425 /* Loopback switch introduces additional latency */
4426 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4427 dv_id += IXGBE_B2BT(tc);
4428
4429 /* Delay value is calculated in bit times convert to KB */
4430 kb = IXGBE_BT2KB(dv_id);
4431 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4432
4433 marker = rx_pba - kb;
4434
4435 /* It is possible that the packet buffer is not large enough
4436 * to provide required headroom. In this case throw an error
4437 * to user and a do the best we can.
4438 */
4439 if (marker < 0) {
4440 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4441 "headroom to support flow control."
4442 "Decrease MTU or number of traffic classes\n", pb);
4443 marker = tc + 1;
4444 }
4445
4446 return marker;
4447 }
4448
4449 /**
4450 * ixgbe_lpbthresh - calculate low water mark for for flow control
4451 *
4452 * @adapter: board private structure to calculate for
4453 * @pb: packet buffer to calculate
4454 */
4455 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
4456 {
4457 struct ixgbe_hw *hw = &adapter->hw;
4458 struct net_device *dev = adapter->netdev;
4459 int tc;
4460 u32 dv_id;
4461
4462 /* Calculate max LAN frame size */
4463 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4464
4465 #ifdef IXGBE_FCOE
4466 /* FCoE traffic class uses FCOE jumbo frames */
4467 if ((dev->features & NETIF_F_FCOE_MTU) &&
4468 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4469 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4470 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4471 #endif
4472
4473 /* Calculate delay value for device */
4474 switch (hw->mac.type) {
4475 case ixgbe_mac_X540:
4476 case ixgbe_mac_X550:
4477 case ixgbe_mac_X550EM_x:
4478 dv_id = IXGBE_LOW_DV_X540(tc);
4479 break;
4480 default:
4481 dv_id = IXGBE_LOW_DV(tc);
4482 break;
4483 }
4484
4485 /* Delay value is calculated in bit times convert to KB */
4486 return IXGBE_BT2KB(dv_id);
4487 }
4488
4489 /*
4490 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4491 */
4492 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4493 {
4494 struct ixgbe_hw *hw = &adapter->hw;
4495 int num_tc = netdev_get_num_tc(adapter->netdev);
4496 int i;
4497
4498 if (!num_tc)
4499 num_tc = 1;
4500
4501 for (i = 0; i < num_tc; i++) {
4502 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4503 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
4504
4505 /* Low water marks must not be larger than high water marks */
4506 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4507 hw->fc.low_water[i] = 0;
4508 }
4509
4510 for (; i < MAX_TRAFFIC_CLASS; i++)
4511 hw->fc.high_water[i] = 0;
4512 }
4513
4514 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4515 {
4516 struct ixgbe_hw *hw = &adapter->hw;
4517 int hdrm;
4518 u8 tc = netdev_get_num_tc(adapter->netdev);
4519
4520 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4521 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4522 hdrm = 32 << adapter->fdir_pballoc;
4523 else
4524 hdrm = 0;
4525
4526 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4527 ixgbe_pbthresh_setup(adapter);
4528 }
4529
4530 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4531 {
4532 struct ixgbe_hw *hw = &adapter->hw;
4533 struct hlist_node *node2;
4534 struct ixgbe_fdir_filter *filter;
4535
4536 spin_lock(&adapter->fdir_perfect_lock);
4537
4538 if (!hlist_empty(&adapter->fdir_filter_list))
4539 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4540
4541 hlist_for_each_entry_safe(filter, node2,
4542 &adapter->fdir_filter_list, fdir_node) {
4543 ixgbe_fdir_write_perfect_filter_82599(hw,
4544 &filter->filter,
4545 filter->sw_idx,
4546 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4547 IXGBE_FDIR_DROP_QUEUE :
4548 adapter->rx_ring[filter->action]->reg_idx);
4549 }
4550
4551 spin_unlock(&adapter->fdir_perfect_lock);
4552 }
4553
4554 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4555 struct ixgbe_adapter *adapter)
4556 {
4557 struct ixgbe_hw *hw = &adapter->hw;
4558 u32 vmolr;
4559
4560 /* No unicast promiscuous support for VMDQ devices. */
4561 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4562 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4563
4564 /* clear the affected bit */
4565 vmolr &= ~IXGBE_VMOLR_MPE;
4566
4567 if (dev->flags & IFF_ALLMULTI) {
4568 vmolr |= IXGBE_VMOLR_MPE;
4569 } else {
4570 vmolr |= IXGBE_VMOLR_ROMPE;
4571 hw->mac.ops.update_mc_addr_list(hw, dev);
4572 }
4573 ixgbe_write_uc_addr_list(adapter->netdev, pool);
4574 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4575 }
4576
4577 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4578 {
4579 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4580 int rss_i = adapter->num_rx_queues_per_pool;
4581 struct ixgbe_hw *hw = &adapter->hw;
4582 u16 pool = vadapter->pool;
4583 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4584 IXGBE_PSRTYPE_UDPHDR |
4585 IXGBE_PSRTYPE_IPV4HDR |
4586 IXGBE_PSRTYPE_L2HDR |
4587 IXGBE_PSRTYPE_IPV6HDR;
4588
4589 if (hw->mac.type == ixgbe_mac_82598EB)
4590 return;
4591
4592 if (rss_i > 3)
4593 psrtype |= 2 << 29;
4594 else if (rss_i > 1)
4595 psrtype |= 1 << 29;
4596
4597 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4598 }
4599
4600 /**
4601 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4602 * @rx_ring: ring to free buffers from
4603 **/
4604 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4605 {
4606 struct device *dev = rx_ring->dev;
4607 unsigned long size;
4608 u16 i;
4609
4610 /* ring already cleared, nothing to do */
4611 if (!rx_ring->rx_buffer_info)
4612 return;
4613
4614 /* Free all the Rx ring sk_buffs */
4615 for (i = 0; i < rx_ring->count; i++) {
4616 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
4617
4618 if (rx_buffer->skb) {
4619 struct sk_buff *skb = rx_buffer->skb;
4620 if (IXGBE_CB(skb)->page_released)
4621 dma_unmap_page(dev,
4622 IXGBE_CB(skb)->dma,
4623 ixgbe_rx_bufsz(rx_ring),
4624 DMA_FROM_DEVICE);
4625 dev_kfree_skb(skb);
4626 rx_buffer->skb = NULL;
4627 }
4628
4629 if (!rx_buffer->page)
4630 continue;
4631
4632 dma_unmap_page(dev, rx_buffer->dma,
4633 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4634 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4635
4636 rx_buffer->page = NULL;
4637 }
4638
4639 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4640 memset(rx_ring->rx_buffer_info, 0, size);
4641
4642 /* Zero out the descriptor ring */
4643 memset(rx_ring->desc, 0, rx_ring->size);
4644
4645 rx_ring->next_to_alloc = 0;
4646 rx_ring->next_to_clean = 0;
4647 rx_ring->next_to_use = 0;
4648 }
4649
4650 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4651 struct ixgbe_ring *rx_ring)
4652 {
4653 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4654 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4655
4656 /* shutdown specific queue receive and wait for dma to settle */
4657 ixgbe_disable_rx_queue(adapter, rx_ring);
4658 usleep_range(10000, 20000);
4659 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4660 ixgbe_clean_rx_ring(rx_ring);
4661 rx_ring->l2_accel_priv = NULL;
4662 }
4663
4664 static int ixgbe_fwd_ring_down(struct net_device *vdev,
4665 struct ixgbe_fwd_adapter *accel)
4666 {
4667 struct ixgbe_adapter *adapter = accel->real_adapter;
4668 unsigned int rxbase = accel->rx_base_queue;
4669 unsigned int txbase = accel->tx_base_queue;
4670 int i;
4671
4672 netif_tx_stop_all_queues(vdev);
4673
4674 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4675 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4676 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4677 }
4678
4679 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4680 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4681 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4682 }
4683
4684
4685 return 0;
4686 }
4687
4688 static int ixgbe_fwd_ring_up(struct net_device *vdev,
4689 struct ixgbe_fwd_adapter *accel)
4690 {
4691 struct ixgbe_adapter *adapter = accel->real_adapter;
4692 unsigned int rxbase, txbase, queues;
4693 int i, baseq, err = 0;
4694
4695 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4696 return 0;
4697
4698 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4699 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4700 accel->pool, adapter->num_rx_pools,
4701 baseq, baseq + adapter->num_rx_queues_per_pool,
4702 adapter->fwd_bitmask);
4703
4704 accel->netdev = vdev;
4705 accel->rx_base_queue = rxbase = baseq;
4706 accel->tx_base_queue = txbase = baseq;
4707
4708 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4709 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4710
4711 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4712 adapter->rx_ring[rxbase + i]->netdev = vdev;
4713 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4714 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4715 }
4716
4717 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4718 adapter->tx_ring[txbase + i]->netdev = vdev;
4719 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4720 }
4721
4722 queues = min_t(unsigned int,
4723 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4724 err = netif_set_real_num_tx_queues(vdev, queues);
4725 if (err)
4726 goto fwd_queue_err;
4727
4728 err = netif_set_real_num_rx_queues(vdev, queues);
4729 if (err)
4730 goto fwd_queue_err;
4731
4732 if (is_valid_ether_addr(vdev->dev_addr))
4733 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4734
4735 ixgbe_fwd_psrtype(accel);
4736 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4737 return err;
4738 fwd_queue_err:
4739 ixgbe_fwd_ring_down(vdev, accel);
4740 return err;
4741 }
4742
4743 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4744 {
4745 struct net_device *upper;
4746 struct list_head *iter;
4747 int err;
4748
4749 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4750 if (netif_is_macvlan(upper)) {
4751 struct macvlan_dev *dfwd = netdev_priv(upper);
4752 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4753
4754 if (dfwd->fwd_priv) {
4755 err = ixgbe_fwd_ring_up(upper, vadapter);
4756 if (err)
4757 continue;
4758 }
4759 }
4760 }
4761 }
4762
4763 static void ixgbe_configure(struct ixgbe_adapter *adapter)
4764 {
4765 struct ixgbe_hw *hw = &adapter->hw;
4766
4767 ixgbe_configure_pb(adapter);
4768 #ifdef CONFIG_IXGBE_DCB
4769 ixgbe_configure_dcb(adapter);
4770 #endif
4771 /*
4772 * We must restore virtualization before VLANs or else
4773 * the VLVF registers will not be populated
4774 */
4775 ixgbe_configure_virtualization(adapter);
4776
4777 ixgbe_set_rx_mode(adapter->netdev);
4778 ixgbe_restore_vlan(adapter);
4779
4780 switch (hw->mac.type) {
4781 case ixgbe_mac_82599EB:
4782 case ixgbe_mac_X540:
4783 hw->mac.ops.disable_rx_buff(hw);
4784 break;
4785 default:
4786 break;
4787 }
4788
4789 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4790 ixgbe_init_fdir_signature_82599(&adapter->hw,
4791 adapter->fdir_pballoc);
4792 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4793 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4794 adapter->fdir_pballoc);
4795 ixgbe_fdir_filter_restore(adapter);
4796 }
4797
4798 switch (hw->mac.type) {
4799 case ixgbe_mac_82599EB:
4800 case ixgbe_mac_X540:
4801 hw->mac.ops.enable_rx_buff(hw);
4802 break;
4803 default:
4804 break;
4805 }
4806
4807 #ifdef CONFIG_IXGBE_DCA
4808 /* configure DCA */
4809 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
4810 ixgbe_setup_dca(adapter);
4811 #endif /* CONFIG_IXGBE_DCA */
4812
4813 #ifdef IXGBE_FCOE
4814 /* configure FCoE L2 filters, redirection table, and Rx control */
4815 ixgbe_configure_fcoe(adapter);
4816
4817 #endif /* IXGBE_FCOE */
4818 ixgbe_configure_tx(adapter);
4819 ixgbe_configure_rx(adapter);
4820 ixgbe_configure_dfwd(adapter);
4821 }
4822
4823 /**
4824 * ixgbe_sfp_link_config - set up SFP+ link
4825 * @adapter: pointer to private adapter struct
4826 **/
4827 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4828 {
4829 /*
4830 * We are assuming the worst case scenario here, and that
4831 * is that an SFP was inserted/removed after the reset
4832 * but before SFP detection was enabled. As such the best
4833 * solution is to just start searching as soon as we start
4834 */
4835 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4836 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4837
4838 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4839 adapter->sfp_poll_time = 0;
4840 }
4841
4842 /**
4843 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4844 * @hw: pointer to private hardware struct
4845 *
4846 * Returns 0 on success, negative on failure
4847 **/
4848 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4849 {
4850 u32 speed;
4851 bool autoneg, link_up = false;
4852 int ret = IXGBE_ERR_LINK_SETUP;
4853
4854 if (hw->mac.ops.check_link)
4855 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4856
4857 if (ret)
4858 return ret;
4859
4860 speed = hw->phy.autoneg_advertised;
4861 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4862 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4863 &autoneg);
4864 if (ret)
4865 return ret;
4866
4867 if (hw->mac.ops.setup_link)
4868 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4869
4870 return ret;
4871 }
4872
4873 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4874 {
4875 struct ixgbe_hw *hw = &adapter->hw;
4876 u32 gpie = 0;
4877
4878 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4879 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4880 IXGBE_GPIE_OCD;
4881 gpie |= IXGBE_GPIE_EIAME;
4882 /*
4883 * use EIAM to auto-mask when MSI-X interrupt is asserted
4884 * this saves a register write for every interrupt
4885 */
4886 switch (hw->mac.type) {
4887 case ixgbe_mac_82598EB:
4888 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4889 break;
4890 case ixgbe_mac_82599EB:
4891 case ixgbe_mac_X540:
4892 case ixgbe_mac_X550:
4893 case ixgbe_mac_X550EM_x:
4894 default:
4895 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4896 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4897 break;
4898 }
4899 } else {
4900 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4901 * specifically only auto mask tx and rx interrupts */
4902 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4903 }
4904
4905 /* XXX: to interrupt immediately for EICS writes, enable this */
4906 /* gpie |= IXGBE_GPIE_EIMEN; */
4907
4908 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4909 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4910
4911 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4912 case IXGBE_82599_VMDQ_8Q_MASK:
4913 gpie |= IXGBE_GPIE_VTMODE_16;
4914 break;
4915 case IXGBE_82599_VMDQ_4Q_MASK:
4916 gpie |= IXGBE_GPIE_VTMODE_32;
4917 break;
4918 default:
4919 gpie |= IXGBE_GPIE_VTMODE_64;
4920 break;
4921 }
4922 }
4923
4924 /* Enable Thermal over heat sensor interrupt */
4925 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4926 switch (adapter->hw.mac.type) {
4927 case ixgbe_mac_82599EB:
4928 gpie |= IXGBE_SDP0_GPIEN_8259X;
4929 break;
4930 default:
4931 break;
4932 }
4933 }
4934
4935 /* Enable fan failure interrupt */
4936 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4937 gpie |= IXGBE_SDP1_GPIEN(hw);
4938
4939 switch (hw->mac.type) {
4940 case ixgbe_mac_82599EB:
4941 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
4942 break;
4943 case ixgbe_mac_X550EM_x:
4944 gpie |= IXGBE_SDP0_GPIEN_X540;
4945 break;
4946 default:
4947 break;
4948 }
4949
4950 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4951 }
4952
4953 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4954 {
4955 struct ixgbe_hw *hw = &adapter->hw;
4956 int err;
4957 u32 ctrl_ext;
4958
4959 ixgbe_get_hw_control(adapter);
4960 ixgbe_setup_gpie(adapter);
4961
4962 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4963 ixgbe_configure_msix(adapter);
4964 else
4965 ixgbe_configure_msi_and_legacy(adapter);
4966
4967 /* enable the optics for 82599 SFP+ fiber */
4968 if (hw->mac.ops.enable_tx_laser)
4969 hw->mac.ops.enable_tx_laser(hw);
4970
4971 if (hw->phy.ops.set_phy_power)
4972 hw->phy.ops.set_phy_power(hw, true);
4973
4974 smp_mb__before_atomic();
4975 clear_bit(__IXGBE_DOWN, &adapter->state);
4976 ixgbe_napi_enable_all(adapter);
4977
4978 if (ixgbe_is_sfp(hw)) {
4979 ixgbe_sfp_link_config(adapter);
4980 } else {
4981 err = ixgbe_non_sfp_link_config(hw);
4982 if (err)
4983 e_err(probe, "link_config FAILED %d\n", err);
4984 }
4985
4986 /* clear any pending interrupts, may auto mask */
4987 IXGBE_READ_REG(hw, IXGBE_EICR);
4988 ixgbe_irq_enable(adapter, true, true);
4989
4990 /*
4991 * If this adapter has a fan, check to see if we had a failure
4992 * before we enabled the interrupt.
4993 */
4994 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4995 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4996 if (esdp & IXGBE_ESDP_SDP1)
4997 e_crit(drv, "Fan has stopped, replace the adapter\n");
4998 }
4999
5000 /* bring the link up in the watchdog, this could race with our first
5001 * link up interrupt but shouldn't be a problem */
5002 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5003 adapter->link_check_timeout = jiffies;
5004 mod_timer(&adapter->service_timer, jiffies);
5005
5006 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5007 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5008 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5009 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5010 }
5011
5012 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5013 {
5014 WARN_ON(in_interrupt());
5015 /* put off any impending NetWatchDogTimeout */
5016 adapter->netdev->trans_start = jiffies;
5017
5018 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
5019 usleep_range(1000, 2000);
5020 ixgbe_down(adapter);
5021 /*
5022 * If SR-IOV enabled then wait a bit before bringing the adapter
5023 * back up to give the VFs time to respond to the reset. The
5024 * two second wait is based upon the watchdog timer cycle in
5025 * the VF driver.
5026 */
5027 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5028 msleep(2000);
5029 ixgbe_up(adapter);
5030 clear_bit(__IXGBE_RESETTING, &adapter->state);
5031 }
5032
5033 void ixgbe_up(struct ixgbe_adapter *adapter)
5034 {
5035 /* hardware has been reset, we need to reload some things */
5036 ixgbe_configure(adapter);
5037
5038 ixgbe_up_complete(adapter);
5039 }
5040
5041 void ixgbe_reset(struct ixgbe_adapter *adapter)
5042 {
5043 struct ixgbe_hw *hw = &adapter->hw;
5044 struct net_device *netdev = adapter->netdev;
5045 int err;
5046 u8 old_addr[ETH_ALEN];
5047
5048 if (ixgbe_removed(hw->hw_addr))
5049 return;
5050 /* lock SFP init bit to prevent race conditions with the watchdog */
5051 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5052 usleep_range(1000, 2000);
5053
5054 /* clear all SFP and link config related flags while holding SFP_INIT */
5055 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5056 IXGBE_FLAG2_SFP_NEEDS_RESET);
5057 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5058
5059 err = hw->mac.ops.init_hw(hw);
5060 switch (err) {
5061 case 0:
5062 case IXGBE_ERR_SFP_NOT_PRESENT:
5063 case IXGBE_ERR_SFP_NOT_SUPPORTED:
5064 break;
5065 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
5066 e_dev_err("master disable timed out\n");
5067 break;
5068 case IXGBE_ERR_EEPROM_VERSION:
5069 /* We are running on a pre-production device, log a warning */
5070 e_dev_warn("This device is a pre-production adapter/LOM. "
5071 "Please be aware there may be issues associated with "
5072 "your hardware. If you are experiencing problems "
5073 "please contact your Intel or hardware "
5074 "representative who provided you with this "
5075 "hardware.\n");
5076 break;
5077 default:
5078 e_dev_err("Hardware Error: %d\n", err);
5079 }
5080
5081 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5082 /* do not flush user set addresses */
5083 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
5084 ixgbe_flush_sw_mac_table(adapter);
5085 ixgbe_mac_set_default_filter(adapter, old_addr);
5086
5087 /* update SAN MAC vmdq pool selection */
5088 if (hw->mac.san_mac_rar_index)
5089 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
5090
5091 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5092 ixgbe_ptp_reset(adapter);
5093
5094 if (hw->phy.ops.set_phy_power) {
5095 if (!netif_running(adapter->netdev) && !adapter->wol)
5096 hw->phy.ops.set_phy_power(hw, false);
5097 else
5098 hw->phy.ops.set_phy_power(hw, true);
5099 }
5100 }
5101
5102 /**
5103 * ixgbe_clean_tx_ring - Free Tx Buffers
5104 * @tx_ring: ring to be cleaned
5105 **/
5106 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
5107 {
5108 struct ixgbe_tx_buffer *tx_buffer_info;
5109 unsigned long size;
5110 u16 i;
5111
5112 /* ring already cleared, nothing to do */
5113 if (!tx_ring->tx_buffer_info)
5114 return;
5115
5116 /* Free all the Tx ring sk_buffs */
5117 for (i = 0; i < tx_ring->count; i++) {
5118 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5119 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
5120 }
5121
5122 netdev_tx_reset_queue(txring_txq(tx_ring));
5123
5124 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5125 memset(tx_ring->tx_buffer_info, 0, size);
5126
5127 /* Zero out the descriptor ring */
5128 memset(tx_ring->desc, 0, tx_ring->size);
5129
5130 tx_ring->next_to_use = 0;
5131 tx_ring->next_to_clean = 0;
5132 }
5133
5134 /**
5135 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
5136 * @adapter: board private structure
5137 **/
5138 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
5139 {
5140 int i;
5141
5142 for (i = 0; i < adapter->num_rx_queues; i++)
5143 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
5144 }
5145
5146 /**
5147 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
5148 * @adapter: board private structure
5149 **/
5150 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
5151 {
5152 int i;
5153
5154 for (i = 0; i < adapter->num_tx_queues; i++)
5155 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
5156 }
5157
5158 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5159 {
5160 struct hlist_node *node2;
5161 struct ixgbe_fdir_filter *filter;
5162
5163 spin_lock(&adapter->fdir_perfect_lock);
5164
5165 hlist_for_each_entry_safe(filter, node2,
5166 &adapter->fdir_filter_list, fdir_node) {
5167 hlist_del(&filter->fdir_node);
5168 kfree(filter);
5169 }
5170 adapter->fdir_filter_count = 0;
5171
5172 spin_unlock(&adapter->fdir_perfect_lock);
5173 }
5174
5175 void ixgbe_down(struct ixgbe_adapter *adapter)
5176 {
5177 struct net_device *netdev = adapter->netdev;
5178 struct ixgbe_hw *hw = &adapter->hw;
5179 struct net_device *upper;
5180 struct list_head *iter;
5181 int i;
5182
5183 /* signal that we are down to the interrupt handler */
5184 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5185 return; /* do nothing if already down */
5186
5187 /* disable receives */
5188 hw->mac.ops.disable_rx(hw);
5189
5190 /* disable all enabled rx queues */
5191 for (i = 0; i < adapter->num_rx_queues; i++)
5192 /* this call also flushes the previous write */
5193 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5194
5195 usleep_range(10000, 20000);
5196
5197 netif_tx_stop_all_queues(netdev);
5198
5199 /* call carrier off first to avoid false dev_watchdog timeouts */
5200 netif_carrier_off(netdev);
5201 netif_tx_disable(netdev);
5202
5203 /* disable any upper devices */
5204 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5205 if (netif_is_macvlan(upper)) {
5206 struct macvlan_dev *vlan = netdev_priv(upper);
5207
5208 if (vlan->fwd_priv) {
5209 netif_tx_stop_all_queues(upper);
5210 netif_carrier_off(upper);
5211 netif_tx_disable(upper);
5212 }
5213 }
5214 }
5215
5216 ixgbe_irq_disable(adapter);
5217
5218 ixgbe_napi_disable_all(adapter);
5219
5220 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5221 IXGBE_FLAG2_RESET_REQUESTED);
5222 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5223
5224 del_timer_sync(&adapter->service_timer);
5225
5226 if (adapter->num_vfs) {
5227 /* Clear EITR Select mapping */
5228 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
5229
5230 /* Mark all the VFs as inactive */
5231 for (i = 0 ; i < adapter->num_vfs; i++)
5232 adapter->vfinfo[i].clear_to_send = false;
5233
5234 /* ping all the active vfs to let them know we are going down */
5235 ixgbe_ping_all_vfs(adapter);
5236
5237 /* Disable all VFTE/VFRE TX/RX */
5238 ixgbe_disable_tx_rx(adapter);
5239 }
5240
5241 /* disable transmits in the hardware now that interrupts are off */
5242 for (i = 0; i < adapter->num_tx_queues; i++) {
5243 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
5244 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5245 }
5246
5247 /* Disable the Tx DMA engine on 82599 and later MAC */
5248 switch (hw->mac.type) {
5249 case ixgbe_mac_82599EB:
5250 case ixgbe_mac_X540:
5251 case ixgbe_mac_X550:
5252 case ixgbe_mac_X550EM_x:
5253 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5254 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5255 ~IXGBE_DMATXCTL_TE));
5256 break;
5257 default:
5258 break;
5259 }
5260
5261 if (!pci_channel_offline(adapter->pdev))
5262 ixgbe_reset(adapter);
5263
5264 /* power down the optics for 82599 SFP+ fiber */
5265 if (hw->mac.ops.disable_tx_laser)
5266 hw->mac.ops.disable_tx_laser(hw);
5267
5268 ixgbe_clean_all_tx_rings(adapter);
5269 ixgbe_clean_all_rx_rings(adapter);
5270 }
5271
5272 /**
5273 * ixgbe_tx_timeout - Respond to a Tx Hang
5274 * @netdev: network interface device structure
5275 **/
5276 static void ixgbe_tx_timeout(struct net_device *netdev)
5277 {
5278 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5279
5280 /* Do the reset outside of interrupt context */
5281 ixgbe_tx_timeout_reset(adapter);
5282 }
5283
5284 /**
5285 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5286 * @adapter: board private structure to initialize
5287 *
5288 * ixgbe_sw_init initializes the Adapter private data structure.
5289 * Fields are initialized based on PCI device information and
5290 * OS network device settings (MTU size).
5291 **/
5292 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
5293 {
5294 struct ixgbe_hw *hw = &adapter->hw;
5295 struct pci_dev *pdev = adapter->pdev;
5296 unsigned int rss, fdir;
5297 u32 fwsm;
5298 #ifdef CONFIG_IXGBE_DCB
5299 int j;
5300 struct tc_configuration *tc;
5301 #endif
5302
5303 /* PCI config space info */
5304
5305 hw->vendor_id = pdev->vendor;
5306 hw->device_id = pdev->device;
5307 hw->revision_id = pdev->revision;
5308 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5309 hw->subsystem_device_id = pdev->subsystem_device;
5310
5311 /* Set common capability flags and settings */
5312 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
5313 adapter->ring_feature[RING_F_RSS].limit = rss;
5314 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5315 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5316 adapter->atr_sample_rate = 20;
5317 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5318 adapter->ring_feature[RING_F_FDIR].limit = fdir;
5319 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5320 #ifdef CONFIG_IXGBE_DCA
5321 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5322 #endif
5323 #ifdef IXGBE_FCOE
5324 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5325 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5326 #ifdef CONFIG_IXGBE_DCB
5327 /* Default traffic class to use for FCoE */
5328 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5329 #endif /* CONFIG_IXGBE_DCB */
5330 #endif /* IXGBE_FCOE */
5331
5332 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5333 hw->mac.num_rar_entries,
5334 GFP_ATOMIC);
5335
5336 /* Set MAC specific capability flags and exceptions */
5337 switch (hw->mac.type) {
5338 case ixgbe_mac_82598EB:
5339 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5340
5341 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5342 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5343
5344 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
5345 adapter->ring_feature[RING_F_FDIR].limit = 0;
5346 adapter->atr_sample_rate = 0;
5347 adapter->fdir_pballoc = 0;
5348 #ifdef IXGBE_FCOE
5349 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5350 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5351 #ifdef CONFIG_IXGBE_DCB
5352 adapter->fcoe.up = 0;
5353 #endif /* IXGBE_DCB */
5354 #endif /* IXGBE_FCOE */
5355 break;
5356 case ixgbe_mac_82599EB:
5357 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5358 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5359 break;
5360 case ixgbe_mac_X540:
5361 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
5362 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5363 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5364 break;
5365 case ixgbe_mac_X550EM_x:
5366 case ixgbe_mac_X550:
5367 #ifdef CONFIG_IXGBE_DCA
5368 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
5369 #endif
5370 #ifdef CONFIG_IXGBE_VXLAN
5371 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
5372 #endif
5373 break;
5374 default:
5375 break;
5376 }
5377
5378 #ifdef IXGBE_FCOE
5379 /* FCoE support exists, always init the FCoE lock */
5380 spin_lock_init(&adapter->fcoe.lock);
5381
5382 #endif
5383 /* n-tuple support exists, always init our spinlock */
5384 spin_lock_init(&adapter->fdir_perfect_lock);
5385
5386 #ifdef CONFIG_IXGBE_DCB
5387 switch (hw->mac.type) {
5388 case ixgbe_mac_X540:
5389 case ixgbe_mac_X550:
5390 case ixgbe_mac_X550EM_x:
5391 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5392 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5393 break;
5394 default:
5395 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5396 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5397 break;
5398 }
5399
5400 /* Configure DCB traffic classes */
5401 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5402 tc = &adapter->dcb_cfg.tc_config[j];
5403 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5404 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5405 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5406 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5407 tc->dcb_pfc = pfc_disabled;
5408 }
5409
5410 /* Initialize default user to priority mapping, UPx->TC0 */
5411 tc = &adapter->dcb_cfg.tc_config[0];
5412 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5413 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5414
5415 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5416 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5417 adapter->dcb_cfg.pfc_mode_enable = false;
5418 adapter->dcb_set_bitmap = 0x00;
5419 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5420 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5421 sizeof(adapter->temp_dcb_cfg));
5422
5423 #endif
5424
5425 /* default flow control settings */
5426 hw->fc.requested_mode = ixgbe_fc_full;
5427 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5428 ixgbe_pbthresh_setup(adapter);
5429 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5430 hw->fc.send_xon = true;
5431 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
5432
5433 #ifdef CONFIG_PCI_IOV
5434 if (max_vfs > 0)
5435 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5436
5437 /* assign number of SR-IOV VFs */
5438 if (hw->mac.type != ixgbe_mac_82598EB) {
5439 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
5440 adapter->num_vfs = 0;
5441 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5442 } else {
5443 adapter->num_vfs = max_vfs;
5444 }
5445 }
5446 #endif /* CONFIG_PCI_IOV */
5447
5448 /* enable itr by default in dynamic mode */
5449 adapter->rx_itr_setting = 1;
5450 adapter->tx_itr_setting = 1;
5451
5452 /* set default ring sizes */
5453 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5454 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5455
5456 /* set default work limits */
5457 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5458
5459 /* initialize eeprom parameters */
5460 if (ixgbe_init_eeprom_params_generic(hw)) {
5461 e_dev_err("EEPROM initialization failed\n");
5462 return -EIO;
5463 }
5464
5465 /* PF holds first pool slot */
5466 set_bit(0, &adapter->fwd_bitmask);
5467 set_bit(__IXGBE_DOWN, &adapter->state);
5468
5469 return 0;
5470 }
5471
5472 /**
5473 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5474 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5475 *
5476 * Return 0 on success, negative on failure
5477 **/
5478 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5479 {
5480 struct device *dev = tx_ring->dev;
5481 int orig_node = dev_to_node(dev);
5482 int ring_node = -1;
5483 int size;
5484
5485 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5486
5487 if (tx_ring->q_vector)
5488 ring_node = tx_ring->q_vector->numa_node;
5489
5490 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
5491 if (!tx_ring->tx_buffer_info)
5492 tx_ring->tx_buffer_info = vzalloc(size);
5493 if (!tx_ring->tx_buffer_info)
5494 goto err;
5495
5496 u64_stats_init(&tx_ring->syncp);
5497
5498 /* round up to nearest 4K */
5499 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5500 tx_ring->size = ALIGN(tx_ring->size, 4096);
5501
5502 set_dev_node(dev, ring_node);
5503 tx_ring->desc = dma_alloc_coherent(dev,
5504 tx_ring->size,
5505 &tx_ring->dma,
5506 GFP_KERNEL);
5507 set_dev_node(dev, orig_node);
5508 if (!tx_ring->desc)
5509 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5510 &tx_ring->dma, GFP_KERNEL);
5511 if (!tx_ring->desc)
5512 goto err;
5513
5514 tx_ring->next_to_use = 0;
5515 tx_ring->next_to_clean = 0;
5516 return 0;
5517
5518 err:
5519 vfree(tx_ring->tx_buffer_info);
5520 tx_ring->tx_buffer_info = NULL;
5521 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5522 return -ENOMEM;
5523 }
5524
5525 /**
5526 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5527 * @adapter: board private structure
5528 *
5529 * If this function returns with an error, then it's possible one or
5530 * more of the rings is populated (while the rest are not). It is the
5531 * callers duty to clean those orphaned rings.
5532 *
5533 * Return 0 on success, negative on failure
5534 **/
5535 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5536 {
5537 int i, err = 0;
5538
5539 for (i = 0; i < adapter->num_tx_queues; i++) {
5540 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5541 if (!err)
5542 continue;
5543
5544 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5545 goto err_setup_tx;
5546 }
5547
5548 return 0;
5549 err_setup_tx:
5550 /* rewind the index freeing the rings as we go */
5551 while (i--)
5552 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5553 return err;
5554 }
5555
5556 /**
5557 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5558 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5559 *
5560 * Returns 0 on success, negative on failure
5561 **/
5562 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5563 {
5564 struct device *dev = rx_ring->dev;
5565 int orig_node = dev_to_node(dev);
5566 int ring_node = -1;
5567 int size;
5568
5569 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5570
5571 if (rx_ring->q_vector)
5572 ring_node = rx_ring->q_vector->numa_node;
5573
5574 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
5575 if (!rx_ring->rx_buffer_info)
5576 rx_ring->rx_buffer_info = vzalloc(size);
5577 if (!rx_ring->rx_buffer_info)
5578 goto err;
5579
5580 u64_stats_init(&rx_ring->syncp);
5581
5582 /* Round up to nearest 4K */
5583 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5584 rx_ring->size = ALIGN(rx_ring->size, 4096);
5585
5586 set_dev_node(dev, ring_node);
5587 rx_ring->desc = dma_alloc_coherent(dev,
5588 rx_ring->size,
5589 &rx_ring->dma,
5590 GFP_KERNEL);
5591 set_dev_node(dev, orig_node);
5592 if (!rx_ring->desc)
5593 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5594 &rx_ring->dma, GFP_KERNEL);
5595 if (!rx_ring->desc)
5596 goto err;
5597
5598 rx_ring->next_to_clean = 0;
5599 rx_ring->next_to_use = 0;
5600
5601 return 0;
5602 err:
5603 vfree(rx_ring->rx_buffer_info);
5604 rx_ring->rx_buffer_info = NULL;
5605 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5606 return -ENOMEM;
5607 }
5608
5609 /**
5610 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5611 * @adapter: board private structure
5612 *
5613 * If this function returns with an error, then it's possible one or
5614 * more of the rings is populated (while the rest are not). It is the
5615 * callers duty to clean those orphaned rings.
5616 *
5617 * Return 0 on success, negative on failure
5618 **/
5619 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5620 {
5621 int i, err = 0;
5622
5623 for (i = 0; i < adapter->num_rx_queues; i++) {
5624 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5625 if (!err)
5626 continue;
5627
5628 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5629 goto err_setup_rx;
5630 }
5631
5632 #ifdef IXGBE_FCOE
5633 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5634 if (!err)
5635 #endif
5636 return 0;
5637 err_setup_rx:
5638 /* rewind the index freeing the rings as we go */
5639 while (i--)
5640 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5641 return err;
5642 }
5643
5644 /**
5645 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5646 * @tx_ring: Tx descriptor ring for a specific queue
5647 *
5648 * Free all transmit software resources
5649 **/
5650 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5651 {
5652 ixgbe_clean_tx_ring(tx_ring);
5653
5654 vfree(tx_ring->tx_buffer_info);
5655 tx_ring->tx_buffer_info = NULL;
5656
5657 /* if not set, then don't free */
5658 if (!tx_ring->desc)
5659 return;
5660
5661 dma_free_coherent(tx_ring->dev, tx_ring->size,
5662 tx_ring->desc, tx_ring->dma);
5663
5664 tx_ring->desc = NULL;
5665 }
5666
5667 /**
5668 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5669 * @adapter: board private structure
5670 *
5671 * Free all transmit software resources
5672 **/
5673 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5674 {
5675 int i;
5676
5677 for (i = 0; i < adapter->num_tx_queues; i++)
5678 if (adapter->tx_ring[i]->desc)
5679 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5680 }
5681
5682 /**
5683 * ixgbe_free_rx_resources - Free Rx Resources
5684 * @rx_ring: ring to clean the resources from
5685 *
5686 * Free all receive software resources
5687 **/
5688 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5689 {
5690 ixgbe_clean_rx_ring(rx_ring);
5691
5692 vfree(rx_ring->rx_buffer_info);
5693 rx_ring->rx_buffer_info = NULL;
5694
5695 /* if not set, then don't free */
5696 if (!rx_ring->desc)
5697 return;
5698
5699 dma_free_coherent(rx_ring->dev, rx_ring->size,
5700 rx_ring->desc, rx_ring->dma);
5701
5702 rx_ring->desc = NULL;
5703 }
5704
5705 /**
5706 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5707 * @adapter: board private structure
5708 *
5709 * Free all receive software resources
5710 **/
5711 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5712 {
5713 int i;
5714
5715 #ifdef IXGBE_FCOE
5716 ixgbe_free_fcoe_ddp_resources(adapter);
5717
5718 #endif
5719 for (i = 0; i < adapter->num_rx_queues; i++)
5720 if (adapter->rx_ring[i]->desc)
5721 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5722 }
5723
5724 /**
5725 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5726 * @netdev: network interface device structure
5727 * @new_mtu: new value for maximum frame size
5728 *
5729 * Returns 0 on success, negative on failure
5730 **/
5731 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5732 {
5733 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5734 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5735
5736 /* MTU < 68 is an error and causes problems on some kernels */
5737 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5738 return -EINVAL;
5739
5740 /*
5741 * For 82599EB we cannot allow legacy VFs to enable their receive
5742 * paths when MTU greater than 1500 is configured. So display a
5743 * warning that legacy VFs will be disabled.
5744 */
5745 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5746 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5747 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
5748 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
5749
5750 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5751
5752 /* must set new MTU before calling down or up */
5753 netdev->mtu = new_mtu;
5754
5755 if (netif_running(netdev))
5756 ixgbe_reinit_locked(adapter);
5757
5758 return 0;
5759 }
5760
5761 /**
5762 * ixgbe_open - Called when a network interface is made active
5763 * @netdev: network interface device structure
5764 *
5765 * Returns 0 on success, negative value on failure
5766 *
5767 * The open entry point is called when a network interface is made
5768 * active by the system (IFF_UP). At this point all resources needed
5769 * for transmit and receive operations are allocated, the interrupt
5770 * handler is registered with the OS, the watchdog timer is started,
5771 * and the stack is notified that the interface is ready.
5772 **/
5773 static int ixgbe_open(struct net_device *netdev)
5774 {
5775 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5776 struct ixgbe_hw *hw = &adapter->hw;
5777 int err, queues;
5778
5779 /* disallow open during test */
5780 if (test_bit(__IXGBE_TESTING, &adapter->state))
5781 return -EBUSY;
5782
5783 netif_carrier_off(netdev);
5784
5785 /* allocate transmit descriptors */
5786 err = ixgbe_setup_all_tx_resources(adapter);
5787 if (err)
5788 goto err_setup_tx;
5789
5790 /* allocate receive descriptors */
5791 err = ixgbe_setup_all_rx_resources(adapter);
5792 if (err)
5793 goto err_setup_rx;
5794
5795 ixgbe_configure(adapter);
5796
5797 err = ixgbe_request_irq(adapter);
5798 if (err)
5799 goto err_req_irq;
5800
5801 /* Notify the stack of the actual queue counts. */
5802 if (adapter->num_rx_pools > 1)
5803 queues = adapter->num_rx_queues_per_pool;
5804 else
5805 queues = adapter->num_tx_queues;
5806
5807 err = netif_set_real_num_tx_queues(netdev, queues);
5808 if (err)
5809 goto err_set_queues;
5810
5811 if (adapter->num_rx_pools > 1 &&
5812 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5813 queues = IXGBE_MAX_L2A_QUEUES;
5814 else
5815 queues = adapter->num_rx_queues;
5816 err = netif_set_real_num_rx_queues(netdev, queues);
5817 if (err)
5818 goto err_set_queues;
5819
5820 ixgbe_ptp_init(adapter);
5821
5822 ixgbe_up_complete(adapter);
5823
5824 ixgbe_clear_vxlan_port(adapter);
5825 #ifdef CONFIG_IXGBE_VXLAN
5826 vxlan_get_rx_port(netdev);
5827 #endif
5828
5829 return 0;
5830
5831 err_set_queues:
5832 ixgbe_free_irq(adapter);
5833 err_req_irq:
5834 ixgbe_free_all_rx_resources(adapter);
5835 if (hw->phy.ops.set_phy_power && !adapter->wol)
5836 hw->phy.ops.set_phy_power(&adapter->hw, false);
5837 err_setup_rx:
5838 ixgbe_free_all_tx_resources(adapter);
5839 err_setup_tx:
5840 ixgbe_reset(adapter);
5841
5842 return err;
5843 }
5844
5845 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5846 {
5847 ixgbe_ptp_suspend(adapter);
5848
5849 if (adapter->hw.phy.ops.enter_lplu) {
5850 adapter->hw.phy.reset_disable = true;
5851 ixgbe_down(adapter);
5852 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
5853 adapter->hw.phy.reset_disable = false;
5854 } else {
5855 ixgbe_down(adapter);
5856 }
5857
5858 ixgbe_free_irq(adapter);
5859
5860 ixgbe_free_all_tx_resources(adapter);
5861 ixgbe_free_all_rx_resources(adapter);
5862 }
5863
5864 /**
5865 * ixgbe_close - Disables a network interface
5866 * @netdev: network interface device structure
5867 *
5868 * Returns 0, this is not allowed to fail
5869 *
5870 * The close entry point is called when an interface is de-activated
5871 * by the OS. The hardware is still under the drivers control, but
5872 * needs to be disabled. A global MAC reset is issued to stop the
5873 * hardware, and all transmit and receive resources are freed.
5874 **/
5875 static int ixgbe_close(struct net_device *netdev)
5876 {
5877 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5878
5879 ixgbe_ptp_stop(adapter);
5880
5881 if (netif_device_present(netdev))
5882 ixgbe_close_suspend(adapter);
5883
5884 ixgbe_fdir_filter_exit(adapter);
5885
5886 ixgbe_release_hw_control(adapter);
5887
5888 return 0;
5889 }
5890
5891 #ifdef CONFIG_PM
5892 static int ixgbe_resume(struct pci_dev *pdev)
5893 {
5894 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5895 struct net_device *netdev = adapter->netdev;
5896 u32 err;
5897
5898 adapter->hw.hw_addr = adapter->io_addr;
5899 pci_set_power_state(pdev, PCI_D0);
5900 pci_restore_state(pdev);
5901 /*
5902 * pci_restore_state clears dev->state_saved so call
5903 * pci_save_state to restore it.
5904 */
5905 pci_save_state(pdev);
5906
5907 err = pci_enable_device_mem(pdev);
5908 if (err) {
5909 e_dev_err("Cannot enable PCI device from suspend\n");
5910 return err;
5911 }
5912 smp_mb__before_atomic();
5913 clear_bit(__IXGBE_DISABLED, &adapter->state);
5914 pci_set_master(pdev);
5915
5916 pci_wake_from_d3(pdev, false);
5917
5918 ixgbe_reset(adapter);
5919
5920 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5921
5922 rtnl_lock();
5923 err = ixgbe_init_interrupt_scheme(adapter);
5924 if (!err && netif_running(netdev))
5925 err = ixgbe_open(netdev);
5926
5927
5928 if (!err)
5929 netif_device_attach(netdev);
5930 rtnl_unlock();
5931
5932 return err;
5933 }
5934 #endif /* CONFIG_PM */
5935
5936 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5937 {
5938 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5939 struct net_device *netdev = adapter->netdev;
5940 struct ixgbe_hw *hw = &adapter->hw;
5941 u32 ctrl, fctrl;
5942 u32 wufc = adapter->wol;
5943 #ifdef CONFIG_PM
5944 int retval = 0;
5945 #endif
5946
5947 rtnl_lock();
5948 netif_device_detach(netdev);
5949
5950 if (netif_running(netdev))
5951 ixgbe_close_suspend(adapter);
5952
5953 ixgbe_clear_interrupt_scheme(adapter);
5954 rtnl_unlock();
5955
5956 #ifdef CONFIG_PM
5957 retval = pci_save_state(pdev);
5958 if (retval)
5959 return retval;
5960
5961 #endif
5962 if (hw->mac.ops.stop_link_on_d3)
5963 hw->mac.ops.stop_link_on_d3(hw);
5964
5965 if (wufc) {
5966 ixgbe_set_rx_mode(netdev);
5967
5968 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5969 if (hw->mac.ops.enable_tx_laser)
5970 hw->mac.ops.enable_tx_laser(hw);
5971
5972 /* turn on all-multi mode if wake on multicast is enabled */
5973 if (wufc & IXGBE_WUFC_MC) {
5974 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5975 fctrl |= IXGBE_FCTRL_MPE;
5976 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5977 }
5978
5979 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5980 ctrl |= IXGBE_CTRL_GIO_DIS;
5981 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5982
5983 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5984 } else {
5985 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5986 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5987 }
5988
5989 switch (hw->mac.type) {
5990 case ixgbe_mac_82598EB:
5991 pci_wake_from_d3(pdev, false);
5992 break;
5993 case ixgbe_mac_82599EB:
5994 case ixgbe_mac_X540:
5995 case ixgbe_mac_X550:
5996 case ixgbe_mac_X550EM_x:
5997 pci_wake_from_d3(pdev, !!wufc);
5998 break;
5999 default:
6000 break;
6001 }
6002
6003 *enable_wake = !!wufc;
6004 if (hw->phy.ops.set_phy_power && !*enable_wake)
6005 hw->phy.ops.set_phy_power(hw, false);
6006
6007 ixgbe_release_hw_control(adapter);
6008
6009 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6010 pci_disable_device(pdev);
6011
6012 return 0;
6013 }
6014
6015 #ifdef CONFIG_PM
6016 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6017 {
6018 int retval;
6019 bool wake;
6020
6021 retval = __ixgbe_shutdown(pdev, &wake);
6022 if (retval)
6023 return retval;
6024
6025 if (wake) {
6026 pci_prepare_to_sleep(pdev);
6027 } else {
6028 pci_wake_from_d3(pdev, false);
6029 pci_set_power_state(pdev, PCI_D3hot);
6030 }
6031
6032 return 0;
6033 }
6034 #endif /* CONFIG_PM */
6035
6036 static void ixgbe_shutdown(struct pci_dev *pdev)
6037 {
6038 bool wake;
6039
6040 __ixgbe_shutdown(pdev, &wake);
6041
6042 if (system_state == SYSTEM_POWER_OFF) {
6043 pci_wake_from_d3(pdev, wake);
6044 pci_set_power_state(pdev, PCI_D3hot);
6045 }
6046 }
6047
6048 /**
6049 * ixgbe_update_stats - Update the board statistics counters.
6050 * @adapter: board private structure
6051 **/
6052 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6053 {
6054 struct net_device *netdev = adapter->netdev;
6055 struct ixgbe_hw *hw = &adapter->hw;
6056 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6057 u64 total_mpc = 0;
6058 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
6059 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6060 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
6061 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
6062
6063 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6064 test_bit(__IXGBE_RESETTING, &adapter->state))
6065 return;
6066
6067 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
6068 u64 rsc_count = 0;
6069 u64 rsc_flush = 0;
6070 for (i = 0; i < adapter->num_rx_queues; i++) {
6071 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6072 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
6073 }
6074 adapter->rsc_total_count = rsc_count;
6075 adapter->rsc_total_flush = rsc_flush;
6076 }
6077
6078 for (i = 0; i < adapter->num_rx_queues; i++) {
6079 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6080 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6081 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6082 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
6083 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
6084 bytes += rx_ring->stats.bytes;
6085 packets += rx_ring->stats.packets;
6086 }
6087 adapter->non_eop_descs = non_eop_descs;
6088 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6089 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
6090 adapter->hw_csum_rx_error = hw_csum_rx_error;
6091 netdev->stats.rx_bytes = bytes;
6092 netdev->stats.rx_packets = packets;
6093
6094 bytes = 0;
6095 packets = 0;
6096 /* gather some stats to the adapter struct that are per queue */
6097 for (i = 0; i < adapter->num_tx_queues; i++) {
6098 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6099 restart_queue += tx_ring->tx_stats.restart_queue;
6100 tx_busy += tx_ring->tx_stats.tx_busy;
6101 bytes += tx_ring->stats.bytes;
6102 packets += tx_ring->stats.packets;
6103 }
6104 adapter->restart_queue = restart_queue;
6105 adapter->tx_busy = tx_busy;
6106 netdev->stats.tx_bytes = bytes;
6107 netdev->stats.tx_packets = packets;
6108
6109 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6110
6111 /* 8 register reads */
6112 for (i = 0; i < 8; i++) {
6113 /* for packet buffers not used, the register should read 0 */
6114 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6115 missed_rx += mpc;
6116 hwstats->mpc[i] += mpc;
6117 total_mpc += hwstats->mpc[i];
6118 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6119 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6120 switch (hw->mac.type) {
6121 case ixgbe_mac_82598EB:
6122 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6123 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6124 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
6125 hwstats->pxonrxc[i] +=
6126 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
6127 break;
6128 case ixgbe_mac_82599EB:
6129 case ixgbe_mac_X540:
6130 case ixgbe_mac_X550:
6131 case ixgbe_mac_X550EM_x:
6132 hwstats->pxonrxc[i] +=
6133 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
6134 break;
6135 default:
6136 break;
6137 }
6138 }
6139
6140 /*16 register reads */
6141 for (i = 0; i < 16; i++) {
6142 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6143 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6144 if ((hw->mac.type == ixgbe_mac_82599EB) ||
6145 (hw->mac.type == ixgbe_mac_X540) ||
6146 (hw->mac.type == ixgbe_mac_X550) ||
6147 (hw->mac.type == ixgbe_mac_X550EM_x)) {
6148 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6149 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6150 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6151 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6152 }
6153 }
6154
6155 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6156 /* work around hardware counting issue */
6157 hwstats->gprc -= missed_rx;
6158
6159 ixgbe_update_xoff_received(adapter);
6160
6161 /* 82598 hardware only has a 32 bit counter in the high register */
6162 switch (hw->mac.type) {
6163 case ixgbe_mac_82598EB:
6164 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
6165 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6166 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6167 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6168 break;
6169 case ixgbe_mac_X540:
6170 case ixgbe_mac_X550:
6171 case ixgbe_mac_X550EM_x:
6172 /* OS2BMC stats are X540 and later */
6173 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6174 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6175 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6176 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6177 case ixgbe_mac_82599EB:
6178 for (i = 0; i < 16; i++)
6179 adapter->hw_rx_no_dma_resources +=
6180 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
6181 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
6182 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
6183 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
6184 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
6185 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
6186 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
6187 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
6188 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6189 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6190 #ifdef IXGBE_FCOE
6191 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6192 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6193 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6194 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6195 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6196 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6197 /* Add up per cpu counters for total ddp aloc fail */
6198 if (adapter->fcoe.ddp_pool) {
6199 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6200 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6201 unsigned int cpu;
6202 u64 noddp = 0, noddp_ext_buff = 0;
6203 for_each_possible_cpu(cpu) {
6204 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6205 noddp += ddp_pool->noddp;
6206 noddp_ext_buff += ddp_pool->noddp_ext_buff;
6207 }
6208 hwstats->fcoe_noddp = noddp;
6209 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
6210 }
6211 #endif /* IXGBE_FCOE */
6212 break;
6213 default:
6214 break;
6215 }
6216 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
6217 hwstats->bprc += bprc;
6218 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
6219 if (hw->mac.type == ixgbe_mac_82598EB)
6220 hwstats->mprc -= bprc;
6221 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6222 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6223 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6224 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6225 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6226 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6227 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6228 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6229 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
6230 hwstats->lxontxc += lxon;
6231 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
6232 hwstats->lxofftxc += lxoff;
6233 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6234 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6235 /*
6236 * 82598 errata - tx of flow control packets is included in tx counters
6237 */
6238 xon_off_tot = lxon + lxoff;
6239 hwstats->gptc -= xon_off_tot;
6240 hwstats->mptc -= xon_off_tot;
6241 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6242 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6243 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6244 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6245 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6246 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6247 hwstats->ptc64 -= xon_off_tot;
6248 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6249 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6250 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6251 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6252 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6253 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
6254
6255 /* Fill out the OS statistics structure */
6256 netdev->stats.multicast = hwstats->mprc;
6257
6258 /* Rx Errors */
6259 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
6260 netdev->stats.rx_dropped = 0;
6261 netdev->stats.rx_length_errors = hwstats->rlec;
6262 netdev->stats.rx_crc_errors = hwstats->crcerrs;
6263 netdev->stats.rx_missed_errors = total_mpc;
6264 }
6265
6266 /**
6267 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
6268 * @adapter: pointer to the device adapter structure
6269 **/
6270 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
6271 {
6272 struct ixgbe_hw *hw = &adapter->hw;
6273 int i;
6274
6275 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6276 return;
6277
6278 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
6279
6280 /* if interface is down do nothing */
6281 if (test_bit(__IXGBE_DOWN, &adapter->state))
6282 return;
6283
6284 /* do nothing if we are not using signature filters */
6285 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6286 return;
6287
6288 adapter->fdir_overflow++;
6289
6290 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6291 for (i = 0; i < adapter->num_tx_queues; i++)
6292 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6293 &(adapter->tx_ring[i]->state));
6294 /* re-enable flow director interrupts */
6295 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
6296 } else {
6297 e_err(probe, "failed to finish FDIR re-initialization, "
6298 "ignored adding FDIR ATR filters\n");
6299 }
6300 }
6301
6302 /**
6303 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6304 * @adapter: pointer to the device adapter structure
6305 *
6306 * This function serves two purposes. First it strobes the interrupt lines
6307 * in order to make certain interrupts are occurring. Secondly it sets the
6308 * bits needed to check for TX hangs. As a result we should immediately
6309 * determine if a hang has occurred.
6310 */
6311 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
6312 {
6313 struct ixgbe_hw *hw = &adapter->hw;
6314 u64 eics = 0;
6315 int i;
6316
6317 /* If we're down, removing or resetting, just bail */
6318 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6319 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6320 test_bit(__IXGBE_RESETTING, &adapter->state))
6321 return;
6322
6323 /* Force detection of hung controller */
6324 if (netif_carrier_ok(adapter->netdev)) {
6325 for (i = 0; i < adapter->num_tx_queues; i++)
6326 set_check_for_tx_hang(adapter->tx_ring[i]);
6327 }
6328
6329 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6330 /*
6331 * for legacy and MSI interrupts don't set any bits
6332 * that are enabled for EIAM, because this operation
6333 * would set *both* EIMS and EICS for any bit in EIAM
6334 */
6335 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6336 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6337 } else {
6338 /* get one bit for every active tx/rx interrupt vector */
6339 for (i = 0; i < adapter->num_q_vectors; i++) {
6340 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6341 if (qv->rx.ring || qv->tx.ring)
6342 eics |= ((u64)1 << i);
6343 }
6344 }
6345
6346 /* Cause software interrupt to ensure rings are cleaned */
6347 ixgbe_irq_rearm_queues(adapter, eics);
6348 }
6349
6350 /**
6351 * ixgbe_watchdog_update_link - update the link status
6352 * @adapter: pointer to the device adapter structure
6353 * @link_speed: pointer to a u32 to store the link_speed
6354 **/
6355 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6356 {
6357 struct ixgbe_hw *hw = &adapter->hw;
6358 u32 link_speed = adapter->link_speed;
6359 bool link_up = adapter->link_up;
6360 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
6361
6362 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6363 return;
6364
6365 if (hw->mac.ops.check_link) {
6366 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6367 } else {
6368 /* always assume link is up, if no check link function */
6369 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6370 link_up = true;
6371 }
6372
6373 if (adapter->ixgbe_ieee_pfc)
6374 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6375
6376 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
6377 hw->mac.ops.fc_enable(hw);
6378 ixgbe_set_rx_drop_en(adapter);
6379 }
6380
6381 if (link_up ||
6382 time_after(jiffies, (adapter->link_check_timeout +
6383 IXGBE_TRY_LINK_TIMEOUT))) {
6384 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6385 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6386 IXGBE_WRITE_FLUSH(hw);
6387 }
6388
6389 adapter->link_up = link_up;
6390 adapter->link_speed = link_speed;
6391 }
6392
6393 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6394 {
6395 #ifdef CONFIG_IXGBE_DCB
6396 struct net_device *netdev = adapter->netdev;
6397 struct dcb_app app = {
6398 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6399 .protocol = 0,
6400 };
6401 u8 up = 0;
6402
6403 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6404 up = dcb_ieee_getapp_mask(netdev, &app);
6405
6406 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6407 #endif
6408 }
6409
6410 /**
6411 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6412 * print link up message
6413 * @adapter: pointer to the device adapter structure
6414 **/
6415 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6416 {
6417 struct net_device *netdev = adapter->netdev;
6418 struct ixgbe_hw *hw = &adapter->hw;
6419 struct net_device *upper;
6420 struct list_head *iter;
6421 u32 link_speed = adapter->link_speed;
6422 const char *speed_str;
6423 bool flow_rx, flow_tx;
6424
6425 /* only continue if link was previously down */
6426 if (netif_carrier_ok(netdev))
6427 return;
6428
6429 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6430
6431 switch (hw->mac.type) {
6432 case ixgbe_mac_82598EB: {
6433 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6434 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6435 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6436 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6437 }
6438 break;
6439 case ixgbe_mac_X540:
6440 case ixgbe_mac_X550:
6441 case ixgbe_mac_X550EM_x:
6442 case ixgbe_mac_82599EB: {
6443 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6444 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6445 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6446 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6447 }
6448 break;
6449 default:
6450 flow_tx = false;
6451 flow_rx = false;
6452 break;
6453 }
6454
6455 adapter->last_rx_ptp_check = jiffies;
6456
6457 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6458 ixgbe_ptp_start_cyclecounter(adapter);
6459
6460 switch (link_speed) {
6461 case IXGBE_LINK_SPEED_10GB_FULL:
6462 speed_str = "10 Gbps";
6463 break;
6464 case IXGBE_LINK_SPEED_2_5GB_FULL:
6465 speed_str = "2.5 Gbps";
6466 break;
6467 case IXGBE_LINK_SPEED_1GB_FULL:
6468 speed_str = "1 Gbps";
6469 break;
6470 case IXGBE_LINK_SPEED_100_FULL:
6471 speed_str = "100 Mbps";
6472 break;
6473 default:
6474 speed_str = "unknown speed";
6475 break;
6476 }
6477 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
6478 ((flow_rx && flow_tx) ? "RX/TX" :
6479 (flow_rx ? "RX" :
6480 (flow_tx ? "TX" : "None"))));
6481
6482 netif_carrier_on(netdev);
6483 ixgbe_check_vf_rate_limit(adapter);
6484
6485 /* enable transmits */
6486 netif_tx_wake_all_queues(adapter->netdev);
6487
6488 /* enable any upper devices */
6489 rtnl_lock();
6490 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6491 if (netif_is_macvlan(upper)) {
6492 struct macvlan_dev *vlan = netdev_priv(upper);
6493
6494 if (vlan->fwd_priv)
6495 netif_tx_wake_all_queues(upper);
6496 }
6497 }
6498 rtnl_unlock();
6499
6500 /* update the default user priority for VFs */
6501 ixgbe_update_default_up(adapter);
6502
6503 /* ping all the active vfs to let them know link has changed */
6504 ixgbe_ping_all_vfs(adapter);
6505 }
6506
6507 /**
6508 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6509 * print link down message
6510 * @adapter: pointer to the adapter structure
6511 **/
6512 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
6513 {
6514 struct net_device *netdev = adapter->netdev;
6515 struct ixgbe_hw *hw = &adapter->hw;
6516
6517 adapter->link_up = false;
6518 adapter->link_speed = 0;
6519
6520 /* only continue if link was up previously */
6521 if (!netif_carrier_ok(netdev))
6522 return;
6523
6524 /* poll for SFP+ cable when link is down */
6525 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6526 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6527
6528 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6529 ixgbe_ptp_start_cyclecounter(adapter);
6530
6531 e_info(drv, "NIC Link is Down\n");
6532 netif_carrier_off(netdev);
6533
6534 /* ping all the active vfs to let them know link has changed */
6535 ixgbe_ping_all_vfs(adapter);
6536 }
6537
6538 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6539 {
6540 int i;
6541
6542 for (i = 0; i < adapter->num_tx_queues; i++) {
6543 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6544
6545 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6546 return true;
6547 }
6548
6549 return false;
6550 }
6551
6552 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6553 {
6554 struct ixgbe_hw *hw = &adapter->hw;
6555 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6556 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6557
6558 int i, j;
6559
6560 if (!adapter->num_vfs)
6561 return false;
6562
6563 /* resetting the PF is only needed for MAC before X550 */
6564 if (hw->mac.type >= ixgbe_mac_X550)
6565 return false;
6566
6567 for (i = 0; i < adapter->num_vfs; i++) {
6568 for (j = 0; j < q_per_pool; j++) {
6569 u32 h, t;
6570
6571 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6572 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6573
6574 if (h != t)
6575 return true;
6576 }
6577 }
6578
6579 return false;
6580 }
6581
6582 /**
6583 * ixgbe_watchdog_flush_tx - flush queues on link down
6584 * @adapter: pointer to the device adapter structure
6585 **/
6586 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6587 {
6588 if (!netif_carrier_ok(adapter->netdev)) {
6589 if (ixgbe_ring_tx_pending(adapter) ||
6590 ixgbe_vf_tx_pending(adapter)) {
6591 /* We've lost link, so the controller stops DMA,
6592 * but we've got queued Tx work that's never going
6593 * to get done, so reset controller to flush Tx.
6594 * (Do the reset outside of interrupt context).
6595 */
6596 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
6597 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6598 }
6599 }
6600 }
6601
6602 #ifdef CONFIG_PCI_IOV
6603 static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6604 struct pci_dev *vfdev)
6605 {
6606 if (!pci_wait_for_pending_transaction(vfdev))
6607 e_dev_warn("Issuing VFLR with pending transactions\n");
6608
6609 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6610 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6611
6612 msleep(100);
6613 }
6614
6615 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6616 {
6617 struct ixgbe_hw *hw = &adapter->hw;
6618 struct pci_dev *pdev = adapter->pdev;
6619 struct pci_dev *vfdev;
6620 u32 gpc;
6621 int pos;
6622 unsigned short vf_id;
6623
6624 if (!(netif_carrier_ok(adapter->netdev)))
6625 return;
6626
6627 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6628 if (gpc) /* If incrementing then no need for the check below */
6629 return;
6630 /* Check to see if a bad DMA write target from an errant or
6631 * malicious VF has caused a PCIe error. If so then we can
6632 * issue a VFLR to the offending VF(s) and then resume without
6633 * requesting a full slot reset.
6634 */
6635
6636 if (!pdev)
6637 return;
6638
6639 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6640 if (!pos)
6641 return;
6642
6643 /* get the device ID for the VF */
6644 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id);
6645
6646 /* check status reg for all VFs owned by this PF */
6647 vfdev = pci_get_device(pdev->vendor, vf_id, NULL);
6648 while (vfdev) {
6649 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) {
6650 u16 status_reg;
6651
6652 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6653 if (status_reg & PCI_STATUS_REC_MASTER_ABORT)
6654 /* issue VFLR */
6655 ixgbe_issue_vf_flr(adapter, vfdev);
6656 }
6657
6658 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev);
6659 }
6660 }
6661
6662 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6663 {
6664 u32 ssvpc;
6665
6666 /* Do not perform spoof check for 82598 or if not in IOV mode */
6667 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6668 adapter->num_vfs == 0)
6669 return;
6670
6671 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6672
6673 /*
6674 * ssvpc register is cleared on read, if zero then no
6675 * spoofed packets in the last interval.
6676 */
6677 if (!ssvpc)
6678 return;
6679
6680 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
6681 }
6682 #else
6683 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6684 {
6685 }
6686
6687 static void
6688 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6689 {
6690 }
6691 #endif /* CONFIG_PCI_IOV */
6692
6693
6694 /**
6695 * ixgbe_watchdog_subtask - check and bring link up
6696 * @adapter: pointer to the device adapter structure
6697 **/
6698 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6699 {
6700 /* if interface is down, removing or resetting, do nothing */
6701 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6702 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6703 test_bit(__IXGBE_RESETTING, &adapter->state))
6704 return;
6705
6706 ixgbe_watchdog_update_link(adapter);
6707
6708 if (adapter->link_up)
6709 ixgbe_watchdog_link_is_up(adapter);
6710 else
6711 ixgbe_watchdog_link_is_down(adapter);
6712
6713 ixgbe_check_for_bad_vf(adapter);
6714 ixgbe_spoof_check(adapter);
6715 ixgbe_update_stats(adapter);
6716
6717 ixgbe_watchdog_flush_tx(adapter);
6718 }
6719
6720 /**
6721 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6722 * @adapter: the ixgbe adapter structure
6723 **/
6724 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6725 {
6726 struct ixgbe_hw *hw = &adapter->hw;
6727 s32 err;
6728
6729 /* not searching for SFP so there is nothing to do here */
6730 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6731 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6732 return;
6733
6734 if (adapter->sfp_poll_time &&
6735 time_after(adapter->sfp_poll_time, jiffies))
6736 return; /* If not yet time to poll for SFP */
6737
6738 /* someone else is in init, wait until next service event */
6739 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6740 return;
6741
6742 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
6743
6744 err = hw->phy.ops.identify_sfp(hw);
6745 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6746 goto sfp_out;
6747
6748 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6749 /* If no cable is present, then we need to reset
6750 * the next time we find a good cable. */
6751 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6752 }
6753
6754 /* exit on error */
6755 if (err)
6756 goto sfp_out;
6757
6758 /* exit if reset not needed */
6759 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6760 goto sfp_out;
6761
6762 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6763
6764 /*
6765 * A module may be identified correctly, but the EEPROM may not have
6766 * support for that module. setup_sfp() will fail in that case, so
6767 * we should not allow that module to load.
6768 */
6769 if (hw->mac.type == ixgbe_mac_82598EB)
6770 err = hw->phy.ops.reset(hw);
6771 else
6772 err = hw->mac.ops.setup_sfp(hw);
6773
6774 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6775 goto sfp_out;
6776
6777 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6778 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6779
6780 sfp_out:
6781 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6782
6783 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6784 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6785 e_dev_err("failed to initialize because an unsupported "
6786 "SFP+ module type was detected.\n");
6787 e_dev_err("Reload the driver after installing a "
6788 "supported module.\n");
6789 unregister_netdev(adapter->netdev);
6790 }
6791 }
6792
6793 /**
6794 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6795 * @adapter: the ixgbe adapter structure
6796 **/
6797 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6798 {
6799 struct ixgbe_hw *hw = &adapter->hw;
6800 u32 speed;
6801 bool autoneg = false;
6802
6803 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6804 return;
6805
6806 /* someone else is in init, wait until next service event */
6807 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6808 return;
6809
6810 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6811
6812 speed = hw->phy.autoneg_advertised;
6813 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
6814 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
6815
6816 /* setup the highest link when no autoneg */
6817 if (!autoneg) {
6818 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6819 speed = IXGBE_LINK_SPEED_10GB_FULL;
6820 }
6821 }
6822
6823 if (hw->mac.ops.setup_link)
6824 hw->mac.ops.setup_link(hw, speed, true);
6825
6826 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6827 adapter->link_check_timeout = jiffies;
6828 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6829 }
6830
6831 /**
6832 * ixgbe_service_timer - Timer Call-back
6833 * @data: pointer to adapter cast into an unsigned long
6834 **/
6835 static void ixgbe_service_timer(unsigned long data)
6836 {
6837 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6838 unsigned long next_event_offset;
6839
6840 /* poll faster when waiting for link */
6841 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6842 next_event_offset = HZ / 10;
6843 else
6844 next_event_offset = HZ * 2;
6845
6846 /* Reset the timer */
6847 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6848
6849 ixgbe_service_event_schedule(adapter);
6850 }
6851
6852 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
6853 {
6854 struct ixgbe_hw *hw = &adapter->hw;
6855 u32 status;
6856
6857 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
6858 return;
6859
6860 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
6861
6862 if (!hw->phy.ops.handle_lasi)
6863 return;
6864
6865 status = hw->phy.ops.handle_lasi(&adapter->hw);
6866 if (status != IXGBE_ERR_OVERTEMP)
6867 return;
6868
6869 e_crit(drv, "%s\n", ixgbe_overheat_msg);
6870 }
6871
6872 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6873 {
6874 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6875 return;
6876
6877 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6878
6879 /* If we're already down, removing or resetting, just bail */
6880 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6881 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6882 test_bit(__IXGBE_RESETTING, &adapter->state))
6883 return;
6884
6885 ixgbe_dump(adapter);
6886 netdev_err(adapter->netdev, "Reset adapter\n");
6887 adapter->tx_timeout_count++;
6888
6889 rtnl_lock();
6890 ixgbe_reinit_locked(adapter);
6891 rtnl_unlock();
6892 }
6893
6894 /**
6895 * ixgbe_service_task - manages and runs subtasks
6896 * @work: pointer to work_struct containing our data
6897 **/
6898 static void ixgbe_service_task(struct work_struct *work)
6899 {
6900 struct ixgbe_adapter *adapter = container_of(work,
6901 struct ixgbe_adapter,
6902 service_task);
6903 if (ixgbe_removed(adapter->hw.hw_addr)) {
6904 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6905 rtnl_lock();
6906 ixgbe_down(adapter);
6907 rtnl_unlock();
6908 }
6909 ixgbe_service_event_complete(adapter);
6910 return;
6911 }
6912 #ifdef CONFIG_IXGBE_VXLAN
6913 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
6914 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
6915 vxlan_get_rx_port(adapter->netdev);
6916 }
6917 #endif /* CONFIG_IXGBE_VXLAN */
6918 ixgbe_reset_subtask(adapter);
6919 ixgbe_phy_interrupt_subtask(adapter);
6920 ixgbe_sfp_detection_subtask(adapter);
6921 ixgbe_sfp_link_config_subtask(adapter);
6922 ixgbe_check_overtemp_subtask(adapter);
6923 ixgbe_watchdog_subtask(adapter);
6924 ixgbe_fdir_reinit_subtask(adapter);
6925 ixgbe_check_hang_subtask(adapter);
6926
6927 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
6928 ixgbe_ptp_overflow_check(adapter);
6929 ixgbe_ptp_rx_hang(adapter);
6930 }
6931
6932 ixgbe_service_event_complete(adapter);
6933 }
6934
6935 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6936 struct ixgbe_tx_buffer *first,
6937 u8 *hdr_len)
6938 {
6939 struct sk_buff *skb = first->skb;
6940 u32 vlan_macip_lens, type_tucmd;
6941 u32 mss_l4len_idx, l4len;
6942 int err;
6943
6944 if (skb->ip_summed != CHECKSUM_PARTIAL)
6945 return 0;
6946
6947 if (!skb_is_gso(skb))
6948 return 0;
6949
6950 err = skb_cow_head(skb, 0);
6951 if (err < 0)
6952 return err;
6953
6954 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6955 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6956
6957 if (first->protocol == htons(ETH_P_IP)) {
6958 struct iphdr *iph = ip_hdr(skb);
6959 iph->tot_len = 0;
6960 iph->check = 0;
6961 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6962 iph->daddr, 0,
6963 IPPROTO_TCP,
6964 0);
6965 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6966 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6967 IXGBE_TX_FLAGS_CSUM |
6968 IXGBE_TX_FLAGS_IPV4;
6969 } else if (skb_is_gso_v6(skb)) {
6970 ipv6_hdr(skb)->payload_len = 0;
6971 tcp_hdr(skb)->check =
6972 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6973 &ipv6_hdr(skb)->daddr,
6974 0, IPPROTO_TCP, 0);
6975 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6976 IXGBE_TX_FLAGS_CSUM;
6977 }
6978
6979 /* compute header lengths */
6980 l4len = tcp_hdrlen(skb);
6981 *hdr_len = skb_transport_offset(skb) + l4len;
6982
6983 /* update gso size and bytecount with header size */
6984 first->gso_segs = skb_shinfo(skb)->gso_segs;
6985 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6986
6987 /* mss_l4len_id: use 0 as index for TSO */
6988 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6989 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6990
6991 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6992 vlan_macip_lens = skb_network_header_len(skb);
6993 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6994 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6995
6996 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6997 mss_l4len_idx);
6998
6999 return 1;
7000 }
7001
7002 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7003 struct ixgbe_tx_buffer *first)
7004 {
7005 struct sk_buff *skb = first->skb;
7006 u32 vlan_macip_lens = 0;
7007 u32 mss_l4len_idx = 0;
7008 u32 type_tucmd = 0;
7009
7010 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7011 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
7012 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
7013 return;
7014 vlan_macip_lens = skb_network_offset(skb) <<
7015 IXGBE_ADVTXD_MACLEN_SHIFT;
7016 } else {
7017 u8 l4_hdr = 0;
7018 union {
7019 struct iphdr *ipv4;
7020 struct ipv6hdr *ipv6;
7021 u8 *raw;
7022 } network_hdr;
7023 union {
7024 struct tcphdr *tcphdr;
7025 u8 *raw;
7026 } transport_hdr;
7027
7028 if (skb->encapsulation) {
7029 network_hdr.raw = skb_inner_network_header(skb);
7030 transport_hdr.raw = skb_inner_transport_header(skb);
7031 vlan_macip_lens = skb_inner_network_offset(skb) <<
7032 IXGBE_ADVTXD_MACLEN_SHIFT;
7033 } else {
7034 network_hdr.raw = skb_network_header(skb);
7035 transport_hdr.raw = skb_transport_header(skb);
7036 vlan_macip_lens = skb_network_offset(skb) <<
7037 IXGBE_ADVTXD_MACLEN_SHIFT;
7038 }
7039
7040 /* use first 4 bits to determine IP version */
7041 switch (network_hdr.ipv4->version) {
7042 case IPVERSION:
7043 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
7044 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
7045 l4_hdr = network_hdr.ipv4->protocol;
7046 break;
7047 case 6:
7048 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
7049 l4_hdr = network_hdr.ipv6->nexthdr;
7050 break;
7051 default:
7052 if (unlikely(net_ratelimit())) {
7053 dev_warn(tx_ring->dev,
7054 "partial checksum but version=%d\n",
7055 network_hdr.ipv4->version);
7056 }
7057 }
7058
7059 switch (l4_hdr) {
7060 case IPPROTO_TCP:
7061 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
7062 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
7063 IXGBE_ADVTXD_L4LEN_SHIFT;
7064 break;
7065 case IPPROTO_SCTP:
7066 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7067 mss_l4len_idx = sizeof(struct sctphdr) <<
7068 IXGBE_ADVTXD_L4LEN_SHIFT;
7069 break;
7070 case IPPROTO_UDP:
7071 mss_l4len_idx = sizeof(struct udphdr) <<
7072 IXGBE_ADVTXD_L4LEN_SHIFT;
7073 break;
7074 default:
7075 if (unlikely(net_ratelimit())) {
7076 dev_warn(tx_ring->dev,
7077 "partial checksum but l4 proto=%x!\n",
7078 l4_hdr);
7079 }
7080 break;
7081 }
7082
7083 /* update TX checksum flag */
7084 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7085 }
7086
7087 /* vlan_macip_lens: MACLEN, VLAN tag */
7088 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
7089
7090 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
7091 type_tucmd, mss_l4len_idx);
7092 }
7093
7094 #define IXGBE_SET_FLAG(_input, _flag, _result) \
7095 ((_flag <= _result) ? \
7096 ((u32)(_input & _flag) * (_result / _flag)) : \
7097 ((u32)(_input & _flag) / (_flag / _result)))
7098
7099 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
7100 {
7101 /* set type for advanced descriptor with frame checksum insertion */
7102 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7103 IXGBE_ADVTXD_DCMD_DEXT |
7104 IXGBE_ADVTXD_DCMD_IFCS;
7105
7106 /* set HW vlan bit if vlan is present */
7107 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7108 IXGBE_ADVTXD_DCMD_VLE);
7109
7110 /* set segmentation enable bits for TSO/FSO */
7111 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7112 IXGBE_ADVTXD_DCMD_TSE);
7113
7114 /* set timestamp bit if present */
7115 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7116 IXGBE_ADVTXD_MAC_TSTAMP);
7117
7118 /* insert frame checksum */
7119 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
7120
7121 return cmd_type;
7122 }
7123
7124 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7125 u32 tx_flags, unsigned int paylen)
7126 {
7127 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
7128
7129 /* enable L4 checksum for TSO and TX checksum offload */
7130 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7131 IXGBE_TX_FLAGS_CSUM,
7132 IXGBE_ADVTXD_POPTS_TXSM);
7133
7134 /* enble IPv4 checksum for TSO */
7135 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7136 IXGBE_TX_FLAGS_IPV4,
7137 IXGBE_ADVTXD_POPTS_IXSM);
7138
7139 /*
7140 * Check Context must be set if Tx switch is enabled, which it
7141 * always is for case where virtual functions are running
7142 */
7143 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7144 IXGBE_TX_FLAGS_CC,
7145 IXGBE_ADVTXD_CC);
7146
7147 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
7148 }
7149
7150 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7151 {
7152 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7153
7154 /* Herbert's original patch had:
7155 * smp_mb__after_netif_stop_queue();
7156 * but since that doesn't exist yet, just open code it.
7157 */
7158 smp_mb();
7159
7160 /* We need to check again in a case another CPU has just
7161 * made room available.
7162 */
7163 if (likely(ixgbe_desc_unused(tx_ring) < size))
7164 return -EBUSY;
7165
7166 /* A reprieve! - use start_queue because it doesn't call schedule */
7167 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7168 ++tx_ring->tx_stats.restart_queue;
7169 return 0;
7170 }
7171
7172 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7173 {
7174 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7175 return 0;
7176
7177 return __ixgbe_maybe_stop_tx(tx_ring, size);
7178 }
7179
7180 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7181 IXGBE_TXD_CMD_RS)
7182
7183 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
7184 struct ixgbe_tx_buffer *first,
7185 const u8 hdr_len)
7186 {
7187 struct sk_buff *skb = first->skb;
7188 struct ixgbe_tx_buffer *tx_buffer;
7189 union ixgbe_adv_tx_desc *tx_desc;
7190 struct skb_frag_struct *frag;
7191 dma_addr_t dma;
7192 unsigned int data_len, size;
7193 u32 tx_flags = first->tx_flags;
7194 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
7195 u16 i = tx_ring->next_to_use;
7196
7197 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7198
7199 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7200
7201 size = skb_headlen(skb);
7202 data_len = skb->data_len;
7203
7204 #ifdef IXGBE_FCOE
7205 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
7206 if (data_len < sizeof(struct fcoe_crc_eof)) {
7207 size -= sizeof(struct fcoe_crc_eof) - data_len;
7208 data_len = 0;
7209 } else {
7210 data_len -= sizeof(struct fcoe_crc_eof);
7211 }
7212 }
7213
7214 #endif
7215 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
7216
7217 tx_buffer = first;
7218
7219 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7220 if (dma_mapping_error(tx_ring->dev, dma))
7221 goto dma_error;
7222
7223 /* record length, and DMA address */
7224 dma_unmap_len_set(tx_buffer, len, size);
7225 dma_unmap_addr_set(tx_buffer, dma, dma);
7226
7227 tx_desc->read.buffer_addr = cpu_to_le64(dma);
7228
7229 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
7230 tx_desc->read.cmd_type_len =
7231 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
7232
7233 i++;
7234 tx_desc++;
7235 if (i == tx_ring->count) {
7236 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7237 i = 0;
7238 }
7239 tx_desc->read.olinfo_status = 0;
7240
7241 dma += IXGBE_MAX_DATA_PER_TXD;
7242 size -= IXGBE_MAX_DATA_PER_TXD;
7243
7244 tx_desc->read.buffer_addr = cpu_to_le64(dma);
7245 }
7246
7247 if (likely(!data_len))
7248 break;
7249
7250 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
7251
7252 i++;
7253 tx_desc++;
7254 if (i == tx_ring->count) {
7255 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7256 i = 0;
7257 }
7258 tx_desc->read.olinfo_status = 0;
7259
7260 #ifdef IXGBE_FCOE
7261 size = min_t(unsigned int, data_len, skb_frag_size(frag));
7262 #else
7263 size = skb_frag_size(frag);
7264 #endif
7265 data_len -= size;
7266
7267 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7268 DMA_TO_DEVICE);
7269
7270 tx_buffer = &tx_ring->tx_buffer_info[i];
7271 }
7272
7273 /* write last descriptor with RS and EOP bits */
7274 cmd_type |= size | IXGBE_TXD_CMD;
7275 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
7276
7277 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
7278
7279 /* set the timestamp */
7280 first->time_stamp = jiffies;
7281
7282 /*
7283 * Force memory writes to complete before letting h/w know there
7284 * are new descriptors to fetch. (Only applicable for weak-ordered
7285 * memory model archs, such as IA-64).
7286 *
7287 * We also need this memory barrier to make certain all of the
7288 * status bits have been updated before next_to_watch is written.
7289 */
7290 wmb();
7291
7292 /* set next_to_watch value indicating a packet is present */
7293 first->next_to_watch = tx_desc;
7294
7295 i++;
7296 if (i == tx_ring->count)
7297 i = 0;
7298
7299 tx_ring->next_to_use = i;
7300
7301 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7302
7303 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
7304 writel(i, tx_ring->tail);
7305
7306 /* we need this if more than one processor can write to our tail
7307 * at a time, it synchronizes IO on IA64/Altix systems
7308 */
7309 mmiowb();
7310 }
7311
7312 return;
7313 dma_error:
7314 dev_err(tx_ring->dev, "TX DMA map failed\n");
7315
7316 /* clear dma mappings for failed tx_buffer_info map */
7317 for (;;) {
7318 tx_buffer = &tx_ring->tx_buffer_info[i];
7319 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7320 if (tx_buffer == first)
7321 break;
7322 if (i == 0)
7323 i = tx_ring->count;
7324 i--;
7325 }
7326
7327 tx_ring->next_to_use = i;
7328 }
7329
7330 static void ixgbe_atr(struct ixgbe_ring *ring,
7331 struct ixgbe_tx_buffer *first)
7332 {
7333 struct ixgbe_q_vector *q_vector = ring->q_vector;
7334 union ixgbe_atr_hash_dword input = { .dword = 0 };
7335 union ixgbe_atr_hash_dword common = { .dword = 0 };
7336 union {
7337 unsigned char *network;
7338 struct iphdr *ipv4;
7339 struct ipv6hdr *ipv6;
7340 } hdr;
7341 struct tcphdr *th;
7342 struct sk_buff *skb;
7343 #ifdef CONFIG_IXGBE_VXLAN
7344 u8 encap = false;
7345 #endif /* CONFIG_IXGBE_VXLAN */
7346 __be16 vlan_id;
7347
7348 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7349 if (!q_vector)
7350 return;
7351
7352 /* do nothing if sampling is disabled */
7353 if (!ring->atr_sample_rate)
7354 return;
7355
7356 ring->atr_count++;
7357
7358 /* snag network header to get L4 type and address */
7359 skb = first->skb;
7360 hdr.network = skb_network_header(skb);
7361 if (skb->encapsulation) {
7362 #ifdef CONFIG_IXGBE_VXLAN
7363 struct ixgbe_adapter *adapter = q_vector->adapter;
7364
7365 if (!adapter->vxlan_port)
7366 return;
7367 if (first->protocol != htons(ETH_P_IP) ||
7368 hdr.ipv4->version != IPVERSION ||
7369 hdr.ipv4->protocol != IPPROTO_UDP) {
7370 return;
7371 }
7372 if (ntohs(udp_hdr(skb)->dest) != adapter->vxlan_port)
7373 return;
7374 encap = true;
7375 hdr.network = skb_inner_network_header(skb);
7376 th = inner_tcp_hdr(skb);
7377 #else
7378 return;
7379 #endif /* CONFIG_IXGBE_VXLAN */
7380 } else {
7381 /* Currently only IPv4/IPv6 with TCP is supported */
7382 if ((first->protocol != htons(ETH_P_IPV6) ||
7383 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
7384 (first->protocol != htons(ETH_P_IP) ||
7385 hdr.ipv4->protocol != IPPROTO_TCP))
7386 return;
7387 th = tcp_hdr(skb);
7388 }
7389
7390 /* skip this packet since it is invalid or the socket is closing */
7391 if (!th || th->fin)
7392 return;
7393
7394 /* sample on all syn packets or once every atr sample count */
7395 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7396 return;
7397
7398 /* reset sample count */
7399 ring->atr_count = 0;
7400
7401 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
7402
7403 /*
7404 * src and dst are inverted, think how the receiver sees them
7405 *
7406 * The input is broken into two sections, a non-compressed section
7407 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7408 * is XORed together and stored in the compressed dword.
7409 */
7410 input.formatted.vlan_id = vlan_id;
7411
7412 /*
7413 * since src port and flex bytes occupy the same word XOR them together
7414 * and write the value to source port portion of compressed dword
7415 */
7416 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
7417 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
7418 else
7419 common.port.src ^= th->dest ^ first->protocol;
7420 common.port.dst ^= th->source;
7421
7422 if (first->protocol == htons(ETH_P_IP)) {
7423 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7424 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7425 } else {
7426 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7427 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7428 hdr.ipv6->saddr.s6_addr32[1] ^
7429 hdr.ipv6->saddr.s6_addr32[2] ^
7430 hdr.ipv6->saddr.s6_addr32[3] ^
7431 hdr.ipv6->daddr.s6_addr32[0] ^
7432 hdr.ipv6->daddr.s6_addr32[1] ^
7433 hdr.ipv6->daddr.s6_addr32[2] ^
7434 hdr.ipv6->daddr.s6_addr32[3];
7435 }
7436
7437 #ifdef CONFIG_IXGBE_VXLAN
7438 if (encap)
7439 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
7440 #endif /* CONFIG_IXGBE_VXLAN */
7441
7442 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
7443 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7444 input, common, ring->queue_index);
7445 }
7446
7447 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
7448 void *accel_priv, select_queue_fallback_t fallback)
7449 {
7450 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7451 #ifdef IXGBE_FCOE
7452 struct ixgbe_adapter *adapter;
7453 struct ixgbe_ring_feature *f;
7454 int txq;
7455 #endif
7456
7457 if (fwd_adapter)
7458 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7459
7460 #ifdef IXGBE_FCOE
7461
7462 /*
7463 * only execute the code below if protocol is FCoE
7464 * or FIP and we have FCoE enabled on the adapter
7465 */
7466 switch (vlan_get_protocol(skb)) {
7467 case htons(ETH_P_FCOE):
7468 case htons(ETH_P_FIP):
7469 adapter = netdev_priv(dev);
7470
7471 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7472 break;
7473 default:
7474 return fallback(dev, skb);
7475 }
7476
7477 f = &adapter->ring_feature[RING_F_FCOE];
7478
7479 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7480 smp_processor_id();
7481
7482 while (txq >= f->indices)
7483 txq -= f->indices;
7484
7485 return txq + f->offset;
7486 #else
7487 return fallback(dev, skb);
7488 #endif
7489 }
7490
7491 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
7492 struct ixgbe_adapter *adapter,
7493 struct ixgbe_ring *tx_ring)
7494 {
7495 struct ixgbe_tx_buffer *first;
7496 int tso;
7497 u32 tx_flags = 0;
7498 unsigned short f;
7499 u16 count = TXD_USE_COUNT(skb_headlen(skb));
7500 __be16 protocol = skb->protocol;
7501 u8 hdr_len = 0;
7502
7503 /*
7504 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
7505 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
7506 * + 2 desc gap to keep tail from touching head,
7507 * + 1 desc for context descriptor,
7508 * otherwise try next time
7509 */
7510 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7511 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7512
7513 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7514 tx_ring->tx_stats.tx_busy++;
7515 return NETDEV_TX_BUSY;
7516 }
7517
7518 /* record the location of the first descriptor for this packet */
7519 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7520 first->skb = skb;
7521 first->bytecount = skb->len;
7522 first->gso_segs = 1;
7523
7524 /* if we have a HW VLAN tag being added default to the HW one */
7525 if (skb_vlan_tag_present(skb)) {
7526 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7527 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7528 /* else if it is a SW VLAN check the next protocol and store the tag */
7529 } else if (protocol == htons(ETH_P_8021Q)) {
7530 struct vlan_hdr *vhdr, _vhdr;
7531 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7532 if (!vhdr)
7533 goto out_drop;
7534
7535 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7536 IXGBE_TX_FLAGS_VLAN_SHIFT;
7537 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7538 }
7539 protocol = vlan_get_protocol(skb);
7540
7541 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7542 adapter->ptp_clock &&
7543 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7544 &adapter->state)) {
7545 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7546 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
7547
7548 /* schedule check for Tx timestamp */
7549 adapter->ptp_tx_skb = skb_get(skb);
7550 adapter->ptp_tx_start = jiffies;
7551 schedule_work(&adapter->ptp_tx_work);
7552 }
7553
7554 skb_tx_timestamp(skb);
7555
7556 #ifdef CONFIG_PCI_IOV
7557 /*
7558 * Use the l2switch_enable flag - would be false if the DMA
7559 * Tx switch had been disabled.
7560 */
7561 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7562 tx_flags |= IXGBE_TX_FLAGS_CC;
7563
7564 #endif
7565 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
7566 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7567 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7568 (skb->priority != TC_PRIO_CONTROL))) {
7569 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
7570 tx_flags |= (skb->priority & 0x7) <<
7571 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
7572 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7573 struct vlan_ethhdr *vhdr;
7574
7575 if (skb_cow_head(skb, 0))
7576 goto out_drop;
7577 vhdr = (struct vlan_ethhdr *)skb->data;
7578 vhdr->h_vlan_TCI = htons(tx_flags >>
7579 IXGBE_TX_FLAGS_VLAN_SHIFT);
7580 } else {
7581 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7582 }
7583 }
7584
7585 /* record initial flags and protocol */
7586 first->tx_flags = tx_flags;
7587 first->protocol = protocol;
7588
7589 #ifdef IXGBE_FCOE
7590 /* setup tx offload for FCoE */
7591 if ((protocol == htons(ETH_P_FCOE)) &&
7592 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
7593 tso = ixgbe_fso(tx_ring, first, &hdr_len);
7594 if (tso < 0)
7595 goto out_drop;
7596
7597 goto xmit_fcoe;
7598 }
7599
7600 #endif /* IXGBE_FCOE */
7601 tso = ixgbe_tso(tx_ring, first, &hdr_len);
7602 if (tso < 0)
7603 goto out_drop;
7604 else if (!tso)
7605 ixgbe_tx_csum(tx_ring, first);
7606
7607 /* add the ATR filter if ATR is on */
7608 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7609 ixgbe_atr(tx_ring, first);
7610
7611 #ifdef IXGBE_FCOE
7612 xmit_fcoe:
7613 #endif /* IXGBE_FCOE */
7614 ixgbe_tx_map(tx_ring, first, hdr_len);
7615
7616 return NETDEV_TX_OK;
7617
7618 out_drop:
7619 dev_kfree_skb_any(first->skb);
7620 first->skb = NULL;
7621
7622 return NETDEV_TX_OK;
7623 }
7624
7625 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7626 struct net_device *netdev,
7627 struct ixgbe_ring *ring)
7628 {
7629 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7630 struct ixgbe_ring *tx_ring;
7631
7632 /*
7633 * The minimum packet size for olinfo paylen is 17 so pad the skb
7634 * in order to meet this minimum size requirement.
7635 */
7636 if (skb_put_padto(skb, 17))
7637 return NETDEV_TX_OK;
7638
7639 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7640
7641 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7642 }
7643
7644 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7645 struct net_device *netdev)
7646 {
7647 return __ixgbe_xmit_frame(skb, netdev, NULL);
7648 }
7649
7650 /**
7651 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7652 * @netdev: network interface device structure
7653 * @p: pointer to an address structure
7654 *
7655 * Returns 0 on success, negative on failure
7656 **/
7657 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7658 {
7659 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7660 struct ixgbe_hw *hw = &adapter->hw;
7661 struct sockaddr *addr = p;
7662 int ret;
7663
7664 if (!is_valid_ether_addr(addr->sa_data))
7665 return -EADDRNOTAVAIL;
7666
7667 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7668 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7669 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7670
7671 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7672 return ret > 0 ? 0 : ret;
7673 }
7674
7675 static int
7676 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7677 {
7678 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7679 struct ixgbe_hw *hw = &adapter->hw;
7680 u16 value;
7681 int rc;
7682
7683 if (prtad != hw->phy.mdio.prtad)
7684 return -EINVAL;
7685 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7686 if (!rc)
7687 rc = value;
7688 return rc;
7689 }
7690
7691 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7692 u16 addr, u16 value)
7693 {
7694 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7695 struct ixgbe_hw *hw = &adapter->hw;
7696
7697 if (prtad != hw->phy.mdio.prtad)
7698 return -EINVAL;
7699 return hw->phy.ops.write_reg(hw, addr, devad, value);
7700 }
7701
7702 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7703 {
7704 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7705
7706 switch (cmd) {
7707 case SIOCSHWTSTAMP:
7708 return ixgbe_ptp_set_ts_config(adapter, req);
7709 case SIOCGHWTSTAMP:
7710 return ixgbe_ptp_get_ts_config(adapter, req);
7711 default:
7712 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7713 }
7714 }
7715
7716 /**
7717 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7718 * netdev->dev_addrs
7719 * @netdev: network interface device structure
7720 *
7721 * Returns non-zero on failure
7722 **/
7723 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7724 {
7725 int err = 0;
7726 struct ixgbe_adapter *adapter = netdev_priv(dev);
7727 struct ixgbe_hw *hw = &adapter->hw;
7728
7729 if (is_valid_ether_addr(hw->mac.san_addr)) {
7730 rtnl_lock();
7731 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
7732 rtnl_unlock();
7733
7734 /* update SAN MAC vmdq pool selection */
7735 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
7736 }
7737 return err;
7738 }
7739
7740 /**
7741 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7742 * netdev->dev_addrs
7743 * @netdev: network interface device structure
7744 *
7745 * Returns non-zero on failure
7746 **/
7747 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7748 {
7749 int err = 0;
7750 struct ixgbe_adapter *adapter = netdev_priv(dev);
7751 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7752
7753 if (is_valid_ether_addr(mac->san_addr)) {
7754 rtnl_lock();
7755 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7756 rtnl_unlock();
7757 }
7758 return err;
7759 }
7760
7761 #ifdef CONFIG_NET_POLL_CONTROLLER
7762 /*
7763 * Polling 'interrupt' - used by things like netconsole to send skbs
7764 * without having to re-enable interrupts. It's not called while
7765 * the interrupt routine is executing.
7766 */
7767 static void ixgbe_netpoll(struct net_device *netdev)
7768 {
7769 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7770 int i;
7771
7772 /* if interface is down do nothing */
7773 if (test_bit(__IXGBE_DOWN, &adapter->state))
7774 return;
7775
7776 /* loop through and schedule all active queues */
7777 for (i = 0; i < adapter->num_q_vectors; i++)
7778 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
7779 }
7780
7781 #endif
7782 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7783 struct rtnl_link_stats64 *stats)
7784 {
7785 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7786 int i;
7787
7788 rcu_read_lock();
7789 for (i = 0; i < adapter->num_rx_queues; i++) {
7790 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7791 u64 bytes, packets;
7792 unsigned int start;
7793
7794 if (ring) {
7795 do {
7796 start = u64_stats_fetch_begin_irq(&ring->syncp);
7797 packets = ring->stats.packets;
7798 bytes = ring->stats.bytes;
7799 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7800 stats->rx_packets += packets;
7801 stats->rx_bytes += bytes;
7802 }
7803 }
7804
7805 for (i = 0; i < adapter->num_tx_queues; i++) {
7806 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7807 u64 bytes, packets;
7808 unsigned int start;
7809
7810 if (ring) {
7811 do {
7812 start = u64_stats_fetch_begin_irq(&ring->syncp);
7813 packets = ring->stats.packets;
7814 bytes = ring->stats.bytes;
7815 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7816 stats->tx_packets += packets;
7817 stats->tx_bytes += bytes;
7818 }
7819 }
7820 rcu_read_unlock();
7821 /* following stats updated by ixgbe_watchdog_task() */
7822 stats->multicast = netdev->stats.multicast;
7823 stats->rx_errors = netdev->stats.rx_errors;
7824 stats->rx_length_errors = netdev->stats.rx_length_errors;
7825 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7826 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7827 return stats;
7828 }
7829
7830 #ifdef CONFIG_IXGBE_DCB
7831 /**
7832 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7833 * @adapter: pointer to ixgbe_adapter
7834 * @tc: number of traffic classes currently enabled
7835 *
7836 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7837 * 802.1Q priority maps to a packet buffer that exists.
7838 */
7839 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7840 {
7841 struct ixgbe_hw *hw = &adapter->hw;
7842 u32 reg, rsave;
7843 int i;
7844
7845 /* 82598 have a static priority to TC mapping that can not
7846 * be changed so no validation is needed.
7847 */
7848 if (hw->mac.type == ixgbe_mac_82598EB)
7849 return;
7850
7851 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7852 rsave = reg;
7853
7854 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7855 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7856
7857 /* If up2tc is out of bounds default to zero */
7858 if (up2tc > tc)
7859 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7860 }
7861
7862 if (reg != rsave)
7863 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7864
7865 return;
7866 }
7867
7868 /**
7869 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7870 * @adapter: Pointer to adapter struct
7871 *
7872 * Populate the netdev user priority to tc map
7873 */
7874 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7875 {
7876 struct net_device *dev = adapter->netdev;
7877 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7878 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7879 u8 prio;
7880
7881 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7882 u8 tc = 0;
7883
7884 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7885 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7886 else if (ets)
7887 tc = ets->prio_tc[prio];
7888
7889 netdev_set_prio_tc_map(dev, prio, tc);
7890 }
7891 }
7892
7893 #endif /* CONFIG_IXGBE_DCB */
7894 /**
7895 * ixgbe_setup_tc - configure net_device for multiple traffic classes
7896 *
7897 * @netdev: net device to configure
7898 * @tc: number of traffic classes to enable
7899 */
7900 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7901 {
7902 struct ixgbe_adapter *adapter = netdev_priv(dev);
7903 struct ixgbe_hw *hw = &adapter->hw;
7904 bool pools;
7905
7906 /* Hardware supports up to 8 traffic classes */
7907 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
7908 return -EINVAL;
7909
7910 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
7911 return -EINVAL;
7912
7913 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7914 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7915 return -EBUSY;
7916
7917 /* Hardware has to reinitialize queues and interrupts to
7918 * match packet buffer alignment. Unfortunately, the
7919 * hardware is not flexible enough to do this dynamically.
7920 */
7921 if (netif_running(dev))
7922 ixgbe_close(dev);
7923 else
7924 ixgbe_reset(adapter);
7925
7926 ixgbe_clear_interrupt_scheme(adapter);
7927
7928 #ifdef CONFIG_IXGBE_DCB
7929 if (tc) {
7930 netdev_set_num_tc(dev, tc);
7931 ixgbe_set_prio_tc_map(adapter);
7932
7933 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7934
7935 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7936 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
7937 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7938 }
7939 } else {
7940 netdev_reset_tc(dev);
7941
7942 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7943 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7944
7945 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7946
7947 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7948 adapter->dcb_cfg.pfc_mode_enable = false;
7949 }
7950
7951 ixgbe_validate_rtr(adapter, tc);
7952
7953 #endif /* CONFIG_IXGBE_DCB */
7954 ixgbe_init_interrupt_scheme(adapter);
7955
7956 if (netif_running(dev))
7957 return ixgbe_open(dev);
7958
7959 return 0;
7960 }
7961
7962 #ifdef CONFIG_PCI_IOV
7963 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7964 {
7965 struct net_device *netdev = adapter->netdev;
7966
7967 rtnl_lock();
7968 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
7969 rtnl_unlock();
7970 }
7971
7972 #endif
7973 void ixgbe_do_reset(struct net_device *netdev)
7974 {
7975 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7976
7977 if (netif_running(netdev))
7978 ixgbe_reinit_locked(adapter);
7979 else
7980 ixgbe_reset(adapter);
7981 }
7982
7983 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7984 netdev_features_t features)
7985 {
7986 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7987
7988 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7989 if (!(features & NETIF_F_RXCSUM))
7990 features &= ~NETIF_F_LRO;
7991
7992 /* Turn off LRO if not RSC capable */
7993 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7994 features &= ~NETIF_F_LRO;
7995
7996 return features;
7997 }
7998
7999 static int ixgbe_set_features(struct net_device *netdev,
8000 netdev_features_t features)
8001 {
8002 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8003 netdev_features_t changed = netdev->features ^ features;
8004 bool need_reset = false;
8005
8006 /* Make sure RSC matches LRO, reset if change */
8007 if (!(features & NETIF_F_LRO)) {
8008 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8009 need_reset = true;
8010 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8011 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8012 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8013 if (adapter->rx_itr_setting == 1 ||
8014 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8015 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8016 need_reset = true;
8017 } else if ((changed ^ features) & NETIF_F_LRO) {
8018 e_info(probe, "rx-usecs set too low, "
8019 "disabling RSC\n");
8020 }
8021 }
8022
8023 /*
8024 * Check if Flow Director n-tuple support was enabled or disabled. If
8025 * the state changed, we need to reset.
8026 */
8027 switch (features & NETIF_F_NTUPLE) {
8028 case NETIF_F_NTUPLE:
8029 /* turn off ATR, enable perfect filters and reset */
8030 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8031 need_reset = true;
8032
8033 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8034 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8035 break;
8036 default:
8037 /* turn off perfect filters, enable ATR and reset */
8038 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8039 need_reset = true;
8040
8041 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8042
8043 /* We cannot enable ATR if SR-IOV is enabled */
8044 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8045 break;
8046
8047 /* We cannot enable ATR if we have 2 or more traffic classes */
8048 if (netdev_get_num_tc(netdev) > 1)
8049 break;
8050
8051 /* We cannot enable ATR if RSS is disabled */
8052 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
8053 break;
8054
8055 /* A sample rate of 0 indicates ATR disabled */
8056 if (!adapter->atr_sample_rate)
8057 break;
8058
8059 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
8060 break;
8061 }
8062
8063 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8064 ixgbe_vlan_strip_enable(adapter);
8065 else
8066 ixgbe_vlan_strip_disable(adapter);
8067
8068 if (changed & NETIF_F_RXALL)
8069 need_reset = true;
8070
8071 netdev->features = features;
8072
8073 #ifdef CONFIG_IXGBE_VXLAN
8074 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8075 if (features & NETIF_F_RXCSUM)
8076 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8077 else
8078 ixgbe_clear_vxlan_port(adapter);
8079 }
8080 #endif /* CONFIG_IXGBE_VXLAN */
8081
8082 if (need_reset)
8083 ixgbe_do_reset(netdev);
8084
8085 return 0;
8086 }
8087
8088 #ifdef CONFIG_IXGBE_VXLAN
8089 /**
8090 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8091 * @dev: The port's netdev
8092 * @sa_family: Socket Family that VXLAN is notifiying us about
8093 * @port: New UDP port number that VXLAN started listening to
8094 **/
8095 static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8096 __be16 port)
8097 {
8098 struct ixgbe_adapter *adapter = netdev_priv(dev);
8099 struct ixgbe_hw *hw = &adapter->hw;
8100 u16 new_port = ntohs(port);
8101
8102 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8103 return;
8104
8105 if (sa_family == AF_INET6)
8106 return;
8107
8108 if (adapter->vxlan_port == new_port)
8109 return;
8110
8111 if (adapter->vxlan_port) {
8112 netdev_info(dev,
8113 "Hit Max num of VXLAN ports, not adding port %d\n",
8114 new_port);
8115 return;
8116 }
8117
8118 adapter->vxlan_port = new_port;
8119 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port);
8120 }
8121
8122 /**
8123 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8124 * @dev: The port's netdev
8125 * @sa_family: Socket Family that VXLAN is notifying us about
8126 * @port: UDP port number that VXLAN stopped listening to
8127 **/
8128 static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8129 __be16 port)
8130 {
8131 struct ixgbe_adapter *adapter = netdev_priv(dev);
8132 u16 new_port = ntohs(port);
8133
8134 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8135 return;
8136
8137 if (sa_family == AF_INET6)
8138 return;
8139
8140 if (adapter->vxlan_port != new_port) {
8141 netdev_info(dev, "Port %d was not found, not deleting\n",
8142 new_port);
8143 return;
8144 }
8145
8146 ixgbe_clear_vxlan_port(adapter);
8147 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8148 }
8149 #endif /* CONFIG_IXGBE_VXLAN */
8150
8151 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8152 struct net_device *dev,
8153 const unsigned char *addr, u16 vid,
8154 u16 flags)
8155 {
8156 /* guarantee we can provide a unique filter for the unicast address */
8157 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
8158 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
8159 return -ENOMEM;
8160 }
8161
8162 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
8163 }
8164
8165 /**
8166 * ixgbe_configure_bridge_mode - set various bridge modes
8167 * @adapter - the private structure
8168 * @mode - requested bridge mode
8169 *
8170 * Configure some settings require for various bridge modes.
8171 **/
8172 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8173 __u16 mode)
8174 {
8175 struct ixgbe_hw *hw = &adapter->hw;
8176 unsigned int p, num_pools;
8177 u32 vmdctl;
8178
8179 switch (mode) {
8180 case BRIDGE_MODE_VEPA:
8181 /* disable Tx loopback, rely on switch hairpin mode */
8182 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
8183
8184 /* must enable Rx switching replication to allow multicast
8185 * packet reception on all VFs, and to enable source address
8186 * pruning.
8187 */
8188 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8189 vmdctl |= IXGBE_VT_CTL_REPLEN;
8190 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8191
8192 /* enable Rx source address pruning. Note, this requires
8193 * replication to be enabled or else it does nothing.
8194 */
8195 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8196 for (p = 0; p < num_pools; p++) {
8197 if (hw->mac.ops.set_source_address_pruning)
8198 hw->mac.ops.set_source_address_pruning(hw,
8199 true,
8200 p);
8201 }
8202 break;
8203 case BRIDGE_MODE_VEB:
8204 /* enable Tx loopback for internal VF/PF communication */
8205 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8206 IXGBE_PFDTXGSWC_VT_LBEN);
8207
8208 /* disable Rx switching replication unless we have SR-IOV
8209 * virtual functions
8210 */
8211 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8212 if (!adapter->num_vfs)
8213 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8214 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8215
8216 /* disable Rx source address pruning, since we don't expect to
8217 * be receiving external loopback of our transmitted frames.
8218 */
8219 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8220 for (p = 0; p < num_pools; p++) {
8221 if (hw->mac.ops.set_source_address_pruning)
8222 hw->mac.ops.set_source_address_pruning(hw,
8223 false,
8224 p);
8225 }
8226 break;
8227 default:
8228 return -EINVAL;
8229 }
8230
8231 adapter->bridge_mode = mode;
8232
8233 e_info(drv, "enabling bridge mode: %s\n",
8234 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8235
8236 return 0;
8237 }
8238
8239 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
8240 struct nlmsghdr *nlh, u16 flags)
8241 {
8242 struct ixgbe_adapter *adapter = netdev_priv(dev);
8243 struct nlattr *attr, *br_spec;
8244 int rem;
8245
8246 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8247 return -EOPNOTSUPP;
8248
8249 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8250 if (!br_spec)
8251 return -EINVAL;
8252
8253 nla_for_each_nested(attr, br_spec, rem) {
8254 int status;
8255 __u16 mode;
8256
8257 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8258 continue;
8259
8260 if (nla_len(attr) < sizeof(mode))
8261 return -EINVAL;
8262
8263 mode = nla_get_u16(attr);
8264 status = ixgbe_configure_bridge_mode(adapter, mode);
8265 if (status)
8266 return status;
8267
8268 break;
8269 }
8270
8271 return 0;
8272 }
8273
8274 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8275 struct net_device *dev,
8276 u32 filter_mask, int nlflags)
8277 {
8278 struct ixgbe_adapter *adapter = netdev_priv(dev);
8279
8280 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8281 return 0;
8282
8283 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
8284 adapter->bridge_mode, 0, 0, nlflags,
8285 filter_mask, NULL);
8286 }
8287
8288 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8289 {
8290 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8291 struct ixgbe_adapter *adapter = netdev_priv(pdev);
8292 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
8293 unsigned int limit;
8294 int pool, err;
8295
8296 /* Hardware has a limited number of available pools. Each VF, and the
8297 * PF require a pool. Check to ensure we don't attempt to use more
8298 * then the available number of pools.
8299 */
8300 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8301 return ERR_PTR(-EINVAL);
8302
8303 #ifdef CONFIG_RPS
8304 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8305 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8306 vdev->name);
8307 return ERR_PTR(-EINVAL);
8308 }
8309 #endif
8310 /* Check for hardware restriction on number of rx/tx queues */
8311 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
8312 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8313 netdev_info(pdev,
8314 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8315 pdev->name);
8316 return ERR_PTR(-EINVAL);
8317 }
8318
8319 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8320 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8321 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8322 return ERR_PTR(-EBUSY);
8323
8324 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
8325 if (!fwd_adapter)
8326 return ERR_PTR(-ENOMEM);
8327
8328 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8329 adapter->num_rx_pools++;
8330 set_bit(pool, &adapter->fwd_bitmask);
8331 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8332
8333 /* Enable VMDq flag so device will be set in VM mode */
8334 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
8335 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
8336 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
8337
8338 /* Force reinit of ring allocation with VMDQ enabled */
8339 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8340 if (err)
8341 goto fwd_add_err;
8342 fwd_adapter->pool = pool;
8343 fwd_adapter->real_adapter = adapter;
8344 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8345 if (err)
8346 goto fwd_add_err;
8347 netif_tx_start_all_queues(vdev);
8348 return fwd_adapter;
8349 fwd_add_err:
8350 /* unwind counter and free adapter struct */
8351 netdev_info(pdev,
8352 "%s: dfwd hardware acceleration failed\n", vdev->name);
8353 clear_bit(pool, &adapter->fwd_bitmask);
8354 adapter->num_rx_pools--;
8355 kfree(fwd_adapter);
8356 return ERR_PTR(err);
8357 }
8358
8359 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8360 {
8361 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8362 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
8363 unsigned int limit;
8364
8365 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8366 adapter->num_rx_pools--;
8367
8368 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8369 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
8370 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8371 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8372 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8373 fwd_adapter->pool, adapter->num_rx_pools,
8374 fwd_adapter->rx_base_queue,
8375 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8376 adapter->fwd_bitmask);
8377 kfree(fwd_adapter);
8378 }
8379
8380 #define IXGBE_MAX_TUNNEL_HDR_LEN 80
8381 static netdev_features_t
8382 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8383 netdev_features_t features)
8384 {
8385 if (!skb->encapsulation)
8386 return features;
8387
8388 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8389 IXGBE_MAX_TUNNEL_HDR_LEN))
8390 return features & ~NETIF_F_ALL_CSUM;
8391
8392 return features;
8393 }
8394
8395 static const struct net_device_ops ixgbe_netdev_ops = {
8396 .ndo_open = ixgbe_open,
8397 .ndo_stop = ixgbe_close,
8398 .ndo_start_xmit = ixgbe_xmit_frame,
8399 .ndo_select_queue = ixgbe_select_queue,
8400 .ndo_set_rx_mode = ixgbe_set_rx_mode,
8401 .ndo_validate_addr = eth_validate_addr,
8402 .ndo_set_mac_address = ixgbe_set_mac,
8403 .ndo_change_mtu = ixgbe_change_mtu,
8404 .ndo_tx_timeout = ixgbe_tx_timeout,
8405 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8406 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
8407 .ndo_do_ioctl = ixgbe_ioctl,
8408 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8409 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
8410 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
8411 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
8412 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
8413 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
8414 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
8415 .ndo_get_stats64 = ixgbe_get_stats64,
8416 #ifdef CONFIG_IXGBE_DCB
8417 .ndo_setup_tc = ixgbe_setup_tc,
8418 #endif
8419 #ifdef CONFIG_NET_POLL_CONTROLLER
8420 .ndo_poll_controller = ixgbe_netpoll,
8421 #endif
8422 #ifdef CONFIG_NET_RX_BUSY_POLL
8423 .ndo_busy_poll = ixgbe_low_latency_recv,
8424 #endif
8425 #ifdef IXGBE_FCOE
8426 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
8427 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
8428 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8429 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8430 .ndo_fcoe_disable = ixgbe_fcoe_disable,
8431 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
8432 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
8433 #endif /* IXGBE_FCOE */
8434 .ndo_set_features = ixgbe_set_features,
8435 .ndo_fix_features = ixgbe_fix_features,
8436 .ndo_fdb_add = ixgbe_ndo_fdb_add,
8437 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8438 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
8439 .ndo_dfwd_add_station = ixgbe_fwd_add,
8440 .ndo_dfwd_del_station = ixgbe_fwd_del,
8441 #ifdef CONFIG_IXGBE_VXLAN
8442 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8443 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
8444 #endif /* CONFIG_IXGBE_VXLAN */
8445 .ndo_features_check = ixgbe_features_check,
8446 };
8447
8448 /**
8449 * ixgbe_enumerate_functions - Get the number of ports this device has
8450 * @adapter: adapter structure
8451 *
8452 * This function enumerates the phsyical functions co-located on a single slot,
8453 * in order to determine how many ports a device has. This is most useful in
8454 * determining the required GT/s of PCIe bandwidth necessary for optimal
8455 * performance.
8456 **/
8457 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8458 {
8459 struct pci_dev *entry, *pdev = adapter->pdev;
8460 int physfns = 0;
8461
8462 /* Some cards can not use the generic count PCIe functions method,
8463 * because they are behind a parent switch, so we hardcode these with
8464 * the correct number of functions.
8465 */
8466 if (ixgbe_pcie_from_parent(&adapter->hw))
8467 physfns = 4;
8468
8469 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8470 /* don't count virtual functions */
8471 if (entry->is_virtfn)
8472 continue;
8473
8474 /* When the devices on the bus don't all match our device ID,
8475 * we can't reliably determine the correct number of
8476 * functions. This can occur if a function has been direct
8477 * attached to a virtual machine using VT-d, for example. In
8478 * this case, simply return -1 to indicate this.
8479 */
8480 if ((entry->vendor != pdev->vendor) ||
8481 (entry->device != pdev->device))
8482 return -1;
8483
8484 physfns++;
8485 }
8486
8487 return physfns;
8488 }
8489
8490 /**
8491 * ixgbe_wol_supported - Check whether device supports WoL
8492 * @hw: hw specific details
8493 * @device_id: the device ID
8494 * @subdev_id: the subsystem device ID
8495 *
8496 * This function is used by probe and ethtool to determine
8497 * which devices have WoL support
8498 *
8499 **/
8500 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8501 u16 subdevice_id)
8502 {
8503 struct ixgbe_hw *hw = &adapter->hw;
8504 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8505 int is_wol_supported = 0;
8506
8507 switch (device_id) {
8508 case IXGBE_DEV_ID_82599_SFP:
8509 /* Only these subdevices could supports WOL */
8510 switch (subdevice_id) {
8511 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8512 case IXGBE_SUBDEV_ID_82599_560FLR:
8513 /* only support first port */
8514 if (hw->bus.func != 0)
8515 break;
8516 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8517 case IXGBE_SUBDEV_ID_82599_SFP:
8518 case IXGBE_SUBDEV_ID_82599_RNDC:
8519 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
8520 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8521 is_wol_supported = 1;
8522 break;
8523 }
8524 break;
8525 case IXGBE_DEV_ID_82599EN_SFP:
8526 /* Only this subdevice supports WOL */
8527 switch (subdevice_id) {
8528 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8529 is_wol_supported = 1;
8530 break;
8531 }
8532 break;
8533 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8534 /* All except this subdevice support WOL */
8535 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8536 is_wol_supported = 1;
8537 break;
8538 case IXGBE_DEV_ID_82599_KX4:
8539 is_wol_supported = 1;
8540 break;
8541 case IXGBE_DEV_ID_X540T:
8542 case IXGBE_DEV_ID_X540T1:
8543 case IXGBE_DEV_ID_X550T:
8544 case IXGBE_DEV_ID_X550EM_X_KX4:
8545 case IXGBE_DEV_ID_X550EM_X_KR:
8546 case IXGBE_DEV_ID_X550EM_X_10G_T:
8547 /* check eeprom to see if enabled wol */
8548 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8549 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8550 (hw->bus.func == 0))) {
8551 is_wol_supported = 1;
8552 }
8553 break;
8554 }
8555
8556 return is_wol_supported;
8557 }
8558
8559 /**
8560 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
8561 * @adapter: Pointer to adapter struct
8562 */
8563 static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
8564 {
8565 #ifdef CONFIG_OF
8566 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
8567 struct ixgbe_hw *hw = &adapter->hw;
8568 const unsigned char *addr;
8569
8570 addr = of_get_mac_address(dp);
8571 if (addr) {
8572 ether_addr_copy(hw->mac.perm_addr, addr);
8573 return;
8574 }
8575 #endif /* CONFIG_OF */
8576
8577 #ifdef CONFIG_SPARC
8578 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
8579 #endif /* CONFIG_SPARC */
8580 }
8581
8582 /**
8583 * ixgbe_probe - Device Initialization Routine
8584 * @pdev: PCI device information struct
8585 * @ent: entry in ixgbe_pci_tbl
8586 *
8587 * Returns 0 on success, negative on failure
8588 *
8589 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8590 * The OS initialization, configuring of the adapter private structure,
8591 * and a hardware reset occur.
8592 **/
8593 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8594 {
8595 struct net_device *netdev;
8596 struct ixgbe_adapter *adapter = NULL;
8597 struct ixgbe_hw *hw;
8598 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
8599 int i, err, pci_using_dac, expected_gts;
8600 unsigned int indices = MAX_TX_QUEUES;
8601 u8 part_str[IXGBE_PBANUM_LENGTH];
8602 bool disable_dev = false;
8603 #ifdef IXGBE_FCOE
8604 u16 device_caps;
8605 #endif
8606 u32 eec;
8607
8608 /* Catch broken hardware that put the wrong VF device ID in
8609 * the PCIe SR-IOV capability.
8610 */
8611 if (pdev->is_virtfn) {
8612 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8613 pci_name(pdev), pdev->vendor, pdev->device);
8614 return -EINVAL;
8615 }
8616
8617 err = pci_enable_device_mem(pdev);
8618 if (err)
8619 return err;
8620
8621 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
8622 pci_using_dac = 1;
8623 } else {
8624 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8625 if (err) {
8626 dev_err(&pdev->dev,
8627 "No usable DMA configuration, aborting\n");
8628 goto err_dma;
8629 }
8630 pci_using_dac = 0;
8631 }
8632
8633 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8634 IORESOURCE_MEM), ixgbe_driver_name);
8635 if (err) {
8636 dev_err(&pdev->dev,
8637 "pci_request_selected_regions failed 0x%x\n", err);
8638 goto err_pci_reg;
8639 }
8640
8641 pci_enable_pcie_error_reporting(pdev);
8642
8643 pci_set_master(pdev);
8644 pci_save_state(pdev);
8645
8646 if (ii->mac == ixgbe_mac_82598EB) {
8647 #ifdef CONFIG_IXGBE_DCB
8648 /* 8 TC w/ 4 queues per TC */
8649 indices = 4 * MAX_TRAFFIC_CLASS;
8650 #else
8651 indices = IXGBE_MAX_RSS_INDICES;
8652 #endif
8653 }
8654
8655 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
8656 if (!netdev) {
8657 err = -ENOMEM;
8658 goto err_alloc_etherdev;
8659 }
8660
8661 SET_NETDEV_DEV(netdev, &pdev->dev);
8662
8663 adapter = netdev_priv(netdev);
8664
8665 adapter->netdev = netdev;
8666 adapter->pdev = pdev;
8667 hw = &adapter->hw;
8668 hw->back = adapter;
8669 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
8670
8671 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8672 pci_resource_len(pdev, 0));
8673 adapter->io_addr = hw->hw_addr;
8674 if (!hw->hw_addr) {
8675 err = -EIO;
8676 goto err_ioremap;
8677 }
8678
8679 netdev->netdev_ops = &ixgbe_netdev_ops;
8680 ixgbe_set_ethtool_ops(netdev);
8681 netdev->watchdog_timeo = 5 * HZ;
8682 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
8683
8684 /* Setup hw api */
8685 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
8686 hw->mac.type = ii->mac;
8687 hw->mvals = ii->mvals;
8688
8689 /* EEPROM */
8690 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8691 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
8692 if (ixgbe_removed(hw->hw_addr)) {
8693 err = -EIO;
8694 goto err_ioremap;
8695 }
8696 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8697 if (!(eec & (1 << 8)))
8698 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8699
8700 /* PHY */
8701 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
8702 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
8703 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8704 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8705 hw->phy.mdio.mmds = 0;
8706 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8707 hw->phy.mdio.dev = netdev;
8708 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8709 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
8710
8711 ii->get_invariants(hw);
8712
8713 /* setup the private structure */
8714 err = ixgbe_sw_init(adapter);
8715 if (err)
8716 goto err_sw_init;
8717
8718 /* Make it possible the adapter to be woken up via WOL */
8719 switch (adapter->hw.mac.type) {
8720 case ixgbe_mac_82599EB:
8721 case ixgbe_mac_X540:
8722 case ixgbe_mac_X550:
8723 case ixgbe_mac_X550EM_x:
8724 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8725 break;
8726 default:
8727 break;
8728 }
8729
8730 /*
8731 * If there is a fan on this device and it has failed log the
8732 * failure.
8733 */
8734 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8735 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8736 if (esdp & IXGBE_ESDP_SDP1)
8737 e_crit(probe, "Fan has stopped, replace the adapter\n");
8738 }
8739
8740 if (allow_unsupported_sfp)
8741 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8742
8743 /* reset_hw fills in the perm_addr as well */
8744 hw->phy.reset_if_overtemp = true;
8745 err = hw->mac.ops.reset_hw(hw);
8746 hw->phy.reset_if_overtemp = false;
8747 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8748 err = 0;
8749 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
8750 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8751 e_dev_err("Reload the driver after installing a supported module.\n");
8752 goto err_sw_init;
8753 } else if (err) {
8754 e_dev_err("HW Init failed: %d\n", err);
8755 goto err_sw_init;
8756 }
8757
8758 #ifdef CONFIG_PCI_IOV
8759 /* SR-IOV not supported on the 82598 */
8760 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8761 goto skip_sriov;
8762 /* Mailbox */
8763 ixgbe_init_mbx_params_pf(hw);
8764 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
8765 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
8766 ixgbe_enable_sriov(adapter);
8767 skip_sriov:
8768
8769 #endif
8770 netdev->features = NETIF_F_SG |
8771 NETIF_F_IP_CSUM |
8772 NETIF_F_IPV6_CSUM |
8773 NETIF_F_HW_VLAN_CTAG_TX |
8774 NETIF_F_HW_VLAN_CTAG_RX |
8775 NETIF_F_TSO |
8776 NETIF_F_TSO6 |
8777 NETIF_F_RXHASH |
8778 NETIF_F_RXCSUM;
8779
8780 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
8781
8782 switch (adapter->hw.mac.type) {
8783 case ixgbe_mac_82599EB:
8784 case ixgbe_mac_X540:
8785 case ixgbe_mac_X550:
8786 case ixgbe_mac_X550EM_x:
8787 netdev->features |= NETIF_F_SCTP_CSUM;
8788 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8789 NETIF_F_NTUPLE;
8790 break;
8791 default:
8792 break;
8793 }
8794
8795 netdev->hw_features |= NETIF_F_RXALL;
8796 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
8797
8798 netdev->vlan_features |= NETIF_F_TSO;
8799 netdev->vlan_features |= NETIF_F_TSO6;
8800 netdev->vlan_features |= NETIF_F_IP_CSUM;
8801 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
8802 netdev->vlan_features |= NETIF_F_SG;
8803
8804 netdev->hw_enc_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
8805 NETIF_F_IPV6_CSUM;
8806
8807 netdev->priv_flags |= IFF_UNICAST_FLT;
8808 netdev->priv_flags |= IFF_SUPP_NOFCS;
8809
8810 #ifdef CONFIG_IXGBE_VXLAN
8811 switch (adapter->hw.mac.type) {
8812 case ixgbe_mac_X550:
8813 case ixgbe_mac_X550EM_x:
8814 netdev->hw_enc_features |= NETIF_F_RXCSUM |
8815 NETIF_F_IP_CSUM |
8816 NETIF_F_IPV6_CSUM;
8817 break;
8818 default:
8819 break;
8820 }
8821 #endif /* CONFIG_IXGBE_VXLAN */
8822
8823 #ifdef CONFIG_IXGBE_DCB
8824 netdev->dcbnl_ops = &dcbnl_ops;
8825 #endif
8826
8827 #ifdef IXGBE_FCOE
8828 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
8829 unsigned int fcoe_l;
8830
8831 if (hw->mac.ops.get_device_caps) {
8832 hw->mac.ops.get_device_caps(hw, &device_caps);
8833 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8834 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
8835 }
8836
8837
8838 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8839 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
8840
8841 netdev->features |= NETIF_F_FSO |
8842 NETIF_F_FCOE_CRC;
8843
8844 netdev->vlan_features |= NETIF_F_FSO |
8845 NETIF_F_FCOE_CRC |
8846 NETIF_F_FCOE_MTU;
8847 }
8848 #endif /* IXGBE_FCOE */
8849 if (pci_using_dac) {
8850 netdev->features |= NETIF_F_HIGHDMA;
8851 netdev->vlan_features |= NETIF_F_HIGHDMA;
8852 }
8853
8854 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8855 netdev->hw_features |= NETIF_F_LRO;
8856 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8857 netdev->features |= NETIF_F_LRO;
8858
8859 /* make sure the EEPROM is good */
8860 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
8861 e_dev_err("The EEPROM Checksum Is Not Valid\n");
8862 err = -EIO;
8863 goto err_sw_init;
8864 }
8865
8866 ixgbe_get_platform_mac_addr(adapter);
8867
8868 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
8869
8870 if (!is_valid_ether_addr(netdev->dev_addr)) {
8871 e_dev_err("invalid MAC address\n");
8872 err = -EIO;
8873 goto err_sw_init;
8874 }
8875
8876 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8877
8878 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
8879 (unsigned long) adapter);
8880
8881 if (ixgbe_removed(hw->hw_addr)) {
8882 err = -EIO;
8883 goto err_sw_init;
8884 }
8885 INIT_WORK(&adapter->service_task, ixgbe_service_task);
8886 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
8887 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
8888
8889 err = ixgbe_init_interrupt_scheme(adapter);
8890 if (err)
8891 goto err_sw_init;
8892
8893 /* WOL not supported for all devices */
8894 adapter->wol = 0;
8895 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
8896 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
8897 pdev->subsystem_device);
8898 if (hw->wol_enabled)
8899 adapter->wol = IXGBE_WUFC_MAG;
8900
8901 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8902
8903 /* save off EEPROM version number */
8904 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8905 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8906
8907 /* pick up the PCI bus settings for reporting later */
8908 if (ixgbe_pcie_from_parent(hw))
8909 ixgbe_get_parent_bus_info(adapter);
8910 else
8911 hw->mac.ops.get_bus_info(hw);
8912
8913 /* calculate the expected PCIe bandwidth required for optimal
8914 * performance. Note that some older parts will never have enough
8915 * bandwidth due to being older generation PCIe parts. We clamp these
8916 * parts to ensure no warning is displayed if it can't be fixed.
8917 */
8918 switch (hw->mac.type) {
8919 case ixgbe_mac_82598EB:
8920 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8921 break;
8922 default:
8923 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8924 break;
8925 }
8926
8927 /* don't check link if we failed to enumerate functions */
8928 if (expected_gts > 0)
8929 ixgbe_check_minimum_link(adapter, expected_gts);
8930
8931 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
8932 if (err)
8933 strlcpy(part_str, "Unknown", sizeof(part_str));
8934 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8935 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8936 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8937 part_str);
8938 else
8939 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8940 hw->mac.type, hw->phy.type, part_str);
8941
8942 e_dev_info("%pM\n", netdev->dev_addr);
8943
8944 /* reset the hardware with the new settings */
8945 err = hw->mac.ops.start_hw(hw);
8946 if (err == IXGBE_ERR_EEPROM_VERSION) {
8947 /* We are running on a pre-production device, log a warning */
8948 e_dev_warn("This device is a pre-production adapter/LOM. "
8949 "Please be aware there may be issues associated "
8950 "with your hardware. If you are experiencing "
8951 "problems please contact your Intel or hardware "
8952 "representative who provided you with this "
8953 "hardware.\n");
8954 }
8955 strcpy(netdev->name, "eth%d");
8956 err = register_netdev(netdev);
8957 if (err)
8958 goto err_register;
8959
8960 pci_set_drvdata(pdev, adapter);
8961
8962 /* power down the optics for 82599 SFP+ fiber */
8963 if (hw->mac.ops.disable_tx_laser)
8964 hw->mac.ops.disable_tx_laser(hw);
8965
8966 /* carrier off reporting is important to ethtool even BEFORE open */
8967 netif_carrier_off(netdev);
8968
8969 #ifdef CONFIG_IXGBE_DCA
8970 if (dca_add_requester(&pdev->dev) == 0) {
8971 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
8972 ixgbe_setup_dca(adapter);
8973 }
8974 #endif
8975 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
8976 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
8977 for (i = 0; i < adapter->num_vfs; i++)
8978 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8979 }
8980
8981 /* firmware requires driver version to be 0xFFFFFFFF
8982 * since os does not support feature
8983 */
8984 if (hw->mac.ops.set_fw_drv_ver)
8985 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8986 0xFF);
8987
8988 /* add san mac addr to netdev */
8989 ixgbe_add_sanmac_netdev(netdev);
8990
8991 e_dev_info("%s\n", ixgbe_default_device_descr);
8992
8993 #ifdef CONFIG_IXGBE_HWMON
8994 if (ixgbe_sysfs_init(adapter))
8995 e_err(probe, "failed to allocate sysfs resources\n");
8996 #endif /* CONFIG_IXGBE_HWMON */
8997
8998 ixgbe_dbg_adapter_init(adapter);
8999
9000 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
9001 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
9002 hw->mac.ops.setup_link(hw,
9003 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
9004 true);
9005
9006 return 0;
9007
9008 err_register:
9009 ixgbe_release_hw_control(adapter);
9010 ixgbe_clear_interrupt_scheme(adapter);
9011 err_sw_init:
9012 ixgbe_disable_sriov(adapter);
9013 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9014 iounmap(adapter->io_addr);
9015 kfree(adapter->mac_table);
9016 err_ioremap:
9017 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9018 free_netdev(netdev);
9019 err_alloc_etherdev:
9020 pci_release_selected_regions(pdev,
9021 pci_select_bars(pdev, IORESOURCE_MEM));
9022 err_pci_reg:
9023 err_dma:
9024 if (!adapter || disable_dev)
9025 pci_disable_device(pdev);
9026 return err;
9027 }
9028
9029 /**
9030 * ixgbe_remove - Device Removal Routine
9031 * @pdev: PCI device information struct
9032 *
9033 * ixgbe_remove is called by the PCI subsystem to alert the driver
9034 * that it should release a PCI device. The could be caused by a
9035 * Hot-Plug event, or because the driver is going to be removed from
9036 * memory.
9037 **/
9038 static void ixgbe_remove(struct pci_dev *pdev)
9039 {
9040 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9041 struct net_device *netdev;
9042 bool disable_dev;
9043
9044 /* if !adapter then we already cleaned up in probe */
9045 if (!adapter)
9046 return;
9047
9048 netdev = adapter->netdev;
9049 ixgbe_dbg_adapter_exit(adapter);
9050
9051 set_bit(__IXGBE_REMOVING, &adapter->state);
9052 cancel_work_sync(&adapter->service_task);
9053
9054
9055 #ifdef CONFIG_IXGBE_DCA
9056 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9057 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9058 dca_remove_requester(&pdev->dev);
9059 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9060 IXGBE_DCA_CTRL_DCA_DISABLE);
9061 }
9062
9063 #endif
9064 #ifdef CONFIG_IXGBE_HWMON
9065 ixgbe_sysfs_exit(adapter);
9066 #endif /* CONFIG_IXGBE_HWMON */
9067
9068 /* remove the added san mac */
9069 ixgbe_del_sanmac_netdev(netdev);
9070
9071 #ifdef CONFIG_PCI_IOV
9072 ixgbe_disable_sriov(adapter);
9073 #endif
9074 if (netdev->reg_state == NETREG_REGISTERED)
9075 unregister_netdev(netdev);
9076
9077 ixgbe_clear_interrupt_scheme(adapter);
9078
9079 ixgbe_release_hw_control(adapter);
9080
9081 #ifdef CONFIG_DCB
9082 kfree(adapter->ixgbe_ieee_pfc);
9083 kfree(adapter->ixgbe_ieee_ets);
9084
9085 #endif
9086 iounmap(adapter->io_addr);
9087 pci_release_selected_regions(pdev, pci_select_bars(pdev,
9088 IORESOURCE_MEM));
9089
9090 e_dev_info("complete\n");
9091
9092 kfree(adapter->mac_table);
9093 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9094 free_netdev(netdev);
9095
9096 pci_disable_pcie_error_reporting(pdev);
9097
9098 if (disable_dev)
9099 pci_disable_device(pdev);
9100 }
9101
9102 /**
9103 * ixgbe_io_error_detected - called when PCI error is detected
9104 * @pdev: Pointer to PCI device
9105 * @state: The current pci connection state
9106 *
9107 * This function is called after a PCI bus error affecting
9108 * this device has been detected.
9109 */
9110 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
9111 pci_channel_state_t state)
9112 {
9113 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9114 struct net_device *netdev = adapter->netdev;
9115
9116 #ifdef CONFIG_PCI_IOV
9117 struct ixgbe_hw *hw = &adapter->hw;
9118 struct pci_dev *bdev, *vfdev;
9119 u32 dw0, dw1, dw2, dw3;
9120 int vf, pos;
9121 u16 req_id, pf_func;
9122
9123 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9124 adapter->num_vfs == 0)
9125 goto skip_bad_vf_detection;
9126
9127 bdev = pdev->bus->self;
9128 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
9129 bdev = bdev->bus->self;
9130
9131 if (!bdev)
9132 goto skip_bad_vf_detection;
9133
9134 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9135 if (!pos)
9136 goto skip_bad_vf_detection;
9137
9138 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9139 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9140 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9141 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9142 if (ixgbe_removed(hw->hw_addr))
9143 goto skip_bad_vf_detection;
9144
9145 req_id = dw1 >> 16;
9146 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9147 if (!(req_id & 0x0080))
9148 goto skip_bad_vf_detection;
9149
9150 pf_func = req_id & 0x01;
9151 if ((pf_func & 1) == (pdev->devfn & 1)) {
9152 unsigned int device_id;
9153
9154 vf = (req_id & 0x7F) >> 1;
9155 e_dev_err("VF %d has caused a PCIe error\n", vf);
9156 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9157 "%8.8x\tdw3: %8.8x\n",
9158 dw0, dw1, dw2, dw3);
9159 switch (adapter->hw.mac.type) {
9160 case ixgbe_mac_82599EB:
9161 device_id = IXGBE_82599_VF_DEVICE_ID;
9162 break;
9163 case ixgbe_mac_X540:
9164 device_id = IXGBE_X540_VF_DEVICE_ID;
9165 break;
9166 case ixgbe_mac_X550:
9167 device_id = IXGBE_DEV_ID_X550_VF;
9168 break;
9169 case ixgbe_mac_X550EM_x:
9170 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9171 break;
9172 default:
9173 device_id = 0;
9174 break;
9175 }
9176
9177 /* Find the pci device of the offending VF */
9178 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
9179 while (vfdev) {
9180 if (vfdev->devfn == (req_id & 0xFF))
9181 break;
9182 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
9183 device_id, vfdev);
9184 }
9185 /*
9186 * There's a slim chance the VF could have been hot plugged,
9187 * so if it is no longer present we don't need to issue the
9188 * VFLR. Just clean up the AER in that case.
9189 */
9190 if (vfdev) {
9191 ixgbe_issue_vf_flr(adapter, vfdev);
9192 /* Free device reference count */
9193 pci_dev_put(vfdev);
9194 }
9195
9196 pci_cleanup_aer_uncorrect_error_status(pdev);
9197 }
9198
9199 /*
9200 * Even though the error may have occurred on the other port
9201 * we still need to increment the vf error reference count for
9202 * both ports because the I/O resume function will be called
9203 * for both of them.
9204 */
9205 adapter->vferr_refcount++;
9206
9207 return PCI_ERS_RESULT_RECOVERED;
9208
9209 skip_bad_vf_detection:
9210 #endif /* CONFIG_PCI_IOV */
9211 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9212 return PCI_ERS_RESULT_DISCONNECT;
9213
9214 rtnl_lock();
9215 netif_device_detach(netdev);
9216
9217 if (state == pci_channel_io_perm_failure) {
9218 rtnl_unlock();
9219 return PCI_ERS_RESULT_DISCONNECT;
9220 }
9221
9222 if (netif_running(netdev))
9223 ixgbe_close_suspend(adapter);
9224
9225 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9226 pci_disable_device(pdev);
9227 rtnl_unlock();
9228
9229 /* Request a slot reset. */
9230 return PCI_ERS_RESULT_NEED_RESET;
9231 }
9232
9233 /**
9234 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9235 * @pdev: Pointer to PCI device
9236 *
9237 * Restart the card from scratch, as if from a cold-boot.
9238 */
9239 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9240 {
9241 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9242 pci_ers_result_t result;
9243 int err;
9244
9245 if (pci_enable_device_mem(pdev)) {
9246 e_err(probe, "Cannot re-enable PCI device after reset.\n");
9247 result = PCI_ERS_RESULT_DISCONNECT;
9248 } else {
9249 smp_mb__before_atomic();
9250 clear_bit(__IXGBE_DISABLED, &adapter->state);
9251 adapter->hw.hw_addr = adapter->io_addr;
9252 pci_set_master(pdev);
9253 pci_restore_state(pdev);
9254 pci_save_state(pdev);
9255
9256 pci_wake_from_d3(pdev, false);
9257
9258 ixgbe_reset(adapter);
9259 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
9260 result = PCI_ERS_RESULT_RECOVERED;
9261 }
9262
9263 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9264 if (err) {
9265 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9266 "failed 0x%0x\n", err);
9267 /* non-fatal, continue */
9268 }
9269
9270 return result;
9271 }
9272
9273 /**
9274 * ixgbe_io_resume - called when traffic can start flowing again.
9275 * @pdev: Pointer to PCI device
9276 *
9277 * This callback is called when the error recovery driver tells us that
9278 * its OK to resume normal operation.
9279 */
9280 static void ixgbe_io_resume(struct pci_dev *pdev)
9281 {
9282 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9283 struct net_device *netdev = adapter->netdev;
9284
9285 #ifdef CONFIG_PCI_IOV
9286 if (adapter->vferr_refcount) {
9287 e_info(drv, "Resuming after VF err\n");
9288 adapter->vferr_refcount--;
9289 return;
9290 }
9291
9292 #endif
9293 rtnl_lock();
9294 if (netif_running(netdev))
9295 ixgbe_open(netdev);
9296
9297 netif_device_attach(netdev);
9298 rtnl_unlock();
9299 }
9300
9301 static const struct pci_error_handlers ixgbe_err_handler = {
9302 .error_detected = ixgbe_io_error_detected,
9303 .slot_reset = ixgbe_io_slot_reset,
9304 .resume = ixgbe_io_resume,
9305 };
9306
9307 static struct pci_driver ixgbe_driver = {
9308 .name = ixgbe_driver_name,
9309 .id_table = ixgbe_pci_tbl,
9310 .probe = ixgbe_probe,
9311 .remove = ixgbe_remove,
9312 #ifdef CONFIG_PM
9313 .suspend = ixgbe_suspend,
9314 .resume = ixgbe_resume,
9315 #endif
9316 .shutdown = ixgbe_shutdown,
9317 .sriov_configure = ixgbe_pci_sriov_configure,
9318 .err_handler = &ixgbe_err_handler
9319 };
9320
9321 /**
9322 * ixgbe_init_module - Driver Registration Routine
9323 *
9324 * ixgbe_init_module is the first routine called when the driver is
9325 * loaded. All it does is register with the PCI subsystem.
9326 **/
9327 static int __init ixgbe_init_module(void)
9328 {
9329 int ret;
9330 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
9331 pr_info("%s\n", ixgbe_copyright);
9332
9333 ixgbe_dbg_init();
9334
9335 ret = pci_register_driver(&ixgbe_driver);
9336 if (ret) {
9337 ixgbe_dbg_exit();
9338 return ret;
9339 }
9340
9341 #ifdef CONFIG_IXGBE_DCA
9342 dca_register_notify(&dca_notifier);
9343 #endif
9344
9345 return 0;
9346 }
9347
9348 module_init(ixgbe_init_module);
9349
9350 /**
9351 * ixgbe_exit_module - Driver Exit Cleanup Routine
9352 *
9353 * ixgbe_exit_module is called just before the driver is removed
9354 * from memory.
9355 **/
9356 static void __exit ixgbe_exit_module(void)
9357 {
9358 #ifdef CONFIG_IXGBE_DCA
9359 dca_unregister_notify(&dca_notifier);
9360 #endif
9361 pci_unregister_driver(&ixgbe_driver);
9362
9363 ixgbe_dbg_exit();
9364 }
9365
9366 #ifdef CONFIG_IXGBE_DCA
9367 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
9368 void *p)
9369 {
9370 int ret_val;
9371
9372 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
9373 __ixgbe_notify_dca);
9374
9375 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9376 }
9377
9378 #endif /* CONFIG_IXGBE_DCA */
9379
9380 module_exit(ixgbe_exit_module);
9381
9382 /* ixgbe_main.c */