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net: vlan: prepare for 802.1ad VLAN filtering offload
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/prefetch.h>
49 #include <scsi/fc/fc_fcoe.h>
50
51 #include "ixgbe.h"
52 #include "ixgbe_common.h"
53 #include "ixgbe_dcb_82599.h"
54 #include "ixgbe_sriov.h"
55
56 char ixgbe_driver_name[] = "ixgbe";
57 static const char ixgbe_driver_string[] =
58 "Intel(R) 10 Gigabit PCI Express Network Driver";
59 #ifdef IXGBE_FCOE
60 char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
62 #else
63 static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65 #endif
66 #define DRV_VERSION "3.13.10-k"
67 const char ixgbe_driver_version[] = DRV_VERSION;
68 static const char ixgbe_copyright[] =
69 "Copyright (c) 1999-2013 Intel Corporation.";
70
71 static const struct ixgbe_info *ixgbe_info_tbl[] = {
72 [board_82598] = &ixgbe_82598_info,
73 [board_82599] = &ixgbe_82599_info,
74 [board_X540] = &ixgbe_X540_info,
75 };
76
77 /* ixgbe_pci_tbl - PCI Device ID Table
78 *
79 * Wildcard entries (PCI_ANY_ID) should come last
80 * Last entry must be all 0s
81 *
82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
83 * Class, Class Mask, private data (not used) }
84 */
85 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
115 /* required last entry */
116 {0, }
117 };
118 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
119
120 #ifdef CONFIG_IXGBE_DCA
121 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
122 void *p);
123 static struct notifier_block dca_notifier = {
124 .notifier_call = ixgbe_notify_dca,
125 .next = NULL,
126 .priority = 0
127 };
128 #endif
129
130 #ifdef CONFIG_PCI_IOV
131 static unsigned int max_vfs;
132 module_param(max_vfs, uint, 0);
133 MODULE_PARM_DESC(max_vfs,
134 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
135 #endif /* CONFIG_PCI_IOV */
136
137 static unsigned int allow_unsupported_sfp;
138 module_param(allow_unsupported_sfp, uint, 0);
139 MODULE_PARM_DESC(allow_unsupported_sfp,
140 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
141
142 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
143 static int debug = -1;
144 module_param(debug, int, 0);
145 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
146
147 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
148 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
149 MODULE_LICENSE("GPL");
150 MODULE_VERSION(DRV_VERSION);
151
152 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
153 u32 reg, u16 *value)
154 {
155 int pos = 0;
156 struct pci_dev *parent_dev;
157 struct pci_bus *parent_bus;
158
159 parent_bus = adapter->pdev->bus->parent;
160 if (!parent_bus)
161 return -1;
162
163 parent_dev = parent_bus->self;
164 if (!parent_dev)
165 return -1;
166
167 pos = pci_find_capability(parent_dev, PCI_CAP_ID_EXP);
168 if (!pos)
169 return -1;
170
171 pci_read_config_word(parent_dev, pos + reg, value);
172 return 0;
173 }
174
175 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
176 {
177 struct ixgbe_hw *hw = &adapter->hw;
178 u16 link_status = 0;
179 int err;
180
181 hw->bus.type = ixgbe_bus_type_pci_express;
182
183 /* Get the negotiated link width and speed from PCI config space of the
184 * parent, as this device is behind a switch
185 */
186 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
187
188 /* assume caller will handle error case */
189 if (err)
190 return err;
191
192 hw->bus.width = ixgbe_convert_bus_width(link_status);
193 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
194
195 return 0;
196 }
197
198 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
199 {
200 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
202 schedule_work(&adapter->service_task);
203 }
204
205 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
206 {
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
208
209 /* flush memory to make sure state is correct before next watchdog */
210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
212 }
213
214 struct ixgbe_reg_info {
215 u32 ofs;
216 char *name;
217 };
218
219 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
220
221 /* General Registers */
222 {IXGBE_CTRL, "CTRL"},
223 {IXGBE_STATUS, "STATUS"},
224 {IXGBE_CTRL_EXT, "CTRL_EXT"},
225
226 /* Interrupt Registers */
227 {IXGBE_EICR, "EICR"},
228
229 /* RX Registers */
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
238
239 /* TX Registers */
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
246
247 /* List Terminator */
248 {}
249 };
250
251
252 /*
253 * ixgbe_regdump - register printout routine
254 */
255 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
256 {
257 int i = 0, j = 0;
258 char rname[16];
259 u32 regs[64];
260
261 switch (reginfo->ofs) {
262 case IXGBE_SRRCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
265 break;
266 case IXGBE_DCA_RXCTRL(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
269 break;
270 case IXGBE_RDLEN(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
273 break;
274 case IXGBE_RDH(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
277 break;
278 case IXGBE_RDT(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
281 break;
282 case IXGBE_RXDCTL(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
285 break;
286 case IXGBE_RDBAL(0):
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
289 break;
290 case IXGBE_RDBAH(0):
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
293 break;
294 case IXGBE_TDBAL(0):
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
297 break;
298 case IXGBE_TDBAH(0):
299 for (i = 0; i < 64; i++)
300 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
301 break;
302 case IXGBE_TDLEN(0):
303 for (i = 0; i < 64; i++)
304 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
305 break;
306 case IXGBE_TDH(0):
307 for (i = 0; i < 64; i++)
308 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
309 break;
310 case IXGBE_TDT(0):
311 for (i = 0; i < 64; i++)
312 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
313 break;
314 case IXGBE_TXDCTL(0):
315 for (i = 0; i < 64; i++)
316 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
317 break;
318 default:
319 pr_info("%-15s %08x\n", reginfo->name,
320 IXGBE_READ_REG(hw, reginfo->ofs));
321 return;
322 }
323
324 for (i = 0; i < 8; i++) {
325 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
326 pr_err("%-15s", rname);
327 for (j = 0; j < 8; j++)
328 pr_cont(" %08x", regs[i*8+j]);
329 pr_cont("\n");
330 }
331
332 }
333
334 /*
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
336 */
337 static void ixgbe_dump(struct ixgbe_adapter *adapter)
338 {
339 struct net_device *netdev = adapter->netdev;
340 struct ixgbe_hw *hw = &adapter->hw;
341 struct ixgbe_reg_info *reginfo;
342 int n = 0;
343 struct ixgbe_ring *tx_ring;
344 struct ixgbe_tx_buffer *tx_buffer;
345 union ixgbe_adv_tx_desc *tx_desc;
346 struct my_u0 { u64 a; u64 b; } *u0;
347 struct ixgbe_ring *rx_ring;
348 union ixgbe_adv_rx_desc *rx_desc;
349 struct ixgbe_rx_buffer *rx_buffer_info;
350 u32 staterr;
351 int i = 0;
352
353 if (!netif_msg_hw(adapter))
354 return;
355
356 /* Print netdevice Info */
357 if (netdev) {
358 dev_info(&adapter->pdev->dev, "Net device Info\n");
359 pr_info("Device Name state "
360 "trans_start last_rx\n");
361 pr_info("%-15s %016lX %016lX %016lX\n",
362 netdev->name,
363 netdev->state,
364 netdev->trans_start,
365 netdev->last_rx);
366 }
367
368 /* Print Registers */
369 dev_info(&adapter->pdev->dev, "Register Dump\n");
370 pr_info(" Register Name Value\n");
371 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
372 reginfo->name; reginfo++) {
373 ixgbe_regdump(hw, reginfo);
374 }
375
376 /* Print TX Ring Summary */
377 if (!netdev || !netif_running(netdev))
378 goto exit;
379
380 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
381 pr_info(" %s %s %s %s\n",
382 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
383 "leng", "ntw", "timestamp");
384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
386 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
387 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
388 n, tx_ring->next_to_use, tx_ring->next_to_clean,
389 (u64)dma_unmap_addr(tx_buffer, dma),
390 dma_unmap_len(tx_buffer, len),
391 tx_buffer->next_to_watch,
392 (u64)tx_buffer->time_stamp);
393 }
394
395 /* Print TX Rings */
396 if (!netif_msg_tx_done(adapter))
397 goto rx_ring_summary;
398
399 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
400
401 /* Transmit Descriptor Formats
402 *
403 * 82598 Advanced Transmit Descriptor
404 * +--------------------------------------------------------------+
405 * 0 | Buffer Address [63:0] |
406 * +--------------------------------------------------------------+
407 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
408 * +--------------------------------------------------------------+
409 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
410 *
411 * 82598 Advanced Transmit Descriptor (Write-Back Format)
412 * +--------------------------------------------------------------+
413 * 0 | RSV [63:0] |
414 * +--------------------------------------------------------------+
415 * 8 | RSV | STA | NXTSEQ |
416 * +--------------------------------------------------------------+
417 * 63 36 35 32 31 0
418 *
419 * 82599+ Advanced Transmit Descriptor
420 * +--------------------------------------------------------------+
421 * 0 | Buffer Address [63:0] |
422 * +--------------------------------------------------------------+
423 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
424 * +--------------------------------------------------------------+
425 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
426 *
427 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
428 * +--------------------------------------------------------------+
429 * 0 | RSV [63:0] |
430 * +--------------------------------------------------------------+
431 * 8 | RSV | STA | RSV |
432 * +--------------------------------------------------------------+
433 * 63 36 35 32 31 0
434 */
435
436 for (n = 0; n < adapter->num_tx_queues; n++) {
437 tx_ring = adapter->tx_ring[n];
438 pr_info("------------------------------------\n");
439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("%s%s %s %s %s %s\n",
442 "T [desc] [address 63:0 ] ",
443 "[PlPOIdStDDt Ln] [bi->dma ] ",
444 "leng", "ntw", "timestamp", "bi->skb");
445
446 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
447 tx_desc = IXGBE_TX_DESC(tx_ring, i);
448 tx_buffer = &tx_ring->tx_buffer_info[i];
449 u0 = (struct my_u0 *)tx_desc;
450 if (dma_unmap_len(tx_buffer, len) > 0) {
451 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
452 i,
453 le64_to_cpu(u0->a),
454 le64_to_cpu(u0->b),
455 (u64)dma_unmap_addr(tx_buffer, dma),
456 dma_unmap_len(tx_buffer, len),
457 tx_buffer->next_to_watch,
458 (u64)tx_buffer->time_stamp,
459 tx_buffer->skb);
460 if (i == tx_ring->next_to_use &&
461 i == tx_ring->next_to_clean)
462 pr_cont(" NTC/U\n");
463 else if (i == tx_ring->next_to_use)
464 pr_cont(" NTU\n");
465 else if (i == tx_ring->next_to_clean)
466 pr_cont(" NTC\n");
467 else
468 pr_cont("\n");
469
470 if (netif_msg_pktdata(adapter) &&
471 tx_buffer->skb)
472 print_hex_dump(KERN_INFO, "",
473 DUMP_PREFIX_ADDRESS, 16, 1,
474 tx_buffer->skb->data,
475 dma_unmap_len(tx_buffer, len),
476 true);
477 }
478 }
479 }
480
481 /* Print RX Rings Summary */
482 rx_ring_summary:
483 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
484 pr_info("Queue [NTU] [NTC]\n");
485 for (n = 0; n < adapter->num_rx_queues; n++) {
486 rx_ring = adapter->rx_ring[n];
487 pr_info("%5d %5X %5X\n",
488 n, rx_ring->next_to_use, rx_ring->next_to_clean);
489 }
490
491 /* Print RX Rings */
492 if (!netif_msg_rx_status(adapter))
493 goto exit;
494
495 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
496
497 /* Receive Descriptor Formats
498 *
499 * 82598 Advanced Receive Descriptor (Read) Format
500 * 63 1 0
501 * +-----------------------------------------------------+
502 * 0 | Packet Buffer Address [63:1] |A0/NSE|
503 * +----------------------------------------------+------+
504 * 8 | Header Buffer Address [63:1] | DD |
505 * +-----------------------------------------------------+
506 *
507 *
508 * 82598 Advanced Receive Descriptor (Write-Back) Format
509 *
510 * 63 48 47 32 31 30 21 20 16 15 4 3 0
511 * +------------------------------------------------------+
512 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
513 * | Packet | IP | | | | Type | Type |
514 * | Checksum | Ident | | | | | |
515 * +------------------------------------------------------+
516 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
517 * +------------------------------------------------------+
518 * 63 48 47 32 31 20 19 0
519 *
520 * 82599+ Advanced Receive Descriptor (Read) Format
521 * 63 1 0
522 * +-----------------------------------------------------+
523 * 0 | Packet Buffer Address [63:1] |A0/NSE|
524 * +----------------------------------------------+------+
525 * 8 | Header Buffer Address [63:1] | DD |
526 * +-----------------------------------------------------+
527 *
528 *
529 * 82599+ Advanced Receive Descriptor (Write-Back) Format
530 *
531 * 63 48 47 32 31 30 21 20 17 16 4 3 0
532 * +------------------------------------------------------+
533 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
534 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
535 * |/ Flow Dir Flt ID | | | | | |
536 * +------------------------------------------------------+
537 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
538 * +------------------------------------------------------+
539 * 63 48 47 32 31 20 19 0
540 */
541
542 for (n = 0; n < adapter->num_rx_queues; n++) {
543 rx_ring = adapter->rx_ring[n];
544 pr_info("------------------------------------\n");
545 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
546 pr_info("------------------------------------\n");
547 pr_info("%s%s%s",
548 "R [desc] [ PktBuf A0] ",
549 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
550 "<-- Adv Rx Read format\n");
551 pr_info("%s%s%s",
552 "RWB[desc] [PcsmIpSHl PtRs] ",
553 "[vl er S cks ln] ---------------- [bi->skb ] ",
554 "<-- Adv Rx Write-Back format\n");
555
556 for (i = 0; i < rx_ring->count; i++) {
557 rx_buffer_info = &rx_ring->rx_buffer_info[i];
558 rx_desc = IXGBE_RX_DESC(rx_ring, i);
559 u0 = (struct my_u0 *)rx_desc;
560 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
561 if (staterr & IXGBE_RXD_STAT_DD) {
562 /* Descriptor Done */
563 pr_info("RWB[0x%03X] %016llX "
564 "%016llX ---------------- %p", i,
565 le64_to_cpu(u0->a),
566 le64_to_cpu(u0->b),
567 rx_buffer_info->skb);
568 } else {
569 pr_info("R [0x%03X] %016llX "
570 "%016llX %016llX %p", i,
571 le64_to_cpu(u0->a),
572 le64_to_cpu(u0->b),
573 (u64)rx_buffer_info->dma,
574 rx_buffer_info->skb);
575
576 if (netif_msg_pktdata(adapter) &&
577 rx_buffer_info->dma) {
578 print_hex_dump(KERN_INFO, "",
579 DUMP_PREFIX_ADDRESS, 16, 1,
580 page_address(rx_buffer_info->page) +
581 rx_buffer_info->page_offset,
582 ixgbe_rx_bufsz(rx_ring), true);
583 }
584 }
585
586 if (i == rx_ring->next_to_use)
587 pr_cont(" NTU\n");
588 else if (i == rx_ring->next_to_clean)
589 pr_cont(" NTC\n");
590 else
591 pr_cont("\n");
592
593 }
594 }
595
596 exit:
597 return;
598 }
599
600 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
601 {
602 u32 ctrl_ext;
603
604 /* Let firmware take over control of h/w */
605 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
606 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
607 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
608 }
609
610 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
611 {
612 u32 ctrl_ext;
613
614 /* Let firmware know the driver has taken over */
615 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
616 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
617 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
618 }
619
620 /**
621 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
622 * @adapter: pointer to adapter struct
623 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
624 * @queue: queue to map the corresponding interrupt to
625 * @msix_vector: the vector to map to the corresponding queue
626 *
627 */
628 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
629 u8 queue, u8 msix_vector)
630 {
631 u32 ivar, index;
632 struct ixgbe_hw *hw = &adapter->hw;
633 switch (hw->mac.type) {
634 case ixgbe_mac_82598EB:
635 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
636 if (direction == -1)
637 direction = 0;
638 index = (((direction * 64) + queue) >> 2) & 0x1F;
639 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
640 ivar &= ~(0xFF << (8 * (queue & 0x3)));
641 ivar |= (msix_vector << (8 * (queue & 0x3)));
642 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
643 break;
644 case ixgbe_mac_82599EB:
645 case ixgbe_mac_X540:
646 if (direction == -1) {
647 /* other causes */
648 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
649 index = ((queue & 1) * 8);
650 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
651 ivar &= ~(0xFF << index);
652 ivar |= (msix_vector << index);
653 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
654 break;
655 } else {
656 /* tx or rx causes */
657 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
658 index = ((16 * (queue & 1)) + (8 * direction));
659 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
660 ivar &= ~(0xFF << index);
661 ivar |= (msix_vector << index);
662 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
663 break;
664 }
665 default:
666 break;
667 }
668 }
669
670 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
671 u64 qmask)
672 {
673 u32 mask;
674
675 switch (adapter->hw.mac.type) {
676 case ixgbe_mac_82598EB:
677 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
678 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
679 break;
680 case ixgbe_mac_82599EB:
681 case ixgbe_mac_X540:
682 mask = (qmask & 0xFFFFFFFF);
683 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
684 mask = (qmask >> 32);
685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
686 break;
687 default:
688 break;
689 }
690 }
691
692 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
693 struct ixgbe_tx_buffer *tx_buffer)
694 {
695 if (tx_buffer->skb) {
696 dev_kfree_skb_any(tx_buffer->skb);
697 if (dma_unmap_len(tx_buffer, len))
698 dma_unmap_single(ring->dev,
699 dma_unmap_addr(tx_buffer, dma),
700 dma_unmap_len(tx_buffer, len),
701 DMA_TO_DEVICE);
702 } else if (dma_unmap_len(tx_buffer, len)) {
703 dma_unmap_page(ring->dev,
704 dma_unmap_addr(tx_buffer, dma),
705 dma_unmap_len(tx_buffer, len),
706 DMA_TO_DEVICE);
707 }
708 tx_buffer->next_to_watch = NULL;
709 tx_buffer->skb = NULL;
710 dma_unmap_len_set(tx_buffer, len, 0);
711 /* tx_buffer must be completely set up in the transmit path */
712 }
713
714 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
715 {
716 struct ixgbe_hw *hw = &adapter->hw;
717 struct ixgbe_hw_stats *hwstats = &adapter->stats;
718 int i;
719 u32 data;
720
721 if ((hw->fc.current_mode != ixgbe_fc_full) &&
722 (hw->fc.current_mode != ixgbe_fc_rx_pause))
723 return;
724
725 switch (hw->mac.type) {
726 case ixgbe_mac_82598EB:
727 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
728 break;
729 default:
730 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
731 }
732 hwstats->lxoffrxc += data;
733
734 /* refill credits (no tx hang) if we received xoff */
735 if (!data)
736 return;
737
738 for (i = 0; i < adapter->num_tx_queues; i++)
739 clear_bit(__IXGBE_HANG_CHECK_ARMED,
740 &adapter->tx_ring[i]->state);
741 }
742
743 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
744 {
745 struct ixgbe_hw *hw = &adapter->hw;
746 struct ixgbe_hw_stats *hwstats = &adapter->stats;
747 u32 xoff[8] = {0};
748 u8 tc;
749 int i;
750 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
751
752 if (adapter->ixgbe_ieee_pfc)
753 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
754
755 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
756 ixgbe_update_xoff_rx_lfc(adapter);
757 return;
758 }
759
760 /* update stats for each tc, only valid with PFC enabled */
761 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
762 u32 pxoffrxc;
763
764 switch (hw->mac.type) {
765 case ixgbe_mac_82598EB:
766 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
767 break;
768 default:
769 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
770 }
771 hwstats->pxoffrxc[i] += pxoffrxc;
772 /* Get the TC for given UP */
773 tc = netdev_get_prio_tc_map(adapter->netdev, i);
774 xoff[tc] += pxoffrxc;
775 }
776
777 /* disarm tx queues that have received xoff frames */
778 for (i = 0; i < adapter->num_tx_queues; i++) {
779 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
780
781 tc = tx_ring->dcb_tc;
782 if (xoff[tc])
783 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
784 }
785 }
786
787 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
788 {
789 return ring->stats.packets;
790 }
791
792 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
793 {
794 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
795 struct ixgbe_hw *hw = &adapter->hw;
796
797 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
798 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
799
800 if (head != tail)
801 return (head < tail) ?
802 tail - head : (tail + ring->count - head);
803
804 return 0;
805 }
806
807 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
808 {
809 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
810 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
811 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
812 bool ret = false;
813
814 clear_check_for_tx_hang(tx_ring);
815
816 /*
817 * Check for a hung queue, but be thorough. This verifies
818 * that a transmit has been completed since the previous
819 * check AND there is at least one packet pending. The
820 * ARMED bit is set to indicate a potential hang. The
821 * bit is cleared if a pause frame is received to remove
822 * false hang detection due to PFC or 802.3x frames. By
823 * requiring this to fail twice we avoid races with
824 * pfc clearing the ARMED bit and conditions where we
825 * run the check_tx_hang logic with a transmit completion
826 * pending but without time to complete it yet.
827 */
828 if ((tx_done_old == tx_done) && tx_pending) {
829 /* make sure it is true for two checks in a row */
830 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
831 &tx_ring->state);
832 } else {
833 /* update completed stats and continue */
834 tx_ring->tx_stats.tx_done_old = tx_done;
835 /* reset the countdown */
836 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
837 }
838
839 return ret;
840 }
841
842 /**
843 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
844 * @adapter: driver private struct
845 **/
846 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
847 {
848
849 /* Do the reset outside of interrupt context */
850 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
851 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
852 e_warn(drv, "initiating reset due to tx timeout\n");
853 ixgbe_service_event_schedule(adapter);
854 }
855 }
856
857 /**
858 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
859 * @q_vector: structure containing interrupt and ring information
860 * @tx_ring: tx ring to clean
861 **/
862 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
863 struct ixgbe_ring *tx_ring)
864 {
865 struct ixgbe_adapter *adapter = q_vector->adapter;
866 struct ixgbe_tx_buffer *tx_buffer;
867 union ixgbe_adv_tx_desc *tx_desc;
868 unsigned int total_bytes = 0, total_packets = 0;
869 unsigned int budget = q_vector->tx.work_limit;
870 unsigned int i = tx_ring->next_to_clean;
871
872 if (test_bit(__IXGBE_DOWN, &adapter->state))
873 return true;
874
875 tx_buffer = &tx_ring->tx_buffer_info[i];
876 tx_desc = IXGBE_TX_DESC(tx_ring, i);
877 i -= tx_ring->count;
878
879 do {
880 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
881
882 /* if next_to_watch is not set then there is no work pending */
883 if (!eop_desc)
884 break;
885
886 /* prevent any other reads prior to eop_desc */
887 read_barrier_depends();
888
889 /* if DD is not set pending work has not been completed */
890 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
891 break;
892
893 /* clear next_to_watch to prevent false hangs */
894 tx_buffer->next_to_watch = NULL;
895
896 /* update the statistics for this packet */
897 total_bytes += tx_buffer->bytecount;
898 total_packets += tx_buffer->gso_segs;
899
900 /* free the skb */
901 dev_kfree_skb_any(tx_buffer->skb);
902
903 /* unmap skb header data */
904 dma_unmap_single(tx_ring->dev,
905 dma_unmap_addr(tx_buffer, dma),
906 dma_unmap_len(tx_buffer, len),
907 DMA_TO_DEVICE);
908
909 /* clear tx_buffer data */
910 tx_buffer->skb = NULL;
911 dma_unmap_len_set(tx_buffer, len, 0);
912
913 /* unmap remaining buffers */
914 while (tx_desc != eop_desc) {
915 tx_buffer++;
916 tx_desc++;
917 i++;
918 if (unlikely(!i)) {
919 i -= tx_ring->count;
920 tx_buffer = tx_ring->tx_buffer_info;
921 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
922 }
923
924 /* unmap any remaining paged data */
925 if (dma_unmap_len(tx_buffer, len)) {
926 dma_unmap_page(tx_ring->dev,
927 dma_unmap_addr(tx_buffer, dma),
928 dma_unmap_len(tx_buffer, len),
929 DMA_TO_DEVICE);
930 dma_unmap_len_set(tx_buffer, len, 0);
931 }
932 }
933
934 /* move us one more past the eop_desc for start of next pkt */
935 tx_buffer++;
936 tx_desc++;
937 i++;
938 if (unlikely(!i)) {
939 i -= tx_ring->count;
940 tx_buffer = tx_ring->tx_buffer_info;
941 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
942 }
943
944 /* issue prefetch for next Tx descriptor */
945 prefetch(tx_desc);
946
947 /* update budget accounting */
948 budget--;
949 } while (likely(budget));
950
951 i += tx_ring->count;
952 tx_ring->next_to_clean = i;
953 u64_stats_update_begin(&tx_ring->syncp);
954 tx_ring->stats.bytes += total_bytes;
955 tx_ring->stats.packets += total_packets;
956 u64_stats_update_end(&tx_ring->syncp);
957 q_vector->tx.total_bytes += total_bytes;
958 q_vector->tx.total_packets += total_packets;
959
960 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
961 /* schedule immediate reset if we believe we hung */
962 struct ixgbe_hw *hw = &adapter->hw;
963 e_err(drv, "Detected Tx Unit Hang\n"
964 " Tx Queue <%d>\n"
965 " TDH, TDT <%x>, <%x>\n"
966 " next_to_use <%x>\n"
967 " next_to_clean <%x>\n"
968 "tx_buffer_info[next_to_clean]\n"
969 " time_stamp <%lx>\n"
970 " jiffies <%lx>\n",
971 tx_ring->queue_index,
972 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
973 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
974 tx_ring->next_to_use, i,
975 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
976
977 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
978
979 e_info(probe,
980 "tx hang %d detected on queue %d, resetting adapter\n",
981 adapter->tx_timeout_count + 1, tx_ring->queue_index);
982
983 /* schedule immediate reset if we believe we hung */
984 ixgbe_tx_timeout_reset(adapter);
985
986 /* the adapter is about to reset, no point in enabling stuff */
987 return true;
988 }
989
990 netdev_tx_completed_queue(txring_txq(tx_ring),
991 total_packets, total_bytes);
992
993 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
994 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
995 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
996 /* Make sure that anybody stopping the queue after this
997 * sees the new next_to_clean.
998 */
999 smp_mb();
1000 if (__netif_subqueue_stopped(tx_ring->netdev,
1001 tx_ring->queue_index)
1002 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1003 netif_wake_subqueue(tx_ring->netdev,
1004 tx_ring->queue_index);
1005 ++tx_ring->tx_stats.restart_queue;
1006 }
1007 }
1008
1009 return !!budget;
1010 }
1011
1012 #ifdef CONFIG_IXGBE_DCA
1013 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1014 struct ixgbe_ring *tx_ring,
1015 int cpu)
1016 {
1017 struct ixgbe_hw *hw = &adapter->hw;
1018 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1019 u16 reg_offset;
1020
1021 switch (hw->mac.type) {
1022 case ixgbe_mac_82598EB:
1023 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1024 break;
1025 case ixgbe_mac_82599EB:
1026 case ixgbe_mac_X540:
1027 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1028 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1029 break;
1030 default:
1031 /* for unknown hardware do not write register */
1032 return;
1033 }
1034
1035 /*
1036 * We can enable relaxed ordering for reads, but not writes when
1037 * DCA is enabled. This is due to a known issue in some chipsets
1038 * which will cause the DCA tag to be cleared.
1039 */
1040 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1041 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1042 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1043
1044 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1045 }
1046
1047 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1048 struct ixgbe_ring *rx_ring,
1049 int cpu)
1050 {
1051 struct ixgbe_hw *hw = &adapter->hw;
1052 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1053 u8 reg_idx = rx_ring->reg_idx;
1054
1055
1056 switch (hw->mac.type) {
1057 case ixgbe_mac_82599EB:
1058 case ixgbe_mac_X540:
1059 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1060 break;
1061 default:
1062 break;
1063 }
1064
1065 /*
1066 * We can enable relaxed ordering for reads, but not writes when
1067 * DCA is enabled. This is due to a known issue in some chipsets
1068 * which will cause the DCA tag to be cleared.
1069 */
1070 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1071 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1072
1073 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1074 }
1075
1076 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1077 {
1078 struct ixgbe_adapter *adapter = q_vector->adapter;
1079 struct ixgbe_ring *ring;
1080 int cpu = get_cpu();
1081
1082 if (q_vector->cpu == cpu)
1083 goto out_no_update;
1084
1085 ixgbe_for_each_ring(ring, q_vector->tx)
1086 ixgbe_update_tx_dca(adapter, ring, cpu);
1087
1088 ixgbe_for_each_ring(ring, q_vector->rx)
1089 ixgbe_update_rx_dca(adapter, ring, cpu);
1090
1091 q_vector->cpu = cpu;
1092 out_no_update:
1093 put_cpu();
1094 }
1095
1096 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1097 {
1098 int i;
1099
1100 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1101 return;
1102
1103 /* always use CB2 mode, difference is masked in the CB driver */
1104 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1105
1106 for (i = 0; i < adapter->num_q_vectors; i++) {
1107 adapter->q_vector[i]->cpu = -1;
1108 ixgbe_update_dca(adapter->q_vector[i]);
1109 }
1110 }
1111
1112 static int __ixgbe_notify_dca(struct device *dev, void *data)
1113 {
1114 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1115 unsigned long event = *(unsigned long *)data;
1116
1117 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1118 return 0;
1119
1120 switch (event) {
1121 case DCA_PROVIDER_ADD:
1122 /* if we're already enabled, don't do it again */
1123 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1124 break;
1125 if (dca_add_requester(dev) == 0) {
1126 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1127 ixgbe_setup_dca(adapter);
1128 break;
1129 }
1130 /* Fall Through since DCA is disabled. */
1131 case DCA_PROVIDER_REMOVE:
1132 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1133 dca_remove_requester(dev);
1134 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1135 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1136 }
1137 break;
1138 }
1139
1140 return 0;
1141 }
1142
1143 #endif /* CONFIG_IXGBE_DCA */
1144 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1145 union ixgbe_adv_rx_desc *rx_desc,
1146 struct sk_buff *skb)
1147 {
1148 if (ring->netdev->features & NETIF_F_RXHASH)
1149 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1150 }
1151
1152 #ifdef IXGBE_FCOE
1153 /**
1154 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1155 * @ring: structure containing ring specific data
1156 * @rx_desc: advanced rx descriptor
1157 *
1158 * Returns : true if it is FCoE pkt
1159 */
1160 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1161 union ixgbe_adv_rx_desc *rx_desc)
1162 {
1163 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1164
1165 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1166 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1167 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1168 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1169 }
1170
1171 #endif /* IXGBE_FCOE */
1172 /**
1173 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1174 * @ring: structure containing ring specific data
1175 * @rx_desc: current Rx descriptor being processed
1176 * @skb: skb currently being received and modified
1177 **/
1178 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1179 union ixgbe_adv_rx_desc *rx_desc,
1180 struct sk_buff *skb)
1181 {
1182 skb_checksum_none_assert(skb);
1183
1184 /* Rx csum disabled */
1185 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1186 return;
1187
1188 /* if IP and error */
1189 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1190 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1191 ring->rx_stats.csum_err++;
1192 return;
1193 }
1194
1195 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1196 return;
1197
1198 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1199 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1200
1201 /*
1202 * 82599 errata, UDP frames with a 0 checksum can be marked as
1203 * checksum errors.
1204 */
1205 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1206 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1207 return;
1208
1209 ring->rx_stats.csum_err++;
1210 return;
1211 }
1212
1213 /* It must be a TCP or UDP packet with a valid checksum */
1214 skb->ip_summed = CHECKSUM_UNNECESSARY;
1215 }
1216
1217 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1218 {
1219 rx_ring->next_to_use = val;
1220
1221 /* update next to alloc since we have filled the ring */
1222 rx_ring->next_to_alloc = val;
1223 /*
1224 * Force memory writes to complete before letting h/w
1225 * know there are new descriptors to fetch. (Only
1226 * applicable for weak-ordered memory model archs,
1227 * such as IA-64).
1228 */
1229 wmb();
1230 writel(val, rx_ring->tail);
1231 }
1232
1233 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1234 struct ixgbe_rx_buffer *bi)
1235 {
1236 struct page *page = bi->page;
1237 dma_addr_t dma = bi->dma;
1238
1239 /* since we are recycling buffers we should seldom need to alloc */
1240 if (likely(dma))
1241 return true;
1242
1243 /* alloc new page for storage */
1244 if (likely(!page)) {
1245 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1246 bi->skb, ixgbe_rx_pg_order(rx_ring));
1247 if (unlikely(!page)) {
1248 rx_ring->rx_stats.alloc_rx_page_failed++;
1249 return false;
1250 }
1251 bi->page = page;
1252 }
1253
1254 /* map page for use */
1255 dma = dma_map_page(rx_ring->dev, page, 0,
1256 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1257
1258 /*
1259 * if mapping failed free memory back to system since
1260 * there isn't much point in holding memory we can't use
1261 */
1262 if (dma_mapping_error(rx_ring->dev, dma)) {
1263 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1264 bi->page = NULL;
1265
1266 rx_ring->rx_stats.alloc_rx_page_failed++;
1267 return false;
1268 }
1269
1270 bi->dma = dma;
1271 bi->page_offset = 0;
1272
1273 return true;
1274 }
1275
1276 /**
1277 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1278 * @rx_ring: ring to place buffers on
1279 * @cleaned_count: number of buffers to replace
1280 **/
1281 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1282 {
1283 union ixgbe_adv_rx_desc *rx_desc;
1284 struct ixgbe_rx_buffer *bi;
1285 u16 i = rx_ring->next_to_use;
1286
1287 /* nothing to do */
1288 if (!cleaned_count)
1289 return;
1290
1291 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1292 bi = &rx_ring->rx_buffer_info[i];
1293 i -= rx_ring->count;
1294
1295 do {
1296 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1297 break;
1298
1299 /*
1300 * Refresh the desc even if buffer_addrs didn't change
1301 * because each write-back erases this info.
1302 */
1303 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1304
1305 rx_desc++;
1306 bi++;
1307 i++;
1308 if (unlikely(!i)) {
1309 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1310 bi = rx_ring->rx_buffer_info;
1311 i -= rx_ring->count;
1312 }
1313
1314 /* clear the hdr_addr for the next_to_use descriptor */
1315 rx_desc->read.hdr_addr = 0;
1316
1317 cleaned_count--;
1318 } while (cleaned_count);
1319
1320 i += rx_ring->count;
1321
1322 if (rx_ring->next_to_use != i)
1323 ixgbe_release_rx_desc(rx_ring, i);
1324 }
1325
1326 /**
1327 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1328 * @data: pointer to the start of the headers
1329 * @max_len: total length of section to find headers in
1330 *
1331 * This function is meant to determine the length of headers that will
1332 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1333 * motivation of doing this is to only perform one pull for IPv4 TCP
1334 * packets so that we can do basic things like calculating the gso_size
1335 * based on the average data per packet.
1336 **/
1337 static unsigned int ixgbe_get_headlen(unsigned char *data,
1338 unsigned int max_len)
1339 {
1340 union {
1341 unsigned char *network;
1342 /* l2 headers */
1343 struct ethhdr *eth;
1344 struct vlan_hdr *vlan;
1345 /* l3 headers */
1346 struct iphdr *ipv4;
1347 struct ipv6hdr *ipv6;
1348 } hdr;
1349 __be16 protocol;
1350 u8 nexthdr = 0; /* default to not TCP */
1351 u8 hlen;
1352
1353 /* this should never happen, but better safe than sorry */
1354 if (max_len < ETH_HLEN)
1355 return max_len;
1356
1357 /* initialize network frame pointer */
1358 hdr.network = data;
1359
1360 /* set first protocol and move network header forward */
1361 protocol = hdr.eth->h_proto;
1362 hdr.network += ETH_HLEN;
1363
1364 /* handle any vlan tag if present */
1365 if (protocol == __constant_htons(ETH_P_8021Q)) {
1366 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1367 return max_len;
1368
1369 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1370 hdr.network += VLAN_HLEN;
1371 }
1372
1373 /* handle L3 protocols */
1374 if (protocol == __constant_htons(ETH_P_IP)) {
1375 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1376 return max_len;
1377
1378 /* access ihl as a u8 to avoid unaligned access on ia64 */
1379 hlen = (hdr.network[0] & 0x0F) << 2;
1380
1381 /* verify hlen meets minimum size requirements */
1382 if (hlen < sizeof(struct iphdr))
1383 return hdr.network - data;
1384
1385 /* record next protocol if header is present */
1386 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
1387 nexthdr = hdr.ipv4->protocol;
1388 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1389 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1390 return max_len;
1391
1392 /* record next protocol */
1393 nexthdr = hdr.ipv6->nexthdr;
1394 hlen = sizeof(struct ipv6hdr);
1395 #ifdef IXGBE_FCOE
1396 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1397 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1398 return max_len;
1399 hlen = FCOE_HEADER_LEN;
1400 #endif
1401 } else {
1402 return hdr.network - data;
1403 }
1404
1405 /* relocate pointer to start of L4 header */
1406 hdr.network += hlen;
1407
1408 /* finally sort out TCP/UDP */
1409 if (nexthdr == IPPROTO_TCP) {
1410 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1411 return max_len;
1412
1413 /* access doff as a u8 to avoid unaligned access on ia64 */
1414 hlen = (hdr.network[12] & 0xF0) >> 2;
1415
1416 /* verify hlen meets minimum size requirements */
1417 if (hlen < sizeof(struct tcphdr))
1418 return hdr.network - data;
1419
1420 hdr.network += hlen;
1421 } else if (nexthdr == IPPROTO_UDP) {
1422 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1423 return max_len;
1424
1425 hdr.network += sizeof(struct udphdr);
1426 }
1427
1428 /*
1429 * If everything has gone correctly hdr.network should be the
1430 * data section of the packet and will be the end of the header.
1431 * If not then it probably represents the end of the last recognized
1432 * header.
1433 */
1434 if ((hdr.network - data) < max_len)
1435 return hdr.network - data;
1436 else
1437 return max_len;
1438 }
1439
1440 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1441 struct sk_buff *skb)
1442 {
1443 u16 hdr_len = skb_headlen(skb);
1444
1445 /* set gso_size to avoid messing up TCP MSS */
1446 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1447 IXGBE_CB(skb)->append_cnt);
1448 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1449 }
1450
1451 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1452 struct sk_buff *skb)
1453 {
1454 /* if append_cnt is 0 then frame is not RSC */
1455 if (!IXGBE_CB(skb)->append_cnt)
1456 return;
1457
1458 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1459 rx_ring->rx_stats.rsc_flush++;
1460
1461 ixgbe_set_rsc_gso_size(rx_ring, skb);
1462
1463 /* gso_size is computed using append_cnt so always clear it last */
1464 IXGBE_CB(skb)->append_cnt = 0;
1465 }
1466
1467 /**
1468 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1469 * @rx_ring: rx descriptor ring packet is being transacted on
1470 * @rx_desc: pointer to the EOP Rx descriptor
1471 * @skb: pointer to current skb being populated
1472 *
1473 * This function checks the ring, descriptor, and packet information in
1474 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1475 * other fields within the skb.
1476 **/
1477 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1478 union ixgbe_adv_rx_desc *rx_desc,
1479 struct sk_buff *skb)
1480 {
1481 struct net_device *dev = rx_ring->netdev;
1482
1483 ixgbe_update_rsc_stats(rx_ring, skb);
1484
1485 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1486
1487 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1488
1489 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1490
1491 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1492 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1493 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1494 __vlan_hwaccel_put_tag(skb, vid);
1495 }
1496
1497 skb_record_rx_queue(skb, rx_ring->queue_index);
1498
1499 skb->protocol = eth_type_trans(skb, dev);
1500 }
1501
1502 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1503 struct sk_buff *skb)
1504 {
1505 struct ixgbe_adapter *adapter = q_vector->adapter;
1506
1507 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1508 napi_gro_receive(&q_vector->napi, skb);
1509 else
1510 netif_rx(skb);
1511 }
1512
1513 /**
1514 * ixgbe_is_non_eop - process handling of non-EOP buffers
1515 * @rx_ring: Rx ring being processed
1516 * @rx_desc: Rx descriptor for current buffer
1517 * @skb: Current socket buffer containing buffer in progress
1518 *
1519 * This function updates next to clean. If the buffer is an EOP buffer
1520 * this function exits returning false, otherwise it will place the
1521 * sk_buff in the next buffer to be chained and return true indicating
1522 * that this is in fact a non-EOP buffer.
1523 **/
1524 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1525 union ixgbe_adv_rx_desc *rx_desc,
1526 struct sk_buff *skb)
1527 {
1528 u32 ntc = rx_ring->next_to_clean + 1;
1529
1530 /* fetch, update, and store next to clean */
1531 ntc = (ntc < rx_ring->count) ? ntc : 0;
1532 rx_ring->next_to_clean = ntc;
1533
1534 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1535
1536 /* update RSC append count if present */
1537 if (ring_is_rsc_enabled(rx_ring)) {
1538 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1539 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1540
1541 if (unlikely(rsc_enabled)) {
1542 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1543
1544 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1545 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1546
1547 /* update ntc based on RSC value */
1548 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1549 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1550 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1551 }
1552 }
1553
1554 /* if we are the last buffer then there is nothing else to do */
1555 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1556 return false;
1557
1558 /* place skb in next buffer to be received */
1559 rx_ring->rx_buffer_info[ntc].skb = skb;
1560 rx_ring->rx_stats.non_eop_descs++;
1561
1562 return true;
1563 }
1564
1565 /**
1566 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1567 * @rx_ring: rx descriptor ring packet is being transacted on
1568 * @skb: pointer to current skb being adjusted
1569 *
1570 * This function is an ixgbe specific version of __pskb_pull_tail. The
1571 * main difference between this version and the original function is that
1572 * this function can make several assumptions about the state of things
1573 * that allow for significant optimizations versus the standard function.
1574 * As a result we can do things like drop a frag and maintain an accurate
1575 * truesize for the skb.
1576 */
1577 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1578 struct sk_buff *skb)
1579 {
1580 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1581 unsigned char *va;
1582 unsigned int pull_len;
1583
1584 /*
1585 * it is valid to use page_address instead of kmap since we are
1586 * working with pages allocated out of the lomem pool per
1587 * alloc_page(GFP_ATOMIC)
1588 */
1589 va = skb_frag_address(frag);
1590
1591 /*
1592 * we need the header to contain the greater of either ETH_HLEN or
1593 * 60 bytes if the skb->len is less than 60 for skb_pad.
1594 */
1595 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1596
1597 /* align pull length to size of long to optimize memcpy performance */
1598 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1599
1600 /* update all of the pointers */
1601 skb_frag_size_sub(frag, pull_len);
1602 frag->page_offset += pull_len;
1603 skb->data_len -= pull_len;
1604 skb->tail += pull_len;
1605 }
1606
1607 /**
1608 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1609 * @rx_ring: rx descriptor ring packet is being transacted on
1610 * @skb: pointer to current skb being updated
1611 *
1612 * This function provides a basic DMA sync up for the first fragment of an
1613 * skb. The reason for doing this is that the first fragment cannot be
1614 * unmapped until we have reached the end of packet descriptor for a buffer
1615 * chain.
1616 */
1617 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1618 struct sk_buff *skb)
1619 {
1620 /* if the page was released unmap it, else just sync our portion */
1621 if (unlikely(IXGBE_CB(skb)->page_released)) {
1622 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1623 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1624 IXGBE_CB(skb)->page_released = false;
1625 } else {
1626 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1627
1628 dma_sync_single_range_for_cpu(rx_ring->dev,
1629 IXGBE_CB(skb)->dma,
1630 frag->page_offset,
1631 ixgbe_rx_bufsz(rx_ring),
1632 DMA_FROM_DEVICE);
1633 }
1634 IXGBE_CB(skb)->dma = 0;
1635 }
1636
1637 /**
1638 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1639 * @rx_ring: rx descriptor ring packet is being transacted on
1640 * @rx_desc: pointer to the EOP Rx descriptor
1641 * @skb: pointer to current skb being fixed
1642 *
1643 * Check for corrupted packet headers caused by senders on the local L2
1644 * embedded NIC switch not setting up their Tx Descriptors right. These
1645 * should be very rare.
1646 *
1647 * Also address the case where we are pulling data in on pages only
1648 * and as such no data is present in the skb header.
1649 *
1650 * In addition if skb is not at least 60 bytes we need to pad it so that
1651 * it is large enough to qualify as a valid Ethernet frame.
1652 *
1653 * Returns true if an error was encountered and skb was freed.
1654 **/
1655 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1656 union ixgbe_adv_rx_desc *rx_desc,
1657 struct sk_buff *skb)
1658 {
1659 struct net_device *netdev = rx_ring->netdev;
1660
1661 /* verify that the packet does not have any known errors */
1662 if (unlikely(ixgbe_test_staterr(rx_desc,
1663 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1664 !(netdev->features & NETIF_F_RXALL))) {
1665 dev_kfree_skb_any(skb);
1666 return true;
1667 }
1668
1669 /* place header in linear portion of buffer */
1670 if (skb_is_nonlinear(skb))
1671 ixgbe_pull_tail(rx_ring, skb);
1672
1673 #ifdef IXGBE_FCOE
1674 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1675 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1676 return false;
1677
1678 #endif
1679 /* if skb_pad returns an error the skb was freed */
1680 if (unlikely(skb->len < 60)) {
1681 int pad_len = 60 - skb->len;
1682
1683 if (skb_pad(skb, pad_len))
1684 return true;
1685 __skb_put(skb, pad_len);
1686 }
1687
1688 return false;
1689 }
1690
1691 /**
1692 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1693 * @rx_ring: rx descriptor ring to store buffers on
1694 * @old_buff: donor buffer to have page reused
1695 *
1696 * Synchronizes page for reuse by the adapter
1697 **/
1698 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1699 struct ixgbe_rx_buffer *old_buff)
1700 {
1701 struct ixgbe_rx_buffer *new_buff;
1702 u16 nta = rx_ring->next_to_alloc;
1703
1704 new_buff = &rx_ring->rx_buffer_info[nta];
1705
1706 /* update, and store next to alloc */
1707 nta++;
1708 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1709
1710 /* transfer page from old buffer to new buffer */
1711 new_buff->page = old_buff->page;
1712 new_buff->dma = old_buff->dma;
1713 new_buff->page_offset = old_buff->page_offset;
1714
1715 /* sync the buffer for use by the device */
1716 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1717 new_buff->page_offset,
1718 ixgbe_rx_bufsz(rx_ring),
1719 DMA_FROM_DEVICE);
1720 }
1721
1722 /**
1723 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1724 * @rx_ring: rx descriptor ring to transact packets on
1725 * @rx_buffer: buffer containing page to add
1726 * @rx_desc: descriptor containing length of buffer written by hardware
1727 * @skb: sk_buff to place the data into
1728 *
1729 * This function will add the data contained in rx_buffer->page to the skb.
1730 * This is done either through a direct copy if the data in the buffer is
1731 * less than the skb header size, otherwise it will just attach the page as
1732 * a frag to the skb.
1733 *
1734 * The function will then update the page offset if necessary and return
1735 * true if the buffer can be reused by the adapter.
1736 **/
1737 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1738 struct ixgbe_rx_buffer *rx_buffer,
1739 union ixgbe_adv_rx_desc *rx_desc,
1740 struct sk_buff *skb)
1741 {
1742 struct page *page = rx_buffer->page;
1743 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1744 #if (PAGE_SIZE < 8192)
1745 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1746 #else
1747 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1748 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1749 ixgbe_rx_bufsz(rx_ring);
1750 #endif
1751
1752 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1753 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1754
1755 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1756
1757 /* we can reuse buffer as-is, just make sure it is local */
1758 if (likely(page_to_nid(page) == numa_node_id()))
1759 return true;
1760
1761 /* this page cannot be reused so discard it */
1762 put_page(page);
1763 return false;
1764 }
1765
1766 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1767 rx_buffer->page_offset, size, truesize);
1768
1769 /* avoid re-using remote pages */
1770 if (unlikely(page_to_nid(page) != numa_node_id()))
1771 return false;
1772
1773 #if (PAGE_SIZE < 8192)
1774 /* if we are only owner of page we can reuse it */
1775 if (unlikely(page_count(page) != 1))
1776 return false;
1777
1778 /* flip page offset to other buffer */
1779 rx_buffer->page_offset ^= truesize;
1780
1781 /*
1782 * since we are the only owner of the page and we need to
1783 * increment it, just set the value to 2 in order to avoid
1784 * an unecessary locked operation
1785 */
1786 atomic_set(&page->_count, 2);
1787 #else
1788 /* move offset up to the next cache line */
1789 rx_buffer->page_offset += truesize;
1790
1791 if (rx_buffer->page_offset > last_offset)
1792 return false;
1793
1794 /* bump ref count on page before it is given to the stack */
1795 get_page(page);
1796 #endif
1797
1798 return true;
1799 }
1800
1801 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1802 union ixgbe_adv_rx_desc *rx_desc)
1803 {
1804 struct ixgbe_rx_buffer *rx_buffer;
1805 struct sk_buff *skb;
1806 struct page *page;
1807
1808 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1809 page = rx_buffer->page;
1810 prefetchw(page);
1811
1812 skb = rx_buffer->skb;
1813
1814 if (likely(!skb)) {
1815 void *page_addr = page_address(page) +
1816 rx_buffer->page_offset;
1817
1818 /* prefetch first cache line of first page */
1819 prefetch(page_addr);
1820 #if L1_CACHE_BYTES < 128
1821 prefetch(page_addr + L1_CACHE_BYTES);
1822 #endif
1823
1824 /* allocate a skb to store the frags */
1825 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1826 IXGBE_RX_HDR_SIZE);
1827 if (unlikely(!skb)) {
1828 rx_ring->rx_stats.alloc_rx_buff_failed++;
1829 return NULL;
1830 }
1831
1832 /*
1833 * we will be copying header into skb->data in
1834 * pskb_may_pull so it is in our interest to prefetch
1835 * it now to avoid a possible cache miss
1836 */
1837 prefetchw(skb->data);
1838
1839 /*
1840 * Delay unmapping of the first packet. It carries the
1841 * header information, HW may still access the header
1842 * after the writeback. Only unmap it when EOP is
1843 * reached
1844 */
1845 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1846 goto dma_sync;
1847
1848 IXGBE_CB(skb)->dma = rx_buffer->dma;
1849 } else {
1850 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1851 ixgbe_dma_sync_frag(rx_ring, skb);
1852
1853 dma_sync:
1854 /* we are reusing so sync this buffer for CPU use */
1855 dma_sync_single_range_for_cpu(rx_ring->dev,
1856 rx_buffer->dma,
1857 rx_buffer->page_offset,
1858 ixgbe_rx_bufsz(rx_ring),
1859 DMA_FROM_DEVICE);
1860 }
1861
1862 /* pull page into skb */
1863 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1864 /* hand second half of page back to the ring */
1865 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1866 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1867 /* the page has been released from the ring */
1868 IXGBE_CB(skb)->page_released = true;
1869 } else {
1870 /* we are not reusing the buffer so unmap it */
1871 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1872 ixgbe_rx_pg_size(rx_ring),
1873 DMA_FROM_DEVICE);
1874 }
1875
1876 /* clear contents of buffer_info */
1877 rx_buffer->skb = NULL;
1878 rx_buffer->dma = 0;
1879 rx_buffer->page = NULL;
1880
1881 return skb;
1882 }
1883
1884 /**
1885 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1886 * @q_vector: structure containing interrupt and ring information
1887 * @rx_ring: rx descriptor ring to transact packets on
1888 * @budget: Total limit on number of packets to process
1889 *
1890 * This function provides a "bounce buffer" approach to Rx interrupt
1891 * processing. The advantage to this is that on systems that have
1892 * expensive overhead for IOMMU access this provides a means of avoiding
1893 * it by maintaining the mapping of the page to the syste.
1894 *
1895 * Returns true if all work is completed without reaching budget
1896 **/
1897 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1898 struct ixgbe_ring *rx_ring,
1899 const int budget)
1900 {
1901 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1902 #ifdef IXGBE_FCOE
1903 struct ixgbe_adapter *adapter = q_vector->adapter;
1904 int ddp_bytes;
1905 unsigned int mss = 0;
1906 #endif /* IXGBE_FCOE */
1907 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1908
1909 do {
1910 union ixgbe_adv_rx_desc *rx_desc;
1911 struct sk_buff *skb;
1912
1913 /* return some buffers to hardware, one at a time is too slow */
1914 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1915 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1916 cleaned_count = 0;
1917 }
1918
1919 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
1920
1921 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1922 break;
1923
1924 /*
1925 * This memory barrier is needed to keep us from reading
1926 * any other fields out of the rx_desc until we know the
1927 * RXD_STAT_DD bit is set
1928 */
1929 rmb();
1930
1931 /* retrieve a buffer from the ring */
1932 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
1933
1934 /* exit if we failed to retrieve a buffer */
1935 if (!skb)
1936 break;
1937
1938 cleaned_count++;
1939
1940 /* place incomplete frames back on ring for completion */
1941 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1942 continue;
1943
1944 /* verify the packet layout is correct */
1945 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1946 continue;
1947
1948 /* probably a little skewed due to removing CRC */
1949 total_rx_bytes += skb->len;
1950
1951 /* populate checksum, timestamp, VLAN, and protocol */
1952 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1953
1954 #ifdef IXGBE_FCOE
1955 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1956 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
1957 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1958 /* include DDPed FCoE data */
1959 if (ddp_bytes > 0) {
1960 if (!mss) {
1961 mss = rx_ring->netdev->mtu -
1962 sizeof(struct fcoe_hdr) -
1963 sizeof(struct fc_frame_header) -
1964 sizeof(struct fcoe_crc_eof);
1965 if (mss > 512)
1966 mss &= ~511;
1967 }
1968 total_rx_bytes += ddp_bytes;
1969 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1970 mss);
1971 }
1972 if (!ddp_bytes) {
1973 dev_kfree_skb_any(skb);
1974 continue;
1975 }
1976 }
1977
1978 #endif /* IXGBE_FCOE */
1979 ixgbe_rx_skb(q_vector, skb);
1980
1981 /* update budget accounting */
1982 total_rx_packets++;
1983 } while (likely(total_rx_packets < budget));
1984
1985 u64_stats_update_begin(&rx_ring->syncp);
1986 rx_ring->stats.packets += total_rx_packets;
1987 rx_ring->stats.bytes += total_rx_bytes;
1988 u64_stats_update_end(&rx_ring->syncp);
1989 q_vector->rx.total_packets += total_rx_packets;
1990 q_vector->rx.total_bytes += total_rx_bytes;
1991
1992 if (cleaned_count)
1993 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1994
1995 return (total_rx_packets < budget);
1996 }
1997
1998 /**
1999 * ixgbe_configure_msix - Configure MSI-X hardware
2000 * @adapter: board private structure
2001 *
2002 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2003 * interrupts.
2004 **/
2005 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2006 {
2007 struct ixgbe_q_vector *q_vector;
2008 int v_idx;
2009 u32 mask;
2010
2011 /* Populate MSIX to EITR Select */
2012 if (adapter->num_vfs > 32) {
2013 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2014 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2015 }
2016
2017 /*
2018 * Populate the IVAR table and set the ITR values to the
2019 * corresponding register.
2020 */
2021 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2022 struct ixgbe_ring *ring;
2023 q_vector = adapter->q_vector[v_idx];
2024
2025 ixgbe_for_each_ring(ring, q_vector->rx)
2026 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2027
2028 ixgbe_for_each_ring(ring, q_vector->tx)
2029 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2030
2031 ixgbe_write_eitr(q_vector);
2032 }
2033
2034 switch (adapter->hw.mac.type) {
2035 case ixgbe_mac_82598EB:
2036 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2037 v_idx);
2038 break;
2039 case ixgbe_mac_82599EB:
2040 case ixgbe_mac_X540:
2041 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2042 break;
2043 default:
2044 break;
2045 }
2046 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2047
2048 /* set up to autoclear timer, and the vectors */
2049 mask = IXGBE_EIMS_ENABLE_MASK;
2050 mask &= ~(IXGBE_EIMS_OTHER |
2051 IXGBE_EIMS_MAILBOX |
2052 IXGBE_EIMS_LSC);
2053
2054 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2055 }
2056
2057 enum latency_range {
2058 lowest_latency = 0,
2059 low_latency = 1,
2060 bulk_latency = 2,
2061 latency_invalid = 255
2062 };
2063
2064 /**
2065 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2066 * @q_vector: structure containing interrupt and ring information
2067 * @ring_container: structure containing ring performance data
2068 *
2069 * Stores a new ITR value based on packets and byte
2070 * counts during the last interrupt. The advantage of per interrupt
2071 * computation is faster updates and more accurate ITR for the current
2072 * traffic pattern. Constants in this function were computed
2073 * based on theoretical maximum wire speed and thresholds were set based
2074 * on testing data as well as attempting to minimize response time
2075 * while increasing bulk throughput.
2076 * this functionality is controlled by the InterruptThrottleRate module
2077 * parameter (see ixgbe_param.c)
2078 **/
2079 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2080 struct ixgbe_ring_container *ring_container)
2081 {
2082 int bytes = ring_container->total_bytes;
2083 int packets = ring_container->total_packets;
2084 u32 timepassed_us;
2085 u64 bytes_perint;
2086 u8 itr_setting = ring_container->itr;
2087
2088 if (packets == 0)
2089 return;
2090
2091 /* simple throttlerate management
2092 * 0-10MB/s lowest (100000 ints/s)
2093 * 10-20MB/s low (20000 ints/s)
2094 * 20-1249MB/s bulk (8000 ints/s)
2095 */
2096 /* what was last interrupt timeslice? */
2097 timepassed_us = q_vector->itr >> 2;
2098 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2099
2100 switch (itr_setting) {
2101 case lowest_latency:
2102 if (bytes_perint > 10)
2103 itr_setting = low_latency;
2104 break;
2105 case low_latency:
2106 if (bytes_perint > 20)
2107 itr_setting = bulk_latency;
2108 else if (bytes_perint <= 10)
2109 itr_setting = lowest_latency;
2110 break;
2111 case bulk_latency:
2112 if (bytes_perint <= 20)
2113 itr_setting = low_latency;
2114 break;
2115 }
2116
2117 /* clear work counters since we have the values we need */
2118 ring_container->total_bytes = 0;
2119 ring_container->total_packets = 0;
2120
2121 /* write updated itr to ring container */
2122 ring_container->itr = itr_setting;
2123 }
2124
2125 /**
2126 * ixgbe_write_eitr - write EITR register in hardware specific way
2127 * @q_vector: structure containing interrupt and ring information
2128 *
2129 * This function is made to be called by ethtool and by the driver
2130 * when it needs to update EITR registers at runtime. Hardware
2131 * specific quirks/differences are taken care of here.
2132 */
2133 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2134 {
2135 struct ixgbe_adapter *adapter = q_vector->adapter;
2136 struct ixgbe_hw *hw = &adapter->hw;
2137 int v_idx = q_vector->v_idx;
2138 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2139
2140 switch (adapter->hw.mac.type) {
2141 case ixgbe_mac_82598EB:
2142 /* must write high and low 16 bits to reset counter */
2143 itr_reg |= (itr_reg << 16);
2144 break;
2145 case ixgbe_mac_82599EB:
2146 case ixgbe_mac_X540:
2147 /*
2148 * set the WDIS bit to not clear the timer bits and cause an
2149 * immediate assertion of the interrupt
2150 */
2151 itr_reg |= IXGBE_EITR_CNT_WDIS;
2152 break;
2153 default:
2154 break;
2155 }
2156 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2157 }
2158
2159 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2160 {
2161 u32 new_itr = q_vector->itr;
2162 u8 current_itr;
2163
2164 ixgbe_update_itr(q_vector, &q_vector->tx);
2165 ixgbe_update_itr(q_vector, &q_vector->rx);
2166
2167 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2168
2169 switch (current_itr) {
2170 /* counts and packets in update_itr are dependent on these numbers */
2171 case lowest_latency:
2172 new_itr = IXGBE_100K_ITR;
2173 break;
2174 case low_latency:
2175 new_itr = IXGBE_20K_ITR;
2176 break;
2177 case bulk_latency:
2178 new_itr = IXGBE_8K_ITR;
2179 break;
2180 default:
2181 break;
2182 }
2183
2184 if (new_itr != q_vector->itr) {
2185 /* do an exponential smoothing */
2186 new_itr = (10 * new_itr * q_vector->itr) /
2187 ((9 * new_itr) + q_vector->itr);
2188
2189 /* save the algorithm value here */
2190 q_vector->itr = new_itr;
2191
2192 ixgbe_write_eitr(q_vector);
2193 }
2194 }
2195
2196 /**
2197 * ixgbe_check_overtemp_subtask - check for over temperature
2198 * @adapter: pointer to adapter
2199 **/
2200 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2201 {
2202 struct ixgbe_hw *hw = &adapter->hw;
2203 u32 eicr = adapter->interrupt_event;
2204
2205 if (test_bit(__IXGBE_DOWN, &adapter->state))
2206 return;
2207
2208 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2209 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2210 return;
2211
2212 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2213
2214 switch (hw->device_id) {
2215 case IXGBE_DEV_ID_82599_T3_LOM:
2216 /*
2217 * Since the warning interrupt is for both ports
2218 * we don't have to check if:
2219 * - This interrupt wasn't for our port.
2220 * - We may have missed the interrupt so always have to
2221 * check if we got a LSC
2222 */
2223 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2224 !(eicr & IXGBE_EICR_LSC))
2225 return;
2226
2227 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2228 u32 speed;
2229 bool link_up = false;
2230
2231 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2232
2233 if (link_up)
2234 return;
2235 }
2236
2237 /* Check if this is not due to overtemp */
2238 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2239 return;
2240
2241 break;
2242 default:
2243 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2244 return;
2245 break;
2246 }
2247 e_crit(drv,
2248 "Network adapter has been stopped because it has over heated. "
2249 "Restart the computer. If the problem persists, "
2250 "power off the system and replace the adapter\n");
2251
2252 adapter->interrupt_event = 0;
2253 }
2254
2255 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2256 {
2257 struct ixgbe_hw *hw = &adapter->hw;
2258
2259 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2260 (eicr & IXGBE_EICR_GPI_SDP1)) {
2261 e_crit(probe, "Fan has stopped, replace the adapter\n");
2262 /* write to clear the interrupt */
2263 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2264 }
2265 }
2266
2267 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2268 {
2269 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2270 return;
2271
2272 switch (adapter->hw.mac.type) {
2273 case ixgbe_mac_82599EB:
2274 /*
2275 * Need to check link state so complete overtemp check
2276 * on service task
2277 */
2278 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2279 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2280 adapter->interrupt_event = eicr;
2281 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2282 ixgbe_service_event_schedule(adapter);
2283 return;
2284 }
2285 return;
2286 case ixgbe_mac_X540:
2287 if (!(eicr & IXGBE_EICR_TS))
2288 return;
2289 break;
2290 default:
2291 return;
2292 }
2293
2294 e_crit(drv,
2295 "Network adapter has been stopped because it has over heated. "
2296 "Restart the computer. If the problem persists, "
2297 "power off the system and replace the adapter\n");
2298 }
2299
2300 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2301 {
2302 struct ixgbe_hw *hw = &adapter->hw;
2303
2304 if (eicr & IXGBE_EICR_GPI_SDP2) {
2305 /* Clear the interrupt */
2306 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2307 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2308 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2309 ixgbe_service_event_schedule(adapter);
2310 }
2311 }
2312
2313 if (eicr & IXGBE_EICR_GPI_SDP1) {
2314 /* Clear the interrupt */
2315 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2316 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2317 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2318 ixgbe_service_event_schedule(adapter);
2319 }
2320 }
2321 }
2322
2323 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2324 {
2325 struct ixgbe_hw *hw = &adapter->hw;
2326
2327 adapter->lsc_int++;
2328 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2329 adapter->link_check_timeout = jiffies;
2330 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2331 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2332 IXGBE_WRITE_FLUSH(hw);
2333 ixgbe_service_event_schedule(adapter);
2334 }
2335 }
2336
2337 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2338 u64 qmask)
2339 {
2340 u32 mask;
2341 struct ixgbe_hw *hw = &adapter->hw;
2342
2343 switch (hw->mac.type) {
2344 case ixgbe_mac_82598EB:
2345 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2346 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2347 break;
2348 case ixgbe_mac_82599EB:
2349 case ixgbe_mac_X540:
2350 mask = (qmask & 0xFFFFFFFF);
2351 if (mask)
2352 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2353 mask = (qmask >> 32);
2354 if (mask)
2355 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2356 break;
2357 default:
2358 break;
2359 }
2360 /* skip the flush */
2361 }
2362
2363 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2364 u64 qmask)
2365 {
2366 u32 mask;
2367 struct ixgbe_hw *hw = &adapter->hw;
2368
2369 switch (hw->mac.type) {
2370 case ixgbe_mac_82598EB:
2371 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2372 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2373 break;
2374 case ixgbe_mac_82599EB:
2375 case ixgbe_mac_X540:
2376 mask = (qmask & 0xFFFFFFFF);
2377 if (mask)
2378 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2379 mask = (qmask >> 32);
2380 if (mask)
2381 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2382 break;
2383 default:
2384 break;
2385 }
2386 /* skip the flush */
2387 }
2388
2389 /**
2390 * ixgbe_irq_enable - Enable default interrupt generation settings
2391 * @adapter: board private structure
2392 **/
2393 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2394 bool flush)
2395 {
2396 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2397
2398 /* don't reenable LSC while waiting for link */
2399 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2400 mask &= ~IXGBE_EIMS_LSC;
2401
2402 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2403 switch (adapter->hw.mac.type) {
2404 case ixgbe_mac_82599EB:
2405 mask |= IXGBE_EIMS_GPI_SDP0;
2406 break;
2407 case ixgbe_mac_X540:
2408 mask |= IXGBE_EIMS_TS;
2409 break;
2410 default:
2411 break;
2412 }
2413 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2414 mask |= IXGBE_EIMS_GPI_SDP1;
2415 switch (adapter->hw.mac.type) {
2416 case ixgbe_mac_82599EB:
2417 mask |= IXGBE_EIMS_GPI_SDP1;
2418 mask |= IXGBE_EIMS_GPI_SDP2;
2419 case ixgbe_mac_X540:
2420 mask |= IXGBE_EIMS_ECC;
2421 mask |= IXGBE_EIMS_MAILBOX;
2422 break;
2423 default:
2424 break;
2425 }
2426
2427 if (adapter->hw.mac.type == ixgbe_mac_X540)
2428 mask |= IXGBE_EIMS_TIMESYNC;
2429
2430 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2431 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2432 mask |= IXGBE_EIMS_FLOW_DIR;
2433
2434 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2435 if (queues)
2436 ixgbe_irq_enable_queues(adapter, ~0);
2437 if (flush)
2438 IXGBE_WRITE_FLUSH(&adapter->hw);
2439 }
2440
2441 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2442 {
2443 struct ixgbe_adapter *adapter = data;
2444 struct ixgbe_hw *hw = &adapter->hw;
2445 u32 eicr;
2446
2447 /*
2448 * Workaround for Silicon errata. Use clear-by-write instead
2449 * of clear-by-read. Reading with EICS will return the
2450 * interrupt causes without clearing, which later be done
2451 * with the write to EICR.
2452 */
2453 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2454 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2455
2456 if (eicr & IXGBE_EICR_LSC)
2457 ixgbe_check_lsc(adapter);
2458
2459 if (eicr & IXGBE_EICR_MAILBOX)
2460 ixgbe_msg_task(adapter);
2461
2462 switch (hw->mac.type) {
2463 case ixgbe_mac_82599EB:
2464 case ixgbe_mac_X540:
2465 if (eicr & IXGBE_EICR_ECC)
2466 e_info(link, "Received unrecoverable ECC Err, please "
2467 "reboot\n");
2468 /* Handle Flow Director Full threshold interrupt */
2469 if (eicr & IXGBE_EICR_FLOW_DIR) {
2470 int reinit_count = 0;
2471 int i;
2472 for (i = 0; i < adapter->num_tx_queues; i++) {
2473 struct ixgbe_ring *ring = adapter->tx_ring[i];
2474 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2475 &ring->state))
2476 reinit_count++;
2477 }
2478 if (reinit_count) {
2479 /* no more flow director interrupts until after init */
2480 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2481 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2482 ixgbe_service_event_schedule(adapter);
2483 }
2484 }
2485 ixgbe_check_sfp_event(adapter, eicr);
2486 ixgbe_check_overtemp_event(adapter, eicr);
2487 break;
2488 default:
2489 break;
2490 }
2491
2492 ixgbe_check_fan_failure(adapter, eicr);
2493
2494 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2495 ixgbe_ptp_check_pps_event(adapter, eicr);
2496
2497 /* re-enable the original interrupt state, no lsc, no queues */
2498 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2499 ixgbe_irq_enable(adapter, false, false);
2500
2501 return IRQ_HANDLED;
2502 }
2503
2504 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2505 {
2506 struct ixgbe_q_vector *q_vector = data;
2507
2508 /* EIAM disabled interrupts (on this vector) for us */
2509
2510 if (q_vector->rx.ring || q_vector->tx.ring)
2511 napi_schedule(&q_vector->napi);
2512
2513 return IRQ_HANDLED;
2514 }
2515
2516 /**
2517 * ixgbe_poll - NAPI Rx polling callback
2518 * @napi: structure for representing this polling device
2519 * @budget: how many packets driver is allowed to clean
2520 *
2521 * This function is used for legacy and MSI, NAPI mode
2522 **/
2523 int ixgbe_poll(struct napi_struct *napi, int budget)
2524 {
2525 struct ixgbe_q_vector *q_vector =
2526 container_of(napi, struct ixgbe_q_vector, napi);
2527 struct ixgbe_adapter *adapter = q_vector->adapter;
2528 struct ixgbe_ring *ring;
2529 int per_ring_budget;
2530 bool clean_complete = true;
2531
2532 #ifdef CONFIG_IXGBE_DCA
2533 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2534 ixgbe_update_dca(q_vector);
2535 #endif
2536
2537 ixgbe_for_each_ring(ring, q_vector->tx)
2538 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2539
2540 /* attempt to distribute budget to each queue fairly, but don't allow
2541 * the budget to go below 1 because we'll exit polling */
2542 if (q_vector->rx.count > 1)
2543 per_ring_budget = max(budget/q_vector->rx.count, 1);
2544 else
2545 per_ring_budget = budget;
2546
2547 ixgbe_for_each_ring(ring, q_vector->rx)
2548 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2549 per_ring_budget);
2550
2551 /* If all work not completed, return budget and keep polling */
2552 if (!clean_complete)
2553 return budget;
2554
2555 /* all work done, exit the polling mode */
2556 napi_complete(napi);
2557 if (adapter->rx_itr_setting & 1)
2558 ixgbe_set_itr(q_vector);
2559 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2560 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2561
2562 return 0;
2563 }
2564
2565 /**
2566 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2567 * @adapter: board private structure
2568 *
2569 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2570 * interrupts from the kernel.
2571 **/
2572 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2573 {
2574 struct net_device *netdev = adapter->netdev;
2575 int vector, err;
2576 int ri = 0, ti = 0;
2577
2578 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2579 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2580 struct msix_entry *entry = &adapter->msix_entries[vector];
2581
2582 if (q_vector->tx.ring && q_vector->rx.ring) {
2583 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2584 "%s-%s-%d", netdev->name, "TxRx", ri++);
2585 ti++;
2586 } else if (q_vector->rx.ring) {
2587 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2588 "%s-%s-%d", netdev->name, "rx", ri++);
2589 } else if (q_vector->tx.ring) {
2590 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2591 "%s-%s-%d", netdev->name, "tx", ti++);
2592 } else {
2593 /* skip this unused q_vector */
2594 continue;
2595 }
2596 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2597 q_vector->name, q_vector);
2598 if (err) {
2599 e_err(probe, "request_irq failed for MSIX interrupt "
2600 "Error: %d\n", err);
2601 goto free_queue_irqs;
2602 }
2603 /* If Flow Director is enabled, set interrupt affinity */
2604 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2605 /* assign the mask for this irq */
2606 irq_set_affinity_hint(entry->vector,
2607 &q_vector->affinity_mask);
2608 }
2609 }
2610
2611 err = request_irq(adapter->msix_entries[vector].vector,
2612 ixgbe_msix_other, 0, netdev->name, adapter);
2613 if (err) {
2614 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2615 goto free_queue_irqs;
2616 }
2617
2618 return 0;
2619
2620 free_queue_irqs:
2621 while (vector) {
2622 vector--;
2623 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2624 NULL);
2625 free_irq(adapter->msix_entries[vector].vector,
2626 adapter->q_vector[vector]);
2627 }
2628 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2629 pci_disable_msix(adapter->pdev);
2630 kfree(adapter->msix_entries);
2631 adapter->msix_entries = NULL;
2632 return err;
2633 }
2634
2635 /**
2636 * ixgbe_intr - legacy mode Interrupt Handler
2637 * @irq: interrupt number
2638 * @data: pointer to a network interface device structure
2639 **/
2640 static irqreturn_t ixgbe_intr(int irq, void *data)
2641 {
2642 struct ixgbe_adapter *adapter = data;
2643 struct ixgbe_hw *hw = &adapter->hw;
2644 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2645 u32 eicr;
2646
2647 /*
2648 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2649 * before the read of EICR.
2650 */
2651 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2652
2653 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2654 * therefore no explicit interrupt disable is necessary */
2655 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2656 if (!eicr) {
2657 /*
2658 * shared interrupt alert!
2659 * make sure interrupts are enabled because the read will
2660 * have disabled interrupts due to EIAM
2661 * finish the workaround of silicon errata on 82598. Unmask
2662 * the interrupt that we masked before the EICR read.
2663 */
2664 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2665 ixgbe_irq_enable(adapter, true, true);
2666 return IRQ_NONE; /* Not our interrupt */
2667 }
2668
2669 if (eicr & IXGBE_EICR_LSC)
2670 ixgbe_check_lsc(adapter);
2671
2672 switch (hw->mac.type) {
2673 case ixgbe_mac_82599EB:
2674 ixgbe_check_sfp_event(adapter, eicr);
2675 /* Fall through */
2676 case ixgbe_mac_X540:
2677 if (eicr & IXGBE_EICR_ECC)
2678 e_info(link, "Received unrecoverable ECC err, please "
2679 "reboot\n");
2680 ixgbe_check_overtemp_event(adapter, eicr);
2681 break;
2682 default:
2683 break;
2684 }
2685
2686 ixgbe_check_fan_failure(adapter, eicr);
2687 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2688 ixgbe_ptp_check_pps_event(adapter, eicr);
2689
2690 /* would disable interrupts here but EIAM disabled it */
2691 napi_schedule(&q_vector->napi);
2692
2693 /*
2694 * re-enable link(maybe) and non-queue interrupts, no flush.
2695 * ixgbe_poll will re-enable the queue interrupts
2696 */
2697 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2698 ixgbe_irq_enable(adapter, false, false);
2699
2700 return IRQ_HANDLED;
2701 }
2702
2703 /**
2704 * ixgbe_request_irq - initialize interrupts
2705 * @adapter: board private structure
2706 *
2707 * Attempts to configure interrupts using the best available
2708 * capabilities of the hardware and kernel.
2709 **/
2710 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2711 {
2712 struct net_device *netdev = adapter->netdev;
2713 int err;
2714
2715 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2716 err = ixgbe_request_msix_irqs(adapter);
2717 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2718 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2719 netdev->name, adapter);
2720 else
2721 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2722 netdev->name, adapter);
2723
2724 if (err)
2725 e_err(probe, "request_irq failed, Error %d\n", err);
2726
2727 return err;
2728 }
2729
2730 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2731 {
2732 int vector;
2733
2734 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2735 free_irq(adapter->pdev->irq, adapter);
2736 return;
2737 }
2738
2739 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2740 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2741 struct msix_entry *entry = &adapter->msix_entries[vector];
2742
2743 /* free only the irqs that were actually requested */
2744 if (!q_vector->rx.ring && !q_vector->tx.ring)
2745 continue;
2746
2747 /* clear the affinity_mask in the IRQ descriptor */
2748 irq_set_affinity_hint(entry->vector, NULL);
2749
2750 free_irq(entry->vector, q_vector);
2751 }
2752
2753 free_irq(adapter->msix_entries[vector++].vector, adapter);
2754 }
2755
2756 /**
2757 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2758 * @adapter: board private structure
2759 **/
2760 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2761 {
2762 switch (adapter->hw.mac.type) {
2763 case ixgbe_mac_82598EB:
2764 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2765 break;
2766 case ixgbe_mac_82599EB:
2767 case ixgbe_mac_X540:
2768 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2770 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2771 break;
2772 default:
2773 break;
2774 }
2775 IXGBE_WRITE_FLUSH(&adapter->hw);
2776 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2777 int vector;
2778
2779 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2780 synchronize_irq(adapter->msix_entries[vector].vector);
2781
2782 synchronize_irq(adapter->msix_entries[vector++].vector);
2783 } else {
2784 synchronize_irq(adapter->pdev->irq);
2785 }
2786 }
2787
2788 /**
2789 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2790 *
2791 **/
2792 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2793 {
2794 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2795
2796 ixgbe_write_eitr(q_vector);
2797
2798 ixgbe_set_ivar(adapter, 0, 0, 0);
2799 ixgbe_set_ivar(adapter, 1, 0, 0);
2800
2801 e_info(hw, "Legacy interrupt IVAR setup done\n");
2802 }
2803
2804 /**
2805 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2806 * @adapter: board private structure
2807 * @ring: structure containing ring specific data
2808 *
2809 * Configure the Tx descriptor ring after a reset.
2810 **/
2811 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2812 struct ixgbe_ring *ring)
2813 {
2814 struct ixgbe_hw *hw = &adapter->hw;
2815 u64 tdba = ring->dma;
2816 int wait_loop = 10;
2817 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2818 u8 reg_idx = ring->reg_idx;
2819
2820 /* disable queue to avoid issues while updating state */
2821 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2822 IXGBE_WRITE_FLUSH(hw);
2823
2824 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2825 (tdba & DMA_BIT_MASK(32)));
2826 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2827 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2828 ring->count * sizeof(union ixgbe_adv_tx_desc));
2829 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2830 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2831 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2832
2833 /*
2834 * set WTHRESH to encourage burst writeback, it should not be set
2835 * higher than 1 when:
2836 * - ITR is 0 as it could cause false TX hangs
2837 * - ITR is set to > 100k int/sec and BQL is enabled
2838 *
2839 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2840 * to or less than the number of on chip descriptors, which is
2841 * currently 40.
2842 */
2843 #if IS_ENABLED(CONFIG_BQL)
2844 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2845 #else
2846 if (!ring->q_vector || (ring->q_vector->itr < 8))
2847 #endif
2848 txdctl |= (1 << 16); /* WTHRESH = 1 */
2849 else
2850 txdctl |= (8 << 16); /* WTHRESH = 8 */
2851
2852 /*
2853 * Setting PTHRESH to 32 both improves performance
2854 * and avoids a TX hang with DFP enabled
2855 */
2856 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2857 32; /* PTHRESH = 32 */
2858
2859 /* reinitialize flowdirector state */
2860 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2861 ring->atr_sample_rate = adapter->atr_sample_rate;
2862 ring->atr_count = 0;
2863 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2864 } else {
2865 ring->atr_sample_rate = 0;
2866 }
2867
2868 /* initialize XPS */
2869 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
2870 struct ixgbe_q_vector *q_vector = ring->q_vector;
2871
2872 if (q_vector)
2873 netif_set_xps_queue(adapter->netdev,
2874 &q_vector->affinity_mask,
2875 ring->queue_index);
2876 }
2877
2878 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2879
2880 /* enable queue */
2881 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2882
2883 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2884 if (hw->mac.type == ixgbe_mac_82598EB &&
2885 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2886 return;
2887
2888 /* poll to verify queue is enabled */
2889 do {
2890 usleep_range(1000, 2000);
2891 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2892 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2893 if (!wait_loop)
2894 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2895 }
2896
2897 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2898 {
2899 struct ixgbe_hw *hw = &adapter->hw;
2900 u32 rttdcs, mtqc;
2901 u8 tcs = netdev_get_num_tc(adapter->netdev);
2902
2903 if (hw->mac.type == ixgbe_mac_82598EB)
2904 return;
2905
2906 /* disable the arbiter while setting MTQC */
2907 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2908 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2909 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2910
2911 /* set transmit pool layout */
2912 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2913 mtqc = IXGBE_MTQC_VT_ENA;
2914 if (tcs > 4)
2915 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2916 else if (tcs > 1)
2917 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2918 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2919 mtqc |= IXGBE_MTQC_32VF;
2920 else
2921 mtqc |= IXGBE_MTQC_64VF;
2922 } else {
2923 if (tcs > 4)
2924 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2925 else if (tcs > 1)
2926 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2927 else
2928 mtqc = IXGBE_MTQC_64Q_1PB;
2929 }
2930
2931 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
2932
2933 /* Enable Security TX Buffer IFG for multiple pb */
2934 if (tcs) {
2935 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2936 sectx |= IXGBE_SECTX_DCB;
2937 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
2938 }
2939
2940 /* re-enable the arbiter */
2941 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2942 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2943 }
2944
2945 /**
2946 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2947 * @adapter: board private structure
2948 *
2949 * Configure the Tx unit of the MAC after a reset.
2950 **/
2951 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2952 {
2953 struct ixgbe_hw *hw = &adapter->hw;
2954 u32 dmatxctl;
2955 u32 i;
2956
2957 ixgbe_setup_mtqc(adapter);
2958
2959 if (hw->mac.type != ixgbe_mac_82598EB) {
2960 /* DMATXCTL.EN must be before Tx queues are enabled */
2961 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2962 dmatxctl |= IXGBE_DMATXCTL_TE;
2963 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2964 }
2965
2966 /* Setup the HW Tx Head and Tail descriptor pointers */
2967 for (i = 0; i < adapter->num_tx_queues; i++)
2968 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2969 }
2970
2971 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2972 struct ixgbe_ring *ring)
2973 {
2974 struct ixgbe_hw *hw = &adapter->hw;
2975 u8 reg_idx = ring->reg_idx;
2976 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2977
2978 srrctl |= IXGBE_SRRCTL_DROP_EN;
2979
2980 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2981 }
2982
2983 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2984 struct ixgbe_ring *ring)
2985 {
2986 struct ixgbe_hw *hw = &adapter->hw;
2987 u8 reg_idx = ring->reg_idx;
2988 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2989
2990 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2991
2992 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2993 }
2994
2995 #ifdef CONFIG_IXGBE_DCB
2996 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2997 #else
2998 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2999 #endif
3000 {
3001 int i;
3002 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3003
3004 if (adapter->ixgbe_ieee_pfc)
3005 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3006
3007 /*
3008 * We should set the drop enable bit if:
3009 * SR-IOV is enabled
3010 * or
3011 * Number of Rx queues > 1 and flow control is disabled
3012 *
3013 * This allows us to avoid head of line blocking for security
3014 * and performance reasons.
3015 */
3016 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3017 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3018 for (i = 0; i < adapter->num_rx_queues; i++)
3019 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3020 } else {
3021 for (i = 0; i < adapter->num_rx_queues; i++)
3022 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3023 }
3024 }
3025
3026 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3027
3028 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3029 struct ixgbe_ring *rx_ring)
3030 {
3031 struct ixgbe_hw *hw = &adapter->hw;
3032 u32 srrctl;
3033 u8 reg_idx = rx_ring->reg_idx;
3034
3035 if (hw->mac.type == ixgbe_mac_82598EB) {
3036 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3037
3038 /*
3039 * if VMDq is not active we must program one srrctl register
3040 * per RSS queue since we have enabled RDRXCTL.MVMEN
3041 */
3042 reg_idx &= mask;
3043 }
3044
3045 /* configure header buffer length, needed for RSC */
3046 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3047
3048 /* configure the packet buffer length */
3049 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3050
3051 /* configure descriptor type */
3052 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3053
3054 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3055 }
3056
3057 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3058 {
3059 struct ixgbe_hw *hw = &adapter->hw;
3060 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
3061 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3062 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3063 u32 mrqc = 0, reta = 0;
3064 u32 rxcsum;
3065 int i, j;
3066 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3067
3068 /*
3069 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3070 * make full use of any rings they may have. We will use the
3071 * PSRTYPE register to control how many rings we use within the PF.
3072 */
3073 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3074 rss_i = 2;
3075
3076 /* Fill out hash function seeds */
3077 for (i = 0; i < 10; i++)
3078 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3079
3080 /* Fill out redirection table */
3081 for (i = 0, j = 0; i < 128; i++, j++) {
3082 if (j == rss_i)
3083 j = 0;
3084 /* reta = 4-byte sliding window of
3085 * 0x00..(indices-1)(indices-1)00..etc. */
3086 reta = (reta << 8) | (j * 0x11);
3087 if ((i & 3) == 3)
3088 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3089 }
3090
3091 /* Disable indicating checksum in descriptor, enables RSS hash */
3092 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3093 rxcsum |= IXGBE_RXCSUM_PCSD;
3094 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3095
3096 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3097 if (adapter->ring_feature[RING_F_RSS].mask)
3098 mrqc = IXGBE_MRQC_RSSEN;
3099 } else {
3100 u8 tcs = netdev_get_num_tc(adapter->netdev);
3101
3102 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3103 if (tcs > 4)
3104 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3105 else if (tcs > 1)
3106 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3107 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3108 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3109 else
3110 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3111 } else {
3112 if (tcs > 4)
3113 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3114 else if (tcs > 1)
3115 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3116 else
3117 mrqc = IXGBE_MRQC_RSSEN;
3118 }
3119 }
3120
3121 /* Perform hash on these packet types */
3122 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3123 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3124 IXGBE_MRQC_RSS_FIELD_IPV6 |
3125 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3126
3127 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3128 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3129 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3130 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3131
3132 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3133 }
3134
3135 /**
3136 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3137 * @adapter: address of board private structure
3138 * @index: index of ring to set
3139 **/
3140 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3141 struct ixgbe_ring *ring)
3142 {
3143 struct ixgbe_hw *hw = &adapter->hw;
3144 u32 rscctrl;
3145 u8 reg_idx = ring->reg_idx;
3146
3147 if (!ring_is_rsc_enabled(ring))
3148 return;
3149
3150 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3151 rscctrl |= IXGBE_RSCCTL_RSCEN;
3152 /*
3153 * we must limit the number of descriptors so that the
3154 * total size of max desc * buf_len is not greater
3155 * than 65536
3156 */
3157 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3158 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3159 }
3160
3161 #define IXGBE_MAX_RX_DESC_POLL 10
3162 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3163 struct ixgbe_ring *ring)
3164 {
3165 struct ixgbe_hw *hw = &adapter->hw;
3166 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3167 u32 rxdctl;
3168 u8 reg_idx = ring->reg_idx;
3169
3170 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3171 if (hw->mac.type == ixgbe_mac_82598EB &&
3172 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3173 return;
3174
3175 do {
3176 usleep_range(1000, 2000);
3177 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3178 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3179
3180 if (!wait_loop) {
3181 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3182 "the polling period\n", reg_idx);
3183 }
3184 }
3185
3186 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3187 struct ixgbe_ring *ring)
3188 {
3189 struct ixgbe_hw *hw = &adapter->hw;
3190 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3191 u32 rxdctl;
3192 u8 reg_idx = ring->reg_idx;
3193
3194 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3195 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3196
3197 /* write value back with RXDCTL.ENABLE bit cleared */
3198 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3199
3200 if (hw->mac.type == ixgbe_mac_82598EB &&
3201 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3202 return;
3203
3204 /* the hardware may take up to 100us to really disable the rx queue */
3205 do {
3206 udelay(10);
3207 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3208 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3209
3210 if (!wait_loop) {
3211 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3212 "the polling period\n", reg_idx);
3213 }
3214 }
3215
3216 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3217 struct ixgbe_ring *ring)
3218 {
3219 struct ixgbe_hw *hw = &adapter->hw;
3220 u64 rdba = ring->dma;
3221 u32 rxdctl;
3222 u8 reg_idx = ring->reg_idx;
3223
3224 /* disable queue to avoid issues while updating state */
3225 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3226 ixgbe_disable_rx_queue(adapter, ring);
3227
3228 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3229 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3230 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3231 ring->count * sizeof(union ixgbe_adv_rx_desc));
3232 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3233 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3234 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3235
3236 ixgbe_configure_srrctl(adapter, ring);
3237 ixgbe_configure_rscctl(adapter, ring);
3238
3239 if (hw->mac.type == ixgbe_mac_82598EB) {
3240 /*
3241 * enable cache line friendly hardware writes:
3242 * PTHRESH=32 descriptors (half the internal cache),
3243 * this also removes ugly rx_no_buffer_count increment
3244 * HTHRESH=4 descriptors (to minimize latency on fetch)
3245 * WTHRESH=8 burst writeback up to two cache lines
3246 */
3247 rxdctl &= ~0x3FFFFF;
3248 rxdctl |= 0x080420;
3249 }
3250
3251 /* enable receive descriptor ring */
3252 rxdctl |= IXGBE_RXDCTL_ENABLE;
3253 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3254
3255 ixgbe_rx_desc_queue_enable(adapter, ring);
3256 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3257 }
3258
3259 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3260 {
3261 struct ixgbe_hw *hw = &adapter->hw;
3262 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3263 int p;
3264
3265 /* PSRTYPE must be initialized in non 82598 adapters */
3266 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3267 IXGBE_PSRTYPE_UDPHDR |
3268 IXGBE_PSRTYPE_IPV4HDR |
3269 IXGBE_PSRTYPE_L2HDR |
3270 IXGBE_PSRTYPE_IPV6HDR;
3271
3272 if (hw->mac.type == ixgbe_mac_82598EB)
3273 return;
3274
3275 if (rss_i > 3)
3276 psrtype |= 2 << 29;
3277 else if (rss_i > 1)
3278 psrtype |= 1 << 29;
3279
3280 for (p = 0; p < adapter->num_rx_pools; p++)
3281 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
3282 psrtype);
3283 }
3284
3285 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3286 {
3287 struct ixgbe_hw *hw = &adapter->hw;
3288 u32 reg_offset, vf_shift;
3289 u32 gcr_ext, vmdctl;
3290 int i;
3291
3292 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3293 return;
3294
3295 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3296 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3297 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3298 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3299 vmdctl |= IXGBE_VT_CTL_REPLEN;
3300 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3301
3302 vf_shift = VMDQ_P(0) % 32;
3303 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3304
3305 /* Enable only the PF's pool for Tx/Rx */
3306 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3307 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3308 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3309 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3310 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3311 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3312
3313 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3314 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3315
3316 /*
3317 * Set up VF register offsets for selected VT Mode,
3318 * i.e. 32 or 64 VFs for SR-IOV
3319 */
3320 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3321 case IXGBE_82599_VMDQ_8Q_MASK:
3322 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3323 break;
3324 case IXGBE_82599_VMDQ_4Q_MASK:
3325 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3326 break;
3327 default:
3328 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3329 break;
3330 }
3331
3332 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3333
3334
3335 /* Enable MAC Anti-Spoofing */
3336 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3337 adapter->num_vfs);
3338 /* For VFs that have spoof checking turned off */
3339 for (i = 0; i < adapter->num_vfs; i++) {
3340 if (!adapter->vfinfo[i].spoofchk_enabled)
3341 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3342 }
3343 }
3344
3345 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3346 {
3347 struct ixgbe_hw *hw = &adapter->hw;
3348 struct net_device *netdev = adapter->netdev;
3349 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3350 struct ixgbe_ring *rx_ring;
3351 int i;
3352 u32 mhadd, hlreg0;
3353
3354 #ifdef IXGBE_FCOE
3355 /* adjust max frame to be able to do baby jumbo for FCoE */
3356 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3357 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3358 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3359
3360 #endif /* IXGBE_FCOE */
3361
3362 /* adjust max frame to be at least the size of a standard frame */
3363 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3364 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3365
3366 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3367 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3368 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3369 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3370
3371 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3372 }
3373
3374 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3375 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3376 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3377 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3378
3379 /*
3380 * Setup the HW Rx Head and Tail Descriptor Pointers and
3381 * the Base and Length of the Rx Descriptor Ring
3382 */
3383 for (i = 0; i < adapter->num_rx_queues; i++) {
3384 rx_ring = adapter->rx_ring[i];
3385 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3386 set_ring_rsc_enabled(rx_ring);
3387 else
3388 clear_ring_rsc_enabled(rx_ring);
3389 }
3390 }
3391
3392 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3393 {
3394 struct ixgbe_hw *hw = &adapter->hw;
3395 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3396
3397 switch (hw->mac.type) {
3398 case ixgbe_mac_82598EB:
3399 /*
3400 * For VMDq support of different descriptor types or
3401 * buffer sizes through the use of multiple SRRCTL
3402 * registers, RDRXCTL.MVMEN must be set to 1
3403 *
3404 * also, the manual doesn't mention it clearly but DCA hints
3405 * will only use queue 0's tags unless this bit is set. Side
3406 * effects of setting this bit are only that SRRCTL must be
3407 * fully programmed [0..15]
3408 */
3409 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3410 break;
3411 case ixgbe_mac_82599EB:
3412 case ixgbe_mac_X540:
3413 /* Disable RSC for ACK packets */
3414 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3415 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3416 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3417 /* hardware requires some bits to be set by default */
3418 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3419 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3420 break;
3421 default:
3422 /* We should do nothing since we don't know this hardware */
3423 return;
3424 }
3425
3426 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3427 }
3428
3429 /**
3430 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3431 * @adapter: board private structure
3432 *
3433 * Configure the Rx unit of the MAC after a reset.
3434 **/
3435 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3436 {
3437 struct ixgbe_hw *hw = &adapter->hw;
3438 int i;
3439 u32 rxctrl;
3440
3441 /* disable receives while setting up the descriptors */
3442 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3443 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3444
3445 ixgbe_setup_psrtype(adapter);
3446 ixgbe_setup_rdrxctl(adapter);
3447
3448 /* Program registers for the distribution of queues */
3449 ixgbe_setup_mrqc(adapter);
3450
3451 /* set_rx_buffer_len must be called before ring initialization */
3452 ixgbe_set_rx_buffer_len(adapter);
3453
3454 /*
3455 * Setup the HW Rx Head and Tail Descriptor Pointers and
3456 * the Base and Length of the Rx Descriptor Ring
3457 */
3458 for (i = 0; i < adapter->num_rx_queues; i++)
3459 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3460
3461 /* disable drop enable for 82598 parts */
3462 if (hw->mac.type == ixgbe_mac_82598EB)
3463 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3464
3465 /* enable all receives */
3466 rxctrl |= IXGBE_RXCTRL_RXEN;
3467 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3468 }
3469
3470 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3471 __be16 proto, u16 vid)
3472 {
3473 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3474 struct ixgbe_hw *hw = &adapter->hw;
3475
3476 /* add VID to filter table */
3477 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3478 set_bit(vid, adapter->active_vlans);
3479
3480 return 0;
3481 }
3482
3483 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3484 __be16 proto, u16 vid)
3485 {
3486 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3487 struct ixgbe_hw *hw = &adapter->hw;
3488
3489 /* remove VID from filter table */
3490 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3491 clear_bit(vid, adapter->active_vlans);
3492
3493 return 0;
3494 }
3495
3496 /**
3497 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3498 * @adapter: driver data
3499 */
3500 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3501 {
3502 struct ixgbe_hw *hw = &adapter->hw;
3503 u32 vlnctrl;
3504
3505 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3506 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3507 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3508 }
3509
3510 /**
3511 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3512 * @adapter: driver data
3513 */
3514 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3515 {
3516 struct ixgbe_hw *hw = &adapter->hw;
3517 u32 vlnctrl;
3518
3519 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3520 vlnctrl |= IXGBE_VLNCTRL_VFE;
3521 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3522 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3523 }
3524
3525 /**
3526 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3527 * @adapter: driver data
3528 */
3529 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3530 {
3531 struct ixgbe_hw *hw = &adapter->hw;
3532 u32 vlnctrl;
3533 int i, j;
3534
3535 switch (hw->mac.type) {
3536 case ixgbe_mac_82598EB:
3537 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3538 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3539 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3540 break;
3541 case ixgbe_mac_82599EB:
3542 case ixgbe_mac_X540:
3543 for (i = 0; i < adapter->num_rx_queues; i++) {
3544 j = adapter->rx_ring[i]->reg_idx;
3545 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3546 vlnctrl &= ~IXGBE_RXDCTL_VME;
3547 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3548 }
3549 break;
3550 default:
3551 break;
3552 }
3553 }
3554
3555 /**
3556 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3557 * @adapter: driver data
3558 */
3559 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3560 {
3561 struct ixgbe_hw *hw = &adapter->hw;
3562 u32 vlnctrl;
3563 int i, j;
3564
3565 switch (hw->mac.type) {
3566 case ixgbe_mac_82598EB:
3567 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3568 vlnctrl |= IXGBE_VLNCTRL_VME;
3569 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3570 break;
3571 case ixgbe_mac_82599EB:
3572 case ixgbe_mac_X540:
3573 for (i = 0; i < adapter->num_rx_queues; i++) {
3574 j = adapter->rx_ring[i]->reg_idx;
3575 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3576 vlnctrl |= IXGBE_RXDCTL_VME;
3577 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3578 }
3579 break;
3580 default:
3581 break;
3582 }
3583 }
3584
3585 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3586 {
3587 u16 vid;
3588
3589 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3590
3591 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3592 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
3593 }
3594
3595 /**
3596 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3597 * @netdev: network interface device structure
3598 *
3599 * Writes unicast address list to the RAR table.
3600 * Returns: -ENOMEM on failure/insufficient address space
3601 * 0 on no addresses written
3602 * X on writing X addresses to the RAR table
3603 **/
3604 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3605 {
3606 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3607 struct ixgbe_hw *hw = &adapter->hw;
3608 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
3609 int count = 0;
3610
3611 /* In SR-IOV mode significantly less RAR entries are available */
3612 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3613 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3614
3615 /* return ENOMEM indicating insufficient memory for addresses */
3616 if (netdev_uc_count(netdev) > rar_entries)
3617 return -ENOMEM;
3618
3619 if (!netdev_uc_empty(netdev)) {
3620 struct netdev_hw_addr *ha;
3621 /* return error if we do not support writing to RAR table */
3622 if (!hw->mac.ops.set_rar)
3623 return -ENOMEM;
3624
3625 netdev_for_each_uc_addr(ha, netdev) {
3626 if (!rar_entries)
3627 break;
3628 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3629 VMDQ_P(0), IXGBE_RAH_AV);
3630 count++;
3631 }
3632 }
3633 /* write the addresses in reverse order to avoid write combining */
3634 for (; rar_entries > 0 ; rar_entries--)
3635 hw->mac.ops.clear_rar(hw, rar_entries);
3636
3637 return count;
3638 }
3639
3640 /**
3641 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3642 * @netdev: network interface device structure
3643 *
3644 * The set_rx_method entry point is called whenever the unicast/multicast
3645 * address list or the network interface flags are updated. This routine is
3646 * responsible for configuring the hardware for proper unicast, multicast and
3647 * promiscuous mode.
3648 **/
3649 void ixgbe_set_rx_mode(struct net_device *netdev)
3650 {
3651 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3652 struct ixgbe_hw *hw = &adapter->hw;
3653 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3654 int count;
3655
3656 /* Check for Promiscuous and All Multicast modes */
3657
3658 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3659
3660 /* set all bits that we expect to always be set */
3661 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3662 fctrl |= IXGBE_FCTRL_BAM;
3663 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3664 fctrl |= IXGBE_FCTRL_PMCF;
3665
3666 /* clear the bits we are changing the status of */
3667 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3668
3669 if (netdev->flags & IFF_PROMISC) {
3670 hw->addr_ctrl.user_set_promisc = true;
3671 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3672 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3673 /* don't hardware filter vlans in promisc mode */
3674 ixgbe_vlan_filter_disable(adapter);
3675 } else {
3676 if (netdev->flags & IFF_ALLMULTI) {
3677 fctrl |= IXGBE_FCTRL_MPE;
3678 vmolr |= IXGBE_VMOLR_MPE;
3679 } else {
3680 /*
3681 * Write addresses to the MTA, if the attempt fails
3682 * then we should just turn on promiscuous mode so
3683 * that we can at least receive multicast traffic
3684 */
3685 hw->mac.ops.update_mc_addr_list(hw, netdev);
3686 vmolr |= IXGBE_VMOLR_ROMPE;
3687 }
3688 ixgbe_vlan_filter_enable(adapter);
3689 hw->addr_ctrl.user_set_promisc = false;
3690 }
3691
3692 /*
3693 * Write addresses to available RAR registers, if there is not
3694 * sufficient space to store all the addresses then enable
3695 * unicast promiscuous mode
3696 */
3697 count = ixgbe_write_uc_addr_list(netdev);
3698 if (count < 0) {
3699 fctrl |= IXGBE_FCTRL_UPE;
3700 vmolr |= IXGBE_VMOLR_ROPE;
3701 }
3702
3703 if (adapter->num_vfs)
3704 ixgbe_restore_vf_multicasts(adapter);
3705
3706 if (hw->mac.type != ixgbe_mac_82598EB) {
3707 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3708 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3709 IXGBE_VMOLR_ROPE);
3710 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3711 }
3712
3713 /* This is useful for sniffing bad packets. */
3714 if (adapter->netdev->features & NETIF_F_RXALL) {
3715 /* UPE and MPE will be handled by normal PROMISC logic
3716 * in e1000e_set_rx_mode */
3717 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3718 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3719 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3720
3721 fctrl &= ~(IXGBE_FCTRL_DPF);
3722 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3723 }
3724
3725 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3726
3727 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3728 ixgbe_vlan_strip_enable(adapter);
3729 else
3730 ixgbe_vlan_strip_disable(adapter);
3731 }
3732
3733 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3734 {
3735 int q_idx;
3736
3737 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3738 napi_enable(&adapter->q_vector[q_idx]->napi);
3739 }
3740
3741 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3742 {
3743 int q_idx;
3744
3745 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3746 napi_disable(&adapter->q_vector[q_idx]->napi);
3747 }
3748
3749 #ifdef CONFIG_IXGBE_DCB
3750 /**
3751 * ixgbe_configure_dcb - Configure DCB hardware
3752 * @adapter: ixgbe adapter struct
3753 *
3754 * This is called by the driver on open to configure the DCB hardware.
3755 * This is also called by the gennetlink interface when reconfiguring
3756 * the DCB state.
3757 */
3758 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3759 {
3760 struct ixgbe_hw *hw = &adapter->hw;
3761 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3762
3763 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3764 if (hw->mac.type == ixgbe_mac_82598EB)
3765 netif_set_gso_max_size(adapter->netdev, 65536);
3766 return;
3767 }
3768
3769 if (hw->mac.type == ixgbe_mac_82598EB)
3770 netif_set_gso_max_size(adapter->netdev, 32768);
3771
3772 #ifdef IXGBE_FCOE
3773 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3774 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3775 #endif
3776
3777 /* reconfigure the hardware */
3778 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3779 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3780 DCB_TX_CONFIG);
3781 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3782 DCB_RX_CONFIG);
3783 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3784 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3785 ixgbe_dcb_hw_ets(&adapter->hw,
3786 adapter->ixgbe_ieee_ets,
3787 max_frame);
3788 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3789 adapter->ixgbe_ieee_pfc->pfc_en,
3790 adapter->ixgbe_ieee_ets->prio_tc);
3791 }
3792
3793 /* Enable RSS Hash per TC */
3794 if (hw->mac.type != ixgbe_mac_82598EB) {
3795 u32 msb = 0;
3796 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3797
3798 while (rss_i) {
3799 msb++;
3800 rss_i >>= 1;
3801 }
3802
3803 /* write msb to all 8 TCs in one write */
3804 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3805 }
3806 }
3807 #endif
3808
3809 /* Additional bittime to account for IXGBE framing */
3810 #define IXGBE_ETH_FRAMING 20
3811
3812 /**
3813 * ixgbe_hpbthresh - calculate high water mark for flow control
3814 *
3815 * @adapter: board private structure to calculate for
3816 * @pb: packet buffer to calculate
3817 */
3818 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3819 {
3820 struct ixgbe_hw *hw = &adapter->hw;
3821 struct net_device *dev = adapter->netdev;
3822 int link, tc, kb, marker;
3823 u32 dv_id, rx_pba;
3824
3825 /* Calculate max LAN frame size */
3826 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3827
3828 #ifdef IXGBE_FCOE
3829 /* FCoE traffic class uses FCOE jumbo frames */
3830 if ((dev->features & NETIF_F_FCOE_MTU) &&
3831 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3832 (pb == ixgbe_fcoe_get_tc(adapter)))
3833 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3834
3835 #endif
3836 /* Calculate delay value for device */
3837 switch (hw->mac.type) {
3838 case ixgbe_mac_X540:
3839 dv_id = IXGBE_DV_X540(link, tc);
3840 break;
3841 default:
3842 dv_id = IXGBE_DV(link, tc);
3843 break;
3844 }
3845
3846 /* Loopback switch introduces additional latency */
3847 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3848 dv_id += IXGBE_B2BT(tc);
3849
3850 /* Delay value is calculated in bit times convert to KB */
3851 kb = IXGBE_BT2KB(dv_id);
3852 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3853
3854 marker = rx_pba - kb;
3855
3856 /* It is possible that the packet buffer is not large enough
3857 * to provide required headroom. In this case throw an error
3858 * to user and a do the best we can.
3859 */
3860 if (marker < 0) {
3861 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3862 "headroom to support flow control."
3863 "Decrease MTU or number of traffic classes\n", pb);
3864 marker = tc + 1;
3865 }
3866
3867 return marker;
3868 }
3869
3870 /**
3871 * ixgbe_lpbthresh - calculate low water mark for for flow control
3872 *
3873 * @adapter: board private structure to calculate for
3874 * @pb: packet buffer to calculate
3875 */
3876 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3877 {
3878 struct ixgbe_hw *hw = &adapter->hw;
3879 struct net_device *dev = adapter->netdev;
3880 int tc;
3881 u32 dv_id;
3882
3883 /* Calculate max LAN frame size */
3884 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3885
3886 /* Calculate delay value for device */
3887 switch (hw->mac.type) {
3888 case ixgbe_mac_X540:
3889 dv_id = IXGBE_LOW_DV_X540(tc);
3890 break;
3891 default:
3892 dv_id = IXGBE_LOW_DV(tc);
3893 break;
3894 }
3895
3896 /* Delay value is calculated in bit times convert to KB */
3897 return IXGBE_BT2KB(dv_id);
3898 }
3899
3900 /*
3901 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3902 */
3903 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3904 {
3905 struct ixgbe_hw *hw = &adapter->hw;
3906 int num_tc = netdev_get_num_tc(adapter->netdev);
3907 int i;
3908
3909 if (!num_tc)
3910 num_tc = 1;
3911
3912 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3913
3914 for (i = 0; i < num_tc; i++) {
3915 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3916
3917 /* Low water marks must not be larger than high water marks */
3918 if (hw->fc.low_water > hw->fc.high_water[i])
3919 hw->fc.low_water = 0;
3920 }
3921 }
3922
3923 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3924 {
3925 struct ixgbe_hw *hw = &adapter->hw;
3926 int hdrm;
3927 u8 tc = netdev_get_num_tc(adapter->netdev);
3928
3929 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3930 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3931 hdrm = 32 << adapter->fdir_pballoc;
3932 else
3933 hdrm = 0;
3934
3935 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3936 ixgbe_pbthresh_setup(adapter);
3937 }
3938
3939 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3940 {
3941 struct ixgbe_hw *hw = &adapter->hw;
3942 struct hlist_node *node2;
3943 struct ixgbe_fdir_filter *filter;
3944
3945 spin_lock(&adapter->fdir_perfect_lock);
3946
3947 if (!hlist_empty(&adapter->fdir_filter_list))
3948 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3949
3950 hlist_for_each_entry_safe(filter, node2,
3951 &adapter->fdir_filter_list, fdir_node) {
3952 ixgbe_fdir_write_perfect_filter_82599(hw,
3953 &filter->filter,
3954 filter->sw_idx,
3955 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3956 IXGBE_FDIR_DROP_QUEUE :
3957 adapter->rx_ring[filter->action]->reg_idx);
3958 }
3959
3960 spin_unlock(&adapter->fdir_perfect_lock);
3961 }
3962
3963 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3964 {
3965 struct ixgbe_hw *hw = &adapter->hw;
3966
3967 ixgbe_configure_pb(adapter);
3968 #ifdef CONFIG_IXGBE_DCB
3969 ixgbe_configure_dcb(adapter);
3970 #endif
3971 /*
3972 * We must restore virtualization before VLANs or else
3973 * the VLVF registers will not be populated
3974 */
3975 ixgbe_configure_virtualization(adapter);
3976
3977 ixgbe_set_rx_mode(adapter->netdev);
3978 ixgbe_restore_vlan(adapter);
3979
3980 switch (hw->mac.type) {
3981 case ixgbe_mac_82599EB:
3982 case ixgbe_mac_X540:
3983 hw->mac.ops.disable_rx_buff(hw);
3984 break;
3985 default:
3986 break;
3987 }
3988
3989 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3990 ixgbe_init_fdir_signature_82599(&adapter->hw,
3991 adapter->fdir_pballoc);
3992 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3993 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3994 adapter->fdir_pballoc);
3995 ixgbe_fdir_filter_restore(adapter);
3996 }
3997
3998 switch (hw->mac.type) {
3999 case ixgbe_mac_82599EB:
4000 case ixgbe_mac_X540:
4001 hw->mac.ops.enable_rx_buff(hw);
4002 break;
4003 default:
4004 break;
4005 }
4006
4007 #ifdef IXGBE_FCOE
4008 /* configure FCoE L2 filters, redirection table, and Rx control */
4009 ixgbe_configure_fcoe(adapter);
4010
4011 #endif /* IXGBE_FCOE */
4012 ixgbe_configure_tx(adapter);
4013 ixgbe_configure_rx(adapter);
4014 }
4015
4016 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4017 {
4018 switch (hw->phy.type) {
4019 case ixgbe_phy_sfp_avago:
4020 case ixgbe_phy_sfp_ftl:
4021 case ixgbe_phy_sfp_intel:
4022 case ixgbe_phy_sfp_unknown:
4023 case ixgbe_phy_sfp_passive_tyco:
4024 case ixgbe_phy_sfp_passive_unknown:
4025 case ixgbe_phy_sfp_active_unknown:
4026 case ixgbe_phy_sfp_ftl_active:
4027 return true;
4028 case ixgbe_phy_nl:
4029 if (hw->mac.type == ixgbe_mac_82598EB)
4030 return true;
4031 default:
4032 return false;
4033 }
4034 }
4035
4036 /**
4037 * ixgbe_sfp_link_config - set up SFP+ link
4038 * @adapter: pointer to private adapter struct
4039 **/
4040 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4041 {
4042 /*
4043 * We are assuming the worst case scenario here, and that
4044 * is that an SFP was inserted/removed after the reset
4045 * but before SFP detection was enabled. As such the best
4046 * solution is to just start searching as soon as we start
4047 */
4048 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4049 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4050
4051 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4052 }
4053
4054 /**
4055 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4056 * @hw: pointer to private hardware struct
4057 *
4058 * Returns 0 on success, negative on failure
4059 **/
4060 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4061 {
4062 u32 speed;
4063 bool autoneg, link_up = false;
4064 u32 ret = IXGBE_ERR_LINK_SETUP;
4065
4066 if (hw->mac.ops.check_link)
4067 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4068
4069 if (ret)
4070 goto link_cfg_out;
4071
4072 speed = hw->phy.autoneg_advertised;
4073 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4074 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4075 &autoneg);
4076 if (ret)
4077 goto link_cfg_out;
4078
4079 if (hw->mac.ops.setup_link)
4080 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4081 link_cfg_out:
4082 return ret;
4083 }
4084
4085 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4086 {
4087 struct ixgbe_hw *hw = &adapter->hw;
4088 u32 gpie = 0;
4089
4090 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4091 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4092 IXGBE_GPIE_OCD;
4093 gpie |= IXGBE_GPIE_EIAME;
4094 /*
4095 * use EIAM to auto-mask when MSI-X interrupt is asserted
4096 * this saves a register write for every interrupt
4097 */
4098 switch (hw->mac.type) {
4099 case ixgbe_mac_82598EB:
4100 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4101 break;
4102 case ixgbe_mac_82599EB:
4103 case ixgbe_mac_X540:
4104 default:
4105 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4106 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4107 break;
4108 }
4109 } else {
4110 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4111 * specifically only auto mask tx and rx interrupts */
4112 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4113 }
4114
4115 /* XXX: to interrupt immediately for EICS writes, enable this */
4116 /* gpie |= IXGBE_GPIE_EIMEN; */
4117
4118 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4119 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4120
4121 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4122 case IXGBE_82599_VMDQ_8Q_MASK:
4123 gpie |= IXGBE_GPIE_VTMODE_16;
4124 break;
4125 case IXGBE_82599_VMDQ_4Q_MASK:
4126 gpie |= IXGBE_GPIE_VTMODE_32;
4127 break;
4128 default:
4129 gpie |= IXGBE_GPIE_VTMODE_64;
4130 break;
4131 }
4132 }
4133
4134 /* Enable Thermal over heat sensor interrupt */
4135 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4136 switch (adapter->hw.mac.type) {
4137 case ixgbe_mac_82599EB:
4138 gpie |= IXGBE_SDP0_GPIEN;
4139 break;
4140 case ixgbe_mac_X540:
4141 gpie |= IXGBE_EIMS_TS;
4142 break;
4143 default:
4144 break;
4145 }
4146 }
4147
4148 /* Enable fan failure interrupt */
4149 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4150 gpie |= IXGBE_SDP1_GPIEN;
4151
4152 if (hw->mac.type == ixgbe_mac_82599EB) {
4153 gpie |= IXGBE_SDP1_GPIEN;
4154 gpie |= IXGBE_SDP2_GPIEN;
4155 }
4156
4157 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4158 }
4159
4160 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4161 {
4162 struct ixgbe_hw *hw = &adapter->hw;
4163 int err;
4164 u32 ctrl_ext;
4165
4166 ixgbe_get_hw_control(adapter);
4167 ixgbe_setup_gpie(adapter);
4168
4169 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4170 ixgbe_configure_msix(adapter);
4171 else
4172 ixgbe_configure_msi_and_legacy(adapter);
4173
4174 /* enable the optics for 82599 SFP+ fiber */
4175 if (hw->mac.ops.enable_tx_laser)
4176 hw->mac.ops.enable_tx_laser(hw);
4177
4178 clear_bit(__IXGBE_DOWN, &adapter->state);
4179 ixgbe_napi_enable_all(adapter);
4180
4181 if (ixgbe_is_sfp(hw)) {
4182 ixgbe_sfp_link_config(adapter);
4183 } else {
4184 err = ixgbe_non_sfp_link_config(hw);
4185 if (err)
4186 e_err(probe, "link_config FAILED %d\n", err);
4187 }
4188
4189 /* clear any pending interrupts, may auto mask */
4190 IXGBE_READ_REG(hw, IXGBE_EICR);
4191 ixgbe_irq_enable(adapter, true, true);
4192
4193 /*
4194 * If this adapter has a fan, check to see if we had a failure
4195 * before we enabled the interrupt.
4196 */
4197 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4198 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4199 if (esdp & IXGBE_ESDP_SDP1)
4200 e_crit(drv, "Fan has stopped, replace the adapter\n");
4201 }
4202
4203 /* enable transmits */
4204 netif_tx_start_all_queues(adapter->netdev);
4205
4206 /* bring the link up in the watchdog, this could race with our first
4207 * link up interrupt but shouldn't be a problem */
4208 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4209 adapter->link_check_timeout = jiffies;
4210 mod_timer(&adapter->service_timer, jiffies);
4211
4212 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4213 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4214 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4215 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4216 }
4217
4218 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4219 {
4220 WARN_ON(in_interrupt());
4221 /* put off any impending NetWatchDogTimeout */
4222 adapter->netdev->trans_start = jiffies;
4223
4224 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4225 usleep_range(1000, 2000);
4226 ixgbe_down(adapter);
4227 /*
4228 * If SR-IOV enabled then wait a bit before bringing the adapter
4229 * back up to give the VFs time to respond to the reset. The
4230 * two second wait is based upon the watchdog timer cycle in
4231 * the VF driver.
4232 */
4233 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4234 msleep(2000);
4235 ixgbe_up(adapter);
4236 clear_bit(__IXGBE_RESETTING, &adapter->state);
4237 }
4238
4239 void ixgbe_up(struct ixgbe_adapter *adapter)
4240 {
4241 /* hardware has been reset, we need to reload some things */
4242 ixgbe_configure(adapter);
4243
4244 ixgbe_up_complete(adapter);
4245 }
4246
4247 void ixgbe_reset(struct ixgbe_adapter *adapter)
4248 {
4249 struct ixgbe_hw *hw = &adapter->hw;
4250 int err;
4251
4252 /* lock SFP init bit to prevent race conditions with the watchdog */
4253 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4254 usleep_range(1000, 2000);
4255
4256 /* clear all SFP and link config related flags while holding SFP_INIT */
4257 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4258 IXGBE_FLAG2_SFP_NEEDS_RESET);
4259 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4260
4261 err = hw->mac.ops.init_hw(hw);
4262 switch (err) {
4263 case 0:
4264 case IXGBE_ERR_SFP_NOT_PRESENT:
4265 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4266 break;
4267 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4268 e_dev_err("master disable timed out\n");
4269 break;
4270 case IXGBE_ERR_EEPROM_VERSION:
4271 /* We are running on a pre-production device, log a warning */
4272 e_dev_warn("This device is a pre-production adapter/LOM. "
4273 "Please be aware there may be issues associated with "
4274 "your hardware. If you are experiencing problems "
4275 "please contact your Intel or hardware "
4276 "representative who provided you with this "
4277 "hardware.\n");
4278 break;
4279 default:
4280 e_dev_err("Hardware Error: %d\n", err);
4281 }
4282
4283 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4284
4285 /* reprogram the RAR[0] in case user changed it. */
4286 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
4287
4288 /* update SAN MAC vmdq pool selection */
4289 if (hw->mac.san_mac_rar_index)
4290 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4291
4292 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4293 ixgbe_ptp_reset(adapter);
4294 }
4295
4296 /**
4297 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4298 * @rx_ring: ring to free buffers from
4299 **/
4300 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4301 {
4302 struct device *dev = rx_ring->dev;
4303 unsigned long size;
4304 u16 i;
4305
4306 /* ring already cleared, nothing to do */
4307 if (!rx_ring->rx_buffer_info)
4308 return;
4309
4310 /* Free all the Rx ring sk_buffs */
4311 for (i = 0; i < rx_ring->count; i++) {
4312 struct ixgbe_rx_buffer *rx_buffer;
4313
4314 rx_buffer = &rx_ring->rx_buffer_info[i];
4315 if (rx_buffer->skb) {
4316 struct sk_buff *skb = rx_buffer->skb;
4317 if (IXGBE_CB(skb)->page_released) {
4318 dma_unmap_page(dev,
4319 IXGBE_CB(skb)->dma,
4320 ixgbe_rx_bufsz(rx_ring),
4321 DMA_FROM_DEVICE);
4322 IXGBE_CB(skb)->page_released = false;
4323 }
4324 dev_kfree_skb(skb);
4325 }
4326 rx_buffer->skb = NULL;
4327 if (rx_buffer->dma)
4328 dma_unmap_page(dev, rx_buffer->dma,
4329 ixgbe_rx_pg_size(rx_ring),
4330 DMA_FROM_DEVICE);
4331 rx_buffer->dma = 0;
4332 if (rx_buffer->page)
4333 __free_pages(rx_buffer->page,
4334 ixgbe_rx_pg_order(rx_ring));
4335 rx_buffer->page = NULL;
4336 }
4337
4338 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4339 memset(rx_ring->rx_buffer_info, 0, size);
4340
4341 /* Zero out the descriptor ring */
4342 memset(rx_ring->desc, 0, rx_ring->size);
4343
4344 rx_ring->next_to_alloc = 0;
4345 rx_ring->next_to_clean = 0;
4346 rx_ring->next_to_use = 0;
4347 }
4348
4349 /**
4350 * ixgbe_clean_tx_ring - Free Tx Buffers
4351 * @tx_ring: ring to be cleaned
4352 **/
4353 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4354 {
4355 struct ixgbe_tx_buffer *tx_buffer_info;
4356 unsigned long size;
4357 u16 i;
4358
4359 /* ring already cleared, nothing to do */
4360 if (!tx_ring->tx_buffer_info)
4361 return;
4362
4363 /* Free all the Tx ring sk_buffs */
4364 for (i = 0; i < tx_ring->count; i++) {
4365 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4366 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4367 }
4368
4369 netdev_tx_reset_queue(txring_txq(tx_ring));
4370
4371 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4372 memset(tx_ring->tx_buffer_info, 0, size);
4373
4374 /* Zero out the descriptor ring */
4375 memset(tx_ring->desc, 0, tx_ring->size);
4376
4377 tx_ring->next_to_use = 0;
4378 tx_ring->next_to_clean = 0;
4379 }
4380
4381 /**
4382 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4383 * @adapter: board private structure
4384 **/
4385 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4386 {
4387 int i;
4388
4389 for (i = 0; i < adapter->num_rx_queues; i++)
4390 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4391 }
4392
4393 /**
4394 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4395 * @adapter: board private structure
4396 **/
4397 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4398 {
4399 int i;
4400
4401 for (i = 0; i < adapter->num_tx_queues; i++)
4402 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4403 }
4404
4405 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4406 {
4407 struct hlist_node *node2;
4408 struct ixgbe_fdir_filter *filter;
4409
4410 spin_lock(&adapter->fdir_perfect_lock);
4411
4412 hlist_for_each_entry_safe(filter, node2,
4413 &adapter->fdir_filter_list, fdir_node) {
4414 hlist_del(&filter->fdir_node);
4415 kfree(filter);
4416 }
4417 adapter->fdir_filter_count = 0;
4418
4419 spin_unlock(&adapter->fdir_perfect_lock);
4420 }
4421
4422 void ixgbe_down(struct ixgbe_adapter *adapter)
4423 {
4424 struct net_device *netdev = adapter->netdev;
4425 struct ixgbe_hw *hw = &adapter->hw;
4426 u32 rxctrl;
4427 int i;
4428
4429 /* signal that we are down to the interrupt handler */
4430 set_bit(__IXGBE_DOWN, &adapter->state);
4431
4432 /* disable receives */
4433 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4434 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4435
4436 /* disable all enabled rx queues */
4437 for (i = 0; i < adapter->num_rx_queues; i++)
4438 /* this call also flushes the previous write */
4439 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4440
4441 usleep_range(10000, 20000);
4442
4443 netif_tx_stop_all_queues(netdev);
4444
4445 /* call carrier off first to avoid false dev_watchdog timeouts */
4446 netif_carrier_off(netdev);
4447 netif_tx_disable(netdev);
4448
4449 ixgbe_irq_disable(adapter);
4450
4451 ixgbe_napi_disable_all(adapter);
4452
4453 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4454 IXGBE_FLAG2_RESET_REQUESTED);
4455 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4456
4457 del_timer_sync(&adapter->service_timer);
4458
4459 if (adapter->num_vfs) {
4460 /* Clear EITR Select mapping */
4461 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4462
4463 /* Mark all the VFs as inactive */
4464 for (i = 0 ; i < adapter->num_vfs; i++)
4465 adapter->vfinfo[i].clear_to_send = false;
4466
4467 /* ping all the active vfs to let them know we are going down */
4468 ixgbe_ping_all_vfs(adapter);
4469
4470 /* Disable all VFTE/VFRE TX/RX */
4471 ixgbe_disable_tx_rx(adapter);
4472 }
4473
4474 /* disable transmits in the hardware now that interrupts are off */
4475 for (i = 0; i < adapter->num_tx_queues; i++) {
4476 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4477 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4478 }
4479
4480 /* Disable the Tx DMA engine on 82599 and X540 */
4481 switch (hw->mac.type) {
4482 case ixgbe_mac_82599EB:
4483 case ixgbe_mac_X540:
4484 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4485 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4486 ~IXGBE_DMATXCTL_TE));
4487 break;
4488 default:
4489 break;
4490 }
4491
4492 if (!pci_channel_offline(adapter->pdev))
4493 ixgbe_reset(adapter);
4494
4495 /* power down the optics for 82599 SFP+ fiber */
4496 if (hw->mac.ops.disable_tx_laser)
4497 hw->mac.ops.disable_tx_laser(hw);
4498
4499 ixgbe_clean_all_tx_rings(adapter);
4500 ixgbe_clean_all_rx_rings(adapter);
4501
4502 #ifdef CONFIG_IXGBE_DCA
4503 /* since we reset the hardware DCA settings were cleared */
4504 ixgbe_setup_dca(adapter);
4505 #endif
4506 }
4507
4508 /**
4509 * ixgbe_tx_timeout - Respond to a Tx Hang
4510 * @netdev: network interface device structure
4511 **/
4512 static void ixgbe_tx_timeout(struct net_device *netdev)
4513 {
4514 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4515
4516 /* Do the reset outside of interrupt context */
4517 ixgbe_tx_timeout_reset(adapter);
4518 }
4519
4520 /**
4521 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4522 * @adapter: board private structure to initialize
4523 *
4524 * ixgbe_sw_init initializes the Adapter private data structure.
4525 * Fields are initialized based on PCI device information and
4526 * OS network device settings (MTU size).
4527 **/
4528 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
4529 {
4530 struct ixgbe_hw *hw = &adapter->hw;
4531 struct pci_dev *pdev = adapter->pdev;
4532 unsigned int rss, fdir;
4533 u32 fwsm;
4534 #ifdef CONFIG_IXGBE_DCB
4535 int j;
4536 struct tc_configuration *tc;
4537 #endif
4538
4539 /* PCI config space info */
4540
4541 hw->vendor_id = pdev->vendor;
4542 hw->device_id = pdev->device;
4543 hw->revision_id = pdev->revision;
4544 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4545 hw->subsystem_device_id = pdev->subsystem_device;
4546
4547 /* Set common capability flags and settings */
4548 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4549 adapter->ring_feature[RING_F_RSS].limit = rss;
4550 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4551 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4552 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4553 adapter->atr_sample_rate = 20;
4554 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
4555 adapter->ring_feature[RING_F_FDIR].limit = fdir;
4556 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4557 #ifdef CONFIG_IXGBE_DCA
4558 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
4559 #endif
4560 #ifdef IXGBE_FCOE
4561 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4562 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4563 #ifdef CONFIG_IXGBE_DCB
4564 /* Default traffic class to use for FCoE */
4565 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4566 #endif /* CONFIG_IXGBE_DCB */
4567 #endif /* IXGBE_FCOE */
4568
4569 /* Set MAC specific capability flags and exceptions */
4570 switch (hw->mac.type) {
4571 case ixgbe_mac_82598EB:
4572 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
4573 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
4574
4575 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4576 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4577
4578 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
4579 adapter->ring_feature[RING_F_FDIR].limit = 0;
4580 adapter->atr_sample_rate = 0;
4581 adapter->fdir_pballoc = 0;
4582 #ifdef IXGBE_FCOE
4583 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
4584 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4585 #ifdef CONFIG_IXGBE_DCB
4586 adapter->fcoe.up = 0;
4587 #endif /* IXGBE_DCB */
4588 #endif /* IXGBE_FCOE */
4589 break;
4590 case ixgbe_mac_82599EB:
4591 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4592 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4593 break;
4594 case ixgbe_mac_X540:
4595 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4596 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4597 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4598 break;
4599 default:
4600 break;
4601 }
4602
4603 #ifdef IXGBE_FCOE
4604 /* FCoE support exists, always init the FCoE lock */
4605 spin_lock_init(&adapter->fcoe.lock);
4606
4607 #endif
4608 /* n-tuple support exists, always init our spinlock */
4609 spin_lock_init(&adapter->fdir_perfect_lock);
4610
4611 #ifdef CONFIG_IXGBE_DCB
4612 switch (hw->mac.type) {
4613 case ixgbe_mac_X540:
4614 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4615 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4616 break;
4617 default:
4618 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4619 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4620 break;
4621 }
4622
4623 /* Configure DCB traffic classes */
4624 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4625 tc = &adapter->dcb_cfg.tc_config[j];
4626 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4627 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4628 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4629 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4630 tc->dcb_pfc = pfc_disabled;
4631 }
4632
4633 /* Initialize default user to priority mapping, UPx->TC0 */
4634 tc = &adapter->dcb_cfg.tc_config[0];
4635 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4636 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4637
4638 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4639 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4640 adapter->dcb_cfg.pfc_mode_enable = false;
4641 adapter->dcb_set_bitmap = 0x00;
4642 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4643 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4644 sizeof(adapter->temp_dcb_cfg));
4645
4646 #endif
4647
4648 /* default flow control settings */
4649 hw->fc.requested_mode = ixgbe_fc_full;
4650 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4651 ixgbe_pbthresh_setup(adapter);
4652 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4653 hw->fc.send_xon = true;
4654 hw->fc.disable_fc_autoneg =
4655 (ixgbe_device_supports_autoneg_fc(hw) == 0) ? false : true;
4656
4657 #ifdef CONFIG_PCI_IOV
4658 /* assign number of SR-IOV VFs */
4659 if (hw->mac.type != ixgbe_mac_82598EB)
4660 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4661
4662 #endif
4663 /* enable itr by default in dynamic mode */
4664 adapter->rx_itr_setting = 1;
4665 adapter->tx_itr_setting = 1;
4666
4667 /* set default ring sizes */
4668 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4669 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4670
4671 /* set default work limits */
4672 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4673
4674 /* initialize eeprom parameters */
4675 if (ixgbe_init_eeprom_params_generic(hw)) {
4676 e_dev_err("EEPROM initialization failed\n");
4677 return -EIO;
4678 }
4679
4680 set_bit(__IXGBE_DOWN, &adapter->state);
4681
4682 return 0;
4683 }
4684
4685 /**
4686 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4687 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4688 *
4689 * Return 0 on success, negative on failure
4690 **/
4691 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4692 {
4693 struct device *dev = tx_ring->dev;
4694 int orig_node = dev_to_node(dev);
4695 int numa_node = -1;
4696 int size;
4697
4698 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4699
4700 if (tx_ring->q_vector)
4701 numa_node = tx_ring->q_vector->numa_node;
4702
4703 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4704 if (!tx_ring->tx_buffer_info)
4705 tx_ring->tx_buffer_info = vzalloc(size);
4706 if (!tx_ring->tx_buffer_info)
4707 goto err;
4708
4709 /* round up to nearest 4K */
4710 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4711 tx_ring->size = ALIGN(tx_ring->size, 4096);
4712
4713 set_dev_node(dev, numa_node);
4714 tx_ring->desc = dma_alloc_coherent(dev,
4715 tx_ring->size,
4716 &tx_ring->dma,
4717 GFP_KERNEL);
4718 set_dev_node(dev, orig_node);
4719 if (!tx_ring->desc)
4720 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4721 &tx_ring->dma, GFP_KERNEL);
4722 if (!tx_ring->desc)
4723 goto err;
4724
4725 tx_ring->next_to_use = 0;
4726 tx_ring->next_to_clean = 0;
4727 return 0;
4728
4729 err:
4730 vfree(tx_ring->tx_buffer_info);
4731 tx_ring->tx_buffer_info = NULL;
4732 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4733 return -ENOMEM;
4734 }
4735
4736 /**
4737 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4738 * @adapter: board private structure
4739 *
4740 * If this function returns with an error, then it's possible one or
4741 * more of the rings is populated (while the rest are not). It is the
4742 * callers duty to clean those orphaned rings.
4743 *
4744 * Return 0 on success, negative on failure
4745 **/
4746 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4747 {
4748 int i, err = 0;
4749
4750 for (i = 0; i < adapter->num_tx_queues; i++) {
4751 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4752 if (!err)
4753 continue;
4754
4755 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4756 goto err_setup_tx;
4757 }
4758
4759 return 0;
4760 err_setup_tx:
4761 /* rewind the index freeing the rings as we go */
4762 while (i--)
4763 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4764 return err;
4765 }
4766
4767 /**
4768 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4769 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4770 *
4771 * Returns 0 on success, negative on failure
4772 **/
4773 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4774 {
4775 struct device *dev = rx_ring->dev;
4776 int orig_node = dev_to_node(dev);
4777 int numa_node = -1;
4778 int size;
4779
4780 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4781
4782 if (rx_ring->q_vector)
4783 numa_node = rx_ring->q_vector->numa_node;
4784
4785 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4786 if (!rx_ring->rx_buffer_info)
4787 rx_ring->rx_buffer_info = vzalloc(size);
4788 if (!rx_ring->rx_buffer_info)
4789 goto err;
4790
4791 /* Round up to nearest 4K */
4792 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4793 rx_ring->size = ALIGN(rx_ring->size, 4096);
4794
4795 set_dev_node(dev, numa_node);
4796 rx_ring->desc = dma_alloc_coherent(dev,
4797 rx_ring->size,
4798 &rx_ring->dma,
4799 GFP_KERNEL);
4800 set_dev_node(dev, orig_node);
4801 if (!rx_ring->desc)
4802 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4803 &rx_ring->dma, GFP_KERNEL);
4804 if (!rx_ring->desc)
4805 goto err;
4806
4807 rx_ring->next_to_clean = 0;
4808 rx_ring->next_to_use = 0;
4809
4810 return 0;
4811 err:
4812 vfree(rx_ring->rx_buffer_info);
4813 rx_ring->rx_buffer_info = NULL;
4814 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4815 return -ENOMEM;
4816 }
4817
4818 /**
4819 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4820 * @adapter: board private structure
4821 *
4822 * If this function returns with an error, then it's possible one or
4823 * more of the rings is populated (while the rest are not). It is the
4824 * callers duty to clean those orphaned rings.
4825 *
4826 * Return 0 on success, negative on failure
4827 **/
4828 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4829 {
4830 int i, err = 0;
4831
4832 for (i = 0; i < adapter->num_rx_queues; i++) {
4833 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4834 if (!err)
4835 continue;
4836
4837 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4838 goto err_setup_rx;
4839 }
4840
4841 #ifdef IXGBE_FCOE
4842 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4843 if (!err)
4844 #endif
4845 return 0;
4846 err_setup_rx:
4847 /* rewind the index freeing the rings as we go */
4848 while (i--)
4849 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4850 return err;
4851 }
4852
4853 /**
4854 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4855 * @tx_ring: Tx descriptor ring for a specific queue
4856 *
4857 * Free all transmit software resources
4858 **/
4859 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4860 {
4861 ixgbe_clean_tx_ring(tx_ring);
4862
4863 vfree(tx_ring->tx_buffer_info);
4864 tx_ring->tx_buffer_info = NULL;
4865
4866 /* if not set, then don't free */
4867 if (!tx_ring->desc)
4868 return;
4869
4870 dma_free_coherent(tx_ring->dev, tx_ring->size,
4871 tx_ring->desc, tx_ring->dma);
4872
4873 tx_ring->desc = NULL;
4874 }
4875
4876 /**
4877 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4878 * @adapter: board private structure
4879 *
4880 * Free all transmit software resources
4881 **/
4882 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4883 {
4884 int i;
4885
4886 for (i = 0; i < adapter->num_tx_queues; i++)
4887 if (adapter->tx_ring[i]->desc)
4888 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4889 }
4890
4891 /**
4892 * ixgbe_free_rx_resources - Free Rx Resources
4893 * @rx_ring: ring to clean the resources from
4894 *
4895 * Free all receive software resources
4896 **/
4897 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4898 {
4899 ixgbe_clean_rx_ring(rx_ring);
4900
4901 vfree(rx_ring->rx_buffer_info);
4902 rx_ring->rx_buffer_info = NULL;
4903
4904 /* if not set, then don't free */
4905 if (!rx_ring->desc)
4906 return;
4907
4908 dma_free_coherent(rx_ring->dev, rx_ring->size,
4909 rx_ring->desc, rx_ring->dma);
4910
4911 rx_ring->desc = NULL;
4912 }
4913
4914 /**
4915 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4916 * @adapter: board private structure
4917 *
4918 * Free all receive software resources
4919 **/
4920 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4921 {
4922 int i;
4923
4924 #ifdef IXGBE_FCOE
4925 ixgbe_free_fcoe_ddp_resources(adapter);
4926
4927 #endif
4928 for (i = 0; i < adapter->num_rx_queues; i++)
4929 if (adapter->rx_ring[i]->desc)
4930 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4931 }
4932
4933 /**
4934 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4935 * @netdev: network interface device structure
4936 * @new_mtu: new value for maximum frame size
4937 *
4938 * Returns 0 on success, negative on failure
4939 **/
4940 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4941 {
4942 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4943 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4944
4945 /* MTU < 68 is an error and causes problems on some kernels */
4946 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4947 return -EINVAL;
4948
4949 /*
4950 * For 82599EB we cannot allow legacy VFs to enable their receive
4951 * paths when MTU greater than 1500 is configured. So display a
4952 * warning that legacy VFs will be disabled.
4953 */
4954 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4955 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4956 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
4957 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
4958
4959 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4960
4961 /* must set new MTU before calling down or up */
4962 netdev->mtu = new_mtu;
4963
4964 if (netif_running(netdev))
4965 ixgbe_reinit_locked(adapter);
4966
4967 return 0;
4968 }
4969
4970 /**
4971 * ixgbe_open - Called when a network interface is made active
4972 * @netdev: network interface device structure
4973 *
4974 * Returns 0 on success, negative value on failure
4975 *
4976 * The open entry point is called when a network interface is made
4977 * active by the system (IFF_UP). At this point all resources needed
4978 * for transmit and receive operations are allocated, the interrupt
4979 * handler is registered with the OS, the watchdog timer is started,
4980 * and the stack is notified that the interface is ready.
4981 **/
4982 static int ixgbe_open(struct net_device *netdev)
4983 {
4984 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4985 int err;
4986
4987 /* disallow open during test */
4988 if (test_bit(__IXGBE_TESTING, &adapter->state))
4989 return -EBUSY;
4990
4991 netif_carrier_off(netdev);
4992
4993 /* allocate transmit descriptors */
4994 err = ixgbe_setup_all_tx_resources(adapter);
4995 if (err)
4996 goto err_setup_tx;
4997
4998 /* allocate receive descriptors */
4999 err = ixgbe_setup_all_rx_resources(adapter);
5000 if (err)
5001 goto err_setup_rx;
5002
5003 ixgbe_configure(adapter);
5004
5005 err = ixgbe_request_irq(adapter);
5006 if (err)
5007 goto err_req_irq;
5008
5009 /* Notify the stack of the actual queue counts. */
5010 err = netif_set_real_num_tx_queues(netdev,
5011 adapter->num_rx_pools > 1 ? 1 :
5012 adapter->num_tx_queues);
5013 if (err)
5014 goto err_set_queues;
5015
5016
5017 err = netif_set_real_num_rx_queues(netdev,
5018 adapter->num_rx_pools > 1 ? 1 :
5019 adapter->num_rx_queues);
5020 if (err)
5021 goto err_set_queues;
5022
5023 ixgbe_ptp_init(adapter);
5024
5025 ixgbe_up_complete(adapter);
5026
5027 return 0;
5028
5029 err_set_queues:
5030 ixgbe_free_irq(adapter);
5031 err_req_irq:
5032 ixgbe_free_all_rx_resources(adapter);
5033 err_setup_rx:
5034 ixgbe_free_all_tx_resources(adapter);
5035 err_setup_tx:
5036 ixgbe_reset(adapter);
5037
5038 return err;
5039 }
5040
5041 /**
5042 * ixgbe_close - Disables a network interface
5043 * @netdev: network interface device structure
5044 *
5045 * Returns 0, this is not allowed to fail
5046 *
5047 * The close entry point is called when an interface is de-activated
5048 * by the OS. The hardware is still under the drivers control, but
5049 * needs to be disabled. A global MAC reset is issued to stop the
5050 * hardware, and all transmit and receive resources are freed.
5051 **/
5052 static int ixgbe_close(struct net_device *netdev)
5053 {
5054 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5055
5056 ixgbe_ptp_stop(adapter);
5057
5058 ixgbe_down(adapter);
5059 ixgbe_free_irq(adapter);
5060
5061 ixgbe_fdir_filter_exit(adapter);
5062
5063 ixgbe_free_all_tx_resources(adapter);
5064 ixgbe_free_all_rx_resources(adapter);
5065
5066 ixgbe_release_hw_control(adapter);
5067
5068 return 0;
5069 }
5070
5071 #ifdef CONFIG_PM
5072 static int ixgbe_resume(struct pci_dev *pdev)
5073 {
5074 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5075 struct net_device *netdev = adapter->netdev;
5076 u32 err;
5077
5078 pci_set_power_state(pdev, PCI_D0);
5079 pci_restore_state(pdev);
5080 /*
5081 * pci_restore_state clears dev->state_saved so call
5082 * pci_save_state to restore it.
5083 */
5084 pci_save_state(pdev);
5085
5086 err = pci_enable_device_mem(pdev);
5087 if (err) {
5088 e_dev_err("Cannot enable PCI device from suspend\n");
5089 return err;
5090 }
5091 pci_set_master(pdev);
5092
5093 pci_wake_from_d3(pdev, false);
5094
5095 ixgbe_reset(adapter);
5096
5097 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5098
5099 rtnl_lock();
5100 err = ixgbe_init_interrupt_scheme(adapter);
5101 if (!err && netif_running(netdev))
5102 err = ixgbe_open(netdev);
5103
5104 rtnl_unlock();
5105
5106 if (err)
5107 return err;
5108
5109 netif_device_attach(netdev);
5110
5111 return 0;
5112 }
5113 #endif /* CONFIG_PM */
5114
5115 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5116 {
5117 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5118 struct net_device *netdev = adapter->netdev;
5119 struct ixgbe_hw *hw = &adapter->hw;
5120 u32 ctrl, fctrl;
5121 u32 wufc = adapter->wol;
5122 #ifdef CONFIG_PM
5123 int retval = 0;
5124 #endif
5125
5126 netif_device_detach(netdev);
5127
5128 rtnl_lock();
5129 if (netif_running(netdev)) {
5130 ixgbe_down(adapter);
5131 ixgbe_free_irq(adapter);
5132 ixgbe_free_all_tx_resources(adapter);
5133 ixgbe_free_all_rx_resources(adapter);
5134 }
5135 rtnl_unlock();
5136
5137 ixgbe_clear_interrupt_scheme(adapter);
5138
5139 #ifdef CONFIG_PM
5140 retval = pci_save_state(pdev);
5141 if (retval)
5142 return retval;
5143
5144 #endif
5145 if (wufc) {
5146 ixgbe_set_rx_mode(netdev);
5147
5148 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5149 if (hw->mac.ops.enable_tx_laser)
5150 hw->mac.ops.enable_tx_laser(hw);
5151
5152 /* turn on all-multi mode if wake on multicast is enabled */
5153 if (wufc & IXGBE_WUFC_MC) {
5154 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5155 fctrl |= IXGBE_FCTRL_MPE;
5156 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5157 }
5158
5159 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5160 ctrl |= IXGBE_CTRL_GIO_DIS;
5161 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5162
5163 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5164 } else {
5165 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5166 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5167 }
5168
5169 switch (hw->mac.type) {
5170 case ixgbe_mac_82598EB:
5171 pci_wake_from_d3(pdev, false);
5172 break;
5173 case ixgbe_mac_82599EB:
5174 case ixgbe_mac_X540:
5175 pci_wake_from_d3(pdev, !!wufc);
5176 break;
5177 default:
5178 break;
5179 }
5180
5181 *enable_wake = !!wufc;
5182
5183 ixgbe_release_hw_control(adapter);
5184
5185 pci_disable_device(pdev);
5186
5187 return 0;
5188 }
5189
5190 #ifdef CONFIG_PM
5191 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5192 {
5193 int retval;
5194 bool wake;
5195
5196 retval = __ixgbe_shutdown(pdev, &wake);
5197 if (retval)
5198 return retval;
5199
5200 if (wake) {
5201 pci_prepare_to_sleep(pdev);
5202 } else {
5203 pci_wake_from_d3(pdev, false);
5204 pci_set_power_state(pdev, PCI_D3hot);
5205 }
5206
5207 return 0;
5208 }
5209 #endif /* CONFIG_PM */
5210
5211 static void ixgbe_shutdown(struct pci_dev *pdev)
5212 {
5213 bool wake;
5214
5215 __ixgbe_shutdown(pdev, &wake);
5216
5217 if (system_state == SYSTEM_POWER_OFF) {
5218 pci_wake_from_d3(pdev, wake);
5219 pci_set_power_state(pdev, PCI_D3hot);
5220 }
5221 }
5222
5223 /**
5224 * ixgbe_update_stats - Update the board statistics counters.
5225 * @adapter: board private structure
5226 **/
5227 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5228 {
5229 struct net_device *netdev = adapter->netdev;
5230 struct ixgbe_hw *hw = &adapter->hw;
5231 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5232 u64 total_mpc = 0;
5233 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5234 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5235 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5236 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5237
5238 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5239 test_bit(__IXGBE_RESETTING, &adapter->state))
5240 return;
5241
5242 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5243 u64 rsc_count = 0;
5244 u64 rsc_flush = 0;
5245 for (i = 0; i < adapter->num_rx_queues; i++) {
5246 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5247 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5248 }
5249 adapter->rsc_total_count = rsc_count;
5250 adapter->rsc_total_flush = rsc_flush;
5251 }
5252
5253 for (i = 0; i < adapter->num_rx_queues; i++) {
5254 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5255 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5256 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5257 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5258 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5259 bytes += rx_ring->stats.bytes;
5260 packets += rx_ring->stats.packets;
5261 }
5262 adapter->non_eop_descs = non_eop_descs;
5263 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5264 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5265 adapter->hw_csum_rx_error = hw_csum_rx_error;
5266 netdev->stats.rx_bytes = bytes;
5267 netdev->stats.rx_packets = packets;
5268
5269 bytes = 0;
5270 packets = 0;
5271 /* gather some stats to the adapter struct that are per queue */
5272 for (i = 0; i < adapter->num_tx_queues; i++) {
5273 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5274 restart_queue += tx_ring->tx_stats.restart_queue;
5275 tx_busy += tx_ring->tx_stats.tx_busy;
5276 bytes += tx_ring->stats.bytes;
5277 packets += tx_ring->stats.packets;
5278 }
5279 adapter->restart_queue = restart_queue;
5280 adapter->tx_busy = tx_busy;
5281 netdev->stats.tx_bytes = bytes;
5282 netdev->stats.tx_packets = packets;
5283
5284 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5285
5286 /* 8 register reads */
5287 for (i = 0; i < 8; i++) {
5288 /* for packet buffers not used, the register should read 0 */
5289 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5290 missed_rx += mpc;
5291 hwstats->mpc[i] += mpc;
5292 total_mpc += hwstats->mpc[i];
5293 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5294 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5295 switch (hw->mac.type) {
5296 case ixgbe_mac_82598EB:
5297 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5298 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5299 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5300 hwstats->pxonrxc[i] +=
5301 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5302 break;
5303 case ixgbe_mac_82599EB:
5304 case ixgbe_mac_X540:
5305 hwstats->pxonrxc[i] +=
5306 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5307 break;
5308 default:
5309 break;
5310 }
5311 }
5312
5313 /*16 register reads */
5314 for (i = 0; i < 16; i++) {
5315 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5316 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5317 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5318 (hw->mac.type == ixgbe_mac_X540)) {
5319 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5320 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5321 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5322 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5323 }
5324 }
5325
5326 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5327 /* work around hardware counting issue */
5328 hwstats->gprc -= missed_rx;
5329
5330 ixgbe_update_xoff_received(adapter);
5331
5332 /* 82598 hardware only has a 32 bit counter in the high register */
5333 switch (hw->mac.type) {
5334 case ixgbe_mac_82598EB:
5335 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5336 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5337 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5338 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5339 break;
5340 case ixgbe_mac_X540:
5341 /* OS2BMC stats are X540 only*/
5342 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5343 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5344 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5345 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5346 case ixgbe_mac_82599EB:
5347 for (i = 0; i < 16; i++)
5348 adapter->hw_rx_no_dma_resources +=
5349 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5350 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5351 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5352 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5353 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5354 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5355 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5356 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5357 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5358 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5359 #ifdef IXGBE_FCOE
5360 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5361 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5362 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5363 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5364 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5365 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5366 /* Add up per cpu counters for total ddp aloc fail */
5367 if (adapter->fcoe.ddp_pool) {
5368 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5369 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5370 unsigned int cpu;
5371 u64 noddp = 0, noddp_ext_buff = 0;
5372 for_each_possible_cpu(cpu) {
5373 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5374 noddp += ddp_pool->noddp;
5375 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5376 }
5377 hwstats->fcoe_noddp = noddp;
5378 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5379 }
5380 #endif /* IXGBE_FCOE */
5381 break;
5382 default:
5383 break;
5384 }
5385 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5386 hwstats->bprc += bprc;
5387 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5388 if (hw->mac.type == ixgbe_mac_82598EB)
5389 hwstats->mprc -= bprc;
5390 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5391 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5392 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5393 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5394 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5395 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5396 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5397 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5398 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5399 hwstats->lxontxc += lxon;
5400 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5401 hwstats->lxofftxc += lxoff;
5402 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5403 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5404 /*
5405 * 82598 errata - tx of flow control packets is included in tx counters
5406 */
5407 xon_off_tot = lxon + lxoff;
5408 hwstats->gptc -= xon_off_tot;
5409 hwstats->mptc -= xon_off_tot;
5410 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5411 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5412 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5413 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5414 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5415 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5416 hwstats->ptc64 -= xon_off_tot;
5417 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5418 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5419 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5420 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5421 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5422 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5423
5424 /* Fill out the OS statistics structure */
5425 netdev->stats.multicast = hwstats->mprc;
5426
5427 /* Rx Errors */
5428 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5429 netdev->stats.rx_dropped = 0;
5430 netdev->stats.rx_length_errors = hwstats->rlec;
5431 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5432 netdev->stats.rx_missed_errors = total_mpc;
5433 }
5434
5435 /**
5436 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5437 * @adapter: pointer to the device adapter structure
5438 **/
5439 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5440 {
5441 struct ixgbe_hw *hw = &adapter->hw;
5442 int i;
5443
5444 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5445 return;
5446
5447 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5448
5449 /* if interface is down do nothing */
5450 if (test_bit(__IXGBE_DOWN, &adapter->state))
5451 return;
5452
5453 /* do nothing if we are not using signature filters */
5454 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5455 return;
5456
5457 adapter->fdir_overflow++;
5458
5459 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5460 for (i = 0; i < adapter->num_tx_queues; i++)
5461 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5462 &(adapter->tx_ring[i]->state));
5463 /* re-enable flow director interrupts */
5464 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5465 } else {
5466 e_err(probe, "failed to finish FDIR re-initialization, "
5467 "ignored adding FDIR ATR filters\n");
5468 }
5469 }
5470
5471 /**
5472 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5473 * @adapter: pointer to the device adapter structure
5474 *
5475 * This function serves two purposes. First it strobes the interrupt lines
5476 * in order to make certain interrupts are occurring. Secondly it sets the
5477 * bits needed to check for TX hangs. As a result we should immediately
5478 * determine if a hang has occurred.
5479 */
5480 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5481 {
5482 struct ixgbe_hw *hw = &adapter->hw;
5483 u64 eics = 0;
5484 int i;
5485
5486 /* If we're down or resetting, just bail */
5487 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5488 test_bit(__IXGBE_RESETTING, &adapter->state))
5489 return;
5490
5491 /* Force detection of hung controller */
5492 if (netif_carrier_ok(adapter->netdev)) {
5493 for (i = 0; i < adapter->num_tx_queues; i++)
5494 set_check_for_tx_hang(adapter->tx_ring[i]);
5495 }
5496
5497 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5498 /*
5499 * for legacy and MSI interrupts don't set any bits
5500 * that are enabled for EIAM, because this operation
5501 * would set *both* EIMS and EICS for any bit in EIAM
5502 */
5503 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5504 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5505 } else {
5506 /* get one bit for every active tx/rx interrupt vector */
5507 for (i = 0; i < adapter->num_q_vectors; i++) {
5508 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5509 if (qv->rx.ring || qv->tx.ring)
5510 eics |= ((u64)1 << i);
5511 }
5512 }
5513
5514 /* Cause software interrupt to ensure rings are cleaned */
5515 ixgbe_irq_rearm_queues(adapter, eics);
5516
5517 }
5518
5519 /**
5520 * ixgbe_watchdog_update_link - update the link status
5521 * @adapter: pointer to the device adapter structure
5522 * @link_speed: pointer to a u32 to store the link_speed
5523 **/
5524 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5525 {
5526 struct ixgbe_hw *hw = &adapter->hw;
5527 u32 link_speed = adapter->link_speed;
5528 bool link_up = adapter->link_up;
5529 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5530
5531 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5532 return;
5533
5534 if (hw->mac.ops.check_link) {
5535 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5536 } else {
5537 /* always assume link is up, if no check link function */
5538 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5539 link_up = true;
5540 }
5541
5542 if (adapter->ixgbe_ieee_pfc)
5543 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5544
5545 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5546 hw->mac.ops.fc_enable(hw);
5547 ixgbe_set_rx_drop_en(adapter);
5548 }
5549
5550 if (link_up ||
5551 time_after(jiffies, (adapter->link_check_timeout +
5552 IXGBE_TRY_LINK_TIMEOUT))) {
5553 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5554 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5555 IXGBE_WRITE_FLUSH(hw);
5556 }
5557
5558 adapter->link_up = link_up;
5559 adapter->link_speed = link_speed;
5560 }
5561
5562 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5563 {
5564 #ifdef CONFIG_IXGBE_DCB
5565 struct net_device *netdev = adapter->netdev;
5566 struct dcb_app app = {
5567 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5568 .protocol = 0,
5569 };
5570 u8 up = 0;
5571
5572 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5573 up = dcb_ieee_getapp_mask(netdev, &app);
5574
5575 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5576 #endif
5577 }
5578
5579 /**
5580 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5581 * print link up message
5582 * @adapter: pointer to the device adapter structure
5583 **/
5584 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5585 {
5586 struct net_device *netdev = adapter->netdev;
5587 struct ixgbe_hw *hw = &adapter->hw;
5588 u32 link_speed = adapter->link_speed;
5589 bool flow_rx, flow_tx;
5590
5591 /* only continue if link was previously down */
5592 if (netif_carrier_ok(netdev))
5593 return;
5594
5595 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5596
5597 switch (hw->mac.type) {
5598 case ixgbe_mac_82598EB: {
5599 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5600 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5601 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5602 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5603 }
5604 break;
5605 case ixgbe_mac_X540:
5606 case ixgbe_mac_82599EB: {
5607 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5608 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5609 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5610 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5611 }
5612 break;
5613 default:
5614 flow_tx = false;
5615 flow_rx = false;
5616 break;
5617 }
5618
5619 adapter->last_rx_ptp_check = jiffies;
5620
5621 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5622 ixgbe_ptp_start_cyclecounter(adapter);
5623
5624 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5625 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5626 "10 Gbps" :
5627 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5628 "1 Gbps" :
5629 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5630 "100 Mbps" :
5631 "unknown speed"))),
5632 ((flow_rx && flow_tx) ? "RX/TX" :
5633 (flow_rx ? "RX" :
5634 (flow_tx ? "TX" : "None"))));
5635
5636 netif_carrier_on(netdev);
5637 ixgbe_check_vf_rate_limit(adapter);
5638
5639 /* update the default user priority for VFs */
5640 ixgbe_update_default_up(adapter);
5641
5642 /* ping all the active vfs to let them know link has changed */
5643 ixgbe_ping_all_vfs(adapter);
5644 }
5645
5646 /**
5647 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5648 * print link down message
5649 * @adapter: pointer to the adapter structure
5650 **/
5651 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5652 {
5653 struct net_device *netdev = adapter->netdev;
5654 struct ixgbe_hw *hw = &adapter->hw;
5655
5656 adapter->link_up = false;
5657 adapter->link_speed = 0;
5658
5659 /* only continue if link was up previously */
5660 if (!netif_carrier_ok(netdev))
5661 return;
5662
5663 /* poll for SFP+ cable when link is down */
5664 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5665 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5666
5667 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5668 ixgbe_ptp_start_cyclecounter(adapter);
5669
5670 e_info(drv, "NIC Link is Down\n");
5671 netif_carrier_off(netdev);
5672
5673 /* ping all the active vfs to let them know link has changed */
5674 ixgbe_ping_all_vfs(adapter);
5675 }
5676
5677 /**
5678 * ixgbe_watchdog_flush_tx - flush queues on link down
5679 * @adapter: pointer to the device adapter structure
5680 **/
5681 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5682 {
5683 int i;
5684 int some_tx_pending = 0;
5685
5686 if (!netif_carrier_ok(adapter->netdev)) {
5687 for (i = 0; i < adapter->num_tx_queues; i++) {
5688 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5689 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5690 some_tx_pending = 1;
5691 break;
5692 }
5693 }
5694
5695 if (some_tx_pending) {
5696 /* We've lost link, so the controller stops DMA,
5697 * but we've got queued Tx work that's never going
5698 * to get done, so reset controller to flush Tx.
5699 * (Do the reset outside of interrupt context).
5700 */
5701 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
5702 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5703 }
5704 }
5705 }
5706
5707 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5708 {
5709 u32 ssvpc;
5710
5711 /* Do not perform spoof check for 82598 or if not in IOV mode */
5712 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5713 adapter->num_vfs == 0)
5714 return;
5715
5716 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5717
5718 /*
5719 * ssvpc register is cleared on read, if zero then no
5720 * spoofed packets in the last interval.
5721 */
5722 if (!ssvpc)
5723 return;
5724
5725 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
5726 }
5727
5728 /**
5729 * ixgbe_watchdog_subtask - check and bring link up
5730 * @adapter: pointer to the device adapter structure
5731 **/
5732 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5733 {
5734 /* if interface is down do nothing */
5735 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5736 test_bit(__IXGBE_RESETTING, &adapter->state))
5737 return;
5738
5739 ixgbe_watchdog_update_link(adapter);
5740
5741 if (adapter->link_up)
5742 ixgbe_watchdog_link_is_up(adapter);
5743 else
5744 ixgbe_watchdog_link_is_down(adapter);
5745
5746 ixgbe_spoof_check(adapter);
5747 ixgbe_update_stats(adapter);
5748
5749 ixgbe_watchdog_flush_tx(adapter);
5750 }
5751
5752 /**
5753 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5754 * @adapter: the ixgbe adapter structure
5755 **/
5756 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5757 {
5758 struct ixgbe_hw *hw = &adapter->hw;
5759 s32 err;
5760
5761 /* not searching for SFP so there is nothing to do here */
5762 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5763 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5764 return;
5765
5766 /* concurent i2c reads are not supported */
5767 if (test_bit(__IXGBE_READ_I2C, &adapter->state))
5768 return;
5769
5770 /* someone else is in init, wait until next service event */
5771 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5772 return;
5773
5774 err = hw->phy.ops.identify_sfp(hw);
5775 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5776 goto sfp_out;
5777
5778 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5779 /* If no cable is present, then we need to reset
5780 * the next time we find a good cable. */
5781 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5782 }
5783
5784 /* exit on error */
5785 if (err)
5786 goto sfp_out;
5787
5788 /* exit if reset not needed */
5789 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5790 goto sfp_out;
5791
5792 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5793
5794 /*
5795 * A module may be identified correctly, but the EEPROM may not have
5796 * support for that module. setup_sfp() will fail in that case, so
5797 * we should not allow that module to load.
5798 */
5799 if (hw->mac.type == ixgbe_mac_82598EB)
5800 err = hw->phy.ops.reset(hw);
5801 else
5802 err = hw->mac.ops.setup_sfp(hw);
5803
5804 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5805 goto sfp_out;
5806
5807 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5808 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5809
5810 sfp_out:
5811 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5812
5813 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5814 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5815 e_dev_err("failed to initialize because an unsupported "
5816 "SFP+ module type was detected.\n");
5817 e_dev_err("Reload the driver after installing a "
5818 "supported module.\n");
5819 unregister_netdev(adapter->netdev);
5820 }
5821 }
5822
5823 /**
5824 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5825 * @adapter: the ixgbe adapter structure
5826 **/
5827 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5828 {
5829 struct ixgbe_hw *hw = &adapter->hw;
5830 u32 speed;
5831 bool autoneg = false;
5832
5833 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5834 return;
5835
5836 /* someone else is in init, wait until next service event */
5837 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5838 return;
5839
5840 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5841
5842 speed = hw->phy.autoneg_advertised;
5843 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5844 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
5845 if (hw->mac.ops.setup_link)
5846 hw->mac.ops.setup_link(hw, speed, true);
5847
5848 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5849 adapter->link_check_timeout = jiffies;
5850 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5851 }
5852
5853 #ifdef CONFIG_PCI_IOV
5854 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5855 {
5856 int vf;
5857 struct ixgbe_hw *hw = &adapter->hw;
5858 struct net_device *netdev = adapter->netdev;
5859 u32 gpc;
5860 u32 ciaa, ciad;
5861
5862 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5863 if (gpc) /* If incrementing then no need for the check below */
5864 return;
5865 /*
5866 * Check to see if a bad DMA write target from an errant or
5867 * malicious VF has caused a PCIe error. If so then we can
5868 * issue a VFLR to the offending VF(s) and then resume without
5869 * requesting a full slot reset.
5870 */
5871
5872 for (vf = 0; vf < adapter->num_vfs; vf++) {
5873 ciaa = (vf << 16) | 0x80000000;
5874 /* 32 bit read so align, we really want status at offset 6 */
5875 ciaa |= PCI_COMMAND;
5876 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5877 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5878 ciaa &= 0x7FFFFFFF;
5879 /* disable debug mode asap after reading data */
5880 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5881 /* Get the upper 16 bits which will be the PCI status reg */
5882 ciad >>= 16;
5883 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5884 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5885 /* Issue VFLR */
5886 ciaa = (vf << 16) | 0x80000000;
5887 ciaa |= 0xA8;
5888 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5889 ciad = 0x00008000; /* VFLR */
5890 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5891 ciaa &= 0x7FFFFFFF;
5892 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5893 }
5894 }
5895 }
5896
5897 #endif
5898 /**
5899 * ixgbe_service_timer - Timer Call-back
5900 * @data: pointer to adapter cast into an unsigned long
5901 **/
5902 static void ixgbe_service_timer(unsigned long data)
5903 {
5904 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5905 unsigned long next_event_offset;
5906 bool ready = true;
5907
5908 /* poll faster when waiting for link */
5909 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5910 next_event_offset = HZ / 10;
5911 else
5912 next_event_offset = HZ * 2;
5913
5914 #ifdef CONFIG_PCI_IOV
5915 /*
5916 * don't bother with SR-IOV VF DMA hang check if there are
5917 * no VFs or the link is down
5918 */
5919 if (!adapter->num_vfs ||
5920 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5921 goto normal_timer_service;
5922
5923 /* If we have VFs allocated then we must check for DMA hangs */
5924 ixgbe_check_for_bad_vf(adapter);
5925 next_event_offset = HZ / 50;
5926 adapter->timer_event_accumulator++;
5927
5928 if (adapter->timer_event_accumulator >= 100)
5929 adapter->timer_event_accumulator = 0;
5930 else
5931 ready = false;
5932
5933 normal_timer_service:
5934 #endif
5935 /* Reset the timer */
5936 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5937
5938 if (ready)
5939 ixgbe_service_event_schedule(adapter);
5940 }
5941
5942 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5943 {
5944 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5945 return;
5946
5947 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5948
5949 /* If we're already down or resetting, just bail */
5950 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5951 test_bit(__IXGBE_RESETTING, &adapter->state))
5952 return;
5953
5954 ixgbe_dump(adapter);
5955 netdev_err(adapter->netdev, "Reset adapter\n");
5956 adapter->tx_timeout_count++;
5957
5958 ixgbe_reinit_locked(adapter);
5959 }
5960
5961 /**
5962 * ixgbe_service_task - manages and runs subtasks
5963 * @work: pointer to work_struct containing our data
5964 **/
5965 static void ixgbe_service_task(struct work_struct *work)
5966 {
5967 struct ixgbe_adapter *adapter = container_of(work,
5968 struct ixgbe_adapter,
5969 service_task);
5970 ixgbe_reset_subtask(adapter);
5971 ixgbe_sfp_detection_subtask(adapter);
5972 ixgbe_sfp_link_config_subtask(adapter);
5973 ixgbe_check_overtemp_subtask(adapter);
5974 ixgbe_watchdog_subtask(adapter);
5975 ixgbe_fdir_reinit_subtask(adapter);
5976 ixgbe_check_hang_subtask(adapter);
5977
5978 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) {
5979 ixgbe_ptp_overflow_check(adapter);
5980 ixgbe_ptp_rx_hang(adapter);
5981 }
5982
5983 ixgbe_service_event_complete(adapter);
5984 }
5985
5986 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5987 struct ixgbe_tx_buffer *first,
5988 u8 *hdr_len)
5989 {
5990 struct sk_buff *skb = first->skb;
5991 u32 vlan_macip_lens, type_tucmd;
5992 u32 mss_l4len_idx, l4len;
5993
5994 if (skb->ip_summed != CHECKSUM_PARTIAL)
5995 return 0;
5996
5997 if (!skb_is_gso(skb))
5998 return 0;
5999
6000 if (skb_header_cloned(skb)) {
6001 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6002 if (err)
6003 return err;
6004 }
6005
6006 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6007 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6008
6009 if (first->protocol == __constant_htons(ETH_P_IP)) {
6010 struct iphdr *iph = ip_hdr(skb);
6011 iph->tot_len = 0;
6012 iph->check = 0;
6013 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6014 iph->daddr, 0,
6015 IPPROTO_TCP,
6016 0);
6017 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6018 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6019 IXGBE_TX_FLAGS_CSUM |
6020 IXGBE_TX_FLAGS_IPV4;
6021 } else if (skb_is_gso_v6(skb)) {
6022 ipv6_hdr(skb)->payload_len = 0;
6023 tcp_hdr(skb)->check =
6024 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6025 &ipv6_hdr(skb)->daddr,
6026 0, IPPROTO_TCP, 0);
6027 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6028 IXGBE_TX_FLAGS_CSUM;
6029 }
6030
6031 /* compute header lengths */
6032 l4len = tcp_hdrlen(skb);
6033 *hdr_len = skb_transport_offset(skb) + l4len;
6034
6035 /* update gso size and bytecount with header size */
6036 first->gso_segs = skb_shinfo(skb)->gso_segs;
6037 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6038
6039 /* mss_l4len_id: use 0 as index for TSO */
6040 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6041 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6042
6043 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6044 vlan_macip_lens = skb_network_header_len(skb);
6045 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6046 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6047
6048 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6049 mss_l4len_idx);
6050
6051 return 1;
6052 }
6053
6054 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6055 struct ixgbe_tx_buffer *first)
6056 {
6057 struct sk_buff *skb = first->skb;
6058 u32 vlan_macip_lens = 0;
6059 u32 mss_l4len_idx = 0;
6060 u32 type_tucmd = 0;
6061
6062 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6063 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6064 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6065 return;
6066 } else {
6067 u8 l4_hdr = 0;
6068 switch (first->protocol) {
6069 case __constant_htons(ETH_P_IP):
6070 vlan_macip_lens |= skb_network_header_len(skb);
6071 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6072 l4_hdr = ip_hdr(skb)->protocol;
6073 break;
6074 case __constant_htons(ETH_P_IPV6):
6075 vlan_macip_lens |= skb_network_header_len(skb);
6076 l4_hdr = ipv6_hdr(skb)->nexthdr;
6077 break;
6078 default:
6079 if (unlikely(net_ratelimit())) {
6080 dev_warn(tx_ring->dev,
6081 "partial checksum but proto=%x!\n",
6082 first->protocol);
6083 }
6084 break;
6085 }
6086
6087 switch (l4_hdr) {
6088 case IPPROTO_TCP:
6089 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6090 mss_l4len_idx = tcp_hdrlen(skb) <<
6091 IXGBE_ADVTXD_L4LEN_SHIFT;
6092 break;
6093 case IPPROTO_SCTP:
6094 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6095 mss_l4len_idx = sizeof(struct sctphdr) <<
6096 IXGBE_ADVTXD_L4LEN_SHIFT;
6097 break;
6098 case IPPROTO_UDP:
6099 mss_l4len_idx = sizeof(struct udphdr) <<
6100 IXGBE_ADVTXD_L4LEN_SHIFT;
6101 break;
6102 default:
6103 if (unlikely(net_ratelimit())) {
6104 dev_warn(tx_ring->dev,
6105 "partial checksum but l4 proto=%x!\n",
6106 l4_hdr);
6107 }
6108 break;
6109 }
6110
6111 /* update TX checksum flag */
6112 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6113 }
6114
6115 /* vlan_macip_lens: MACLEN, VLAN tag */
6116 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6117 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6118
6119 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6120 type_tucmd, mss_l4len_idx);
6121 }
6122
6123 #define IXGBE_SET_FLAG(_input, _flag, _result) \
6124 ((_flag <= _result) ? \
6125 ((u32)(_input & _flag) * (_result / _flag)) : \
6126 ((u32)(_input & _flag) / (_flag / _result)))
6127
6128 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6129 {
6130 /* set type for advanced descriptor with frame checksum insertion */
6131 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6132 IXGBE_ADVTXD_DCMD_DEXT |
6133 IXGBE_ADVTXD_DCMD_IFCS;
6134
6135 /* set HW vlan bit if vlan is present */
6136 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6137 IXGBE_ADVTXD_DCMD_VLE);
6138
6139 /* set segmentation enable bits for TSO/FSO */
6140 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6141 IXGBE_ADVTXD_DCMD_TSE);
6142
6143 /* set timestamp bit if present */
6144 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6145 IXGBE_ADVTXD_MAC_TSTAMP);
6146
6147 /* insert frame checksum */
6148 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
6149
6150 return cmd_type;
6151 }
6152
6153 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6154 u32 tx_flags, unsigned int paylen)
6155 {
6156 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
6157
6158 /* enable L4 checksum for TSO and TX checksum offload */
6159 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6160 IXGBE_TX_FLAGS_CSUM,
6161 IXGBE_ADVTXD_POPTS_TXSM);
6162
6163 /* enble IPv4 checksum for TSO */
6164 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6165 IXGBE_TX_FLAGS_IPV4,
6166 IXGBE_ADVTXD_POPTS_IXSM);
6167
6168 /*
6169 * Check Context must be set if Tx switch is enabled, which it
6170 * always is for case where virtual functions are running
6171 */
6172 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6173 IXGBE_TX_FLAGS_CC,
6174 IXGBE_ADVTXD_CC);
6175
6176 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6177 }
6178
6179 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6180 IXGBE_TXD_CMD_RS)
6181
6182 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6183 struct ixgbe_tx_buffer *first,
6184 const u8 hdr_len)
6185 {
6186 struct sk_buff *skb = first->skb;
6187 struct ixgbe_tx_buffer *tx_buffer;
6188 union ixgbe_adv_tx_desc *tx_desc;
6189 struct skb_frag_struct *frag;
6190 dma_addr_t dma;
6191 unsigned int data_len, size;
6192 u32 tx_flags = first->tx_flags;
6193 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
6194 u16 i = tx_ring->next_to_use;
6195
6196 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6197
6198 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6199
6200 size = skb_headlen(skb);
6201 data_len = skb->data_len;
6202
6203 #ifdef IXGBE_FCOE
6204 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6205 if (data_len < sizeof(struct fcoe_crc_eof)) {
6206 size -= sizeof(struct fcoe_crc_eof) - data_len;
6207 data_len = 0;
6208 } else {
6209 data_len -= sizeof(struct fcoe_crc_eof);
6210 }
6211 }
6212
6213 #endif
6214 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6215
6216 tx_buffer = first;
6217
6218 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6219 if (dma_mapping_error(tx_ring->dev, dma))
6220 goto dma_error;
6221
6222 /* record length, and DMA address */
6223 dma_unmap_len_set(tx_buffer, len, size);
6224 dma_unmap_addr_set(tx_buffer, dma, dma);
6225
6226 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6227
6228 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6229 tx_desc->read.cmd_type_len =
6230 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
6231
6232 i++;
6233 tx_desc++;
6234 if (i == tx_ring->count) {
6235 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6236 i = 0;
6237 }
6238 tx_desc->read.olinfo_status = 0;
6239
6240 dma += IXGBE_MAX_DATA_PER_TXD;
6241 size -= IXGBE_MAX_DATA_PER_TXD;
6242
6243 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6244 }
6245
6246 if (likely(!data_len))
6247 break;
6248
6249 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6250
6251 i++;
6252 tx_desc++;
6253 if (i == tx_ring->count) {
6254 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6255 i = 0;
6256 }
6257 tx_desc->read.olinfo_status = 0;
6258
6259 #ifdef IXGBE_FCOE
6260 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6261 #else
6262 size = skb_frag_size(frag);
6263 #endif
6264 data_len -= size;
6265
6266 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6267 DMA_TO_DEVICE);
6268
6269 tx_buffer = &tx_ring->tx_buffer_info[i];
6270 }
6271
6272 /* write last descriptor with RS and EOP bits */
6273 cmd_type |= size | IXGBE_TXD_CMD;
6274 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6275
6276 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6277
6278 /* set the timestamp */
6279 first->time_stamp = jiffies;
6280
6281 /*
6282 * Force memory writes to complete before letting h/w know there
6283 * are new descriptors to fetch. (Only applicable for weak-ordered
6284 * memory model archs, such as IA-64).
6285 *
6286 * We also need this memory barrier to make certain all of the
6287 * status bits have been updated before next_to_watch is written.
6288 */
6289 wmb();
6290
6291 /* set next_to_watch value indicating a packet is present */
6292 first->next_to_watch = tx_desc;
6293
6294 i++;
6295 if (i == tx_ring->count)
6296 i = 0;
6297
6298 tx_ring->next_to_use = i;
6299
6300 /* notify HW of packet */
6301 writel(i, tx_ring->tail);
6302
6303 return;
6304 dma_error:
6305 dev_err(tx_ring->dev, "TX DMA map failed\n");
6306
6307 /* clear dma mappings for failed tx_buffer_info map */
6308 for (;;) {
6309 tx_buffer = &tx_ring->tx_buffer_info[i];
6310 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6311 if (tx_buffer == first)
6312 break;
6313 if (i == 0)
6314 i = tx_ring->count;
6315 i--;
6316 }
6317
6318 tx_ring->next_to_use = i;
6319 }
6320
6321 static void ixgbe_atr(struct ixgbe_ring *ring,
6322 struct ixgbe_tx_buffer *first)
6323 {
6324 struct ixgbe_q_vector *q_vector = ring->q_vector;
6325 union ixgbe_atr_hash_dword input = { .dword = 0 };
6326 union ixgbe_atr_hash_dword common = { .dword = 0 };
6327 union {
6328 unsigned char *network;
6329 struct iphdr *ipv4;
6330 struct ipv6hdr *ipv6;
6331 } hdr;
6332 struct tcphdr *th;
6333 __be16 vlan_id;
6334
6335 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6336 if (!q_vector)
6337 return;
6338
6339 /* do nothing if sampling is disabled */
6340 if (!ring->atr_sample_rate)
6341 return;
6342
6343 ring->atr_count++;
6344
6345 /* snag network header to get L4 type and address */
6346 hdr.network = skb_network_header(first->skb);
6347
6348 /* Currently only IPv4/IPv6 with TCP is supported */
6349 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6350 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6351 (first->protocol != __constant_htons(ETH_P_IP) ||
6352 hdr.ipv4->protocol != IPPROTO_TCP))
6353 return;
6354
6355 th = tcp_hdr(first->skb);
6356
6357 /* skip this packet since it is invalid or the socket is closing */
6358 if (!th || th->fin)
6359 return;
6360
6361 /* sample on all syn packets or once every atr sample count */
6362 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6363 return;
6364
6365 /* reset sample count */
6366 ring->atr_count = 0;
6367
6368 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6369
6370 /*
6371 * src and dst are inverted, think how the receiver sees them
6372 *
6373 * The input is broken into two sections, a non-compressed section
6374 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6375 * is XORed together and stored in the compressed dword.
6376 */
6377 input.formatted.vlan_id = vlan_id;
6378
6379 /*
6380 * since src port and flex bytes occupy the same word XOR them together
6381 * and write the value to source port portion of compressed dword
6382 */
6383 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6384 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6385 else
6386 common.port.src ^= th->dest ^ first->protocol;
6387 common.port.dst ^= th->source;
6388
6389 if (first->protocol == __constant_htons(ETH_P_IP)) {
6390 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6391 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6392 } else {
6393 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6394 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6395 hdr.ipv6->saddr.s6_addr32[1] ^
6396 hdr.ipv6->saddr.s6_addr32[2] ^
6397 hdr.ipv6->saddr.s6_addr32[3] ^
6398 hdr.ipv6->daddr.s6_addr32[0] ^
6399 hdr.ipv6->daddr.s6_addr32[1] ^
6400 hdr.ipv6->daddr.s6_addr32[2] ^
6401 hdr.ipv6->daddr.s6_addr32[3];
6402 }
6403
6404 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6405 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6406 input, common, ring->queue_index);
6407 }
6408
6409 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6410 {
6411 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6412 /* Herbert's original patch had:
6413 * smp_mb__after_netif_stop_queue();
6414 * but since that doesn't exist yet, just open code it. */
6415 smp_mb();
6416
6417 /* We need to check again in a case another CPU has just
6418 * made room available. */
6419 if (likely(ixgbe_desc_unused(tx_ring) < size))
6420 return -EBUSY;
6421
6422 /* A reprieve! - use start_queue because it doesn't call schedule */
6423 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6424 ++tx_ring->tx_stats.restart_queue;
6425 return 0;
6426 }
6427
6428 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6429 {
6430 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6431 return 0;
6432 return __ixgbe_maybe_stop_tx(tx_ring, size);
6433 }
6434
6435 #ifdef IXGBE_FCOE
6436 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6437 {
6438 struct ixgbe_adapter *adapter;
6439 struct ixgbe_ring_feature *f;
6440 int txq;
6441
6442 /*
6443 * only execute the code below if protocol is FCoE
6444 * or FIP and we have FCoE enabled on the adapter
6445 */
6446 switch (vlan_get_protocol(skb)) {
6447 case __constant_htons(ETH_P_FCOE):
6448 case __constant_htons(ETH_P_FIP):
6449 adapter = netdev_priv(dev);
6450
6451 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6452 break;
6453 default:
6454 return __netdev_pick_tx(dev, skb);
6455 }
6456
6457 f = &adapter->ring_feature[RING_F_FCOE];
6458
6459 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6460 smp_processor_id();
6461
6462 while (txq >= f->indices)
6463 txq -= f->indices;
6464
6465 return txq + f->offset;
6466 }
6467
6468 #endif
6469 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6470 struct ixgbe_adapter *adapter,
6471 struct ixgbe_ring *tx_ring)
6472 {
6473 struct ixgbe_tx_buffer *first;
6474 int tso;
6475 u32 tx_flags = 0;
6476 unsigned short f;
6477 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6478 __be16 protocol = skb->protocol;
6479 u8 hdr_len = 0;
6480
6481 /*
6482 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6483 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6484 * + 2 desc gap to keep tail from touching head,
6485 * + 1 desc for context descriptor,
6486 * otherwise try next time
6487 */
6488 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6489 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6490
6491 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6492 tx_ring->tx_stats.tx_busy++;
6493 return NETDEV_TX_BUSY;
6494 }
6495
6496 /* record the location of the first descriptor for this packet */
6497 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6498 first->skb = skb;
6499 first->bytecount = skb->len;
6500 first->gso_segs = 1;
6501
6502 /* if we have a HW VLAN tag being added default to the HW one */
6503 if (vlan_tx_tag_present(skb)) {
6504 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6505 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6506 /* else if it is a SW VLAN check the next protocol and store the tag */
6507 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6508 struct vlan_hdr *vhdr, _vhdr;
6509 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6510 if (!vhdr)
6511 goto out_drop;
6512
6513 protocol = vhdr->h_vlan_encapsulated_proto;
6514 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6515 IXGBE_TX_FLAGS_VLAN_SHIFT;
6516 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6517 }
6518
6519 skb_tx_timestamp(skb);
6520
6521 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6522 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6523 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6524
6525 /* schedule check for Tx timestamp */
6526 adapter->ptp_tx_skb = skb_get(skb);
6527 adapter->ptp_tx_start = jiffies;
6528 schedule_work(&adapter->ptp_tx_work);
6529 }
6530
6531 #ifdef CONFIG_PCI_IOV
6532 /*
6533 * Use the l2switch_enable flag - would be false if the DMA
6534 * Tx switch had been disabled.
6535 */
6536 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6537 tx_flags |= IXGBE_TX_FLAGS_CC;
6538
6539 #endif
6540 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6541 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6542 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6543 (skb->priority != TC_PRIO_CONTROL))) {
6544 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6545 tx_flags |= (skb->priority & 0x7) <<
6546 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6547 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6548 struct vlan_ethhdr *vhdr;
6549 if (skb_header_cloned(skb) &&
6550 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6551 goto out_drop;
6552 vhdr = (struct vlan_ethhdr *)skb->data;
6553 vhdr->h_vlan_TCI = htons(tx_flags >>
6554 IXGBE_TX_FLAGS_VLAN_SHIFT);
6555 } else {
6556 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6557 }
6558 }
6559
6560 /* record initial flags and protocol */
6561 first->tx_flags = tx_flags;
6562 first->protocol = protocol;
6563
6564 #ifdef IXGBE_FCOE
6565 /* setup tx offload for FCoE */
6566 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6567 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
6568 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6569 if (tso < 0)
6570 goto out_drop;
6571
6572 goto xmit_fcoe;
6573 }
6574
6575 #endif /* IXGBE_FCOE */
6576 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6577 if (tso < 0)
6578 goto out_drop;
6579 else if (!tso)
6580 ixgbe_tx_csum(tx_ring, first);
6581
6582 /* add the ATR filter if ATR is on */
6583 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6584 ixgbe_atr(tx_ring, first);
6585
6586 #ifdef IXGBE_FCOE
6587 xmit_fcoe:
6588 #endif /* IXGBE_FCOE */
6589 ixgbe_tx_map(tx_ring, first, hdr_len);
6590
6591 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6592
6593 return NETDEV_TX_OK;
6594
6595 out_drop:
6596 dev_kfree_skb_any(first->skb);
6597 first->skb = NULL;
6598
6599 return NETDEV_TX_OK;
6600 }
6601
6602 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6603 struct net_device *netdev)
6604 {
6605 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6606 struct ixgbe_ring *tx_ring;
6607
6608 /*
6609 * The minimum packet size for olinfo paylen is 17 so pad the skb
6610 * in order to meet this minimum size requirement.
6611 */
6612 if (unlikely(skb->len < 17)) {
6613 if (skb_pad(skb, 17 - skb->len))
6614 return NETDEV_TX_OK;
6615 skb->len = 17;
6616 skb_set_tail_pointer(skb, 17);
6617 }
6618
6619 tx_ring = adapter->tx_ring[skb->queue_mapping];
6620 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6621 }
6622
6623 /**
6624 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6625 * @netdev: network interface device structure
6626 * @p: pointer to an address structure
6627 *
6628 * Returns 0 on success, negative on failure
6629 **/
6630 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6631 {
6632 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6633 struct ixgbe_hw *hw = &adapter->hw;
6634 struct sockaddr *addr = p;
6635
6636 if (!is_valid_ether_addr(addr->sa_data))
6637 return -EADDRNOTAVAIL;
6638
6639 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6640 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6641
6642 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
6643
6644 return 0;
6645 }
6646
6647 static int
6648 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6649 {
6650 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6651 struct ixgbe_hw *hw = &adapter->hw;
6652 u16 value;
6653 int rc;
6654
6655 if (prtad != hw->phy.mdio.prtad)
6656 return -EINVAL;
6657 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6658 if (!rc)
6659 rc = value;
6660 return rc;
6661 }
6662
6663 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6664 u16 addr, u16 value)
6665 {
6666 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6667 struct ixgbe_hw *hw = &adapter->hw;
6668
6669 if (prtad != hw->phy.mdio.prtad)
6670 return -EINVAL;
6671 return hw->phy.ops.write_reg(hw, addr, devad, value);
6672 }
6673
6674 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6675 {
6676 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6677
6678 switch (cmd) {
6679 case SIOCSHWTSTAMP:
6680 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6681 default:
6682 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6683 }
6684 }
6685
6686 /**
6687 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6688 * netdev->dev_addrs
6689 * @netdev: network interface device structure
6690 *
6691 * Returns non-zero on failure
6692 **/
6693 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6694 {
6695 int err = 0;
6696 struct ixgbe_adapter *adapter = netdev_priv(dev);
6697 struct ixgbe_hw *hw = &adapter->hw;
6698
6699 if (is_valid_ether_addr(hw->mac.san_addr)) {
6700 rtnl_lock();
6701 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
6702 rtnl_unlock();
6703
6704 /* update SAN MAC vmdq pool selection */
6705 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
6706 }
6707 return err;
6708 }
6709
6710 /**
6711 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6712 * netdev->dev_addrs
6713 * @netdev: network interface device structure
6714 *
6715 * Returns non-zero on failure
6716 **/
6717 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6718 {
6719 int err = 0;
6720 struct ixgbe_adapter *adapter = netdev_priv(dev);
6721 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6722
6723 if (is_valid_ether_addr(mac->san_addr)) {
6724 rtnl_lock();
6725 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6726 rtnl_unlock();
6727 }
6728 return err;
6729 }
6730
6731 #ifdef CONFIG_NET_POLL_CONTROLLER
6732 /*
6733 * Polling 'interrupt' - used by things like netconsole to send skbs
6734 * without having to re-enable interrupts. It's not called while
6735 * the interrupt routine is executing.
6736 */
6737 static void ixgbe_netpoll(struct net_device *netdev)
6738 {
6739 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6740 int i;
6741
6742 /* if interface is down do nothing */
6743 if (test_bit(__IXGBE_DOWN, &adapter->state))
6744 return;
6745
6746 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6747 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6748 for (i = 0; i < adapter->num_q_vectors; i++)
6749 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
6750 } else {
6751 ixgbe_intr(adapter->pdev->irq, netdev);
6752 }
6753 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6754 }
6755
6756 #endif
6757 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6758 struct rtnl_link_stats64 *stats)
6759 {
6760 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6761 int i;
6762
6763 rcu_read_lock();
6764 for (i = 0; i < adapter->num_rx_queues; i++) {
6765 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6766 u64 bytes, packets;
6767 unsigned int start;
6768
6769 if (ring) {
6770 do {
6771 start = u64_stats_fetch_begin_bh(&ring->syncp);
6772 packets = ring->stats.packets;
6773 bytes = ring->stats.bytes;
6774 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6775 stats->rx_packets += packets;
6776 stats->rx_bytes += bytes;
6777 }
6778 }
6779
6780 for (i = 0; i < adapter->num_tx_queues; i++) {
6781 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6782 u64 bytes, packets;
6783 unsigned int start;
6784
6785 if (ring) {
6786 do {
6787 start = u64_stats_fetch_begin_bh(&ring->syncp);
6788 packets = ring->stats.packets;
6789 bytes = ring->stats.bytes;
6790 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6791 stats->tx_packets += packets;
6792 stats->tx_bytes += bytes;
6793 }
6794 }
6795 rcu_read_unlock();
6796 /* following stats updated by ixgbe_watchdog_task() */
6797 stats->multicast = netdev->stats.multicast;
6798 stats->rx_errors = netdev->stats.rx_errors;
6799 stats->rx_length_errors = netdev->stats.rx_length_errors;
6800 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6801 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6802 return stats;
6803 }
6804
6805 #ifdef CONFIG_IXGBE_DCB
6806 /**
6807 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6808 * @adapter: pointer to ixgbe_adapter
6809 * @tc: number of traffic classes currently enabled
6810 *
6811 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6812 * 802.1Q priority maps to a packet buffer that exists.
6813 */
6814 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6815 {
6816 struct ixgbe_hw *hw = &adapter->hw;
6817 u32 reg, rsave;
6818 int i;
6819
6820 /* 82598 have a static priority to TC mapping that can not
6821 * be changed so no validation is needed.
6822 */
6823 if (hw->mac.type == ixgbe_mac_82598EB)
6824 return;
6825
6826 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6827 rsave = reg;
6828
6829 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6830 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6831
6832 /* If up2tc is out of bounds default to zero */
6833 if (up2tc > tc)
6834 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6835 }
6836
6837 if (reg != rsave)
6838 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6839
6840 return;
6841 }
6842
6843 /**
6844 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6845 * @adapter: Pointer to adapter struct
6846 *
6847 * Populate the netdev user priority to tc map
6848 */
6849 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6850 {
6851 struct net_device *dev = adapter->netdev;
6852 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6853 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6854 u8 prio;
6855
6856 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6857 u8 tc = 0;
6858
6859 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6860 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6861 else if (ets)
6862 tc = ets->prio_tc[prio];
6863
6864 netdev_set_prio_tc_map(dev, prio, tc);
6865 }
6866 }
6867
6868 #endif /* CONFIG_IXGBE_DCB */
6869 /**
6870 * ixgbe_setup_tc - configure net_device for multiple traffic classes
6871 *
6872 * @netdev: net device to configure
6873 * @tc: number of traffic classes to enable
6874 */
6875 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6876 {
6877 struct ixgbe_adapter *adapter = netdev_priv(dev);
6878 struct ixgbe_hw *hw = &adapter->hw;
6879
6880 /* Hardware supports up to 8 traffic classes */
6881 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6882 (hw->mac.type == ixgbe_mac_82598EB &&
6883 tc < MAX_TRAFFIC_CLASS))
6884 return -EINVAL;
6885
6886 /* Hardware has to reinitialize queues and interrupts to
6887 * match packet buffer alignment. Unfortunately, the
6888 * hardware is not flexible enough to do this dynamically.
6889 */
6890 if (netif_running(dev))
6891 ixgbe_close(dev);
6892 ixgbe_clear_interrupt_scheme(adapter);
6893
6894 #ifdef CONFIG_IXGBE_DCB
6895 if (tc) {
6896 netdev_set_num_tc(dev, tc);
6897 ixgbe_set_prio_tc_map(adapter);
6898
6899 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6900
6901 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6902 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
6903 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6904 }
6905 } else {
6906 netdev_reset_tc(dev);
6907
6908 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6909 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6910
6911 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6912
6913 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6914 adapter->dcb_cfg.pfc_mode_enable = false;
6915 }
6916
6917 ixgbe_validate_rtr(adapter, tc);
6918
6919 #endif /* CONFIG_IXGBE_DCB */
6920 ixgbe_init_interrupt_scheme(adapter);
6921
6922 if (netif_running(dev))
6923 return ixgbe_open(dev);
6924
6925 return 0;
6926 }
6927
6928 #ifdef CONFIG_PCI_IOV
6929 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
6930 {
6931 struct net_device *netdev = adapter->netdev;
6932
6933 rtnl_lock();
6934 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
6935 rtnl_unlock();
6936 }
6937
6938 #endif
6939 void ixgbe_do_reset(struct net_device *netdev)
6940 {
6941 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6942
6943 if (netif_running(netdev))
6944 ixgbe_reinit_locked(adapter);
6945 else
6946 ixgbe_reset(adapter);
6947 }
6948
6949 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6950 netdev_features_t features)
6951 {
6952 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6953
6954 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6955 if (!(features & NETIF_F_RXCSUM))
6956 features &= ~NETIF_F_LRO;
6957
6958 /* Turn off LRO if not RSC capable */
6959 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6960 features &= ~NETIF_F_LRO;
6961
6962 return features;
6963 }
6964
6965 static int ixgbe_set_features(struct net_device *netdev,
6966 netdev_features_t features)
6967 {
6968 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6969 netdev_features_t changed = netdev->features ^ features;
6970 bool need_reset = false;
6971
6972 /* Make sure RSC matches LRO, reset if change */
6973 if (!(features & NETIF_F_LRO)) {
6974 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6975 need_reset = true;
6976 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6977 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6978 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6979 if (adapter->rx_itr_setting == 1 ||
6980 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6981 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6982 need_reset = true;
6983 } else if ((changed ^ features) & NETIF_F_LRO) {
6984 e_info(probe, "rx-usecs set too low, "
6985 "disabling RSC\n");
6986 }
6987 }
6988
6989 /*
6990 * Check if Flow Director n-tuple support was enabled or disabled. If
6991 * the state changed, we need to reset.
6992 */
6993 switch (features & NETIF_F_NTUPLE) {
6994 case NETIF_F_NTUPLE:
6995 /* turn off ATR, enable perfect filters and reset */
6996 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6997 need_reset = true;
6998
6999 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7000 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7001 break;
7002 default:
7003 /* turn off perfect filters, enable ATR and reset */
7004 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7005 need_reset = true;
7006
7007 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7008
7009 /* We cannot enable ATR if SR-IOV is enabled */
7010 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7011 break;
7012
7013 /* We cannot enable ATR if we have 2 or more traffic classes */
7014 if (netdev_get_num_tc(netdev) > 1)
7015 break;
7016
7017 /* We cannot enable ATR if RSS is disabled */
7018 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7019 break;
7020
7021 /* A sample rate of 0 indicates ATR disabled */
7022 if (!adapter->atr_sample_rate)
7023 break;
7024
7025 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7026 break;
7027 }
7028
7029 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7030 ixgbe_vlan_strip_enable(adapter);
7031 else
7032 ixgbe_vlan_strip_disable(adapter);
7033
7034 if (changed & NETIF_F_RXALL)
7035 need_reset = true;
7036
7037 netdev->features = features;
7038 if (need_reset)
7039 ixgbe_do_reset(netdev);
7040
7041 return 0;
7042 }
7043
7044 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7045 struct net_device *dev,
7046 const unsigned char *addr,
7047 u16 flags)
7048 {
7049 struct ixgbe_adapter *adapter = netdev_priv(dev);
7050 int err;
7051
7052 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7053 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
7054
7055 /* Hardware does not support aging addresses so if a
7056 * ndm_state is given only allow permanent addresses
7057 */
7058 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7059 pr_info("%s: FDB only supports static addresses\n",
7060 ixgbe_driver_name);
7061 return -EINVAL;
7062 }
7063
7064 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
7065 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7066
7067 if (netdev_uc_count(dev) < rar_uc_entries)
7068 err = dev_uc_add_excl(dev, addr);
7069 else
7070 err = -ENOMEM;
7071 } else if (is_multicast_ether_addr(addr)) {
7072 err = dev_mc_add_excl(dev, addr);
7073 } else {
7074 err = -EINVAL;
7075 }
7076
7077 /* Only return duplicate errors if NLM_F_EXCL is set */
7078 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7079 err = 0;
7080
7081 return err;
7082 }
7083
7084 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7085 struct nlmsghdr *nlh)
7086 {
7087 struct ixgbe_adapter *adapter = netdev_priv(dev);
7088 struct nlattr *attr, *br_spec;
7089 int rem;
7090
7091 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7092 return -EOPNOTSUPP;
7093
7094 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7095
7096 nla_for_each_nested(attr, br_spec, rem) {
7097 __u16 mode;
7098 u32 reg = 0;
7099
7100 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7101 continue;
7102
7103 mode = nla_get_u16(attr);
7104 if (mode == BRIDGE_MODE_VEPA) {
7105 reg = 0;
7106 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7107 } else if (mode == BRIDGE_MODE_VEB) {
7108 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7109 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7110 } else
7111 return -EINVAL;
7112
7113 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7114
7115 e_info(drv, "enabling bridge mode: %s\n",
7116 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7117 }
7118
7119 return 0;
7120 }
7121
7122 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7123 struct net_device *dev,
7124 u32 filter_mask)
7125 {
7126 struct ixgbe_adapter *adapter = netdev_priv(dev);
7127 u16 mode;
7128
7129 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7130 return 0;
7131
7132 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
7133 mode = BRIDGE_MODE_VEB;
7134 else
7135 mode = BRIDGE_MODE_VEPA;
7136
7137 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7138 }
7139
7140 static const struct net_device_ops ixgbe_netdev_ops = {
7141 .ndo_open = ixgbe_open,
7142 .ndo_stop = ixgbe_close,
7143 .ndo_start_xmit = ixgbe_xmit_frame,
7144 #ifdef IXGBE_FCOE
7145 .ndo_select_queue = ixgbe_select_queue,
7146 #endif
7147 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7148 .ndo_validate_addr = eth_validate_addr,
7149 .ndo_set_mac_address = ixgbe_set_mac,
7150 .ndo_change_mtu = ixgbe_change_mtu,
7151 .ndo_tx_timeout = ixgbe_tx_timeout,
7152 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7153 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7154 .ndo_do_ioctl = ixgbe_ioctl,
7155 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7156 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7157 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7158 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7159 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7160 .ndo_get_stats64 = ixgbe_get_stats64,
7161 #ifdef CONFIG_IXGBE_DCB
7162 .ndo_setup_tc = ixgbe_setup_tc,
7163 #endif
7164 #ifdef CONFIG_NET_POLL_CONTROLLER
7165 .ndo_poll_controller = ixgbe_netpoll,
7166 #endif
7167 #ifdef IXGBE_FCOE
7168 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7169 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7170 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7171 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7172 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7173 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7174 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7175 #endif /* IXGBE_FCOE */
7176 .ndo_set_features = ixgbe_set_features,
7177 .ndo_fix_features = ixgbe_fix_features,
7178 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7179 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7180 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7181 };
7182
7183 /**
7184 * ixgbe_wol_supported - Check whether device supports WoL
7185 * @hw: hw specific details
7186 * @device_id: the device ID
7187 * @subdev_id: the subsystem device ID
7188 *
7189 * This function is used by probe and ethtool to determine
7190 * which devices have WoL support
7191 *
7192 **/
7193 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7194 u16 subdevice_id)
7195 {
7196 struct ixgbe_hw *hw = &adapter->hw;
7197 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7198 int is_wol_supported = 0;
7199
7200 switch (device_id) {
7201 case IXGBE_DEV_ID_82599_SFP:
7202 /* Only these subdevices could supports WOL */
7203 switch (subdevice_id) {
7204 case IXGBE_SUBDEV_ID_82599_560FLR:
7205 /* only support first port */
7206 if (hw->bus.func != 0)
7207 break;
7208 case IXGBE_SUBDEV_ID_82599_SFP:
7209 case IXGBE_SUBDEV_ID_82599_RNDC:
7210 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7211 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
7212 is_wol_supported = 1;
7213 break;
7214 }
7215 break;
7216 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7217 /* All except this subdevice support WOL */
7218 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7219 is_wol_supported = 1;
7220 break;
7221 case IXGBE_DEV_ID_82599_KX4:
7222 is_wol_supported = 1;
7223 break;
7224 case IXGBE_DEV_ID_X540T:
7225 case IXGBE_DEV_ID_X540T1:
7226 /* check eeprom to see if enabled wol */
7227 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7228 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7229 (hw->bus.func == 0))) {
7230 is_wol_supported = 1;
7231 }
7232 break;
7233 }
7234
7235 return is_wol_supported;
7236 }
7237
7238 /**
7239 * ixgbe_probe - Device Initialization Routine
7240 * @pdev: PCI device information struct
7241 * @ent: entry in ixgbe_pci_tbl
7242 *
7243 * Returns 0 on success, negative on failure
7244 *
7245 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7246 * The OS initialization, configuring of the adapter private structure,
7247 * and a hardware reset occur.
7248 **/
7249 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7250 {
7251 struct net_device *netdev;
7252 struct ixgbe_adapter *adapter = NULL;
7253 struct ixgbe_hw *hw;
7254 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7255 static int cards_found;
7256 int i, err, pci_using_dac;
7257 unsigned int indices = MAX_TX_QUEUES;
7258 u8 part_str[IXGBE_PBANUM_LENGTH];
7259 #ifdef IXGBE_FCOE
7260 u16 device_caps;
7261 #endif
7262 u32 eec;
7263
7264 /* Catch broken hardware that put the wrong VF device ID in
7265 * the PCIe SR-IOV capability.
7266 */
7267 if (pdev->is_virtfn) {
7268 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7269 pci_name(pdev), pdev->vendor, pdev->device);
7270 return -EINVAL;
7271 }
7272
7273 err = pci_enable_device_mem(pdev);
7274 if (err)
7275 return err;
7276
7277 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7278 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7279 pci_using_dac = 1;
7280 } else {
7281 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7282 if (err) {
7283 err = dma_set_coherent_mask(&pdev->dev,
7284 DMA_BIT_MASK(32));
7285 if (err) {
7286 dev_err(&pdev->dev,
7287 "No usable DMA configuration, aborting\n");
7288 goto err_dma;
7289 }
7290 }
7291 pci_using_dac = 0;
7292 }
7293
7294 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7295 IORESOURCE_MEM), ixgbe_driver_name);
7296 if (err) {
7297 dev_err(&pdev->dev,
7298 "pci_request_selected_regions failed 0x%x\n", err);
7299 goto err_pci_reg;
7300 }
7301
7302 pci_enable_pcie_error_reporting(pdev);
7303
7304 pci_set_master(pdev);
7305 pci_save_state(pdev);
7306
7307 if (ii->mac == ixgbe_mac_82598EB) {
7308 #ifdef CONFIG_IXGBE_DCB
7309 /* 8 TC w/ 4 queues per TC */
7310 indices = 4 * MAX_TRAFFIC_CLASS;
7311 #else
7312 indices = IXGBE_MAX_RSS_INDICES;
7313 #endif
7314 }
7315
7316 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7317 if (!netdev) {
7318 err = -ENOMEM;
7319 goto err_alloc_etherdev;
7320 }
7321
7322 SET_NETDEV_DEV(netdev, &pdev->dev);
7323
7324 adapter = netdev_priv(netdev);
7325 pci_set_drvdata(pdev, adapter);
7326
7327 adapter->netdev = netdev;
7328 adapter->pdev = pdev;
7329 hw = &adapter->hw;
7330 hw->back = adapter;
7331 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7332
7333 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7334 pci_resource_len(pdev, 0));
7335 if (!hw->hw_addr) {
7336 err = -EIO;
7337 goto err_ioremap;
7338 }
7339
7340 netdev->netdev_ops = &ixgbe_netdev_ops;
7341 ixgbe_set_ethtool_ops(netdev);
7342 netdev->watchdog_timeo = 5 * HZ;
7343 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7344
7345 adapter->bd_number = cards_found;
7346
7347 /* Setup hw api */
7348 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7349 hw->mac.type = ii->mac;
7350
7351 /* EEPROM */
7352 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7353 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7354 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7355 if (!(eec & (1 << 8)))
7356 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7357
7358 /* PHY */
7359 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7360 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7361 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7362 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7363 hw->phy.mdio.mmds = 0;
7364 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7365 hw->phy.mdio.dev = netdev;
7366 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7367 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7368
7369 ii->get_invariants(hw);
7370
7371 /* setup the private structure */
7372 err = ixgbe_sw_init(adapter);
7373 if (err)
7374 goto err_sw_init;
7375
7376 /* Cache if MNG FW is up so we don't have to read the REG later */
7377 if (hw->mac.ops.mng_fw_enabled)
7378 hw->mng_fw_enabled = hw->mac.ops.mng_fw_enabled(hw);
7379
7380 /* Make it possible the adapter to be woken up via WOL */
7381 switch (adapter->hw.mac.type) {
7382 case ixgbe_mac_82599EB:
7383 case ixgbe_mac_X540:
7384 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7385 break;
7386 default:
7387 break;
7388 }
7389
7390 /*
7391 * If there is a fan on this device and it has failed log the
7392 * failure.
7393 */
7394 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7395 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7396 if (esdp & IXGBE_ESDP_SDP1)
7397 e_crit(probe, "Fan has stopped, replace the adapter\n");
7398 }
7399
7400 if (allow_unsupported_sfp)
7401 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7402
7403 /* reset_hw fills in the perm_addr as well */
7404 hw->phy.reset_if_overtemp = true;
7405 err = hw->mac.ops.reset_hw(hw);
7406 hw->phy.reset_if_overtemp = false;
7407 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7408 hw->mac.type == ixgbe_mac_82598EB) {
7409 err = 0;
7410 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7411 e_dev_err("failed to load because an unsupported SFP+ "
7412 "module type was detected.\n");
7413 e_dev_err("Reload the driver after installing a supported "
7414 "module.\n");
7415 goto err_sw_init;
7416 } else if (err) {
7417 e_dev_err("HW Init failed: %d\n", err);
7418 goto err_sw_init;
7419 }
7420
7421 #ifdef CONFIG_PCI_IOV
7422 /* SR-IOV not supported on the 82598 */
7423 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7424 goto skip_sriov;
7425 /* Mailbox */
7426 ixgbe_init_mbx_params_pf(hw);
7427 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
7428 ixgbe_enable_sriov(adapter);
7429 pci_sriov_set_totalvfs(pdev, 63);
7430 skip_sriov:
7431
7432 #endif
7433 netdev->features = NETIF_F_SG |
7434 NETIF_F_IP_CSUM |
7435 NETIF_F_IPV6_CSUM |
7436 NETIF_F_HW_VLAN_CTAG_TX |
7437 NETIF_F_HW_VLAN_CTAG_RX |
7438 NETIF_F_HW_VLAN_CTAG_FILTER |
7439 NETIF_F_TSO |
7440 NETIF_F_TSO6 |
7441 NETIF_F_RXHASH |
7442 NETIF_F_RXCSUM;
7443
7444 netdev->hw_features = netdev->features;
7445
7446 switch (adapter->hw.mac.type) {
7447 case ixgbe_mac_82599EB:
7448 case ixgbe_mac_X540:
7449 netdev->features |= NETIF_F_SCTP_CSUM;
7450 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7451 NETIF_F_NTUPLE;
7452 break;
7453 default:
7454 break;
7455 }
7456
7457 netdev->hw_features |= NETIF_F_RXALL;
7458
7459 netdev->vlan_features |= NETIF_F_TSO;
7460 netdev->vlan_features |= NETIF_F_TSO6;
7461 netdev->vlan_features |= NETIF_F_IP_CSUM;
7462 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7463 netdev->vlan_features |= NETIF_F_SG;
7464
7465 netdev->priv_flags |= IFF_UNICAST_FLT;
7466 netdev->priv_flags |= IFF_SUPP_NOFCS;
7467
7468 #ifdef CONFIG_IXGBE_DCB
7469 netdev->dcbnl_ops = &dcbnl_ops;
7470 #endif
7471
7472 #ifdef IXGBE_FCOE
7473 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7474 unsigned int fcoe_l;
7475
7476 if (hw->mac.ops.get_device_caps) {
7477 hw->mac.ops.get_device_caps(hw, &device_caps);
7478 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7479 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7480 }
7481
7482
7483 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
7484 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7485
7486 netdev->features |= NETIF_F_FSO |
7487 NETIF_F_FCOE_CRC;
7488
7489 netdev->vlan_features |= NETIF_F_FSO |
7490 NETIF_F_FCOE_CRC |
7491 NETIF_F_FCOE_MTU;
7492 }
7493 #endif /* IXGBE_FCOE */
7494 if (pci_using_dac) {
7495 netdev->features |= NETIF_F_HIGHDMA;
7496 netdev->vlan_features |= NETIF_F_HIGHDMA;
7497 }
7498
7499 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7500 netdev->hw_features |= NETIF_F_LRO;
7501 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7502 netdev->features |= NETIF_F_LRO;
7503
7504 /* make sure the EEPROM is good */
7505 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7506 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7507 err = -EIO;
7508 goto err_sw_init;
7509 }
7510
7511 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7512
7513 if (!is_valid_ether_addr(netdev->dev_addr)) {
7514 e_dev_err("invalid MAC address\n");
7515 err = -EIO;
7516 goto err_sw_init;
7517 }
7518
7519 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7520 (unsigned long) adapter);
7521
7522 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7523 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7524
7525 err = ixgbe_init_interrupt_scheme(adapter);
7526 if (err)
7527 goto err_sw_init;
7528
7529 /* WOL not supported for all devices */
7530 adapter->wol = 0;
7531 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7532 hw->wol_supported = ixgbe_wol_supported(adapter, pdev->device,
7533 pdev->subsystem_device);
7534 if (hw->wol_supported)
7535 adapter->wol = IXGBE_WUFC_MAG;
7536
7537 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7538
7539 /* save off EEPROM version number */
7540 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7541 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7542
7543 /* pick up the PCI bus settings for reporting later */
7544 hw->mac.ops.get_bus_info(hw);
7545 if (hw->device_id == IXGBE_DEV_ID_82599_SFP_SF_QP)
7546 ixgbe_get_parent_bus_info(adapter);
7547
7548 /* print bus type/speed/width info */
7549 e_dev_info("(PCI Express:%s:%s) %pM\n",
7550 (hw->bus.speed == ixgbe_bus_speed_8000 ? "8.0GT/s" :
7551 hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7552 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7553 "Unknown"),
7554 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7555 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7556 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7557 "Unknown"),
7558 netdev->dev_addr);
7559
7560 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7561 if (err)
7562 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7563 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7564 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7565 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7566 part_str);
7567 else
7568 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7569 hw->mac.type, hw->phy.type, part_str);
7570
7571 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7572 e_dev_warn("PCI-Express bandwidth available for this card is "
7573 "not sufficient for optimal performance.\n");
7574 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7575 "is required.\n");
7576 }
7577
7578 /* reset the hardware with the new settings */
7579 err = hw->mac.ops.start_hw(hw);
7580 if (err == IXGBE_ERR_EEPROM_VERSION) {
7581 /* We are running on a pre-production device, log a warning */
7582 e_dev_warn("This device is a pre-production adapter/LOM. "
7583 "Please be aware there may be issues associated "
7584 "with your hardware. If you are experiencing "
7585 "problems please contact your Intel or hardware "
7586 "representative who provided you with this "
7587 "hardware.\n");
7588 }
7589 strcpy(netdev->name, "eth%d");
7590 err = register_netdev(netdev);
7591 if (err)
7592 goto err_register;
7593
7594 /* power down the optics for 82599 SFP+ fiber */
7595 if (hw->mac.ops.disable_tx_laser)
7596 hw->mac.ops.disable_tx_laser(hw);
7597
7598 /* carrier off reporting is important to ethtool even BEFORE open */
7599 netif_carrier_off(netdev);
7600
7601 #ifdef CONFIG_IXGBE_DCA
7602 if (dca_add_requester(&pdev->dev) == 0) {
7603 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7604 ixgbe_setup_dca(adapter);
7605 }
7606 #endif
7607 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7608 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7609 for (i = 0; i < adapter->num_vfs; i++)
7610 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7611 }
7612
7613 /* firmware requires driver version to be 0xFFFFFFFF
7614 * since os does not support feature
7615 */
7616 if (hw->mac.ops.set_fw_drv_ver)
7617 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7618 0xFF);
7619
7620 /* add san mac addr to netdev */
7621 ixgbe_add_sanmac_netdev(netdev);
7622
7623 e_dev_info("%s\n", ixgbe_default_device_descr);
7624 cards_found++;
7625
7626 #ifdef CONFIG_IXGBE_HWMON
7627 if (ixgbe_sysfs_init(adapter))
7628 e_err(probe, "failed to allocate sysfs resources\n");
7629 #endif /* CONFIG_IXGBE_HWMON */
7630
7631 ixgbe_dbg_adapter_init(adapter);
7632
7633 /* Need link setup for MNG FW, else wait for IXGBE_UP */
7634 if (hw->mng_fw_enabled && hw->mac.ops.setup_link)
7635 hw->mac.ops.setup_link(hw,
7636 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
7637 true);
7638
7639 return 0;
7640
7641 err_register:
7642 ixgbe_release_hw_control(adapter);
7643 ixgbe_clear_interrupt_scheme(adapter);
7644 err_sw_init:
7645 ixgbe_disable_sriov(adapter);
7646 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7647 iounmap(hw->hw_addr);
7648 err_ioremap:
7649 free_netdev(netdev);
7650 err_alloc_etherdev:
7651 pci_release_selected_regions(pdev,
7652 pci_select_bars(pdev, IORESOURCE_MEM));
7653 err_pci_reg:
7654 err_dma:
7655 pci_disable_device(pdev);
7656 return err;
7657 }
7658
7659 /**
7660 * ixgbe_remove - Device Removal Routine
7661 * @pdev: PCI device information struct
7662 *
7663 * ixgbe_remove is called by the PCI subsystem to alert the driver
7664 * that it should release a PCI device. The could be caused by a
7665 * Hot-Plug event, or because the driver is going to be removed from
7666 * memory.
7667 **/
7668 static void ixgbe_remove(struct pci_dev *pdev)
7669 {
7670 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7671 struct net_device *netdev = adapter->netdev;
7672
7673 ixgbe_dbg_adapter_exit(adapter);
7674
7675 set_bit(__IXGBE_DOWN, &adapter->state);
7676 cancel_work_sync(&adapter->service_task);
7677
7678
7679 #ifdef CONFIG_IXGBE_DCA
7680 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7681 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7682 dca_remove_requester(&pdev->dev);
7683 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7684 }
7685
7686 #endif
7687 #ifdef CONFIG_IXGBE_HWMON
7688 ixgbe_sysfs_exit(adapter);
7689 #endif /* CONFIG_IXGBE_HWMON */
7690
7691 /* remove the added san mac */
7692 ixgbe_del_sanmac_netdev(netdev);
7693
7694 if (netdev->reg_state == NETREG_REGISTERED)
7695 unregister_netdev(netdev);
7696
7697 #ifdef CONFIG_PCI_IOV
7698 /*
7699 * Only disable SR-IOV on unload if the user specified the now
7700 * deprecated max_vfs module parameter.
7701 */
7702 if (max_vfs)
7703 ixgbe_disable_sriov(adapter);
7704 #endif
7705 ixgbe_clear_interrupt_scheme(adapter);
7706
7707 ixgbe_release_hw_control(adapter);
7708
7709 #ifdef CONFIG_DCB
7710 kfree(adapter->ixgbe_ieee_pfc);
7711 kfree(adapter->ixgbe_ieee_ets);
7712
7713 #endif
7714 iounmap(adapter->hw.hw_addr);
7715 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7716 IORESOURCE_MEM));
7717
7718 e_dev_info("complete\n");
7719
7720 free_netdev(netdev);
7721
7722 pci_disable_pcie_error_reporting(pdev);
7723
7724 pci_disable_device(pdev);
7725 }
7726
7727 /**
7728 * ixgbe_io_error_detected - called when PCI error is detected
7729 * @pdev: Pointer to PCI device
7730 * @state: The current pci connection state
7731 *
7732 * This function is called after a PCI bus error affecting
7733 * this device has been detected.
7734 */
7735 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7736 pci_channel_state_t state)
7737 {
7738 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7739 struct net_device *netdev = adapter->netdev;
7740
7741 #ifdef CONFIG_PCI_IOV
7742 struct pci_dev *bdev, *vfdev;
7743 u32 dw0, dw1, dw2, dw3;
7744 int vf, pos;
7745 u16 req_id, pf_func;
7746
7747 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7748 adapter->num_vfs == 0)
7749 goto skip_bad_vf_detection;
7750
7751 bdev = pdev->bus->self;
7752 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
7753 bdev = bdev->bus->self;
7754
7755 if (!bdev)
7756 goto skip_bad_vf_detection;
7757
7758 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7759 if (!pos)
7760 goto skip_bad_vf_detection;
7761
7762 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7763 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7764 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7765 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7766
7767 req_id = dw1 >> 16;
7768 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7769 if (!(req_id & 0x0080))
7770 goto skip_bad_vf_detection;
7771
7772 pf_func = req_id & 0x01;
7773 if ((pf_func & 1) == (pdev->devfn & 1)) {
7774 unsigned int device_id;
7775
7776 vf = (req_id & 0x7F) >> 1;
7777 e_dev_err("VF %d has caused a PCIe error\n", vf);
7778 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7779 "%8.8x\tdw3: %8.8x\n",
7780 dw0, dw1, dw2, dw3);
7781 switch (adapter->hw.mac.type) {
7782 case ixgbe_mac_82599EB:
7783 device_id = IXGBE_82599_VF_DEVICE_ID;
7784 break;
7785 case ixgbe_mac_X540:
7786 device_id = IXGBE_X540_VF_DEVICE_ID;
7787 break;
7788 default:
7789 device_id = 0;
7790 break;
7791 }
7792
7793 /* Find the pci device of the offending VF */
7794 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
7795 while (vfdev) {
7796 if (vfdev->devfn == (req_id & 0xFF))
7797 break;
7798 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
7799 device_id, vfdev);
7800 }
7801 /*
7802 * There's a slim chance the VF could have been hot plugged,
7803 * so if it is no longer present we don't need to issue the
7804 * VFLR. Just clean up the AER in that case.
7805 */
7806 if (vfdev) {
7807 e_dev_err("Issuing VFLR to VF %d\n", vf);
7808 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7809 /* Free device reference count */
7810 pci_dev_put(vfdev);
7811 }
7812
7813 pci_cleanup_aer_uncorrect_error_status(pdev);
7814 }
7815
7816 /*
7817 * Even though the error may have occurred on the other port
7818 * we still need to increment the vf error reference count for
7819 * both ports because the I/O resume function will be called
7820 * for both of them.
7821 */
7822 adapter->vferr_refcount++;
7823
7824 return PCI_ERS_RESULT_RECOVERED;
7825
7826 skip_bad_vf_detection:
7827 #endif /* CONFIG_PCI_IOV */
7828 netif_device_detach(netdev);
7829
7830 if (state == pci_channel_io_perm_failure)
7831 return PCI_ERS_RESULT_DISCONNECT;
7832
7833 if (netif_running(netdev))
7834 ixgbe_down(adapter);
7835 pci_disable_device(pdev);
7836
7837 /* Request a slot reset. */
7838 return PCI_ERS_RESULT_NEED_RESET;
7839 }
7840
7841 /**
7842 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7843 * @pdev: Pointer to PCI device
7844 *
7845 * Restart the card from scratch, as if from a cold-boot.
7846 */
7847 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7848 {
7849 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7850 pci_ers_result_t result;
7851 int err;
7852
7853 if (pci_enable_device_mem(pdev)) {
7854 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7855 result = PCI_ERS_RESULT_DISCONNECT;
7856 } else {
7857 pci_set_master(pdev);
7858 pci_restore_state(pdev);
7859 pci_save_state(pdev);
7860
7861 pci_wake_from_d3(pdev, false);
7862
7863 ixgbe_reset(adapter);
7864 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7865 result = PCI_ERS_RESULT_RECOVERED;
7866 }
7867
7868 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7869 if (err) {
7870 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7871 "failed 0x%0x\n", err);
7872 /* non-fatal, continue */
7873 }
7874
7875 return result;
7876 }
7877
7878 /**
7879 * ixgbe_io_resume - called when traffic can start flowing again.
7880 * @pdev: Pointer to PCI device
7881 *
7882 * This callback is called when the error recovery driver tells us that
7883 * its OK to resume normal operation.
7884 */
7885 static void ixgbe_io_resume(struct pci_dev *pdev)
7886 {
7887 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7888 struct net_device *netdev = adapter->netdev;
7889
7890 #ifdef CONFIG_PCI_IOV
7891 if (adapter->vferr_refcount) {
7892 e_info(drv, "Resuming after VF err\n");
7893 adapter->vferr_refcount--;
7894 return;
7895 }
7896
7897 #endif
7898 if (netif_running(netdev))
7899 ixgbe_up(adapter);
7900
7901 netif_device_attach(netdev);
7902 }
7903
7904 static const struct pci_error_handlers ixgbe_err_handler = {
7905 .error_detected = ixgbe_io_error_detected,
7906 .slot_reset = ixgbe_io_slot_reset,
7907 .resume = ixgbe_io_resume,
7908 };
7909
7910 static struct pci_driver ixgbe_driver = {
7911 .name = ixgbe_driver_name,
7912 .id_table = ixgbe_pci_tbl,
7913 .probe = ixgbe_probe,
7914 .remove = ixgbe_remove,
7915 #ifdef CONFIG_PM
7916 .suspend = ixgbe_suspend,
7917 .resume = ixgbe_resume,
7918 #endif
7919 .shutdown = ixgbe_shutdown,
7920 .sriov_configure = ixgbe_pci_sriov_configure,
7921 .err_handler = &ixgbe_err_handler
7922 };
7923
7924 /**
7925 * ixgbe_init_module - Driver Registration Routine
7926 *
7927 * ixgbe_init_module is the first routine called when the driver is
7928 * loaded. All it does is register with the PCI subsystem.
7929 **/
7930 static int __init ixgbe_init_module(void)
7931 {
7932 int ret;
7933 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7934 pr_info("%s\n", ixgbe_copyright);
7935
7936 ixgbe_dbg_init();
7937
7938 ret = pci_register_driver(&ixgbe_driver);
7939 if (ret) {
7940 ixgbe_dbg_exit();
7941 return ret;
7942 }
7943
7944 #ifdef CONFIG_IXGBE_DCA
7945 dca_register_notify(&dca_notifier);
7946 #endif
7947
7948 return 0;
7949 }
7950
7951 module_init(ixgbe_init_module);
7952
7953 /**
7954 * ixgbe_exit_module - Driver Exit Cleanup Routine
7955 *
7956 * ixgbe_exit_module is called just before the driver is removed
7957 * from memory.
7958 **/
7959 static void __exit ixgbe_exit_module(void)
7960 {
7961 #ifdef CONFIG_IXGBE_DCA
7962 dca_unregister_notify(&dca_notifier);
7963 #endif
7964 pci_unregister_driver(&ixgbe_driver);
7965
7966 ixgbe_dbg_exit();
7967
7968 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7969 }
7970
7971 #ifdef CONFIG_IXGBE_DCA
7972 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7973 void *p)
7974 {
7975 int ret_val;
7976
7977 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7978 __ixgbe_notify_dca);
7979
7980 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7981 }
7982
7983 #endif /* CONFIG_IXGBE_DCA */
7984
7985 module_exit(ixgbe_exit_module);
7986
7987 /* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)