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ixgbe: Add missing code for enabling overheat sensor interrupt
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
49
50 #include "ixgbe.h"
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
54
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
58 #define MAJ 3
59 #define MIN 4
60 #define BUILD 8
61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
62 __stringify(BUILD) "-k"
63 const char ixgbe_driver_version[] = DRV_VERSION;
64 static const char ixgbe_copyright[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
66
67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
68 [board_82598] = &ixgbe_82598_info,
69 [board_82599] = &ixgbe_82599_info,
70 [board_X540] = &ixgbe_X540_info,
71 };
72
73 /* ixgbe_pci_tbl - PCI Device ID Table
74 *
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
77 *
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
80 */
81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
108 /* required last entry */
109 {0, }
110 };
111 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
112
113 #ifdef CONFIG_IXGBE_DCA
114 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
115 void *p);
116 static struct notifier_block dca_notifier = {
117 .notifier_call = ixgbe_notify_dca,
118 .next = NULL,
119 .priority = 0
120 };
121 #endif
122
123 #ifdef CONFIG_PCI_IOV
124 static unsigned int max_vfs;
125 module_param(max_vfs, uint, 0);
126 MODULE_PARM_DESC(max_vfs,
127 "Maximum number of virtual functions to allocate per physical function");
128 #endif /* CONFIG_PCI_IOV */
129
130 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
131 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
132 MODULE_LICENSE("GPL");
133 MODULE_VERSION(DRV_VERSION);
134
135 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
136
137 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
138 {
139 struct ixgbe_hw *hw = &adapter->hw;
140 u32 gcr;
141 u32 gpie;
142 u32 vmdctl;
143
144 #ifdef CONFIG_PCI_IOV
145 /* disable iov and allow time for transactions to clear */
146 pci_disable_sriov(adapter->pdev);
147 #endif
148
149 /* turn off device IOV mode */
150 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
151 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
152 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
153 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
154 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
155 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
156
157 /* set default pool back to 0 */
158 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
159 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
160 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
161 IXGBE_WRITE_FLUSH(hw);
162
163 /* take a breather then clean up driver data */
164 msleep(100);
165
166 kfree(adapter->vfinfo);
167 adapter->vfinfo = NULL;
168
169 adapter->num_vfs = 0;
170 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
171 }
172
173 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
174 {
175 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
176 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
177 schedule_work(&adapter->service_task);
178 }
179
180 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
181 {
182 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
183
184 /* flush memory to make sure state is correct before next watchog */
185 smp_mb__before_clear_bit();
186 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
187 }
188
189 struct ixgbe_reg_info {
190 u32 ofs;
191 char *name;
192 };
193
194 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
195
196 /* General Registers */
197 {IXGBE_CTRL, "CTRL"},
198 {IXGBE_STATUS, "STATUS"},
199 {IXGBE_CTRL_EXT, "CTRL_EXT"},
200
201 /* Interrupt Registers */
202 {IXGBE_EICR, "EICR"},
203
204 /* RX Registers */
205 {IXGBE_SRRCTL(0), "SRRCTL"},
206 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
207 {IXGBE_RDLEN(0), "RDLEN"},
208 {IXGBE_RDH(0), "RDH"},
209 {IXGBE_RDT(0), "RDT"},
210 {IXGBE_RXDCTL(0), "RXDCTL"},
211 {IXGBE_RDBAL(0), "RDBAL"},
212 {IXGBE_RDBAH(0), "RDBAH"},
213
214 /* TX Registers */
215 {IXGBE_TDBAL(0), "TDBAL"},
216 {IXGBE_TDBAH(0), "TDBAH"},
217 {IXGBE_TDLEN(0), "TDLEN"},
218 {IXGBE_TDH(0), "TDH"},
219 {IXGBE_TDT(0), "TDT"},
220 {IXGBE_TXDCTL(0), "TXDCTL"},
221
222 /* List Terminator */
223 {}
224 };
225
226
227 /*
228 * ixgbe_regdump - register printout routine
229 */
230 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
231 {
232 int i = 0, j = 0;
233 char rname[16];
234 u32 regs[64];
235
236 switch (reginfo->ofs) {
237 case IXGBE_SRRCTL(0):
238 for (i = 0; i < 64; i++)
239 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
240 break;
241 case IXGBE_DCA_RXCTRL(0):
242 for (i = 0; i < 64; i++)
243 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
244 break;
245 case IXGBE_RDLEN(0):
246 for (i = 0; i < 64; i++)
247 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
248 break;
249 case IXGBE_RDH(0):
250 for (i = 0; i < 64; i++)
251 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
252 break;
253 case IXGBE_RDT(0):
254 for (i = 0; i < 64; i++)
255 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
256 break;
257 case IXGBE_RXDCTL(0):
258 for (i = 0; i < 64; i++)
259 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
260 break;
261 case IXGBE_RDBAL(0):
262 for (i = 0; i < 64; i++)
263 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
264 break;
265 case IXGBE_RDBAH(0):
266 for (i = 0; i < 64; i++)
267 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
268 break;
269 case IXGBE_TDBAL(0):
270 for (i = 0; i < 64; i++)
271 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
272 break;
273 case IXGBE_TDBAH(0):
274 for (i = 0; i < 64; i++)
275 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
276 break;
277 case IXGBE_TDLEN(0):
278 for (i = 0; i < 64; i++)
279 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
280 break;
281 case IXGBE_TDH(0):
282 for (i = 0; i < 64; i++)
283 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
284 break;
285 case IXGBE_TDT(0):
286 for (i = 0; i < 64; i++)
287 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
288 break;
289 case IXGBE_TXDCTL(0):
290 for (i = 0; i < 64; i++)
291 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
292 break;
293 default:
294 pr_info("%-15s %08x\n", reginfo->name,
295 IXGBE_READ_REG(hw, reginfo->ofs));
296 return;
297 }
298
299 for (i = 0; i < 8; i++) {
300 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
301 pr_err("%-15s", rname);
302 for (j = 0; j < 8; j++)
303 pr_cont(" %08x", regs[i*8+j]);
304 pr_cont("\n");
305 }
306
307 }
308
309 /*
310 * ixgbe_dump - Print registers, tx-rings and rx-rings
311 */
312 static void ixgbe_dump(struct ixgbe_adapter *adapter)
313 {
314 struct net_device *netdev = adapter->netdev;
315 struct ixgbe_hw *hw = &adapter->hw;
316 struct ixgbe_reg_info *reginfo;
317 int n = 0;
318 struct ixgbe_ring *tx_ring;
319 struct ixgbe_tx_buffer *tx_buffer_info;
320 union ixgbe_adv_tx_desc *tx_desc;
321 struct my_u0 { u64 a; u64 b; } *u0;
322 struct ixgbe_ring *rx_ring;
323 union ixgbe_adv_rx_desc *rx_desc;
324 struct ixgbe_rx_buffer *rx_buffer_info;
325 u32 staterr;
326 int i = 0;
327
328 if (!netif_msg_hw(adapter))
329 return;
330
331 /* Print netdevice Info */
332 if (netdev) {
333 dev_info(&adapter->pdev->dev, "Net device Info\n");
334 pr_info("Device Name state "
335 "trans_start last_rx\n");
336 pr_info("%-15s %016lX %016lX %016lX\n",
337 netdev->name,
338 netdev->state,
339 netdev->trans_start,
340 netdev->last_rx);
341 }
342
343 /* Print Registers */
344 dev_info(&adapter->pdev->dev, "Register Dump\n");
345 pr_info(" Register Name Value\n");
346 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
347 reginfo->name; reginfo++) {
348 ixgbe_regdump(hw, reginfo);
349 }
350
351 /* Print TX Ring Summary */
352 if (!netdev || !netif_running(netdev))
353 goto exit;
354
355 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
356 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
357 for (n = 0; n < adapter->num_tx_queues; n++) {
358 tx_ring = adapter->tx_ring[n];
359 tx_buffer_info =
360 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
361 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
362 n, tx_ring->next_to_use, tx_ring->next_to_clean,
363 (u64)tx_buffer_info->dma,
364 tx_buffer_info->length,
365 tx_buffer_info->next_to_watch,
366 (u64)tx_buffer_info->time_stamp);
367 }
368
369 /* Print TX Rings */
370 if (!netif_msg_tx_done(adapter))
371 goto rx_ring_summary;
372
373 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
374
375 /* Transmit Descriptor Formats
376 *
377 * Advanced Transmit Descriptor
378 * +--------------------------------------------------------------+
379 * 0 | Buffer Address [63:0] |
380 * +--------------------------------------------------------------+
381 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
382 * +--------------------------------------------------------------+
383 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
384 */
385
386 for (n = 0; n < adapter->num_tx_queues; n++) {
387 tx_ring = adapter->tx_ring[n];
388 pr_info("------------------------------------\n");
389 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
390 pr_info("------------------------------------\n");
391 pr_info("T [desc] [address 63:0 ] "
392 "[PlPOIdStDDt Ln] [bi->dma ] "
393 "leng ntw timestamp bi->skb\n");
394
395 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
396 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
397 tx_buffer_info = &tx_ring->tx_buffer_info[i];
398 u0 = (struct my_u0 *)tx_desc;
399 pr_info("T [0x%03X] %016llX %016llX %016llX"
400 " %04X %p %016llX %p", i,
401 le64_to_cpu(u0->a),
402 le64_to_cpu(u0->b),
403 (u64)tx_buffer_info->dma,
404 tx_buffer_info->length,
405 tx_buffer_info->next_to_watch,
406 (u64)tx_buffer_info->time_stamp,
407 tx_buffer_info->skb);
408 if (i == tx_ring->next_to_use &&
409 i == tx_ring->next_to_clean)
410 pr_cont(" NTC/U\n");
411 else if (i == tx_ring->next_to_use)
412 pr_cont(" NTU\n");
413 else if (i == tx_ring->next_to_clean)
414 pr_cont(" NTC\n");
415 else
416 pr_cont("\n");
417
418 if (netif_msg_pktdata(adapter) &&
419 tx_buffer_info->dma != 0)
420 print_hex_dump(KERN_INFO, "",
421 DUMP_PREFIX_ADDRESS, 16, 1,
422 phys_to_virt(tx_buffer_info->dma),
423 tx_buffer_info->length, true);
424 }
425 }
426
427 /* Print RX Rings Summary */
428 rx_ring_summary:
429 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
430 pr_info("Queue [NTU] [NTC]\n");
431 for (n = 0; n < adapter->num_rx_queues; n++) {
432 rx_ring = adapter->rx_ring[n];
433 pr_info("%5d %5X %5X\n",
434 n, rx_ring->next_to_use, rx_ring->next_to_clean);
435 }
436
437 /* Print RX Rings */
438 if (!netif_msg_rx_status(adapter))
439 goto exit;
440
441 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
442
443 /* Advanced Receive Descriptor (Read) Format
444 * 63 1 0
445 * +-----------------------------------------------------+
446 * 0 | Packet Buffer Address [63:1] |A0/NSE|
447 * +----------------------------------------------+------+
448 * 8 | Header Buffer Address [63:1] | DD |
449 * +-----------------------------------------------------+
450 *
451 *
452 * Advanced Receive Descriptor (Write-Back) Format
453 *
454 * 63 48 47 32 31 30 21 20 16 15 4 3 0
455 * +------------------------------------------------------+
456 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
457 * | Checksum Ident | | | | Type | Type |
458 * +------------------------------------------------------+
459 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
460 * +------------------------------------------------------+
461 * 63 48 47 32 31 20 19 0
462 */
463 for (n = 0; n < adapter->num_rx_queues; n++) {
464 rx_ring = adapter->rx_ring[n];
465 pr_info("------------------------------------\n");
466 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
467 pr_info("------------------------------------\n");
468 pr_info("R [desc] [ PktBuf A0] "
469 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
470 "<-- Adv Rx Read format\n");
471 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
472 "[vl er S cks ln] ---------------- [bi->skb] "
473 "<-- Adv Rx Write-Back format\n");
474
475 for (i = 0; i < rx_ring->count; i++) {
476 rx_buffer_info = &rx_ring->rx_buffer_info[i];
477 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
478 u0 = (struct my_u0 *)rx_desc;
479 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
480 if (staterr & IXGBE_RXD_STAT_DD) {
481 /* Descriptor Done */
482 pr_info("RWB[0x%03X] %016llX "
483 "%016llX ---------------- %p", i,
484 le64_to_cpu(u0->a),
485 le64_to_cpu(u0->b),
486 rx_buffer_info->skb);
487 } else {
488 pr_info("R [0x%03X] %016llX "
489 "%016llX %016llX %p", i,
490 le64_to_cpu(u0->a),
491 le64_to_cpu(u0->b),
492 (u64)rx_buffer_info->dma,
493 rx_buffer_info->skb);
494
495 if (netif_msg_pktdata(adapter)) {
496 print_hex_dump(KERN_INFO, "",
497 DUMP_PREFIX_ADDRESS, 16, 1,
498 phys_to_virt(rx_buffer_info->dma),
499 rx_ring->rx_buf_len, true);
500
501 if (rx_ring->rx_buf_len
502 < IXGBE_RXBUFFER_2048)
503 print_hex_dump(KERN_INFO, "",
504 DUMP_PREFIX_ADDRESS, 16, 1,
505 phys_to_virt(
506 rx_buffer_info->page_dma +
507 rx_buffer_info->page_offset
508 ),
509 PAGE_SIZE/2, true);
510 }
511 }
512
513 if (i == rx_ring->next_to_use)
514 pr_cont(" NTU\n");
515 else if (i == rx_ring->next_to_clean)
516 pr_cont(" NTC\n");
517 else
518 pr_cont("\n");
519
520 }
521 }
522
523 exit:
524 return;
525 }
526
527 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
528 {
529 u32 ctrl_ext;
530
531 /* Let firmware take over control of h/w */
532 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
534 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
535 }
536
537 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
538 {
539 u32 ctrl_ext;
540
541 /* Let firmware know the driver has taken over */
542 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
543 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
544 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
545 }
546
547 /*
548 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
549 * @adapter: pointer to adapter struct
550 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
551 * @queue: queue to map the corresponding interrupt to
552 * @msix_vector: the vector to map to the corresponding queue
553 *
554 */
555 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
556 u8 queue, u8 msix_vector)
557 {
558 u32 ivar, index;
559 struct ixgbe_hw *hw = &adapter->hw;
560 switch (hw->mac.type) {
561 case ixgbe_mac_82598EB:
562 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
563 if (direction == -1)
564 direction = 0;
565 index = (((direction * 64) + queue) >> 2) & 0x1F;
566 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
567 ivar &= ~(0xFF << (8 * (queue & 0x3)));
568 ivar |= (msix_vector << (8 * (queue & 0x3)));
569 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
570 break;
571 case ixgbe_mac_82599EB:
572 case ixgbe_mac_X540:
573 if (direction == -1) {
574 /* other causes */
575 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
576 index = ((queue & 1) * 8);
577 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
578 ivar &= ~(0xFF << index);
579 ivar |= (msix_vector << index);
580 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
581 break;
582 } else {
583 /* tx or rx causes */
584 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
585 index = ((16 * (queue & 1)) + (8 * direction));
586 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
587 ivar &= ~(0xFF << index);
588 ivar |= (msix_vector << index);
589 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
590 break;
591 }
592 default:
593 break;
594 }
595 }
596
597 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
598 u64 qmask)
599 {
600 u32 mask;
601
602 switch (adapter->hw.mac.type) {
603 case ixgbe_mac_82598EB:
604 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
606 break;
607 case ixgbe_mac_82599EB:
608 case ixgbe_mac_X540:
609 mask = (qmask & 0xFFFFFFFF);
610 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
611 mask = (qmask >> 32);
612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
613 break;
614 default:
615 break;
616 }
617 }
618
619 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
620 struct ixgbe_tx_buffer *tx_buffer)
621 {
622 if (tx_buffer->dma) {
623 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
624 dma_unmap_page(ring->dev,
625 tx_buffer->dma,
626 tx_buffer->length,
627 DMA_TO_DEVICE);
628 else
629 dma_unmap_single(ring->dev,
630 tx_buffer->dma,
631 tx_buffer->length,
632 DMA_TO_DEVICE);
633 }
634 tx_buffer->dma = 0;
635 }
636
637 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
638 struct ixgbe_tx_buffer *tx_buffer_info)
639 {
640 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
641 if (tx_buffer_info->skb)
642 dev_kfree_skb_any(tx_buffer_info->skb);
643 tx_buffer_info->skb = NULL;
644 /* tx_buffer_info must be completely set up in the transmit path */
645 }
646
647 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
648 {
649 struct ixgbe_hw *hw = &adapter->hw;
650 struct ixgbe_hw_stats *hwstats = &adapter->stats;
651 u32 data = 0;
652 u32 xoff[8] = {0};
653 int i;
654
655 if ((hw->fc.current_mode == ixgbe_fc_full) ||
656 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
657 switch (hw->mac.type) {
658 case ixgbe_mac_82598EB:
659 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
660 break;
661 default:
662 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
663 }
664 hwstats->lxoffrxc += data;
665
666 /* refill credits (no tx hang) if we received xoff */
667 if (!data)
668 return;
669
670 for (i = 0; i < adapter->num_tx_queues; i++)
671 clear_bit(__IXGBE_HANG_CHECK_ARMED,
672 &adapter->tx_ring[i]->state);
673 return;
674 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
675 return;
676
677 /* update stats for each tc, only valid with PFC enabled */
678 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
679 switch (hw->mac.type) {
680 case ixgbe_mac_82598EB:
681 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
682 break;
683 default:
684 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
685 }
686 hwstats->pxoffrxc[i] += xoff[i];
687 }
688
689 /* disarm tx queues that have received xoff frames */
690 for (i = 0; i < adapter->num_tx_queues; i++) {
691 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
692 u8 tc = tx_ring->dcb_tc;
693
694 if (xoff[tc])
695 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
696 }
697 }
698
699 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
700 {
701 return ring->tx_stats.completed;
702 }
703
704 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
705 {
706 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
707 struct ixgbe_hw *hw = &adapter->hw;
708
709 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
710 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
711
712 if (head != tail)
713 return (head < tail) ?
714 tail - head : (tail + ring->count - head);
715
716 return 0;
717 }
718
719 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
720 {
721 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
722 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
723 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
724 bool ret = false;
725
726 clear_check_for_tx_hang(tx_ring);
727
728 /*
729 * Check for a hung queue, but be thorough. This verifies
730 * that a transmit has been completed since the previous
731 * check AND there is at least one packet pending. The
732 * ARMED bit is set to indicate a potential hang. The
733 * bit is cleared if a pause frame is received to remove
734 * false hang detection due to PFC or 802.3x frames. By
735 * requiring this to fail twice we avoid races with
736 * pfc clearing the ARMED bit and conditions where we
737 * run the check_tx_hang logic with a transmit completion
738 * pending but without time to complete it yet.
739 */
740 if ((tx_done_old == tx_done) && tx_pending) {
741 /* make sure it is true for two checks in a row */
742 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
743 &tx_ring->state);
744 } else {
745 /* update completed stats and continue */
746 tx_ring->tx_stats.tx_done_old = tx_done;
747 /* reset the countdown */
748 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
749 }
750
751 return ret;
752 }
753
754 /**
755 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
756 * @adapter: driver private struct
757 **/
758 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
759 {
760
761 /* Do the reset outside of interrupt context */
762 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
763 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
764 ixgbe_service_event_schedule(adapter);
765 }
766 }
767
768 /**
769 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
770 * @q_vector: structure containing interrupt and ring information
771 * @tx_ring: tx ring to clean
772 **/
773 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
774 struct ixgbe_ring *tx_ring)
775 {
776 struct ixgbe_adapter *adapter = q_vector->adapter;
777 struct ixgbe_tx_buffer *tx_buffer;
778 union ixgbe_adv_tx_desc *tx_desc;
779 unsigned int total_bytes = 0, total_packets = 0;
780 unsigned int budget = q_vector->tx.work_limit;
781 u16 i = tx_ring->next_to_clean;
782
783 tx_buffer = &tx_ring->tx_buffer_info[i];
784 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
785
786 for (; budget; budget--) {
787 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
788
789 /* if next_to_watch is not set then there is no work pending */
790 if (!eop_desc)
791 break;
792
793 /* if DD is not set pending work has not been completed */
794 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
795 break;
796
797 /* count the packet as being completed */
798 tx_ring->tx_stats.completed++;
799
800 /* clear next_to_watch to prevent false hangs */
801 tx_buffer->next_to_watch = NULL;
802
803 /* prevent any other reads prior to eop_desc being verified */
804 rmb();
805
806 do {
807 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
808 tx_desc->wb.status = 0;
809 if (likely(tx_desc == eop_desc)) {
810 eop_desc = NULL;
811 dev_kfree_skb_any(tx_buffer->skb);
812 tx_buffer->skb = NULL;
813
814 total_bytes += tx_buffer->bytecount;
815 total_packets += tx_buffer->gso_segs;
816 }
817
818 tx_buffer++;
819 tx_desc++;
820 i++;
821 if (unlikely(i == tx_ring->count)) {
822 i = 0;
823
824 tx_buffer = tx_ring->tx_buffer_info;
825 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
826 }
827
828 } while (eop_desc);
829 }
830
831 tx_ring->next_to_clean = i;
832 u64_stats_update_begin(&tx_ring->syncp);
833 tx_ring->stats.bytes += total_bytes;
834 tx_ring->stats.packets += total_packets;
835 u64_stats_update_end(&tx_ring->syncp);
836 q_vector->tx.total_bytes += total_bytes;
837 q_vector->tx.total_packets += total_packets;
838
839 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
840 /* schedule immediate reset if we believe we hung */
841 struct ixgbe_hw *hw = &adapter->hw;
842 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
843 e_err(drv, "Detected Tx Unit Hang\n"
844 " Tx Queue <%d>\n"
845 " TDH, TDT <%x>, <%x>\n"
846 " next_to_use <%x>\n"
847 " next_to_clean <%x>\n"
848 "tx_buffer_info[next_to_clean]\n"
849 " time_stamp <%lx>\n"
850 " jiffies <%lx>\n",
851 tx_ring->queue_index,
852 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
853 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
854 tx_ring->next_to_use, i,
855 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
856
857 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
858
859 e_info(probe,
860 "tx hang %d detected on queue %d, resetting adapter\n",
861 adapter->tx_timeout_count + 1, tx_ring->queue_index);
862
863 /* schedule immediate reset if we believe we hung */
864 ixgbe_tx_timeout_reset(adapter);
865
866 /* the adapter is about to reset, no point in enabling stuff */
867 return true;
868 }
869
870 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
871 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
872 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
873 /* Make sure that anybody stopping the queue after this
874 * sees the new next_to_clean.
875 */
876 smp_mb();
877 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
878 !test_bit(__IXGBE_DOWN, &adapter->state)) {
879 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
880 ++tx_ring->tx_stats.restart_queue;
881 }
882 }
883
884 return !!budget;
885 }
886
887 #ifdef CONFIG_IXGBE_DCA
888 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
889 struct ixgbe_ring *rx_ring,
890 int cpu)
891 {
892 struct ixgbe_hw *hw = &adapter->hw;
893 u32 rxctrl;
894 u8 reg_idx = rx_ring->reg_idx;
895
896 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
897 switch (hw->mac.type) {
898 case ixgbe_mac_82598EB:
899 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
900 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
901 break;
902 case ixgbe_mac_82599EB:
903 case ixgbe_mac_X540:
904 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
905 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
906 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
907 break;
908 default:
909 break;
910 }
911 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
912 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
913 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
914 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
915 }
916
917 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
918 struct ixgbe_ring *tx_ring,
919 int cpu)
920 {
921 struct ixgbe_hw *hw = &adapter->hw;
922 u32 txctrl;
923 u8 reg_idx = tx_ring->reg_idx;
924
925 switch (hw->mac.type) {
926 case ixgbe_mac_82598EB:
927 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
928 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
929 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
930 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
931 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
932 break;
933 case ixgbe_mac_82599EB:
934 case ixgbe_mac_X540:
935 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
936 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
937 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
938 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
939 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
940 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
941 break;
942 default:
943 break;
944 }
945 }
946
947 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
948 {
949 struct ixgbe_adapter *adapter = q_vector->adapter;
950 struct ixgbe_ring *ring;
951 int cpu = get_cpu();
952
953 if (q_vector->cpu == cpu)
954 goto out_no_update;
955
956 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
957 ixgbe_update_tx_dca(adapter, ring, cpu);
958
959 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
960 ixgbe_update_rx_dca(adapter, ring, cpu);
961
962 q_vector->cpu = cpu;
963 out_no_update:
964 put_cpu();
965 }
966
967 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
968 {
969 int num_q_vectors;
970 int i;
971
972 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
973 return;
974
975 /* always use CB2 mode, difference is masked in the CB driver */
976 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
977
978 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
979 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
980 else
981 num_q_vectors = 1;
982
983 for (i = 0; i < num_q_vectors; i++) {
984 adapter->q_vector[i]->cpu = -1;
985 ixgbe_update_dca(adapter->q_vector[i]);
986 }
987 }
988
989 static int __ixgbe_notify_dca(struct device *dev, void *data)
990 {
991 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
992 unsigned long event = *(unsigned long *)data;
993
994 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
995 return 0;
996
997 switch (event) {
998 case DCA_PROVIDER_ADD:
999 /* if we're already enabled, don't do it again */
1000 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1001 break;
1002 if (dca_add_requester(dev) == 0) {
1003 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1004 ixgbe_setup_dca(adapter);
1005 break;
1006 }
1007 /* Fall Through since DCA is disabled. */
1008 case DCA_PROVIDER_REMOVE:
1009 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1010 dca_remove_requester(dev);
1011 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1012 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1013 }
1014 break;
1015 }
1016
1017 return 0;
1018 }
1019 #endif /* CONFIG_IXGBE_DCA */
1020
1021 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1022 struct sk_buff *skb)
1023 {
1024 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1025 }
1026
1027 /**
1028 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1029 * @adapter: address of board private structure
1030 * @rx_desc: advanced rx descriptor
1031 *
1032 * Returns : true if it is FCoE pkt
1033 */
1034 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1035 union ixgbe_adv_rx_desc *rx_desc)
1036 {
1037 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1038
1039 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1040 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1041 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1042 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1043 }
1044
1045 /**
1046 * ixgbe_receive_skb - Send a completed packet up the stack
1047 * @adapter: board private structure
1048 * @skb: packet to send up
1049 * @status: hardware indication of status of receive
1050 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1051 * @rx_desc: rx descriptor
1052 **/
1053 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1054 struct sk_buff *skb, u8 status,
1055 struct ixgbe_ring *ring,
1056 union ixgbe_adv_rx_desc *rx_desc)
1057 {
1058 struct ixgbe_adapter *adapter = q_vector->adapter;
1059 struct napi_struct *napi = &q_vector->napi;
1060 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1061 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1062
1063 if (is_vlan && (tag & VLAN_VID_MASK))
1064 __vlan_hwaccel_put_tag(skb, tag);
1065
1066 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1067 napi_gro_receive(napi, skb);
1068 else
1069 netif_rx(skb);
1070 }
1071
1072 /**
1073 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1074 * @adapter: address of board private structure
1075 * @status_err: hardware indication of status of receive
1076 * @skb: skb currently being received and modified
1077 * @status_err: status error value of last descriptor in packet
1078 **/
1079 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1080 union ixgbe_adv_rx_desc *rx_desc,
1081 struct sk_buff *skb,
1082 u32 status_err)
1083 {
1084 skb->ip_summed = CHECKSUM_NONE;
1085
1086 /* Rx csum disabled */
1087 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1088 return;
1089
1090 /* if IP and error */
1091 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1092 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1093 adapter->hw_csum_rx_error++;
1094 return;
1095 }
1096
1097 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1098 return;
1099
1100 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1101 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1102
1103 /*
1104 * 82599 errata, UDP frames with a 0 checksum can be marked as
1105 * checksum errors.
1106 */
1107 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1108 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1109 return;
1110
1111 adapter->hw_csum_rx_error++;
1112 return;
1113 }
1114
1115 /* It must be a TCP or UDP packet with a valid checksum */
1116 skb->ip_summed = CHECKSUM_UNNECESSARY;
1117 }
1118
1119 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1120 {
1121 /*
1122 * Force memory writes to complete before letting h/w
1123 * know there are new descriptors to fetch. (Only
1124 * applicable for weak-ordered memory model archs,
1125 * such as IA-64).
1126 */
1127 wmb();
1128 writel(val, rx_ring->tail);
1129 }
1130
1131 /**
1132 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1133 * @rx_ring: ring to place buffers on
1134 * @cleaned_count: number of buffers to replace
1135 **/
1136 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1137 {
1138 union ixgbe_adv_rx_desc *rx_desc;
1139 struct ixgbe_rx_buffer *bi;
1140 struct sk_buff *skb;
1141 u16 i = rx_ring->next_to_use;
1142
1143 /* do nothing if no valid netdev defined */
1144 if (!rx_ring->netdev)
1145 return;
1146
1147 while (cleaned_count--) {
1148 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1149 bi = &rx_ring->rx_buffer_info[i];
1150 skb = bi->skb;
1151
1152 if (!skb) {
1153 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1154 rx_ring->rx_buf_len);
1155 if (!skb) {
1156 rx_ring->rx_stats.alloc_rx_buff_failed++;
1157 goto no_buffers;
1158 }
1159 /* initialize queue mapping */
1160 skb_record_rx_queue(skb, rx_ring->queue_index);
1161 bi->skb = skb;
1162 }
1163
1164 if (!bi->dma) {
1165 bi->dma = dma_map_single(rx_ring->dev,
1166 skb->data,
1167 rx_ring->rx_buf_len,
1168 DMA_FROM_DEVICE);
1169 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1170 rx_ring->rx_stats.alloc_rx_buff_failed++;
1171 bi->dma = 0;
1172 goto no_buffers;
1173 }
1174 }
1175
1176 if (ring_is_ps_enabled(rx_ring)) {
1177 if (!bi->page) {
1178 bi->page = netdev_alloc_page(rx_ring->netdev);
1179 if (!bi->page) {
1180 rx_ring->rx_stats.alloc_rx_page_failed++;
1181 goto no_buffers;
1182 }
1183 }
1184
1185 if (!bi->page_dma) {
1186 /* use a half page if we're re-using */
1187 bi->page_offset ^= PAGE_SIZE / 2;
1188 bi->page_dma = dma_map_page(rx_ring->dev,
1189 bi->page,
1190 bi->page_offset,
1191 PAGE_SIZE / 2,
1192 DMA_FROM_DEVICE);
1193 if (dma_mapping_error(rx_ring->dev,
1194 bi->page_dma)) {
1195 rx_ring->rx_stats.alloc_rx_page_failed++;
1196 bi->page_dma = 0;
1197 goto no_buffers;
1198 }
1199 }
1200
1201 /* Refresh the desc even if buffer_addrs didn't change
1202 * because each write-back erases this info. */
1203 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1204 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1205 } else {
1206 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1207 rx_desc->read.hdr_addr = 0;
1208 }
1209
1210 i++;
1211 if (i == rx_ring->count)
1212 i = 0;
1213 }
1214
1215 no_buffers:
1216 if (rx_ring->next_to_use != i) {
1217 rx_ring->next_to_use = i;
1218 ixgbe_release_rx_desc(rx_ring, i);
1219 }
1220 }
1221
1222 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1223 {
1224 /* HW will not DMA in data larger than the given buffer, even if it
1225 * parses the (NFS, of course) header to be larger. In that case, it
1226 * fills the header buffer and spills the rest into the page.
1227 */
1228 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1229 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1230 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1231 if (hlen > IXGBE_RX_HDR_SIZE)
1232 hlen = IXGBE_RX_HDR_SIZE;
1233 return hlen;
1234 }
1235
1236 /**
1237 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1238 * @skb: pointer to the last skb in the rsc queue
1239 *
1240 * This function changes a queue full of hw rsc buffers into a completed
1241 * packet. It uses the ->prev pointers to find the first packet and then
1242 * turns it into the frag list owner.
1243 **/
1244 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1245 {
1246 unsigned int frag_list_size = 0;
1247 unsigned int skb_cnt = 1;
1248
1249 while (skb->prev) {
1250 struct sk_buff *prev = skb->prev;
1251 frag_list_size += skb->len;
1252 skb->prev = NULL;
1253 skb = prev;
1254 skb_cnt++;
1255 }
1256
1257 skb_shinfo(skb)->frag_list = skb->next;
1258 skb->next = NULL;
1259 skb->len += frag_list_size;
1260 skb->data_len += frag_list_size;
1261 skb->truesize += frag_list_size;
1262 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1263
1264 return skb;
1265 }
1266
1267 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1268 {
1269 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1270 IXGBE_RXDADV_RSCCNT_MASK);
1271 }
1272
1273 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1274 struct ixgbe_ring *rx_ring,
1275 int budget)
1276 {
1277 struct ixgbe_adapter *adapter = q_vector->adapter;
1278 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1279 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1280 struct sk_buff *skb;
1281 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1282 const int current_node = numa_node_id();
1283 #ifdef IXGBE_FCOE
1284 int ddp_bytes = 0;
1285 #endif /* IXGBE_FCOE */
1286 u32 staterr;
1287 u16 i;
1288 u16 cleaned_count = 0;
1289 bool pkt_is_rsc = false;
1290
1291 i = rx_ring->next_to_clean;
1292 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1293 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1294
1295 while (staterr & IXGBE_RXD_STAT_DD) {
1296 u32 upper_len = 0;
1297
1298 rmb(); /* read descriptor and rx_buffer_info after status DD */
1299
1300 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1301
1302 skb = rx_buffer_info->skb;
1303 rx_buffer_info->skb = NULL;
1304 prefetch(skb->data);
1305
1306 if (ring_is_rsc_enabled(rx_ring))
1307 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1308
1309 /* if this is a skb from previous receive DMA will be 0 */
1310 if (rx_buffer_info->dma) {
1311 u16 hlen;
1312 if (pkt_is_rsc &&
1313 !(staterr & IXGBE_RXD_STAT_EOP) &&
1314 !skb->prev) {
1315 /*
1316 * When HWRSC is enabled, delay unmapping
1317 * of the first packet. It carries the
1318 * header information, HW may still
1319 * access the header after the writeback.
1320 * Only unmap it when EOP is reached
1321 */
1322 IXGBE_RSC_CB(skb)->delay_unmap = true;
1323 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1324 } else {
1325 dma_unmap_single(rx_ring->dev,
1326 rx_buffer_info->dma,
1327 rx_ring->rx_buf_len,
1328 DMA_FROM_DEVICE);
1329 }
1330 rx_buffer_info->dma = 0;
1331
1332 if (ring_is_ps_enabled(rx_ring)) {
1333 hlen = ixgbe_get_hlen(rx_desc);
1334 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1335 } else {
1336 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1337 }
1338
1339 skb_put(skb, hlen);
1340 } else {
1341 /* assume packet split since header is unmapped */
1342 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1343 }
1344
1345 if (upper_len) {
1346 dma_unmap_page(rx_ring->dev,
1347 rx_buffer_info->page_dma,
1348 PAGE_SIZE / 2,
1349 DMA_FROM_DEVICE);
1350 rx_buffer_info->page_dma = 0;
1351 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1352 rx_buffer_info->page,
1353 rx_buffer_info->page_offset,
1354 upper_len);
1355
1356 if ((page_count(rx_buffer_info->page) == 1) &&
1357 (page_to_nid(rx_buffer_info->page) == current_node))
1358 get_page(rx_buffer_info->page);
1359 else
1360 rx_buffer_info->page = NULL;
1361
1362 skb->len += upper_len;
1363 skb->data_len += upper_len;
1364 skb->truesize += upper_len;
1365 }
1366
1367 i++;
1368 if (i == rx_ring->count)
1369 i = 0;
1370
1371 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1372 prefetch(next_rxd);
1373 cleaned_count++;
1374
1375 if (pkt_is_rsc) {
1376 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1377 IXGBE_RXDADV_NEXTP_SHIFT;
1378 next_buffer = &rx_ring->rx_buffer_info[nextp];
1379 } else {
1380 next_buffer = &rx_ring->rx_buffer_info[i];
1381 }
1382
1383 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1384 if (ring_is_ps_enabled(rx_ring)) {
1385 rx_buffer_info->skb = next_buffer->skb;
1386 rx_buffer_info->dma = next_buffer->dma;
1387 next_buffer->skb = skb;
1388 next_buffer->dma = 0;
1389 } else {
1390 skb->next = next_buffer->skb;
1391 skb->next->prev = skb;
1392 }
1393 rx_ring->rx_stats.non_eop_descs++;
1394 goto next_desc;
1395 }
1396
1397 if (skb->prev) {
1398 skb = ixgbe_transform_rsc_queue(skb);
1399 /* if we got here without RSC the packet is invalid */
1400 if (!pkt_is_rsc) {
1401 __pskb_trim(skb, 0);
1402 rx_buffer_info->skb = skb;
1403 goto next_desc;
1404 }
1405 }
1406
1407 if (ring_is_rsc_enabled(rx_ring)) {
1408 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1409 dma_unmap_single(rx_ring->dev,
1410 IXGBE_RSC_CB(skb)->dma,
1411 rx_ring->rx_buf_len,
1412 DMA_FROM_DEVICE);
1413 IXGBE_RSC_CB(skb)->dma = 0;
1414 IXGBE_RSC_CB(skb)->delay_unmap = false;
1415 }
1416 }
1417 if (pkt_is_rsc) {
1418 if (ring_is_ps_enabled(rx_ring))
1419 rx_ring->rx_stats.rsc_count +=
1420 skb_shinfo(skb)->nr_frags;
1421 else
1422 rx_ring->rx_stats.rsc_count +=
1423 IXGBE_RSC_CB(skb)->skb_cnt;
1424 rx_ring->rx_stats.rsc_flush++;
1425 }
1426
1427 /* ERR_MASK will only have valid bits if EOP set */
1428 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1429 dev_kfree_skb_any(skb);
1430 goto next_desc;
1431 }
1432
1433 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1434 if (adapter->netdev->features & NETIF_F_RXHASH)
1435 ixgbe_rx_hash(rx_desc, skb);
1436
1437 /* probably a little skewed due to removing CRC */
1438 total_rx_bytes += skb->len;
1439 total_rx_packets++;
1440
1441 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1442 #ifdef IXGBE_FCOE
1443 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1444 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1445 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1446 staterr);
1447 if (!ddp_bytes) {
1448 dev_kfree_skb_any(skb);
1449 goto next_desc;
1450 }
1451 }
1452 #endif /* IXGBE_FCOE */
1453 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1454
1455 budget--;
1456 next_desc:
1457 rx_desc->wb.upper.status_error = 0;
1458
1459 if (!budget)
1460 break;
1461
1462 /* return some buffers to hardware, one at a time is too slow */
1463 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1464 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1465 cleaned_count = 0;
1466 }
1467
1468 /* use prefetched values */
1469 rx_desc = next_rxd;
1470 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1471 }
1472
1473 rx_ring->next_to_clean = i;
1474 cleaned_count = ixgbe_desc_unused(rx_ring);
1475
1476 if (cleaned_count)
1477 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1478
1479 #ifdef IXGBE_FCOE
1480 /* include DDPed FCoE data */
1481 if (ddp_bytes > 0) {
1482 unsigned int mss;
1483
1484 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1485 sizeof(struct fc_frame_header) -
1486 sizeof(struct fcoe_crc_eof);
1487 if (mss > 512)
1488 mss &= ~511;
1489 total_rx_bytes += ddp_bytes;
1490 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1491 }
1492 #endif /* IXGBE_FCOE */
1493
1494 u64_stats_update_begin(&rx_ring->syncp);
1495 rx_ring->stats.packets += total_rx_packets;
1496 rx_ring->stats.bytes += total_rx_bytes;
1497 u64_stats_update_end(&rx_ring->syncp);
1498 q_vector->rx.total_packets += total_rx_packets;
1499 q_vector->rx.total_bytes += total_rx_bytes;
1500
1501 return !!budget;
1502 }
1503
1504 /**
1505 * ixgbe_configure_msix - Configure MSI-X hardware
1506 * @adapter: board private structure
1507 *
1508 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1509 * interrupts.
1510 **/
1511 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1512 {
1513 struct ixgbe_q_vector *q_vector;
1514 int q_vectors, v_idx;
1515 u32 mask;
1516
1517 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1518
1519 /* Populate MSIX to EITR Select */
1520 if (adapter->num_vfs > 32) {
1521 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1522 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1523 }
1524
1525 /*
1526 * Populate the IVAR table and set the ITR values to the
1527 * corresponding register.
1528 */
1529 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1530 struct ixgbe_ring *ring;
1531 q_vector = adapter->q_vector[v_idx];
1532
1533 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1534 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1535
1536 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1537 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1538
1539 if (q_vector->tx.ring && !q_vector->rx.ring)
1540 /* tx only */
1541 q_vector->eitr = adapter->tx_eitr_param;
1542 else if (q_vector->rx.ring)
1543 /* rx or mixed */
1544 q_vector->eitr = adapter->rx_eitr_param;
1545
1546 ixgbe_write_eitr(q_vector);
1547 }
1548
1549 switch (adapter->hw.mac.type) {
1550 case ixgbe_mac_82598EB:
1551 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1552 v_idx);
1553 break;
1554 case ixgbe_mac_82599EB:
1555 case ixgbe_mac_X540:
1556 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1557 break;
1558
1559 default:
1560 break;
1561 }
1562 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1563
1564 /* set up to autoclear timer, and the vectors */
1565 mask = IXGBE_EIMS_ENABLE_MASK;
1566 if (adapter->num_vfs)
1567 mask &= ~(IXGBE_EIMS_OTHER |
1568 IXGBE_EIMS_MAILBOX |
1569 IXGBE_EIMS_LSC);
1570 else
1571 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1572 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1573 }
1574
1575 enum latency_range {
1576 lowest_latency = 0,
1577 low_latency = 1,
1578 bulk_latency = 2,
1579 latency_invalid = 255
1580 };
1581
1582 /**
1583 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1584 * @q_vector: structure containing interrupt and ring information
1585 * @ring_container: structure containing ring performance data
1586 *
1587 * Stores a new ITR value based on packets and byte
1588 * counts during the last interrupt. The advantage of per interrupt
1589 * computation is faster updates and more accurate ITR for the current
1590 * traffic pattern. Constants in this function were computed
1591 * based on theoretical maximum wire speed and thresholds were set based
1592 * on testing data as well as attempting to minimize response time
1593 * while increasing bulk throughput.
1594 * this functionality is controlled by the InterruptThrottleRate module
1595 * parameter (see ixgbe_param.c)
1596 **/
1597 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1598 struct ixgbe_ring_container *ring_container)
1599 {
1600 u64 bytes_perint;
1601 struct ixgbe_adapter *adapter = q_vector->adapter;
1602 int bytes = ring_container->total_bytes;
1603 int packets = ring_container->total_packets;
1604 u32 timepassed_us;
1605 u8 itr_setting = ring_container->itr;
1606
1607 if (packets == 0)
1608 return;
1609
1610 /* simple throttlerate management
1611 * 0-20MB/s lowest (100000 ints/s)
1612 * 20-100MB/s low (20000 ints/s)
1613 * 100-1249MB/s bulk (8000 ints/s)
1614 */
1615 /* what was last interrupt timeslice? */
1616 timepassed_us = 1000000/q_vector->eitr;
1617 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1618
1619 switch (itr_setting) {
1620 case lowest_latency:
1621 if (bytes_perint > adapter->eitr_low)
1622 itr_setting = low_latency;
1623 break;
1624 case low_latency:
1625 if (bytes_perint > adapter->eitr_high)
1626 itr_setting = bulk_latency;
1627 else if (bytes_perint <= adapter->eitr_low)
1628 itr_setting = lowest_latency;
1629 break;
1630 case bulk_latency:
1631 if (bytes_perint <= adapter->eitr_high)
1632 itr_setting = low_latency;
1633 break;
1634 }
1635
1636 /* clear work counters since we have the values we need */
1637 ring_container->total_bytes = 0;
1638 ring_container->total_packets = 0;
1639
1640 /* write updated itr to ring container */
1641 ring_container->itr = itr_setting;
1642 }
1643
1644 /**
1645 * ixgbe_write_eitr - write EITR register in hardware specific way
1646 * @q_vector: structure containing interrupt and ring information
1647 *
1648 * This function is made to be called by ethtool and by the driver
1649 * when it needs to update EITR registers at runtime. Hardware
1650 * specific quirks/differences are taken care of here.
1651 */
1652 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1653 {
1654 struct ixgbe_adapter *adapter = q_vector->adapter;
1655 struct ixgbe_hw *hw = &adapter->hw;
1656 int v_idx = q_vector->v_idx;
1657 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1658
1659 switch (adapter->hw.mac.type) {
1660 case ixgbe_mac_82598EB:
1661 /* must write high and low 16 bits to reset counter */
1662 itr_reg |= (itr_reg << 16);
1663 break;
1664 case ixgbe_mac_82599EB:
1665 case ixgbe_mac_X540:
1666 /*
1667 * 82599 and X540 can support a value of zero, so allow it for
1668 * max interrupt rate, but there is an errata where it can
1669 * not be zero with RSC
1670 */
1671 if (itr_reg == 8 &&
1672 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1673 itr_reg = 0;
1674
1675 /*
1676 * set the WDIS bit to not clear the timer bits and cause an
1677 * immediate assertion of the interrupt
1678 */
1679 itr_reg |= IXGBE_EITR_CNT_WDIS;
1680 break;
1681 default:
1682 break;
1683 }
1684 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1685 }
1686
1687 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1688 {
1689 u32 new_itr = q_vector->eitr;
1690 u8 current_itr;
1691
1692 ixgbe_update_itr(q_vector, &q_vector->tx);
1693 ixgbe_update_itr(q_vector, &q_vector->rx);
1694
1695 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1696
1697 switch (current_itr) {
1698 /* counts and packets in update_itr are dependent on these numbers */
1699 case lowest_latency:
1700 new_itr = 100000;
1701 break;
1702 case low_latency:
1703 new_itr = 20000; /* aka hwitr = ~200 */
1704 break;
1705 case bulk_latency:
1706 new_itr = 8000;
1707 break;
1708 default:
1709 break;
1710 }
1711
1712 if (new_itr != q_vector->eitr) {
1713 /* do an exponential smoothing */
1714 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1715
1716 /* save the algorithm value here */
1717 q_vector->eitr = new_itr;
1718
1719 ixgbe_write_eitr(q_vector);
1720 }
1721 }
1722
1723 /**
1724 * ixgbe_check_overtemp_subtask - check for over tempurature
1725 * @adapter: pointer to adapter
1726 **/
1727 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1728 {
1729 struct ixgbe_hw *hw = &adapter->hw;
1730 u32 eicr = adapter->interrupt_event;
1731
1732 if (test_bit(__IXGBE_DOWN, &adapter->state))
1733 return;
1734
1735 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1736 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1737 return;
1738
1739 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1740
1741 switch (hw->device_id) {
1742 case IXGBE_DEV_ID_82599_T3_LOM:
1743 /*
1744 * Since the warning interrupt is for both ports
1745 * we don't have to check if:
1746 * - This interrupt wasn't for our port.
1747 * - We may have missed the interrupt so always have to
1748 * check if we got a LSC
1749 */
1750 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1751 !(eicr & IXGBE_EICR_LSC))
1752 return;
1753
1754 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1755 u32 autoneg;
1756 bool link_up = false;
1757
1758 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1759
1760 if (link_up)
1761 return;
1762 }
1763
1764 /* Check if this is not due to overtemp */
1765 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1766 return;
1767
1768 break;
1769 default:
1770 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1771 return;
1772 break;
1773 }
1774 e_crit(drv,
1775 "Network adapter has been stopped because it has over heated. "
1776 "Restart the computer. If the problem persists, "
1777 "power off the system and replace the adapter\n");
1778
1779 adapter->interrupt_event = 0;
1780 }
1781
1782 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1783 {
1784 struct ixgbe_hw *hw = &adapter->hw;
1785
1786 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1787 (eicr & IXGBE_EICR_GPI_SDP1)) {
1788 e_crit(probe, "Fan has stopped, replace the adapter\n");
1789 /* write to clear the interrupt */
1790 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1791 }
1792 }
1793
1794 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1795 {
1796 struct ixgbe_hw *hw = &adapter->hw;
1797
1798 if (eicr & IXGBE_EICR_GPI_SDP2) {
1799 /* Clear the interrupt */
1800 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1801 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1802 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1803 ixgbe_service_event_schedule(adapter);
1804 }
1805 }
1806
1807 if (eicr & IXGBE_EICR_GPI_SDP1) {
1808 /* Clear the interrupt */
1809 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1810 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1811 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1812 ixgbe_service_event_schedule(adapter);
1813 }
1814 }
1815 }
1816
1817 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1818 {
1819 struct ixgbe_hw *hw = &adapter->hw;
1820
1821 adapter->lsc_int++;
1822 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1823 adapter->link_check_timeout = jiffies;
1824 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1825 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1826 IXGBE_WRITE_FLUSH(hw);
1827 ixgbe_service_event_schedule(adapter);
1828 }
1829 }
1830
1831 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1832 u64 qmask)
1833 {
1834 u32 mask;
1835 struct ixgbe_hw *hw = &adapter->hw;
1836
1837 switch (hw->mac.type) {
1838 case ixgbe_mac_82598EB:
1839 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1840 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1841 break;
1842 case ixgbe_mac_82599EB:
1843 case ixgbe_mac_X540:
1844 mask = (qmask & 0xFFFFFFFF);
1845 if (mask)
1846 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1847 mask = (qmask >> 32);
1848 if (mask)
1849 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1850 break;
1851 default:
1852 break;
1853 }
1854 /* skip the flush */
1855 }
1856
1857 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1858 u64 qmask)
1859 {
1860 u32 mask;
1861 struct ixgbe_hw *hw = &adapter->hw;
1862
1863 switch (hw->mac.type) {
1864 case ixgbe_mac_82598EB:
1865 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1866 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1867 break;
1868 case ixgbe_mac_82599EB:
1869 case ixgbe_mac_X540:
1870 mask = (qmask & 0xFFFFFFFF);
1871 if (mask)
1872 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1873 mask = (qmask >> 32);
1874 if (mask)
1875 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1876 break;
1877 default:
1878 break;
1879 }
1880 /* skip the flush */
1881 }
1882
1883 /**
1884 * ixgbe_irq_enable - Enable default interrupt generation settings
1885 * @adapter: board private structure
1886 **/
1887 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1888 bool flush)
1889 {
1890 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1891
1892 /* don't reenable LSC while waiting for link */
1893 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1894 mask &= ~IXGBE_EIMS_LSC;
1895
1896 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
1897 mask |= IXGBE_EIMS_GPI_SDP0;
1898 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1899 mask |= IXGBE_EIMS_GPI_SDP1;
1900 switch (adapter->hw.mac.type) {
1901 case ixgbe_mac_82599EB:
1902 case ixgbe_mac_X540:
1903 mask |= IXGBE_EIMS_ECC;
1904 mask |= IXGBE_EIMS_GPI_SDP1;
1905 mask |= IXGBE_EIMS_GPI_SDP2;
1906 mask |= IXGBE_EIMS_MAILBOX;
1907 break;
1908 default:
1909 break;
1910 }
1911 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1912 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1913 mask |= IXGBE_EIMS_FLOW_DIR;
1914
1915 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1916 if (queues)
1917 ixgbe_irq_enable_queues(adapter, ~0);
1918 if (flush)
1919 IXGBE_WRITE_FLUSH(&adapter->hw);
1920 }
1921
1922 static irqreturn_t ixgbe_msix_other(int irq, void *data)
1923 {
1924 struct ixgbe_adapter *adapter = data;
1925 struct ixgbe_hw *hw = &adapter->hw;
1926 u32 eicr;
1927
1928 /*
1929 * Workaround for Silicon errata. Use clear-by-write instead
1930 * of clear-by-read. Reading with EICS will return the
1931 * interrupt causes without clearing, which later be done
1932 * with the write to EICR.
1933 */
1934 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1935 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1936
1937 if (eicr & IXGBE_EICR_LSC)
1938 ixgbe_check_lsc(adapter);
1939
1940 if (eicr & IXGBE_EICR_MAILBOX)
1941 ixgbe_msg_task(adapter);
1942
1943 switch (hw->mac.type) {
1944 case ixgbe_mac_82599EB:
1945 case ixgbe_mac_X540:
1946 if (eicr & IXGBE_EICR_ECC)
1947 e_info(link, "Received unrecoverable ECC Err, please "
1948 "reboot\n");
1949 /* Handle Flow Director Full threshold interrupt */
1950 if (eicr & IXGBE_EICR_FLOW_DIR) {
1951 int reinit_count = 0;
1952 int i;
1953 for (i = 0; i < adapter->num_tx_queues; i++) {
1954 struct ixgbe_ring *ring = adapter->tx_ring[i];
1955 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1956 &ring->state))
1957 reinit_count++;
1958 }
1959 if (reinit_count) {
1960 /* no more flow director interrupts until after init */
1961 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1962 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1963 ixgbe_service_event_schedule(adapter);
1964 }
1965 }
1966 ixgbe_check_sfp_event(adapter, eicr);
1967 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1968 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1969 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1970 adapter->interrupt_event = eicr;
1971 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1972 ixgbe_service_event_schedule(adapter);
1973 }
1974 }
1975 break;
1976 default:
1977 break;
1978 }
1979
1980 ixgbe_check_fan_failure(adapter, eicr);
1981
1982 /* re-enable the original interrupt state, no lsc, no queues */
1983 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1984 ixgbe_irq_enable(adapter, false, false);
1985
1986 return IRQ_HANDLED;
1987 }
1988
1989 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
1990 {
1991 struct ixgbe_q_vector *q_vector = data;
1992
1993 /* EIAM disabled interrupts (on this vector) for us */
1994
1995 if (q_vector->rx.ring || q_vector->tx.ring)
1996 napi_schedule(&q_vector->napi);
1997
1998 return IRQ_HANDLED;
1999 }
2000
2001 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2002 int r_idx)
2003 {
2004 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2005 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2006
2007 rx_ring->q_vector = q_vector;
2008 rx_ring->next = q_vector->rx.ring;
2009 q_vector->rx.ring = rx_ring;
2010 q_vector->rx.count++;
2011 }
2012
2013 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2014 int t_idx)
2015 {
2016 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2017 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2018
2019 tx_ring->q_vector = q_vector;
2020 tx_ring->next = q_vector->tx.ring;
2021 q_vector->tx.ring = tx_ring;
2022 q_vector->tx.count++;
2023 q_vector->tx.work_limit = a->tx_work_limit;
2024 }
2025
2026 /**
2027 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2028 * @adapter: board private structure to initialize
2029 *
2030 * This function maps descriptor rings to the queue-specific vectors
2031 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2032 * one vector per ring/queue, but on a constrained vector budget, we
2033 * group the rings as "efficiently" as possible. You would add new
2034 * mapping configurations in here.
2035 **/
2036 static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2037 {
2038 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2039 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2040 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
2041 int v_start = 0;
2042
2043 /* only one q_vector if MSI-X is disabled. */
2044 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2045 q_vectors = 1;
2046
2047 /*
2048 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2049 * group them so there are multiple queues per vector.
2050 *
2051 * Re-adjusting *qpv takes care of the remainder.
2052 */
2053 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2054 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2055 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
2056 map_vector_to_rxq(adapter, v_start, rxr_idx);
2057 }
2058
2059 /*
2060 * If there are not enough q_vectors for each ring to have it's own
2061 * vector then we must pair up Rx/Tx on a each vector
2062 */
2063 if ((v_start + txr_remaining) > q_vectors)
2064 v_start = 0;
2065
2066 for (; v_start < q_vectors && txr_remaining; v_start++) {
2067 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2068 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2069 map_vector_to_txq(adapter, v_start, txr_idx);
2070 }
2071 }
2072
2073 /**
2074 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2075 * @adapter: board private structure
2076 *
2077 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2078 * interrupts from the kernel.
2079 **/
2080 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2081 {
2082 struct net_device *netdev = adapter->netdev;
2083 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2084 int vector, err;
2085 int ri = 0, ti = 0;
2086
2087 for (vector = 0; vector < q_vectors; vector++) {
2088 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2089 struct msix_entry *entry = &adapter->msix_entries[vector];
2090
2091 if (q_vector->tx.ring && q_vector->rx.ring) {
2092 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2093 "%s-%s-%d", netdev->name, "TxRx", ri++);
2094 ti++;
2095 } else if (q_vector->rx.ring) {
2096 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2097 "%s-%s-%d", netdev->name, "rx", ri++);
2098 } else if (q_vector->tx.ring) {
2099 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2100 "%s-%s-%d", netdev->name, "tx", ti++);
2101 } else {
2102 /* skip this unused q_vector */
2103 continue;
2104 }
2105 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2106 q_vector->name, q_vector);
2107 if (err) {
2108 e_err(probe, "request_irq failed for MSIX interrupt "
2109 "Error: %d\n", err);
2110 goto free_queue_irqs;
2111 }
2112 /* If Flow Director is enabled, set interrupt affinity */
2113 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2114 /* assign the mask for this irq */
2115 irq_set_affinity_hint(entry->vector,
2116 q_vector->affinity_mask);
2117 }
2118 }
2119
2120 err = request_irq(adapter->msix_entries[vector].vector,
2121 ixgbe_msix_other, 0, netdev->name, adapter);
2122 if (err) {
2123 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2124 goto free_queue_irqs;
2125 }
2126
2127 return 0;
2128
2129 free_queue_irqs:
2130 while (vector) {
2131 vector--;
2132 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2133 NULL);
2134 free_irq(adapter->msix_entries[vector].vector,
2135 adapter->q_vector[vector]);
2136 }
2137 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2138 pci_disable_msix(adapter->pdev);
2139 kfree(adapter->msix_entries);
2140 adapter->msix_entries = NULL;
2141 return err;
2142 }
2143
2144 /**
2145 * ixgbe_intr - legacy mode Interrupt Handler
2146 * @irq: interrupt number
2147 * @data: pointer to a network interface device structure
2148 **/
2149 static irqreturn_t ixgbe_intr(int irq, void *data)
2150 {
2151 struct ixgbe_adapter *adapter = data;
2152 struct ixgbe_hw *hw = &adapter->hw;
2153 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2154 u32 eicr;
2155
2156 /*
2157 * Workaround for silicon errata on 82598. Mask the interrupts
2158 * before the read of EICR.
2159 */
2160 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2161
2162 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2163 * therefore no explict interrupt disable is necessary */
2164 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2165 if (!eicr) {
2166 /*
2167 * shared interrupt alert!
2168 * make sure interrupts are enabled because the read will
2169 * have disabled interrupts due to EIAM
2170 * finish the workaround of silicon errata on 82598. Unmask
2171 * the interrupt that we masked before the EICR read.
2172 */
2173 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2174 ixgbe_irq_enable(adapter, true, true);
2175 return IRQ_NONE; /* Not our interrupt */
2176 }
2177
2178 if (eicr & IXGBE_EICR_LSC)
2179 ixgbe_check_lsc(adapter);
2180
2181 switch (hw->mac.type) {
2182 case ixgbe_mac_82599EB:
2183 ixgbe_check_sfp_event(adapter, eicr);
2184 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2185 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2186 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2187 adapter->interrupt_event = eicr;
2188 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2189 ixgbe_service_event_schedule(adapter);
2190 }
2191 }
2192 break;
2193 default:
2194 break;
2195 }
2196
2197 ixgbe_check_fan_failure(adapter, eicr);
2198
2199 if (napi_schedule_prep(&(q_vector->napi))) {
2200 /* would disable interrupts here but EIAM disabled it */
2201 __napi_schedule(&(q_vector->napi));
2202 }
2203
2204 /*
2205 * re-enable link(maybe) and non-queue interrupts, no flush.
2206 * ixgbe_poll will re-enable the queue interrupts
2207 */
2208
2209 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2210 ixgbe_irq_enable(adapter, false, false);
2211
2212 return IRQ_HANDLED;
2213 }
2214
2215 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2216 {
2217 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2218 int i;
2219
2220 /* legacy and MSI only use one vector */
2221 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2222 q_vectors = 1;
2223
2224 for (i = 0; i < adapter->num_rx_queues; i++) {
2225 adapter->rx_ring[i]->q_vector = NULL;
2226 adapter->rx_ring[i]->next = NULL;
2227 }
2228 for (i = 0; i < adapter->num_tx_queues; i++) {
2229 adapter->tx_ring[i]->q_vector = NULL;
2230 adapter->tx_ring[i]->next = NULL;
2231 }
2232
2233 for (i = 0; i < q_vectors; i++) {
2234 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2235 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2236 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
2237 }
2238 }
2239
2240 /**
2241 * ixgbe_request_irq - initialize interrupts
2242 * @adapter: board private structure
2243 *
2244 * Attempts to configure interrupts using the best available
2245 * capabilities of the hardware and kernel.
2246 **/
2247 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2248 {
2249 struct net_device *netdev = adapter->netdev;
2250 int err;
2251
2252 /* map all of the rings to the q_vectors */
2253 ixgbe_map_rings_to_vectors(adapter);
2254
2255 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2256 err = ixgbe_request_msix_irqs(adapter);
2257 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2258 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2259 netdev->name, adapter);
2260 else
2261 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2262 netdev->name, adapter);
2263
2264 if (err) {
2265 e_err(probe, "request_irq failed, Error %d\n", err);
2266
2267 /* place q_vectors and rings back into a known good state */
2268 ixgbe_reset_q_vectors(adapter);
2269 }
2270
2271 return err;
2272 }
2273
2274 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2275 {
2276 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2277 int i, q_vectors;
2278
2279 q_vectors = adapter->num_msix_vectors;
2280 i = q_vectors - 1;
2281 free_irq(adapter->msix_entries[i].vector, adapter);
2282 i--;
2283
2284 for (; i >= 0; i--) {
2285 /* free only the irqs that were actually requested */
2286 if (!adapter->q_vector[i]->rx.ring &&
2287 !adapter->q_vector[i]->tx.ring)
2288 continue;
2289
2290 /* clear the affinity_mask in the IRQ descriptor */
2291 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2292 NULL);
2293
2294 free_irq(adapter->msix_entries[i].vector,
2295 adapter->q_vector[i]);
2296 }
2297 } else {
2298 free_irq(adapter->pdev->irq, adapter);
2299 }
2300
2301 /* clear q_vector state information */
2302 ixgbe_reset_q_vectors(adapter);
2303 }
2304
2305 /**
2306 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2307 * @adapter: board private structure
2308 **/
2309 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2310 {
2311 switch (adapter->hw.mac.type) {
2312 case ixgbe_mac_82598EB:
2313 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2314 break;
2315 case ixgbe_mac_82599EB:
2316 case ixgbe_mac_X540:
2317 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2318 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2319 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2320 break;
2321 default:
2322 break;
2323 }
2324 IXGBE_WRITE_FLUSH(&adapter->hw);
2325 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2326 int i;
2327 for (i = 0; i < adapter->num_msix_vectors; i++)
2328 synchronize_irq(adapter->msix_entries[i].vector);
2329 } else {
2330 synchronize_irq(adapter->pdev->irq);
2331 }
2332 }
2333
2334 /**
2335 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2336 *
2337 **/
2338 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2339 {
2340 struct ixgbe_hw *hw = &adapter->hw;
2341
2342 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2343 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2344
2345 ixgbe_set_ivar(adapter, 0, 0, 0);
2346 ixgbe_set_ivar(adapter, 1, 0, 0);
2347
2348 e_info(hw, "Legacy interrupt IVAR setup done\n");
2349 }
2350
2351 /**
2352 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2353 * @adapter: board private structure
2354 * @ring: structure containing ring specific data
2355 *
2356 * Configure the Tx descriptor ring after a reset.
2357 **/
2358 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2359 struct ixgbe_ring *ring)
2360 {
2361 struct ixgbe_hw *hw = &adapter->hw;
2362 u64 tdba = ring->dma;
2363 int wait_loop = 10;
2364 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2365 u8 reg_idx = ring->reg_idx;
2366
2367 /* disable queue to avoid issues while updating state */
2368 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2369 IXGBE_WRITE_FLUSH(hw);
2370
2371 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2372 (tdba & DMA_BIT_MASK(32)));
2373 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2374 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2375 ring->count * sizeof(union ixgbe_adv_tx_desc));
2376 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2377 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2378 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2379
2380 /*
2381 * set WTHRESH to encourage burst writeback, it should not be set
2382 * higher than 1 when ITR is 0 as it could cause false TX hangs
2383 *
2384 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2385 * to or less than the number of on chip descriptors, which is
2386 * currently 40.
2387 */
2388 if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2389 txdctl |= (1 << 16); /* WTHRESH = 1 */
2390 else
2391 txdctl |= (8 << 16); /* WTHRESH = 8 */
2392
2393 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2394 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2395 32; /* PTHRESH = 32 */
2396
2397 /* reinitialize flowdirector state */
2398 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2399 adapter->atr_sample_rate) {
2400 ring->atr_sample_rate = adapter->atr_sample_rate;
2401 ring->atr_count = 0;
2402 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2403 } else {
2404 ring->atr_sample_rate = 0;
2405 }
2406
2407 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2408
2409 /* enable queue */
2410 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2411
2412 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2413 if (hw->mac.type == ixgbe_mac_82598EB &&
2414 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2415 return;
2416
2417 /* poll to verify queue is enabled */
2418 do {
2419 usleep_range(1000, 2000);
2420 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2421 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2422 if (!wait_loop)
2423 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2424 }
2425
2426 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2427 {
2428 struct ixgbe_hw *hw = &adapter->hw;
2429 u32 rttdcs;
2430 u32 reg;
2431 u8 tcs = netdev_get_num_tc(adapter->netdev);
2432
2433 if (hw->mac.type == ixgbe_mac_82598EB)
2434 return;
2435
2436 /* disable the arbiter while setting MTQC */
2437 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2438 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2439 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2440
2441 /* set transmit pool layout */
2442 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2443 case (IXGBE_FLAG_SRIOV_ENABLED):
2444 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2445 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2446 break;
2447 default:
2448 if (!tcs)
2449 reg = IXGBE_MTQC_64Q_1PB;
2450 else if (tcs <= 4)
2451 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2452 else
2453 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2454
2455 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2456
2457 /* Enable Security TX Buffer IFG for multiple pb */
2458 if (tcs) {
2459 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2460 reg |= IXGBE_SECTX_DCB;
2461 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2462 }
2463 break;
2464 }
2465
2466 /* re-enable the arbiter */
2467 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2468 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2469 }
2470
2471 /**
2472 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2473 * @adapter: board private structure
2474 *
2475 * Configure the Tx unit of the MAC after a reset.
2476 **/
2477 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2478 {
2479 struct ixgbe_hw *hw = &adapter->hw;
2480 u32 dmatxctl;
2481 u32 i;
2482
2483 ixgbe_setup_mtqc(adapter);
2484
2485 if (hw->mac.type != ixgbe_mac_82598EB) {
2486 /* DMATXCTL.EN must be before Tx queues are enabled */
2487 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2488 dmatxctl |= IXGBE_DMATXCTL_TE;
2489 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2490 }
2491
2492 /* Setup the HW Tx Head and Tail descriptor pointers */
2493 for (i = 0; i < adapter->num_tx_queues; i++)
2494 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2495 }
2496
2497 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2498
2499 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2500 struct ixgbe_ring *rx_ring)
2501 {
2502 u32 srrctl;
2503 u8 reg_idx = rx_ring->reg_idx;
2504
2505 switch (adapter->hw.mac.type) {
2506 case ixgbe_mac_82598EB: {
2507 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2508 const int mask = feature[RING_F_RSS].mask;
2509 reg_idx = reg_idx & mask;
2510 }
2511 break;
2512 case ixgbe_mac_82599EB:
2513 case ixgbe_mac_X540:
2514 default:
2515 break;
2516 }
2517
2518 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2519
2520 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2521 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2522 if (adapter->num_vfs)
2523 srrctl |= IXGBE_SRRCTL_DROP_EN;
2524
2525 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2526 IXGBE_SRRCTL_BSIZEHDR_MASK;
2527
2528 if (ring_is_ps_enabled(rx_ring)) {
2529 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2530 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2531 #else
2532 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2533 #endif
2534 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2535 } else {
2536 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2537 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2538 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2539 }
2540
2541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2542 }
2543
2544 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2545 {
2546 struct ixgbe_hw *hw = &adapter->hw;
2547 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2548 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2549 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2550 u32 mrqc = 0, reta = 0;
2551 u32 rxcsum;
2552 int i, j;
2553 u8 tcs = netdev_get_num_tc(adapter->netdev);
2554 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2555
2556 if (tcs)
2557 maxq = min(maxq, adapter->num_tx_queues / tcs);
2558
2559 /* Fill out hash function seeds */
2560 for (i = 0; i < 10; i++)
2561 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2562
2563 /* Fill out redirection table */
2564 for (i = 0, j = 0; i < 128; i++, j++) {
2565 if (j == maxq)
2566 j = 0;
2567 /* reta = 4-byte sliding window of
2568 * 0x00..(indices-1)(indices-1)00..etc. */
2569 reta = (reta << 8) | (j * 0x11);
2570 if ((i & 3) == 3)
2571 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2572 }
2573
2574 /* Disable indicating checksum in descriptor, enables RSS hash */
2575 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2576 rxcsum |= IXGBE_RXCSUM_PCSD;
2577 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2578
2579 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2580 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2581 mrqc = IXGBE_MRQC_RSSEN;
2582 } else {
2583 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2584 | IXGBE_FLAG_SRIOV_ENABLED);
2585
2586 switch (mask) {
2587 case (IXGBE_FLAG_RSS_ENABLED):
2588 if (!tcs)
2589 mrqc = IXGBE_MRQC_RSSEN;
2590 else if (tcs <= 4)
2591 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2592 else
2593 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2594 break;
2595 case (IXGBE_FLAG_SRIOV_ENABLED):
2596 mrqc = IXGBE_MRQC_VMDQEN;
2597 break;
2598 default:
2599 break;
2600 }
2601 }
2602
2603 /* Perform hash on these packet types */
2604 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2605 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2606 | IXGBE_MRQC_RSS_FIELD_IPV6
2607 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2608
2609 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2610 }
2611
2612 /**
2613 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2614 * @adapter: address of board private structure
2615 * @index: index of ring to set
2616 **/
2617 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2618 struct ixgbe_ring *ring)
2619 {
2620 struct ixgbe_hw *hw = &adapter->hw;
2621 u32 rscctrl;
2622 int rx_buf_len;
2623 u8 reg_idx = ring->reg_idx;
2624
2625 if (!ring_is_rsc_enabled(ring))
2626 return;
2627
2628 rx_buf_len = ring->rx_buf_len;
2629 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2630 rscctrl |= IXGBE_RSCCTL_RSCEN;
2631 /*
2632 * we must limit the number of descriptors so that the
2633 * total size of max desc * buf_len is not greater
2634 * than 65535
2635 */
2636 if (ring_is_ps_enabled(ring)) {
2637 #if (MAX_SKB_FRAGS > 16)
2638 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2639 #elif (MAX_SKB_FRAGS > 8)
2640 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2641 #elif (MAX_SKB_FRAGS > 4)
2642 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2643 #else
2644 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2645 #endif
2646 } else {
2647 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2648 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2649 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2650 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2651 else
2652 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2653 }
2654 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2655 }
2656
2657 /**
2658 * ixgbe_set_uta - Set unicast filter table address
2659 * @adapter: board private structure
2660 *
2661 * The unicast table address is a register array of 32-bit registers.
2662 * The table is meant to be used in a way similar to how the MTA is used
2663 * however due to certain limitations in the hardware it is necessary to
2664 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2665 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2666 **/
2667 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2668 {
2669 struct ixgbe_hw *hw = &adapter->hw;
2670 int i;
2671
2672 /* The UTA table only exists on 82599 hardware and newer */
2673 if (hw->mac.type < ixgbe_mac_82599EB)
2674 return;
2675
2676 /* we only need to do this if VMDq is enabled */
2677 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2678 return;
2679
2680 for (i = 0; i < 128; i++)
2681 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2682 }
2683
2684 #define IXGBE_MAX_RX_DESC_POLL 10
2685 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2686 struct ixgbe_ring *ring)
2687 {
2688 struct ixgbe_hw *hw = &adapter->hw;
2689 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2690 u32 rxdctl;
2691 u8 reg_idx = ring->reg_idx;
2692
2693 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2694 if (hw->mac.type == ixgbe_mac_82598EB &&
2695 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2696 return;
2697
2698 do {
2699 usleep_range(1000, 2000);
2700 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2701 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2702
2703 if (!wait_loop) {
2704 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2705 "the polling period\n", reg_idx);
2706 }
2707 }
2708
2709 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2710 struct ixgbe_ring *ring)
2711 {
2712 struct ixgbe_hw *hw = &adapter->hw;
2713 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2714 u32 rxdctl;
2715 u8 reg_idx = ring->reg_idx;
2716
2717 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2718 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2719
2720 /* write value back with RXDCTL.ENABLE bit cleared */
2721 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2722
2723 if (hw->mac.type == ixgbe_mac_82598EB &&
2724 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2725 return;
2726
2727 /* the hardware may take up to 100us to really disable the rx queue */
2728 do {
2729 udelay(10);
2730 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2731 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2732
2733 if (!wait_loop) {
2734 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2735 "the polling period\n", reg_idx);
2736 }
2737 }
2738
2739 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2740 struct ixgbe_ring *ring)
2741 {
2742 struct ixgbe_hw *hw = &adapter->hw;
2743 u64 rdba = ring->dma;
2744 u32 rxdctl;
2745 u8 reg_idx = ring->reg_idx;
2746
2747 /* disable queue to avoid issues while updating state */
2748 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2749 ixgbe_disable_rx_queue(adapter, ring);
2750
2751 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2752 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2753 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2754 ring->count * sizeof(union ixgbe_adv_rx_desc));
2755 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2756 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2757 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2758
2759 ixgbe_configure_srrctl(adapter, ring);
2760 ixgbe_configure_rscctl(adapter, ring);
2761
2762 /* If operating in IOV mode set RLPML for X540 */
2763 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2764 hw->mac.type == ixgbe_mac_X540) {
2765 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2766 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2767 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2768 }
2769
2770 if (hw->mac.type == ixgbe_mac_82598EB) {
2771 /*
2772 * enable cache line friendly hardware writes:
2773 * PTHRESH=32 descriptors (half the internal cache),
2774 * this also removes ugly rx_no_buffer_count increment
2775 * HTHRESH=4 descriptors (to minimize latency on fetch)
2776 * WTHRESH=8 burst writeback up to two cache lines
2777 */
2778 rxdctl &= ~0x3FFFFF;
2779 rxdctl |= 0x080420;
2780 }
2781
2782 /* enable receive descriptor ring */
2783 rxdctl |= IXGBE_RXDCTL_ENABLE;
2784 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2785
2786 ixgbe_rx_desc_queue_enable(adapter, ring);
2787 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
2788 }
2789
2790 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2791 {
2792 struct ixgbe_hw *hw = &adapter->hw;
2793 int p;
2794
2795 /* PSRTYPE must be initialized in non 82598 adapters */
2796 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2797 IXGBE_PSRTYPE_UDPHDR |
2798 IXGBE_PSRTYPE_IPV4HDR |
2799 IXGBE_PSRTYPE_L2HDR |
2800 IXGBE_PSRTYPE_IPV6HDR;
2801
2802 if (hw->mac.type == ixgbe_mac_82598EB)
2803 return;
2804
2805 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2806 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2807
2808 for (p = 0; p < adapter->num_rx_pools; p++)
2809 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2810 psrtype);
2811 }
2812
2813 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2814 {
2815 struct ixgbe_hw *hw = &adapter->hw;
2816 u32 gcr_ext;
2817 u32 vt_reg_bits;
2818 u32 reg_offset, vf_shift;
2819 u32 vmdctl;
2820
2821 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2822 return;
2823
2824 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2825 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2826 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2827 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2828
2829 vf_shift = adapter->num_vfs % 32;
2830 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2831
2832 /* Enable only the PF's pool for Tx/Rx */
2833 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2834 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2835 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2836 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2837 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2838
2839 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2840 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2841
2842 /*
2843 * Set up VF register offsets for selected VT Mode,
2844 * i.e. 32 or 64 VFs for SR-IOV
2845 */
2846 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2847 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2848 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2849 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2850
2851 /* enable Tx loopback for VF/PF communication */
2852 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2853 /* Enable MAC Anti-Spoofing */
2854 hw->mac.ops.set_mac_anti_spoofing(hw,
2855 (adapter->antispoofing_enabled =
2856 (adapter->num_vfs != 0)),
2857 adapter->num_vfs);
2858 }
2859
2860 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2861 {
2862 struct ixgbe_hw *hw = &adapter->hw;
2863 struct net_device *netdev = adapter->netdev;
2864 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2865 int rx_buf_len;
2866 struct ixgbe_ring *rx_ring;
2867 int i;
2868 u32 mhadd, hlreg0;
2869
2870 /* Decide whether to use packet split mode or not */
2871 /* On by default */
2872 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2873
2874 /* Do not use packet split if we're in SR-IOV Mode */
2875 if (adapter->num_vfs)
2876 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2877
2878 /* Disable packet split due to 82599 erratum #45 */
2879 if (hw->mac.type == ixgbe_mac_82599EB)
2880 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2881
2882 /* Set the RX buffer length according to the mode */
2883 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2884 rx_buf_len = IXGBE_RX_HDR_SIZE;
2885 } else {
2886 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2887 (netdev->mtu <= ETH_DATA_LEN))
2888 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2889 else
2890 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2891 }
2892
2893 #ifdef IXGBE_FCOE
2894 /* adjust max frame to be able to do baby jumbo for FCoE */
2895 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2896 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2897 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2898
2899 #endif /* IXGBE_FCOE */
2900 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2901 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2902 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2903 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2904
2905 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2906 }
2907
2908 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2909 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2910 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2911 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2912
2913 /*
2914 * Setup the HW Rx Head and Tail Descriptor Pointers and
2915 * the Base and Length of the Rx Descriptor Ring
2916 */
2917 for (i = 0; i < adapter->num_rx_queues; i++) {
2918 rx_ring = adapter->rx_ring[i];
2919 rx_ring->rx_buf_len = rx_buf_len;
2920
2921 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2922 set_ring_ps_enabled(rx_ring);
2923 else
2924 clear_ring_ps_enabled(rx_ring);
2925
2926 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2927 set_ring_rsc_enabled(rx_ring);
2928 else
2929 clear_ring_rsc_enabled(rx_ring);
2930
2931 #ifdef IXGBE_FCOE
2932 if (netdev->features & NETIF_F_FCOE_MTU) {
2933 struct ixgbe_ring_feature *f;
2934 f = &adapter->ring_feature[RING_F_FCOE];
2935 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2936 clear_ring_ps_enabled(rx_ring);
2937 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2938 rx_ring->rx_buf_len =
2939 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2940 } else if (!ring_is_rsc_enabled(rx_ring) &&
2941 !ring_is_ps_enabled(rx_ring)) {
2942 rx_ring->rx_buf_len =
2943 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2944 }
2945 }
2946 #endif /* IXGBE_FCOE */
2947 }
2948 }
2949
2950 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2951 {
2952 struct ixgbe_hw *hw = &adapter->hw;
2953 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2954
2955 switch (hw->mac.type) {
2956 case ixgbe_mac_82598EB:
2957 /*
2958 * For VMDq support of different descriptor types or
2959 * buffer sizes through the use of multiple SRRCTL
2960 * registers, RDRXCTL.MVMEN must be set to 1
2961 *
2962 * also, the manual doesn't mention it clearly but DCA hints
2963 * will only use queue 0's tags unless this bit is set. Side
2964 * effects of setting this bit are only that SRRCTL must be
2965 * fully programmed [0..15]
2966 */
2967 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2968 break;
2969 case ixgbe_mac_82599EB:
2970 case ixgbe_mac_X540:
2971 /* Disable RSC for ACK packets */
2972 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2973 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2974 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2975 /* hardware requires some bits to be set by default */
2976 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2977 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2978 break;
2979 default:
2980 /* We should do nothing since we don't know this hardware */
2981 return;
2982 }
2983
2984 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2985 }
2986
2987 /**
2988 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2989 * @adapter: board private structure
2990 *
2991 * Configure the Rx unit of the MAC after a reset.
2992 **/
2993 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2994 {
2995 struct ixgbe_hw *hw = &adapter->hw;
2996 int i;
2997 u32 rxctrl;
2998
2999 /* disable receives while setting up the descriptors */
3000 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3001 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3002
3003 ixgbe_setup_psrtype(adapter);
3004 ixgbe_setup_rdrxctl(adapter);
3005
3006 /* Program registers for the distribution of queues */
3007 ixgbe_setup_mrqc(adapter);
3008
3009 ixgbe_set_uta(adapter);
3010
3011 /* set_rx_buffer_len must be called before ring initialization */
3012 ixgbe_set_rx_buffer_len(adapter);
3013
3014 /*
3015 * Setup the HW Rx Head and Tail Descriptor Pointers and
3016 * the Base and Length of the Rx Descriptor Ring
3017 */
3018 for (i = 0; i < adapter->num_rx_queues; i++)
3019 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3020
3021 /* disable drop enable for 82598 parts */
3022 if (hw->mac.type == ixgbe_mac_82598EB)
3023 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3024
3025 /* enable all receives */
3026 rxctrl |= IXGBE_RXCTRL_RXEN;
3027 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3028 }
3029
3030 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3031 {
3032 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3033 struct ixgbe_hw *hw = &adapter->hw;
3034 int pool_ndx = adapter->num_vfs;
3035
3036 /* add VID to filter table */
3037 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3038 set_bit(vid, adapter->active_vlans);
3039 }
3040
3041 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3042 {
3043 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3044 struct ixgbe_hw *hw = &adapter->hw;
3045 int pool_ndx = adapter->num_vfs;
3046
3047 /* remove VID from filter table */
3048 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3049 clear_bit(vid, adapter->active_vlans);
3050 }
3051
3052 /**
3053 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3054 * @adapter: driver data
3055 */
3056 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3057 {
3058 struct ixgbe_hw *hw = &adapter->hw;
3059 u32 vlnctrl;
3060
3061 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3062 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3063 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3064 }
3065
3066 /**
3067 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3068 * @adapter: driver data
3069 */
3070 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3071 {
3072 struct ixgbe_hw *hw = &adapter->hw;
3073 u32 vlnctrl;
3074
3075 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3076 vlnctrl |= IXGBE_VLNCTRL_VFE;
3077 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3078 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3079 }
3080
3081 /**
3082 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3083 * @adapter: driver data
3084 */
3085 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3086 {
3087 struct ixgbe_hw *hw = &adapter->hw;
3088 u32 vlnctrl;
3089 int i, j;
3090
3091 switch (hw->mac.type) {
3092 case ixgbe_mac_82598EB:
3093 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3094 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3095 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3096 break;
3097 case ixgbe_mac_82599EB:
3098 case ixgbe_mac_X540:
3099 for (i = 0; i < adapter->num_rx_queues; i++) {
3100 j = adapter->rx_ring[i]->reg_idx;
3101 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3102 vlnctrl &= ~IXGBE_RXDCTL_VME;
3103 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3104 }
3105 break;
3106 default:
3107 break;
3108 }
3109 }
3110
3111 /**
3112 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3113 * @adapter: driver data
3114 */
3115 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3116 {
3117 struct ixgbe_hw *hw = &adapter->hw;
3118 u32 vlnctrl;
3119 int i, j;
3120
3121 switch (hw->mac.type) {
3122 case ixgbe_mac_82598EB:
3123 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3124 vlnctrl |= IXGBE_VLNCTRL_VME;
3125 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3126 break;
3127 case ixgbe_mac_82599EB:
3128 case ixgbe_mac_X540:
3129 for (i = 0; i < adapter->num_rx_queues; i++) {
3130 j = adapter->rx_ring[i]->reg_idx;
3131 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3132 vlnctrl |= IXGBE_RXDCTL_VME;
3133 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3134 }
3135 break;
3136 default:
3137 break;
3138 }
3139 }
3140
3141 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3142 {
3143 u16 vid;
3144
3145 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3146
3147 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3148 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3149 }
3150
3151 /**
3152 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3153 * @netdev: network interface device structure
3154 *
3155 * Writes unicast address list to the RAR table.
3156 * Returns: -ENOMEM on failure/insufficient address space
3157 * 0 on no addresses written
3158 * X on writing X addresses to the RAR table
3159 **/
3160 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3161 {
3162 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3163 struct ixgbe_hw *hw = &adapter->hw;
3164 unsigned int vfn = adapter->num_vfs;
3165 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3166 int count = 0;
3167
3168 /* return ENOMEM indicating insufficient memory for addresses */
3169 if (netdev_uc_count(netdev) > rar_entries)
3170 return -ENOMEM;
3171
3172 if (!netdev_uc_empty(netdev) && rar_entries) {
3173 struct netdev_hw_addr *ha;
3174 /* return error if we do not support writing to RAR table */
3175 if (!hw->mac.ops.set_rar)
3176 return -ENOMEM;
3177
3178 netdev_for_each_uc_addr(ha, netdev) {
3179 if (!rar_entries)
3180 break;
3181 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3182 vfn, IXGBE_RAH_AV);
3183 count++;
3184 }
3185 }
3186 /* write the addresses in reverse order to avoid write combining */
3187 for (; rar_entries > 0 ; rar_entries--)
3188 hw->mac.ops.clear_rar(hw, rar_entries);
3189
3190 return count;
3191 }
3192
3193 /**
3194 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3195 * @netdev: network interface device structure
3196 *
3197 * The set_rx_method entry point is called whenever the unicast/multicast
3198 * address list or the network interface flags are updated. This routine is
3199 * responsible for configuring the hardware for proper unicast, multicast and
3200 * promiscuous mode.
3201 **/
3202 void ixgbe_set_rx_mode(struct net_device *netdev)
3203 {
3204 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3205 struct ixgbe_hw *hw = &adapter->hw;
3206 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3207 int count;
3208
3209 /* Check for Promiscuous and All Multicast modes */
3210
3211 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3212
3213 /* set all bits that we expect to always be set */
3214 fctrl |= IXGBE_FCTRL_BAM;
3215 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3216 fctrl |= IXGBE_FCTRL_PMCF;
3217
3218 /* clear the bits we are changing the status of */
3219 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3220
3221 if (netdev->flags & IFF_PROMISC) {
3222 hw->addr_ctrl.user_set_promisc = true;
3223 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3224 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3225 /* don't hardware filter vlans in promisc mode */
3226 ixgbe_vlan_filter_disable(adapter);
3227 } else {
3228 if (netdev->flags & IFF_ALLMULTI) {
3229 fctrl |= IXGBE_FCTRL_MPE;
3230 vmolr |= IXGBE_VMOLR_MPE;
3231 } else {
3232 /*
3233 * Write addresses to the MTA, if the attempt fails
3234 * then we should just turn on promiscuous mode so
3235 * that we can at least receive multicast traffic
3236 */
3237 hw->mac.ops.update_mc_addr_list(hw, netdev);
3238 vmolr |= IXGBE_VMOLR_ROMPE;
3239 }
3240 ixgbe_vlan_filter_enable(adapter);
3241 hw->addr_ctrl.user_set_promisc = false;
3242 /*
3243 * Write addresses to available RAR registers, if there is not
3244 * sufficient space to store all the addresses then enable
3245 * unicast promiscuous mode
3246 */
3247 count = ixgbe_write_uc_addr_list(netdev);
3248 if (count < 0) {
3249 fctrl |= IXGBE_FCTRL_UPE;
3250 vmolr |= IXGBE_VMOLR_ROPE;
3251 }
3252 }
3253
3254 if (adapter->num_vfs) {
3255 ixgbe_restore_vf_multicasts(adapter);
3256 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3257 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3258 IXGBE_VMOLR_ROPE);
3259 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3260 }
3261
3262 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3263
3264 if (netdev->features & NETIF_F_HW_VLAN_RX)
3265 ixgbe_vlan_strip_enable(adapter);
3266 else
3267 ixgbe_vlan_strip_disable(adapter);
3268 }
3269
3270 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3271 {
3272 int q_idx;
3273 struct ixgbe_q_vector *q_vector;
3274 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3275
3276 /* legacy and MSI only use one vector */
3277 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3278 q_vectors = 1;
3279
3280 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3281 q_vector = adapter->q_vector[q_idx];
3282 napi_enable(&q_vector->napi);
3283 }
3284 }
3285
3286 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3287 {
3288 int q_idx;
3289 struct ixgbe_q_vector *q_vector;
3290 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3291
3292 /* legacy and MSI only use one vector */
3293 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3294 q_vectors = 1;
3295
3296 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3297 q_vector = adapter->q_vector[q_idx];
3298 napi_disable(&q_vector->napi);
3299 }
3300 }
3301
3302 #ifdef CONFIG_IXGBE_DCB
3303 /*
3304 * ixgbe_configure_dcb - Configure DCB hardware
3305 * @adapter: ixgbe adapter struct
3306 *
3307 * This is called by the driver on open to configure the DCB hardware.
3308 * This is also called by the gennetlink interface when reconfiguring
3309 * the DCB state.
3310 */
3311 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3312 {
3313 struct ixgbe_hw *hw = &adapter->hw;
3314 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3315
3316 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3317 if (hw->mac.type == ixgbe_mac_82598EB)
3318 netif_set_gso_max_size(adapter->netdev, 65536);
3319 return;
3320 }
3321
3322 if (hw->mac.type == ixgbe_mac_82598EB)
3323 netif_set_gso_max_size(adapter->netdev, 32768);
3324
3325
3326 /* Enable VLAN tag insert/strip */
3327 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3328
3329 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3330
3331 /* reconfigure the hardware */
3332 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3333 #ifdef IXGBE_FCOE
3334 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3335 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3336 #endif
3337 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3338 DCB_TX_CONFIG);
3339 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3340 DCB_RX_CONFIG);
3341 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3342 } else {
3343 struct net_device *dev = adapter->netdev;
3344
3345 if (adapter->ixgbe_ieee_ets)
3346 dev->dcbnl_ops->ieee_setets(dev,
3347 adapter->ixgbe_ieee_ets);
3348 if (adapter->ixgbe_ieee_pfc)
3349 dev->dcbnl_ops->ieee_setpfc(dev,
3350 adapter->ixgbe_ieee_pfc);
3351 }
3352
3353 /* Enable RSS Hash per TC */
3354 if (hw->mac.type != ixgbe_mac_82598EB) {
3355 int i;
3356 u32 reg = 0;
3357
3358 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3359 u8 msb = 0;
3360 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3361
3362 while (cnt >>= 1)
3363 msb++;
3364
3365 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3366 }
3367 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3368 }
3369 }
3370
3371 #endif
3372
3373 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3374 {
3375 struct ixgbe_hw *hw = &adapter->hw;
3376 int hdrm;
3377 u8 tc = netdev_get_num_tc(adapter->netdev);
3378
3379 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3380 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3381 hdrm = 32 << adapter->fdir_pballoc;
3382 else
3383 hdrm = 0;
3384
3385 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3386 }
3387
3388 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3389 {
3390 struct ixgbe_hw *hw = &adapter->hw;
3391 struct hlist_node *node, *node2;
3392 struct ixgbe_fdir_filter *filter;
3393
3394 spin_lock(&adapter->fdir_perfect_lock);
3395
3396 if (!hlist_empty(&adapter->fdir_filter_list))
3397 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3398
3399 hlist_for_each_entry_safe(filter, node, node2,
3400 &adapter->fdir_filter_list, fdir_node) {
3401 ixgbe_fdir_write_perfect_filter_82599(hw,
3402 &filter->filter,
3403 filter->sw_idx,
3404 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3405 IXGBE_FDIR_DROP_QUEUE :
3406 adapter->rx_ring[filter->action]->reg_idx);
3407 }
3408
3409 spin_unlock(&adapter->fdir_perfect_lock);
3410 }
3411
3412 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3413 {
3414 ixgbe_configure_pb(adapter);
3415 #ifdef CONFIG_IXGBE_DCB
3416 ixgbe_configure_dcb(adapter);
3417 #endif
3418
3419 ixgbe_set_rx_mode(adapter->netdev);
3420 ixgbe_restore_vlan(adapter);
3421
3422 #ifdef IXGBE_FCOE
3423 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3424 ixgbe_configure_fcoe(adapter);
3425
3426 #endif /* IXGBE_FCOE */
3427 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3428 ixgbe_init_fdir_signature_82599(&adapter->hw,
3429 adapter->fdir_pballoc);
3430 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3431 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3432 adapter->fdir_pballoc);
3433 ixgbe_fdir_filter_restore(adapter);
3434 }
3435
3436 ixgbe_configure_virtualization(adapter);
3437
3438 ixgbe_configure_tx(adapter);
3439 ixgbe_configure_rx(adapter);
3440 }
3441
3442 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3443 {
3444 switch (hw->phy.type) {
3445 case ixgbe_phy_sfp_avago:
3446 case ixgbe_phy_sfp_ftl:
3447 case ixgbe_phy_sfp_intel:
3448 case ixgbe_phy_sfp_unknown:
3449 case ixgbe_phy_sfp_passive_tyco:
3450 case ixgbe_phy_sfp_passive_unknown:
3451 case ixgbe_phy_sfp_active_unknown:
3452 case ixgbe_phy_sfp_ftl_active:
3453 return true;
3454 default:
3455 return false;
3456 }
3457 }
3458
3459 /**
3460 * ixgbe_sfp_link_config - set up SFP+ link
3461 * @adapter: pointer to private adapter struct
3462 **/
3463 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3464 {
3465 /*
3466 * We are assuming the worst case scenerio here, and that
3467 * is that an SFP was inserted/removed after the reset
3468 * but before SFP detection was enabled. As such the best
3469 * solution is to just start searching as soon as we start
3470 */
3471 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3472 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3473
3474 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3475 }
3476
3477 /**
3478 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3479 * @hw: pointer to private hardware struct
3480 *
3481 * Returns 0 on success, negative on failure
3482 **/
3483 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3484 {
3485 u32 autoneg;
3486 bool negotiation, link_up = false;
3487 u32 ret = IXGBE_ERR_LINK_SETUP;
3488
3489 if (hw->mac.ops.check_link)
3490 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3491
3492 if (ret)
3493 goto link_cfg_out;
3494
3495 autoneg = hw->phy.autoneg_advertised;
3496 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3497 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3498 &negotiation);
3499 if (ret)
3500 goto link_cfg_out;
3501
3502 if (hw->mac.ops.setup_link)
3503 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3504 link_cfg_out:
3505 return ret;
3506 }
3507
3508 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3509 {
3510 struct ixgbe_hw *hw = &adapter->hw;
3511 u32 gpie = 0;
3512
3513 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3514 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3515 IXGBE_GPIE_OCD;
3516 gpie |= IXGBE_GPIE_EIAME;
3517 /*
3518 * use EIAM to auto-mask when MSI-X interrupt is asserted
3519 * this saves a register write for every interrupt
3520 */
3521 switch (hw->mac.type) {
3522 case ixgbe_mac_82598EB:
3523 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3524 break;
3525 case ixgbe_mac_82599EB:
3526 case ixgbe_mac_X540:
3527 default:
3528 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3529 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3530 break;
3531 }
3532 } else {
3533 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3534 * specifically only auto mask tx and rx interrupts */
3535 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3536 }
3537
3538 /* XXX: to interrupt immediately for EICS writes, enable this */
3539 /* gpie |= IXGBE_GPIE_EIMEN; */
3540
3541 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3542 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3543 gpie |= IXGBE_GPIE_VTMODE_64;
3544 }
3545
3546 /* Enable Thermal over heat sensor interrupt */
3547 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3548 gpie |= IXGBE_SDP0_GPIEN;
3549
3550 /* Enable fan failure interrupt */
3551 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3552 gpie |= IXGBE_SDP1_GPIEN;
3553
3554 if (hw->mac.type == ixgbe_mac_82599EB) {
3555 gpie |= IXGBE_SDP1_GPIEN;
3556 gpie |= IXGBE_SDP2_GPIEN;
3557 }
3558
3559 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3560 }
3561
3562 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
3563 {
3564 struct ixgbe_hw *hw = &adapter->hw;
3565 int err;
3566 u32 ctrl_ext;
3567
3568 ixgbe_get_hw_control(adapter);
3569 ixgbe_setup_gpie(adapter);
3570
3571 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3572 ixgbe_configure_msix(adapter);
3573 else
3574 ixgbe_configure_msi_and_legacy(adapter);
3575
3576 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3577 if (hw->mac.ops.enable_tx_laser &&
3578 ((hw->phy.multispeed_fiber) ||
3579 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3580 (hw->mac.type == ixgbe_mac_82599EB))))
3581 hw->mac.ops.enable_tx_laser(hw);
3582
3583 clear_bit(__IXGBE_DOWN, &adapter->state);
3584 ixgbe_napi_enable_all(adapter);
3585
3586 if (ixgbe_is_sfp(hw)) {
3587 ixgbe_sfp_link_config(adapter);
3588 } else {
3589 err = ixgbe_non_sfp_link_config(hw);
3590 if (err)
3591 e_err(probe, "link_config FAILED %d\n", err);
3592 }
3593
3594 /* clear any pending interrupts, may auto mask */
3595 IXGBE_READ_REG(hw, IXGBE_EICR);
3596 ixgbe_irq_enable(adapter, true, true);
3597
3598 /*
3599 * If this adapter has a fan, check to see if we had a failure
3600 * before we enabled the interrupt.
3601 */
3602 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3603 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3604 if (esdp & IXGBE_ESDP_SDP1)
3605 e_crit(drv, "Fan has stopped, replace the adapter\n");
3606 }
3607
3608 /* enable transmits */
3609 netif_tx_start_all_queues(adapter->netdev);
3610
3611 /* bring the link up in the watchdog, this could race with our first
3612 * link up interrupt but shouldn't be a problem */
3613 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3614 adapter->link_check_timeout = jiffies;
3615 mod_timer(&adapter->service_timer, jiffies);
3616
3617 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3618 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3619 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3620 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3621 }
3622
3623 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3624 {
3625 WARN_ON(in_interrupt());
3626 /* put off any impending NetWatchDogTimeout */
3627 adapter->netdev->trans_start = jiffies;
3628
3629 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3630 usleep_range(1000, 2000);
3631 ixgbe_down(adapter);
3632 /*
3633 * If SR-IOV enabled then wait a bit before bringing the adapter
3634 * back up to give the VFs time to respond to the reset. The
3635 * two second wait is based upon the watchdog timer cycle in
3636 * the VF driver.
3637 */
3638 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3639 msleep(2000);
3640 ixgbe_up(adapter);
3641 clear_bit(__IXGBE_RESETTING, &adapter->state);
3642 }
3643
3644 void ixgbe_up(struct ixgbe_adapter *adapter)
3645 {
3646 /* hardware has been reset, we need to reload some things */
3647 ixgbe_configure(adapter);
3648
3649 ixgbe_up_complete(adapter);
3650 }
3651
3652 void ixgbe_reset(struct ixgbe_adapter *adapter)
3653 {
3654 struct ixgbe_hw *hw = &adapter->hw;
3655 int err;
3656
3657 /* lock SFP init bit to prevent race conditions with the watchdog */
3658 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3659 usleep_range(1000, 2000);
3660
3661 /* clear all SFP and link config related flags while holding SFP_INIT */
3662 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3663 IXGBE_FLAG2_SFP_NEEDS_RESET);
3664 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3665
3666 err = hw->mac.ops.init_hw(hw);
3667 switch (err) {
3668 case 0:
3669 case IXGBE_ERR_SFP_NOT_PRESENT:
3670 case IXGBE_ERR_SFP_NOT_SUPPORTED:
3671 break;
3672 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3673 e_dev_err("master disable timed out\n");
3674 break;
3675 case IXGBE_ERR_EEPROM_VERSION:
3676 /* We are running on a pre-production device, log a warning */
3677 e_dev_warn("This device is a pre-production adapter/LOM. "
3678 "Please be aware there may be issuesassociated with "
3679 "your hardware. If you are experiencing problems "
3680 "please contact your Intel or hardware "
3681 "representative who provided you with this "
3682 "hardware.\n");
3683 break;
3684 default:
3685 e_dev_err("Hardware Error: %d\n", err);
3686 }
3687
3688 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3689
3690 /* reprogram the RAR[0] in case user changed it. */
3691 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3692 IXGBE_RAH_AV);
3693 }
3694
3695 /**
3696 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3697 * @rx_ring: ring to free buffers from
3698 **/
3699 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3700 {
3701 struct device *dev = rx_ring->dev;
3702 unsigned long size;
3703 u16 i;
3704
3705 /* ring already cleared, nothing to do */
3706 if (!rx_ring->rx_buffer_info)
3707 return;
3708
3709 /* Free all the Rx ring sk_buffs */
3710 for (i = 0; i < rx_ring->count; i++) {
3711 struct ixgbe_rx_buffer *rx_buffer_info;
3712
3713 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3714 if (rx_buffer_info->dma) {
3715 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3716 rx_ring->rx_buf_len,
3717 DMA_FROM_DEVICE);
3718 rx_buffer_info->dma = 0;
3719 }
3720 if (rx_buffer_info->skb) {
3721 struct sk_buff *skb = rx_buffer_info->skb;
3722 rx_buffer_info->skb = NULL;
3723 do {
3724 struct sk_buff *this = skb;
3725 if (IXGBE_RSC_CB(this)->delay_unmap) {
3726 dma_unmap_single(dev,
3727 IXGBE_RSC_CB(this)->dma,
3728 rx_ring->rx_buf_len,
3729 DMA_FROM_DEVICE);
3730 IXGBE_RSC_CB(this)->dma = 0;
3731 IXGBE_RSC_CB(skb)->delay_unmap = false;
3732 }
3733 skb = skb->prev;
3734 dev_kfree_skb(this);
3735 } while (skb);
3736 }
3737 if (!rx_buffer_info->page)
3738 continue;
3739 if (rx_buffer_info->page_dma) {
3740 dma_unmap_page(dev, rx_buffer_info->page_dma,
3741 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3742 rx_buffer_info->page_dma = 0;
3743 }
3744 put_page(rx_buffer_info->page);
3745 rx_buffer_info->page = NULL;
3746 rx_buffer_info->page_offset = 0;
3747 }
3748
3749 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3750 memset(rx_ring->rx_buffer_info, 0, size);
3751
3752 /* Zero out the descriptor ring */
3753 memset(rx_ring->desc, 0, rx_ring->size);
3754
3755 rx_ring->next_to_clean = 0;
3756 rx_ring->next_to_use = 0;
3757 }
3758
3759 /**
3760 * ixgbe_clean_tx_ring - Free Tx Buffers
3761 * @tx_ring: ring to be cleaned
3762 **/
3763 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3764 {
3765 struct ixgbe_tx_buffer *tx_buffer_info;
3766 unsigned long size;
3767 u16 i;
3768
3769 /* ring already cleared, nothing to do */
3770 if (!tx_ring->tx_buffer_info)
3771 return;
3772
3773 /* Free all the Tx ring sk_buffs */
3774 for (i = 0; i < tx_ring->count; i++) {
3775 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3776 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3777 }
3778
3779 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3780 memset(tx_ring->tx_buffer_info, 0, size);
3781
3782 /* Zero out the descriptor ring */
3783 memset(tx_ring->desc, 0, tx_ring->size);
3784
3785 tx_ring->next_to_use = 0;
3786 tx_ring->next_to_clean = 0;
3787 }
3788
3789 /**
3790 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3791 * @adapter: board private structure
3792 **/
3793 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3794 {
3795 int i;
3796
3797 for (i = 0; i < adapter->num_rx_queues; i++)
3798 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3799 }
3800
3801 /**
3802 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3803 * @adapter: board private structure
3804 **/
3805 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3806 {
3807 int i;
3808
3809 for (i = 0; i < adapter->num_tx_queues; i++)
3810 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3811 }
3812
3813 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3814 {
3815 struct hlist_node *node, *node2;
3816 struct ixgbe_fdir_filter *filter;
3817
3818 spin_lock(&adapter->fdir_perfect_lock);
3819
3820 hlist_for_each_entry_safe(filter, node, node2,
3821 &adapter->fdir_filter_list, fdir_node) {
3822 hlist_del(&filter->fdir_node);
3823 kfree(filter);
3824 }
3825 adapter->fdir_filter_count = 0;
3826
3827 spin_unlock(&adapter->fdir_perfect_lock);
3828 }
3829
3830 void ixgbe_down(struct ixgbe_adapter *adapter)
3831 {
3832 struct net_device *netdev = adapter->netdev;
3833 struct ixgbe_hw *hw = &adapter->hw;
3834 u32 rxctrl;
3835 int i;
3836
3837 /* signal that we are down to the interrupt handler */
3838 set_bit(__IXGBE_DOWN, &adapter->state);
3839
3840 /* disable receives */
3841 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3842 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3843
3844 /* disable all enabled rx queues */
3845 for (i = 0; i < adapter->num_rx_queues; i++)
3846 /* this call also flushes the previous write */
3847 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
3848
3849 usleep_range(10000, 20000);
3850
3851 netif_tx_stop_all_queues(netdev);
3852
3853 /* call carrier off first to avoid false dev_watchdog timeouts */
3854 netif_carrier_off(netdev);
3855 netif_tx_disable(netdev);
3856
3857 ixgbe_irq_disable(adapter);
3858
3859 ixgbe_napi_disable_all(adapter);
3860
3861 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
3862 IXGBE_FLAG2_RESET_REQUESTED);
3863 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3864
3865 del_timer_sync(&adapter->service_timer);
3866
3867 if (adapter->num_vfs) {
3868 /* Clear EITR Select mapping */
3869 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
3870
3871 /* Mark all the VFs as inactive */
3872 for (i = 0 ; i < adapter->num_vfs; i++)
3873 adapter->vfinfo[i].clear_to_send = 0;
3874
3875 /* ping all the active vfs to let them know we are going down */
3876 ixgbe_ping_all_vfs(adapter);
3877
3878 /* Disable all VFTE/VFRE TX/RX */
3879 ixgbe_disable_tx_rx(adapter);
3880 }
3881
3882 /* disable transmits in the hardware now that interrupts are off */
3883 for (i = 0; i < adapter->num_tx_queues; i++) {
3884 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
3885 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
3886 }
3887
3888 /* Disable the Tx DMA engine on 82599 and X540 */
3889 switch (hw->mac.type) {
3890 case ixgbe_mac_82599EB:
3891 case ixgbe_mac_X540:
3892 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3893 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3894 ~IXGBE_DMATXCTL_TE));
3895 break;
3896 default:
3897 break;
3898 }
3899
3900 if (!pci_channel_offline(adapter->pdev))
3901 ixgbe_reset(adapter);
3902
3903 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
3904 if (hw->mac.ops.disable_tx_laser &&
3905 ((hw->phy.multispeed_fiber) ||
3906 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3907 (hw->mac.type == ixgbe_mac_82599EB))))
3908 hw->mac.ops.disable_tx_laser(hw);
3909
3910 ixgbe_clean_all_tx_rings(adapter);
3911 ixgbe_clean_all_rx_rings(adapter);
3912
3913 #ifdef CONFIG_IXGBE_DCA
3914 /* since we reset the hardware DCA settings were cleared */
3915 ixgbe_setup_dca(adapter);
3916 #endif
3917 }
3918
3919 /**
3920 * ixgbe_poll - NAPI Rx polling callback
3921 * @napi: structure for representing this polling device
3922 * @budget: how many packets driver is allowed to clean
3923 *
3924 * This function is used for legacy and MSI, NAPI mode
3925 **/
3926 static int ixgbe_poll(struct napi_struct *napi, int budget)
3927 {
3928 struct ixgbe_q_vector *q_vector =
3929 container_of(napi, struct ixgbe_q_vector, napi);
3930 struct ixgbe_adapter *adapter = q_vector->adapter;
3931 struct ixgbe_ring *ring;
3932 int per_ring_budget;
3933 bool clean_complete = true;
3934
3935 #ifdef CONFIG_IXGBE_DCA
3936 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3937 ixgbe_update_dca(q_vector);
3938 #endif
3939
3940 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
3941 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
3942
3943 /* attempt to distribute budget to each queue fairly, but don't allow
3944 * the budget to go below 1 because we'll exit polling */
3945 if (q_vector->rx.count > 1)
3946 per_ring_budget = max(budget/q_vector->rx.count, 1);
3947 else
3948 per_ring_budget = budget;
3949
3950 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
3951 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
3952 per_ring_budget);
3953
3954 /* If all work not completed, return budget and keep polling */
3955 if (!clean_complete)
3956 return budget;
3957
3958 /* all work done, exit the polling mode */
3959 napi_complete(napi);
3960 if (adapter->rx_itr_setting & 1)
3961 ixgbe_set_itr(q_vector);
3962 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3963 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
3964
3965 return 0;
3966 }
3967
3968 /**
3969 * ixgbe_tx_timeout - Respond to a Tx Hang
3970 * @netdev: network interface device structure
3971 **/
3972 static void ixgbe_tx_timeout(struct net_device *netdev)
3973 {
3974 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3975
3976 /* Do the reset outside of interrupt context */
3977 ixgbe_tx_timeout_reset(adapter);
3978 }
3979
3980 /**
3981 * ixgbe_set_rss_queues: Allocate queues for RSS
3982 * @adapter: board private structure to initialize
3983 *
3984 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3985 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3986 *
3987 **/
3988 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3989 {
3990 bool ret = false;
3991 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3992
3993 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3994 f->mask = 0xF;
3995 adapter->num_rx_queues = f->indices;
3996 adapter->num_tx_queues = f->indices;
3997 ret = true;
3998 } else {
3999 ret = false;
4000 }
4001
4002 return ret;
4003 }
4004
4005 /**
4006 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4007 * @adapter: board private structure to initialize
4008 *
4009 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4010 * to the original CPU that initiated the Tx session. This runs in addition
4011 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4012 * Rx load across CPUs using RSS.
4013 *
4014 **/
4015 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4016 {
4017 bool ret = false;
4018 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4019
4020 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4021 f_fdir->mask = 0;
4022
4023 /* Flow Director must have RSS enabled */
4024 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4025 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4026 adapter->num_tx_queues = f_fdir->indices;
4027 adapter->num_rx_queues = f_fdir->indices;
4028 ret = true;
4029 } else {
4030 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4031 }
4032 return ret;
4033 }
4034
4035 #ifdef IXGBE_FCOE
4036 /**
4037 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4038 * @adapter: board private structure to initialize
4039 *
4040 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4041 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4042 * rx queues out of the max number of rx queues, instead, it is used as the
4043 * index of the first rx queue used by FCoE.
4044 *
4045 **/
4046 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4047 {
4048 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4049
4050 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4051 return false;
4052
4053 f->indices = min((int)num_online_cpus(), f->indices);
4054
4055 adapter->num_rx_queues = 1;
4056 adapter->num_tx_queues = 1;
4057
4058 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4059 e_info(probe, "FCoE enabled with RSS\n");
4060 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4061 ixgbe_set_fdir_queues(adapter);
4062 else
4063 ixgbe_set_rss_queues(adapter);
4064 }
4065
4066 /* adding FCoE rx rings to the end */
4067 f->mask = adapter->num_rx_queues;
4068 adapter->num_rx_queues += f->indices;
4069 adapter->num_tx_queues += f->indices;
4070
4071 return true;
4072 }
4073 #endif /* IXGBE_FCOE */
4074
4075 /* Artificial max queue cap per traffic class in DCB mode */
4076 #define DCB_QUEUE_CAP 8
4077
4078 #ifdef CONFIG_IXGBE_DCB
4079 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4080 {
4081 int per_tc_q, q, i, offset = 0;
4082 struct net_device *dev = adapter->netdev;
4083 int tcs = netdev_get_num_tc(dev);
4084
4085 if (!tcs)
4086 return false;
4087
4088 /* Map queue offset and counts onto allocated tx queues */
4089 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4090 q = min((int)num_online_cpus(), per_tc_q);
4091
4092 for (i = 0; i < tcs; i++) {
4093 netdev_set_prio_tc_map(dev, i, i);
4094 netdev_set_tc_queue(dev, i, q, offset);
4095 offset += q;
4096 }
4097
4098 adapter->num_tx_queues = q * tcs;
4099 adapter->num_rx_queues = q * tcs;
4100
4101 #ifdef IXGBE_FCOE
4102 /* FCoE enabled queues require special configuration indexed
4103 * by feature specific indices and mask. Here we map FCoE
4104 * indices onto the DCB queue pairs allowing FCoE to own
4105 * configuration later.
4106 */
4107 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4108 int tc;
4109 struct ixgbe_ring_feature *f =
4110 &adapter->ring_feature[RING_F_FCOE];
4111
4112 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4113 f->indices = dev->tc_to_txq[tc].count;
4114 f->mask = dev->tc_to_txq[tc].offset;
4115 }
4116 #endif
4117
4118 return true;
4119 }
4120 #endif
4121
4122 /**
4123 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4124 * @adapter: board private structure to initialize
4125 *
4126 * IOV doesn't actually use anything, so just NAK the
4127 * request for now and let the other queue routines
4128 * figure out what to do.
4129 */
4130 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4131 {
4132 return false;
4133 }
4134
4135 /*
4136 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4137 * @adapter: board private structure to initialize
4138 *
4139 * This is the top level queue allocation routine. The order here is very
4140 * important, starting with the "most" number of features turned on at once,
4141 * and ending with the smallest set of features. This way large combinations
4142 * can be allocated if they're turned on, and smaller combinations are the
4143 * fallthrough conditions.
4144 *
4145 **/
4146 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4147 {
4148 /* Start with base case */
4149 adapter->num_rx_queues = 1;
4150 adapter->num_tx_queues = 1;
4151 adapter->num_rx_pools = adapter->num_rx_queues;
4152 adapter->num_rx_queues_per_pool = 1;
4153
4154 if (ixgbe_set_sriov_queues(adapter))
4155 goto done;
4156
4157 #ifdef CONFIG_IXGBE_DCB
4158 if (ixgbe_set_dcb_queues(adapter))
4159 goto done;
4160
4161 #endif
4162 #ifdef IXGBE_FCOE
4163 if (ixgbe_set_fcoe_queues(adapter))
4164 goto done;
4165
4166 #endif /* IXGBE_FCOE */
4167 if (ixgbe_set_fdir_queues(adapter))
4168 goto done;
4169
4170 if (ixgbe_set_rss_queues(adapter))
4171 goto done;
4172
4173 /* fallback to base case */
4174 adapter->num_rx_queues = 1;
4175 adapter->num_tx_queues = 1;
4176
4177 done:
4178 /* Notify the stack of the (possibly) reduced queue counts. */
4179 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4180 return netif_set_real_num_rx_queues(adapter->netdev,
4181 adapter->num_rx_queues);
4182 }
4183
4184 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4185 int vectors)
4186 {
4187 int err, vector_threshold;
4188
4189 /* We'll want at least 3 (vector_threshold):
4190 * 1) TxQ[0] Cleanup
4191 * 2) RxQ[0] Cleanup
4192 * 3) Other (Link Status Change, etc.)
4193 * 4) TCP Timer (optional)
4194 */
4195 vector_threshold = MIN_MSIX_COUNT;
4196
4197 /* The more we get, the more we will assign to Tx/Rx Cleanup
4198 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4199 * Right now, we simply care about how many we'll get; we'll
4200 * set them up later while requesting irq's.
4201 */
4202 while (vectors >= vector_threshold) {
4203 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4204 vectors);
4205 if (!err) /* Success in acquiring all requested vectors. */
4206 break;
4207 else if (err < 0)
4208 vectors = 0; /* Nasty failure, quit now */
4209 else /* err == number of vectors we should try again with */
4210 vectors = err;
4211 }
4212
4213 if (vectors < vector_threshold) {
4214 /* Can't allocate enough MSI-X interrupts? Oh well.
4215 * This just means we'll go with either a single MSI
4216 * vector or fall back to legacy interrupts.
4217 */
4218 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4219 "Unable to allocate MSI-X interrupts\n");
4220 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4221 kfree(adapter->msix_entries);
4222 adapter->msix_entries = NULL;
4223 } else {
4224 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4225 /*
4226 * Adjust for only the vectors we'll use, which is minimum
4227 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4228 * vectors we were allocated.
4229 */
4230 adapter->num_msix_vectors = min(vectors,
4231 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4232 }
4233 }
4234
4235 /**
4236 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4237 * @adapter: board private structure to initialize
4238 *
4239 * Cache the descriptor ring offsets for RSS to the assigned rings.
4240 *
4241 **/
4242 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4243 {
4244 int i;
4245
4246 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4247 return false;
4248
4249 for (i = 0; i < adapter->num_rx_queues; i++)
4250 adapter->rx_ring[i]->reg_idx = i;
4251 for (i = 0; i < adapter->num_tx_queues; i++)
4252 adapter->tx_ring[i]->reg_idx = i;
4253
4254 return true;
4255 }
4256
4257 #ifdef CONFIG_IXGBE_DCB
4258
4259 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4260 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4261 unsigned int *tx, unsigned int *rx)
4262 {
4263 struct net_device *dev = adapter->netdev;
4264 struct ixgbe_hw *hw = &adapter->hw;
4265 u8 num_tcs = netdev_get_num_tc(dev);
4266
4267 *tx = 0;
4268 *rx = 0;
4269
4270 switch (hw->mac.type) {
4271 case ixgbe_mac_82598EB:
4272 *tx = tc << 2;
4273 *rx = tc << 3;
4274 break;
4275 case ixgbe_mac_82599EB:
4276 case ixgbe_mac_X540:
4277 if (num_tcs > 4) {
4278 if (tc < 3) {
4279 *tx = tc << 5;
4280 *rx = tc << 4;
4281 } else if (tc < 5) {
4282 *tx = ((tc + 2) << 4);
4283 *rx = tc << 4;
4284 } else if (tc < num_tcs) {
4285 *tx = ((tc + 8) << 3);
4286 *rx = tc << 4;
4287 }
4288 } else {
4289 *rx = tc << 5;
4290 switch (tc) {
4291 case 0:
4292 *tx = 0;
4293 break;
4294 case 1:
4295 *tx = 64;
4296 break;
4297 case 2:
4298 *tx = 96;
4299 break;
4300 case 3:
4301 *tx = 112;
4302 break;
4303 default:
4304 break;
4305 }
4306 }
4307 break;
4308 default:
4309 break;
4310 }
4311 }
4312
4313 /**
4314 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4315 * @adapter: board private structure to initialize
4316 *
4317 * Cache the descriptor ring offsets for DCB to the assigned rings.
4318 *
4319 **/
4320 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4321 {
4322 struct net_device *dev = adapter->netdev;
4323 int i, j, k;
4324 u8 num_tcs = netdev_get_num_tc(dev);
4325
4326 if (!num_tcs)
4327 return false;
4328
4329 for (i = 0, k = 0; i < num_tcs; i++) {
4330 unsigned int tx_s, rx_s;
4331 u16 count = dev->tc_to_txq[i].count;
4332
4333 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4334 for (j = 0; j < count; j++, k++) {
4335 adapter->tx_ring[k]->reg_idx = tx_s + j;
4336 adapter->rx_ring[k]->reg_idx = rx_s + j;
4337 adapter->tx_ring[k]->dcb_tc = i;
4338 adapter->rx_ring[k]->dcb_tc = i;
4339 }
4340 }
4341
4342 return true;
4343 }
4344 #endif
4345
4346 /**
4347 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4348 * @adapter: board private structure to initialize
4349 *
4350 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4351 *
4352 **/
4353 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4354 {
4355 int i;
4356 bool ret = false;
4357
4358 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4359 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4360 for (i = 0; i < adapter->num_rx_queues; i++)
4361 adapter->rx_ring[i]->reg_idx = i;
4362 for (i = 0; i < adapter->num_tx_queues; i++)
4363 adapter->tx_ring[i]->reg_idx = i;
4364 ret = true;
4365 }
4366
4367 return ret;
4368 }
4369
4370 #ifdef IXGBE_FCOE
4371 /**
4372 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4373 * @adapter: board private structure to initialize
4374 *
4375 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4376 *
4377 */
4378 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4379 {
4380 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4381 int i;
4382 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4383
4384 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4385 return false;
4386
4387 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4388 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4389 ixgbe_cache_ring_fdir(adapter);
4390 else
4391 ixgbe_cache_ring_rss(adapter);
4392
4393 fcoe_rx_i = f->mask;
4394 fcoe_tx_i = f->mask;
4395 }
4396 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4397 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4398 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4399 }
4400 return true;
4401 }
4402
4403 #endif /* IXGBE_FCOE */
4404 /**
4405 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4406 * @adapter: board private structure to initialize
4407 *
4408 * SR-IOV doesn't use any descriptor rings but changes the default if
4409 * no other mapping is used.
4410 *
4411 */
4412 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4413 {
4414 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4415 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4416 if (adapter->num_vfs)
4417 return true;
4418 else
4419 return false;
4420 }
4421
4422 /**
4423 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4424 * @adapter: board private structure to initialize
4425 *
4426 * Once we know the feature-set enabled for the device, we'll cache
4427 * the register offset the descriptor ring is assigned to.
4428 *
4429 * Note, the order the various feature calls is important. It must start with
4430 * the "most" features enabled at the same time, then trickle down to the
4431 * least amount of features turned on at once.
4432 **/
4433 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4434 {
4435 /* start with default case */
4436 adapter->rx_ring[0]->reg_idx = 0;
4437 adapter->tx_ring[0]->reg_idx = 0;
4438
4439 if (ixgbe_cache_ring_sriov(adapter))
4440 return;
4441
4442 #ifdef CONFIG_IXGBE_DCB
4443 if (ixgbe_cache_ring_dcb(adapter))
4444 return;
4445 #endif
4446
4447 #ifdef IXGBE_FCOE
4448 if (ixgbe_cache_ring_fcoe(adapter))
4449 return;
4450 #endif /* IXGBE_FCOE */
4451
4452 if (ixgbe_cache_ring_fdir(adapter))
4453 return;
4454
4455 if (ixgbe_cache_ring_rss(adapter))
4456 return;
4457 }
4458
4459 /**
4460 * ixgbe_alloc_queues - Allocate memory for all rings
4461 * @adapter: board private structure to initialize
4462 *
4463 * We allocate one ring per queue at run-time since we don't know the
4464 * number of queues at compile-time. The polling_netdev array is
4465 * intended for Multiqueue, but should work fine with a single queue.
4466 **/
4467 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4468 {
4469 int rx = 0, tx = 0, nid = adapter->node;
4470
4471 if (nid < 0 || !node_online(nid))
4472 nid = first_online_node;
4473
4474 for (; tx < adapter->num_tx_queues; tx++) {
4475 struct ixgbe_ring *ring;
4476
4477 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4478 if (!ring)
4479 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4480 if (!ring)
4481 goto err_allocation;
4482 ring->count = adapter->tx_ring_count;
4483 ring->queue_index = tx;
4484 ring->numa_node = nid;
4485 ring->dev = &adapter->pdev->dev;
4486 ring->netdev = adapter->netdev;
4487
4488 adapter->tx_ring[tx] = ring;
4489 }
4490
4491 for (; rx < adapter->num_rx_queues; rx++) {
4492 struct ixgbe_ring *ring;
4493
4494 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4495 if (!ring)
4496 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4497 if (!ring)
4498 goto err_allocation;
4499 ring->count = adapter->rx_ring_count;
4500 ring->queue_index = rx;
4501 ring->numa_node = nid;
4502 ring->dev = &adapter->pdev->dev;
4503 ring->netdev = adapter->netdev;
4504
4505 adapter->rx_ring[rx] = ring;
4506 }
4507
4508 ixgbe_cache_ring_register(adapter);
4509
4510 return 0;
4511
4512 err_allocation:
4513 while (tx)
4514 kfree(adapter->tx_ring[--tx]);
4515
4516 while (rx)
4517 kfree(adapter->rx_ring[--rx]);
4518 return -ENOMEM;
4519 }
4520
4521 /**
4522 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4523 * @adapter: board private structure to initialize
4524 *
4525 * Attempt to configure the interrupts using the best available
4526 * capabilities of the hardware and the kernel.
4527 **/
4528 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4529 {
4530 struct ixgbe_hw *hw = &adapter->hw;
4531 int err = 0;
4532 int vector, v_budget;
4533
4534 /*
4535 * It's easy to be greedy for MSI-X vectors, but it really
4536 * doesn't do us much good if we have a lot more vectors
4537 * than CPU's. So let's be conservative and only ask for
4538 * (roughly) the same number of vectors as there are CPU's.
4539 */
4540 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4541 (int)num_online_cpus()) + NON_Q_VECTORS;
4542
4543 /*
4544 * At the same time, hardware can only support a maximum of
4545 * hw.mac->max_msix_vectors vectors. With features
4546 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4547 * descriptor queues supported by our device. Thus, we cap it off in
4548 * those rare cases where the cpu count also exceeds our vector limit.
4549 */
4550 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4551
4552 /* A failure in MSI-X entry allocation isn't fatal, but it does
4553 * mean we disable MSI-X capabilities of the adapter. */
4554 adapter->msix_entries = kcalloc(v_budget,
4555 sizeof(struct msix_entry), GFP_KERNEL);
4556 if (adapter->msix_entries) {
4557 for (vector = 0; vector < v_budget; vector++)
4558 adapter->msix_entries[vector].entry = vector;
4559
4560 ixgbe_acquire_msix_vectors(adapter, v_budget);
4561
4562 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4563 goto out;
4564 }
4565
4566 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4567 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4568 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4569 e_err(probe,
4570 "ATR is not supported while multiple "
4571 "queues are disabled. Disabling Flow Director\n");
4572 }
4573 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4574 adapter->atr_sample_rate = 0;
4575 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4576 ixgbe_disable_sriov(adapter);
4577
4578 err = ixgbe_set_num_queues(adapter);
4579 if (err)
4580 return err;
4581
4582 err = pci_enable_msi(adapter->pdev);
4583 if (!err) {
4584 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4585 } else {
4586 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4587 "Unable to allocate MSI interrupt, "
4588 "falling back to legacy. Error: %d\n", err);
4589 /* reset err */
4590 err = 0;
4591 }
4592
4593 out:
4594 return err;
4595 }
4596
4597 /**
4598 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4599 * @adapter: board private structure to initialize
4600 *
4601 * We allocate one q_vector per queue interrupt. If allocation fails we
4602 * return -ENOMEM.
4603 **/
4604 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4605 {
4606 int v_idx, num_q_vectors;
4607 struct ixgbe_q_vector *q_vector;
4608
4609 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4610 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4611 else
4612 num_q_vectors = 1;
4613
4614 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4615 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4616 GFP_KERNEL, adapter->node);
4617 if (!q_vector)
4618 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4619 GFP_KERNEL);
4620 if (!q_vector)
4621 goto err_out;
4622
4623 q_vector->adapter = adapter;
4624 q_vector->v_idx = v_idx;
4625
4626 /* Allocate the affinity_hint cpumask, configure the mask */
4627 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4628 goto err_out;
4629 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4630
4631 if (q_vector->tx.count && !q_vector->rx.count)
4632 q_vector->eitr = adapter->tx_eitr_param;
4633 else
4634 q_vector->eitr = adapter->rx_eitr_param;
4635
4636 netif_napi_add(adapter->netdev, &q_vector->napi,
4637 ixgbe_poll, 64);
4638 adapter->q_vector[v_idx] = q_vector;
4639 }
4640
4641 return 0;
4642
4643 err_out:
4644 while (v_idx) {
4645 v_idx--;
4646 q_vector = adapter->q_vector[v_idx];
4647 netif_napi_del(&q_vector->napi);
4648 free_cpumask_var(q_vector->affinity_mask);
4649 kfree(q_vector);
4650 adapter->q_vector[v_idx] = NULL;
4651 }
4652 return -ENOMEM;
4653 }
4654
4655 /**
4656 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4657 * @adapter: board private structure to initialize
4658 *
4659 * This function frees the memory allocated to the q_vectors. In addition if
4660 * NAPI is enabled it will delete any references to the NAPI struct prior
4661 * to freeing the q_vector.
4662 **/
4663 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4664 {
4665 int v_idx, num_q_vectors;
4666
4667 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4668 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4669 else
4670 num_q_vectors = 1;
4671
4672 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4673 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4674 adapter->q_vector[v_idx] = NULL;
4675 netif_napi_del(&q_vector->napi);
4676 free_cpumask_var(q_vector->affinity_mask);
4677 kfree(q_vector);
4678 }
4679 }
4680
4681 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4682 {
4683 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4684 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4685 pci_disable_msix(adapter->pdev);
4686 kfree(adapter->msix_entries);
4687 adapter->msix_entries = NULL;
4688 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4689 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4690 pci_disable_msi(adapter->pdev);
4691 }
4692 }
4693
4694 /**
4695 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4696 * @adapter: board private structure to initialize
4697 *
4698 * We determine which interrupt scheme to use based on...
4699 * - Kernel support (MSI, MSI-X)
4700 * - which can be user-defined (via MODULE_PARAM)
4701 * - Hardware queue count (num_*_queues)
4702 * - defined by miscellaneous hardware support/features (RSS, etc.)
4703 **/
4704 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4705 {
4706 int err;
4707
4708 /* Number of supported queues */
4709 err = ixgbe_set_num_queues(adapter);
4710 if (err)
4711 return err;
4712
4713 err = ixgbe_set_interrupt_capability(adapter);
4714 if (err) {
4715 e_dev_err("Unable to setup interrupt capabilities\n");
4716 goto err_set_interrupt;
4717 }
4718
4719 err = ixgbe_alloc_q_vectors(adapter);
4720 if (err) {
4721 e_dev_err("Unable to allocate memory for queue vectors\n");
4722 goto err_alloc_q_vectors;
4723 }
4724
4725 err = ixgbe_alloc_queues(adapter);
4726 if (err) {
4727 e_dev_err("Unable to allocate memory for queues\n");
4728 goto err_alloc_queues;
4729 }
4730
4731 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4732 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4733 adapter->num_rx_queues, adapter->num_tx_queues);
4734
4735 set_bit(__IXGBE_DOWN, &adapter->state);
4736
4737 return 0;
4738
4739 err_alloc_queues:
4740 ixgbe_free_q_vectors(adapter);
4741 err_alloc_q_vectors:
4742 ixgbe_reset_interrupt_capability(adapter);
4743 err_set_interrupt:
4744 return err;
4745 }
4746
4747 /**
4748 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4749 * @adapter: board private structure to clear interrupt scheme on
4750 *
4751 * We go through and clear interrupt specific resources and reset the structure
4752 * to pre-load conditions
4753 **/
4754 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4755 {
4756 int i;
4757
4758 for (i = 0; i < adapter->num_tx_queues; i++) {
4759 kfree(adapter->tx_ring[i]);
4760 adapter->tx_ring[i] = NULL;
4761 }
4762 for (i = 0; i < adapter->num_rx_queues; i++) {
4763 struct ixgbe_ring *ring = adapter->rx_ring[i];
4764
4765 /* ixgbe_get_stats64() might access this ring, we must wait
4766 * a grace period before freeing it.
4767 */
4768 kfree_rcu(ring, rcu);
4769 adapter->rx_ring[i] = NULL;
4770 }
4771
4772 adapter->num_tx_queues = 0;
4773 adapter->num_rx_queues = 0;
4774
4775 ixgbe_free_q_vectors(adapter);
4776 ixgbe_reset_interrupt_capability(adapter);
4777 }
4778
4779 /**
4780 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4781 * @adapter: board private structure to initialize
4782 *
4783 * ixgbe_sw_init initializes the Adapter private data structure.
4784 * Fields are initialized based on PCI device information and
4785 * OS network device settings (MTU size).
4786 **/
4787 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4788 {
4789 struct ixgbe_hw *hw = &adapter->hw;
4790 struct pci_dev *pdev = adapter->pdev;
4791 struct net_device *dev = adapter->netdev;
4792 unsigned int rss;
4793 #ifdef CONFIG_IXGBE_DCB
4794 int j;
4795 struct tc_configuration *tc;
4796 #endif
4797 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4798
4799 /* PCI config space info */
4800
4801 hw->vendor_id = pdev->vendor;
4802 hw->device_id = pdev->device;
4803 hw->revision_id = pdev->revision;
4804 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4805 hw->subsystem_device_id = pdev->subsystem_device;
4806
4807 /* Set capability flags */
4808 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4809 adapter->ring_feature[RING_F_RSS].indices = rss;
4810 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4811 switch (hw->mac.type) {
4812 case ixgbe_mac_82598EB:
4813 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4814 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4815 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4816 break;
4817 case ixgbe_mac_82599EB:
4818 case ixgbe_mac_X540:
4819 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4820 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4821 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4822 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4823 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4824 /* Flow Director hash filters enabled */
4825 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4826 adapter->atr_sample_rate = 20;
4827 adapter->ring_feature[RING_F_FDIR].indices =
4828 IXGBE_MAX_FDIR_INDICES;
4829 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4830 #ifdef IXGBE_FCOE
4831 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4832 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4833 adapter->ring_feature[RING_F_FCOE].indices = 0;
4834 #ifdef CONFIG_IXGBE_DCB
4835 /* Default traffic class to use for FCoE */
4836 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4837 #endif
4838 #endif /* IXGBE_FCOE */
4839 break;
4840 default:
4841 break;
4842 }
4843
4844 /* n-tuple support exists, always init our spinlock */
4845 spin_lock_init(&adapter->fdir_perfect_lock);
4846
4847 #ifdef CONFIG_IXGBE_DCB
4848 /* Configure DCB traffic classes */
4849 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4850 tc = &adapter->dcb_cfg.tc_config[j];
4851 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4852 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4853 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4854 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4855 tc->dcb_pfc = pfc_disabled;
4856 }
4857 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4858 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4859 adapter->dcb_cfg.pfc_mode_enable = false;
4860 adapter->dcb_set_bitmap = 0x00;
4861 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4862 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4863 MAX_TRAFFIC_CLASS);
4864
4865 #endif
4866
4867 /* default flow control settings */
4868 hw->fc.requested_mode = ixgbe_fc_full;
4869 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4870 #ifdef CONFIG_DCB
4871 adapter->last_lfc_mode = hw->fc.current_mode;
4872 #endif
4873 hw->fc.high_water = FC_HIGH_WATER(max_frame);
4874 hw->fc.low_water = FC_LOW_WATER(max_frame);
4875 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4876 hw->fc.send_xon = true;
4877 hw->fc.disable_fc_autoneg = false;
4878
4879 /* enable itr by default in dynamic mode */
4880 adapter->rx_itr_setting = 1;
4881 adapter->rx_eitr_param = 20000;
4882 adapter->tx_itr_setting = 1;
4883 adapter->tx_eitr_param = 10000;
4884
4885 /* set defaults for eitr in MegaBytes */
4886 adapter->eitr_low = 10;
4887 adapter->eitr_high = 20;
4888
4889 /* set default ring sizes */
4890 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4891 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4892
4893 /* set default work limits */
4894 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4895
4896 /* initialize eeprom parameters */
4897 if (ixgbe_init_eeprom_params_generic(hw)) {
4898 e_dev_err("EEPROM initialization failed\n");
4899 return -EIO;
4900 }
4901
4902 /* enable rx csum by default */
4903 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4904
4905 /* get assigned NUMA node */
4906 adapter->node = dev_to_node(&pdev->dev);
4907
4908 set_bit(__IXGBE_DOWN, &adapter->state);
4909
4910 return 0;
4911 }
4912
4913 /**
4914 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4915 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4916 *
4917 * Return 0 on success, negative on failure
4918 **/
4919 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4920 {
4921 struct device *dev = tx_ring->dev;
4922 int size;
4923
4924 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4925 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
4926 if (!tx_ring->tx_buffer_info)
4927 tx_ring->tx_buffer_info = vzalloc(size);
4928 if (!tx_ring->tx_buffer_info)
4929 goto err;
4930
4931 /* round up to nearest 4K */
4932 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4933 tx_ring->size = ALIGN(tx_ring->size, 4096);
4934
4935 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4936 &tx_ring->dma, GFP_KERNEL);
4937 if (!tx_ring->desc)
4938 goto err;
4939
4940 tx_ring->next_to_use = 0;
4941 tx_ring->next_to_clean = 0;
4942 return 0;
4943
4944 err:
4945 vfree(tx_ring->tx_buffer_info);
4946 tx_ring->tx_buffer_info = NULL;
4947 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4948 return -ENOMEM;
4949 }
4950
4951 /**
4952 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4953 * @adapter: board private structure
4954 *
4955 * If this function returns with an error, then it's possible one or
4956 * more of the rings is populated (while the rest are not). It is the
4957 * callers duty to clean those orphaned rings.
4958 *
4959 * Return 0 on success, negative on failure
4960 **/
4961 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4962 {
4963 int i, err = 0;
4964
4965 for (i = 0; i < adapter->num_tx_queues; i++) {
4966 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4967 if (!err)
4968 continue;
4969 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4970 break;
4971 }
4972
4973 return err;
4974 }
4975
4976 /**
4977 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4978 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4979 *
4980 * Returns 0 on success, negative on failure
4981 **/
4982 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4983 {
4984 struct device *dev = rx_ring->dev;
4985 int size;
4986
4987 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4988 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
4989 if (!rx_ring->rx_buffer_info)
4990 rx_ring->rx_buffer_info = vzalloc(size);
4991 if (!rx_ring->rx_buffer_info)
4992 goto err;
4993
4994 /* Round up to nearest 4K */
4995 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4996 rx_ring->size = ALIGN(rx_ring->size, 4096);
4997
4998 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4999 &rx_ring->dma, GFP_KERNEL);
5000
5001 if (!rx_ring->desc)
5002 goto err;
5003
5004 rx_ring->next_to_clean = 0;
5005 rx_ring->next_to_use = 0;
5006
5007 return 0;
5008 err:
5009 vfree(rx_ring->rx_buffer_info);
5010 rx_ring->rx_buffer_info = NULL;
5011 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5012 return -ENOMEM;
5013 }
5014
5015 /**
5016 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5017 * @adapter: board private structure
5018 *
5019 * If this function returns with an error, then it's possible one or
5020 * more of the rings is populated (while the rest are not). It is the
5021 * callers duty to clean those orphaned rings.
5022 *
5023 * Return 0 on success, negative on failure
5024 **/
5025 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5026 {
5027 int i, err = 0;
5028
5029 for (i = 0; i < adapter->num_rx_queues; i++) {
5030 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5031 if (!err)
5032 continue;
5033 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5034 break;
5035 }
5036
5037 return err;
5038 }
5039
5040 /**
5041 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5042 * @tx_ring: Tx descriptor ring for a specific queue
5043 *
5044 * Free all transmit software resources
5045 **/
5046 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5047 {
5048 ixgbe_clean_tx_ring(tx_ring);
5049
5050 vfree(tx_ring->tx_buffer_info);
5051 tx_ring->tx_buffer_info = NULL;
5052
5053 /* if not set, then don't free */
5054 if (!tx_ring->desc)
5055 return;
5056
5057 dma_free_coherent(tx_ring->dev, tx_ring->size,
5058 tx_ring->desc, tx_ring->dma);
5059
5060 tx_ring->desc = NULL;
5061 }
5062
5063 /**
5064 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5065 * @adapter: board private structure
5066 *
5067 * Free all transmit software resources
5068 **/
5069 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5070 {
5071 int i;
5072
5073 for (i = 0; i < adapter->num_tx_queues; i++)
5074 if (adapter->tx_ring[i]->desc)
5075 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5076 }
5077
5078 /**
5079 * ixgbe_free_rx_resources - Free Rx Resources
5080 * @rx_ring: ring to clean the resources from
5081 *
5082 * Free all receive software resources
5083 **/
5084 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5085 {
5086 ixgbe_clean_rx_ring(rx_ring);
5087
5088 vfree(rx_ring->rx_buffer_info);
5089 rx_ring->rx_buffer_info = NULL;
5090
5091 /* if not set, then don't free */
5092 if (!rx_ring->desc)
5093 return;
5094
5095 dma_free_coherent(rx_ring->dev, rx_ring->size,
5096 rx_ring->desc, rx_ring->dma);
5097
5098 rx_ring->desc = NULL;
5099 }
5100
5101 /**
5102 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5103 * @adapter: board private structure
5104 *
5105 * Free all receive software resources
5106 **/
5107 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5108 {
5109 int i;
5110
5111 for (i = 0; i < adapter->num_rx_queues; i++)
5112 if (adapter->rx_ring[i]->desc)
5113 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5114 }
5115
5116 /**
5117 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5118 * @netdev: network interface device structure
5119 * @new_mtu: new value for maximum frame size
5120 *
5121 * Returns 0 on success, negative on failure
5122 **/
5123 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5124 {
5125 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5126 struct ixgbe_hw *hw = &adapter->hw;
5127 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5128
5129 /* MTU < 68 is an error and causes problems on some kernels */
5130 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5131 hw->mac.type != ixgbe_mac_X540) {
5132 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5133 return -EINVAL;
5134 } else {
5135 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5136 return -EINVAL;
5137 }
5138
5139 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5140 /* must set new MTU before calling down or up */
5141 netdev->mtu = new_mtu;
5142
5143 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5144 hw->fc.low_water = FC_LOW_WATER(max_frame);
5145
5146 if (netif_running(netdev))
5147 ixgbe_reinit_locked(adapter);
5148
5149 return 0;
5150 }
5151
5152 /**
5153 * ixgbe_open - Called when a network interface is made active
5154 * @netdev: network interface device structure
5155 *
5156 * Returns 0 on success, negative value on failure
5157 *
5158 * The open entry point is called when a network interface is made
5159 * active by the system (IFF_UP). At this point all resources needed
5160 * for transmit and receive operations are allocated, the interrupt
5161 * handler is registered with the OS, the watchdog timer is started,
5162 * and the stack is notified that the interface is ready.
5163 **/
5164 static int ixgbe_open(struct net_device *netdev)
5165 {
5166 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5167 int err;
5168
5169 /* disallow open during test */
5170 if (test_bit(__IXGBE_TESTING, &adapter->state))
5171 return -EBUSY;
5172
5173 netif_carrier_off(netdev);
5174
5175 /* allocate transmit descriptors */
5176 err = ixgbe_setup_all_tx_resources(adapter);
5177 if (err)
5178 goto err_setup_tx;
5179
5180 /* allocate receive descriptors */
5181 err = ixgbe_setup_all_rx_resources(adapter);
5182 if (err)
5183 goto err_setup_rx;
5184
5185 ixgbe_configure(adapter);
5186
5187 err = ixgbe_request_irq(adapter);
5188 if (err)
5189 goto err_req_irq;
5190
5191 ixgbe_up_complete(adapter);
5192
5193 netif_tx_start_all_queues(netdev);
5194
5195 return 0;
5196
5197 err_req_irq:
5198 err_setup_rx:
5199 ixgbe_free_all_rx_resources(adapter);
5200 err_setup_tx:
5201 ixgbe_free_all_tx_resources(adapter);
5202 ixgbe_reset(adapter);
5203
5204 return err;
5205 }
5206
5207 /**
5208 * ixgbe_close - Disables a network interface
5209 * @netdev: network interface device structure
5210 *
5211 * Returns 0, this is not allowed to fail
5212 *
5213 * The close entry point is called when an interface is de-activated
5214 * by the OS. The hardware is still under the drivers control, but
5215 * needs to be disabled. A global MAC reset is issued to stop the
5216 * hardware, and all transmit and receive resources are freed.
5217 **/
5218 static int ixgbe_close(struct net_device *netdev)
5219 {
5220 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5221
5222 ixgbe_down(adapter);
5223 ixgbe_free_irq(adapter);
5224
5225 ixgbe_fdir_filter_exit(adapter);
5226
5227 ixgbe_free_all_tx_resources(adapter);
5228 ixgbe_free_all_rx_resources(adapter);
5229
5230 ixgbe_release_hw_control(adapter);
5231
5232 return 0;
5233 }
5234
5235 #ifdef CONFIG_PM
5236 static int ixgbe_resume(struct pci_dev *pdev)
5237 {
5238 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5239 struct net_device *netdev = adapter->netdev;
5240 u32 err;
5241
5242 pci_set_power_state(pdev, PCI_D0);
5243 pci_restore_state(pdev);
5244 /*
5245 * pci_restore_state clears dev->state_saved so call
5246 * pci_save_state to restore it.
5247 */
5248 pci_save_state(pdev);
5249
5250 err = pci_enable_device_mem(pdev);
5251 if (err) {
5252 e_dev_err("Cannot enable PCI device from suspend\n");
5253 return err;
5254 }
5255 pci_set_master(pdev);
5256
5257 pci_wake_from_d3(pdev, false);
5258
5259 err = ixgbe_init_interrupt_scheme(adapter);
5260 if (err) {
5261 e_dev_err("Cannot initialize interrupts for device\n");
5262 return err;
5263 }
5264
5265 ixgbe_reset(adapter);
5266
5267 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5268
5269 if (netif_running(netdev)) {
5270 err = ixgbe_open(netdev);
5271 if (err)
5272 return err;
5273 }
5274
5275 netif_device_attach(netdev);
5276
5277 return 0;
5278 }
5279 #endif /* CONFIG_PM */
5280
5281 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5282 {
5283 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5284 struct net_device *netdev = adapter->netdev;
5285 struct ixgbe_hw *hw = &adapter->hw;
5286 u32 ctrl, fctrl;
5287 u32 wufc = adapter->wol;
5288 #ifdef CONFIG_PM
5289 int retval = 0;
5290 #endif
5291
5292 netif_device_detach(netdev);
5293
5294 if (netif_running(netdev)) {
5295 ixgbe_down(adapter);
5296 ixgbe_free_irq(adapter);
5297 ixgbe_free_all_tx_resources(adapter);
5298 ixgbe_free_all_rx_resources(adapter);
5299 }
5300
5301 ixgbe_clear_interrupt_scheme(adapter);
5302 #ifdef CONFIG_DCB
5303 kfree(adapter->ixgbe_ieee_pfc);
5304 kfree(adapter->ixgbe_ieee_ets);
5305 #endif
5306
5307 #ifdef CONFIG_PM
5308 retval = pci_save_state(pdev);
5309 if (retval)
5310 return retval;
5311
5312 #endif
5313 if (wufc) {
5314 ixgbe_set_rx_mode(netdev);
5315
5316 /* turn on all-multi mode if wake on multicast is enabled */
5317 if (wufc & IXGBE_WUFC_MC) {
5318 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5319 fctrl |= IXGBE_FCTRL_MPE;
5320 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5321 }
5322
5323 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5324 ctrl |= IXGBE_CTRL_GIO_DIS;
5325 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5326
5327 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5328 } else {
5329 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5330 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5331 }
5332
5333 switch (hw->mac.type) {
5334 case ixgbe_mac_82598EB:
5335 pci_wake_from_d3(pdev, false);
5336 break;
5337 case ixgbe_mac_82599EB:
5338 case ixgbe_mac_X540:
5339 pci_wake_from_d3(pdev, !!wufc);
5340 break;
5341 default:
5342 break;
5343 }
5344
5345 *enable_wake = !!wufc;
5346
5347 ixgbe_release_hw_control(adapter);
5348
5349 pci_disable_device(pdev);
5350
5351 return 0;
5352 }
5353
5354 #ifdef CONFIG_PM
5355 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5356 {
5357 int retval;
5358 bool wake;
5359
5360 retval = __ixgbe_shutdown(pdev, &wake);
5361 if (retval)
5362 return retval;
5363
5364 if (wake) {
5365 pci_prepare_to_sleep(pdev);
5366 } else {
5367 pci_wake_from_d3(pdev, false);
5368 pci_set_power_state(pdev, PCI_D3hot);
5369 }
5370
5371 return 0;
5372 }
5373 #endif /* CONFIG_PM */
5374
5375 static void ixgbe_shutdown(struct pci_dev *pdev)
5376 {
5377 bool wake;
5378
5379 __ixgbe_shutdown(pdev, &wake);
5380
5381 if (system_state == SYSTEM_POWER_OFF) {
5382 pci_wake_from_d3(pdev, wake);
5383 pci_set_power_state(pdev, PCI_D3hot);
5384 }
5385 }
5386
5387 /**
5388 * ixgbe_update_stats - Update the board statistics counters.
5389 * @adapter: board private structure
5390 **/
5391 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5392 {
5393 struct net_device *netdev = adapter->netdev;
5394 struct ixgbe_hw *hw = &adapter->hw;
5395 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5396 u64 total_mpc = 0;
5397 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5398 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5399 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5400 u64 bytes = 0, packets = 0;
5401
5402 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5403 test_bit(__IXGBE_RESETTING, &adapter->state))
5404 return;
5405
5406 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5407 u64 rsc_count = 0;
5408 u64 rsc_flush = 0;
5409 for (i = 0; i < 16; i++)
5410 adapter->hw_rx_no_dma_resources +=
5411 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5412 for (i = 0; i < adapter->num_rx_queues; i++) {
5413 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5414 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5415 }
5416 adapter->rsc_total_count = rsc_count;
5417 adapter->rsc_total_flush = rsc_flush;
5418 }
5419
5420 for (i = 0; i < adapter->num_rx_queues; i++) {
5421 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5422 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5423 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5424 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5425 bytes += rx_ring->stats.bytes;
5426 packets += rx_ring->stats.packets;
5427 }
5428 adapter->non_eop_descs = non_eop_descs;
5429 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5430 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5431 netdev->stats.rx_bytes = bytes;
5432 netdev->stats.rx_packets = packets;
5433
5434 bytes = 0;
5435 packets = 0;
5436 /* gather some stats to the adapter struct that are per queue */
5437 for (i = 0; i < adapter->num_tx_queues; i++) {
5438 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5439 restart_queue += tx_ring->tx_stats.restart_queue;
5440 tx_busy += tx_ring->tx_stats.tx_busy;
5441 bytes += tx_ring->stats.bytes;
5442 packets += tx_ring->stats.packets;
5443 }
5444 adapter->restart_queue = restart_queue;
5445 adapter->tx_busy = tx_busy;
5446 netdev->stats.tx_bytes = bytes;
5447 netdev->stats.tx_packets = packets;
5448
5449 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5450 for (i = 0; i < 8; i++) {
5451 /* for packet buffers not used, the register should read 0 */
5452 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5453 missed_rx += mpc;
5454 hwstats->mpc[i] += mpc;
5455 total_mpc += hwstats->mpc[i];
5456 if (hw->mac.type == ixgbe_mac_82598EB)
5457 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5458 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5459 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5460 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5461 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5462 switch (hw->mac.type) {
5463 case ixgbe_mac_82598EB:
5464 hwstats->pxonrxc[i] +=
5465 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5466 break;
5467 case ixgbe_mac_82599EB:
5468 case ixgbe_mac_X540:
5469 hwstats->pxonrxc[i] +=
5470 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5471 break;
5472 default:
5473 break;
5474 }
5475 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5476 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5477 }
5478 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5479 /* work around hardware counting issue */
5480 hwstats->gprc -= missed_rx;
5481
5482 ixgbe_update_xoff_received(adapter);
5483
5484 /* 82598 hardware only has a 32 bit counter in the high register */
5485 switch (hw->mac.type) {
5486 case ixgbe_mac_82598EB:
5487 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5488 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5489 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5490 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5491 break;
5492 case ixgbe_mac_X540:
5493 /* OS2BMC stats are X540 only*/
5494 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5495 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5496 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5497 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5498 case ixgbe_mac_82599EB:
5499 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5500 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5501 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5502 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5503 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5504 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5505 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5506 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5507 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5508 #ifdef IXGBE_FCOE
5509 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5510 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5511 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5512 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5513 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5514 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5515 #endif /* IXGBE_FCOE */
5516 break;
5517 default:
5518 break;
5519 }
5520 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5521 hwstats->bprc += bprc;
5522 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5523 if (hw->mac.type == ixgbe_mac_82598EB)
5524 hwstats->mprc -= bprc;
5525 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5526 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5527 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5528 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5529 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5530 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5531 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5532 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5533 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5534 hwstats->lxontxc += lxon;
5535 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5536 hwstats->lxofftxc += lxoff;
5537 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5538 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5539 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5540 /*
5541 * 82598 errata - tx of flow control packets is included in tx counters
5542 */
5543 xon_off_tot = lxon + lxoff;
5544 hwstats->gptc -= xon_off_tot;
5545 hwstats->mptc -= xon_off_tot;
5546 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5547 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5548 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5549 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5550 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5551 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5552 hwstats->ptc64 -= xon_off_tot;
5553 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5554 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5555 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5556 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5557 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5558 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5559
5560 /* Fill out the OS statistics structure */
5561 netdev->stats.multicast = hwstats->mprc;
5562
5563 /* Rx Errors */
5564 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5565 netdev->stats.rx_dropped = 0;
5566 netdev->stats.rx_length_errors = hwstats->rlec;
5567 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5568 netdev->stats.rx_missed_errors = total_mpc;
5569 }
5570
5571 /**
5572 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5573 * @adapter - pointer to the device adapter structure
5574 **/
5575 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5576 {
5577 struct ixgbe_hw *hw = &adapter->hw;
5578 int i;
5579
5580 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5581 return;
5582
5583 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5584
5585 /* if interface is down do nothing */
5586 if (test_bit(__IXGBE_DOWN, &adapter->state))
5587 return;
5588
5589 /* do nothing if we are not using signature filters */
5590 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5591 return;
5592
5593 adapter->fdir_overflow++;
5594
5595 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5596 for (i = 0; i < adapter->num_tx_queues; i++)
5597 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5598 &(adapter->tx_ring[i]->state));
5599 /* re-enable flow director interrupts */
5600 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5601 } else {
5602 e_err(probe, "failed to finish FDIR re-initialization, "
5603 "ignored adding FDIR ATR filters\n");
5604 }
5605 }
5606
5607 /**
5608 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5609 * @adapter - pointer to the device adapter structure
5610 *
5611 * This function serves two purposes. First it strobes the interrupt lines
5612 * in order to make certain interrupts are occuring. Secondly it sets the
5613 * bits needed to check for TX hangs. As a result we should immediately
5614 * determine if a hang has occured.
5615 */
5616 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5617 {
5618 struct ixgbe_hw *hw = &adapter->hw;
5619 u64 eics = 0;
5620 int i;
5621
5622 /* If we're down or resetting, just bail */
5623 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5624 test_bit(__IXGBE_RESETTING, &adapter->state))
5625 return;
5626
5627 /* Force detection of hung controller */
5628 if (netif_carrier_ok(adapter->netdev)) {
5629 for (i = 0; i < adapter->num_tx_queues; i++)
5630 set_check_for_tx_hang(adapter->tx_ring[i]);
5631 }
5632
5633 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5634 /*
5635 * for legacy and MSI interrupts don't set any bits
5636 * that are enabled for EIAM, because this operation
5637 * would set *both* EIMS and EICS for any bit in EIAM
5638 */
5639 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5640 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5641 } else {
5642 /* get one bit for every active tx/rx interrupt vector */
5643 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5644 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5645 if (qv->rx.ring || qv->tx.ring)
5646 eics |= ((u64)1 << i);
5647 }
5648 }
5649
5650 /* Cause software interrupt to ensure rings are cleaned */
5651 ixgbe_irq_rearm_queues(adapter, eics);
5652
5653 }
5654
5655 /**
5656 * ixgbe_watchdog_update_link - update the link status
5657 * @adapter - pointer to the device adapter structure
5658 * @link_speed - pointer to a u32 to store the link_speed
5659 **/
5660 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5661 {
5662 struct ixgbe_hw *hw = &adapter->hw;
5663 u32 link_speed = adapter->link_speed;
5664 bool link_up = adapter->link_up;
5665 int i;
5666
5667 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5668 return;
5669
5670 if (hw->mac.ops.check_link) {
5671 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5672 } else {
5673 /* always assume link is up, if no check link function */
5674 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5675 link_up = true;
5676 }
5677 if (link_up) {
5678 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5679 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5680 hw->mac.ops.fc_enable(hw, i);
5681 } else {
5682 hw->mac.ops.fc_enable(hw, 0);
5683 }
5684 }
5685
5686 if (link_up ||
5687 time_after(jiffies, (adapter->link_check_timeout +
5688 IXGBE_TRY_LINK_TIMEOUT))) {
5689 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5690 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5691 IXGBE_WRITE_FLUSH(hw);
5692 }
5693
5694 adapter->link_up = link_up;
5695 adapter->link_speed = link_speed;
5696 }
5697
5698 /**
5699 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5700 * print link up message
5701 * @adapter - pointer to the device adapter structure
5702 **/
5703 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5704 {
5705 struct net_device *netdev = adapter->netdev;
5706 struct ixgbe_hw *hw = &adapter->hw;
5707 u32 link_speed = adapter->link_speed;
5708 bool flow_rx, flow_tx;
5709
5710 /* only continue if link was previously down */
5711 if (netif_carrier_ok(netdev))
5712 return;
5713
5714 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5715
5716 switch (hw->mac.type) {
5717 case ixgbe_mac_82598EB: {
5718 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5719 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5720 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5721 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5722 }
5723 break;
5724 case ixgbe_mac_X540:
5725 case ixgbe_mac_82599EB: {
5726 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5727 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5728 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5729 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5730 }
5731 break;
5732 default:
5733 flow_tx = false;
5734 flow_rx = false;
5735 break;
5736 }
5737 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5738 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5739 "10 Gbps" :
5740 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5741 "1 Gbps" :
5742 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5743 "100 Mbps" :
5744 "unknown speed"))),
5745 ((flow_rx && flow_tx) ? "RX/TX" :
5746 (flow_rx ? "RX" :
5747 (flow_tx ? "TX" : "None"))));
5748
5749 netif_carrier_on(netdev);
5750 ixgbe_check_vf_rate_limit(adapter);
5751 }
5752
5753 /**
5754 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5755 * print link down message
5756 * @adapter - pointer to the adapter structure
5757 **/
5758 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
5759 {
5760 struct net_device *netdev = adapter->netdev;
5761 struct ixgbe_hw *hw = &adapter->hw;
5762
5763 adapter->link_up = false;
5764 adapter->link_speed = 0;
5765
5766 /* only continue if link was up previously */
5767 if (!netif_carrier_ok(netdev))
5768 return;
5769
5770 /* poll for SFP+ cable when link is down */
5771 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5772 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5773
5774 e_info(drv, "NIC Link is Down\n");
5775 netif_carrier_off(netdev);
5776 }
5777
5778 /**
5779 * ixgbe_watchdog_flush_tx - flush queues on link down
5780 * @adapter - pointer to the device adapter structure
5781 **/
5782 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5783 {
5784 int i;
5785 int some_tx_pending = 0;
5786
5787 if (!netif_carrier_ok(adapter->netdev)) {
5788 for (i = 0; i < adapter->num_tx_queues; i++) {
5789 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5790 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5791 some_tx_pending = 1;
5792 break;
5793 }
5794 }
5795
5796 if (some_tx_pending) {
5797 /* We've lost link, so the controller stops DMA,
5798 * but we've got queued Tx work that's never going
5799 * to get done, so reset controller to flush Tx.
5800 * (Do the reset outside of interrupt context).
5801 */
5802 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5803 }
5804 }
5805 }
5806
5807 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5808 {
5809 u32 ssvpc;
5810
5811 /* Do not perform spoof check for 82598 */
5812 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5813 return;
5814
5815 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5816
5817 /*
5818 * ssvpc register is cleared on read, if zero then no
5819 * spoofed packets in the last interval.
5820 */
5821 if (!ssvpc)
5822 return;
5823
5824 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5825 }
5826
5827 /**
5828 * ixgbe_watchdog_subtask - check and bring link up
5829 * @adapter - pointer to the device adapter structure
5830 **/
5831 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5832 {
5833 /* if interface is down do nothing */
5834 if (test_bit(__IXGBE_DOWN, &adapter->state))
5835 return;
5836
5837 ixgbe_watchdog_update_link(adapter);
5838
5839 if (adapter->link_up)
5840 ixgbe_watchdog_link_is_up(adapter);
5841 else
5842 ixgbe_watchdog_link_is_down(adapter);
5843
5844 ixgbe_spoof_check(adapter);
5845 ixgbe_update_stats(adapter);
5846
5847 ixgbe_watchdog_flush_tx(adapter);
5848 }
5849
5850 /**
5851 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5852 * @adapter - the ixgbe adapter structure
5853 **/
5854 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5855 {
5856 struct ixgbe_hw *hw = &adapter->hw;
5857 s32 err;
5858
5859 /* not searching for SFP so there is nothing to do here */
5860 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5861 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5862 return;
5863
5864 /* someone else is in init, wait until next service event */
5865 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5866 return;
5867
5868 err = hw->phy.ops.identify_sfp(hw);
5869 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5870 goto sfp_out;
5871
5872 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5873 /* If no cable is present, then we need to reset
5874 * the next time we find a good cable. */
5875 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5876 }
5877
5878 /* exit on error */
5879 if (err)
5880 goto sfp_out;
5881
5882 /* exit if reset not needed */
5883 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5884 goto sfp_out;
5885
5886 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5887
5888 /*
5889 * A module may be identified correctly, but the EEPROM may not have
5890 * support for that module. setup_sfp() will fail in that case, so
5891 * we should not allow that module to load.
5892 */
5893 if (hw->mac.type == ixgbe_mac_82598EB)
5894 err = hw->phy.ops.reset(hw);
5895 else
5896 err = hw->mac.ops.setup_sfp(hw);
5897
5898 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5899 goto sfp_out;
5900
5901 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5902 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5903
5904 sfp_out:
5905 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5906
5907 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5908 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5909 e_dev_err("failed to initialize because an unsupported "
5910 "SFP+ module type was detected.\n");
5911 e_dev_err("Reload the driver after installing a "
5912 "supported module.\n");
5913 unregister_netdev(adapter->netdev);
5914 }
5915 }
5916
5917 /**
5918 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5919 * @adapter - the ixgbe adapter structure
5920 **/
5921 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5922 {
5923 struct ixgbe_hw *hw = &adapter->hw;
5924 u32 autoneg;
5925 bool negotiation;
5926
5927 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5928 return;
5929
5930 /* someone else is in init, wait until next service event */
5931 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5932 return;
5933
5934 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5935
5936 autoneg = hw->phy.autoneg_advertised;
5937 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5938 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5939 hw->mac.autotry_restart = false;
5940 if (hw->mac.ops.setup_link)
5941 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5942
5943 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5944 adapter->link_check_timeout = jiffies;
5945 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5946 }
5947
5948 /**
5949 * ixgbe_service_timer - Timer Call-back
5950 * @data: pointer to adapter cast into an unsigned long
5951 **/
5952 static void ixgbe_service_timer(unsigned long data)
5953 {
5954 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5955 unsigned long next_event_offset;
5956
5957 /* poll faster when waiting for link */
5958 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5959 next_event_offset = HZ / 10;
5960 else
5961 next_event_offset = HZ * 2;
5962
5963 /* Reset the timer */
5964 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5965
5966 ixgbe_service_event_schedule(adapter);
5967 }
5968
5969 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5970 {
5971 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5972 return;
5973
5974 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5975
5976 /* If we're already down or resetting, just bail */
5977 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5978 test_bit(__IXGBE_RESETTING, &adapter->state))
5979 return;
5980
5981 ixgbe_dump(adapter);
5982 netdev_err(adapter->netdev, "Reset adapter\n");
5983 adapter->tx_timeout_count++;
5984
5985 ixgbe_reinit_locked(adapter);
5986 }
5987
5988 /**
5989 * ixgbe_service_task - manages and runs subtasks
5990 * @work: pointer to work_struct containing our data
5991 **/
5992 static void ixgbe_service_task(struct work_struct *work)
5993 {
5994 struct ixgbe_adapter *adapter = container_of(work,
5995 struct ixgbe_adapter,
5996 service_task);
5997
5998 ixgbe_reset_subtask(adapter);
5999 ixgbe_sfp_detection_subtask(adapter);
6000 ixgbe_sfp_link_config_subtask(adapter);
6001 ixgbe_check_overtemp_subtask(adapter);
6002 ixgbe_watchdog_subtask(adapter);
6003 ixgbe_fdir_reinit_subtask(adapter);
6004 ixgbe_check_hang_subtask(adapter);
6005
6006 ixgbe_service_event_complete(adapter);
6007 }
6008
6009 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6010 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6011 {
6012 struct ixgbe_adv_tx_context_desc *context_desc;
6013 u16 i = tx_ring->next_to_use;
6014
6015 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6016
6017 i++;
6018 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6019
6020 /* set bits to identify this as an advanced context descriptor */
6021 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6022
6023 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6024 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6025 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6026 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6027 }
6028
6029 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6030 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6031 {
6032 int err;
6033 u32 vlan_macip_lens, type_tucmd;
6034 u32 mss_l4len_idx, l4len;
6035
6036 if (!skb_is_gso(skb))
6037 return 0;
6038
6039 if (skb_header_cloned(skb)) {
6040 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6041 if (err)
6042 return err;
6043 }
6044
6045 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6046 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6047
6048 if (protocol == __constant_htons(ETH_P_IP)) {
6049 struct iphdr *iph = ip_hdr(skb);
6050 iph->tot_len = 0;
6051 iph->check = 0;
6052 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6053 iph->daddr, 0,
6054 IPPROTO_TCP,
6055 0);
6056 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6057 } else if (skb_is_gso_v6(skb)) {
6058 ipv6_hdr(skb)->payload_len = 0;
6059 tcp_hdr(skb)->check =
6060 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6061 &ipv6_hdr(skb)->daddr,
6062 0, IPPROTO_TCP, 0);
6063 }
6064
6065 l4len = tcp_hdrlen(skb);
6066 *hdr_len = skb_transport_offset(skb) + l4len;
6067
6068 /* mss_l4len_id: use 1 as index for TSO */
6069 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6070 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6071 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6072
6073 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6074 vlan_macip_lens = skb_network_header_len(skb);
6075 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6076 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6077
6078 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6079 mss_l4len_idx);
6080
6081 return 1;
6082 }
6083
6084 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6085 struct sk_buff *skb, u32 tx_flags,
6086 __be16 protocol)
6087 {
6088 u32 vlan_macip_lens = 0;
6089 u32 mss_l4len_idx = 0;
6090 u32 type_tucmd = 0;
6091
6092 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6093 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6094 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
6095 return false;
6096 } else {
6097 u8 l4_hdr = 0;
6098 switch (protocol) {
6099 case __constant_htons(ETH_P_IP):
6100 vlan_macip_lens |= skb_network_header_len(skb);
6101 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6102 l4_hdr = ip_hdr(skb)->protocol;
6103 break;
6104 case __constant_htons(ETH_P_IPV6):
6105 vlan_macip_lens |= skb_network_header_len(skb);
6106 l4_hdr = ipv6_hdr(skb)->nexthdr;
6107 break;
6108 default:
6109 if (unlikely(net_ratelimit())) {
6110 dev_warn(tx_ring->dev,
6111 "partial checksum but proto=%x!\n",
6112 skb->protocol);
6113 }
6114 break;
6115 }
6116
6117 switch (l4_hdr) {
6118 case IPPROTO_TCP:
6119 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6120 mss_l4len_idx = tcp_hdrlen(skb) <<
6121 IXGBE_ADVTXD_L4LEN_SHIFT;
6122 break;
6123 case IPPROTO_SCTP:
6124 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6125 mss_l4len_idx = sizeof(struct sctphdr) <<
6126 IXGBE_ADVTXD_L4LEN_SHIFT;
6127 break;
6128 case IPPROTO_UDP:
6129 mss_l4len_idx = sizeof(struct udphdr) <<
6130 IXGBE_ADVTXD_L4LEN_SHIFT;
6131 break;
6132 default:
6133 if (unlikely(net_ratelimit())) {
6134 dev_warn(tx_ring->dev,
6135 "partial checksum but l4 proto=%x!\n",
6136 skb->protocol);
6137 }
6138 break;
6139 }
6140 }
6141
6142 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6143 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6144
6145 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6146 type_tucmd, mss_l4len_idx);
6147
6148 return (skb->ip_summed == CHECKSUM_PARTIAL);
6149 }
6150
6151 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6152 {
6153 /* set type for advanced descriptor with frame checksum insertion */
6154 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6155 IXGBE_ADVTXD_DCMD_IFCS |
6156 IXGBE_ADVTXD_DCMD_DEXT);
6157
6158 /* set HW vlan bit if vlan is present */
6159 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6160 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6161
6162 /* set segmentation enable bits for TSO/FSO */
6163 #ifdef IXGBE_FCOE
6164 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6165 #else
6166 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6167 #endif
6168 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6169
6170 return cmd_type;
6171 }
6172
6173 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6174 {
6175 __le32 olinfo_status =
6176 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6177
6178 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6179 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6180 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6181 /* enble IPv4 checksum for TSO */
6182 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6183 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6184 }
6185
6186 /* enable L4 checksum for TSO and TX checksum offload */
6187 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6188 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6189
6190 #ifdef IXGBE_FCOE
6191 /* use index 1 context for FCOE/FSO */
6192 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6193 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6194 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6195
6196 #endif
6197 /*
6198 * Check Context must be set if Tx switch is enabled, which it
6199 * always is for case where virtual functions are running
6200 */
6201 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6202 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6203
6204 return olinfo_status;
6205 }
6206
6207 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6208 IXGBE_TXD_CMD_RS)
6209
6210 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6211 struct sk_buff *skb,
6212 struct ixgbe_tx_buffer *first,
6213 u32 tx_flags,
6214 const u8 hdr_len)
6215 {
6216 struct device *dev = tx_ring->dev;
6217 struct ixgbe_tx_buffer *tx_buffer_info;
6218 union ixgbe_adv_tx_desc *tx_desc;
6219 dma_addr_t dma;
6220 __le32 cmd_type, olinfo_status;
6221 struct skb_frag_struct *frag;
6222 unsigned int f = 0;
6223 unsigned int data_len = skb->data_len;
6224 unsigned int size = skb_headlen(skb);
6225 u32 offset = 0;
6226 u32 paylen = skb->len - hdr_len;
6227 u16 i = tx_ring->next_to_use;
6228 u16 gso_segs;
6229
6230 #ifdef IXGBE_FCOE
6231 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6232 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6233 data_len -= sizeof(struct fcoe_crc_eof);
6234 } else {
6235 size -= sizeof(struct fcoe_crc_eof) - data_len;
6236 data_len = 0;
6237 }
6238 }
6239
6240 #endif
6241 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6242 if (dma_mapping_error(dev, dma))
6243 goto dma_error;
6244
6245 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6246 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6247
6248 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6249
6250 for (;;) {
6251 while (size > IXGBE_MAX_DATA_PER_TXD) {
6252 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6253 tx_desc->read.cmd_type_len =
6254 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6255 tx_desc->read.olinfo_status = olinfo_status;
6256
6257 offset += IXGBE_MAX_DATA_PER_TXD;
6258 size -= IXGBE_MAX_DATA_PER_TXD;
6259
6260 tx_desc++;
6261 i++;
6262 if (i == tx_ring->count) {
6263 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6264 i = 0;
6265 }
6266 }
6267
6268 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6269 tx_buffer_info->length = offset + size;
6270 tx_buffer_info->tx_flags = tx_flags;
6271 tx_buffer_info->dma = dma;
6272
6273 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6274 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6275 tx_desc->read.olinfo_status = olinfo_status;
6276
6277 if (!data_len)
6278 break;
6279
6280 frag = &skb_shinfo(skb)->frags[f];
6281 #ifdef IXGBE_FCOE
6282 size = min_t(unsigned int, data_len, frag->size);
6283 #else
6284 size = frag->size;
6285 #endif
6286 data_len -= size;
6287 f++;
6288
6289 offset = 0;
6290 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6291
6292 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
6293 if (dma_mapping_error(dev, dma))
6294 goto dma_error;
6295
6296 tx_desc++;
6297 i++;
6298 if (i == tx_ring->count) {
6299 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6300 i = 0;
6301 }
6302 }
6303
6304 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6305
6306 i++;
6307 if (i == tx_ring->count)
6308 i = 0;
6309
6310 tx_ring->next_to_use = i;
6311
6312 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6313 gso_segs = skb_shinfo(skb)->gso_segs;
6314 #ifdef IXGBE_FCOE
6315 /* adjust for FCoE Sequence Offload */
6316 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6317 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6318 skb_shinfo(skb)->gso_size);
6319 #endif /* IXGBE_FCOE */
6320 else
6321 gso_segs = 1;
6322
6323 /* multiply data chunks by size of headers */
6324 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6325 tx_buffer_info->gso_segs = gso_segs;
6326 tx_buffer_info->skb = skb;
6327
6328 /* set the timestamp */
6329 first->time_stamp = jiffies;
6330
6331 /*
6332 * Force memory writes to complete before letting h/w
6333 * know there are new descriptors to fetch. (Only
6334 * applicable for weak-ordered memory model archs,
6335 * such as IA-64).
6336 */
6337 wmb();
6338
6339 /* set next_to_watch value indicating a packet is present */
6340 first->next_to_watch = tx_desc;
6341
6342 /* notify HW of packet */
6343 writel(i, tx_ring->tail);
6344
6345 return;
6346 dma_error:
6347 dev_err(dev, "TX DMA map failed\n");
6348
6349 /* clear dma mappings for failed tx_buffer_info map */
6350 for (;;) {
6351 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6352 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6353 if (tx_buffer_info == first)
6354 break;
6355 if (i == 0)
6356 i = tx_ring->count;
6357 i--;
6358 }
6359
6360 dev_kfree_skb_any(skb);
6361
6362 tx_ring->next_to_use = i;
6363 }
6364
6365 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6366 u32 tx_flags, __be16 protocol)
6367 {
6368 struct ixgbe_q_vector *q_vector = ring->q_vector;
6369 union ixgbe_atr_hash_dword input = { .dword = 0 };
6370 union ixgbe_atr_hash_dword common = { .dword = 0 };
6371 union {
6372 unsigned char *network;
6373 struct iphdr *ipv4;
6374 struct ipv6hdr *ipv6;
6375 } hdr;
6376 struct tcphdr *th;
6377 __be16 vlan_id;
6378
6379 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6380 if (!q_vector)
6381 return;
6382
6383 /* do nothing if sampling is disabled */
6384 if (!ring->atr_sample_rate)
6385 return;
6386
6387 ring->atr_count++;
6388
6389 /* snag network header to get L4 type and address */
6390 hdr.network = skb_network_header(skb);
6391
6392 /* Currently only IPv4/IPv6 with TCP is supported */
6393 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6394 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6395 (protocol != __constant_htons(ETH_P_IP) ||
6396 hdr.ipv4->protocol != IPPROTO_TCP))
6397 return;
6398
6399 th = tcp_hdr(skb);
6400
6401 /* skip this packet since it is invalid or the socket is closing */
6402 if (!th || th->fin)
6403 return;
6404
6405 /* sample on all syn packets or once every atr sample count */
6406 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6407 return;
6408
6409 /* reset sample count */
6410 ring->atr_count = 0;
6411
6412 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6413
6414 /*
6415 * src and dst are inverted, think how the receiver sees them
6416 *
6417 * The input is broken into two sections, a non-compressed section
6418 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6419 * is XORed together and stored in the compressed dword.
6420 */
6421 input.formatted.vlan_id = vlan_id;
6422
6423 /*
6424 * since src port and flex bytes occupy the same word XOR them together
6425 * and write the value to source port portion of compressed dword
6426 */
6427 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6428 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6429 else
6430 common.port.src ^= th->dest ^ protocol;
6431 common.port.dst ^= th->source;
6432
6433 if (protocol == __constant_htons(ETH_P_IP)) {
6434 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6435 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6436 } else {
6437 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6438 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6439 hdr.ipv6->saddr.s6_addr32[1] ^
6440 hdr.ipv6->saddr.s6_addr32[2] ^
6441 hdr.ipv6->saddr.s6_addr32[3] ^
6442 hdr.ipv6->daddr.s6_addr32[0] ^
6443 hdr.ipv6->daddr.s6_addr32[1] ^
6444 hdr.ipv6->daddr.s6_addr32[2] ^
6445 hdr.ipv6->daddr.s6_addr32[3];
6446 }
6447
6448 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6449 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6450 input, common, ring->queue_index);
6451 }
6452
6453 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6454 {
6455 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6456 /* Herbert's original patch had:
6457 * smp_mb__after_netif_stop_queue();
6458 * but since that doesn't exist yet, just open code it. */
6459 smp_mb();
6460
6461 /* We need to check again in a case another CPU has just
6462 * made room available. */
6463 if (likely(ixgbe_desc_unused(tx_ring) < size))
6464 return -EBUSY;
6465
6466 /* A reprieve! - use start_queue because it doesn't call schedule */
6467 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6468 ++tx_ring->tx_stats.restart_queue;
6469 return 0;
6470 }
6471
6472 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6473 {
6474 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6475 return 0;
6476 return __ixgbe_maybe_stop_tx(tx_ring, size);
6477 }
6478
6479 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6480 {
6481 struct ixgbe_adapter *adapter = netdev_priv(dev);
6482 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6483 smp_processor_id();
6484 #ifdef IXGBE_FCOE
6485 __be16 protocol = vlan_get_protocol(skb);
6486
6487 if (((protocol == htons(ETH_P_FCOE)) ||
6488 (protocol == htons(ETH_P_FIP))) &&
6489 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6490 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6491 txq += adapter->ring_feature[RING_F_FCOE].mask;
6492 return txq;
6493 }
6494 #endif
6495
6496 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6497 while (unlikely(txq >= dev->real_num_tx_queues))
6498 txq -= dev->real_num_tx_queues;
6499 return txq;
6500 }
6501
6502 return skb_tx_hash(dev, skb);
6503 }
6504
6505 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6506 struct ixgbe_adapter *adapter,
6507 struct ixgbe_ring *tx_ring)
6508 {
6509 struct ixgbe_tx_buffer *first;
6510 int tso;
6511 u32 tx_flags = 0;
6512 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6513 unsigned short f;
6514 #endif
6515 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6516 __be16 protocol = skb->protocol;
6517 u8 hdr_len = 0;
6518
6519 /*
6520 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6521 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6522 * + 2 desc gap to keep tail from touching head,
6523 * + 1 desc for context descriptor,
6524 * otherwise try next time
6525 */
6526 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6527 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6528 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6529 #else
6530 count += skb_shinfo(skb)->nr_frags;
6531 #endif
6532 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6533 tx_ring->tx_stats.tx_busy++;
6534 return NETDEV_TX_BUSY;
6535 }
6536
6537 #ifdef CONFIG_PCI_IOV
6538 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6539 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6540
6541 #endif
6542 /* if we have a HW VLAN tag being added default to the HW one */
6543 if (vlan_tx_tag_present(skb)) {
6544 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6545 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6546 /* else if it is a SW VLAN check the next protocol and store the tag */
6547 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6548 struct vlan_hdr *vhdr, _vhdr;
6549 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6550 if (!vhdr)
6551 goto out_drop;
6552
6553 protocol = vhdr->h_vlan_encapsulated_proto;
6554 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6555 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6556 }
6557
6558 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6559 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6560 (skb->priority != TC_PRIO_CONTROL))) {
6561 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6562 tx_flags |= tx_ring->dcb_tc <<
6563 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6564 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6565 struct vlan_ethhdr *vhdr;
6566 if (skb_header_cloned(skb) &&
6567 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6568 goto out_drop;
6569 vhdr = (struct vlan_ethhdr *)skb->data;
6570 vhdr->h_vlan_TCI = htons(tx_flags >>
6571 IXGBE_TX_FLAGS_VLAN_SHIFT);
6572 } else {
6573 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6574 }
6575 }
6576
6577 /* record the location of the first descriptor for this packet */
6578 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6579
6580 #ifdef IXGBE_FCOE
6581 /* setup tx offload for FCoE */
6582 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6583 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6584 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6585 if (tso < 0)
6586 goto out_drop;
6587 else if (tso)
6588 tx_flags |= IXGBE_TX_FLAGS_FSO |
6589 IXGBE_TX_FLAGS_FCOE;
6590 else
6591 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6592
6593 goto xmit_fcoe;
6594 }
6595
6596 #endif /* IXGBE_FCOE */
6597 /* setup IPv4/IPv6 offloads */
6598 if (protocol == __constant_htons(ETH_P_IP))
6599 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6600
6601 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6602 if (tso < 0)
6603 goto out_drop;
6604 else if (tso)
6605 tx_flags |= IXGBE_TX_FLAGS_TSO;
6606 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6607 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6608
6609 /* add the ATR filter if ATR is on */
6610 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6611 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6612
6613 #ifdef IXGBE_FCOE
6614 xmit_fcoe:
6615 #endif /* IXGBE_FCOE */
6616 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6617
6618 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6619
6620 return NETDEV_TX_OK;
6621
6622 out_drop:
6623 dev_kfree_skb_any(skb);
6624 return NETDEV_TX_OK;
6625 }
6626
6627 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6628 {
6629 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6630 struct ixgbe_ring *tx_ring;
6631
6632 tx_ring = adapter->tx_ring[skb->queue_mapping];
6633 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6634 }
6635
6636 /**
6637 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6638 * @netdev: network interface device structure
6639 * @p: pointer to an address structure
6640 *
6641 * Returns 0 on success, negative on failure
6642 **/
6643 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6644 {
6645 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6646 struct ixgbe_hw *hw = &adapter->hw;
6647 struct sockaddr *addr = p;
6648
6649 if (!is_valid_ether_addr(addr->sa_data))
6650 return -EADDRNOTAVAIL;
6651
6652 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6653 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6654
6655 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6656 IXGBE_RAH_AV);
6657
6658 return 0;
6659 }
6660
6661 static int
6662 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6663 {
6664 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6665 struct ixgbe_hw *hw = &adapter->hw;
6666 u16 value;
6667 int rc;
6668
6669 if (prtad != hw->phy.mdio.prtad)
6670 return -EINVAL;
6671 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6672 if (!rc)
6673 rc = value;
6674 return rc;
6675 }
6676
6677 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6678 u16 addr, u16 value)
6679 {
6680 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6681 struct ixgbe_hw *hw = &adapter->hw;
6682
6683 if (prtad != hw->phy.mdio.prtad)
6684 return -EINVAL;
6685 return hw->phy.ops.write_reg(hw, addr, devad, value);
6686 }
6687
6688 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6689 {
6690 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6691
6692 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6693 }
6694
6695 /**
6696 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6697 * netdev->dev_addrs
6698 * @netdev: network interface device structure
6699 *
6700 * Returns non-zero on failure
6701 **/
6702 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6703 {
6704 int err = 0;
6705 struct ixgbe_adapter *adapter = netdev_priv(dev);
6706 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6707
6708 if (is_valid_ether_addr(mac->san_addr)) {
6709 rtnl_lock();
6710 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6711 rtnl_unlock();
6712 }
6713 return err;
6714 }
6715
6716 /**
6717 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6718 * netdev->dev_addrs
6719 * @netdev: network interface device structure
6720 *
6721 * Returns non-zero on failure
6722 **/
6723 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6724 {
6725 int err = 0;
6726 struct ixgbe_adapter *adapter = netdev_priv(dev);
6727 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6728
6729 if (is_valid_ether_addr(mac->san_addr)) {
6730 rtnl_lock();
6731 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6732 rtnl_unlock();
6733 }
6734 return err;
6735 }
6736
6737 #ifdef CONFIG_NET_POLL_CONTROLLER
6738 /*
6739 * Polling 'interrupt' - used by things like netconsole to send skbs
6740 * without having to re-enable interrupts. It's not called while
6741 * the interrupt routine is executing.
6742 */
6743 static void ixgbe_netpoll(struct net_device *netdev)
6744 {
6745 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6746 int i;
6747
6748 /* if interface is down do nothing */
6749 if (test_bit(__IXGBE_DOWN, &adapter->state))
6750 return;
6751
6752 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6753 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6754 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6755 for (i = 0; i < num_q_vectors; i++) {
6756 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6757 ixgbe_msix_clean_rings(0, q_vector);
6758 }
6759 } else {
6760 ixgbe_intr(adapter->pdev->irq, netdev);
6761 }
6762 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6763 }
6764 #endif
6765
6766 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6767 struct rtnl_link_stats64 *stats)
6768 {
6769 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6770 int i;
6771
6772 rcu_read_lock();
6773 for (i = 0; i < adapter->num_rx_queues; i++) {
6774 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6775 u64 bytes, packets;
6776 unsigned int start;
6777
6778 if (ring) {
6779 do {
6780 start = u64_stats_fetch_begin_bh(&ring->syncp);
6781 packets = ring->stats.packets;
6782 bytes = ring->stats.bytes;
6783 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6784 stats->rx_packets += packets;
6785 stats->rx_bytes += bytes;
6786 }
6787 }
6788
6789 for (i = 0; i < adapter->num_tx_queues; i++) {
6790 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6791 u64 bytes, packets;
6792 unsigned int start;
6793
6794 if (ring) {
6795 do {
6796 start = u64_stats_fetch_begin_bh(&ring->syncp);
6797 packets = ring->stats.packets;
6798 bytes = ring->stats.bytes;
6799 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6800 stats->tx_packets += packets;
6801 stats->tx_bytes += bytes;
6802 }
6803 }
6804 rcu_read_unlock();
6805 /* following stats updated by ixgbe_watchdog_task() */
6806 stats->multicast = netdev->stats.multicast;
6807 stats->rx_errors = netdev->stats.rx_errors;
6808 stats->rx_length_errors = netdev->stats.rx_length_errors;
6809 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6810 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6811 return stats;
6812 }
6813
6814 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6815 * #adapter: pointer to ixgbe_adapter
6816 * @tc: number of traffic classes currently enabled
6817 *
6818 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6819 * 802.1Q priority maps to a packet buffer that exists.
6820 */
6821 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6822 {
6823 struct ixgbe_hw *hw = &adapter->hw;
6824 u32 reg, rsave;
6825 int i;
6826
6827 /* 82598 have a static priority to TC mapping that can not
6828 * be changed so no validation is needed.
6829 */
6830 if (hw->mac.type == ixgbe_mac_82598EB)
6831 return;
6832
6833 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6834 rsave = reg;
6835
6836 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6837 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6838
6839 /* If up2tc is out of bounds default to zero */
6840 if (up2tc > tc)
6841 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6842 }
6843
6844 if (reg != rsave)
6845 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6846
6847 return;
6848 }
6849
6850
6851 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6852 * classes.
6853 *
6854 * @netdev: net device to configure
6855 * @tc: number of traffic classes to enable
6856 */
6857 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6858 {
6859 struct ixgbe_adapter *adapter = netdev_priv(dev);
6860 struct ixgbe_hw *hw = &adapter->hw;
6861
6862 /* Multiple traffic classes requires multiple queues */
6863 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6864 e_err(drv, "Enable failed, needs MSI-X\n");
6865 return -EINVAL;
6866 }
6867
6868 /* Hardware supports up to 8 traffic classes */
6869 if (tc > MAX_TRAFFIC_CLASS ||
6870 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
6871 return -EINVAL;
6872
6873 /* Hardware has to reinitialize queues and interrupts to
6874 * match packet buffer alignment. Unfortunantly, the
6875 * hardware is not flexible enough to do this dynamically.
6876 */
6877 if (netif_running(dev))
6878 ixgbe_close(dev);
6879 ixgbe_clear_interrupt_scheme(adapter);
6880
6881 if (tc) {
6882 netdev_set_num_tc(dev, tc);
6883 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
6884
6885 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6886 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6887
6888 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6889 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6890 } else {
6891 netdev_reset_tc(dev);
6892
6893 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6894
6895 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6896 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6897
6898 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6899 adapter->dcb_cfg.pfc_mode_enable = false;
6900 }
6901
6902 ixgbe_init_interrupt_scheme(adapter);
6903 ixgbe_validate_rtr(adapter, tc);
6904 if (netif_running(dev))
6905 ixgbe_open(dev);
6906
6907 return 0;
6908 }
6909
6910 void ixgbe_do_reset(struct net_device *netdev)
6911 {
6912 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6913
6914 if (netif_running(netdev))
6915 ixgbe_reinit_locked(adapter);
6916 else
6917 ixgbe_reset(adapter);
6918 }
6919
6920 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
6921 {
6922 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6923
6924 #ifdef CONFIG_DCB
6925 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6926 data &= ~NETIF_F_HW_VLAN_RX;
6927 #endif
6928
6929 /* return error if RXHASH is being enabled when RSS is not supported */
6930 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6931 data &= ~NETIF_F_RXHASH;
6932
6933 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6934 if (!(data & NETIF_F_RXCSUM))
6935 data &= ~NETIF_F_LRO;
6936
6937 /* Turn off LRO if not RSC capable or invalid ITR settings */
6938 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
6939 data &= ~NETIF_F_LRO;
6940 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
6941 (adapter->rx_itr_setting != 1 &&
6942 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
6943 data &= ~NETIF_F_LRO;
6944 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
6945 }
6946
6947 return data;
6948 }
6949
6950 static int ixgbe_set_features(struct net_device *netdev, u32 data)
6951 {
6952 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6953 bool need_reset = false;
6954
6955 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6956 if (!(data & NETIF_F_RXCSUM))
6957 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
6958 else
6959 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
6960
6961 /* Make sure RSC matches LRO, reset if change */
6962 if (!!(data & NETIF_F_LRO) !=
6963 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6964 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
6965 switch (adapter->hw.mac.type) {
6966 case ixgbe_mac_X540:
6967 case ixgbe_mac_82599EB:
6968 need_reset = true;
6969 break;
6970 default:
6971 break;
6972 }
6973 }
6974
6975 /*
6976 * Check if Flow Director n-tuple support was enabled or disabled. If
6977 * the state changed, we need to reset.
6978 */
6979 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6980 /* turn off ATR, enable perfect filters and reset */
6981 if (data & NETIF_F_NTUPLE) {
6982 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6983 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6984 need_reset = true;
6985 }
6986 } else if (!(data & NETIF_F_NTUPLE)) {
6987 /* turn off Flow Director, set ATR and reset */
6988 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6989 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
6990 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
6991 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6992 need_reset = true;
6993 }
6994
6995 if (need_reset)
6996 ixgbe_do_reset(netdev);
6997
6998 return 0;
6999
7000 }
7001
7002 static const struct net_device_ops ixgbe_netdev_ops = {
7003 .ndo_open = ixgbe_open,
7004 .ndo_stop = ixgbe_close,
7005 .ndo_start_xmit = ixgbe_xmit_frame,
7006 .ndo_select_queue = ixgbe_select_queue,
7007 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7008 .ndo_validate_addr = eth_validate_addr,
7009 .ndo_set_mac_address = ixgbe_set_mac,
7010 .ndo_change_mtu = ixgbe_change_mtu,
7011 .ndo_tx_timeout = ixgbe_tx_timeout,
7012 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7013 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7014 .ndo_do_ioctl = ixgbe_ioctl,
7015 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7016 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7017 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7018 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7019 .ndo_get_stats64 = ixgbe_get_stats64,
7020 .ndo_setup_tc = ixgbe_setup_tc,
7021 #ifdef CONFIG_NET_POLL_CONTROLLER
7022 .ndo_poll_controller = ixgbe_netpoll,
7023 #endif
7024 #ifdef IXGBE_FCOE
7025 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7026 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7027 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7028 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7029 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7030 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7031 #endif /* IXGBE_FCOE */
7032 .ndo_set_features = ixgbe_set_features,
7033 .ndo_fix_features = ixgbe_fix_features,
7034 };
7035
7036 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7037 const struct ixgbe_info *ii)
7038 {
7039 #ifdef CONFIG_PCI_IOV
7040 struct ixgbe_hw *hw = &adapter->hw;
7041 int err;
7042 int num_vf_macvlans, i;
7043 struct vf_macvlans *mv_list;
7044
7045 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7046 return;
7047
7048 /* The 82599 supports up to 64 VFs per physical function
7049 * but this implementation limits allocation to 63 so that
7050 * basic networking resources are still available to the
7051 * physical function
7052 */
7053 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7054 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7055 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7056 if (err) {
7057 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7058 goto err_novfs;
7059 }
7060
7061 num_vf_macvlans = hw->mac.num_rar_entries -
7062 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7063
7064 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7065 sizeof(struct vf_macvlans),
7066 GFP_KERNEL);
7067 if (mv_list) {
7068 /* Initialize list of VF macvlans */
7069 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7070 for (i = 0; i < num_vf_macvlans; i++) {
7071 mv_list->vf = -1;
7072 mv_list->free = true;
7073 mv_list->rar_entry = hw->mac.num_rar_entries -
7074 (i + adapter->num_vfs + 1);
7075 list_add(&mv_list->l, &adapter->vf_mvs.l);
7076 mv_list++;
7077 }
7078 }
7079
7080 /* If call to enable VFs succeeded then allocate memory
7081 * for per VF control structures.
7082 */
7083 adapter->vfinfo =
7084 kcalloc(adapter->num_vfs,
7085 sizeof(struct vf_data_storage), GFP_KERNEL);
7086 if (adapter->vfinfo) {
7087 /* Now that we're sure SR-IOV is enabled
7088 * and memory allocated set up the mailbox parameters
7089 */
7090 ixgbe_init_mbx_params_pf(hw);
7091 memcpy(&hw->mbx.ops, ii->mbx_ops,
7092 sizeof(hw->mbx.ops));
7093
7094 /* Disable RSC when in SR-IOV mode */
7095 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7096 IXGBE_FLAG2_RSC_ENABLED);
7097 return;
7098 }
7099
7100 /* Oh oh */
7101 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7102 "SRIOV disabled\n");
7103 pci_disable_sriov(adapter->pdev);
7104
7105 err_novfs:
7106 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7107 adapter->num_vfs = 0;
7108 #endif /* CONFIG_PCI_IOV */
7109 }
7110
7111 /**
7112 * ixgbe_probe - Device Initialization Routine
7113 * @pdev: PCI device information struct
7114 * @ent: entry in ixgbe_pci_tbl
7115 *
7116 * Returns 0 on success, negative on failure
7117 *
7118 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7119 * The OS initialization, configuring of the adapter private structure,
7120 * and a hardware reset occur.
7121 **/
7122 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7123 const struct pci_device_id *ent)
7124 {
7125 struct net_device *netdev;
7126 struct ixgbe_adapter *adapter = NULL;
7127 struct ixgbe_hw *hw;
7128 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7129 static int cards_found;
7130 int i, err, pci_using_dac;
7131 u8 part_str[IXGBE_PBANUM_LENGTH];
7132 unsigned int indices = num_possible_cpus();
7133 #ifdef IXGBE_FCOE
7134 u16 device_caps;
7135 #endif
7136 u32 eec;
7137
7138 /* Catch broken hardware that put the wrong VF device ID in
7139 * the PCIe SR-IOV capability.
7140 */
7141 if (pdev->is_virtfn) {
7142 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7143 pci_name(pdev), pdev->vendor, pdev->device);
7144 return -EINVAL;
7145 }
7146
7147 err = pci_enable_device_mem(pdev);
7148 if (err)
7149 return err;
7150
7151 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7152 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7153 pci_using_dac = 1;
7154 } else {
7155 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7156 if (err) {
7157 err = dma_set_coherent_mask(&pdev->dev,
7158 DMA_BIT_MASK(32));
7159 if (err) {
7160 dev_err(&pdev->dev,
7161 "No usable DMA configuration, aborting\n");
7162 goto err_dma;
7163 }
7164 }
7165 pci_using_dac = 0;
7166 }
7167
7168 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7169 IORESOURCE_MEM), ixgbe_driver_name);
7170 if (err) {
7171 dev_err(&pdev->dev,
7172 "pci_request_selected_regions failed 0x%x\n", err);
7173 goto err_pci_reg;
7174 }
7175
7176 pci_enable_pcie_error_reporting(pdev);
7177
7178 pci_set_master(pdev);
7179 pci_save_state(pdev);
7180
7181 #ifdef CONFIG_IXGBE_DCB
7182 indices *= MAX_TRAFFIC_CLASS;
7183 #endif
7184
7185 if (ii->mac == ixgbe_mac_82598EB)
7186 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7187 else
7188 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7189
7190 #ifdef IXGBE_FCOE
7191 indices += min_t(unsigned int, num_possible_cpus(),
7192 IXGBE_MAX_FCOE_INDICES);
7193 #endif
7194 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7195 if (!netdev) {
7196 err = -ENOMEM;
7197 goto err_alloc_etherdev;
7198 }
7199
7200 SET_NETDEV_DEV(netdev, &pdev->dev);
7201
7202 adapter = netdev_priv(netdev);
7203 pci_set_drvdata(pdev, adapter);
7204
7205 adapter->netdev = netdev;
7206 adapter->pdev = pdev;
7207 hw = &adapter->hw;
7208 hw->back = adapter;
7209 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7210
7211 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7212 pci_resource_len(pdev, 0));
7213 if (!hw->hw_addr) {
7214 err = -EIO;
7215 goto err_ioremap;
7216 }
7217
7218 for (i = 1; i <= 5; i++) {
7219 if (pci_resource_len(pdev, i) == 0)
7220 continue;
7221 }
7222
7223 netdev->netdev_ops = &ixgbe_netdev_ops;
7224 ixgbe_set_ethtool_ops(netdev);
7225 netdev->watchdog_timeo = 5 * HZ;
7226 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7227
7228 adapter->bd_number = cards_found;
7229
7230 /* Setup hw api */
7231 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7232 hw->mac.type = ii->mac;
7233
7234 /* EEPROM */
7235 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7236 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7237 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7238 if (!(eec & (1 << 8)))
7239 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7240
7241 /* PHY */
7242 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7243 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7244 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7245 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7246 hw->phy.mdio.mmds = 0;
7247 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7248 hw->phy.mdio.dev = netdev;
7249 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7250 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7251
7252 ii->get_invariants(hw);
7253
7254 /* setup the private structure */
7255 err = ixgbe_sw_init(adapter);
7256 if (err)
7257 goto err_sw_init;
7258
7259 /* Make it possible the adapter to be woken up via WOL */
7260 switch (adapter->hw.mac.type) {
7261 case ixgbe_mac_82599EB:
7262 case ixgbe_mac_X540:
7263 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7264 break;
7265 default:
7266 break;
7267 }
7268
7269 /*
7270 * If there is a fan on this device and it has failed log the
7271 * failure.
7272 */
7273 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7274 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7275 if (esdp & IXGBE_ESDP_SDP1)
7276 e_crit(probe, "Fan has stopped, replace the adapter\n");
7277 }
7278
7279 /* reset_hw fills in the perm_addr as well */
7280 hw->phy.reset_if_overtemp = true;
7281 err = hw->mac.ops.reset_hw(hw);
7282 hw->phy.reset_if_overtemp = false;
7283 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7284 hw->mac.type == ixgbe_mac_82598EB) {
7285 err = 0;
7286 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7287 e_dev_err("failed to load because an unsupported SFP+ "
7288 "module type was detected.\n");
7289 e_dev_err("Reload the driver after installing a supported "
7290 "module.\n");
7291 goto err_sw_init;
7292 } else if (err) {
7293 e_dev_err("HW Init failed: %d\n", err);
7294 goto err_sw_init;
7295 }
7296
7297 ixgbe_probe_vf(adapter, ii);
7298
7299 netdev->features = NETIF_F_SG |
7300 NETIF_F_IP_CSUM |
7301 NETIF_F_IPV6_CSUM |
7302 NETIF_F_HW_VLAN_TX |
7303 NETIF_F_HW_VLAN_RX |
7304 NETIF_F_HW_VLAN_FILTER |
7305 NETIF_F_TSO |
7306 NETIF_F_TSO6 |
7307 NETIF_F_RXHASH |
7308 NETIF_F_RXCSUM;
7309
7310 netdev->hw_features = netdev->features;
7311
7312 switch (adapter->hw.mac.type) {
7313 case ixgbe_mac_82599EB:
7314 case ixgbe_mac_X540:
7315 netdev->features |= NETIF_F_SCTP_CSUM;
7316 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7317 NETIF_F_NTUPLE;
7318 break;
7319 default:
7320 break;
7321 }
7322
7323 netdev->vlan_features |= NETIF_F_TSO;
7324 netdev->vlan_features |= NETIF_F_TSO6;
7325 netdev->vlan_features |= NETIF_F_IP_CSUM;
7326 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7327 netdev->vlan_features |= NETIF_F_SG;
7328
7329 netdev->priv_flags |= IFF_UNICAST_FLT;
7330
7331 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7332 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7333 IXGBE_FLAG_DCB_ENABLED);
7334
7335 #ifdef CONFIG_IXGBE_DCB
7336 netdev->dcbnl_ops = &dcbnl_ops;
7337 #endif
7338
7339 #ifdef IXGBE_FCOE
7340 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7341 if (hw->mac.ops.get_device_caps) {
7342 hw->mac.ops.get_device_caps(hw, &device_caps);
7343 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7344 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7345 }
7346 }
7347 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7348 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7349 netdev->vlan_features |= NETIF_F_FSO;
7350 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7351 }
7352 #endif /* IXGBE_FCOE */
7353 if (pci_using_dac) {
7354 netdev->features |= NETIF_F_HIGHDMA;
7355 netdev->vlan_features |= NETIF_F_HIGHDMA;
7356 }
7357
7358 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7359 netdev->hw_features |= NETIF_F_LRO;
7360 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7361 netdev->features |= NETIF_F_LRO;
7362
7363 /* make sure the EEPROM is good */
7364 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7365 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7366 err = -EIO;
7367 goto err_eeprom;
7368 }
7369
7370 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7371 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7372
7373 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7374 e_dev_err("invalid MAC address\n");
7375 err = -EIO;
7376 goto err_eeprom;
7377 }
7378
7379 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7380 if (hw->mac.ops.disable_tx_laser &&
7381 ((hw->phy.multispeed_fiber) ||
7382 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7383 (hw->mac.type == ixgbe_mac_82599EB))))
7384 hw->mac.ops.disable_tx_laser(hw);
7385
7386 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7387 (unsigned long) adapter);
7388
7389 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7390 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7391
7392 err = ixgbe_init_interrupt_scheme(adapter);
7393 if (err)
7394 goto err_sw_init;
7395
7396 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7397 netdev->hw_features &= ~NETIF_F_RXHASH;
7398 netdev->features &= ~NETIF_F_RXHASH;
7399 }
7400
7401 switch (pdev->device) {
7402 case IXGBE_DEV_ID_82599_SFP:
7403 /* Only this subdevice supports WOL */
7404 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7405 adapter->wol = IXGBE_WUFC_MAG;
7406 break;
7407 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7408 /* All except this subdevice support WOL */
7409 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7410 adapter->wol = IXGBE_WUFC_MAG;
7411 break;
7412 case IXGBE_DEV_ID_82599_KX4:
7413 adapter->wol = IXGBE_WUFC_MAG;
7414 break;
7415 default:
7416 adapter->wol = 0;
7417 break;
7418 }
7419 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7420
7421 /* pick up the PCI bus settings for reporting later */
7422 hw->mac.ops.get_bus_info(hw);
7423
7424 /* print bus type/speed/width info */
7425 e_dev_info("(PCI Express:%s:%s) %pM\n",
7426 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7427 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7428 "Unknown"),
7429 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7430 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7431 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7432 "Unknown"),
7433 netdev->dev_addr);
7434
7435 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7436 if (err)
7437 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7438 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7439 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7440 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7441 part_str);
7442 else
7443 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7444 hw->mac.type, hw->phy.type, part_str);
7445
7446 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7447 e_dev_warn("PCI-Express bandwidth available for this card is "
7448 "not sufficient for optimal performance.\n");
7449 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7450 "is required.\n");
7451 }
7452
7453 /* save off EEPROM version number */
7454 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7455
7456 /* reset the hardware with the new settings */
7457 err = hw->mac.ops.start_hw(hw);
7458
7459 if (err == IXGBE_ERR_EEPROM_VERSION) {
7460 /* We are running on a pre-production device, log a warning */
7461 e_dev_warn("This device is a pre-production adapter/LOM. "
7462 "Please be aware there may be issues associated "
7463 "with your hardware. If you are experiencing "
7464 "problems please contact your Intel or hardware "
7465 "representative who provided you with this "
7466 "hardware.\n");
7467 }
7468 strcpy(netdev->name, "eth%d");
7469 err = register_netdev(netdev);
7470 if (err)
7471 goto err_register;
7472
7473 /* carrier off reporting is important to ethtool even BEFORE open */
7474 netif_carrier_off(netdev);
7475
7476 #ifdef CONFIG_IXGBE_DCA
7477 if (dca_add_requester(&pdev->dev) == 0) {
7478 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7479 ixgbe_setup_dca(adapter);
7480 }
7481 #endif
7482 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7483 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7484 for (i = 0; i < adapter->num_vfs; i++)
7485 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7486 }
7487
7488 /* Inform firmware of driver version */
7489 if (hw->mac.ops.set_fw_drv_ver)
7490 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7491 FW_CEM_UNUSED_VER);
7492
7493 /* add san mac addr to netdev */
7494 ixgbe_add_sanmac_netdev(netdev);
7495
7496 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7497 cards_found++;
7498 return 0;
7499
7500 err_register:
7501 ixgbe_release_hw_control(adapter);
7502 ixgbe_clear_interrupt_scheme(adapter);
7503 err_sw_init:
7504 err_eeprom:
7505 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7506 ixgbe_disable_sriov(adapter);
7507 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7508 iounmap(hw->hw_addr);
7509 err_ioremap:
7510 free_netdev(netdev);
7511 err_alloc_etherdev:
7512 pci_release_selected_regions(pdev,
7513 pci_select_bars(pdev, IORESOURCE_MEM));
7514 err_pci_reg:
7515 err_dma:
7516 pci_disable_device(pdev);
7517 return err;
7518 }
7519
7520 /**
7521 * ixgbe_remove - Device Removal Routine
7522 * @pdev: PCI device information struct
7523 *
7524 * ixgbe_remove is called by the PCI subsystem to alert the driver
7525 * that it should release a PCI device. The could be caused by a
7526 * Hot-Plug event, or because the driver is going to be removed from
7527 * memory.
7528 **/
7529 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7530 {
7531 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7532 struct net_device *netdev = adapter->netdev;
7533
7534 set_bit(__IXGBE_DOWN, &adapter->state);
7535 cancel_work_sync(&adapter->service_task);
7536
7537 #ifdef CONFIG_IXGBE_DCA
7538 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7539 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7540 dca_remove_requester(&pdev->dev);
7541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7542 }
7543
7544 #endif
7545 #ifdef IXGBE_FCOE
7546 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7547 ixgbe_cleanup_fcoe(adapter);
7548
7549 #endif /* IXGBE_FCOE */
7550
7551 /* remove the added san mac */
7552 ixgbe_del_sanmac_netdev(netdev);
7553
7554 if (netdev->reg_state == NETREG_REGISTERED)
7555 unregister_netdev(netdev);
7556
7557 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7558 ixgbe_disable_sriov(adapter);
7559
7560 ixgbe_clear_interrupt_scheme(adapter);
7561
7562 ixgbe_release_hw_control(adapter);
7563
7564 iounmap(adapter->hw.hw_addr);
7565 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7566 IORESOURCE_MEM));
7567
7568 e_dev_info("complete\n");
7569
7570 free_netdev(netdev);
7571
7572 pci_disable_pcie_error_reporting(pdev);
7573
7574 pci_disable_device(pdev);
7575 }
7576
7577 /**
7578 * ixgbe_io_error_detected - called when PCI error is detected
7579 * @pdev: Pointer to PCI device
7580 * @state: The current pci connection state
7581 *
7582 * This function is called after a PCI bus error affecting
7583 * this device has been detected.
7584 */
7585 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7586 pci_channel_state_t state)
7587 {
7588 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7589 struct net_device *netdev = adapter->netdev;
7590
7591 netif_device_detach(netdev);
7592
7593 if (state == pci_channel_io_perm_failure)
7594 return PCI_ERS_RESULT_DISCONNECT;
7595
7596 if (netif_running(netdev))
7597 ixgbe_down(adapter);
7598 pci_disable_device(pdev);
7599
7600 /* Request a slot reset. */
7601 return PCI_ERS_RESULT_NEED_RESET;
7602 }
7603
7604 /**
7605 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7606 * @pdev: Pointer to PCI device
7607 *
7608 * Restart the card from scratch, as if from a cold-boot.
7609 */
7610 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7611 {
7612 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7613 pci_ers_result_t result;
7614 int err;
7615
7616 if (pci_enable_device_mem(pdev)) {
7617 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7618 result = PCI_ERS_RESULT_DISCONNECT;
7619 } else {
7620 pci_set_master(pdev);
7621 pci_restore_state(pdev);
7622 pci_save_state(pdev);
7623
7624 pci_wake_from_d3(pdev, false);
7625
7626 ixgbe_reset(adapter);
7627 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7628 result = PCI_ERS_RESULT_RECOVERED;
7629 }
7630
7631 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7632 if (err) {
7633 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7634 "failed 0x%0x\n", err);
7635 /* non-fatal, continue */
7636 }
7637
7638 return result;
7639 }
7640
7641 /**
7642 * ixgbe_io_resume - called when traffic can start flowing again.
7643 * @pdev: Pointer to PCI device
7644 *
7645 * This callback is called when the error recovery driver tells us that
7646 * its OK to resume normal operation.
7647 */
7648 static void ixgbe_io_resume(struct pci_dev *pdev)
7649 {
7650 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7651 struct net_device *netdev = adapter->netdev;
7652
7653 if (netif_running(netdev))
7654 ixgbe_up(adapter);
7655
7656 netif_device_attach(netdev);
7657 }
7658
7659 static struct pci_error_handlers ixgbe_err_handler = {
7660 .error_detected = ixgbe_io_error_detected,
7661 .slot_reset = ixgbe_io_slot_reset,
7662 .resume = ixgbe_io_resume,
7663 };
7664
7665 static struct pci_driver ixgbe_driver = {
7666 .name = ixgbe_driver_name,
7667 .id_table = ixgbe_pci_tbl,
7668 .probe = ixgbe_probe,
7669 .remove = __devexit_p(ixgbe_remove),
7670 #ifdef CONFIG_PM
7671 .suspend = ixgbe_suspend,
7672 .resume = ixgbe_resume,
7673 #endif
7674 .shutdown = ixgbe_shutdown,
7675 .err_handler = &ixgbe_err_handler
7676 };
7677
7678 /**
7679 * ixgbe_init_module - Driver Registration Routine
7680 *
7681 * ixgbe_init_module is the first routine called when the driver is
7682 * loaded. All it does is register with the PCI subsystem.
7683 **/
7684 static int __init ixgbe_init_module(void)
7685 {
7686 int ret;
7687 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7688 pr_info("%s\n", ixgbe_copyright);
7689
7690 #ifdef CONFIG_IXGBE_DCA
7691 dca_register_notify(&dca_notifier);
7692 #endif
7693
7694 ret = pci_register_driver(&ixgbe_driver);
7695 return ret;
7696 }
7697
7698 module_init(ixgbe_init_module);
7699
7700 /**
7701 * ixgbe_exit_module - Driver Exit Cleanup Routine
7702 *
7703 * ixgbe_exit_module is called just before the driver is removed
7704 * from memory.
7705 **/
7706 static void __exit ixgbe_exit_module(void)
7707 {
7708 #ifdef CONFIG_IXGBE_DCA
7709 dca_unregister_notify(&dca_notifier);
7710 #endif
7711 pci_unregister_driver(&ixgbe_driver);
7712 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7713 }
7714
7715 #ifdef CONFIG_IXGBE_DCA
7716 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7717 void *p)
7718 {
7719 int ret_val;
7720
7721 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7722 __ixgbe_notify_dca);
7723
7724 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7725 }
7726
7727 #endif /* CONFIG_IXGBE_DCA */
7728
7729 module_exit(ixgbe_exit_module);
7730
7731 /* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)