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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
49
50 #include "ixgbe.h"
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
54
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
58 #define MAJ 3
59 #define MIN 4
60 #define BUILD 8
61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
62 __stringify(BUILD) "-k"
63 const char ixgbe_driver_version[] = DRV_VERSION;
64 static const char ixgbe_copyright[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
66
67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
68 [board_82598] = &ixgbe_82598_info,
69 [board_82599] = &ixgbe_82599_info,
70 [board_X540] = &ixgbe_X540_info,
71 };
72
73 /* ixgbe_pci_tbl - PCI Device ID Table
74 *
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
77 *
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
80 */
81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
108 /* required last entry */
109 {0, }
110 };
111 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
112
113 #ifdef CONFIG_IXGBE_DCA
114 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
115 void *p);
116 static struct notifier_block dca_notifier = {
117 .notifier_call = ixgbe_notify_dca,
118 .next = NULL,
119 .priority = 0
120 };
121 #endif
122
123 #ifdef CONFIG_PCI_IOV
124 static unsigned int max_vfs;
125 module_param(max_vfs, uint, 0);
126 MODULE_PARM_DESC(max_vfs,
127 "Maximum number of virtual functions to allocate per physical function");
128 #endif /* CONFIG_PCI_IOV */
129
130 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
131 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
132 MODULE_LICENSE("GPL");
133 MODULE_VERSION(DRV_VERSION);
134
135 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
136
137 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
138 {
139 struct ixgbe_hw *hw = &adapter->hw;
140 u32 gcr;
141 u32 gpie;
142 u32 vmdctl;
143
144 #ifdef CONFIG_PCI_IOV
145 /* disable iov and allow time for transactions to clear */
146 pci_disable_sriov(adapter->pdev);
147 #endif
148
149 /* turn off device IOV mode */
150 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
151 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
152 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
153 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
154 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
155 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
156
157 /* set default pool back to 0 */
158 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
159 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
160 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
161 IXGBE_WRITE_FLUSH(hw);
162
163 /* take a breather then clean up driver data */
164 msleep(100);
165
166 kfree(adapter->vfinfo);
167 adapter->vfinfo = NULL;
168
169 adapter->num_vfs = 0;
170 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
171 }
172
173 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
174 {
175 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
176 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
177 schedule_work(&adapter->service_task);
178 }
179
180 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
181 {
182 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
183
184 /* flush memory to make sure state is correct before next watchog */
185 smp_mb__before_clear_bit();
186 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
187 }
188
189 struct ixgbe_reg_info {
190 u32 ofs;
191 char *name;
192 };
193
194 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
195
196 /* General Registers */
197 {IXGBE_CTRL, "CTRL"},
198 {IXGBE_STATUS, "STATUS"},
199 {IXGBE_CTRL_EXT, "CTRL_EXT"},
200
201 /* Interrupt Registers */
202 {IXGBE_EICR, "EICR"},
203
204 /* RX Registers */
205 {IXGBE_SRRCTL(0), "SRRCTL"},
206 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
207 {IXGBE_RDLEN(0), "RDLEN"},
208 {IXGBE_RDH(0), "RDH"},
209 {IXGBE_RDT(0), "RDT"},
210 {IXGBE_RXDCTL(0), "RXDCTL"},
211 {IXGBE_RDBAL(0), "RDBAL"},
212 {IXGBE_RDBAH(0), "RDBAH"},
213
214 /* TX Registers */
215 {IXGBE_TDBAL(0), "TDBAL"},
216 {IXGBE_TDBAH(0), "TDBAH"},
217 {IXGBE_TDLEN(0), "TDLEN"},
218 {IXGBE_TDH(0), "TDH"},
219 {IXGBE_TDT(0), "TDT"},
220 {IXGBE_TXDCTL(0), "TXDCTL"},
221
222 /* List Terminator */
223 {}
224 };
225
226
227 /*
228 * ixgbe_regdump - register printout routine
229 */
230 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
231 {
232 int i = 0, j = 0;
233 char rname[16];
234 u32 regs[64];
235
236 switch (reginfo->ofs) {
237 case IXGBE_SRRCTL(0):
238 for (i = 0; i < 64; i++)
239 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
240 break;
241 case IXGBE_DCA_RXCTRL(0):
242 for (i = 0; i < 64; i++)
243 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
244 break;
245 case IXGBE_RDLEN(0):
246 for (i = 0; i < 64; i++)
247 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
248 break;
249 case IXGBE_RDH(0):
250 for (i = 0; i < 64; i++)
251 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
252 break;
253 case IXGBE_RDT(0):
254 for (i = 0; i < 64; i++)
255 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
256 break;
257 case IXGBE_RXDCTL(0):
258 for (i = 0; i < 64; i++)
259 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
260 break;
261 case IXGBE_RDBAL(0):
262 for (i = 0; i < 64; i++)
263 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
264 break;
265 case IXGBE_RDBAH(0):
266 for (i = 0; i < 64; i++)
267 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
268 break;
269 case IXGBE_TDBAL(0):
270 for (i = 0; i < 64; i++)
271 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
272 break;
273 case IXGBE_TDBAH(0):
274 for (i = 0; i < 64; i++)
275 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
276 break;
277 case IXGBE_TDLEN(0):
278 for (i = 0; i < 64; i++)
279 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
280 break;
281 case IXGBE_TDH(0):
282 for (i = 0; i < 64; i++)
283 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
284 break;
285 case IXGBE_TDT(0):
286 for (i = 0; i < 64; i++)
287 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
288 break;
289 case IXGBE_TXDCTL(0):
290 for (i = 0; i < 64; i++)
291 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
292 break;
293 default:
294 pr_info("%-15s %08x\n", reginfo->name,
295 IXGBE_READ_REG(hw, reginfo->ofs));
296 return;
297 }
298
299 for (i = 0; i < 8; i++) {
300 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
301 pr_err("%-15s", rname);
302 for (j = 0; j < 8; j++)
303 pr_cont(" %08x", regs[i*8+j]);
304 pr_cont("\n");
305 }
306
307 }
308
309 /*
310 * ixgbe_dump - Print registers, tx-rings and rx-rings
311 */
312 static void ixgbe_dump(struct ixgbe_adapter *adapter)
313 {
314 struct net_device *netdev = adapter->netdev;
315 struct ixgbe_hw *hw = &adapter->hw;
316 struct ixgbe_reg_info *reginfo;
317 int n = 0;
318 struct ixgbe_ring *tx_ring;
319 struct ixgbe_tx_buffer *tx_buffer_info;
320 union ixgbe_adv_tx_desc *tx_desc;
321 struct my_u0 { u64 a; u64 b; } *u0;
322 struct ixgbe_ring *rx_ring;
323 union ixgbe_adv_rx_desc *rx_desc;
324 struct ixgbe_rx_buffer *rx_buffer_info;
325 u32 staterr;
326 int i = 0;
327
328 if (!netif_msg_hw(adapter))
329 return;
330
331 /* Print netdevice Info */
332 if (netdev) {
333 dev_info(&adapter->pdev->dev, "Net device Info\n");
334 pr_info("Device Name state "
335 "trans_start last_rx\n");
336 pr_info("%-15s %016lX %016lX %016lX\n",
337 netdev->name,
338 netdev->state,
339 netdev->trans_start,
340 netdev->last_rx);
341 }
342
343 /* Print Registers */
344 dev_info(&adapter->pdev->dev, "Register Dump\n");
345 pr_info(" Register Name Value\n");
346 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
347 reginfo->name; reginfo++) {
348 ixgbe_regdump(hw, reginfo);
349 }
350
351 /* Print TX Ring Summary */
352 if (!netdev || !netif_running(netdev))
353 goto exit;
354
355 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
356 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
357 for (n = 0; n < adapter->num_tx_queues; n++) {
358 tx_ring = adapter->tx_ring[n];
359 tx_buffer_info =
360 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
361 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
362 n, tx_ring->next_to_use, tx_ring->next_to_clean,
363 (u64)tx_buffer_info->dma,
364 tx_buffer_info->length,
365 tx_buffer_info->next_to_watch,
366 (u64)tx_buffer_info->time_stamp);
367 }
368
369 /* Print TX Rings */
370 if (!netif_msg_tx_done(adapter))
371 goto rx_ring_summary;
372
373 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
374
375 /* Transmit Descriptor Formats
376 *
377 * Advanced Transmit Descriptor
378 * +--------------------------------------------------------------+
379 * 0 | Buffer Address [63:0] |
380 * +--------------------------------------------------------------+
381 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
382 * +--------------------------------------------------------------+
383 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
384 */
385
386 for (n = 0; n < adapter->num_tx_queues; n++) {
387 tx_ring = adapter->tx_ring[n];
388 pr_info("------------------------------------\n");
389 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
390 pr_info("------------------------------------\n");
391 pr_info("T [desc] [address 63:0 ] "
392 "[PlPOIdStDDt Ln] [bi->dma ] "
393 "leng ntw timestamp bi->skb\n");
394
395 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
396 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
397 tx_buffer_info = &tx_ring->tx_buffer_info[i];
398 u0 = (struct my_u0 *)tx_desc;
399 pr_info("T [0x%03X] %016llX %016llX %016llX"
400 " %04X %p %016llX %p", i,
401 le64_to_cpu(u0->a),
402 le64_to_cpu(u0->b),
403 (u64)tx_buffer_info->dma,
404 tx_buffer_info->length,
405 tx_buffer_info->next_to_watch,
406 (u64)tx_buffer_info->time_stamp,
407 tx_buffer_info->skb);
408 if (i == tx_ring->next_to_use &&
409 i == tx_ring->next_to_clean)
410 pr_cont(" NTC/U\n");
411 else if (i == tx_ring->next_to_use)
412 pr_cont(" NTU\n");
413 else if (i == tx_ring->next_to_clean)
414 pr_cont(" NTC\n");
415 else
416 pr_cont("\n");
417
418 if (netif_msg_pktdata(adapter) &&
419 tx_buffer_info->dma != 0)
420 print_hex_dump(KERN_INFO, "",
421 DUMP_PREFIX_ADDRESS, 16, 1,
422 phys_to_virt(tx_buffer_info->dma),
423 tx_buffer_info->length, true);
424 }
425 }
426
427 /* Print RX Rings Summary */
428 rx_ring_summary:
429 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
430 pr_info("Queue [NTU] [NTC]\n");
431 for (n = 0; n < adapter->num_rx_queues; n++) {
432 rx_ring = adapter->rx_ring[n];
433 pr_info("%5d %5X %5X\n",
434 n, rx_ring->next_to_use, rx_ring->next_to_clean);
435 }
436
437 /* Print RX Rings */
438 if (!netif_msg_rx_status(adapter))
439 goto exit;
440
441 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
442
443 /* Advanced Receive Descriptor (Read) Format
444 * 63 1 0
445 * +-----------------------------------------------------+
446 * 0 | Packet Buffer Address [63:1] |A0/NSE|
447 * +----------------------------------------------+------+
448 * 8 | Header Buffer Address [63:1] | DD |
449 * +-----------------------------------------------------+
450 *
451 *
452 * Advanced Receive Descriptor (Write-Back) Format
453 *
454 * 63 48 47 32 31 30 21 20 16 15 4 3 0
455 * +------------------------------------------------------+
456 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
457 * | Checksum Ident | | | | Type | Type |
458 * +------------------------------------------------------+
459 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
460 * +------------------------------------------------------+
461 * 63 48 47 32 31 20 19 0
462 */
463 for (n = 0; n < adapter->num_rx_queues; n++) {
464 rx_ring = adapter->rx_ring[n];
465 pr_info("------------------------------------\n");
466 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
467 pr_info("------------------------------------\n");
468 pr_info("R [desc] [ PktBuf A0] "
469 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
470 "<-- Adv Rx Read format\n");
471 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
472 "[vl er S cks ln] ---------------- [bi->skb] "
473 "<-- Adv Rx Write-Back format\n");
474
475 for (i = 0; i < rx_ring->count; i++) {
476 rx_buffer_info = &rx_ring->rx_buffer_info[i];
477 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
478 u0 = (struct my_u0 *)rx_desc;
479 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
480 if (staterr & IXGBE_RXD_STAT_DD) {
481 /* Descriptor Done */
482 pr_info("RWB[0x%03X] %016llX "
483 "%016llX ---------------- %p", i,
484 le64_to_cpu(u0->a),
485 le64_to_cpu(u0->b),
486 rx_buffer_info->skb);
487 } else {
488 pr_info("R [0x%03X] %016llX "
489 "%016llX %016llX %p", i,
490 le64_to_cpu(u0->a),
491 le64_to_cpu(u0->b),
492 (u64)rx_buffer_info->dma,
493 rx_buffer_info->skb);
494
495 if (netif_msg_pktdata(adapter)) {
496 print_hex_dump(KERN_INFO, "",
497 DUMP_PREFIX_ADDRESS, 16, 1,
498 phys_to_virt(rx_buffer_info->dma),
499 rx_ring->rx_buf_len, true);
500
501 if (rx_ring->rx_buf_len
502 < IXGBE_RXBUFFER_2048)
503 print_hex_dump(KERN_INFO, "",
504 DUMP_PREFIX_ADDRESS, 16, 1,
505 phys_to_virt(
506 rx_buffer_info->page_dma +
507 rx_buffer_info->page_offset
508 ),
509 PAGE_SIZE/2, true);
510 }
511 }
512
513 if (i == rx_ring->next_to_use)
514 pr_cont(" NTU\n");
515 else if (i == rx_ring->next_to_clean)
516 pr_cont(" NTC\n");
517 else
518 pr_cont("\n");
519
520 }
521 }
522
523 exit:
524 return;
525 }
526
527 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
528 {
529 u32 ctrl_ext;
530
531 /* Let firmware take over control of h/w */
532 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
534 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
535 }
536
537 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
538 {
539 u32 ctrl_ext;
540
541 /* Let firmware know the driver has taken over */
542 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
543 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
544 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
545 }
546
547 /*
548 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
549 * @adapter: pointer to adapter struct
550 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
551 * @queue: queue to map the corresponding interrupt to
552 * @msix_vector: the vector to map to the corresponding queue
553 *
554 */
555 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
556 u8 queue, u8 msix_vector)
557 {
558 u32 ivar, index;
559 struct ixgbe_hw *hw = &adapter->hw;
560 switch (hw->mac.type) {
561 case ixgbe_mac_82598EB:
562 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
563 if (direction == -1)
564 direction = 0;
565 index = (((direction * 64) + queue) >> 2) & 0x1F;
566 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
567 ivar &= ~(0xFF << (8 * (queue & 0x3)));
568 ivar |= (msix_vector << (8 * (queue & 0x3)));
569 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
570 break;
571 case ixgbe_mac_82599EB:
572 case ixgbe_mac_X540:
573 if (direction == -1) {
574 /* other causes */
575 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
576 index = ((queue & 1) * 8);
577 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
578 ivar &= ~(0xFF << index);
579 ivar |= (msix_vector << index);
580 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
581 break;
582 } else {
583 /* tx or rx causes */
584 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
585 index = ((16 * (queue & 1)) + (8 * direction));
586 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
587 ivar &= ~(0xFF << index);
588 ivar |= (msix_vector << index);
589 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
590 break;
591 }
592 default:
593 break;
594 }
595 }
596
597 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
598 u64 qmask)
599 {
600 u32 mask;
601
602 switch (adapter->hw.mac.type) {
603 case ixgbe_mac_82598EB:
604 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
606 break;
607 case ixgbe_mac_82599EB:
608 case ixgbe_mac_X540:
609 mask = (qmask & 0xFFFFFFFF);
610 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
611 mask = (qmask >> 32);
612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
613 break;
614 default:
615 break;
616 }
617 }
618
619 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
620 struct ixgbe_tx_buffer *tx_buffer)
621 {
622 if (tx_buffer->dma) {
623 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
624 dma_unmap_page(ring->dev,
625 tx_buffer->dma,
626 tx_buffer->length,
627 DMA_TO_DEVICE);
628 else
629 dma_unmap_single(ring->dev,
630 tx_buffer->dma,
631 tx_buffer->length,
632 DMA_TO_DEVICE);
633 }
634 tx_buffer->dma = 0;
635 }
636
637 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
638 struct ixgbe_tx_buffer *tx_buffer_info)
639 {
640 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
641 if (tx_buffer_info->skb)
642 dev_kfree_skb_any(tx_buffer_info->skb);
643 tx_buffer_info->skb = NULL;
644 /* tx_buffer_info must be completely set up in the transmit path */
645 }
646
647 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
648 {
649 struct ixgbe_hw *hw = &adapter->hw;
650 struct ixgbe_hw_stats *hwstats = &adapter->stats;
651 u32 data = 0;
652 u32 xoff[8] = {0};
653 int i;
654
655 if ((hw->fc.current_mode == ixgbe_fc_full) ||
656 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
657 switch (hw->mac.type) {
658 case ixgbe_mac_82598EB:
659 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
660 break;
661 default:
662 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
663 }
664 hwstats->lxoffrxc += data;
665
666 /* refill credits (no tx hang) if we received xoff */
667 if (!data)
668 return;
669
670 for (i = 0; i < adapter->num_tx_queues; i++)
671 clear_bit(__IXGBE_HANG_CHECK_ARMED,
672 &adapter->tx_ring[i]->state);
673 return;
674 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
675 return;
676
677 /* update stats for each tc, only valid with PFC enabled */
678 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
679 switch (hw->mac.type) {
680 case ixgbe_mac_82598EB:
681 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
682 break;
683 default:
684 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
685 }
686 hwstats->pxoffrxc[i] += xoff[i];
687 }
688
689 /* disarm tx queues that have received xoff frames */
690 for (i = 0; i < adapter->num_tx_queues; i++) {
691 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
692 u8 tc = tx_ring->dcb_tc;
693
694 if (xoff[tc])
695 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
696 }
697 }
698
699 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
700 {
701 return ring->tx_stats.completed;
702 }
703
704 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
705 {
706 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
707 struct ixgbe_hw *hw = &adapter->hw;
708
709 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
710 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
711
712 if (head != tail)
713 return (head < tail) ?
714 tail - head : (tail + ring->count - head);
715
716 return 0;
717 }
718
719 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
720 {
721 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
722 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
723 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
724 bool ret = false;
725
726 clear_check_for_tx_hang(tx_ring);
727
728 /*
729 * Check for a hung queue, but be thorough. This verifies
730 * that a transmit has been completed since the previous
731 * check AND there is at least one packet pending. The
732 * ARMED bit is set to indicate a potential hang. The
733 * bit is cleared if a pause frame is received to remove
734 * false hang detection due to PFC or 802.3x frames. By
735 * requiring this to fail twice we avoid races with
736 * pfc clearing the ARMED bit and conditions where we
737 * run the check_tx_hang logic with a transmit completion
738 * pending but without time to complete it yet.
739 */
740 if ((tx_done_old == tx_done) && tx_pending) {
741 /* make sure it is true for two checks in a row */
742 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
743 &tx_ring->state);
744 } else {
745 /* update completed stats and continue */
746 tx_ring->tx_stats.tx_done_old = tx_done;
747 /* reset the countdown */
748 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
749 }
750
751 return ret;
752 }
753
754 /**
755 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
756 * @adapter: driver private struct
757 **/
758 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
759 {
760
761 /* Do the reset outside of interrupt context */
762 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
763 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
764 ixgbe_service_event_schedule(adapter);
765 }
766 }
767
768 /**
769 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
770 * @q_vector: structure containing interrupt and ring information
771 * @tx_ring: tx ring to clean
772 **/
773 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
774 struct ixgbe_ring *tx_ring)
775 {
776 struct ixgbe_adapter *adapter = q_vector->adapter;
777 struct ixgbe_tx_buffer *tx_buffer;
778 union ixgbe_adv_tx_desc *tx_desc;
779 unsigned int total_bytes = 0, total_packets = 0;
780 unsigned int budget = q_vector->tx.work_limit;
781 u16 i = tx_ring->next_to_clean;
782
783 tx_buffer = &tx_ring->tx_buffer_info[i];
784 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
785
786 for (; budget; budget--) {
787 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
788
789 /* if next_to_watch is not set then there is no work pending */
790 if (!eop_desc)
791 break;
792
793 /* if DD is not set pending work has not been completed */
794 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
795 break;
796
797 /* count the packet as being completed */
798 tx_ring->tx_stats.completed++;
799
800 /* clear next_to_watch to prevent false hangs */
801 tx_buffer->next_to_watch = NULL;
802
803 /* prevent any other reads prior to eop_desc being verified */
804 rmb();
805
806 do {
807 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
808 tx_desc->wb.status = 0;
809 if (likely(tx_desc == eop_desc)) {
810 eop_desc = NULL;
811 dev_kfree_skb_any(tx_buffer->skb);
812 tx_buffer->skb = NULL;
813
814 total_bytes += tx_buffer->bytecount;
815 total_packets += tx_buffer->gso_segs;
816 }
817
818 tx_buffer++;
819 tx_desc++;
820 i++;
821 if (unlikely(i == tx_ring->count)) {
822 i = 0;
823
824 tx_buffer = tx_ring->tx_buffer_info;
825 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
826 }
827
828 } while (eop_desc);
829 }
830
831 tx_ring->next_to_clean = i;
832 u64_stats_update_begin(&tx_ring->syncp);
833 tx_ring->stats.bytes += total_bytes;
834 tx_ring->stats.packets += total_packets;
835 u64_stats_update_end(&tx_ring->syncp);
836 q_vector->tx.total_bytes += total_bytes;
837 q_vector->tx.total_packets += total_packets;
838
839 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
840 /* schedule immediate reset if we believe we hung */
841 struct ixgbe_hw *hw = &adapter->hw;
842 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
843 e_err(drv, "Detected Tx Unit Hang\n"
844 " Tx Queue <%d>\n"
845 " TDH, TDT <%x>, <%x>\n"
846 " next_to_use <%x>\n"
847 " next_to_clean <%x>\n"
848 "tx_buffer_info[next_to_clean]\n"
849 " time_stamp <%lx>\n"
850 " jiffies <%lx>\n",
851 tx_ring->queue_index,
852 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
853 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
854 tx_ring->next_to_use, i,
855 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
856
857 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
858
859 e_info(probe,
860 "tx hang %d detected on queue %d, resetting adapter\n",
861 adapter->tx_timeout_count + 1, tx_ring->queue_index);
862
863 /* schedule immediate reset if we believe we hung */
864 ixgbe_tx_timeout_reset(adapter);
865
866 /* the adapter is about to reset, no point in enabling stuff */
867 return true;
868 }
869
870 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
871 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
872 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
873 /* Make sure that anybody stopping the queue after this
874 * sees the new next_to_clean.
875 */
876 smp_mb();
877 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
878 !test_bit(__IXGBE_DOWN, &adapter->state)) {
879 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
880 ++tx_ring->tx_stats.restart_queue;
881 }
882 }
883
884 return !!budget;
885 }
886
887 #ifdef CONFIG_IXGBE_DCA
888 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
889 struct ixgbe_ring *rx_ring,
890 int cpu)
891 {
892 struct ixgbe_hw *hw = &adapter->hw;
893 u32 rxctrl;
894 u8 reg_idx = rx_ring->reg_idx;
895
896 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
897 switch (hw->mac.type) {
898 case ixgbe_mac_82598EB:
899 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
900 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
901 break;
902 case ixgbe_mac_82599EB:
903 case ixgbe_mac_X540:
904 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
905 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
906 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
907 break;
908 default:
909 break;
910 }
911 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
912 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
913 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
914 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
915 }
916
917 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
918 struct ixgbe_ring *tx_ring,
919 int cpu)
920 {
921 struct ixgbe_hw *hw = &adapter->hw;
922 u32 txctrl;
923 u8 reg_idx = tx_ring->reg_idx;
924
925 switch (hw->mac.type) {
926 case ixgbe_mac_82598EB:
927 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
928 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
929 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
930 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
931 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
932 break;
933 case ixgbe_mac_82599EB:
934 case ixgbe_mac_X540:
935 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
936 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
937 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
938 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
939 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
940 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
941 break;
942 default:
943 break;
944 }
945 }
946
947 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
948 {
949 struct ixgbe_adapter *adapter = q_vector->adapter;
950 struct ixgbe_ring *ring;
951 int cpu = get_cpu();
952
953 if (q_vector->cpu == cpu)
954 goto out_no_update;
955
956 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
957 ixgbe_update_tx_dca(adapter, ring, cpu);
958
959 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
960 ixgbe_update_rx_dca(adapter, ring, cpu);
961
962 q_vector->cpu = cpu;
963 out_no_update:
964 put_cpu();
965 }
966
967 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
968 {
969 int num_q_vectors;
970 int i;
971
972 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
973 return;
974
975 /* always use CB2 mode, difference is masked in the CB driver */
976 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
977
978 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
979 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
980 else
981 num_q_vectors = 1;
982
983 for (i = 0; i < num_q_vectors; i++) {
984 adapter->q_vector[i]->cpu = -1;
985 ixgbe_update_dca(adapter->q_vector[i]);
986 }
987 }
988
989 static int __ixgbe_notify_dca(struct device *dev, void *data)
990 {
991 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
992 unsigned long event = *(unsigned long *)data;
993
994 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
995 return 0;
996
997 switch (event) {
998 case DCA_PROVIDER_ADD:
999 /* if we're already enabled, don't do it again */
1000 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1001 break;
1002 if (dca_add_requester(dev) == 0) {
1003 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1004 ixgbe_setup_dca(adapter);
1005 break;
1006 }
1007 /* Fall Through since DCA is disabled. */
1008 case DCA_PROVIDER_REMOVE:
1009 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1010 dca_remove_requester(dev);
1011 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1012 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1013 }
1014 break;
1015 }
1016
1017 return 0;
1018 }
1019 #endif /* CONFIG_IXGBE_DCA */
1020
1021 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1022 struct sk_buff *skb)
1023 {
1024 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1025 }
1026
1027 /**
1028 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1029 * @adapter: address of board private structure
1030 * @rx_desc: advanced rx descriptor
1031 *
1032 * Returns : true if it is FCoE pkt
1033 */
1034 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1035 union ixgbe_adv_rx_desc *rx_desc)
1036 {
1037 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1038
1039 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1040 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1041 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1042 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1043 }
1044
1045 /**
1046 * ixgbe_receive_skb - Send a completed packet up the stack
1047 * @adapter: board private structure
1048 * @skb: packet to send up
1049 * @status: hardware indication of status of receive
1050 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1051 * @rx_desc: rx descriptor
1052 **/
1053 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1054 struct sk_buff *skb, u8 status,
1055 struct ixgbe_ring *ring,
1056 union ixgbe_adv_rx_desc *rx_desc)
1057 {
1058 struct ixgbe_adapter *adapter = q_vector->adapter;
1059 struct napi_struct *napi = &q_vector->napi;
1060 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1061 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1062
1063 if (is_vlan && (tag & VLAN_VID_MASK))
1064 __vlan_hwaccel_put_tag(skb, tag);
1065
1066 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1067 napi_gro_receive(napi, skb);
1068 else
1069 netif_rx(skb);
1070 }
1071
1072 /**
1073 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1074 * @adapter: address of board private structure
1075 * @status_err: hardware indication of status of receive
1076 * @skb: skb currently being received and modified
1077 * @status_err: status error value of last descriptor in packet
1078 **/
1079 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1080 union ixgbe_adv_rx_desc *rx_desc,
1081 struct sk_buff *skb,
1082 u32 status_err)
1083 {
1084 skb->ip_summed = CHECKSUM_NONE;
1085
1086 /* Rx csum disabled */
1087 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1088 return;
1089
1090 /* if IP and error */
1091 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1092 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1093 adapter->hw_csum_rx_error++;
1094 return;
1095 }
1096
1097 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1098 return;
1099
1100 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1101 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1102
1103 /*
1104 * 82599 errata, UDP frames with a 0 checksum can be marked as
1105 * checksum errors.
1106 */
1107 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1108 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1109 return;
1110
1111 adapter->hw_csum_rx_error++;
1112 return;
1113 }
1114
1115 /* It must be a TCP or UDP packet with a valid checksum */
1116 skb->ip_summed = CHECKSUM_UNNECESSARY;
1117 }
1118
1119 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1120 {
1121 /*
1122 * Force memory writes to complete before letting h/w
1123 * know there are new descriptors to fetch. (Only
1124 * applicable for weak-ordered memory model archs,
1125 * such as IA-64).
1126 */
1127 wmb();
1128 writel(val, rx_ring->tail);
1129 }
1130
1131 /**
1132 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1133 * @rx_ring: ring to place buffers on
1134 * @cleaned_count: number of buffers to replace
1135 **/
1136 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1137 {
1138 union ixgbe_adv_rx_desc *rx_desc;
1139 struct ixgbe_rx_buffer *bi;
1140 struct sk_buff *skb;
1141 u16 i = rx_ring->next_to_use;
1142
1143 /* do nothing if no valid netdev defined */
1144 if (!rx_ring->netdev)
1145 return;
1146
1147 while (cleaned_count--) {
1148 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1149 bi = &rx_ring->rx_buffer_info[i];
1150 skb = bi->skb;
1151
1152 if (!skb) {
1153 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1154 rx_ring->rx_buf_len);
1155 if (!skb) {
1156 rx_ring->rx_stats.alloc_rx_buff_failed++;
1157 goto no_buffers;
1158 }
1159 /* initialize queue mapping */
1160 skb_record_rx_queue(skb, rx_ring->queue_index);
1161 bi->skb = skb;
1162 }
1163
1164 if (!bi->dma) {
1165 bi->dma = dma_map_single(rx_ring->dev,
1166 skb->data,
1167 rx_ring->rx_buf_len,
1168 DMA_FROM_DEVICE);
1169 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1170 rx_ring->rx_stats.alloc_rx_buff_failed++;
1171 bi->dma = 0;
1172 goto no_buffers;
1173 }
1174 }
1175
1176 if (ring_is_ps_enabled(rx_ring)) {
1177 if (!bi->page) {
1178 bi->page = netdev_alloc_page(rx_ring->netdev);
1179 if (!bi->page) {
1180 rx_ring->rx_stats.alloc_rx_page_failed++;
1181 goto no_buffers;
1182 }
1183 }
1184
1185 if (!bi->page_dma) {
1186 /* use a half page if we're re-using */
1187 bi->page_offset ^= PAGE_SIZE / 2;
1188 bi->page_dma = dma_map_page(rx_ring->dev,
1189 bi->page,
1190 bi->page_offset,
1191 PAGE_SIZE / 2,
1192 DMA_FROM_DEVICE);
1193 if (dma_mapping_error(rx_ring->dev,
1194 bi->page_dma)) {
1195 rx_ring->rx_stats.alloc_rx_page_failed++;
1196 bi->page_dma = 0;
1197 goto no_buffers;
1198 }
1199 }
1200
1201 /* Refresh the desc even if buffer_addrs didn't change
1202 * because each write-back erases this info. */
1203 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1204 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1205 } else {
1206 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1207 rx_desc->read.hdr_addr = 0;
1208 }
1209
1210 i++;
1211 if (i == rx_ring->count)
1212 i = 0;
1213 }
1214
1215 no_buffers:
1216 if (rx_ring->next_to_use != i) {
1217 rx_ring->next_to_use = i;
1218 ixgbe_release_rx_desc(rx_ring, i);
1219 }
1220 }
1221
1222 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1223 {
1224 /* HW will not DMA in data larger than the given buffer, even if it
1225 * parses the (NFS, of course) header to be larger. In that case, it
1226 * fills the header buffer and spills the rest into the page.
1227 */
1228 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1229 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1230 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1231 if (hlen > IXGBE_RX_HDR_SIZE)
1232 hlen = IXGBE_RX_HDR_SIZE;
1233 return hlen;
1234 }
1235
1236 /**
1237 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1238 * @skb: pointer to the last skb in the rsc queue
1239 *
1240 * This function changes a queue full of hw rsc buffers into a completed
1241 * packet. It uses the ->prev pointers to find the first packet and then
1242 * turns it into the frag list owner.
1243 **/
1244 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1245 {
1246 unsigned int frag_list_size = 0;
1247 unsigned int skb_cnt = 1;
1248
1249 while (skb->prev) {
1250 struct sk_buff *prev = skb->prev;
1251 frag_list_size += skb->len;
1252 skb->prev = NULL;
1253 skb = prev;
1254 skb_cnt++;
1255 }
1256
1257 skb_shinfo(skb)->frag_list = skb->next;
1258 skb->next = NULL;
1259 skb->len += frag_list_size;
1260 skb->data_len += frag_list_size;
1261 skb->truesize += frag_list_size;
1262 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1263
1264 return skb;
1265 }
1266
1267 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1268 {
1269 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1270 IXGBE_RXDADV_RSCCNT_MASK);
1271 }
1272
1273 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1274 struct ixgbe_ring *rx_ring,
1275 int budget)
1276 {
1277 struct ixgbe_adapter *adapter = q_vector->adapter;
1278 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1279 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1280 struct sk_buff *skb;
1281 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1282 const int current_node = numa_node_id();
1283 #ifdef IXGBE_FCOE
1284 int ddp_bytes = 0;
1285 #endif /* IXGBE_FCOE */
1286 u32 staterr;
1287 u16 i;
1288 u16 cleaned_count = 0;
1289 bool pkt_is_rsc = false;
1290
1291 i = rx_ring->next_to_clean;
1292 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1293 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1294
1295 while (staterr & IXGBE_RXD_STAT_DD) {
1296 u32 upper_len = 0;
1297
1298 rmb(); /* read descriptor and rx_buffer_info after status DD */
1299
1300 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1301
1302 skb = rx_buffer_info->skb;
1303 rx_buffer_info->skb = NULL;
1304 prefetch(skb->data);
1305
1306 if (ring_is_rsc_enabled(rx_ring))
1307 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1308
1309 /* if this is a skb from previous receive DMA will be 0 */
1310 if (rx_buffer_info->dma) {
1311 u16 hlen;
1312 if (pkt_is_rsc &&
1313 !(staterr & IXGBE_RXD_STAT_EOP) &&
1314 !skb->prev) {
1315 /*
1316 * When HWRSC is enabled, delay unmapping
1317 * of the first packet. It carries the
1318 * header information, HW may still
1319 * access the header after the writeback.
1320 * Only unmap it when EOP is reached
1321 */
1322 IXGBE_RSC_CB(skb)->delay_unmap = true;
1323 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1324 } else {
1325 dma_unmap_single(rx_ring->dev,
1326 rx_buffer_info->dma,
1327 rx_ring->rx_buf_len,
1328 DMA_FROM_DEVICE);
1329 }
1330 rx_buffer_info->dma = 0;
1331
1332 if (ring_is_ps_enabled(rx_ring)) {
1333 hlen = ixgbe_get_hlen(rx_desc);
1334 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1335 } else {
1336 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1337 }
1338
1339 skb_put(skb, hlen);
1340 } else {
1341 /* assume packet split since header is unmapped */
1342 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1343 }
1344
1345 if (upper_len) {
1346 dma_unmap_page(rx_ring->dev,
1347 rx_buffer_info->page_dma,
1348 PAGE_SIZE / 2,
1349 DMA_FROM_DEVICE);
1350 rx_buffer_info->page_dma = 0;
1351 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1352 rx_buffer_info->page,
1353 rx_buffer_info->page_offset,
1354 upper_len);
1355
1356 if ((page_count(rx_buffer_info->page) == 1) &&
1357 (page_to_nid(rx_buffer_info->page) == current_node))
1358 get_page(rx_buffer_info->page);
1359 else
1360 rx_buffer_info->page = NULL;
1361
1362 skb->len += upper_len;
1363 skb->data_len += upper_len;
1364 skb->truesize += upper_len;
1365 }
1366
1367 i++;
1368 if (i == rx_ring->count)
1369 i = 0;
1370
1371 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1372 prefetch(next_rxd);
1373 cleaned_count++;
1374
1375 if (pkt_is_rsc) {
1376 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1377 IXGBE_RXDADV_NEXTP_SHIFT;
1378 next_buffer = &rx_ring->rx_buffer_info[nextp];
1379 } else {
1380 next_buffer = &rx_ring->rx_buffer_info[i];
1381 }
1382
1383 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1384 if (ring_is_ps_enabled(rx_ring)) {
1385 rx_buffer_info->skb = next_buffer->skb;
1386 rx_buffer_info->dma = next_buffer->dma;
1387 next_buffer->skb = skb;
1388 next_buffer->dma = 0;
1389 } else {
1390 skb->next = next_buffer->skb;
1391 skb->next->prev = skb;
1392 }
1393 rx_ring->rx_stats.non_eop_descs++;
1394 goto next_desc;
1395 }
1396
1397 if (skb->prev) {
1398 skb = ixgbe_transform_rsc_queue(skb);
1399 /* if we got here without RSC the packet is invalid */
1400 if (!pkt_is_rsc) {
1401 __pskb_trim(skb, 0);
1402 rx_buffer_info->skb = skb;
1403 goto next_desc;
1404 }
1405 }
1406
1407 if (ring_is_rsc_enabled(rx_ring)) {
1408 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1409 dma_unmap_single(rx_ring->dev,
1410 IXGBE_RSC_CB(skb)->dma,
1411 rx_ring->rx_buf_len,
1412 DMA_FROM_DEVICE);
1413 IXGBE_RSC_CB(skb)->dma = 0;
1414 IXGBE_RSC_CB(skb)->delay_unmap = false;
1415 }
1416 }
1417 if (pkt_is_rsc) {
1418 if (ring_is_ps_enabled(rx_ring))
1419 rx_ring->rx_stats.rsc_count +=
1420 skb_shinfo(skb)->nr_frags;
1421 else
1422 rx_ring->rx_stats.rsc_count +=
1423 IXGBE_RSC_CB(skb)->skb_cnt;
1424 rx_ring->rx_stats.rsc_flush++;
1425 }
1426
1427 /* ERR_MASK will only have valid bits if EOP set */
1428 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1429 dev_kfree_skb_any(skb);
1430 goto next_desc;
1431 }
1432
1433 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1434 if (adapter->netdev->features & NETIF_F_RXHASH)
1435 ixgbe_rx_hash(rx_desc, skb);
1436
1437 /* probably a little skewed due to removing CRC */
1438 total_rx_bytes += skb->len;
1439 total_rx_packets++;
1440
1441 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1442 #ifdef IXGBE_FCOE
1443 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1444 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1445 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1446 staterr);
1447 if (!ddp_bytes) {
1448 dev_kfree_skb_any(skb);
1449 goto next_desc;
1450 }
1451 }
1452 #endif /* IXGBE_FCOE */
1453 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1454
1455 budget--;
1456 next_desc:
1457 rx_desc->wb.upper.status_error = 0;
1458
1459 if (!budget)
1460 break;
1461
1462 /* return some buffers to hardware, one at a time is too slow */
1463 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1464 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1465 cleaned_count = 0;
1466 }
1467
1468 /* use prefetched values */
1469 rx_desc = next_rxd;
1470 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1471 }
1472
1473 rx_ring->next_to_clean = i;
1474 cleaned_count = ixgbe_desc_unused(rx_ring);
1475
1476 if (cleaned_count)
1477 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1478
1479 #ifdef IXGBE_FCOE
1480 /* include DDPed FCoE data */
1481 if (ddp_bytes > 0) {
1482 unsigned int mss;
1483
1484 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1485 sizeof(struct fc_frame_header) -
1486 sizeof(struct fcoe_crc_eof);
1487 if (mss > 512)
1488 mss &= ~511;
1489 total_rx_bytes += ddp_bytes;
1490 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1491 }
1492 #endif /* IXGBE_FCOE */
1493
1494 u64_stats_update_begin(&rx_ring->syncp);
1495 rx_ring->stats.packets += total_rx_packets;
1496 rx_ring->stats.bytes += total_rx_bytes;
1497 u64_stats_update_end(&rx_ring->syncp);
1498 q_vector->rx.total_packets += total_rx_packets;
1499 q_vector->rx.total_bytes += total_rx_bytes;
1500
1501 return !!budget;
1502 }
1503
1504 /**
1505 * ixgbe_configure_msix - Configure MSI-X hardware
1506 * @adapter: board private structure
1507 *
1508 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1509 * interrupts.
1510 **/
1511 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1512 {
1513 struct ixgbe_q_vector *q_vector;
1514 int q_vectors, v_idx;
1515 u32 mask;
1516
1517 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1518
1519 /* Populate MSIX to EITR Select */
1520 if (adapter->num_vfs > 32) {
1521 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1522 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1523 }
1524
1525 /*
1526 * Populate the IVAR table and set the ITR values to the
1527 * corresponding register.
1528 */
1529 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1530 struct ixgbe_ring *ring;
1531 q_vector = adapter->q_vector[v_idx];
1532
1533 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1534 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1535
1536 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1537 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1538
1539 if (q_vector->tx.ring && !q_vector->rx.ring)
1540 /* tx only */
1541 q_vector->eitr = adapter->tx_eitr_param;
1542 else if (q_vector->rx.ring)
1543 /* rx or mixed */
1544 q_vector->eitr = adapter->rx_eitr_param;
1545
1546 ixgbe_write_eitr(q_vector);
1547 }
1548
1549 switch (adapter->hw.mac.type) {
1550 case ixgbe_mac_82598EB:
1551 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1552 v_idx);
1553 break;
1554 case ixgbe_mac_82599EB:
1555 case ixgbe_mac_X540:
1556 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1557 break;
1558
1559 default:
1560 break;
1561 }
1562 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1563
1564 /* set up to autoclear timer, and the vectors */
1565 mask = IXGBE_EIMS_ENABLE_MASK;
1566 if (adapter->num_vfs)
1567 mask &= ~(IXGBE_EIMS_OTHER |
1568 IXGBE_EIMS_MAILBOX |
1569 IXGBE_EIMS_LSC);
1570 else
1571 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1572 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1573 }
1574
1575 enum latency_range {
1576 lowest_latency = 0,
1577 low_latency = 1,
1578 bulk_latency = 2,
1579 latency_invalid = 255
1580 };
1581
1582 /**
1583 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1584 * @q_vector: structure containing interrupt and ring information
1585 * @ring_container: structure containing ring performance data
1586 *
1587 * Stores a new ITR value based on packets and byte
1588 * counts during the last interrupt. The advantage of per interrupt
1589 * computation is faster updates and more accurate ITR for the current
1590 * traffic pattern. Constants in this function were computed
1591 * based on theoretical maximum wire speed and thresholds were set based
1592 * on testing data as well as attempting to minimize response time
1593 * while increasing bulk throughput.
1594 * this functionality is controlled by the InterruptThrottleRate module
1595 * parameter (see ixgbe_param.c)
1596 **/
1597 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1598 struct ixgbe_ring_container *ring_container)
1599 {
1600 u64 bytes_perint;
1601 struct ixgbe_adapter *adapter = q_vector->adapter;
1602 int bytes = ring_container->total_bytes;
1603 int packets = ring_container->total_packets;
1604 u32 timepassed_us;
1605 u8 itr_setting = ring_container->itr;
1606
1607 if (packets == 0)
1608 return;
1609
1610 /* simple throttlerate management
1611 * 0-20MB/s lowest (100000 ints/s)
1612 * 20-100MB/s low (20000 ints/s)
1613 * 100-1249MB/s bulk (8000 ints/s)
1614 */
1615 /* what was last interrupt timeslice? */
1616 timepassed_us = 1000000/q_vector->eitr;
1617 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1618
1619 switch (itr_setting) {
1620 case lowest_latency:
1621 if (bytes_perint > adapter->eitr_low)
1622 itr_setting = low_latency;
1623 break;
1624 case low_latency:
1625 if (bytes_perint > adapter->eitr_high)
1626 itr_setting = bulk_latency;
1627 else if (bytes_perint <= adapter->eitr_low)
1628 itr_setting = lowest_latency;
1629 break;
1630 case bulk_latency:
1631 if (bytes_perint <= adapter->eitr_high)
1632 itr_setting = low_latency;
1633 break;
1634 }
1635
1636 /* clear work counters since we have the values we need */
1637 ring_container->total_bytes = 0;
1638 ring_container->total_packets = 0;
1639
1640 /* write updated itr to ring container */
1641 ring_container->itr = itr_setting;
1642 }
1643
1644 /**
1645 * ixgbe_write_eitr - write EITR register in hardware specific way
1646 * @q_vector: structure containing interrupt and ring information
1647 *
1648 * This function is made to be called by ethtool and by the driver
1649 * when it needs to update EITR registers at runtime. Hardware
1650 * specific quirks/differences are taken care of here.
1651 */
1652 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1653 {
1654 struct ixgbe_adapter *adapter = q_vector->adapter;
1655 struct ixgbe_hw *hw = &adapter->hw;
1656 int v_idx = q_vector->v_idx;
1657 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1658
1659 switch (adapter->hw.mac.type) {
1660 case ixgbe_mac_82598EB:
1661 /* must write high and low 16 bits to reset counter */
1662 itr_reg |= (itr_reg << 16);
1663 break;
1664 case ixgbe_mac_82599EB:
1665 case ixgbe_mac_X540:
1666 /*
1667 * 82599 and X540 can support a value of zero, so allow it for
1668 * max interrupt rate, but there is an errata where it can
1669 * not be zero with RSC
1670 */
1671 if (itr_reg == 8 &&
1672 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1673 itr_reg = 0;
1674
1675 /*
1676 * set the WDIS bit to not clear the timer bits and cause an
1677 * immediate assertion of the interrupt
1678 */
1679 itr_reg |= IXGBE_EITR_CNT_WDIS;
1680 break;
1681 default:
1682 break;
1683 }
1684 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1685 }
1686
1687 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1688 {
1689 u32 new_itr = q_vector->eitr;
1690 u8 current_itr;
1691
1692 ixgbe_update_itr(q_vector, &q_vector->tx);
1693 ixgbe_update_itr(q_vector, &q_vector->rx);
1694
1695 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1696
1697 switch (current_itr) {
1698 /* counts and packets in update_itr are dependent on these numbers */
1699 case lowest_latency:
1700 new_itr = 100000;
1701 break;
1702 case low_latency:
1703 new_itr = 20000; /* aka hwitr = ~200 */
1704 break;
1705 case bulk_latency:
1706 new_itr = 8000;
1707 break;
1708 default:
1709 break;
1710 }
1711
1712 if (new_itr != q_vector->eitr) {
1713 /* do an exponential smoothing */
1714 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1715
1716 /* save the algorithm value here */
1717 q_vector->eitr = new_itr;
1718
1719 ixgbe_write_eitr(q_vector);
1720 }
1721 }
1722
1723 /**
1724 * ixgbe_check_overtemp_subtask - check for over tempurature
1725 * @adapter: pointer to adapter
1726 **/
1727 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1728 {
1729 struct ixgbe_hw *hw = &adapter->hw;
1730 u32 eicr = adapter->interrupt_event;
1731
1732 if (test_bit(__IXGBE_DOWN, &adapter->state))
1733 return;
1734
1735 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1736 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1737 return;
1738
1739 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1740
1741 switch (hw->device_id) {
1742 case IXGBE_DEV_ID_82599_T3_LOM:
1743 /*
1744 * Since the warning interrupt is for both ports
1745 * we don't have to check if:
1746 * - This interrupt wasn't for our port.
1747 * - We may have missed the interrupt so always have to
1748 * check if we got a LSC
1749 */
1750 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1751 !(eicr & IXGBE_EICR_LSC))
1752 return;
1753
1754 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1755 u32 autoneg;
1756 bool link_up = false;
1757
1758 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1759
1760 if (link_up)
1761 return;
1762 }
1763
1764 /* Check if this is not due to overtemp */
1765 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1766 return;
1767
1768 break;
1769 default:
1770 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1771 return;
1772 break;
1773 }
1774 e_crit(drv,
1775 "Network adapter has been stopped because it has over heated. "
1776 "Restart the computer. If the problem persists, "
1777 "power off the system and replace the adapter\n");
1778
1779 adapter->interrupt_event = 0;
1780 }
1781
1782 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1783 {
1784 struct ixgbe_hw *hw = &adapter->hw;
1785
1786 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1787 (eicr & IXGBE_EICR_GPI_SDP1)) {
1788 e_crit(probe, "Fan has stopped, replace the adapter\n");
1789 /* write to clear the interrupt */
1790 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1791 }
1792 }
1793
1794 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1795 {
1796 struct ixgbe_hw *hw = &adapter->hw;
1797
1798 if (eicr & IXGBE_EICR_GPI_SDP2) {
1799 /* Clear the interrupt */
1800 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1801 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1802 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1803 ixgbe_service_event_schedule(adapter);
1804 }
1805 }
1806
1807 if (eicr & IXGBE_EICR_GPI_SDP1) {
1808 /* Clear the interrupt */
1809 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1810 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1811 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1812 ixgbe_service_event_schedule(adapter);
1813 }
1814 }
1815 }
1816
1817 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1818 {
1819 struct ixgbe_hw *hw = &adapter->hw;
1820
1821 adapter->lsc_int++;
1822 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1823 adapter->link_check_timeout = jiffies;
1824 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1825 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1826 IXGBE_WRITE_FLUSH(hw);
1827 ixgbe_service_event_schedule(adapter);
1828 }
1829 }
1830
1831 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1832 u64 qmask)
1833 {
1834 u32 mask;
1835 struct ixgbe_hw *hw = &adapter->hw;
1836
1837 switch (hw->mac.type) {
1838 case ixgbe_mac_82598EB:
1839 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1840 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1841 break;
1842 case ixgbe_mac_82599EB:
1843 case ixgbe_mac_X540:
1844 mask = (qmask & 0xFFFFFFFF);
1845 if (mask)
1846 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1847 mask = (qmask >> 32);
1848 if (mask)
1849 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1850 break;
1851 default:
1852 break;
1853 }
1854 /* skip the flush */
1855 }
1856
1857 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1858 u64 qmask)
1859 {
1860 u32 mask;
1861 struct ixgbe_hw *hw = &adapter->hw;
1862
1863 switch (hw->mac.type) {
1864 case ixgbe_mac_82598EB:
1865 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1866 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1867 break;
1868 case ixgbe_mac_82599EB:
1869 case ixgbe_mac_X540:
1870 mask = (qmask & 0xFFFFFFFF);
1871 if (mask)
1872 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1873 mask = (qmask >> 32);
1874 if (mask)
1875 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1876 break;
1877 default:
1878 break;
1879 }
1880 /* skip the flush */
1881 }
1882
1883 /**
1884 * ixgbe_irq_enable - Enable default interrupt generation settings
1885 * @adapter: board private structure
1886 **/
1887 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1888 bool flush)
1889 {
1890 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1891
1892 /* don't reenable LSC while waiting for link */
1893 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1894 mask &= ~IXGBE_EIMS_LSC;
1895
1896 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
1897 mask |= IXGBE_EIMS_GPI_SDP0;
1898 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1899 mask |= IXGBE_EIMS_GPI_SDP1;
1900 switch (adapter->hw.mac.type) {
1901 case ixgbe_mac_82599EB:
1902 case ixgbe_mac_X540:
1903 mask |= IXGBE_EIMS_ECC;
1904 mask |= IXGBE_EIMS_GPI_SDP1;
1905 mask |= IXGBE_EIMS_GPI_SDP2;
1906 mask |= IXGBE_EIMS_MAILBOX;
1907 break;
1908 default:
1909 break;
1910 }
1911 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1912 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1913 mask |= IXGBE_EIMS_FLOW_DIR;
1914
1915 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1916 if (queues)
1917 ixgbe_irq_enable_queues(adapter, ~0);
1918 if (flush)
1919 IXGBE_WRITE_FLUSH(&adapter->hw);
1920 }
1921
1922 static irqreturn_t ixgbe_msix_other(int irq, void *data)
1923 {
1924 struct ixgbe_adapter *adapter = data;
1925 struct ixgbe_hw *hw = &adapter->hw;
1926 u32 eicr;
1927
1928 /*
1929 * Workaround for Silicon errata. Use clear-by-write instead
1930 * of clear-by-read. Reading with EICS will return the
1931 * interrupt causes without clearing, which later be done
1932 * with the write to EICR.
1933 */
1934 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1935 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1936
1937 if (eicr & IXGBE_EICR_LSC)
1938 ixgbe_check_lsc(adapter);
1939
1940 if (eicr & IXGBE_EICR_MAILBOX)
1941 ixgbe_msg_task(adapter);
1942
1943 switch (hw->mac.type) {
1944 case ixgbe_mac_82599EB:
1945 case ixgbe_mac_X540:
1946 if (eicr & IXGBE_EICR_ECC)
1947 e_info(link, "Received unrecoverable ECC Err, please "
1948 "reboot\n");
1949 /* Handle Flow Director Full threshold interrupt */
1950 if (eicr & IXGBE_EICR_FLOW_DIR) {
1951 int reinit_count = 0;
1952 int i;
1953 for (i = 0; i < adapter->num_tx_queues; i++) {
1954 struct ixgbe_ring *ring = adapter->tx_ring[i];
1955 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1956 &ring->state))
1957 reinit_count++;
1958 }
1959 if (reinit_count) {
1960 /* no more flow director interrupts until after init */
1961 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1962 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1963 ixgbe_service_event_schedule(adapter);
1964 }
1965 }
1966 ixgbe_check_sfp_event(adapter, eicr);
1967 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1968 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1969 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1970 adapter->interrupt_event = eicr;
1971 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1972 ixgbe_service_event_schedule(adapter);
1973 }
1974 }
1975 break;
1976 default:
1977 break;
1978 }
1979
1980 ixgbe_check_fan_failure(adapter, eicr);
1981
1982 /* re-enable the original interrupt state, no lsc, no queues */
1983 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1984 ixgbe_irq_enable(adapter, false, false);
1985
1986 return IRQ_HANDLED;
1987 }
1988
1989 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
1990 {
1991 struct ixgbe_q_vector *q_vector = data;
1992
1993 /* EIAM disabled interrupts (on this vector) for us */
1994
1995 if (q_vector->rx.ring || q_vector->tx.ring)
1996 napi_schedule(&q_vector->napi);
1997
1998 return IRQ_HANDLED;
1999 }
2000
2001 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2002 int r_idx)
2003 {
2004 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2005 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2006
2007 rx_ring->q_vector = q_vector;
2008 rx_ring->next = q_vector->rx.ring;
2009 q_vector->rx.ring = rx_ring;
2010 q_vector->rx.count++;
2011 }
2012
2013 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2014 int t_idx)
2015 {
2016 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2017 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2018
2019 tx_ring->q_vector = q_vector;
2020 tx_ring->next = q_vector->tx.ring;
2021 q_vector->tx.ring = tx_ring;
2022 q_vector->tx.count++;
2023 q_vector->tx.work_limit = a->tx_work_limit;
2024 }
2025
2026 /**
2027 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2028 * @adapter: board private structure to initialize
2029 *
2030 * This function maps descriptor rings to the queue-specific vectors
2031 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2032 * one vector per ring/queue, but on a constrained vector budget, we
2033 * group the rings as "efficiently" as possible. You would add new
2034 * mapping configurations in here.
2035 **/
2036 static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2037 {
2038 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2039 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2040 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
2041 int v_start = 0;
2042
2043 /* only one q_vector if MSI-X is disabled. */
2044 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2045 q_vectors = 1;
2046
2047 /*
2048 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2049 * group them so there are multiple queues per vector.
2050 *
2051 * Re-adjusting *qpv takes care of the remainder.
2052 */
2053 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2054 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2055 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
2056 map_vector_to_rxq(adapter, v_start, rxr_idx);
2057 }
2058
2059 /*
2060 * If there are not enough q_vectors for each ring to have it's own
2061 * vector then we must pair up Rx/Tx on a each vector
2062 */
2063 if ((v_start + txr_remaining) > q_vectors)
2064 v_start = 0;
2065
2066 for (; v_start < q_vectors && txr_remaining; v_start++) {
2067 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2068 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2069 map_vector_to_txq(adapter, v_start, txr_idx);
2070 }
2071 }
2072
2073 /**
2074 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2075 * @adapter: board private structure
2076 *
2077 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2078 * interrupts from the kernel.
2079 **/
2080 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2081 {
2082 struct net_device *netdev = adapter->netdev;
2083 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2084 int vector, err;
2085 int ri = 0, ti = 0;
2086
2087 for (vector = 0; vector < q_vectors; vector++) {
2088 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2089 struct msix_entry *entry = &adapter->msix_entries[vector];
2090
2091 if (q_vector->tx.ring && q_vector->rx.ring) {
2092 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2093 "%s-%s-%d", netdev->name, "TxRx", ri++);
2094 ti++;
2095 } else if (q_vector->rx.ring) {
2096 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2097 "%s-%s-%d", netdev->name, "rx", ri++);
2098 } else if (q_vector->tx.ring) {
2099 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2100 "%s-%s-%d", netdev->name, "tx", ti++);
2101 } else {
2102 /* skip this unused q_vector */
2103 continue;
2104 }
2105 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2106 q_vector->name, q_vector);
2107 if (err) {
2108 e_err(probe, "request_irq failed for MSIX interrupt "
2109 "Error: %d\n", err);
2110 goto free_queue_irqs;
2111 }
2112 /* If Flow Director is enabled, set interrupt affinity */
2113 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2114 /* assign the mask for this irq */
2115 irq_set_affinity_hint(entry->vector,
2116 q_vector->affinity_mask);
2117 }
2118 }
2119
2120 err = request_irq(adapter->msix_entries[vector].vector,
2121 ixgbe_msix_other, 0, netdev->name, adapter);
2122 if (err) {
2123 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2124 goto free_queue_irqs;
2125 }
2126
2127 return 0;
2128
2129 free_queue_irqs:
2130 while (vector) {
2131 vector--;
2132 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2133 NULL);
2134 free_irq(adapter->msix_entries[vector].vector,
2135 adapter->q_vector[vector]);
2136 }
2137 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2138 pci_disable_msix(adapter->pdev);
2139 kfree(adapter->msix_entries);
2140 adapter->msix_entries = NULL;
2141 return err;
2142 }
2143
2144 /**
2145 * ixgbe_intr - legacy mode Interrupt Handler
2146 * @irq: interrupt number
2147 * @data: pointer to a network interface device structure
2148 **/
2149 static irqreturn_t ixgbe_intr(int irq, void *data)
2150 {
2151 struct ixgbe_adapter *adapter = data;
2152 struct ixgbe_hw *hw = &adapter->hw;
2153 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2154 u32 eicr;
2155
2156 /*
2157 * Workaround for silicon errata on 82598. Mask the interrupts
2158 * before the read of EICR.
2159 */
2160 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2161
2162 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2163 * therefore no explict interrupt disable is necessary */
2164 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2165 if (!eicr) {
2166 /*
2167 * shared interrupt alert!
2168 * make sure interrupts are enabled because the read will
2169 * have disabled interrupts due to EIAM
2170 * finish the workaround of silicon errata on 82598. Unmask
2171 * the interrupt that we masked before the EICR read.
2172 */
2173 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2174 ixgbe_irq_enable(adapter, true, true);
2175 return IRQ_NONE; /* Not our interrupt */
2176 }
2177
2178 if (eicr & IXGBE_EICR_LSC)
2179 ixgbe_check_lsc(adapter);
2180
2181 switch (hw->mac.type) {
2182 case ixgbe_mac_82599EB:
2183 ixgbe_check_sfp_event(adapter, eicr);
2184 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2185 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2186 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2187 adapter->interrupt_event = eicr;
2188 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2189 ixgbe_service_event_schedule(adapter);
2190 }
2191 }
2192 break;
2193 default:
2194 break;
2195 }
2196
2197 ixgbe_check_fan_failure(adapter, eicr);
2198
2199 if (napi_schedule_prep(&(q_vector->napi))) {
2200 /* would disable interrupts here but EIAM disabled it */
2201 __napi_schedule(&(q_vector->napi));
2202 }
2203
2204 /*
2205 * re-enable link(maybe) and non-queue interrupts, no flush.
2206 * ixgbe_poll will re-enable the queue interrupts
2207 */
2208
2209 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2210 ixgbe_irq_enable(adapter, false, false);
2211
2212 return IRQ_HANDLED;
2213 }
2214
2215 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2216 {
2217 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2218 int i;
2219
2220 /* legacy and MSI only use one vector */
2221 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2222 q_vectors = 1;
2223
2224 for (i = 0; i < adapter->num_rx_queues; i++) {
2225 adapter->rx_ring[i]->q_vector = NULL;
2226 adapter->rx_ring[i]->next = NULL;
2227 }
2228 for (i = 0; i < adapter->num_tx_queues; i++) {
2229 adapter->tx_ring[i]->q_vector = NULL;
2230 adapter->tx_ring[i]->next = NULL;
2231 }
2232
2233 for (i = 0; i < q_vectors; i++) {
2234 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2235 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2236 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
2237 }
2238 }
2239
2240 /**
2241 * ixgbe_request_irq - initialize interrupts
2242 * @adapter: board private structure
2243 *
2244 * Attempts to configure interrupts using the best available
2245 * capabilities of the hardware and kernel.
2246 **/
2247 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2248 {
2249 struct net_device *netdev = adapter->netdev;
2250 int err;
2251
2252 /* map all of the rings to the q_vectors */
2253 ixgbe_map_rings_to_vectors(adapter);
2254
2255 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2256 err = ixgbe_request_msix_irqs(adapter);
2257 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2258 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2259 netdev->name, adapter);
2260 else
2261 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2262 netdev->name, adapter);
2263
2264 if (err) {
2265 e_err(probe, "request_irq failed, Error %d\n", err);
2266
2267 /* place q_vectors and rings back into a known good state */
2268 ixgbe_reset_q_vectors(adapter);
2269 }
2270
2271 return err;
2272 }
2273
2274 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2275 {
2276 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2277 int i, q_vectors;
2278
2279 q_vectors = adapter->num_msix_vectors;
2280 i = q_vectors - 1;
2281 free_irq(adapter->msix_entries[i].vector, adapter);
2282 i--;
2283
2284 for (; i >= 0; i--) {
2285 /* free only the irqs that were actually requested */
2286 if (!adapter->q_vector[i]->rx.ring &&
2287 !adapter->q_vector[i]->tx.ring)
2288 continue;
2289
2290 /* clear the affinity_mask in the IRQ descriptor */
2291 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2292 NULL);
2293
2294 free_irq(adapter->msix_entries[i].vector,
2295 adapter->q_vector[i]);
2296 }
2297 } else {
2298 free_irq(adapter->pdev->irq, adapter);
2299 }
2300
2301 /* clear q_vector state information */
2302 ixgbe_reset_q_vectors(adapter);
2303 }
2304
2305 /**
2306 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2307 * @adapter: board private structure
2308 **/
2309 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2310 {
2311 switch (adapter->hw.mac.type) {
2312 case ixgbe_mac_82598EB:
2313 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2314 break;
2315 case ixgbe_mac_82599EB:
2316 case ixgbe_mac_X540:
2317 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2318 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2319 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2320 break;
2321 default:
2322 break;
2323 }
2324 IXGBE_WRITE_FLUSH(&adapter->hw);
2325 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2326 int i;
2327 for (i = 0; i < adapter->num_msix_vectors; i++)
2328 synchronize_irq(adapter->msix_entries[i].vector);
2329 } else {
2330 synchronize_irq(adapter->pdev->irq);
2331 }
2332 }
2333
2334 /**
2335 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2336 *
2337 **/
2338 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2339 {
2340 struct ixgbe_hw *hw = &adapter->hw;
2341
2342 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2343 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2344
2345 ixgbe_set_ivar(adapter, 0, 0, 0);
2346 ixgbe_set_ivar(adapter, 1, 0, 0);
2347
2348 e_info(hw, "Legacy interrupt IVAR setup done\n");
2349 }
2350
2351 /**
2352 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2353 * @adapter: board private structure
2354 * @ring: structure containing ring specific data
2355 *
2356 * Configure the Tx descriptor ring after a reset.
2357 **/
2358 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2359 struct ixgbe_ring *ring)
2360 {
2361 struct ixgbe_hw *hw = &adapter->hw;
2362 u64 tdba = ring->dma;
2363 int wait_loop = 10;
2364 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2365 u8 reg_idx = ring->reg_idx;
2366
2367 /* disable queue to avoid issues while updating state */
2368 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2369 IXGBE_WRITE_FLUSH(hw);
2370
2371 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2372 (tdba & DMA_BIT_MASK(32)));
2373 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2374 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2375 ring->count * sizeof(union ixgbe_adv_tx_desc));
2376 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2377 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2378 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2379
2380 /*
2381 * set WTHRESH to encourage burst writeback, it should not be set
2382 * higher than 1 when ITR is 0 as it could cause false TX hangs
2383 *
2384 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2385 * to or less than the number of on chip descriptors, which is
2386 * currently 40.
2387 */
2388 if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2389 txdctl |= (1 << 16); /* WTHRESH = 1 */
2390 else
2391 txdctl |= (8 << 16); /* WTHRESH = 8 */
2392
2393 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2394 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2395 32; /* PTHRESH = 32 */
2396
2397 /* reinitialize flowdirector state */
2398 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2399 adapter->atr_sample_rate) {
2400 ring->atr_sample_rate = adapter->atr_sample_rate;
2401 ring->atr_count = 0;
2402 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2403 } else {
2404 ring->atr_sample_rate = 0;
2405 }
2406
2407 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2408
2409 /* enable queue */
2410 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2411
2412 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2413 if (hw->mac.type == ixgbe_mac_82598EB &&
2414 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2415 return;
2416
2417 /* poll to verify queue is enabled */
2418 do {
2419 usleep_range(1000, 2000);
2420 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2421 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2422 if (!wait_loop)
2423 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2424 }
2425
2426 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2427 {
2428 struct ixgbe_hw *hw = &adapter->hw;
2429 u32 rttdcs;
2430 u32 reg;
2431 u8 tcs = netdev_get_num_tc(adapter->netdev);
2432
2433 if (hw->mac.type == ixgbe_mac_82598EB)
2434 return;
2435
2436 /* disable the arbiter while setting MTQC */
2437 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2438 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2439 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2440
2441 /* set transmit pool layout */
2442 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2443 case (IXGBE_FLAG_SRIOV_ENABLED):
2444 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2445 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2446 break;
2447 default:
2448 if (!tcs)
2449 reg = IXGBE_MTQC_64Q_1PB;
2450 else if (tcs <= 4)
2451 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2452 else
2453 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2454
2455 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2456
2457 /* Enable Security TX Buffer IFG for multiple pb */
2458 if (tcs) {
2459 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2460 reg |= IXGBE_SECTX_DCB;
2461 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2462 }
2463 break;
2464 }
2465
2466 /* re-enable the arbiter */
2467 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2468 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2469 }
2470
2471 /**
2472 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2473 * @adapter: board private structure
2474 *
2475 * Configure the Tx unit of the MAC after a reset.
2476 **/
2477 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2478 {
2479 struct ixgbe_hw *hw = &adapter->hw;
2480 u32 dmatxctl;
2481 u32 i;
2482
2483 ixgbe_setup_mtqc(adapter);
2484
2485 if (hw->mac.type != ixgbe_mac_82598EB) {
2486 /* DMATXCTL.EN must be before Tx queues are enabled */
2487 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2488 dmatxctl |= IXGBE_DMATXCTL_TE;
2489 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2490 }
2491
2492 /* Setup the HW Tx Head and Tail descriptor pointers */
2493 for (i = 0; i < adapter->num_tx_queues; i++)
2494 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2495 }
2496
2497 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2498
2499 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2500 struct ixgbe_ring *rx_ring)
2501 {
2502 u32 srrctl;
2503 u8 reg_idx = rx_ring->reg_idx;
2504
2505 switch (adapter->hw.mac.type) {
2506 case ixgbe_mac_82598EB: {
2507 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2508 const int mask = feature[RING_F_RSS].mask;
2509 reg_idx = reg_idx & mask;
2510 }
2511 break;
2512 case ixgbe_mac_82599EB:
2513 case ixgbe_mac_X540:
2514 default:
2515 break;
2516 }
2517
2518 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2519
2520 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2521 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2522 if (adapter->num_vfs)
2523 srrctl |= IXGBE_SRRCTL_DROP_EN;
2524
2525 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2526 IXGBE_SRRCTL_BSIZEHDR_MASK;
2527
2528 if (ring_is_ps_enabled(rx_ring)) {
2529 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2530 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2531 #else
2532 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2533 #endif
2534 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2535 } else {
2536 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2537 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2538 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2539 }
2540
2541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2542 }
2543
2544 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2545 {
2546 struct ixgbe_hw *hw = &adapter->hw;
2547 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2548 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2549 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2550 u32 mrqc = 0, reta = 0;
2551 u32 rxcsum;
2552 int i, j;
2553 u8 tcs = netdev_get_num_tc(adapter->netdev);
2554 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2555
2556 if (tcs)
2557 maxq = min(maxq, adapter->num_tx_queues / tcs);
2558
2559 /* Fill out hash function seeds */
2560 for (i = 0; i < 10; i++)
2561 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2562
2563 /* Fill out redirection table */
2564 for (i = 0, j = 0; i < 128; i++, j++) {
2565 if (j == maxq)
2566 j = 0;
2567 /* reta = 4-byte sliding window of
2568 * 0x00..(indices-1)(indices-1)00..etc. */
2569 reta = (reta << 8) | (j * 0x11);
2570 if ((i & 3) == 3)
2571 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2572 }
2573
2574 /* Disable indicating checksum in descriptor, enables RSS hash */
2575 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2576 rxcsum |= IXGBE_RXCSUM_PCSD;
2577 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2578
2579 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2580 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2581 mrqc = IXGBE_MRQC_RSSEN;
2582 } else {
2583 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2584 | IXGBE_FLAG_SRIOV_ENABLED);
2585
2586 switch (mask) {
2587 case (IXGBE_FLAG_RSS_ENABLED):
2588 if (!tcs)
2589 mrqc = IXGBE_MRQC_RSSEN;
2590 else if (tcs <= 4)
2591 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2592 else
2593 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2594 break;
2595 case (IXGBE_FLAG_SRIOV_ENABLED):
2596 mrqc = IXGBE_MRQC_VMDQEN;
2597 break;
2598 default:
2599 break;
2600 }
2601 }
2602
2603 /* Perform hash on these packet types */
2604 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2605 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2606 | IXGBE_MRQC_RSS_FIELD_IPV6
2607 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2608
2609 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2610 }
2611
2612 /**
2613 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2614 * @adapter: address of board private structure
2615 * @index: index of ring to set
2616 **/
2617 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2618 struct ixgbe_ring *ring)
2619 {
2620 struct ixgbe_hw *hw = &adapter->hw;
2621 u32 rscctrl;
2622 int rx_buf_len;
2623 u8 reg_idx = ring->reg_idx;
2624
2625 if (!ring_is_rsc_enabled(ring))
2626 return;
2627
2628 rx_buf_len = ring->rx_buf_len;
2629 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2630 rscctrl |= IXGBE_RSCCTL_RSCEN;
2631 /*
2632 * we must limit the number of descriptors so that the
2633 * total size of max desc * buf_len is not greater
2634 * than 65535
2635 */
2636 if (ring_is_ps_enabled(ring)) {
2637 #if (MAX_SKB_FRAGS > 16)
2638 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2639 #elif (MAX_SKB_FRAGS > 8)
2640 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2641 #elif (MAX_SKB_FRAGS > 4)
2642 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2643 #else
2644 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2645 #endif
2646 } else {
2647 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2648 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2649 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2650 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2651 else
2652 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2653 }
2654 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2655 }
2656
2657 /**
2658 * ixgbe_set_uta - Set unicast filter table address
2659 * @adapter: board private structure
2660 *
2661 * The unicast table address is a register array of 32-bit registers.
2662 * The table is meant to be used in a way similar to how the MTA is used
2663 * however due to certain limitations in the hardware it is necessary to
2664 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2665 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2666 **/
2667 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2668 {
2669 struct ixgbe_hw *hw = &adapter->hw;
2670 int i;
2671
2672 /* The UTA table only exists on 82599 hardware and newer */
2673 if (hw->mac.type < ixgbe_mac_82599EB)
2674 return;
2675
2676 /* we only need to do this if VMDq is enabled */
2677 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2678 return;
2679
2680 for (i = 0; i < 128; i++)
2681 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2682 }
2683
2684 #define IXGBE_MAX_RX_DESC_POLL 10
2685 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2686 struct ixgbe_ring *ring)
2687 {
2688 struct ixgbe_hw *hw = &adapter->hw;
2689 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2690 u32 rxdctl;
2691 u8 reg_idx = ring->reg_idx;
2692
2693 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2694 if (hw->mac.type == ixgbe_mac_82598EB &&
2695 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2696 return;
2697
2698 do {
2699 usleep_range(1000, 2000);
2700 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2701 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2702
2703 if (!wait_loop) {
2704 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2705 "the polling period\n", reg_idx);
2706 }
2707 }
2708
2709 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2710 struct ixgbe_ring *ring)
2711 {
2712 struct ixgbe_hw *hw = &adapter->hw;
2713 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2714 u32 rxdctl;
2715 u8 reg_idx = ring->reg_idx;
2716
2717 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2718 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2719
2720 /* write value back with RXDCTL.ENABLE bit cleared */
2721 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2722
2723 if (hw->mac.type == ixgbe_mac_82598EB &&
2724 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2725 return;
2726
2727 /* the hardware may take up to 100us to really disable the rx queue */
2728 do {
2729 udelay(10);
2730 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2731 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2732
2733 if (!wait_loop) {
2734 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2735 "the polling period\n", reg_idx);
2736 }
2737 }
2738
2739 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2740 struct ixgbe_ring *ring)
2741 {
2742 struct ixgbe_hw *hw = &adapter->hw;
2743 u64 rdba = ring->dma;
2744 u32 rxdctl;
2745 u8 reg_idx = ring->reg_idx;
2746
2747 /* disable queue to avoid issues while updating state */
2748 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2749 ixgbe_disable_rx_queue(adapter, ring);
2750
2751 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2752 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2753 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2754 ring->count * sizeof(union ixgbe_adv_rx_desc));
2755 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2756 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2757 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2758
2759 ixgbe_configure_srrctl(adapter, ring);
2760 ixgbe_configure_rscctl(adapter, ring);
2761
2762 /* If operating in IOV mode set RLPML for X540 */
2763 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2764 hw->mac.type == ixgbe_mac_X540) {
2765 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2766 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2767 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2768 }
2769
2770 if (hw->mac.type == ixgbe_mac_82598EB) {
2771 /*
2772 * enable cache line friendly hardware writes:
2773 * PTHRESH=32 descriptors (half the internal cache),
2774 * this also removes ugly rx_no_buffer_count increment
2775 * HTHRESH=4 descriptors (to minimize latency on fetch)
2776 * WTHRESH=8 burst writeback up to two cache lines
2777 */
2778 rxdctl &= ~0x3FFFFF;
2779 rxdctl |= 0x080420;
2780 }
2781
2782 /* enable receive descriptor ring */
2783 rxdctl |= IXGBE_RXDCTL_ENABLE;
2784 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2785
2786 ixgbe_rx_desc_queue_enable(adapter, ring);
2787 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
2788 }
2789
2790 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2791 {
2792 struct ixgbe_hw *hw = &adapter->hw;
2793 int p;
2794
2795 /* PSRTYPE must be initialized in non 82598 adapters */
2796 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2797 IXGBE_PSRTYPE_UDPHDR |
2798 IXGBE_PSRTYPE_IPV4HDR |
2799 IXGBE_PSRTYPE_L2HDR |
2800 IXGBE_PSRTYPE_IPV6HDR;
2801
2802 if (hw->mac.type == ixgbe_mac_82598EB)
2803 return;
2804
2805 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2806 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2807
2808 for (p = 0; p < adapter->num_rx_pools; p++)
2809 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2810 psrtype);
2811 }
2812
2813 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2814 {
2815 struct ixgbe_hw *hw = &adapter->hw;
2816 u32 gcr_ext;
2817 u32 vt_reg_bits;
2818 u32 reg_offset, vf_shift;
2819 u32 vmdctl;
2820
2821 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2822 return;
2823
2824 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2825 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2826 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2827 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2828
2829 vf_shift = adapter->num_vfs % 32;
2830 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2831
2832 /* Enable only the PF's pool for Tx/Rx */
2833 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2834 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2835 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2836 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2837 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2838
2839 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2840 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2841
2842 /*
2843 * Set up VF register offsets for selected VT Mode,
2844 * i.e. 32 or 64 VFs for SR-IOV
2845 */
2846 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2847 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2848 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2849 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2850
2851 /* enable Tx loopback for VF/PF communication */
2852 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2853 /* Enable MAC Anti-Spoofing */
2854 hw->mac.ops.set_mac_anti_spoofing(hw,
2855 (adapter->antispoofing_enabled =
2856 (adapter->num_vfs != 0)),
2857 adapter->num_vfs);
2858 }
2859
2860 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2861 {
2862 struct ixgbe_hw *hw = &adapter->hw;
2863 struct net_device *netdev = adapter->netdev;
2864 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2865 int rx_buf_len;
2866 struct ixgbe_ring *rx_ring;
2867 int i;
2868 u32 mhadd, hlreg0;
2869
2870 /* Decide whether to use packet split mode or not */
2871 /* On by default */
2872 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2873
2874 /* Do not use packet split if we're in SR-IOV Mode */
2875 if (adapter->num_vfs)
2876 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2877
2878 /* Disable packet split due to 82599 erratum #45 */
2879 if (hw->mac.type == ixgbe_mac_82599EB)
2880 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2881
2882 /* Set the RX buffer length according to the mode */
2883 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2884 rx_buf_len = IXGBE_RX_HDR_SIZE;
2885 } else {
2886 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2887 (netdev->mtu <= ETH_DATA_LEN))
2888 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2889 else
2890 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2891 }
2892
2893 #ifdef IXGBE_FCOE
2894 /* adjust max frame to be able to do baby jumbo for FCoE */
2895 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2896 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2897 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2898
2899 #endif /* IXGBE_FCOE */
2900 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2901 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2902 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2903 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2904
2905 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2906 }
2907
2908 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2909 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2910 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2911 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2912
2913 /*
2914 * Setup the HW Rx Head and Tail Descriptor Pointers and
2915 * the Base and Length of the Rx Descriptor Ring
2916 */
2917 for (i = 0; i < adapter->num_rx_queues; i++) {
2918 rx_ring = adapter->rx_ring[i];
2919 rx_ring->rx_buf_len = rx_buf_len;
2920
2921 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2922 set_ring_ps_enabled(rx_ring);
2923 else
2924 clear_ring_ps_enabled(rx_ring);
2925
2926 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2927 set_ring_rsc_enabled(rx_ring);
2928 else
2929 clear_ring_rsc_enabled(rx_ring);
2930
2931 #ifdef IXGBE_FCOE
2932 if (netdev->features & NETIF_F_FCOE_MTU) {
2933 struct ixgbe_ring_feature *f;
2934 f = &adapter->ring_feature[RING_F_FCOE];
2935 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2936 clear_ring_ps_enabled(rx_ring);
2937 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2938 rx_ring->rx_buf_len =
2939 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2940 } else if (!ring_is_rsc_enabled(rx_ring) &&
2941 !ring_is_ps_enabled(rx_ring)) {
2942 rx_ring->rx_buf_len =
2943 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2944 }
2945 }
2946 #endif /* IXGBE_FCOE */
2947 }
2948 }
2949
2950 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2951 {
2952 struct ixgbe_hw *hw = &adapter->hw;
2953 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2954
2955 switch (hw->mac.type) {
2956 case ixgbe_mac_82598EB:
2957 /*
2958 * For VMDq support of different descriptor types or
2959 * buffer sizes through the use of multiple SRRCTL
2960 * registers, RDRXCTL.MVMEN must be set to 1
2961 *
2962 * also, the manual doesn't mention it clearly but DCA hints
2963 * will only use queue 0's tags unless this bit is set. Side
2964 * effects of setting this bit are only that SRRCTL must be
2965 * fully programmed [0..15]
2966 */
2967 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2968 break;
2969 case ixgbe_mac_82599EB:
2970 case ixgbe_mac_X540:
2971 /* Disable RSC for ACK packets */
2972 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2973 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2974 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2975 /* hardware requires some bits to be set by default */
2976 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2977 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2978 break;
2979 default:
2980 /* We should do nothing since we don't know this hardware */
2981 return;
2982 }
2983
2984 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2985 }
2986
2987 /**
2988 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2989 * @adapter: board private structure
2990 *
2991 * Configure the Rx unit of the MAC after a reset.
2992 **/
2993 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2994 {
2995 struct ixgbe_hw *hw = &adapter->hw;
2996 int i;
2997 u32 rxctrl;
2998
2999 /* disable receives while setting up the descriptors */
3000 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3001 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3002
3003 ixgbe_setup_psrtype(adapter);
3004 ixgbe_setup_rdrxctl(adapter);
3005
3006 /* Program registers for the distribution of queues */
3007 ixgbe_setup_mrqc(adapter);
3008
3009 ixgbe_set_uta(adapter);
3010
3011 /* set_rx_buffer_len must be called before ring initialization */
3012 ixgbe_set_rx_buffer_len(adapter);
3013
3014 /*
3015 * Setup the HW Rx Head and Tail Descriptor Pointers and
3016 * the Base and Length of the Rx Descriptor Ring
3017 */
3018 for (i = 0; i < adapter->num_rx_queues; i++)
3019 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3020
3021 /* disable drop enable for 82598 parts */
3022 if (hw->mac.type == ixgbe_mac_82598EB)
3023 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3024
3025 /* enable all receives */
3026 rxctrl |= IXGBE_RXCTRL_RXEN;
3027 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3028 }
3029
3030 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3031 {
3032 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3033 struct ixgbe_hw *hw = &adapter->hw;
3034 int pool_ndx = adapter->num_vfs;
3035
3036 /* add VID to filter table */
3037 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3038 set_bit(vid, adapter->active_vlans);
3039 }
3040
3041 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3042 {
3043 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3044 struct ixgbe_hw *hw = &adapter->hw;
3045 int pool_ndx = adapter->num_vfs;
3046
3047 /* remove VID from filter table */
3048 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3049 clear_bit(vid, adapter->active_vlans);
3050 }
3051
3052 /**
3053 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3054 * @adapter: driver data
3055 */
3056 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3057 {
3058 struct ixgbe_hw *hw = &adapter->hw;
3059 u32 vlnctrl;
3060
3061 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3062 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3063 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3064 }
3065
3066 /**
3067 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3068 * @adapter: driver data
3069 */
3070 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3071 {
3072 struct ixgbe_hw *hw = &adapter->hw;
3073 u32 vlnctrl;
3074
3075 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3076 vlnctrl |= IXGBE_VLNCTRL_VFE;
3077 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3078 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3079 }
3080
3081 /**
3082 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3083 * @adapter: driver data
3084 */
3085 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3086 {
3087 struct ixgbe_hw *hw = &adapter->hw;
3088 u32 vlnctrl;
3089 int i, j;
3090
3091 switch (hw->mac.type) {
3092 case ixgbe_mac_82598EB:
3093 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3094 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3095 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3096 break;
3097 case ixgbe_mac_82599EB:
3098 case ixgbe_mac_X540:
3099 for (i = 0; i < adapter->num_rx_queues; i++) {
3100 j = adapter->rx_ring[i]->reg_idx;
3101 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3102 vlnctrl &= ~IXGBE_RXDCTL_VME;
3103 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3104 }
3105 break;
3106 default:
3107 break;
3108 }
3109 }
3110
3111 /**
3112 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3113 * @adapter: driver data
3114 */
3115 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3116 {
3117 struct ixgbe_hw *hw = &adapter->hw;
3118 u32 vlnctrl;
3119 int i, j;
3120
3121 switch (hw->mac.type) {
3122 case ixgbe_mac_82598EB:
3123 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3124 vlnctrl |= IXGBE_VLNCTRL_VME;
3125 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3126 break;
3127 case ixgbe_mac_82599EB:
3128 case ixgbe_mac_X540:
3129 for (i = 0; i < adapter->num_rx_queues; i++) {
3130 j = adapter->rx_ring[i]->reg_idx;
3131 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3132 vlnctrl |= IXGBE_RXDCTL_VME;
3133 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3134 }
3135 break;
3136 default:
3137 break;
3138 }
3139 }
3140
3141 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3142 {
3143 u16 vid;
3144
3145 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3146
3147 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3148 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3149 }
3150
3151 /**
3152 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3153 * @netdev: network interface device structure
3154 *
3155 * Writes unicast address list to the RAR table.
3156 * Returns: -ENOMEM on failure/insufficient address space
3157 * 0 on no addresses written
3158 * X on writing X addresses to the RAR table
3159 **/
3160 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3161 {
3162 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3163 struct ixgbe_hw *hw = &adapter->hw;
3164 unsigned int vfn = adapter->num_vfs;
3165 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3166 int count = 0;
3167
3168 /* return ENOMEM indicating insufficient memory for addresses */
3169 if (netdev_uc_count(netdev) > rar_entries)
3170 return -ENOMEM;
3171
3172 if (!netdev_uc_empty(netdev) && rar_entries) {
3173 struct netdev_hw_addr *ha;
3174 /* return error if we do not support writing to RAR table */
3175 if (!hw->mac.ops.set_rar)
3176 return -ENOMEM;
3177
3178 netdev_for_each_uc_addr(ha, netdev) {
3179 if (!rar_entries)
3180 break;
3181 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3182 vfn, IXGBE_RAH_AV);
3183 count++;
3184 }
3185 }
3186 /* write the addresses in reverse order to avoid write combining */
3187 for (; rar_entries > 0 ; rar_entries--)
3188 hw->mac.ops.clear_rar(hw, rar_entries);
3189
3190 return count;
3191 }
3192
3193 /**
3194 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3195 * @netdev: network interface device structure
3196 *
3197 * The set_rx_method entry point is called whenever the unicast/multicast
3198 * address list or the network interface flags are updated. This routine is
3199 * responsible for configuring the hardware for proper unicast, multicast and
3200 * promiscuous mode.
3201 **/
3202 void ixgbe_set_rx_mode(struct net_device *netdev)
3203 {
3204 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3205 struct ixgbe_hw *hw = &adapter->hw;
3206 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3207 int count;
3208
3209 /* Check for Promiscuous and All Multicast modes */
3210
3211 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3212
3213 /* set all bits that we expect to always be set */
3214 fctrl |= IXGBE_FCTRL_BAM;
3215 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3216 fctrl |= IXGBE_FCTRL_PMCF;
3217
3218 /* clear the bits we are changing the status of */
3219 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3220
3221 if (netdev->flags & IFF_PROMISC) {
3222 hw->addr_ctrl.user_set_promisc = true;
3223 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3224 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3225 /* don't hardware filter vlans in promisc mode */
3226 ixgbe_vlan_filter_disable(adapter);
3227 } else {
3228 if (netdev->flags & IFF_ALLMULTI) {
3229 fctrl |= IXGBE_FCTRL_MPE;
3230 vmolr |= IXGBE_VMOLR_MPE;
3231 } else {
3232 /*
3233 * Write addresses to the MTA, if the attempt fails
3234 * then we should just turn on promiscuous mode so
3235 * that we can at least receive multicast traffic
3236 */
3237 hw->mac.ops.update_mc_addr_list(hw, netdev);
3238 vmolr |= IXGBE_VMOLR_ROMPE;
3239 }
3240 ixgbe_vlan_filter_enable(adapter);
3241 hw->addr_ctrl.user_set_promisc = false;
3242 /*
3243 * Write addresses to available RAR registers, if there is not
3244 * sufficient space to store all the addresses then enable
3245 * unicast promiscuous mode
3246 */
3247 count = ixgbe_write_uc_addr_list(netdev);
3248 if (count < 0) {
3249 fctrl |= IXGBE_FCTRL_UPE;
3250 vmolr |= IXGBE_VMOLR_ROPE;
3251 }
3252 }
3253
3254 if (adapter->num_vfs) {
3255 ixgbe_restore_vf_multicasts(adapter);
3256 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3257 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3258 IXGBE_VMOLR_ROPE);
3259 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3260 }
3261
3262 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3263
3264 if (netdev->features & NETIF_F_HW_VLAN_RX)
3265 ixgbe_vlan_strip_enable(adapter);
3266 else
3267 ixgbe_vlan_strip_disable(adapter);
3268 }
3269
3270 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3271 {
3272 int q_idx;
3273 struct ixgbe_q_vector *q_vector;
3274 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3275
3276 /* legacy and MSI only use one vector */
3277 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3278 q_vectors = 1;
3279
3280 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3281 q_vector = adapter->q_vector[q_idx];
3282 napi_enable(&q_vector->napi);
3283 }
3284 }
3285
3286 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3287 {
3288 int q_idx;
3289 struct ixgbe_q_vector *q_vector;
3290 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3291
3292 /* legacy and MSI only use one vector */
3293 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3294 q_vectors = 1;
3295
3296 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3297 q_vector = adapter->q_vector[q_idx];
3298 napi_disable(&q_vector->napi);
3299 }
3300 }
3301
3302 #ifdef CONFIG_IXGBE_DCB
3303 /*
3304 * ixgbe_configure_dcb - Configure DCB hardware
3305 * @adapter: ixgbe adapter struct
3306 *
3307 * This is called by the driver on open to configure the DCB hardware.
3308 * This is also called by the gennetlink interface when reconfiguring
3309 * the DCB state.
3310 */
3311 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3312 {
3313 struct ixgbe_hw *hw = &adapter->hw;
3314 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3315
3316 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3317 if (hw->mac.type == ixgbe_mac_82598EB)
3318 netif_set_gso_max_size(adapter->netdev, 65536);
3319 return;
3320 }
3321
3322 if (hw->mac.type == ixgbe_mac_82598EB)
3323 netif_set_gso_max_size(adapter->netdev, 32768);
3324
3325
3326 /* Enable VLAN tag insert/strip */
3327 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3328
3329 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3330
3331 /* reconfigure the hardware */
3332 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3333 #ifdef IXGBE_FCOE
3334 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3335 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3336 #endif
3337 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3338 DCB_TX_CONFIG);
3339 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3340 DCB_RX_CONFIG);
3341 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3342 } else {
3343 struct net_device *dev = adapter->netdev;
3344
3345 if (adapter->ixgbe_ieee_ets)
3346 dev->dcbnl_ops->ieee_setets(dev,
3347 adapter->ixgbe_ieee_ets);
3348 if (adapter->ixgbe_ieee_pfc)
3349 dev->dcbnl_ops->ieee_setpfc(dev,
3350 adapter->ixgbe_ieee_pfc);
3351 }
3352
3353 /* Enable RSS Hash per TC */
3354 if (hw->mac.type != ixgbe_mac_82598EB) {
3355 int i;
3356 u32 reg = 0;
3357
3358 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3359 u8 msb = 0;
3360 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3361
3362 while (cnt >>= 1)
3363 msb++;
3364
3365 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3366 }
3367 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3368 }
3369 }
3370
3371 #endif
3372
3373 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3374 {
3375 struct ixgbe_hw *hw = &adapter->hw;
3376 int hdrm;
3377 u8 tc = netdev_get_num_tc(adapter->netdev);
3378
3379 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3380 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3381 hdrm = 32 << adapter->fdir_pballoc;
3382 else
3383 hdrm = 0;
3384
3385 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3386 }
3387
3388 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3389 {
3390 struct ixgbe_hw *hw = &adapter->hw;
3391 struct hlist_node *node, *node2;
3392 struct ixgbe_fdir_filter *filter;
3393
3394 spin_lock(&adapter->fdir_perfect_lock);
3395
3396 if (!hlist_empty(&adapter->fdir_filter_list))
3397 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3398
3399 hlist_for_each_entry_safe(filter, node, node2,
3400 &adapter->fdir_filter_list, fdir_node) {
3401 ixgbe_fdir_write_perfect_filter_82599(hw,
3402 &filter->filter,
3403 filter->sw_idx,
3404 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3405 IXGBE_FDIR_DROP_QUEUE :
3406 adapter->rx_ring[filter->action]->reg_idx);
3407 }
3408
3409 spin_unlock(&adapter->fdir_perfect_lock);
3410 }
3411
3412 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3413 {
3414 ixgbe_configure_pb(adapter);
3415 #ifdef CONFIG_IXGBE_DCB
3416 ixgbe_configure_dcb(adapter);
3417 #endif
3418
3419 ixgbe_set_rx_mode(adapter->netdev);
3420 ixgbe_restore_vlan(adapter);
3421
3422 #ifdef IXGBE_FCOE
3423 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3424 ixgbe_configure_fcoe(adapter);
3425
3426 #endif /* IXGBE_FCOE */
3427 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3428 ixgbe_init_fdir_signature_82599(&adapter->hw,
3429 adapter->fdir_pballoc);
3430 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3431 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3432 adapter->fdir_pballoc);
3433 ixgbe_fdir_filter_restore(adapter);
3434 }
3435
3436 ixgbe_configure_virtualization(adapter);
3437
3438 ixgbe_configure_tx(adapter);
3439 ixgbe_configure_rx(adapter);
3440 }
3441
3442 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3443 {
3444 switch (hw->phy.type) {
3445 case ixgbe_phy_sfp_avago:
3446 case ixgbe_phy_sfp_ftl:
3447 case ixgbe_phy_sfp_intel:
3448 case ixgbe_phy_sfp_unknown:
3449 case ixgbe_phy_sfp_passive_tyco:
3450 case ixgbe_phy_sfp_passive_unknown:
3451 case ixgbe_phy_sfp_active_unknown:
3452 case ixgbe_phy_sfp_ftl_active:
3453 return true;
3454 default:
3455 return false;
3456 }
3457 }
3458
3459 /**
3460 * ixgbe_sfp_link_config - set up SFP+ link
3461 * @adapter: pointer to private adapter struct
3462 **/
3463 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3464 {
3465 /*
3466 * We are assuming the worst case scenerio here, and that
3467 * is that an SFP was inserted/removed after the reset
3468 * but before SFP detection was enabled. As such the best
3469 * solution is to just start searching as soon as we start
3470 */
3471 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3472 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3473
3474 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3475 }
3476
3477 /**
3478 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3479 * @hw: pointer to private hardware struct
3480 *
3481 * Returns 0 on success, negative on failure
3482 **/
3483 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3484 {
3485 u32 autoneg;
3486 bool negotiation, link_up = false;
3487 u32 ret = IXGBE_ERR_LINK_SETUP;
3488
3489 if (hw->mac.ops.check_link)
3490 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3491
3492 if (ret)
3493 goto link_cfg_out;
3494
3495 autoneg = hw->phy.autoneg_advertised;
3496 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3497 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3498 &negotiation);
3499 if (ret)
3500 goto link_cfg_out;
3501
3502 if (hw->mac.ops.setup_link)
3503 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3504 link_cfg_out:
3505 return ret;
3506 }
3507
3508 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3509 {
3510 struct ixgbe_hw *hw = &adapter->hw;
3511 u32 gpie = 0;
3512
3513 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3514 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3515 IXGBE_GPIE_OCD;
3516 gpie |= IXGBE_GPIE_EIAME;
3517 /*
3518 * use EIAM to auto-mask when MSI-X interrupt is asserted
3519 * this saves a register write for every interrupt
3520 */
3521 switch (hw->mac.type) {
3522 case ixgbe_mac_82598EB:
3523 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3524 break;
3525 case ixgbe_mac_82599EB:
3526 case ixgbe_mac_X540:
3527 default:
3528 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3529 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3530 break;
3531 }
3532 } else {
3533 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3534 * specifically only auto mask tx and rx interrupts */
3535 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3536 }
3537
3538 /* XXX: to interrupt immediately for EICS writes, enable this */
3539 /* gpie |= IXGBE_GPIE_EIMEN; */
3540
3541 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3542 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3543 gpie |= IXGBE_GPIE_VTMODE_64;
3544 }
3545
3546 /* Enable fan failure interrupt */
3547 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3548 gpie |= IXGBE_SDP1_GPIEN;
3549
3550 if (hw->mac.type == ixgbe_mac_82599EB) {
3551 gpie |= IXGBE_SDP1_GPIEN;
3552 gpie |= IXGBE_SDP2_GPIEN;
3553 }
3554
3555 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3556 }
3557
3558 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3559 {
3560 struct ixgbe_hw *hw = &adapter->hw;
3561 int err;
3562 u32 ctrl_ext;
3563
3564 ixgbe_get_hw_control(adapter);
3565 ixgbe_setup_gpie(adapter);
3566
3567 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3568 ixgbe_configure_msix(adapter);
3569 else
3570 ixgbe_configure_msi_and_legacy(adapter);
3571
3572 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3573 if (hw->mac.ops.enable_tx_laser &&
3574 ((hw->phy.multispeed_fiber) ||
3575 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3576 (hw->mac.type == ixgbe_mac_82599EB))))
3577 hw->mac.ops.enable_tx_laser(hw);
3578
3579 clear_bit(__IXGBE_DOWN, &adapter->state);
3580 ixgbe_napi_enable_all(adapter);
3581
3582 if (ixgbe_is_sfp(hw)) {
3583 ixgbe_sfp_link_config(adapter);
3584 } else {
3585 err = ixgbe_non_sfp_link_config(hw);
3586 if (err)
3587 e_err(probe, "link_config FAILED %d\n", err);
3588 }
3589
3590 /* clear any pending interrupts, may auto mask */
3591 IXGBE_READ_REG(hw, IXGBE_EICR);
3592 ixgbe_irq_enable(adapter, true, true);
3593
3594 /*
3595 * If this adapter has a fan, check to see if we had a failure
3596 * before we enabled the interrupt.
3597 */
3598 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3599 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3600 if (esdp & IXGBE_ESDP_SDP1)
3601 e_crit(drv, "Fan has stopped, replace the adapter\n");
3602 }
3603
3604 /* enable transmits */
3605 netif_tx_start_all_queues(adapter->netdev);
3606
3607 /* bring the link up in the watchdog, this could race with our first
3608 * link up interrupt but shouldn't be a problem */
3609 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3610 adapter->link_check_timeout = jiffies;
3611 mod_timer(&adapter->service_timer, jiffies);
3612
3613 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3614 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3615 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3616 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3617
3618 return 0;
3619 }
3620
3621 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3622 {
3623 WARN_ON(in_interrupt());
3624 /* put off any impending NetWatchDogTimeout */
3625 adapter->netdev->trans_start = jiffies;
3626
3627 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3628 usleep_range(1000, 2000);
3629 ixgbe_down(adapter);
3630 /*
3631 * If SR-IOV enabled then wait a bit before bringing the adapter
3632 * back up to give the VFs time to respond to the reset. The
3633 * two second wait is based upon the watchdog timer cycle in
3634 * the VF driver.
3635 */
3636 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3637 msleep(2000);
3638 ixgbe_up(adapter);
3639 clear_bit(__IXGBE_RESETTING, &adapter->state);
3640 }
3641
3642 int ixgbe_up(struct ixgbe_adapter *adapter)
3643 {
3644 /* hardware has been reset, we need to reload some things */
3645 ixgbe_configure(adapter);
3646
3647 return ixgbe_up_complete(adapter);
3648 }
3649
3650 void ixgbe_reset(struct ixgbe_adapter *adapter)
3651 {
3652 struct ixgbe_hw *hw = &adapter->hw;
3653 int err;
3654
3655 /* lock SFP init bit to prevent race conditions with the watchdog */
3656 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3657 usleep_range(1000, 2000);
3658
3659 /* clear all SFP and link config related flags while holding SFP_INIT */
3660 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3661 IXGBE_FLAG2_SFP_NEEDS_RESET);
3662 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3663
3664 err = hw->mac.ops.init_hw(hw);
3665 switch (err) {
3666 case 0:
3667 case IXGBE_ERR_SFP_NOT_PRESENT:
3668 case IXGBE_ERR_SFP_NOT_SUPPORTED:
3669 break;
3670 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3671 e_dev_err("master disable timed out\n");
3672 break;
3673 case IXGBE_ERR_EEPROM_VERSION:
3674 /* We are running on a pre-production device, log a warning */
3675 e_dev_warn("This device is a pre-production adapter/LOM. "
3676 "Please be aware there may be issuesassociated with "
3677 "your hardware. If you are experiencing problems "
3678 "please contact your Intel or hardware "
3679 "representative who provided you with this "
3680 "hardware.\n");
3681 break;
3682 default:
3683 e_dev_err("Hardware Error: %d\n", err);
3684 }
3685
3686 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3687
3688 /* reprogram the RAR[0] in case user changed it. */
3689 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3690 IXGBE_RAH_AV);
3691 }
3692
3693 /**
3694 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3695 * @rx_ring: ring to free buffers from
3696 **/
3697 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3698 {
3699 struct device *dev = rx_ring->dev;
3700 unsigned long size;
3701 u16 i;
3702
3703 /* ring already cleared, nothing to do */
3704 if (!rx_ring->rx_buffer_info)
3705 return;
3706
3707 /* Free all the Rx ring sk_buffs */
3708 for (i = 0; i < rx_ring->count; i++) {
3709 struct ixgbe_rx_buffer *rx_buffer_info;
3710
3711 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3712 if (rx_buffer_info->dma) {
3713 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3714 rx_ring->rx_buf_len,
3715 DMA_FROM_DEVICE);
3716 rx_buffer_info->dma = 0;
3717 }
3718 if (rx_buffer_info->skb) {
3719 struct sk_buff *skb = rx_buffer_info->skb;
3720 rx_buffer_info->skb = NULL;
3721 do {
3722 struct sk_buff *this = skb;
3723 if (IXGBE_RSC_CB(this)->delay_unmap) {
3724 dma_unmap_single(dev,
3725 IXGBE_RSC_CB(this)->dma,
3726 rx_ring->rx_buf_len,
3727 DMA_FROM_DEVICE);
3728 IXGBE_RSC_CB(this)->dma = 0;
3729 IXGBE_RSC_CB(skb)->delay_unmap = false;
3730 }
3731 skb = skb->prev;
3732 dev_kfree_skb(this);
3733 } while (skb);
3734 }
3735 if (!rx_buffer_info->page)
3736 continue;
3737 if (rx_buffer_info->page_dma) {
3738 dma_unmap_page(dev, rx_buffer_info->page_dma,
3739 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3740 rx_buffer_info->page_dma = 0;
3741 }
3742 put_page(rx_buffer_info->page);
3743 rx_buffer_info->page = NULL;
3744 rx_buffer_info->page_offset = 0;
3745 }
3746
3747 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3748 memset(rx_ring->rx_buffer_info, 0, size);
3749
3750 /* Zero out the descriptor ring */
3751 memset(rx_ring->desc, 0, rx_ring->size);
3752
3753 rx_ring->next_to_clean = 0;
3754 rx_ring->next_to_use = 0;
3755 }
3756
3757 /**
3758 * ixgbe_clean_tx_ring - Free Tx Buffers
3759 * @tx_ring: ring to be cleaned
3760 **/
3761 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3762 {
3763 struct ixgbe_tx_buffer *tx_buffer_info;
3764 unsigned long size;
3765 u16 i;
3766
3767 /* ring already cleared, nothing to do */
3768 if (!tx_ring->tx_buffer_info)
3769 return;
3770
3771 /* Free all the Tx ring sk_buffs */
3772 for (i = 0; i < tx_ring->count; i++) {
3773 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3774 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3775 }
3776
3777 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3778 memset(tx_ring->tx_buffer_info, 0, size);
3779
3780 /* Zero out the descriptor ring */
3781 memset(tx_ring->desc, 0, tx_ring->size);
3782
3783 tx_ring->next_to_use = 0;
3784 tx_ring->next_to_clean = 0;
3785 }
3786
3787 /**
3788 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3789 * @adapter: board private structure
3790 **/
3791 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3792 {
3793 int i;
3794
3795 for (i = 0; i < adapter->num_rx_queues; i++)
3796 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3797 }
3798
3799 /**
3800 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3801 * @adapter: board private structure
3802 **/
3803 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3804 {
3805 int i;
3806
3807 for (i = 0; i < adapter->num_tx_queues; i++)
3808 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3809 }
3810
3811 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3812 {
3813 struct hlist_node *node, *node2;
3814 struct ixgbe_fdir_filter *filter;
3815
3816 spin_lock(&adapter->fdir_perfect_lock);
3817
3818 hlist_for_each_entry_safe(filter, node, node2,
3819 &adapter->fdir_filter_list, fdir_node) {
3820 hlist_del(&filter->fdir_node);
3821 kfree(filter);
3822 }
3823 adapter->fdir_filter_count = 0;
3824
3825 spin_unlock(&adapter->fdir_perfect_lock);
3826 }
3827
3828 void ixgbe_down(struct ixgbe_adapter *adapter)
3829 {
3830 struct net_device *netdev = adapter->netdev;
3831 struct ixgbe_hw *hw = &adapter->hw;
3832 u32 rxctrl;
3833 int i;
3834
3835 /* signal that we are down to the interrupt handler */
3836 set_bit(__IXGBE_DOWN, &adapter->state);
3837
3838 /* disable receives */
3839 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3840 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3841
3842 /* disable all enabled rx queues */
3843 for (i = 0; i < adapter->num_rx_queues; i++)
3844 /* this call also flushes the previous write */
3845 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
3846
3847 usleep_range(10000, 20000);
3848
3849 netif_tx_stop_all_queues(netdev);
3850
3851 /* call carrier off first to avoid false dev_watchdog timeouts */
3852 netif_carrier_off(netdev);
3853 netif_tx_disable(netdev);
3854
3855 ixgbe_irq_disable(adapter);
3856
3857 ixgbe_napi_disable_all(adapter);
3858
3859 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
3860 IXGBE_FLAG2_RESET_REQUESTED);
3861 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3862
3863 del_timer_sync(&adapter->service_timer);
3864
3865 if (adapter->num_vfs) {
3866 /* Clear EITR Select mapping */
3867 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
3868
3869 /* Mark all the VFs as inactive */
3870 for (i = 0 ; i < adapter->num_vfs; i++)
3871 adapter->vfinfo[i].clear_to_send = 0;
3872
3873 /* ping all the active vfs to let them know we are going down */
3874 ixgbe_ping_all_vfs(adapter);
3875
3876 /* Disable all VFTE/VFRE TX/RX */
3877 ixgbe_disable_tx_rx(adapter);
3878 }
3879
3880 /* disable transmits in the hardware now that interrupts are off */
3881 for (i = 0; i < adapter->num_tx_queues; i++) {
3882 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
3883 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
3884 }
3885
3886 /* Disable the Tx DMA engine on 82599 and X540 */
3887 switch (hw->mac.type) {
3888 case ixgbe_mac_82599EB:
3889 case ixgbe_mac_X540:
3890 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3891 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3892 ~IXGBE_DMATXCTL_TE));
3893 break;
3894 default:
3895 break;
3896 }
3897
3898 if (!pci_channel_offline(adapter->pdev))
3899 ixgbe_reset(adapter);
3900
3901 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
3902 if (hw->mac.ops.disable_tx_laser &&
3903 ((hw->phy.multispeed_fiber) ||
3904 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3905 (hw->mac.type == ixgbe_mac_82599EB))))
3906 hw->mac.ops.disable_tx_laser(hw);
3907
3908 ixgbe_clean_all_tx_rings(adapter);
3909 ixgbe_clean_all_rx_rings(adapter);
3910
3911 #ifdef CONFIG_IXGBE_DCA
3912 /* since we reset the hardware DCA settings were cleared */
3913 ixgbe_setup_dca(adapter);
3914 #endif
3915 }
3916
3917 /**
3918 * ixgbe_poll - NAPI Rx polling callback
3919 * @napi: structure for representing this polling device
3920 * @budget: how many packets driver is allowed to clean
3921 *
3922 * This function is used for legacy and MSI, NAPI mode
3923 **/
3924 static int ixgbe_poll(struct napi_struct *napi, int budget)
3925 {
3926 struct ixgbe_q_vector *q_vector =
3927 container_of(napi, struct ixgbe_q_vector, napi);
3928 struct ixgbe_adapter *adapter = q_vector->adapter;
3929 struct ixgbe_ring *ring;
3930 int per_ring_budget;
3931 bool clean_complete = true;
3932
3933 #ifdef CONFIG_IXGBE_DCA
3934 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3935 ixgbe_update_dca(q_vector);
3936 #endif
3937
3938 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
3939 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
3940
3941 /* attempt to distribute budget to each queue fairly, but don't allow
3942 * the budget to go below 1 because we'll exit polling */
3943 if (q_vector->rx.count > 1)
3944 per_ring_budget = max(budget/q_vector->rx.count, 1);
3945 else
3946 per_ring_budget = budget;
3947
3948 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
3949 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
3950 per_ring_budget);
3951
3952 /* If all work not completed, return budget and keep polling */
3953 if (!clean_complete)
3954 return budget;
3955
3956 /* all work done, exit the polling mode */
3957 napi_complete(napi);
3958 if (adapter->rx_itr_setting & 1)
3959 ixgbe_set_itr(q_vector);
3960 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3961 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
3962
3963 return 0;
3964 }
3965
3966 /**
3967 * ixgbe_tx_timeout - Respond to a Tx Hang
3968 * @netdev: network interface device structure
3969 **/
3970 static void ixgbe_tx_timeout(struct net_device *netdev)
3971 {
3972 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3973
3974 /* Do the reset outside of interrupt context */
3975 ixgbe_tx_timeout_reset(adapter);
3976 }
3977
3978 /**
3979 * ixgbe_set_rss_queues: Allocate queues for RSS
3980 * @adapter: board private structure to initialize
3981 *
3982 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3983 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3984 *
3985 **/
3986 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3987 {
3988 bool ret = false;
3989 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3990
3991 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3992 f->mask = 0xF;
3993 adapter->num_rx_queues = f->indices;
3994 adapter->num_tx_queues = f->indices;
3995 ret = true;
3996 } else {
3997 ret = false;
3998 }
3999
4000 return ret;
4001 }
4002
4003 /**
4004 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4005 * @adapter: board private structure to initialize
4006 *
4007 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4008 * to the original CPU that initiated the Tx session. This runs in addition
4009 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4010 * Rx load across CPUs using RSS.
4011 *
4012 **/
4013 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4014 {
4015 bool ret = false;
4016 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4017
4018 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4019 f_fdir->mask = 0;
4020
4021 /* Flow Director must have RSS enabled */
4022 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4023 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4024 adapter->num_tx_queues = f_fdir->indices;
4025 adapter->num_rx_queues = f_fdir->indices;
4026 ret = true;
4027 } else {
4028 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4029 }
4030 return ret;
4031 }
4032
4033 #ifdef IXGBE_FCOE
4034 /**
4035 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4036 * @adapter: board private structure to initialize
4037 *
4038 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4039 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4040 * rx queues out of the max number of rx queues, instead, it is used as the
4041 * index of the first rx queue used by FCoE.
4042 *
4043 **/
4044 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4045 {
4046 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4047
4048 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4049 return false;
4050
4051 f->indices = min((int)num_online_cpus(), f->indices);
4052
4053 adapter->num_rx_queues = 1;
4054 adapter->num_tx_queues = 1;
4055
4056 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4057 e_info(probe, "FCoE enabled with RSS\n");
4058 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4059 ixgbe_set_fdir_queues(adapter);
4060 else
4061 ixgbe_set_rss_queues(adapter);
4062 }
4063
4064 /* adding FCoE rx rings to the end */
4065 f->mask = adapter->num_rx_queues;
4066 adapter->num_rx_queues += f->indices;
4067 adapter->num_tx_queues += f->indices;
4068
4069 return true;
4070 }
4071 #endif /* IXGBE_FCOE */
4072
4073 /* Artificial max queue cap per traffic class in DCB mode */
4074 #define DCB_QUEUE_CAP 8
4075
4076 #ifdef CONFIG_IXGBE_DCB
4077 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4078 {
4079 int per_tc_q, q, i, offset = 0;
4080 struct net_device *dev = adapter->netdev;
4081 int tcs = netdev_get_num_tc(dev);
4082
4083 if (!tcs)
4084 return false;
4085
4086 /* Map queue offset and counts onto allocated tx queues */
4087 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4088 q = min((int)num_online_cpus(), per_tc_q);
4089
4090 for (i = 0; i < tcs; i++) {
4091 netdev_set_prio_tc_map(dev, i, i);
4092 netdev_set_tc_queue(dev, i, q, offset);
4093 offset += q;
4094 }
4095
4096 adapter->num_tx_queues = q * tcs;
4097 adapter->num_rx_queues = q * tcs;
4098
4099 #ifdef IXGBE_FCOE
4100 /* FCoE enabled queues require special configuration indexed
4101 * by feature specific indices and mask. Here we map FCoE
4102 * indices onto the DCB queue pairs allowing FCoE to own
4103 * configuration later.
4104 */
4105 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4106 int tc;
4107 struct ixgbe_ring_feature *f =
4108 &adapter->ring_feature[RING_F_FCOE];
4109
4110 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4111 f->indices = dev->tc_to_txq[tc].count;
4112 f->mask = dev->tc_to_txq[tc].offset;
4113 }
4114 #endif
4115
4116 return true;
4117 }
4118 #endif
4119
4120 /**
4121 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4122 * @adapter: board private structure to initialize
4123 *
4124 * IOV doesn't actually use anything, so just NAK the
4125 * request for now and let the other queue routines
4126 * figure out what to do.
4127 */
4128 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4129 {
4130 return false;
4131 }
4132
4133 /*
4134 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4135 * @adapter: board private structure to initialize
4136 *
4137 * This is the top level queue allocation routine. The order here is very
4138 * important, starting with the "most" number of features turned on at once,
4139 * and ending with the smallest set of features. This way large combinations
4140 * can be allocated if they're turned on, and smaller combinations are the
4141 * fallthrough conditions.
4142 *
4143 **/
4144 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4145 {
4146 /* Start with base case */
4147 adapter->num_rx_queues = 1;
4148 adapter->num_tx_queues = 1;
4149 adapter->num_rx_pools = adapter->num_rx_queues;
4150 adapter->num_rx_queues_per_pool = 1;
4151
4152 if (ixgbe_set_sriov_queues(adapter))
4153 goto done;
4154
4155 #ifdef CONFIG_IXGBE_DCB
4156 if (ixgbe_set_dcb_queues(adapter))
4157 goto done;
4158
4159 #endif
4160 #ifdef IXGBE_FCOE
4161 if (ixgbe_set_fcoe_queues(adapter))
4162 goto done;
4163
4164 #endif /* IXGBE_FCOE */
4165 if (ixgbe_set_fdir_queues(adapter))
4166 goto done;
4167
4168 if (ixgbe_set_rss_queues(adapter))
4169 goto done;
4170
4171 /* fallback to base case */
4172 adapter->num_rx_queues = 1;
4173 adapter->num_tx_queues = 1;
4174
4175 done:
4176 /* Notify the stack of the (possibly) reduced queue counts. */
4177 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4178 return netif_set_real_num_rx_queues(adapter->netdev,
4179 adapter->num_rx_queues);
4180 }
4181
4182 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4183 int vectors)
4184 {
4185 int err, vector_threshold;
4186
4187 /* We'll want at least 3 (vector_threshold):
4188 * 1) TxQ[0] Cleanup
4189 * 2) RxQ[0] Cleanup
4190 * 3) Other (Link Status Change, etc.)
4191 * 4) TCP Timer (optional)
4192 */
4193 vector_threshold = MIN_MSIX_COUNT;
4194
4195 /* The more we get, the more we will assign to Tx/Rx Cleanup
4196 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4197 * Right now, we simply care about how many we'll get; we'll
4198 * set them up later while requesting irq's.
4199 */
4200 while (vectors >= vector_threshold) {
4201 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4202 vectors);
4203 if (!err) /* Success in acquiring all requested vectors. */
4204 break;
4205 else if (err < 0)
4206 vectors = 0; /* Nasty failure, quit now */
4207 else /* err == number of vectors we should try again with */
4208 vectors = err;
4209 }
4210
4211 if (vectors < vector_threshold) {
4212 /* Can't allocate enough MSI-X interrupts? Oh well.
4213 * This just means we'll go with either a single MSI
4214 * vector or fall back to legacy interrupts.
4215 */
4216 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4217 "Unable to allocate MSI-X interrupts\n");
4218 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4219 kfree(adapter->msix_entries);
4220 adapter->msix_entries = NULL;
4221 } else {
4222 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4223 /*
4224 * Adjust for only the vectors we'll use, which is minimum
4225 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4226 * vectors we were allocated.
4227 */
4228 adapter->num_msix_vectors = min(vectors,
4229 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4230 }
4231 }
4232
4233 /**
4234 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4235 * @adapter: board private structure to initialize
4236 *
4237 * Cache the descriptor ring offsets for RSS to the assigned rings.
4238 *
4239 **/
4240 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4241 {
4242 int i;
4243
4244 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4245 return false;
4246
4247 for (i = 0; i < adapter->num_rx_queues; i++)
4248 adapter->rx_ring[i]->reg_idx = i;
4249 for (i = 0; i < adapter->num_tx_queues; i++)
4250 adapter->tx_ring[i]->reg_idx = i;
4251
4252 return true;
4253 }
4254
4255 #ifdef CONFIG_IXGBE_DCB
4256
4257 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4258 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4259 unsigned int *tx, unsigned int *rx)
4260 {
4261 struct net_device *dev = adapter->netdev;
4262 struct ixgbe_hw *hw = &adapter->hw;
4263 u8 num_tcs = netdev_get_num_tc(dev);
4264
4265 *tx = 0;
4266 *rx = 0;
4267
4268 switch (hw->mac.type) {
4269 case ixgbe_mac_82598EB:
4270 *tx = tc << 2;
4271 *rx = tc << 3;
4272 break;
4273 case ixgbe_mac_82599EB:
4274 case ixgbe_mac_X540:
4275 if (num_tcs > 4) {
4276 if (tc < 3) {
4277 *tx = tc << 5;
4278 *rx = tc << 4;
4279 } else if (tc < 5) {
4280 *tx = ((tc + 2) << 4);
4281 *rx = tc << 4;
4282 } else if (tc < num_tcs) {
4283 *tx = ((tc + 8) << 3);
4284 *rx = tc << 4;
4285 }
4286 } else {
4287 *rx = tc << 5;
4288 switch (tc) {
4289 case 0:
4290 *tx = 0;
4291 break;
4292 case 1:
4293 *tx = 64;
4294 break;
4295 case 2:
4296 *tx = 96;
4297 break;
4298 case 3:
4299 *tx = 112;
4300 break;
4301 default:
4302 break;
4303 }
4304 }
4305 break;
4306 default:
4307 break;
4308 }
4309 }
4310
4311 /**
4312 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4313 * @adapter: board private structure to initialize
4314 *
4315 * Cache the descriptor ring offsets for DCB to the assigned rings.
4316 *
4317 **/
4318 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4319 {
4320 struct net_device *dev = adapter->netdev;
4321 int i, j, k;
4322 u8 num_tcs = netdev_get_num_tc(dev);
4323
4324 if (!num_tcs)
4325 return false;
4326
4327 for (i = 0, k = 0; i < num_tcs; i++) {
4328 unsigned int tx_s, rx_s;
4329 u16 count = dev->tc_to_txq[i].count;
4330
4331 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4332 for (j = 0; j < count; j++, k++) {
4333 adapter->tx_ring[k]->reg_idx = tx_s + j;
4334 adapter->rx_ring[k]->reg_idx = rx_s + j;
4335 adapter->tx_ring[k]->dcb_tc = i;
4336 adapter->rx_ring[k]->dcb_tc = i;
4337 }
4338 }
4339
4340 return true;
4341 }
4342 #endif
4343
4344 /**
4345 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4346 * @adapter: board private structure to initialize
4347 *
4348 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4349 *
4350 **/
4351 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4352 {
4353 int i;
4354 bool ret = false;
4355
4356 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4357 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4358 for (i = 0; i < adapter->num_rx_queues; i++)
4359 adapter->rx_ring[i]->reg_idx = i;
4360 for (i = 0; i < adapter->num_tx_queues; i++)
4361 adapter->tx_ring[i]->reg_idx = i;
4362 ret = true;
4363 }
4364
4365 return ret;
4366 }
4367
4368 #ifdef IXGBE_FCOE
4369 /**
4370 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4371 * @adapter: board private structure to initialize
4372 *
4373 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4374 *
4375 */
4376 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4377 {
4378 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4379 int i;
4380 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4381
4382 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4383 return false;
4384
4385 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4386 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4387 ixgbe_cache_ring_fdir(adapter);
4388 else
4389 ixgbe_cache_ring_rss(adapter);
4390
4391 fcoe_rx_i = f->mask;
4392 fcoe_tx_i = f->mask;
4393 }
4394 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4395 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4396 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4397 }
4398 return true;
4399 }
4400
4401 #endif /* IXGBE_FCOE */
4402 /**
4403 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4404 * @adapter: board private structure to initialize
4405 *
4406 * SR-IOV doesn't use any descriptor rings but changes the default if
4407 * no other mapping is used.
4408 *
4409 */
4410 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4411 {
4412 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4413 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4414 if (adapter->num_vfs)
4415 return true;
4416 else
4417 return false;
4418 }
4419
4420 /**
4421 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4422 * @adapter: board private structure to initialize
4423 *
4424 * Once we know the feature-set enabled for the device, we'll cache
4425 * the register offset the descriptor ring is assigned to.
4426 *
4427 * Note, the order the various feature calls is important. It must start with
4428 * the "most" features enabled at the same time, then trickle down to the
4429 * least amount of features turned on at once.
4430 **/
4431 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4432 {
4433 /* start with default case */
4434 adapter->rx_ring[0]->reg_idx = 0;
4435 adapter->tx_ring[0]->reg_idx = 0;
4436
4437 if (ixgbe_cache_ring_sriov(adapter))
4438 return;
4439
4440 #ifdef CONFIG_IXGBE_DCB
4441 if (ixgbe_cache_ring_dcb(adapter))
4442 return;
4443 #endif
4444
4445 #ifdef IXGBE_FCOE
4446 if (ixgbe_cache_ring_fcoe(adapter))
4447 return;
4448 #endif /* IXGBE_FCOE */
4449
4450 if (ixgbe_cache_ring_fdir(adapter))
4451 return;
4452
4453 if (ixgbe_cache_ring_rss(adapter))
4454 return;
4455 }
4456
4457 /**
4458 * ixgbe_alloc_queues - Allocate memory for all rings
4459 * @adapter: board private structure to initialize
4460 *
4461 * We allocate one ring per queue at run-time since we don't know the
4462 * number of queues at compile-time. The polling_netdev array is
4463 * intended for Multiqueue, but should work fine with a single queue.
4464 **/
4465 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4466 {
4467 int rx = 0, tx = 0, nid = adapter->node;
4468
4469 if (nid < 0 || !node_online(nid))
4470 nid = first_online_node;
4471
4472 for (; tx < adapter->num_tx_queues; tx++) {
4473 struct ixgbe_ring *ring;
4474
4475 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4476 if (!ring)
4477 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4478 if (!ring)
4479 goto err_allocation;
4480 ring->count = adapter->tx_ring_count;
4481 ring->queue_index = tx;
4482 ring->numa_node = nid;
4483 ring->dev = &adapter->pdev->dev;
4484 ring->netdev = adapter->netdev;
4485
4486 adapter->tx_ring[tx] = ring;
4487 }
4488
4489 for (; rx < adapter->num_rx_queues; rx++) {
4490 struct ixgbe_ring *ring;
4491
4492 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4493 if (!ring)
4494 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4495 if (!ring)
4496 goto err_allocation;
4497 ring->count = adapter->rx_ring_count;
4498 ring->queue_index = rx;
4499 ring->numa_node = nid;
4500 ring->dev = &adapter->pdev->dev;
4501 ring->netdev = adapter->netdev;
4502
4503 adapter->rx_ring[rx] = ring;
4504 }
4505
4506 ixgbe_cache_ring_register(adapter);
4507
4508 return 0;
4509
4510 err_allocation:
4511 while (tx)
4512 kfree(adapter->tx_ring[--tx]);
4513
4514 while (rx)
4515 kfree(adapter->rx_ring[--rx]);
4516 return -ENOMEM;
4517 }
4518
4519 /**
4520 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4521 * @adapter: board private structure to initialize
4522 *
4523 * Attempt to configure the interrupts using the best available
4524 * capabilities of the hardware and the kernel.
4525 **/
4526 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4527 {
4528 struct ixgbe_hw *hw = &adapter->hw;
4529 int err = 0;
4530 int vector, v_budget;
4531
4532 /*
4533 * It's easy to be greedy for MSI-X vectors, but it really
4534 * doesn't do us much good if we have a lot more vectors
4535 * than CPU's. So let's be conservative and only ask for
4536 * (roughly) the same number of vectors as there are CPU's.
4537 */
4538 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4539 (int)num_online_cpus()) + NON_Q_VECTORS;
4540
4541 /*
4542 * At the same time, hardware can only support a maximum of
4543 * hw.mac->max_msix_vectors vectors. With features
4544 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4545 * descriptor queues supported by our device. Thus, we cap it off in
4546 * those rare cases where the cpu count also exceeds our vector limit.
4547 */
4548 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4549
4550 /* A failure in MSI-X entry allocation isn't fatal, but it does
4551 * mean we disable MSI-X capabilities of the adapter. */
4552 adapter->msix_entries = kcalloc(v_budget,
4553 sizeof(struct msix_entry), GFP_KERNEL);
4554 if (adapter->msix_entries) {
4555 for (vector = 0; vector < v_budget; vector++)
4556 adapter->msix_entries[vector].entry = vector;
4557
4558 ixgbe_acquire_msix_vectors(adapter, v_budget);
4559
4560 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4561 goto out;
4562 }
4563
4564 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4565 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4566 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4567 e_err(probe,
4568 "ATR is not supported while multiple "
4569 "queues are disabled. Disabling Flow Director\n");
4570 }
4571 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4572 adapter->atr_sample_rate = 0;
4573 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4574 ixgbe_disable_sriov(adapter);
4575
4576 err = ixgbe_set_num_queues(adapter);
4577 if (err)
4578 return err;
4579
4580 err = pci_enable_msi(adapter->pdev);
4581 if (!err) {
4582 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4583 } else {
4584 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4585 "Unable to allocate MSI interrupt, "
4586 "falling back to legacy. Error: %d\n", err);
4587 /* reset err */
4588 err = 0;
4589 }
4590
4591 out:
4592 return err;
4593 }
4594
4595 /**
4596 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4597 * @adapter: board private structure to initialize
4598 *
4599 * We allocate one q_vector per queue interrupt. If allocation fails we
4600 * return -ENOMEM.
4601 **/
4602 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4603 {
4604 int v_idx, num_q_vectors;
4605 struct ixgbe_q_vector *q_vector;
4606
4607 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4608 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4609 else
4610 num_q_vectors = 1;
4611
4612 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4613 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4614 GFP_KERNEL, adapter->node);
4615 if (!q_vector)
4616 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4617 GFP_KERNEL);
4618 if (!q_vector)
4619 goto err_out;
4620
4621 q_vector->adapter = adapter;
4622 q_vector->v_idx = v_idx;
4623
4624 /* Allocate the affinity_hint cpumask, configure the mask */
4625 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4626 goto err_out;
4627 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4628
4629 if (q_vector->tx.count && !q_vector->rx.count)
4630 q_vector->eitr = adapter->tx_eitr_param;
4631 else
4632 q_vector->eitr = adapter->rx_eitr_param;
4633
4634 netif_napi_add(adapter->netdev, &q_vector->napi,
4635 ixgbe_poll, 64);
4636 adapter->q_vector[v_idx] = q_vector;
4637 }
4638
4639 return 0;
4640
4641 err_out:
4642 while (v_idx) {
4643 v_idx--;
4644 q_vector = adapter->q_vector[v_idx];
4645 netif_napi_del(&q_vector->napi);
4646 free_cpumask_var(q_vector->affinity_mask);
4647 kfree(q_vector);
4648 adapter->q_vector[v_idx] = NULL;
4649 }
4650 return -ENOMEM;
4651 }
4652
4653 /**
4654 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4655 * @adapter: board private structure to initialize
4656 *
4657 * This function frees the memory allocated to the q_vectors. In addition if
4658 * NAPI is enabled it will delete any references to the NAPI struct prior
4659 * to freeing the q_vector.
4660 **/
4661 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4662 {
4663 int v_idx, num_q_vectors;
4664
4665 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4666 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4667 else
4668 num_q_vectors = 1;
4669
4670 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4671 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4672 adapter->q_vector[v_idx] = NULL;
4673 netif_napi_del(&q_vector->napi);
4674 free_cpumask_var(q_vector->affinity_mask);
4675 kfree(q_vector);
4676 }
4677 }
4678
4679 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4680 {
4681 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4682 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4683 pci_disable_msix(adapter->pdev);
4684 kfree(adapter->msix_entries);
4685 adapter->msix_entries = NULL;
4686 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4687 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4688 pci_disable_msi(adapter->pdev);
4689 }
4690 }
4691
4692 /**
4693 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4694 * @adapter: board private structure to initialize
4695 *
4696 * We determine which interrupt scheme to use based on...
4697 * - Kernel support (MSI, MSI-X)
4698 * - which can be user-defined (via MODULE_PARAM)
4699 * - Hardware queue count (num_*_queues)
4700 * - defined by miscellaneous hardware support/features (RSS, etc.)
4701 **/
4702 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4703 {
4704 int err;
4705
4706 /* Number of supported queues */
4707 err = ixgbe_set_num_queues(adapter);
4708 if (err)
4709 return err;
4710
4711 err = ixgbe_set_interrupt_capability(adapter);
4712 if (err) {
4713 e_dev_err("Unable to setup interrupt capabilities\n");
4714 goto err_set_interrupt;
4715 }
4716
4717 err = ixgbe_alloc_q_vectors(adapter);
4718 if (err) {
4719 e_dev_err("Unable to allocate memory for queue vectors\n");
4720 goto err_alloc_q_vectors;
4721 }
4722
4723 err = ixgbe_alloc_queues(adapter);
4724 if (err) {
4725 e_dev_err("Unable to allocate memory for queues\n");
4726 goto err_alloc_queues;
4727 }
4728
4729 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4730 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4731 adapter->num_rx_queues, adapter->num_tx_queues);
4732
4733 set_bit(__IXGBE_DOWN, &adapter->state);
4734
4735 return 0;
4736
4737 err_alloc_queues:
4738 ixgbe_free_q_vectors(adapter);
4739 err_alloc_q_vectors:
4740 ixgbe_reset_interrupt_capability(adapter);
4741 err_set_interrupt:
4742 return err;
4743 }
4744
4745 /**
4746 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4747 * @adapter: board private structure to clear interrupt scheme on
4748 *
4749 * We go through and clear interrupt specific resources and reset the structure
4750 * to pre-load conditions
4751 **/
4752 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4753 {
4754 int i;
4755
4756 for (i = 0; i < adapter->num_tx_queues; i++) {
4757 kfree(adapter->tx_ring[i]);
4758 adapter->tx_ring[i] = NULL;
4759 }
4760 for (i = 0; i < adapter->num_rx_queues; i++) {
4761 struct ixgbe_ring *ring = adapter->rx_ring[i];
4762
4763 /* ixgbe_get_stats64() might access this ring, we must wait
4764 * a grace period before freeing it.
4765 */
4766 kfree_rcu(ring, rcu);
4767 adapter->rx_ring[i] = NULL;
4768 }
4769
4770 adapter->num_tx_queues = 0;
4771 adapter->num_rx_queues = 0;
4772
4773 ixgbe_free_q_vectors(adapter);
4774 ixgbe_reset_interrupt_capability(adapter);
4775 }
4776
4777 /**
4778 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4779 * @adapter: board private structure to initialize
4780 *
4781 * ixgbe_sw_init initializes the Adapter private data structure.
4782 * Fields are initialized based on PCI device information and
4783 * OS network device settings (MTU size).
4784 **/
4785 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4786 {
4787 struct ixgbe_hw *hw = &adapter->hw;
4788 struct pci_dev *pdev = adapter->pdev;
4789 struct net_device *dev = adapter->netdev;
4790 unsigned int rss;
4791 #ifdef CONFIG_IXGBE_DCB
4792 int j;
4793 struct tc_configuration *tc;
4794 #endif
4795 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4796
4797 /* PCI config space info */
4798
4799 hw->vendor_id = pdev->vendor;
4800 hw->device_id = pdev->device;
4801 hw->revision_id = pdev->revision;
4802 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4803 hw->subsystem_device_id = pdev->subsystem_device;
4804
4805 /* Set capability flags */
4806 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4807 adapter->ring_feature[RING_F_RSS].indices = rss;
4808 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4809 switch (hw->mac.type) {
4810 case ixgbe_mac_82598EB:
4811 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4812 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4813 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4814 break;
4815 case ixgbe_mac_82599EB:
4816 case ixgbe_mac_X540:
4817 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4818 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4819 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4820 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4821 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4822 /* Flow Director hash filters enabled */
4823 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4824 adapter->atr_sample_rate = 20;
4825 adapter->ring_feature[RING_F_FDIR].indices =
4826 IXGBE_MAX_FDIR_INDICES;
4827 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4828 #ifdef IXGBE_FCOE
4829 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4830 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4831 adapter->ring_feature[RING_F_FCOE].indices = 0;
4832 #ifdef CONFIG_IXGBE_DCB
4833 /* Default traffic class to use for FCoE */
4834 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4835 #endif
4836 #endif /* IXGBE_FCOE */
4837 break;
4838 default:
4839 break;
4840 }
4841
4842 /* n-tuple support exists, always init our spinlock */
4843 spin_lock_init(&adapter->fdir_perfect_lock);
4844
4845 #ifdef CONFIG_IXGBE_DCB
4846 /* Configure DCB traffic classes */
4847 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4848 tc = &adapter->dcb_cfg.tc_config[j];
4849 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4850 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4851 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4852 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4853 tc->dcb_pfc = pfc_disabled;
4854 }
4855 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4856 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4857 adapter->dcb_cfg.pfc_mode_enable = false;
4858 adapter->dcb_set_bitmap = 0x00;
4859 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4860 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4861 MAX_TRAFFIC_CLASS);
4862
4863 #endif
4864
4865 /* default flow control settings */
4866 hw->fc.requested_mode = ixgbe_fc_full;
4867 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4868 #ifdef CONFIG_DCB
4869 adapter->last_lfc_mode = hw->fc.current_mode;
4870 #endif
4871 hw->fc.high_water = FC_HIGH_WATER(max_frame);
4872 hw->fc.low_water = FC_LOW_WATER(max_frame);
4873 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4874 hw->fc.send_xon = true;
4875 hw->fc.disable_fc_autoneg = false;
4876
4877 /* enable itr by default in dynamic mode */
4878 adapter->rx_itr_setting = 1;
4879 adapter->rx_eitr_param = 20000;
4880 adapter->tx_itr_setting = 1;
4881 adapter->tx_eitr_param = 10000;
4882
4883 /* set defaults for eitr in MegaBytes */
4884 adapter->eitr_low = 10;
4885 adapter->eitr_high = 20;
4886
4887 /* set default ring sizes */
4888 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4889 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4890
4891 /* set default work limits */
4892 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4893
4894 /* initialize eeprom parameters */
4895 if (ixgbe_init_eeprom_params_generic(hw)) {
4896 e_dev_err("EEPROM initialization failed\n");
4897 return -EIO;
4898 }
4899
4900 /* enable rx csum by default */
4901 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4902
4903 /* get assigned NUMA node */
4904 adapter->node = dev_to_node(&pdev->dev);
4905
4906 set_bit(__IXGBE_DOWN, &adapter->state);
4907
4908 return 0;
4909 }
4910
4911 /**
4912 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4913 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4914 *
4915 * Return 0 on success, negative on failure
4916 **/
4917 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4918 {
4919 struct device *dev = tx_ring->dev;
4920 int size;
4921
4922 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4923 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
4924 if (!tx_ring->tx_buffer_info)
4925 tx_ring->tx_buffer_info = vzalloc(size);
4926 if (!tx_ring->tx_buffer_info)
4927 goto err;
4928
4929 /* round up to nearest 4K */
4930 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4931 tx_ring->size = ALIGN(tx_ring->size, 4096);
4932
4933 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4934 &tx_ring->dma, GFP_KERNEL);
4935 if (!tx_ring->desc)
4936 goto err;
4937
4938 tx_ring->next_to_use = 0;
4939 tx_ring->next_to_clean = 0;
4940 return 0;
4941
4942 err:
4943 vfree(tx_ring->tx_buffer_info);
4944 tx_ring->tx_buffer_info = NULL;
4945 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4946 return -ENOMEM;
4947 }
4948
4949 /**
4950 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4951 * @adapter: board private structure
4952 *
4953 * If this function returns with an error, then it's possible one or
4954 * more of the rings is populated (while the rest are not). It is the
4955 * callers duty to clean those orphaned rings.
4956 *
4957 * Return 0 on success, negative on failure
4958 **/
4959 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4960 {
4961 int i, err = 0;
4962
4963 for (i = 0; i < adapter->num_tx_queues; i++) {
4964 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4965 if (!err)
4966 continue;
4967 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4968 break;
4969 }
4970
4971 return err;
4972 }
4973
4974 /**
4975 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4976 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4977 *
4978 * Returns 0 on success, negative on failure
4979 **/
4980 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4981 {
4982 struct device *dev = rx_ring->dev;
4983 int size;
4984
4985 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4986 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
4987 if (!rx_ring->rx_buffer_info)
4988 rx_ring->rx_buffer_info = vzalloc(size);
4989 if (!rx_ring->rx_buffer_info)
4990 goto err;
4991
4992 /* Round up to nearest 4K */
4993 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4994 rx_ring->size = ALIGN(rx_ring->size, 4096);
4995
4996 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4997 &rx_ring->dma, GFP_KERNEL);
4998
4999 if (!rx_ring->desc)
5000 goto err;
5001
5002 rx_ring->next_to_clean = 0;
5003 rx_ring->next_to_use = 0;
5004
5005 return 0;
5006 err:
5007 vfree(rx_ring->rx_buffer_info);
5008 rx_ring->rx_buffer_info = NULL;
5009 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5010 return -ENOMEM;
5011 }
5012
5013 /**
5014 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5015 * @adapter: board private structure
5016 *
5017 * If this function returns with an error, then it's possible one or
5018 * more of the rings is populated (while the rest are not). It is the
5019 * callers duty to clean those orphaned rings.
5020 *
5021 * Return 0 on success, negative on failure
5022 **/
5023 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5024 {
5025 int i, err = 0;
5026
5027 for (i = 0; i < adapter->num_rx_queues; i++) {
5028 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5029 if (!err)
5030 continue;
5031 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5032 break;
5033 }
5034
5035 return err;
5036 }
5037
5038 /**
5039 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5040 * @tx_ring: Tx descriptor ring for a specific queue
5041 *
5042 * Free all transmit software resources
5043 **/
5044 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5045 {
5046 ixgbe_clean_tx_ring(tx_ring);
5047
5048 vfree(tx_ring->tx_buffer_info);
5049 tx_ring->tx_buffer_info = NULL;
5050
5051 /* if not set, then don't free */
5052 if (!tx_ring->desc)
5053 return;
5054
5055 dma_free_coherent(tx_ring->dev, tx_ring->size,
5056 tx_ring->desc, tx_ring->dma);
5057
5058 tx_ring->desc = NULL;
5059 }
5060
5061 /**
5062 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5063 * @adapter: board private structure
5064 *
5065 * Free all transmit software resources
5066 **/
5067 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5068 {
5069 int i;
5070
5071 for (i = 0; i < adapter->num_tx_queues; i++)
5072 if (adapter->tx_ring[i]->desc)
5073 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5074 }
5075
5076 /**
5077 * ixgbe_free_rx_resources - Free Rx Resources
5078 * @rx_ring: ring to clean the resources from
5079 *
5080 * Free all receive software resources
5081 **/
5082 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5083 {
5084 ixgbe_clean_rx_ring(rx_ring);
5085
5086 vfree(rx_ring->rx_buffer_info);
5087 rx_ring->rx_buffer_info = NULL;
5088
5089 /* if not set, then don't free */
5090 if (!rx_ring->desc)
5091 return;
5092
5093 dma_free_coherent(rx_ring->dev, rx_ring->size,
5094 rx_ring->desc, rx_ring->dma);
5095
5096 rx_ring->desc = NULL;
5097 }
5098
5099 /**
5100 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5101 * @adapter: board private structure
5102 *
5103 * Free all receive software resources
5104 **/
5105 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5106 {
5107 int i;
5108
5109 for (i = 0; i < adapter->num_rx_queues; i++)
5110 if (adapter->rx_ring[i]->desc)
5111 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5112 }
5113
5114 /**
5115 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5116 * @netdev: network interface device structure
5117 * @new_mtu: new value for maximum frame size
5118 *
5119 * Returns 0 on success, negative on failure
5120 **/
5121 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5122 {
5123 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5124 struct ixgbe_hw *hw = &adapter->hw;
5125 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5126
5127 /* MTU < 68 is an error and causes problems on some kernels */
5128 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5129 hw->mac.type != ixgbe_mac_X540) {
5130 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5131 return -EINVAL;
5132 } else {
5133 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5134 return -EINVAL;
5135 }
5136
5137 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5138 /* must set new MTU before calling down or up */
5139 netdev->mtu = new_mtu;
5140
5141 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5142 hw->fc.low_water = FC_LOW_WATER(max_frame);
5143
5144 if (netif_running(netdev))
5145 ixgbe_reinit_locked(adapter);
5146
5147 return 0;
5148 }
5149
5150 /**
5151 * ixgbe_open - Called when a network interface is made active
5152 * @netdev: network interface device structure
5153 *
5154 * Returns 0 on success, negative value on failure
5155 *
5156 * The open entry point is called when a network interface is made
5157 * active by the system (IFF_UP). At this point all resources needed
5158 * for transmit and receive operations are allocated, the interrupt
5159 * handler is registered with the OS, the watchdog timer is started,
5160 * and the stack is notified that the interface is ready.
5161 **/
5162 static int ixgbe_open(struct net_device *netdev)
5163 {
5164 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5165 int err;
5166
5167 /* disallow open during test */
5168 if (test_bit(__IXGBE_TESTING, &adapter->state))
5169 return -EBUSY;
5170
5171 netif_carrier_off(netdev);
5172
5173 /* allocate transmit descriptors */
5174 err = ixgbe_setup_all_tx_resources(adapter);
5175 if (err)
5176 goto err_setup_tx;
5177
5178 /* allocate receive descriptors */
5179 err = ixgbe_setup_all_rx_resources(adapter);
5180 if (err)
5181 goto err_setup_rx;
5182
5183 ixgbe_configure(adapter);
5184
5185 err = ixgbe_request_irq(adapter);
5186 if (err)
5187 goto err_req_irq;
5188
5189 err = ixgbe_up_complete(adapter);
5190 if (err)
5191 goto err_up;
5192
5193 netif_tx_start_all_queues(netdev);
5194
5195 return 0;
5196
5197 err_up:
5198 ixgbe_release_hw_control(adapter);
5199 ixgbe_free_irq(adapter);
5200 err_req_irq:
5201 err_setup_rx:
5202 ixgbe_free_all_rx_resources(adapter);
5203 err_setup_tx:
5204 ixgbe_free_all_tx_resources(adapter);
5205 ixgbe_reset(adapter);
5206
5207 return err;
5208 }
5209
5210 /**
5211 * ixgbe_close - Disables a network interface
5212 * @netdev: network interface device structure
5213 *
5214 * Returns 0, this is not allowed to fail
5215 *
5216 * The close entry point is called when an interface is de-activated
5217 * by the OS. The hardware is still under the drivers control, but
5218 * needs to be disabled. A global MAC reset is issued to stop the
5219 * hardware, and all transmit and receive resources are freed.
5220 **/
5221 static int ixgbe_close(struct net_device *netdev)
5222 {
5223 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5224
5225 ixgbe_down(adapter);
5226 ixgbe_free_irq(adapter);
5227
5228 ixgbe_fdir_filter_exit(adapter);
5229
5230 ixgbe_free_all_tx_resources(adapter);
5231 ixgbe_free_all_rx_resources(adapter);
5232
5233 ixgbe_release_hw_control(adapter);
5234
5235 return 0;
5236 }
5237
5238 #ifdef CONFIG_PM
5239 static int ixgbe_resume(struct pci_dev *pdev)
5240 {
5241 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5242 struct net_device *netdev = adapter->netdev;
5243 u32 err;
5244
5245 pci_set_power_state(pdev, PCI_D0);
5246 pci_restore_state(pdev);
5247 /*
5248 * pci_restore_state clears dev->state_saved so call
5249 * pci_save_state to restore it.
5250 */
5251 pci_save_state(pdev);
5252
5253 err = pci_enable_device_mem(pdev);
5254 if (err) {
5255 e_dev_err("Cannot enable PCI device from suspend\n");
5256 return err;
5257 }
5258 pci_set_master(pdev);
5259
5260 pci_wake_from_d3(pdev, false);
5261
5262 err = ixgbe_init_interrupt_scheme(adapter);
5263 if (err) {
5264 e_dev_err("Cannot initialize interrupts for device\n");
5265 return err;
5266 }
5267
5268 ixgbe_reset(adapter);
5269
5270 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5271
5272 if (netif_running(netdev)) {
5273 err = ixgbe_open(netdev);
5274 if (err)
5275 return err;
5276 }
5277
5278 netif_device_attach(netdev);
5279
5280 return 0;
5281 }
5282 #endif /* CONFIG_PM */
5283
5284 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5285 {
5286 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5287 struct net_device *netdev = adapter->netdev;
5288 struct ixgbe_hw *hw = &adapter->hw;
5289 u32 ctrl, fctrl;
5290 u32 wufc = adapter->wol;
5291 #ifdef CONFIG_PM
5292 int retval = 0;
5293 #endif
5294
5295 netif_device_detach(netdev);
5296
5297 if (netif_running(netdev)) {
5298 ixgbe_down(adapter);
5299 ixgbe_free_irq(adapter);
5300 ixgbe_free_all_tx_resources(adapter);
5301 ixgbe_free_all_rx_resources(adapter);
5302 }
5303
5304 ixgbe_clear_interrupt_scheme(adapter);
5305 #ifdef CONFIG_DCB
5306 kfree(adapter->ixgbe_ieee_pfc);
5307 kfree(adapter->ixgbe_ieee_ets);
5308 #endif
5309
5310 #ifdef CONFIG_PM
5311 retval = pci_save_state(pdev);
5312 if (retval)
5313 return retval;
5314
5315 #endif
5316 if (wufc) {
5317 ixgbe_set_rx_mode(netdev);
5318
5319 /* turn on all-multi mode if wake on multicast is enabled */
5320 if (wufc & IXGBE_WUFC_MC) {
5321 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5322 fctrl |= IXGBE_FCTRL_MPE;
5323 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5324 }
5325
5326 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5327 ctrl |= IXGBE_CTRL_GIO_DIS;
5328 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5329
5330 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5331 } else {
5332 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5333 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5334 }
5335
5336 switch (hw->mac.type) {
5337 case ixgbe_mac_82598EB:
5338 pci_wake_from_d3(pdev, false);
5339 break;
5340 case ixgbe_mac_82599EB:
5341 case ixgbe_mac_X540:
5342 pci_wake_from_d3(pdev, !!wufc);
5343 break;
5344 default:
5345 break;
5346 }
5347
5348 *enable_wake = !!wufc;
5349
5350 ixgbe_release_hw_control(adapter);
5351
5352 pci_disable_device(pdev);
5353
5354 return 0;
5355 }
5356
5357 #ifdef CONFIG_PM
5358 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5359 {
5360 int retval;
5361 bool wake;
5362
5363 retval = __ixgbe_shutdown(pdev, &wake);
5364 if (retval)
5365 return retval;
5366
5367 if (wake) {
5368 pci_prepare_to_sleep(pdev);
5369 } else {
5370 pci_wake_from_d3(pdev, false);
5371 pci_set_power_state(pdev, PCI_D3hot);
5372 }
5373
5374 return 0;
5375 }
5376 #endif /* CONFIG_PM */
5377
5378 static void ixgbe_shutdown(struct pci_dev *pdev)
5379 {
5380 bool wake;
5381
5382 __ixgbe_shutdown(pdev, &wake);
5383
5384 if (system_state == SYSTEM_POWER_OFF) {
5385 pci_wake_from_d3(pdev, wake);
5386 pci_set_power_state(pdev, PCI_D3hot);
5387 }
5388 }
5389
5390 /**
5391 * ixgbe_update_stats - Update the board statistics counters.
5392 * @adapter: board private structure
5393 **/
5394 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5395 {
5396 struct net_device *netdev = adapter->netdev;
5397 struct ixgbe_hw *hw = &adapter->hw;
5398 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5399 u64 total_mpc = 0;
5400 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5401 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5402 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5403 u64 bytes = 0, packets = 0;
5404
5405 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5406 test_bit(__IXGBE_RESETTING, &adapter->state))
5407 return;
5408
5409 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5410 u64 rsc_count = 0;
5411 u64 rsc_flush = 0;
5412 for (i = 0; i < 16; i++)
5413 adapter->hw_rx_no_dma_resources +=
5414 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5415 for (i = 0; i < adapter->num_rx_queues; i++) {
5416 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5417 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5418 }
5419 adapter->rsc_total_count = rsc_count;
5420 adapter->rsc_total_flush = rsc_flush;
5421 }
5422
5423 for (i = 0; i < adapter->num_rx_queues; i++) {
5424 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5425 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5426 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5427 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5428 bytes += rx_ring->stats.bytes;
5429 packets += rx_ring->stats.packets;
5430 }
5431 adapter->non_eop_descs = non_eop_descs;
5432 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5433 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5434 netdev->stats.rx_bytes = bytes;
5435 netdev->stats.rx_packets = packets;
5436
5437 bytes = 0;
5438 packets = 0;
5439 /* gather some stats to the adapter struct that are per queue */
5440 for (i = 0; i < adapter->num_tx_queues; i++) {
5441 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5442 restart_queue += tx_ring->tx_stats.restart_queue;
5443 tx_busy += tx_ring->tx_stats.tx_busy;
5444 bytes += tx_ring->stats.bytes;
5445 packets += tx_ring->stats.packets;
5446 }
5447 adapter->restart_queue = restart_queue;
5448 adapter->tx_busy = tx_busy;
5449 netdev->stats.tx_bytes = bytes;
5450 netdev->stats.tx_packets = packets;
5451
5452 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5453 for (i = 0; i < 8; i++) {
5454 /* for packet buffers not used, the register should read 0 */
5455 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5456 missed_rx += mpc;
5457 hwstats->mpc[i] += mpc;
5458 total_mpc += hwstats->mpc[i];
5459 if (hw->mac.type == ixgbe_mac_82598EB)
5460 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5461 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5462 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5463 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5464 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5465 switch (hw->mac.type) {
5466 case ixgbe_mac_82598EB:
5467 hwstats->pxonrxc[i] +=
5468 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5469 break;
5470 case ixgbe_mac_82599EB:
5471 case ixgbe_mac_X540:
5472 hwstats->pxonrxc[i] +=
5473 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5474 break;
5475 default:
5476 break;
5477 }
5478 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5479 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5480 }
5481 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5482 /* work around hardware counting issue */
5483 hwstats->gprc -= missed_rx;
5484
5485 ixgbe_update_xoff_received(adapter);
5486
5487 /* 82598 hardware only has a 32 bit counter in the high register */
5488 switch (hw->mac.type) {
5489 case ixgbe_mac_82598EB:
5490 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5491 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5492 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5493 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5494 break;
5495 case ixgbe_mac_X540:
5496 /* OS2BMC stats are X540 only*/
5497 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5498 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5499 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5500 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5501 case ixgbe_mac_82599EB:
5502 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5503 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5504 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5505 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5506 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5507 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5508 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5509 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5510 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5511 #ifdef IXGBE_FCOE
5512 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5513 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5514 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5515 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5516 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5517 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5518 #endif /* IXGBE_FCOE */
5519 break;
5520 default:
5521 break;
5522 }
5523 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5524 hwstats->bprc += bprc;
5525 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5526 if (hw->mac.type == ixgbe_mac_82598EB)
5527 hwstats->mprc -= bprc;
5528 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5529 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5530 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5531 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5532 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5533 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5534 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5535 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5536 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5537 hwstats->lxontxc += lxon;
5538 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5539 hwstats->lxofftxc += lxoff;
5540 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5541 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5542 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5543 /*
5544 * 82598 errata - tx of flow control packets is included in tx counters
5545 */
5546 xon_off_tot = lxon + lxoff;
5547 hwstats->gptc -= xon_off_tot;
5548 hwstats->mptc -= xon_off_tot;
5549 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5550 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5551 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5552 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5553 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5554 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5555 hwstats->ptc64 -= xon_off_tot;
5556 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5557 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5558 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5559 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5560 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5561 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5562
5563 /* Fill out the OS statistics structure */
5564 netdev->stats.multicast = hwstats->mprc;
5565
5566 /* Rx Errors */
5567 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5568 netdev->stats.rx_dropped = 0;
5569 netdev->stats.rx_length_errors = hwstats->rlec;
5570 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5571 netdev->stats.rx_missed_errors = total_mpc;
5572 }
5573
5574 /**
5575 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5576 * @adapter - pointer to the device adapter structure
5577 **/
5578 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5579 {
5580 struct ixgbe_hw *hw = &adapter->hw;
5581 int i;
5582
5583 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5584 return;
5585
5586 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5587
5588 /* if interface is down do nothing */
5589 if (test_bit(__IXGBE_DOWN, &adapter->state))
5590 return;
5591
5592 /* do nothing if we are not using signature filters */
5593 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5594 return;
5595
5596 adapter->fdir_overflow++;
5597
5598 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5599 for (i = 0; i < adapter->num_tx_queues; i++)
5600 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5601 &(adapter->tx_ring[i]->state));
5602 /* re-enable flow director interrupts */
5603 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5604 } else {
5605 e_err(probe, "failed to finish FDIR re-initialization, "
5606 "ignored adding FDIR ATR filters\n");
5607 }
5608 }
5609
5610 /**
5611 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5612 * @adapter - pointer to the device adapter structure
5613 *
5614 * This function serves two purposes. First it strobes the interrupt lines
5615 * in order to make certain interrupts are occuring. Secondly it sets the
5616 * bits needed to check for TX hangs. As a result we should immediately
5617 * determine if a hang has occured.
5618 */
5619 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5620 {
5621 struct ixgbe_hw *hw = &adapter->hw;
5622 u64 eics = 0;
5623 int i;
5624
5625 /* If we're down or resetting, just bail */
5626 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5627 test_bit(__IXGBE_RESETTING, &adapter->state))
5628 return;
5629
5630 /* Force detection of hung controller */
5631 if (netif_carrier_ok(adapter->netdev)) {
5632 for (i = 0; i < adapter->num_tx_queues; i++)
5633 set_check_for_tx_hang(adapter->tx_ring[i]);
5634 }
5635
5636 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5637 /*
5638 * for legacy and MSI interrupts don't set any bits
5639 * that are enabled for EIAM, because this operation
5640 * would set *both* EIMS and EICS for any bit in EIAM
5641 */
5642 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5643 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5644 } else {
5645 /* get one bit for every active tx/rx interrupt vector */
5646 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5647 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5648 if (qv->rx.ring || qv->tx.ring)
5649 eics |= ((u64)1 << i);
5650 }
5651 }
5652
5653 /* Cause software interrupt to ensure rings are cleaned */
5654 ixgbe_irq_rearm_queues(adapter, eics);
5655
5656 }
5657
5658 /**
5659 * ixgbe_watchdog_update_link - update the link status
5660 * @adapter - pointer to the device adapter structure
5661 * @link_speed - pointer to a u32 to store the link_speed
5662 **/
5663 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5664 {
5665 struct ixgbe_hw *hw = &adapter->hw;
5666 u32 link_speed = adapter->link_speed;
5667 bool link_up = adapter->link_up;
5668 int i;
5669
5670 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5671 return;
5672
5673 if (hw->mac.ops.check_link) {
5674 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5675 } else {
5676 /* always assume link is up, if no check link function */
5677 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5678 link_up = true;
5679 }
5680 if (link_up) {
5681 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5682 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5683 hw->mac.ops.fc_enable(hw, i);
5684 } else {
5685 hw->mac.ops.fc_enable(hw, 0);
5686 }
5687 }
5688
5689 if (link_up ||
5690 time_after(jiffies, (adapter->link_check_timeout +
5691 IXGBE_TRY_LINK_TIMEOUT))) {
5692 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5693 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5694 IXGBE_WRITE_FLUSH(hw);
5695 }
5696
5697 adapter->link_up = link_up;
5698 adapter->link_speed = link_speed;
5699 }
5700
5701 /**
5702 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5703 * print link up message
5704 * @adapter - pointer to the device adapter structure
5705 **/
5706 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5707 {
5708 struct net_device *netdev = adapter->netdev;
5709 struct ixgbe_hw *hw = &adapter->hw;
5710 u32 link_speed = adapter->link_speed;
5711 bool flow_rx, flow_tx;
5712
5713 /* only continue if link was previously down */
5714 if (netif_carrier_ok(netdev))
5715 return;
5716
5717 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5718
5719 switch (hw->mac.type) {
5720 case ixgbe_mac_82598EB: {
5721 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5722 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5723 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5724 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5725 }
5726 break;
5727 case ixgbe_mac_X540:
5728 case ixgbe_mac_82599EB: {
5729 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5730 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5731 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5732 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5733 }
5734 break;
5735 default:
5736 flow_tx = false;
5737 flow_rx = false;
5738 break;
5739 }
5740 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5741 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5742 "10 Gbps" :
5743 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5744 "1 Gbps" :
5745 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5746 "100 Mbps" :
5747 "unknown speed"))),
5748 ((flow_rx && flow_tx) ? "RX/TX" :
5749 (flow_rx ? "RX" :
5750 (flow_tx ? "TX" : "None"))));
5751
5752 netif_carrier_on(netdev);
5753 ixgbe_check_vf_rate_limit(adapter);
5754 }
5755
5756 /**
5757 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5758 * print link down message
5759 * @adapter - pointer to the adapter structure
5760 **/
5761 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
5762 {
5763 struct net_device *netdev = adapter->netdev;
5764 struct ixgbe_hw *hw = &adapter->hw;
5765
5766 adapter->link_up = false;
5767 adapter->link_speed = 0;
5768
5769 /* only continue if link was up previously */
5770 if (!netif_carrier_ok(netdev))
5771 return;
5772
5773 /* poll for SFP+ cable when link is down */
5774 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5775 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5776
5777 e_info(drv, "NIC Link is Down\n");
5778 netif_carrier_off(netdev);
5779 }
5780
5781 /**
5782 * ixgbe_watchdog_flush_tx - flush queues on link down
5783 * @adapter - pointer to the device adapter structure
5784 **/
5785 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5786 {
5787 int i;
5788 int some_tx_pending = 0;
5789
5790 if (!netif_carrier_ok(adapter->netdev)) {
5791 for (i = 0; i < adapter->num_tx_queues; i++) {
5792 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5793 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5794 some_tx_pending = 1;
5795 break;
5796 }
5797 }
5798
5799 if (some_tx_pending) {
5800 /* We've lost link, so the controller stops DMA,
5801 * but we've got queued Tx work that's never going
5802 * to get done, so reset controller to flush Tx.
5803 * (Do the reset outside of interrupt context).
5804 */
5805 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5806 }
5807 }
5808 }
5809
5810 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5811 {
5812 u32 ssvpc;
5813
5814 /* Do not perform spoof check for 82598 */
5815 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5816 return;
5817
5818 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5819
5820 /*
5821 * ssvpc register is cleared on read, if zero then no
5822 * spoofed packets in the last interval.
5823 */
5824 if (!ssvpc)
5825 return;
5826
5827 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5828 }
5829
5830 /**
5831 * ixgbe_watchdog_subtask - check and bring link up
5832 * @adapter - pointer to the device adapter structure
5833 **/
5834 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5835 {
5836 /* if interface is down do nothing */
5837 if (test_bit(__IXGBE_DOWN, &adapter->state))
5838 return;
5839
5840 ixgbe_watchdog_update_link(adapter);
5841
5842 if (adapter->link_up)
5843 ixgbe_watchdog_link_is_up(adapter);
5844 else
5845 ixgbe_watchdog_link_is_down(adapter);
5846
5847 ixgbe_spoof_check(adapter);
5848 ixgbe_update_stats(adapter);
5849
5850 ixgbe_watchdog_flush_tx(adapter);
5851 }
5852
5853 /**
5854 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5855 * @adapter - the ixgbe adapter structure
5856 **/
5857 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5858 {
5859 struct ixgbe_hw *hw = &adapter->hw;
5860 s32 err;
5861
5862 /* not searching for SFP so there is nothing to do here */
5863 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5864 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5865 return;
5866
5867 /* someone else is in init, wait until next service event */
5868 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5869 return;
5870
5871 err = hw->phy.ops.identify_sfp(hw);
5872 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5873 goto sfp_out;
5874
5875 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5876 /* If no cable is present, then we need to reset
5877 * the next time we find a good cable. */
5878 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5879 }
5880
5881 /* exit on error */
5882 if (err)
5883 goto sfp_out;
5884
5885 /* exit if reset not needed */
5886 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5887 goto sfp_out;
5888
5889 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5890
5891 /*
5892 * A module may be identified correctly, but the EEPROM may not have
5893 * support for that module. setup_sfp() will fail in that case, so
5894 * we should not allow that module to load.
5895 */
5896 if (hw->mac.type == ixgbe_mac_82598EB)
5897 err = hw->phy.ops.reset(hw);
5898 else
5899 err = hw->mac.ops.setup_sfp(hw);
5900
5901 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5902 goto sfp_out;
5903
5904 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5905 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5906
5907 sfp_out:
5908 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5909
5910 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5911 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5912 e_dev_err("failed to initialize because an unsupported "
5913 "SFP+ module type was detected.\n");
5914 e_dev_err("Reload the driver after installing a "
5915 "supported module.\n");
5916 unregister_netdev(adapter->netdev);
5917 }
5918 }
5919
5920 /**
5921 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5922 * @adapter - the ixgbe adapter structure
5923 **/
5924 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5925 {
5926 struct ixgbe_hw *hw = &adapter->hw;
5927 u32 autoneg;
5928 bool negotiation;
5929
5930 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5931 return;
5932
5933 /* someone else is in init, wait until next service event */
5934 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5935 return;
5936
5937 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5938
5939 autoneg = hw->phy.autoneg_advertised;
5940 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5941 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5942 hw->mac.autotry_restart = false;
5943 if (hw->mac.ops.setup_link)
5944 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5945
5946 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5947 adapter->link_check_timeout = jiffies;
5948 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5949 }
5950
5951 /**
5952 * ixgbe_service_timer - Timer Call-back
5953 * @data: pointer to adapter cast into an unsigned long
5954 **/
5955 static void ixgbe_service_timer(unsigned long data)
5956 {
5957 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5958 unsigned long next_event_offset;
5959
5960 /* poll faster when waiting for link */
5961 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5962 next_event_offset = HZ / 10;
5963 else
5964 next_event_offset = HZ * 2;
5965
5966 /* Reset the timer */
5967 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5968
5969 ixgbe_service_event_schedule(adapter);
5970 }
5971
5972 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5973 {
5974 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5975 return;
5976
5977 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5978
5979 /* If we're already down or resetting, just bail */
5980 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5981 test_bit(__IXGBE_RESETTING, &adapter->state))
5982 return;
5983
5984 ixgbe_dump(adapter);
5985 netdev_err(adapter->netdev, "Reset adapter\n");
5986 adapter->tx_timeout_count++;
5987
5988 ixgbe_reinit_locked(adapter);
5989 }
5990
5991 /**
5992 * ixgbe_service_task - manages and runs subtasks
5993 * @work: pointer to work_struct containing our data
5994 **/
5995 static void ixgbe_service_task(struct work_struct *work)
5996 {
5997 struct ixgbe_adapter *adapter = container_of(work,
5998 struct ixgbe_adapter,
5999 service_task);
6000
6001 ixgbe_reset_subtask(adapter);
6002 ixgbe_sfp_detection_subtask(adapter);
6003 ixgbe_sfp_link_config_subtask(adapter);
6004 ixgbe_check_overtemp_subtask(adapter);
6005 ixgbe_watchdog_subtask(adapter);
6006 ixgbe_fdir_reinit_subtask(adapter);
6007 ixgbe_check_hang_subtask(adapter);
6008
6009 ixgbe_service_event_complete(adapter);
6010 }
6011
6012 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6013 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6014 {
6015 struct ixgbe_adv_tx_context_desc *context_desc;
6016 u16 i = tx_ring->next_to_use;
6017
6018 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6019
6020 i++;
6021 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6022
6023 /* set bits to identify this as an advanced context descriptor */
6024 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6025
6026 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6027 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6028 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6029 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6030 }
6031
6032 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6033 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6034 {
6035 int err;
6036 u32 vlan_macip_lens, type_tucmd;
6037 u32 mss_l4len_idx, l4len;
6038
6039 if (!skb_is_gso(skb))
6040 return 0;
6041
6042 if (skb_header_cloned(skb)) {
6043 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6044 if (err)
6045 return err;
6046 }
6047
6048 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6049 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6050
6051 if (protocol == __constant_htons(ETH_P_IP)) {
6052 struct iphdr *iph = ip_hdr(skb);
6053 iph->tot_len = 0;
6054 iph->check = 0;
6055 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6056 iph->daddr, 0,
6057 IPPROTO_TCP,
6058 0);
6059 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6060 } else if (skb_is_gso_v6(skb)) {
6061 ipv6_hdr(skb)->payload_len = 0;
6062 tcp_hdr(skb)->check =
6063 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6064 &ipv6_hdr(skb)->daddr,
6065 0, IPPROTO_TCP, 0);
6066 }
6067
6068 l4len = tcp_hdrlen(skb);
6069 *hdr_len = skb_transport_offset(skb) + l4len;
6070
6071 /* mss_l4len_id: use 1 as index for TSO */
6072 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6073 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6074 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6075
6076 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6077 vlan_macip_lens = skb_network_header_len(skb);
6078 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6079 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6080
6081 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6082 mss_l4len_idx);
6083
6084 return 1;
6085 }
6086
6087 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6088 struct sk_buff *skb, u32 tx_flags,
6089 __be16 protocol)
6090 {
6091 u32 vlan_macip_lens = 0;
6092 u32 mss_l4len_idx = 0;
6093 u32 type_tucmd = 0;
6094
6095 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6096 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6097 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
6098 return false;
6099 } else {
6100 u8 l4_hdr = 0;
6101 switch (protocol) {
6102 case __constant_htons(ETH_P_IP):
6103 vlan_macip_lens |= skb_network_header_len(skb);
6104 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6105 l4_hdr = ip_hdr(skb)->protocol;
6106 break;
6107 case __constant_htons(ETH_P_IPV6):
6108 vlan_macip_lens |= skb_network_header_len(skb);
6109 l4_hdr = ipv6_hdr(skb)->nexthdr;
6110 break;
6111 default:
6112 if (unlikely(net_ratelimit())) {
6113 dev_warn(tx_ring->dev,
6114 "partial checksum but proto=%x!\n",
6115 skb->protocol);
6116 }
6117 break;
6118 }
6119
6120 switch (l4_hdr) {
6121 case IPPROTO_TCP:
6122 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6123 mss_l4len_idx = tcp_hdrlen(skb) <<
6124 IXGBE_ADVTXD_L4LEN_SHIFT;
6125 break;
6126 case IPPROTO_SCTP:
6127 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6128 mss_l4len_idx = sizeof(struct sctphdr) <<
6129 IXGBE_ADVTXD_L4LEN_SHIFT;
6130 break;
6131 case IPPROTO_UDP:
6132 mss_l4len_idx = sizeof(struct udphdr) <<
6133 IXGBE_ADVTXD_L4LEN_SHIFT;
6134 break;
6135 default:
6136 if (unlikely(net_ratelimit())) {
6137 dev_warn(tx_ring->dev,
6138 "partial checksum but l4 proto=%x!\n",
6139 skb->protocol);
6140 }
6141 break;
6142 }
6143 }
6144
6145 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6146 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6147
6148 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6149 type_tucmd, mss_l4len_idx);
6150
6151 return (skb->ip_summed == CHECKSUM_PARTIAL);
6152 }
6153
6154 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6155 {
6156 /* set type for advanced descriptor with frame checksum insertion */
6157 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6158 IXGBE_ADVTXD_DCMD_IFCS |
6159 IXGBE_ADVTXD_DCMD_DEXT);
6160
6161 /* set HW vlan bit if vlan is present */
6162 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6163 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6164
6165 /* set segmentation enable bits for TSO/FSO */
6166 #ifdef IXGBE_FCOE
6167 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6168 #else
6169 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6170 #endif
6171 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6172
6173 return cmd_type;
6174 }
6175
6176 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6177 {
6178 __le32 olinfo_status =
6179 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6180
6181 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6182 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6183 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6184 /* enble IPv4 checksum for TSO */
6185 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6186 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6187 }
6188
6189 /* enable L4 checksum for TSO and TX checksum offload */
6190 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6191 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6192
6193 #ifdef IXGBE_FCOE
6194 /* use index 1 context for FCOE/FSO */
6195 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6196 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6197 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6198
6199 #endif
6200 /*
6201 * Check Context must be set if Tx switch is enabled, which it
6202 * always is for case where virtual functions are running
6203 */
6204 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6205 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6206
6207 return olinfo_status;
6208 }
6209
6210 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6211 IXGBE_TXD_CMD_RS)
6212
6213 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6214 struct sk_buff *skb,
6215 struct ixgbe_tx_buffer *first,
6216 u32 tx_flags,
6217 const u8 hdr_len)
6218 {
6219 struct device *dev = tx_ring->dev;
6220 struct ixgbe_tx_buffer *tx_buffer_info;
6221 union ixgbe_adv_tx_desc *tx_desc;
6222 dma_addr_t dma;
6223 __le32 cmd_type, olinfo_status;
6224 struct skb_frag_struct *frag;
6225 unsigned int f = 0;
6226 unsigned int data_len = skb->data_len;
6227 unsigned int size = skb_headlen(skb);
6228 u32 offset = 0;
6229 u32 paylen = skb->len - hdr_len;
6230 u16 i = tx_ring->next_to_use;
6231 u16 gso_segs;
6232
6233 #ifdef IXGBE_FCOE
6234 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6235 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6236 data_len -= sizeof(struct fcoe_crc_eof);
6237 } else {
6238 size -= sizeof(struct fcoe_crc_eof) - data_len;
6239 data_len = 0;
6240 }
6241 }
6242
6243 #endif
6244 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6245 if (dma_mapping_error(dev, dma))
6246 goto dma_error;
6247
6248 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6249 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6250
6251 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6252
6253 for (;;) {
6254 while (size > IXGBE_MAX_DATA_PER_TXD) {
6255 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6256 tx_desc->read.cmd_type_len =
6257 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6258 tx_desc->read.olinfo_status = olinfo_status;
6259
6260 offset += IXGBE_MAX_DATA_PER_TXD;
6261 size -= IXGBE_MAX_DATA_PER_TXD;
6262
6263 tx_desc++;
6264 i++;
6265 if (i == tx_ring->count) {
6266 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6267 i = 0;
6268 }
6269 }
6270
6271 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6272 tx_buffer_info->length = offset + size;
6273 tx_buffer_info->tx_flags = tx_flags;
6274 tx_buffer_info->dma = dma;
6275
6276 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6277 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6278 tx_desc->read.olinfo_status = olinfo_status;
6279
6280 if (!data_len)
6281 break;
6282
6283 frag = &skb_shinfo(skb)->frags[f];
6284 #ifdef IXGBE_FCOE
6285 size = min_t(unsigned int, data_len, frag->size);
6286 #else
6287 size = frag->size;
6288 #endif
6289 data_len -= size;
6290 f++;
6291
6292 offset = 0;
6293 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6294
6295 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
6296 if (dma_mapping_error(dev, dma))
6297 goto dma_error;
6298
6299 tx_desc++;
6300 i++;
6301 if (i == tx_ring->count) {
6302 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6303 i = 0;
6304 }
6305 }
6306
6307 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6308
6309 i++;
6310 if (i == tx_ring->count)
6311 i = 0;
6312
6313 tx_ring->next_to_use = i;
6314
6315 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6316 gso_segs = skb_shinfo(skb)->gso_segs;
6317 #ifdef IXGBE_FCOE
6318 /* adjust for FCoE Sequence Offload */
6319 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6320 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6321 skb_shinfo(skb)->gso_size);
6322 #endif /* IXGBE_FCOE */
6323 else
6324 gso_segs = 1;
6325
6326 /* multiply data chunks by size of headers */
6327 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6328 tx_buffer_info->gso_segs = gso_segs;
6329 tx_buffer_info->skb = skb;
6330
6331 /* set the timestamp */
6332 first->time_stamp = jiffies;
6333
6334 /*
6335 * Force memory writes to complete before letting h/w
6336 * know there are new descriptors to fetch. (Only
6337 * applicable for weak-ordered memory model archs,
6338 * such as IA-64).
6339 */
6340 wmb();
6341
6342 /* set next_to_watch value indicating a packet is present */
6343 first->next_to_watch = tx_desc;
6344
6345 /* notify HW of packet */
6346 writel(i, tx_ring->tail);
6347
6348 return;
6349 dma_error:
6350 dev_err(dev, "TX DMA map failed\n");
6351
6352 /* clear dma mappings for failed tx_buffer_info map */
6353 for (;;) {
6354 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6355 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6356 if (tx_buffer_info == first)
6357 break;
6358 if (i == 0)
6359 i = tx_ring->count;
6360 i--;
6361 }
6362
6363 dev_kfree_skb_any(skb);
6364
6365 tx_ring->next_to_use = i;
6366 }
6367
6368 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6369 u32 tx_flags, __be16 protocol)
6370 {
6371 struct ixgbe_q_vector *q_vector = ring->q_vector;
6372 union ixgbe_atr_hash_dword input = { .dword = 0 };
6373 union ixgbe_atr_hash_dword common = { .dword = 0 };
6374 union {
6375 unsigned char *network;
6376 struct iphdr *ipv4;
6377 struct ipv6hdr *ipv6;
6378 } hdr;
6379 struct tcphdr *th;
6380 __be16 vlan_id;
6381
6382 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6383 if (!q_vector)
6384 return;
6385
6386 /* do nothing if sampling is disabled */
6387 if (!ring->atr_sample_rate)
6388 return;
6389
6390 ring->atr_count++;
6391
6392 /* snag network header to get L4 type and address */
6393 hdr.network = skb_network_header(skb);
6394
6395 /* Currently only IPv4/IPv6 with TCP is supported */
6396 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6397 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6398 (protocol != __constant_htons(ETH_P_IP) ||
6399 hdr.ipv4->protocol != IPPROTO_TCP))
6400 return;
6401
6402 th = tcp_hdr(skb);
6403
6404 /* skip this packet since it is invalid or the socket is closing */
6405 if (!th || th->fin)
6406 return;
6407
6408 /* sample on all syn packets or once every atr sample count */
6409 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6410 return;
6411
6412 /* reset sample count */
6413 ring->atr_count = 0;
6414
6415 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6416
6417 /*
6418 * src and dst are inverted, think how the receiver sees them
6419 *
6420 * The input is broken into two sections, a non-compressed section
6421 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6422 * is XORed together and stored in the compressed dword.
6423 */
6424 input.formatted.vlan_id = vlan_id;
6425
6426 /*
6427 * since src port and flex bytes occupy the same word XOR them together
6428 * and write the value to source port portion of compressed dword
6429 */
6430 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6431 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6432 else
6433 common.port.src ^= th->dest ^ protocol;
6434 common.port.dst ^= th->source;
6435
6436 if (protocol == __constant_htons(ETH_P_IP)) {
6437 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6438 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6439 } else {
6440 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6441 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6442 hdr.ipv6->saddr.s6_addr32[1] ^
6443 hdr.ipv6->saddr.s6_addr32[2] ^
6444 hdr.ipv6->saddr.s6_addr32[3] ^
6445 hdr.ipv6->daddr.s6_addr32[0] ^
6446 hdr.ipv6->daddr.s6_addr32[1] ^
6447 hdr.ipv6->daddr.s6_addr32[2] ^
6448 hdr.ipv6->daddr.s6_addr32[3];
6449 }
6450
6451 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6452 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6453 input, common, ring->queue_index);
6454 }
6455
6456 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6457 {
6458 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6459 /* Herbert's original patch had:
6460 * smp_mb__after_netif_stop_queue();
6461 * but since that doesn't exist yet, just open code it. */
6462 smp_mb();
6463
6464 /* We need to check again in a case another CPU has just
6465 * made room available. */
6466 if (likely(ixgbe_desc_unused(tx_ring) < size))
6467 return -EBUSY;
6468
6469 /* A reprieve! - use start_queue because it doesn't call schedule */
6470 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6471 ++tx_ring->tx_stats.restart_queue;
6472 return 0;
6473 }
6474
6475 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6476 {
6477 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6478 return 0;
6479 return __ixgbe_maybe_stop_tx(tx_ring, size);
6480 }
6481
6482 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6483 {
6484 struct ixgbe_adapter *adapter = netdev_priv(dev);
6485 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6486 smp_processor_id();
6487 #ifdef IXGBE_FCOE
6488 __be16 protocol = vlan_get_protocol(skb);
6489
6490 if (((protocol == htons(ETH_P_FCOE)) ||
6491 (protocol == htons(ETH_P_FIP))) &&
6492 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6493 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6494 txq += adapter->ring_feature[RING_F_FCOE].mask;
6495 return txq;
6496 }
6497 #endif
6498
6499 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6500 while (unlikely(txq >= dev->real_num_tx_queues))
6501 txq -= dev->real_num_tx_queues;
6502 return txq;
6503 }
6504
6505 return skb_tx_hash(dev, skb);
6506 }
6507
6508 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6509 struct ixgbe_adapter *adapter,
6510 struct ixgbe_ring *tx_ring)
6511 {
6512 struct ixgbe_tx_buffer *first;
6513 int tso;
6514 u32 tx_flags = 0;
6515 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6516 unsigned short f;
6517 #endif
6518 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6519 __be16 protocol = skb->protocol;
6520 u8 hdr_len = 0;
6521
6522 /*
6523 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6524 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6525 * + 2 desc gap to keep tail from touching head,
6526 * + 1 desc for context descriptor,
6527 * otherwise try next time
6528 */
6529 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6530 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6531 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6532 #else
6533 count += skb_shinfo(skb)->nr_frags;
6534 #endif
6535 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6536 tx_ring->tx_stats.tx_busy++;
6537 return NETDEV_TX_BUSY;
6538 }
6539
6540 #ifdef CONFIG_PCI_IOV
6541 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6542 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6543
6544 #endif
6545 /* if we have a HW VLAN tag being added default to the HW one */
6546 if (vlan_tx_tag_present(skb)) {
6547 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6548 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6549 /* else if it is a SW VLAN check the next protocol and store the tag */
6550 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6551 struct vlan_hdr *vhdr, _vhdr;
6552 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6553 if (!vhdr)
6554 goto out_drop;
6555
6556 protocol = vhdr->h_vlan_encapsulated_proto;
6557 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6558 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6559 }
6560
6561 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6562 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6563 (skb->priority != TC_PRIO_CONTROL))) {
6564 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6565 tx_flags |= tx_ring->dcb_tc <<
6566 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6567 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6568 struct vlan_ethhdr *vhdr;
6569 if (skb_header_cloned(skb) &&
6570 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6571 goto out_drop;
6572 vhdr = (struct vlan_ethhdr *)skb->data;
6573 vhdr->h_vlan_TCI = htons(tx_flags >>
6574 IXGBE_TX_FLAGS_VLAN_SHIFT);
6575 } else {
6576 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6577 }
6578 }
6579
6580 /* record the location of the first descriptor for this packet */
6581 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6582
6583 #ifdef IXGBE_FCOE
6584 /* setup tx offload for FCoE */
6585 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6586 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6587 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6588 if (tso < 0)
6589 goto out_drop;
6590 else if (tso)
6591 tx_flags |= IXGBE_TX_FLAGS_FSO |
6592 IXGBE_TX_FLAGS_FCOE;
6593 else
6594 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6595
6596 goto xmit_fcoe;
6597 }
6598
6599 #endif /* IXGBE_FCOE */
6600 /* setup IPv4/IPv6 offloads */
6601 if (protocol == __constant_htons(ETH_P_IP))
6602 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6603
6604 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6605 if (tso < 0)
6606 goto out_drop;
6607 else if (tso)
6608 tx_flags |= IXGBE_TX_FLAGS_TSO;
6609 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6610 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6611
6612 /* add the ATR filter if ATR is on */
6613 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6614 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6615
6616 #ifdef IXGBE_FCOE
6617 xmit_fcoe:
6618 #endif /* IXGBE_FCOE */
6619 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6620
6621 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6622
6623 return NETDEV_TX_OK;
6624
6625 out_drop:
6626 dev_kfree_skb_any(skb);
6627 return NETDEV_TX_OK;
6628 }
6629
6630 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6631 {
6632 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6633 struct ixgbe_ring *tx_ring;
6634
6635 tx_ring = adapter->tx_ring[skb->queue_mapping];
6636 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6637 }
6638
6639 /**
6640 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6641 * @netdev: network interface device structure
6642 * @p: pointer to an address structure
6643 *
6644 * Returns 0 on success, negative on failure
6645 **/
6646 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6647 {
6648 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6649 struct ixgbe_hw *hw = &adapter->hw;
6650 struct sockaddr *addr = p;
6651
6652 if (!is_valid_ether_addr(addr->sa_data))
6653 return -EADDRNOTAVAIL;
6654
6655 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6656 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6657
6658 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6659 IXGBE_RAH_AV);
6660
6661 return 0;
6662 }
6663
6664 static int
6665 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6666 {
6667 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6668 struct ixgbe_hw *hw = &adapter->hw;
6669 u16 value;
6670 int rc;
6671
6672 if (prtad != hw->phy.mdio.prtad)
6673 return -EINVAL;
6674 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6675 if (!rc)
6676 rc = value;
6677 return rc;
6678 }
6679
6680 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6681 u16 addr, u16 value)
6682 {
6683 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6684 struct ixgbe_hw *hw = &adapter->hw;
6685
6686 if (prtad != hw->phy.mdio.prtad)
6687 return -EINVAL;
6688 return hw->phy.ops.write_reg(hw, addr, devad, value);
6689 }
6690
6691 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6692 {
6693 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6694
6695 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6696 }
6697
6698 /**
6699 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6700 * netdev->dev_addrs
6701 * @netdev: network interface device structure
6702 *
6703 * Returns non-zero on failure
6704 **/
6705 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6706 {
6707 int err = 0;
6708 struct ixgbe_adapter *adapter = netdev_priv(dev);
6709 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6710
6711 if (is_valid_ether_addr(mac->san_addr)) {
6712 rtnl_lock();
6713 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6714 rtnl_unlock();
6715 }
6716 return err;
6717 }
6718
6719 /**
6720 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6721 * netdev->dev_addrs
6722 * @netdev: network interface device structure
6723 *
6724 * Returns non-zero on failure
6725 **/
6726 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6727 {
6728 int err = 0;
6729 struct ixgbe_adapter *adapter = netdev_priv(dev);
6730 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6731
6732 if (is_valid_ether_addr(mac->san_addr)) {
6733 rtnl_lock();
6734 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6735 rtnl_unlock();
6736 }
6737 return err;
6738 }
6739
6740 #ifdef CONFIG_NET_POLL_CONTROLLER
6741 /*
6742 * Polling 'interrupt' - used by things like netconsole to send skbs
6743 * without having to re-enable interrupts. It's not called while
6744 * the interrupt routine is executing.
6745 */
6746 static void ixgbe_netpoll(struct net_device *netdev)
6747 {
6748 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6749 int i;
6750
6751 /* if interface is down do nothing */
6752 if (test_bit(__IXGBE_DOWN, &adapter->state))
6753 return;
6754
6755 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6756 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6757 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6758 for (i = 0; i < num_q_vectors; i++) {
6759 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6760 ixgbe_msix_clean_rings(0, q_vector);
6761 }
6762 } else {
6763 ixgbe_intr(adapter->pdev->irq, netdev);
6764 }
6765 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6766 }
6767 #endif
6768
6769 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6770 struct rtnl_link_stats64 *stats)
6771 {
6772 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6773 int i;
6774
6775 rcu_read_lock();
6776 for (i = 0; i < adapter->num_rx_queues; i++) {
6777 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6778 u64 bytes, packets;
6779 unsigned int start;
6780
6781 if (ring) {
6782 do {
6783 start = u64_stats_fetch_begin_bh(&ring->syncp);
6784 packets = ring->stats.packets;
6785 bytes = ring->stats.bytes;
6786 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6787 stats->rx_packets += packets;
6788 stats->rx_bytes += bytes;
6789 }
6790 }
6791
6792 for (i = 0; i < adapter->num_tx_queues; i++) {
6793 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6794 u64 bytes, packets;
6795 unsigned int start;
6796
6797 if (ring) {
6798 do {
6799 start = u64_stats_fetch_begin_bh(&ring->syncp);
6800 packets = ring->stats.packets;
6801 bytes = ring->stats.bytes;
6802 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6803 stats->tx_packets += packets;
6804 stats->tx_bytes += bytes;
6805 }
6806 }
6807 rcu_read_unlock();
6808 /* following stats updated by ixgbe_watchdog_task() */
6809 stats->multicast = netdev->stats.multicast;
6810 stats->rx_errors = netdev->stats.rx_errors;
6811 stats->rx_length_errors = netdev->stats.rx_length_errors;
6812 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6813 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6814 return stats;
6815 }
6816
6817 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6818 * #adapter: pointer to ixgbe_adapter
6819 * @tc: number of traffic classes currently enabled
6820 *
6821 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6822 * 802.1Q priority maps to a packet buffer that exists.
6823 */
6824 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6825 {
6826 struct ixgbe_hw *hw = &adapter->hw;
6827 u32 reg, rsave;
6828 int i;
6829
6830 /* 82598 have a static priority to TC mapping that can not
6831 * be changed so no validation is needed.
6832 */
6833 if (hw->mac.type == ixgbe_mac_82598EB)
6834 return;
6835
6836 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6837 rsave = reg;
6838
6839 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6840 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6841
6842 /* If up2tc is out of bounds default to zero */
6843 if (up2tc > tc)
6844 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6845 }
6846
6847 if (reg != rsave)
6848 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6849
6850 return;
6851 }
6852
6853
6854 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6855 * classes.
6856 *
6857 * @netdev: net device to configure
6858 * @tc: number of traffic classes to enable
6859 */
6860 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6861 {
6862 struct ixgbe_adapter *adapter = netdev_priv(dev);
6863 struct ixgbe_hw *hw = &adapter->hw;
6864
6865 /* Multiple traffic classes requires multiple queues */
6866 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6867 e_err(drv, "Enable failed, needs MSI-X\n");
6868 return -EINVAL;
6869 }
6870
6871 /* Hardware supports up to 8 traffic classes */
6872 if (tc > MAX_TRAFFIC_CLASS ||
6873 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
6874 return -EINVAL;
6875
6876 /* Hardware has to reinitialize queues and interrupts to
6877 * match packet buffer alignment. Unfortunantly, the
6878 * hardware is not flexible enough to do this dynamically.
6879 */
6880 if (netif_running(dev))
6881 ixgbe_close(dev);
6882 ixgbe_clear_interrupt_scheme(adapter);
6883
6884 if (tc) {
6885 netdev_set_num_tc(dev, tc);
6886 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
6887
6888 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6889 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6890
6891 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6892 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6893 } else {
6894 netdev_reset_tc(dev);
6895
6896 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6897
6898 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6899 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6900
6901 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6902 adapter->dcb_cfg.pfc_mode_enable = false;
6903 }
6904
6905 ixgbe_init_interrupt_scheme(adapter);
6906 ixgbe_validate_rtr(adapter, tc);
6907 if (netif_running(dev))
6908 ixgbe_open(dev);
6909
6910 return 0;
6911 }
6912
6913 void ixgbe_do_reset(struct net_device *netdev)
6914 {
6915 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6916
6917 if (netif_running(netdev))
6918 ixgbe_reinit_locked(adapter);
6919 else
6920 ixgbe_reset(adapter);
6921 }
6922
6923 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
6924 {
6925 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6926
6927 #ifdef CONFIG_DCB
6928 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6929 data &= ~NETIF_F_HW_VLAN_RX;
6930 #endif
6931
6932 /* return error if RXHASH is being enabled when RSS is not supported */
6933 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6934 data &= ~NETIF_F_RXHASH;
6935
6936 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6937 if (!(data & NETIF_F_RXCSUM))
6938 data &= ~NETIF_F_LRO;
6939
6940 /* Turn off LRO if not RSC capable or invalid ITR settings */
6941 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
6942 data &= ~NETIF_F_LRO;
6943 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
6944 (adapter->rx_itr_setting != 1 &&
6945 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
6946 data &= ~NETIF_F_LRO;
6947 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
6948 }
6949
6950 return data;
6951 }
6952
6953 static int ixgbe_set_features(struct net_device *netdev, u32 data)
6954 {
6955 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6956 bool need_reset = false;
6957
6958 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6959 if (!(data & NETIF_F_RXCSUM))
6960 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
6961 else
6962 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
6963
6964 /* Make sure RSC matches LRO, reset if change */
6965 if (!!(data & NETIF_F_LRO) !=
6966 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6967 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
6968 switch (adapter->hw.mac.type) {
6969 case ixgbe_mac_X540:
6970 case ixgbe_mac_82599EB:
6971 need_reset = true;
6972 break;
6973 default:
6974 break;
6975 }
6976 }
6977
6978 /*
6979 * Check if Flow Director n-tuple support was enabled or disabled. If
6980 * the state changed, we need to reset.
6981 */
6982 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6983 /* turn off ATR, enable perfect filters and reset */
6984 if (data & NETIF_F_NTUPLE) {
6985 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6986 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6987 need_reset = true;
6988 }
6989 } else if (!(data & NETIF_F_NTUPLE)) {
6990 /* turn off Flow Director, set ATR and reset */
6991 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6992 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
6993 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
6994 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6995 need_reset = true;
6996 }
6997
6998 if (need_reset)
6999 ixgbe_do_reset(netdev);
7000
7001 return 0;
7002
7003 }
7004
7005 static const struct net_device_ops ixgbe_netdev_ops = {
7006 .ndo_open = ixgbe_open,
7007 .ndo_stop = ixgbe_close,
7008 .ndo_start_xmit = ixgbe_xmit_frame,
7009 .ndo_select_queue = ixgbe_select_queue,
7010 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7011 .ndo_validate_addr = eth_validate_addr,
7012 .ndo_set_mac_address = ixgbe_set_mac,
7013 .ndo_change_mtu = ixgbe_change_mtu,
7014 .ndo_tx_timeout = ixgbe_tx_timeout,
7015 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7016 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7017 .ndo_do_ioctl = ixgbe_ioctl,
7018 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7019 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7020 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7021 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7022 .ndo_get_stats64 = ixgbe_get_stats64,
7023 .ndo_setup_tc = ixgbe_setup_tc,
7024 #ifdef CONFIG_NET_POLL_CONTROLLER
7025 .ndo_poll_controller = ixgbe_netpoll,
7026 #endif
7027 #ifdef IXGBE_FCOE
7028 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7029 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7030 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7031 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7032 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7033 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7034 #endif /* IXGBE_FCOE */
7035 .ndo_set_features = ixgbe_set_features,
7036 .ndo_fix_features = ixgbe_fix_features,
7037 };
7038
7039 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7040 const struct ixgbe_info *ii)
7041 {
7042 #ifdef CONFIG_PCI_IOV
7043 struct ixgbe_hw *hw = &adapter->hw;
7044 int err;
7045 int num_vf_macvlans, i;
7046 struct vf_macvlans *mv_list;
7047
7048 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7049 return;
7050
7051 /* The 82599 supports up to 64 VFs per physical function
7052 * but this implementation limits allocation to 63 so that
7053 * basic networking resources are still available to the
7054 * physical function
7055 */
7056 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7057 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7058 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7059 if (err) {
7060 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7061 goto err_novfs;
7062 }
7063
7064 num_vf_macvlans = hw->mac.num_rar_entries -
7065 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7066
7067 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7068 sizeof(struct vf_macvlans),
7069 GFP_KERNEL);
7070 if (mv_list) {
7071 /* Initialize list of VF macvlans */
7072 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7073 for (i = 0; i < num_vf_macvlans; i++) {
7074 mv_list->vf = -1;
7075 mv_list->free = true;
7076 mv_list->rar_entry = hw->mac.num_rar_entries -
7077 (i + adapter->num_vfs + 1);
7078 list_add(&mv_list->l, &adapter->vf_mvs.l);
7079 mv_list++;
7080 }
7081 }
7082
7083 /* If call to enable VFs succeeded then allocate memory
7084 * for per VF control structures.
7085 */
7086 adapter->vfinfo =
7087 kcalloc(adapter->num_vfs,
7088 sizeof(struct vf_data_storage), GFP_KERNEL);
7089 if (adapter->vfinfo) {
7090 /* Now that we're sure SR-IOV is enabled
7091 * and memory allocated set up the mailbox parameters
7092 */
7093 ixgbe_init_mbx_params_pf(hw);
7094 memcpy(&hw->mbx.ops, ii->mbx_ops,
7095 sizeof(hw->mbx.ops));
7096
7097 /* Disable RSC when in SR-IOV mode */
7098 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7099 IXGBE_FLAG2_RSC_ENABLED);
7100 return;
7101 }
7102
7103 /* Oh oh */
7104 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7105 "SRIOV disabled\n");
7106 pci_disable_sriov(adapter->pdev);
7107
7108 err_novfs:
7109 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7110 adapter->num_vfs = 0;
7111 #endif /* CONFIG_PCI_IOV */
7112 }
7113
7114 /**
7115 * ixgbe_probe - Device Initialization Routine
7116 * @pdev: PCI device information struct
7117 * @ent: entry in ixgbe_pci_tbl
7118 *
7119 * Returns 0 on success, negative on failure
7120 *
7121 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7122 * The OS initialization, configuring of the adapter private structure,
7123 * and a hardware reset occur.
7124 **/
7125 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7126 const struct pci_device_id *ent)
7127 {
7128 struct net_device *netdev;
7129 struct ixgbe_adapter *adapter = NULL;
7130 struct ixgbe_hw *hw;
7131 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7132 static int cards_found;
7133 int i, err, pci_using_dac;
7134 u8 part_str[IXGBE_PBANUM_LENGTH];
7135 unsigned int indices = num_possible_cpus();
7136 #ifdef IXGBE_FCOE
7137 u16 device_caps;
7138 #endif
7139 u32 eec;
7140
7141 /* Catch broken hardware that put the wrong VF device ID in
7142 * the PCIe SR-IOV capability.
7143 */
7144 if (pdev->is_virtfn) {
7145 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7146 pci_name(pdev), pdev->vendor, pdev->device);
7147 return -EINVAL;
7148 }
7149
7150 err = pci_enable_device_mem(pdev);
7151 if (err)
7152 return err;
7153
7154 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7155 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7156 pci_using_dac = 1;
7157 } else {
7158 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7159 if (err) {
7160 err = dma_set_coherent_mask(&pdev->dev,
7161 DMA_BIT_MASK(32));
7162 if (err) {
7163 dev_err(&pdev->dev,
7164 "No usable DMA configuration, aborting\n");
7165 goto err_dma;
7166 }
7167 }
7168 pci_using_dac = 0;
7169 }
7170
7171 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7172 IORESOURCE_MEM), ixgbe_driver_name);
7173 if (err) {
7174 dev_err(&pdev->dev,
7175 "pci_request_selected_regions failed 0x%x\n", err);
7176 goto err_pci_reg;
7177 }
7178
7179 pci_enable_pcie_error_reporting(pdev);
7180
7181 pci_set_master(pdev);
7182 pci_save_state(pdev);
7183
7184 #ifdef CONFIG_IXGBE_DCB
7185 indices *= MAX_TRAFFIC_CLASS;
7186 #endif
7187
7188 if (ii->mac == ixgbe_mac_82598EB)
7189 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7190 else
7191 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7192
7193 #ifdef IXGBE_FCOE
7194 indices += min_t(unsigned int, num_possible_cpus(),
7195 IXGBE_MAX_FCOE_INDICES);
7196 #endif
7197 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7198 if (!netdev) {
7199 err = -ENOMEM;
7200 goto err_alloc_etherdev;
7201 }
7202
7203 SET_NETDEV_DEV(netdev, &pdev->dev);
7204
7205 adapter = netdev_priv(netdev);
7206 pci_set_drvdata(pdev, adapter);
7207
7208 adapter->netdev = netdev;
7209 adapter->pdev = pdev;
7210 hw = &adapter->hw;
7211 hw->back = adapter;
7212 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7213
7214 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7215 pci_resource_len(pdev, 0));
7216 if (!hw->hw_addr) {
7217 err = -EIO;
7218 goto err_ioremap;
7219 }
7220
7221 for (i = 1; i <= 5; i++) {
7222 if (pci_resource_len(pdev, i) == 0)
7223 continue;
7224 }
7225
7226 netdev->netdev_ops = &ixgbe_netdev_ops;
7227 ixgbe_set_ethtool_ops(netdev);
7228 netdev->watchdog_timeo = 5 * HZ;
7229 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7230
7231 adapter->bd_number = cards_found;
7232
7233 /* Setup hw api */
7234 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7235 hw->mac.type = ii->mac;
7236
7237 /* EEPROM */
7238 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7239 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7240 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7241 if (!(eec & (1 << 8)))
7242 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7243
7244 /* PHY */
7245 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7246 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7247 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7248 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7249 hw->phy.mdio.mmds = 0;
7250 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7251 hw->phy.mdio.dev = netdev;
7252 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7253 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7254
7255 ii->get_invariants(hw);
7256
7257 /* setup the private structure */
7258 err = ixgbe_sw_init(adapter);
7259 if (err)
7260 goto err_sw_init;
7261
7262 /* Make it possible the adapter to be woken up via WOL */
7263 switch (adapter->hw.mac.type) {
7264 case ixgbe_mac_82599EB:
7265 case ixgbe_mac_X540:
7266 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7267 break;
7268 default:
7269 break;
7270 }
7271
7272 /*
7273 * If there is a fan on this device and it has failed log the
7274 * failure.
7275 */
7276 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7277 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7278 if (esdp & IXGBE_ESDP_SDP1)
7279 e_crit(probe, "Fan has stopped, replace the adapter\n");
7280 }
7281
7282 /* reset_hw fills in the perm_addr as well */
7283 hw->phy.reset_if_overtemp = true;
7284 err = hw->mac.ops.reset_hw(hw);
7285 hw->phy.reset_if_overtemp = false;
7286 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7287 hw->mac.type == ixgbe_mac_82598EB) {
7288 err = 0;
7289 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7290 e_dev_err("failed to load because an unsupported SFP+ "
7291 "module type was detected.\n");
7292 e_dev_err("Reload the driver after installing a supported "
7293 "module.\n");
7294 goto err_sw_init;
7295 } else if (err) {
7296 e_dev_err("HW Init failed: %d\n", err);
7297 goto err_sw_init;
7298 }
7299
7300 ixgbe_probe_vf(adapter, ii);
7301
7302 netdev->features = NETIF_F_SG |
7303 NETIF_F_IP_CSUM |
7304 NETIF_F_IPV6_CSUM |
7305 NETIF_F_HW_VLAN_TX |
7306 NETIF_F_HW_VLAN_RX |
7307 NETIF_F_HW_VLAN_FILTER |
7308 NETIF_F_TSO |
7309 NETIF_F_TSO6 |
7310 NETIF_F_RXHASH |
7311 NETIF_F_RXCSUM;
7312
7313 netdev->hw_features = netdev->features;
7314
7315 switch (adapter->hw.mac.type) {
7316 case ixgbe_mac_82599EB:
7317 case ixgbe_mac_X540:
7318 netdev->features |= NETIF_F_SCTP_CSUM;
7319 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7320 NETIF_F_NTUPLE;
7321 break;
7322 default:
7323 break;
7324 }
7325
7326 netdev->vlan_features |= NETIF_F_TSO;
7327 netdev->vlan_features |= NETIF_F_TSO6;
7328 netdev->vlan_features |= NETIF_F_IP_CSUM;
7329 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7330 netdev->vlan_features |= NETIF_F_SG;
7331
7332 netdev->priv_flags |= IFF_UNICAST_FLT;
7333
7334 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7335 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7336 IXGBE_FLAG_DCB_ENABLED);
7337
7338 #ifdef CONFIG_IXGBE_DCB
7339 netdev->dcbnl_ops = &dcbnl_ops;
7340 #endif
7341
7342 #ifdef IXGBE_FCOE
7343 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7344 if (hw->mac.ops.get_device_caps) {
7345 hw->mac.ops.get_device_caps(hw, &device_caps);
7346 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7347 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7348 }
7349 }
7350 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7351 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7352 netdev->vlan_features |= NETIF_F_FSO;
7353 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7354 }
7355 #endif /* IXGBE_FCOE */
7356 if (pci_using_dac) {
7357 netdev->features |= NETIF_F_HIGHDMA;
7358 netdev->vlan_features |= NETIF_F_HIGHDMA;
7359 }
7360
7361 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7362 netdev->hw_features |= NETIF_F_LRO;
7363 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7364 netdev->features |= NETIF_F_LRO;
7365
7366 /* make sure the EEPROM is good */
7367 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7368 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7369 err = -EIO;
7370 goto err_eeprom;
7371 }
7372
7373 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7374 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7375
7376 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7377 e_dev_err("invalid MAC address\n");
7378 err = -EIO;
7379 goto err_eeprom;
7380 }
7381
7382 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7383 if (hw->mac.ops.disable_tx_laser &&
7384 ((hw->phy.multispeed_fiber) ||
7385 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7386 (hw->mac.type == ixgbe_mac_82599EB))))
7387 hw->mac.ops.disable_tx_laser(hw);
7388
7389 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7390 (unsigned long) adapter);
7391
7392 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7393 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7394
7395 err = ixgbe_init_interrupt_scheme(adapter);
7396 if (err)
7397 goto err_sw_init;
7398
7399 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7400 netdev->hw_features &= ~NETIF_F_RXHASH;
7401 netdev->features &= ~NETIF_F_RXHASH;
7402 }
7403
7404 switch (pdev->device) {
7405 case IXGBE_DEV_ID_82599_SFP:
7406 /* Only this subdevice supports WOL */
7407 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7408 adapter->wol = IXGBE_WUFC_MAG;
7409 break;
7410 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7411 /* All except this subdevice support WOL */
7412 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7413 adapter->wol = IXGBE_WUFC_MAG;
7414 break;
7415 case IXGBE_DEV_ID_82599_KX4:
7416 adapter->wol = IXGBE_WUFC_MAG;
7417 break;
7418 default:
7419 adapter->wol = 0;
7420 break;
7421 }
7422 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7423
7424 /* pick up the PCI bus settings for reporting later */
7425 hw->mac.ops.get_bus_info(hw);
7426
7427 /* print bus type/speed/width info */
7428 e_dev_info("(PCI Express:%s:%s) %pM\n",
7429 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7430 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7431 "Unknown"),
7432 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7433 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7434 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7435 "Unknown"),
7436 netdev->dev_addr);
7437
7438 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7439 if (err)
7440 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7441 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7442 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7443 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7444 part_str);
7445 else
7446 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7447 hw->mac.type, hw->phy.type, part_str);
7448
7449 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7450 e_dev_warn("PCI-Express bandwidth available for this card is "
7451 "not sufficient for optimal performance.\n");
7452 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7453 "is required.\n");
7454 }
7455
7456 /* save off EEPROM version number */
7457 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7458
7459 /* reset the hardware with the new settings */
7460 err = hw->mac.ops.start_hw(hw);
7461
7462 if (err == IXGBE_ERR_EEPROM_VERSION) {
7463 /* We are running on a pre-production device, log a warning */
7464 e_dev_warn("This device is a pre-production adapter/LOM. "
7465 "Please be aware there may be issues associated "
7466 "with your hardware. If you are experiencing "
7467 "problems please contact your Intel or hardware "
7468 "representative who provided you with this "
7469 "hardware.\n");
7470 }
7471 strcpy(netdev->name, "eth%d");
7472 err = register_netdev(netdev);
7473 if (err)
7474 goto err_register;
7475
7476 /* carrier off reporting is important to ethtool even BEFORE open */
7477 netif_carrier_off(netdev);
7478
7479 #ifdef CONFIG_IXGBE_DCA
7480 if (dca_add_requester(&pdev->dev) == 0) {
7481 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7482 ixgbe_setup_dca(adapter);
7483 }
7484 #endif
7485 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7486 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7487 for (i = 0; i < adapter->num_vfs; i++)
7488 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7489 }
7490
7491 /* Inform firmware of driver version */
7492 if (hw->mac.ops.set_fw_drv_ver)
7493 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7494 FW_CEM_UNUSED_VER);
7495
7496 /* add san mac addr to netdev */
7497 ixgbe_add_sanmac_netdev(netdev);
7498
7499 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7500 cards_found++;
7501 return 0;
7502
7503 err_register:
7504 ixgbe_release_hw_control(adapter);
7505 ixgbe_clear_interrupt_scheme(adapter);
7506 err_sw_init:
7507 err_eeprom:
7508 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7509 ixgbe_disable_sriov(adapter);
7510 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7511 iounmap(hw->hw_addr);
7512 err_ioremap:
7513 free_netdev(netdev);
7514 err_alloc_etherdev:
7515 pci_release_selected_regions(pdev,
7516 pci_select_bars(pdev, IORESOURCE_MEM));
7517 err_pci_reg:
7518 err_dma:
7519 pci_disable_device(pdev);
7520 return err;
7521 }
7522
7523 /**
7524 * ixgbe_remove - Device Removal Routine
7525 * @pdev: PCI device information struct
7526 *
7527 * ixgbe_remove is called by the PCI subsystem to alert the driver
7528 * that it should release a PCI device. The could be caused by a
7529 * Hot-Plug event, or because the driver is going to be removed from
7530 * memory.
7531 **/
7532 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7533 {
7534 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7535 struct net_device *netdev = adapter->netdev;
7536
7537 set_bit(__IXGBE_DOWN, &adapter->state);
7538 cancel_work_sync(&adapter->service_task);
7539
7540 #ifdef CONFIG_IXGBE_DCA
7541 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7542 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7543 dca_remove_requester(&pdev->dev);
7544 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7545 }
7546
7547 #endif
7548 #ifdef IXGBE_FCOE
7549 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7550 ixgbe_cleanup_fcoe(adapter);
7551
7552 #endif /* IXGBE_FCOE */
7553
7554 /* remove the added san mac */
7555 ixgbe_del_sanmac_netdev(netdev);
7556
7557 if (netdev->reg_state == NETREG_REGISTERED)
7558 unregister_netdev(netdev);
7559
7560 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7561 ixgbe_disable_sriov(adapter);
7562
7563 ixgbe_clear_interrupt_scheme(adapter);
7564
7565 ixgbe_release_hw_control(adapter);
7566
7567 iounmap(adapter->hw.hw_addr);
7568 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7569 IORESOURCE_MEM));
7570
7571 e_dev_info("complete\n");
7572
7573 free_netdev(netdev);
7574
7575 pci_disable_pcie_error_reporting(pdev);
7576
7577 pci_disable_device(pdev);
7578 }
7579
7580 /**
7581 * ixgbe_io_error_detected - called when PCI error is detected
7582 * @pdev: Pointer to PCI device
7583 * @state: The current pci connection state
7584 *
7585 * This function is called after a PCI bus error affecting
7586 * this device has been detected.
7587 */
7588 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7589 pci_channel_state_t state)
7590 {
7591 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7592 struct net_device *netdev = adapter->netdev;
7593
7594 netif_device_detach(netdev);
7595
7596 if (state == pci_channel_io_perm_failure)
7597 return PCI_ERS_RESULT_DISCONNECT;
7598
7599 if (netif_running(netdev))
7600 ixgbe_down(adapter);
7601 pci_disable_device(pdev);
7602
7603 /* Request a slot reset. */
7604 return PCI_ERS_RESULT_NEED_RESET;
7605 }
7606
7607 /**
7608 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7609 * @pdev: Pointer to PCI device
7610 *
7611 * Restart the card from scratch, as if from a cold-boot.
7612 */
7613 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7614 {
7615 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7616 pci_ers_result_t result;
7617 int err;
7618
7619 if (pci_enable_device_mem(pdev)) {
7620 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7621 result = PCI_ERS_RESULT_DISCONNECT;
7622 } else {
7623 pci_set_master(pdev);
7624 pci_restore_state(pdev);
7625 pci_save_state(pdev);
7626
7627 pci_wake_from_d3(pdev, false);
7628
7629 ixgbe_reset(adapter);
7630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7631 result = PCI_ERS_RESULT_RECOVERED;
7632 }
7633
7634 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7635 if (err) {
7636 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7637 "failed 0x%0x\n", err);
7638 /* non-fatal, continue */
7639 }
7640
7641 return result;
7642 }
7643
7644 /**
7645 * ixgbe_io_resume - called when traffic can start flowing again.
7646 * @pdev: Pointer to PCI device
7647 *
7648 * This callback is called when the error recovery driver tells us that
7649 * its OK to resume normal operation.
7650 */
7651 static void ixgbe_io_resume(struct pci_dev *pdev)
7652 {
7653 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7654 struct net_device *netdev = adapter->netdev;
7655
7656 if (netif_running(netdev)) {
7657 if (ixgbe_up(adapter)) {
7658 e_info(probe, "ixgbe_up failed after reset\n");
7659 return;
7660 }
7661 }
7662
7663 netif_device_attach(netdev);
7664 }
7665
7666 static struct pci_error_handlers ixgbe_err_handler = {
7667 .error_detected = ixgbe_io_error_detected,
7668 .slot_reset = ixgbe_io_slot_reset,
7669 .resume = ixgbe_io_resume,
7670 };
7671
7672 static struct pci_driver ixgbe_driver = {
7673 .name = ixgbe_driver_name,
7674 .id_table = ixgbe_pci_tbl,
7675 .probe = ixgbe_probe,
7676 .remove = __devexit_p(ixgbe_remove),
7677 #ifdef CONFIG_PM
7678 .suspend = ixgbe_suspend,
7679 .resume = ixgbe_resume,
7680 #endif
7681 .shutdown = ixgbe_shutdown,
7682 .err_handler = &ixgbe_err_handler
7683 };
7684
7685 /**
7686 * ixgbe_init_module - Driver Registration Routine
7687 *
7688 * ixgbe_init_module is the first routine called when the driver is
7689 * loaded. All it does is register with the PCI subsystem.
7690 **/
7691 static int __init ixgbe_init_module(void)
7692 {
7693 int ret;
7694 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7695 pr_info("%s\n", ixgbe_copyright);
7696
7697 #ifdef CONFIG_IXGBE_DCA
7698 dca_register_notify(&dca_notifier);
7699 #endif
7700
7701 ret = pci_register_driver(&ixgbe_driver);
7702 return ret;
7703 }
7704
7705 module_init(ixgbe_init_module);
7706
7707 /**
7708 * ixgbe_exit_module - Driver Exit Cleanup Routine
7709 *
7710 * ixgbe_exit_module is called just before the driver is removed
7711 * from memory.
7712 **/
7713 static void __exit ixgbe_exit_module(void)
7714 {
7715 #ifdef CONFIG_IXGBE_DCA
7716 dca_unregister_notify(&dca_notifier);
7717 #endif
7718 pci_unregister_driver(&ixgbe_driver);
7719 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7720 }
7721
7722 #ifdef CONFIG_IXGBE_DCA
7723 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7724 void *p)
7725 {
7726 int ret_val;
7727
7728 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7729 __ixgbe_notify_dca);
7730
7731 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7732 }
7733
7734 #endif /* CONFIG_IXGBE_DCA */
7735
7736 module_exit(ixgbe_exit_module);
7737
7738 /* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)