1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
29 /* Linux PRO/1000 Ethernet Driver main header file */
34 #include "e1000_mac.h"
35 #include "e1000_82575.h"
37 #include <linux/clocksource.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/bitops.h>
41 #include <linux/if_vlan.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
47 #define E1000_PCS_CFG_IGN_SD 1
49 /* Interrupt defines */
50 #define IGB_START_ITR 648 /* ~6000 ints/sec */
51 #define IGB_4K_ITR 980
52 #define IGB_20K_ITR 196
53 #define IGB_70K_ITR 56
55 /* TX/RX descriptor defines */
56 #define IGB_DEFAULT_TXD 256
57 #define IGB_DEFAULT_TX_WORK 128
58 #define IGB_MIN_TXD 80
59 #define IGB_MAX_TXD 4096
61 #define IGB_DEFAULT_RXD 256
62 #define IGB_MIN_RXD 80
63 #define IGB_MAX_RXD 4096
65 #define IGB_DEFAULT_ITR 3 /* dynamic */
66 #define IGB_MAX_ITR_USECS 10000
67 #define IGB_MIN_ITR_USECS 10
68 #define NON_Q_VECTORS 1
69 #define MAX_Q_VECTORS 8
71 /* Transmit and receive queues */
72 #define IGB_MAX_RX_QUEUES 8
73 #define IGB_MAX_RX_QUEUES_82575 4
74 #define IGB_MAX_RX_QUEUES_I211 2
75 #define IGB_MAX_TX_QUEUES 8
76 #define IGB_MAX_VF_MC_ENTRIES 30
77 #define IGB_MAX_VF_FUNCTIONS 8
78 #define IGB_MAX_VFTA_ENTRIES 128
79 #define IGB_82576_VF_DEV_ID 0x10CA
80 #define IGB_I350_VF_DEV_ID 0x1520
82 /* NVM version defines */
83 #define IGB_MAJOR_MASK 0xF000
84 #define IGB_MINOR_MASK 0x0FF0
85 #define IGB_BUILD_MASK 0x000F
86 #define IGB_COMB_VER_MASK 0x00FF
87 #define IGB_MAJOR_SHIFT 12
88 #define IGB_MINOR_SHIFT 4
89 #define IGB_COMB_VER_SHFT 8
90 #define IGB_NVM_VER_INVALID 0xFFFF
91 #define IGB_ETRACK_SHIFT 16
92 #define NVM_ETRACK_WORD 0x0042
93 #define NVM_COMB_VER_OFF 0x0083
94 #define NVM_COMB_VER_PTR 0x003d
96 struct vf_data_storage
{
97 unsigned char vf_mac_addresses
[ETH_ALEN
];
98 u16 vf_mc_hashes
[IGB_MAX_VF_MC_ENTRIES
];
102 unsigned long last_nack
;
103 u16 pf_vlan
; /* When set, guest VLAN config not allowed. */
106 bool spoofchk_enabled
;
109 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
110 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
111 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
112 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
114 /* RX descriptor control thresholds.
115 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
116 * descriptors available in its onboard memory.
117 * Setting this to 0 disables RX descriptor prefetch.
118 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
119 * available in host memory.
120 * If PTHRESH is 0, this should also be 0.
121 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
122 * descriptors until either it has this many to write back, or the
125 #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
126 #define IGB_RX_HTHRESH 8
127 #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
128 #define IGB_TX_HTHRESH 1
129 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
130 adapter->msix_entries) ? 1 : 4)
131 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
132 adapter->msix_entries) ? 1 : 16)
134 /* this is the size past which hardware will drop packets when setting LPE=0 */
135 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
137 /* Supported Rx Buffer Sizes */
138 #define IGB_RXBUFFER_256 256
139 #define IGB_RXBUFFER_2048 2048
140 #define IGB_RX_HDR_LEN IGB_RXBUFFER_256
141 #define IGB_RX_BUFSZ IGB_RXBUFFER_2048
143 /* How many Rx Buffers do we bundle into one write to the hardware ? */
144 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
146 #define AUTO_ALL_MODES 0
147 #define IGB_EEPROM_APME 0x0400
149 #ifndef IGB_MASTER_SLAVE
150 /* Switch to override PHY master/slave setting */
151 #define IGB_MASTER_SLAVE e1000_ms_hw_default
154 #define IGB_MNG_VLAN_NONE -1
158 IGB_TX_FLAGS_VLAN
= 0x01,
159 IGB_TX_FLAGS_TSO
= 0x02,
160 IGB_TX_FLAGS_TSTAMP
= 0x04,
163 IGB_TX_FLAGS_IPV4
= 0x10,
164 IGB_TX_FLAGS_CSUM
= 0x20,
168 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
169 #define IGB_TX_FLAGS_VLAN_SHIFT 16
171 /* The largest size we can write to the descriptor is 65535. In order to
172 * maintain a power of two alignment we have to limit ourselves to 32K.
174 #define IGB_MAX_TXD_PWR 15
175 #define IGB_MAX_DATA_PER_TXD (1 << IGB_MAX_TXD_PWR)
177 /* Tx Descriptors needed, worst case */
178 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
179 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
181 /* EEPROM byte offsets */
182 #define IGB_SFF_8472_SWAP 0x5C
183 #define IGB_SFF_8472_COMP 0x5E
186 #define IGB_SFF_ADDRESSING_MODE 0x4
187 #define IGB_SFF_8472_UNSUP 0x00
189 /* wrapper around a pointer to a socket buffer,
190 * so a DMA handle can be stored along with the buffer
192 struct igb_tx_buffer
{
193 union e1000_adv_tx_desc
*next_to_watch
;
194 unsigned long time_stamp
;
196 unsigned int bytecount
;
199 DEFINE_DMA_UNMAP_ADDR(dma
);
200 DEFINE_DMA_UNMAP_LEN(len
);
204 struct igb_rx_buffer
{
207 unsigned int page_offset
;
210 struct igb_tx_queue_stats
{
217 struct igb_rx_queue_stats
{
225 struct igb_ring_container
{
226 struct igb_ring
*ring
; /* pointer to linked list of rings */
227 unsigned int total_bytes
; /* total bytes processed this int */
228 unsigned int total_packets
; /* total packets processed this int */
229 u16 work_limit
; /* total work allowed per interrupt */
230 u8 count
; /* total number of rings in vector */
231 u8 itr
; /* current ITR setting for ring */
235 struct igb_q_vector
*q_vector
; /* backlink to q_vector */
236 struct net_device
*netdev
; /* back pointer to net_device */
237 struct device
*dev
; /* device pointer for dma mapping */
238 union { /* array of buffer info structs */
239 struct igb_tx_buffer
*tx_buffer_info
;
240 struct igb_rx_buffer
*rx_buffer_info
;
242 unsigned long last_rx_timestamp
;
243 void *desc
; /* descriptor ring memory */
244 unsigned long flags
; /* ring specific flags */
245 void __iomem
*tail
; /* pointer to ring tail register */
246 dma_addr_t dma
; /* phys address of the ring */
247 unsigned int size
; /* length of desc. ring in bytes */
249 u16 count
; /* number of desc. in the ring */
250 u8 queue_index
; /* logical index of the ring*/
251 u8 reg_idx
; /* physical index of the ring */
253 /* everything past this point are written often */
261 struct igb_tx_queue_stats tx_stats
;
262 struct u64_stats_sync tx_syncp
;
263 struct u64_stats_sync tx_syncp2
;
268 struct igb_rx_queue_stats rx_stats
;
269 struct u64_stats_sync rx_syncp
;
272 } ____cacheline_internodealigned_in_smp
;
274 struct igb_q_vector
{
275 struct igb_adapter
*adapter
; /* backlink */
276 int cpu
; /* CPU for DCA */
277 u32 eims_value
; /* EIMS mask value */
281 void __iomem
*itr_register
;
283 struct igb_ring_container rx
, tx
;
285 struct napi_struct napi
;
286 struct rcu_head rcu
; /* to avoid race with update stats on free */
287 char name
[IFNAMSIZ
+ 9];
289 /* for dynamic allocation of rings associated with this q_vector */
290 struct igb_ring ring
[0] ____cacheline_internodealigned_in_smp
;
293 enum e1000_ring_flags_t
{
294 IGB_RING_FLAG_RX_SCTP_CSUM
,
295 IGB_RING_FLAG_RX_LB_VLAN_BSWAP
,
296 IGB_RING_FLAG_TX_CTX_IDX
,
297 IGB_RING_FLAG_TX_DETECT_HANG
300 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
302 #define IGB_RX_DESC(R, i) \
303 (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
304 #define IGB_TX_DESC(R, i) \
305 (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
306 #define IGB_TX_CTXTDESC(R, i) \
307 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
309 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */
310 static inline __le32
igb_test_staterr(union e1000_adv_rx_desc
*rx_desc
,
311 const u32 stat_err_bits
)
313 return rx_desc
->wb
.upper
.status_error
& cpu_to_le32(stat_err_bits
);
316 /* igb_desc_unused - calculate if we have unused descriptors */
317 static inline int igb_desc_unused(struct igb_ring
*ring
)
319 if (ring
->next_to_clean
> ring
->next_to_use
)
320 return ring
->next_to_clean
- ring
->next_to_use
- 1;
322 return ring
->count
+ ring
->next_to_clean
- ring
->next_to_use
- 1;
325 struct igb_i2c_client_list
{
326 struct i2c_client
*client
;
327 struct igb_i2c_client_list
*next
;
330 #ifdef CONFIG_IGB_HWMON
332 #define IGB_HWMON_TYPE_LOC 0
333 #define IGB_HWMON_TYPE_TEMP 1
334 #define IGB_HWMON_TYPE_CAUTION 2
335 #define IGB_HWMON_TYPE_MAX 3
338 struct device_attribute dev_attr
;
340 struct e1000_thermal_diode_data
*sensor
;
345 struct device
*device
;
346 struct hwmon_attr
*hwmon_list
;
347 unsigned int n_hwmon
;
351 /* board specific private data structure */
353 unsigned long active_vlans
[BITS_TO_LONGS(VLAN_N_VID
)];
355 struct net_device
*netdev
;
360 unsigned int num_q_vectors
;
361 struct msix_entry
*msix_entries
;
363 /* Interrupt Throttle Rate */
371 u32 tx_timeout_count
;
373 struct igb_ring
*tx_ring
[16];
377 struct igb_ring
*rx_ring
[16];
382 struct timer_list watchdog_timer
;
383 struct timer_list phy_info_timer
;
392 struct work_struct reset_task
;
393 struct work_struct watchdog_task
;
395 u8 tx_timeout_factor
;
396 struct timer_list blink_timer
;
397 unsigned long led_status
;
399 /* OS defined structs */
400 struct pci_dev
*pdev
;
402 spinlock_t stats64_lock
;
403 struct rtnl_link_stats64 stats64
;
405 /* structs defined in e1000_hw.h */
407 struct e1000_hw_stats stats
;
408 struct e1000_phy_info phy_info
;
409 struct e1000_phy_stats phy_stats
;
412 struct igb_ring test_tx_ring
;
413 struct igb_ring test_rx_ring
;
417 struct igb_q_vector
*q_vector
[MAX_Q_VECTORS
];
418 u32 eims_enable_mask
;
421 /* to not mess up cache alignment, always add to the bottom */
424 unsigned int vfs_allocated_count
;
425 struct vf_data_storage
*vf_data
;
426 int vf_rate_link_speed
;
431 struct ptp_clock
*ptp_clock
;
432 struct ptp_clock_info ptp_caps
;
433 struct delayed_work ptp_overflow_work
;
434 struct work_struct ptp_tx_work
;
435 struct sk_buff
*ptp_tx_skb
;
436 unsigned long ptp_tx_start
;
437 unsigned long last_rx_ptp_check
;
438 spinlock_t tmreg_lock
;
439 struct cyclecounter cc
;
440 struct timecounter tc
;
441 u32 tx_hwtstamp_timeouts
;
442 u32 rx_hwtstamp_cleared
;
445 #ifdef CONFIG_IGB_HWMON
446 struct hwmon_buff igb_hwmon_buff
;
449 struct i2c_algo_bit_data i2c_algo
;
450 struct i2c_adapter i2c_adap
;
451 struct i2c_client
*i2c_client
;
454 #define IGB_FLAG_HAS_MSI (1 << 0)
455 #define IGB_FLAG_DCA_ENABLED (1 << 1)
456 #define IGB_FLAG_QUAD_PORT_A (1 << 2)
457 #define IGB_FLAG_QUEUE_PAIRS (1 << 3)
458 #define IGB_FLAG_DMAC (1 << 4)
459 #define IGB_FLAG_PTP (1 << 5)
460 #define IGB_FLAG_RSS_FIELD_IPV4_UDP (1 << 6)
461 #define IGB_FLAG_RSS_FIELD_IPV6_UDP (1 << 7)
462 #define IGB_FLAG_WOL_SUPPORTED (1 << 8)
464 /* DMA Coalescing defines */
465 #define IGB_MIN_TXPBSIZE 20408
466 #define IGB_TX_BUF_4096 4096
467 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
469 #define IGB_82576_TSYNC_SHIFT 19
470 #define IGB_TS_HDR_LEN 16
481 extern char igb_driver_name
[];
482 extern char igb_driver_version
[];
484 extern int igb_up(struct igb_adapter
*);
485 extern void igb_down(struct igb_adapter
*);
486 extern void igb_reinit_locked(struct igb_adapter
*);
487 extern void igb_reset(struct igb_adapter
*);
488 extern int igb_set_spd_dplx(struct igb_adapter
*, u32
, u8
);
489 extern int igb_setup_tx_resources(struct igb_ring
*);
490 extern int igb_setup_rx_resources(struct igb_ring
*);
491 extern void igb_free_tx_resources(struct igb_ring
*);
492 extern void igb_free_rx_resources(struct igb_ring
*);
493 extern void igb_configure_tx_ring(struct igb_adapter
*, struct igb_ring
*);
494 extern void igb_configure_rx_ring(struct igb_adapter
*, struct igb_ring
*);
495 extern void igb_setup_tctl(struct igb_adapter
*);
496 extern void igb_setup_rctl(struct igb_adapter
*);
497 extern netdev_tx_t
igb_xmit_frame_ring(struct sk_buff
*, struct igb_ring
*);
498 extern void igb_unmap_and_free_tx_resource(struct igb_ring
*,
499 struct igb_tx_buffer
*);
500 extern void igb_alloc_rx_buffers(struct igb_ring
*, u16
);
501 extern void igb_update_stats(struct igb_adapter
*, struct rtnl_link_stats64
*);
502 extern bool igb_has_link(struct igb_adapter
*adapter
);
503 extern void igb_set_ethtool_ops(struct net_device
*);
504 extern void igb_power_up_link(struct igb_adapter
*);
505 extern void igb_set_fw_version(struct igb_adapter
*);
506 extern void igb_ptp_init(struct igb_adapter
*adapter
);
507 extern void igb_ptp_stop(struct igb_adapter
*adapter
);
508 extern void igb_ptp_reset(struct igb_adapter
*adapter
);
509 extern void igb_ptp_tx_work(struct work_struct
*work
);
510 extern void igb_ptp_rx_hang(struct igb_adapter
*adapter
);
511 extern void igb_ptp_tx_hwtstamp(struct igb_adapter
*adapter
);
512 extern void igb_ptp_rx_rgtstamp(struct igb_q_vector
*q_vector
,
513 struct sk_buff
*skb
);
514 extern void igb_ptp_rx_pktstamp(struct igb_q_vector
*q_vector
,
516 struct sk_buff
*skb
);
517 static inline void igb_ptp_rx_hwtstamp(struct igb_q_vector
*q_vector
,
518 union e1000_adv_rx_desc
*rx_desc
,
521 if (igb_test_staterr(rx_desc
, E1000_RXDADV_STAT_TS
) &&
522 !igb_test_staterr(rx_desc
, E1000_RXDADV_STAT_TSIP
))
523 igb_ptp_rx_rgtstamp(q_vector
, skb
);
526 extern int igb_ptp_hwtstamp_ioctl(struct net_device
*netdev
,
527 struct ifreq
*ifr
, int cmd
);
528 #ifdef CONFIG_IGB_HWMON
529 extern void igb_sysfs_exit(struct igb_adapter
*adapter
);
530 extern int igb_sysfs_init(struct igb_adapter
*adapter
);
532 static inline s32
igb_reset_phy(struct e1000_hw
*hw
)
534 if (hw
->phy
.ops
.reset
)
535 return hw
->phy
.ops
.reset(hw
);
540 static inline s32
igb_read_phy_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
542 if (hw
->phy
.ops
.read_reg
)
543 return hw
->phy
.ops
.read_reg(hw
, offset
, data
);
548 static inline s32
igb_write_phy_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
)
550 if (hw
->phy
.ops
.write_reg
)
551 return hw
->phy
.ops
.write_reg(hw
, offset
, data
);
556 static inline s32
igb_get_phy_info(struct e1000_hw
*hw
)
558 if (hw
->phy
.ops
.get_phy_info
)
559 return hw
->phy
.ops
.get_phy_info(hw
);
564 static inline struct netdev_queue
*txring_txq(const struct igb_ring
*tx_ring
)
566 return netdev_get_tx_queue(tx_ring
->netdev
, tx_ring
->queue_index
);