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net/at91_ether: use macb register definitions
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / cadence / at91_ether.c
1 /*
2 * Ethernet driver for the Atmel AT91RM9200 (Thunder)
3 *
4 * Copyright (C) 2003 SAN People (Pty) Ltd
5 *
6 * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
7 * Initial version by Rick Bronson 01/11/2003
8 *
9 * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
10 * (Polaroid Corporation)
11 *
12 * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 */
19
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/mii.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/skbuff.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/ethtool.h>
29 #include <linux/platform_data/macb.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/gfp.h>
33 #include <linux/phy.h>
34
35 #include <asm/io.h>
36 #include <asm/uaccess.h>
37 #include <asm/mach-types.h>
38
39 #include <asm/gpio.h>
40 #include <mach/board.h>
41
42 #include "at91_ether.h"
43 #include "macb.h"
44
45 #define DRV_NAME "at91_ether"
46 #define DRV_VERSION "1.0"
47
48 #define LINK_POLL_INTERVAL (HZ)
49
50 /* ..................................................................... */
51
52 /*
53 * Read from a EMAC register.
54 */
55 static inline unsigned long at91_emac_read(struct at91_private *lp, unsigned int reg)
56 {
57 return __raw_readl(lp->emac_base + reg);
58 }
59
60 /*
61 * Write to a EMAC register.
62 */
63 static inline void at91_emac_write(struct at91_private *lp, unsigned int reg, unsigned long value)
64 {
65 __raw_writel(value, lp->emac_base + reg);
66 }
67
68 /* ........................... PHY INTERFACE ........................... */
69
70 /*
71 * Enable the MDIO bit in MAC control register
72 * When not called from an interrupt-handler, access to the PHY must be
73 * protected by a spinlock.
74 */
75 static void enable_mdi(struct at91_private *lp)
76 {
77 unsigned long ctl;
78
79 ctl = at91_emac_read(lp, MACB_NCR);
80 at91_emac_write(lp, MACB_NCR, ctl | MACB_BIT(MPE)); /* enable management port */
81 }
82
83 /*
84 * Disable the MDIO bit in the MAC control register
85 */
86 static void disable_mdi(struct at91_private *lp)
87 {
88 unsigned long ctl;
89
90 ctl = at91_emac_read(lp, MACB_NCR);
91 at91_emac_write(lp, MACB_NCR, ctl & ~MACB_BIT(MPE)); /* disable management port */
92 }
93
94 /*
95 * Wait until the PHY operation is complete.
96 */
97 static inline void at91_phy_wait(struct at91_private *lp)
98 {
99 unsigned long timeout = jiffies + 2;
100
101 while (!(at91_emac_read(lp, MACB_NSR) & MACB_BIT(IDLE))) {
102 if (time_after(jiffies, timeout)) {
103 printk("at91_ether: MIO timeout\n");
104 break;
105 }
106 cpu_relax();
107 }
108 }
109
110 /*
111 * Write value to the a PHY register
112 * Note: MDI interface is assumed to already have been enabled.
113 */
114 static void write_phy(struct at91_private *lp, unsigned char phy_addr, unsigned char address, unsigned int value)
115 {
116 at91_emac_write(lp, MACB_MAN, MACB_BF(SOF, MACB_MAN_SOF) | MACB_BF(CODE, MACB_MAN_CODE)
117 | MACB_BF(RW, MACB_MAN_WRITE) | ((phy_addr & 0x1f) << 23)
118 | (address << 18) | (value & ((1<<MACB_DATA_SIZE) - 1)));
119
120 /* Wait until IDLE bit in Network Status register is cleared */
121 at91_phy_wait(lp);
122 }
123
124 /*
125 * Read value stored in a PHY register.
126 * Note: MDI interface is assumed to already have been enabled.
127 */
128 static void read_phy(struct at91_private *lp, unsigned char phy_addr, unsigned char address, unsigned int *value)
129 {
130 at91_emac_write(lp, MACB_MAN, MACB_BF(SOF, MACB_MAN_SOF) | MACB_BF(CODE, MACB_MAN_CODE)
131 | MACB_BF(RW, MACB_MAN_READ) | ((phy_addr & 0x1f) << 23)
132 | (address << 18));
133
134 /* Wait until IDLE bit in Network Status register is cleared */
135 at91_phy_wait(lp);
136
137 *value = at91_emac_read(lp, MACB_MAN) & ((1<<MACB_DATA_SIZE) - 1);
138 }
139
140 /* ........................... PHY MANAGEMENT .......................... */
141
142 /*
143 * Access the PHY to determine the current link speed and mode, and update the
144 * MAC accordingly.
145 * If no link or auto-negotiation is busy, then no changes are made.
146 */
147 static void update_linkspeed(struct net_device *dev, int silent)
148 {
149 struct at91_private *lp = netdev_priv(dev);
150 unsigned int bmsr, bmcr, lpa, mac_cfg;
151 unsigned int speed, duplex;
152
153 if (!mii_link_ok(&lp->mii)) { /* no link */
154 netif_carrier_off(dev);
155 if (!silent)
156 printk(KERN_INFO "%s: Link down.\n", dev->name);
157 return;
158 }
159
160 /* Link up, or auto-negotiation still in progress */
161 read_phy(lp, lp->phy_address, MII_BMSR, &bmsr);
162 read_phy(lp, lp->phy_address, MII_BMCR, &bmcr);
163 if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */
164 if (!(bmsr & BMSR_ANEGCOMPLETE))
165 return; /* Do nothing - another interrupt generated when negotiation complete */
166
167 read_phy(lp, lp->phy_address, MII_LPA, &lpa);
168 if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100;
169 else speed = SPEED_10;
170 if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL;
171 else duplex = DUPLEX_HALF;
172 } else {
173 speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
174 duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
175 }
176
177 /* Update the MAC */
178 mac_cfg = at91_emac_read(lp, MACB_NCFGR) & ~(MACB_BIT(SPD) | MACB_BIT(FD));
179 if (speed == SPEED_100) {
180 if (duplex == DUPLEX_FULL) /* 100 Full Duplex */
181 mac_cfg |= MACB_BIT(SPD) | MACB_BIT(FD);
182 else /* 100 Half Duplex */
183 mac_cfg |= MACB_BIT(SPD);
184 } else {
185 if (duplex == DUPLEX_FULL) /* 10 Full Duplex */
186 mac_cfg |= MACB_BIT(FD);
187 else {} /* 10 Half Duplex */
188 }
189 at91_emac_write(lp, MACB_NCFGR, mac_cfg);
190
191 if (!silent)
192 printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
193 netif_carrier_on(dev);
194 }
195
196 /*
197 * Handle interrupts from the PHY
198 */
199 static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id)
200 {
201 struct net_device *dev = (struct net_device *) dev_id;
202 struct at91_private *lp = netdev_priv(dev);
203 unsigned int phy;
204
205 /*
206 * This hander is triggered on both edges, but the PHY chips expect
207 * level-triggering. We therefore have to check if the PHY actually has
208 * an IRQ pending.
209 */
210 enable_mdi(lp);
211 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
212 read_phy(lp, lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */
213 if (!(phy & (1 << 0)))
214 goto done;
215 }
216 else if (lp->phy_type == MII_LXT971A_ID) {
217 read_phy(lp, lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */
218 if (!(phy & (1 << 2)))
219 goto done;
220 }
221 else if (lp->phy_type == MII_BCM5221_ID) {
222 read_phy(lp, lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */
223 if (!(phy & (1 << 0)))
224 goto done;
225 }
226 else if (lp->phy_type == MII_KS8721_ID) {
227 read_phy(lp, lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */
228 if (!(phy & ((1 << 2) | 1)))
229 goto done;
230 }
231 else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */
232 read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &phy);
233 if (!(phy & ((1 << 2) | 1)))
234 goto done;
235 }
236 else if (lp->phy_type == MII_DP83848_ID) {
237 read_phy(lp, lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */
238 if (!(phy & (1 << 7)))
239 goto done;
240 }
241
242 update_linkspeed(dev, 0);
243
244 done:
245 disable_mdi(lp);
246
247 return IRQ_HANDLED;
248 }
249
250 /*
251 * Initialize and enable the PHY interrupt for link-state changes
252 */
253 static void enable_phyirq(struct net_device *dev)
254 {
255 struct at91_private *lp = netdev_priv(dev);
256 unsigned int dsintr, irq_number;
257 int status;
258
259 if (!gpio_is_valid(lp->board_data.phy_irq_pin)) {
260 /*
261 * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
262 * or board does not have it connected.
263 */
264 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
265 return;
266 }
267
268 irq_number = gpio_to_irq(lp->board_data.phy_irq_pin);
269 status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev);
270 if (status) {
271 printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status);
272 return;
273 }
274
275 spin_lock_irq(&lp->lock);
276 enable_mdi(lp);
277
278 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
279 read_phy(lp, lp->phy_address, MII_DSINTR_REG, &dsintr);
280 dsintr = dsintr & ~0xf00; /* clear bits 8..11 */
281 write_phy(lp, lp->phy_address, MII_DSINTR_REG, dsintr);
282 }
283 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
284 read_phy(lp, lp->phy_address, MII_ISINTE_REG, &dsintr);
285 dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */
286 write_phy(lp, lp->phy_address, MII_ISINTE_REG, dsintr);
287 }
288 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
289 dsintr = (1 << 15) | ( 1 << 14);
290 write_phy(lp, lp->phy_address, MII_BCMINTR_REG, dsintr);
291 }
292 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
293 dsintr = (1 << 10) | ( 1 << 8);
294 write_phy(lp, lp->phy_address, MII_TPISTATUS, dsintr);
295 }
296 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
297 read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &dsintr);
298 dsintr = dsintr | 0x500; /* set bits 8, 10 */
299 write_phy(lp, lp->phy_address, MII_T78Q21INT_REG, dsintr);
300 }
301 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
302 read_phy(lp, lp->phy_address, MII_DPMISR_REG, &dsintr);
303 dsintr = dsintr | 0x3c; /* set bits 2..5 */
304 write_phy(lp, lp->phy_address, MII_DPMISR_REG, dsintr);
305 read_phy(lp, lp->phy_address, MII_DPMICR_REG, &dsintr);
306 dsintr = dsintr | 0x3; /* set bits 0,1 */
307 write_phy(lp, lp->phy_address, MII_DPMICR_REG, dsintr);
308 }
309
310 disable_mdi(lp);
311 spin_unlock_irq(&lp->lock);
312 }
313
314 /*
315 * Disable the PHY interrupt
316 */
317 static void disable_phyirq(struct net_device *dev)
318 {
319 struct at91_private *lp = netdev_priv(dev);
320 unsigned int dsintr;
321 unsigned int irq_number;
322
323 if (!gpio_is_valid(lp->board_data.phy_irq_pin)) {
324 del_timer_sync(&lp->check_timer);
325 return;
326 }
327
328 spin_lock_irq(&lp->lock);
329 enable_mdi(lp);
330
331 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
332 read_phy(lp, lp->phy_address, MII_DSINTR_REG, &dsintr);
333 dsintr = dsintr | 0xf00; /* set bits 8..11 */
334 write_phy(lp, lp->phy_address, MII_DSINTR_REG, dsintr);
335 }
336 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
337 read_phy(lp, lp->phy_address, MII_ISINTE_REG, &dsintr);
338 dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */
339 write_phy(lp, lp->phy_address, MII_ISINTE_REG, dsintr);
340 }
341 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
342 read_phy(lp, lp->phy_address, MII_BCMINTR_REG, &dsintr);
343 dsintr = ~(1 << 14);
344 write_phy(lp, lp->phy_address, MII_BCMINTR_REG, dsintr);
345 }
346 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
347 read_phy(lp, lp->phy_address, MII_TPISTATUS, &dsintr);
348 dsintr = ~((1 << 10) | (1 << 8));
349 write_phy(lp, lp->phy_address, MII_TPISTATUS, dsintr);
350 }
351 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
352 read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &dsintr);
353 dsintr = dsintr & ~0x500; /* clear bits 8, 10 */
354 write_phy(lp, lp->phy_address, MII_T78Q21INT_REG, dsintr);
355 }
356 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
357 read_phy(lp, lp->phy_address, MII_DPMICR_REG, &dsintr);
358 dsintr = dsintr & ~0x3; /* clear bits 0, 1 */
359 write_phy(lp, lp->phy_address, MII_DPMICR_REG, dsintr);
360 read_phy(lp, lp->phy_address, MII_DPMISR_REG, &dsintr);
361 dsintr = dsintr & ~0x3c; /* clear bits 2..5 */
362 write_phy(lp, lp->phy_address, MII_DPMISR_REG, dsintr);
363 }
364
365 disable_mdi(lp);
366 spin_unlock_irq(&lp->lock);
367
368 irq_number = gpio_to_irq(lp->board_data.phy_irq_pin);
369 free_irq(irq_number, dev); /* Free interrupt handler */
370 }
371
372 /*
373 * Perform a software reset of the PHY.
374 */
375 #if 0
376 static void reset_phy(struct net_device *dev)
377 {
378 struct at91_private *lp = netdev_priv(dev);
379 unsigned int bmcr;
380
381 spin_lock_irq(&lp->lock);
382 enable_mdi(lp);
383
384 /* Perform PHY reset */
385 write_phy(lp, lp->phy_address, MII_BMCR, BMCR_RESET);
386
387 /* Wait until PHY reset is complete */
388 do {
389 read_phy(lp, lp->phy_address, MII_BMCR, &bmcr);
390 } while (!(bmcr & BMCR_RESET));
391
392 disable_mdi(lp);
393 spin_unlock_irq(&lp->lock);
394 }
395 #endif
396
397 static void at91ether_check_link(unsigned long dev_id)
398 {
399 struct net_device *dev = (struct net_device *) dev_id;
400 struct at91_private *lp = netdev_priv(dev);
401
402 enable_mdi(lp);
403 update_linkspeed(dev, 1);
404 disable_mdi(lp);
405
406 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
407 }
408
409 /*
410 * Perform any PHY-specific initialization.
411 */
412 static void __init initialize_phy(struct at91_private *lp)
413 {
414 unsigned int val;
415
416 spin_lock_irq(&lp->lock);
417 enable_mdi(lp);
418
419 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
420 read_phy(lp, lp->phy_address, MII_DSCR_REG, &val);
421 if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */
422 lp->phy_media = PORT_FIBRE;
423 } else if (machine_is_csb337()) {
424 /* mix link activity status into LED2 link state */
425 write_phy(lp, lp->phy_address, MII_LEDCTRL_REG, 0x0d22);
426 } else if (machine_is_ecbat91())
427 write_phy(lp, lp->phy_address, MII_LEDCTRL_REG, 0x156A);
428
429 disable_mdi(lp);
430 spin_unlock_irq(&lp->lock);
431 }
432
433 /* ......................... ADDRESS MANAGEMENT ........................ */
434
435 /*
436 * NOTE: Your bootloader must always set the MAC address correctly before
437 * booting into Linux.
438 *
439 * - It must always set the MAC address after reset, even if it doesn't
440 * happen to access the Ethernet while it's booting. Some versions of
441 * U-Boot on the AT91RM9200-DK do not do this.
442 *
443 * - Likewise it must store the addresses in the correct byte order.
444 * MicroMonitor (uMon) on the CSB337 does this incorrectly (and
445 * continues to do so, for bug-compatibility).
446 */
447
448 static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo)
449 {
450 char addr[6];
451
452 if (machine_is_csb337()) {
453 addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */
454 addr[4] = (lo & 0xff00) >> 8;
455 addr[3] = (lo & 0xff0000) >> 16;
456 addr[2] = (lo & 0xff000000) >> 24;
457 addr[1] = (hi & 0xff);
458 addr[0] = (hi & 0xff00) >> 8;
459 }
460 else {
461 addr[0] = (lo & 0xff);
462 addr[1] = (lo & 0xff00) >> 8;
463 addr[2] = (lo & 0xff0000) >> 16;
464 addr[3] = (lo & 0xff000000) >> 24;
465 addr[4] = (hi & 0xff);
466 addr[5] = (hi & 0xff00) >> 8;
467 }
468
469 if (is_valid_ether_addr(addr)) {
470 memcpy(dev->dev_addr, &addr, 6);
471 return 1;
472 }
473 return 0;
474 }
475
476 /*
477 * Set the ethernet MAC address in dev->dev_addr
478 */
479 static void __init get_mac_address(struct net_device *dev)
480 {
481 struct at91_private *lp = netdev_priv(dev);
482
483 /* Check Specific-Address 1 */
484 if (unpack_mac_address(dev, at91_emac_read(lp, MACB_SA1T), at91_emac_read(lp, MACB_SA1B)))
485 return;
486 /* Check Specific-Address 2 */
487 if (unpack_mac_address(dev, at91_emac_read(lp, MACB_SA2T), at91_emac_read(lp, MACB_SA2B)))
488 return;
489 /* Check Specific-Address 3 */
490 if (unpack_mac_address(dev, at91_emac_read(lp, MACB_SA3T), at91_emac_read(lp, MACB_SA3B)))
491 return;
492 /* Check Specific-Address 4 */
493 if (unpack_mac_address(dev, at91_emac_read(lp, MACB_SA4T), at91_emac_read(lp, MACB_SA4B)))
494 return;
495
496 printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n");
497 }
498
499 /*
500 * Program the hardware MAC address from dev->dev_addr.
501 */
502 static void update_mac_address(struct net_device *dev)
503 {
504 struct at91_private *lp = netdev_priv(dev);
505
506 at91_emac_write(lp, MACB_SA1B, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16)
507 | (dev->dev_addr[1] << 8) | (dev->dev_addr[0]));
508 at91_emac_write(lp, MACB_SA1T, (dev->dev_addr[5] << 8) | (dev->dev_addr[4]));
509
510 at91_emac_write(lp, MACB_SA2B, 0);
511 at91_emac_write(lp, MACB_SA2T, 0);
512 }
513
514 /*
515 * Store the new hardware address in dev->dev_addr, and update the MAC.
516 */
517 static int set_mac_address(struct net_device *dev, void* addr)
518 {
519 struct sockaddr *address = addr;
520
521 if (!is_valid_ether_addr(address->sa_data))
522 return -EADDRNOTAVAIL;
523
524 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
525 update_mac_address(dev);
526
527 printk("%s: Setting MAC address to %pM\n", dev->name,
528 dev->dev_addr);
529
530 return 0;
531 }
532
533 static int inline hash_bit_value(int bitnr, __u8 *addr)
534 {
535 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
536 return 1;
537 return 0;
538 }
539
540 /*
541 * The hash address register is 64 bits long and takes up two locations in the memory map.
542 * The least significant bits are stored in EMAC_HSL and the most significant
543 * bits in EMAC_HSH.
544 *
545 * The unicast hash enable and the multicast hash enable bits in the network configuration
546 * register enable the reception of hash matched frames. The destination address is
547 * reduced to a 6 bit index into the 64 bit hash register using the following hash function.
548 * The hash function is an exclusive or of every sixth bit of the destination address.
549 * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
550 * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
551 * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
552 * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
553 * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
554 * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
555 * da[0] represents the least significant bit of the first byte received, that is, the multicast/
556 * unicast indicator, and da[47] represents the most significant bit of the last byte
557 * received.
558 * If the hash index points to a bit that is set in the hash register then the frame will be
559 * matched according to whether the frame is multicast or unicast.
560 * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and
561 * the hash index points to a bit set in the hash register.
562 * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the
563 * hash index points to a bit set in the hash register.
564 * To receive all multicast frames, the hash register should be set with all ones and the
565 * multicast hash enable bit should be set in the network configuration register.
566 */
567
568 /*
569 * Return the hash index value for the specified address.
570 */
571 static int hash_get_index(__u8 *addr)
572 {
573 int i, j, bitval;
574 int hash_index = 0;
575
576 for (j = 0; j < 6; j++) {
577 for (i = 0, bitval = 0; i < 8; i++)
578 bitval ^= hash_bit_value(i*6 + j, addr);
579
580 hash_index |= (bitval << j);
581 }
582
583 return hash_index;
584 }
585
586 /*
587 * Add multicast addresses to the internal multicast-hash table.
588 */
589 static void at91ether_sethashtable(struct net_device *dev)
590 {
591 struct at91_private *lp = netdev_priv(dev);
592 struct netdev_hw_addr *ha;
593 unsigned long mc_filter[2];
594 unsigned int bitnr;
595
596 mc_filter[0] = mc_filter[1] = 0;
597
598 netdev_for_each_mc_addr(ha, dev) {
599 bitnr = hash_get_index(ha->addr);
600 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
601 }
602
603 at91_emac_write(lp, MACB_HRB, mc_filter[0]);
604 at91_emac_write(lp, MACB_HRT, mc_filter[1]);
605 }
606
607 /*
608 * Enable/Disable promiscuous and multicast modes.
609 */
610 static void at91ether_set_multicast_list(struct net_device *dev)
611 {
612 struct at91_private *lp = netdev_priv(dev);
613 unsigned long cfg;
614
615 cfg = at91_emac_read(lp, MACB_NCFGR);
616
617 if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */
618 cfg |= MACB_BIT(CAF);
619 else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */
620 cfg &= ~MACB_BIT(CAF);
621
622 if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */
623 at91_emac_write(lp, MACB_HRT, -1);
624 at91_emac_write(lp, MACB_HRB, -1);
625 cfg |= MACB_BIT(NCFGR_MTI);
626 } else if (!netdev_mc_empty(dev)) { /* Enable specific multicasts */
627 at91ether_sethashtable(dev);
628 cfg |= MACB_BIT(NCFGR_MTI);
629 } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */
630 at91_emac_write(lp, MACB_HRT, 0);
631 at91_emac_write(lp, MACB_HRB, 0);
632 cfg &= ~MACB_BIT(NCFGR_MTI);
633 }
634
635 at91_emac_write(lp, MACB_NCFGR, cfg);
636 }
637
638 /* ......................... ETHTOOL SUPPORT ........................... */
639
640 static int mdio_read(struct net_device *dev, int phy_id, int location)
641 {
642 struct at91_private *lp = netdev_priv(dev);
643 unsigned int value;
644
645 read_phy(lp, phy_id, location, &value);
646 return value;
647 }
648
649 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
650 {
651 struct at91_private *lp = netdev_priv(dev);
652
653 write_phy(lp, phy_id, location, value);
654 }
655
656 static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
657 {
658 struct at91_private *lp = netdev_priv(dev);
659 int ret;
660
661 spin_lock_irq(&lp->lock);
662 enable_mdi(lp);
663
664 ret = mii_ethtool_gset(&lp->mii, cmd);
665
666 disable_mdi(lp);
667 spin_unlock_irq(&lp->lock);
668
669 if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */
670 cmd->supported = SUPPORTED_FIBRE;
671 cmd->port = PORT_FIBRE;
672 }
673
674 return ret;
675 }
676
677 static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
678 {
679 struct at91_private *lp = netdev_priv(dev);
680 int ret;
681
682 spin_lock_irq(&lp->lock);
683 enable_mdi(lp);
684
685 ret = mii_ethtool_sset(&lp->mii, cmd);
686
687 disable_mdi(lp);
688 spin_unlock_irq(&lp->lock);
689
690 return ret;
691 }
692
693 static int at91ether_nwayreset(struct net_device *dev)
694 {
695 struct at91_private *lp = netdev_priv(dev);
696 int ret;
697
698 spin_lock_irq(&lp->lock);
699 enable_mdi(lp);
700
701 ret = mii_nway_restart(&lp->mii);
702
703 disable_mdi(lp);
704 spin_unlock_irq(&lp->lock);
705
706 return ret;
707 }
708
709 static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
710 {
711 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
712 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
713 strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
714 }
715
716 static const struct ethtool_ops at91ether_ethtool_ops = {
717 .get_settings = at91ether_get_settings,
718 .set_settings = at91ether_set_settings,
719 .get_drvinfo = at91ether_get_drvinfo,
720 .nway_reset = at91ether_nwayreset,
721 .get_link = ethtool_op_get_link,
722 };
723
724 static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
725 {
726 struct at91_private *lp = netdev_priv(dev);
727 int res;
728
729 if (!netif_running(dev))
730 return -EINVAL;
731
732 spin_lock_irq(&lp->lock);
733 enable_mdi(lp);
734 res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL);
735 disable_mdi(lp);
736 spin_unlock_irq(&lp->lock);
737
738 return res;
739 }
740
741 /* ................................ MAC ................................ */
742
743 /*
744 * Initialize and start the Receiver and Transmit subsystems
745 */
746 static void at91ether_start(struct net_device *dev)
747 {
748 struct at91_private *lp = netdev_priv(dev);
749 struct recv_desc_bufs *dlist, *dlist_phys;
750 int i;
751 unsigned long ctl;
752
753 dlist = lp->dlist;
754 dlist_phys = lp->dlist_phys;
755
756 for (i = 0; i < MAX_RX_DESCR; i++) {
757 dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0];
758 dlist->descriptors[i].size = 0;
759 }
760
761 /* Set the Wrap bit on the last descriptor */
762 dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP;
763
764 /* Reset buffer index */
765 lp->rxBuffIndex = 0;
766
767 /* Program address of descriptor list in Rx Buffer Queue register */
768 at91_emac_write(lp, MACB_RBQP, (unsigned long) dlist_phys);
769
770 /* Enable Receive and Transmit */
771 ctl = at91_emac_read(lp, MACB_NCR);
772 at91_emac_write(lp, MACB_NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
773 }
774
775 /*
776 * Open the ethernet interface
777 */
778 static int at91ether_open(struct net_device *dev)
779 {
780 struct at91_private *lp = netdev_priv(dev);
781 unsigned long ctl;
782
783 if (!is_valid_ether_addr(dev->dev_addr))
784 return -EADDRNOTAVAIL;
785
786 clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */
787
788 /* Clear internal statistics */
789 ctl = at91_emac_read(lp, MACB_NCR);
790 at91_emac_write(lp, MACB_NCR, ctl | MACB_BIT(CLRSTAT));
791
792 /* Update the MAC address (incase user has changed it) */
793 update_mac_address(dev);
794
795 /* Enable PHY interrupt */
796 enable_phyirq(dev);
797
798 /* Enable MAC interrupts */
799 at91_emac_write(lp, MACB_IER, MACB_BIT(RCOMP) | MACB_BIT(RXUBR)
800 | MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE) | MACB_BIT(TCOMP)
801 | MACB_BIT(ISR_ROVR) | MACB_BIT(HRESP));
802
803 /* Determine current link speed */
804 spin_lock_irq(&lp->lock);
805 enable_mdi(lp);
806 update_linkspeed(dev, 0);
807 disable_mdi(lp);
808 spin_unlock_irq(&lp->lock);
809
810 at91ether_start(dev);
811 netif_start_queue(dev);
812 return 0;
813 }
814
815 /*
816 * Close the interface
817 */
818 static int at91ether_close(struct net_device *dev)
819 {
820 struct at91_private *lp = netdev_priv(dev);
821 unsigned long ctl;
822
823 /* Disable Receiver and Transmitter */
824 ctl = at91_emac_read(lp, MACB_NCR);
825 at91_emac_write(lp, MACB_NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
826
827 /* Disable PHY interrupt */
828 disable_phyirq(dev);
829
830 /* Disable MAC interrupts */
831 at91_emac_write(lp, MACB_IDR, MACB_BIT(RCOMP) | MACB_BIT(RXUBR)
832 | MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)
833 | MACB_BIT(TCOMP) | MACB_BIT(ISR_ROVR)
834 | MACB_BIT(HRESP));
835
836 netif_stop_queue(dev);
837
838 clk_disable(lp->ether_clk); /* Disable Peripheral clock */
839
840 return 0;
841 }
842
843 /*
844 * Transmit packet.
845 */
846 static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
847 {
848 struct at91_private *lp = netdev_priv(dev);
849
850 if (at91_emac_read(lp, MACB_TSR) & MACB_BIT(RM9200_BNQ)) {
851 netif_stop_queue(dev);
852
853 /* Store packet information (to free when Tx completed) */
854 lp->skb = skb;
855 lp->skb_length = skb->len;
856 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
857 dev->stats.tx_bytes += skb->len;
858
859 /* Set address of the data in the Transmit Address register */
860 at91_emac_write(lp, MACB_TAR, lp->skb_physaddr);
861 /* Set length of the packet in the Transmit Control register */
862 at91_emac_write(lp, MACB_TCR, skb->len);
863
864 } else {
865 printk(KERN_ERR "at91_ether.c: at91ether_start_xmit() called, but device is busy!\n");
866 return NETDEV_TX_BUSY; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
867 on this skb, he also reports -ENETDOWN and printk's, so either
868 we free and return(0) or don't free and return 1 */
869 }
870
871 return NETDEV_TX_OK;
872 }
873
874 /*
875 * Update the current statistics from the internal statistics registers.
876 */
877 static struct net_device_stats *at91ether_stats(struct net_device *dev)
878 {
879 struct at91_private *lp = netdev_priv(dev);
880 int ale, lenerr, seqe, lcol, ecol;
881
882 if (netif_running(dev)) {
883 dev->stats.rx_packets += at91_emac_read(lp, MACB_FRO); /* Good frames received */
884 ale = at91_emac_read(lp, MACB_ALE);
885 dev->stats.rx_frame_errors += ale; /* Alignment errors */
886 lenerr = at91_emac_read(lp, MACB_ELE) + at91_emac_read(lp, MACB_USF);
887 dev->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */
888 seqe = at91_emac_read(lp, MACB_FCSE);
889 dev->stats.rx_crc_errors += seqe; /* CRC error */
890 dev->stats.rx_fifo_errors += at91_emac_read(lp, MACB_RRE);/* Receive buffer not available */
891 dev->stats.rx_errors += (ale + lenerr + seqe
892 + at91_emac_read(lp, MACB_RSE) + at91_emac_read(lp, MACB_RJA));
893
894 dev->stats.tx_packets += at91_emac_read(lp, MACB_FTO); /* Frames successfully transmitted */
895 dev->stats.tx_fifo_errors += at91_emac_read(lp, MACB_TUND); /* Transmit FIFO underruns */
896 dev->stats.tx_carrier_errors += at91_emac_read(lp, MACB_CSE); /* Carrier Sense errors */
897 dev->stats.tx_heartbeat_errors += at91_emac_read(lp, MACB_STE);/* Heartbeat error */
898
899 lcol = at91_emac_read(lp, MACB_LCOL);
900 ecol = at91_emac_read(lp, MACB_EXCOL);
901 dev->stats.tx_window_errors += lcol; /* Late collisions */
902 dev->stats.tx_aborted_errors += ecol; /* 16 collisions */
903
904 dev->stats.collisions += (at91_emac_read(lp, MACB_SCF) + at91_emac_read(lp, MACB_MCF) + lcol + ecol);
905 }
906 return &dev->stats;
907 }
908
909 /*
910 * Extract received frame from buffer descriptors and sent to upper layers.
911 * (Called from interrupt context)
912 */
913 static void at91ether_rx(struct net_device *dev)
914 {
915 struct at91_private *lp = netdev_priv(dev);
916 struct recv_desc_bufs *dlist;
917 unsigned char *p_recv;
918 struct sk_buff *skb;
919 unsigned int pktlen;
920
921 dlist = lp->dlist;
922 while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
923 p_recv = dlist->recv_buf[lp->rxBuffIndex];
924 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */
925 skb = netdev_alloc_skb(dev, pktlen + 2);
926 if (skb != NULL) {
927 skb_reserve(skb, 2);
928 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
929
930 skb->protocol = eth_type_trans(skb, dev);
931 dev->stats.rx_bytes += pktlen;
932 netif_rx(skb);
933 }
934 else {
935 dev->stats.rx_dropped += 1;
936 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
937 }
938
939 if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST)
940 dev->stats.multicast++;
941
942 dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */
943 if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */
944 lp->rxBuffIndex = 0;
945 else
946 lp->rxBuffIndex++;
947 }
948 }
949
950 /*
951 * MAC interrupt handler
952 */
953 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
954 {
955 struct net_device *dev = (struct net_device *) dev_id;
956 struct at91_private *lp = netdev_priv(dev);
957 unsigned long intstatus, ctl;
958
959 /* MAC Interrupt Status register indicates what interrupts are pending.
960 It is automatically cleared once read. */
961 intstatus = at91_emac_read(lp, MACB_ISR);
962
963 if (intstatus & MACB_BIT(RCOMP)) /* Receive complete */
964 at91ether_rx(dev);
965
966 if (intstatus & MACB_BIT(TCOMP)) { /* Transmit complete */
967 /* The TCOM bit is set even if the transmission failed. */
968 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
969 dev->stats.tx_errors += 1;
970
971 if (lp->skb) {
972 dev_kfree_skb_irq(lp->skb);
973 lp->skb = NULL;
974 dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE);
975 }
976 netif_wake_queue(dev);
977 }
978
979 /* Work-around for Errata #11 */
980 if (intstatus & MACB_BIT(RXUBR)) {
981 ctl = at91_emac_read(lp, MACB_NCR);
982 at91_emac_write(lp, MACB_NCR, ctl & ~MACB_BIT(RE));
983 at91_emac_write(lp, MACB_NCR, ctl | MACB_BIT(RE));
984 }
985
986 if (intstatus & MACB_BIT(ISR_ROVR))
987 printk("%s: ROVR error\n", dev->name);
988
989 return IRQ_HANDLED;
990 }
991
992 #ifdef CONFIG_NET_POLL_CONTROLLER
993 static void at91ether_poll_controller(struct net_device *dev)
994 {
995 unsigned long flags;
996
997 local_irq_save(flags);
998 at91ether_interrupt(dev->irq, dev);
999 local_irq_restore(flags);
1000 }
1001 #endif
1002
1003 static const struct net_device_ops at91ether_netdev_ops = {
1004 .ndo_open = at91ether_open,
1005 .ndo_stop = at91ether_close,
1006 .ndo_start_xmit = at91ether_start_xmit,
1007 .ndo_get_stats = at91ether_stats,
1008 .ndo_set_rx_mode = at91ether_set_multicast_list,
1009 .ndo_set_mac_address = set_mac_address,
1010 .ndo_do_ioctl = at91ether_ioctl,
1011 .ndo_validate_addr = eth_validate_addr,
1012 .ndo_change_mtu = eth_change_mtu,
1013 #ifdef CONFIG_NET_POLL_CONTROLLER
1014 .ndo_poll_controller = at91ether_poll_controller,
1015 #endif
1016 };
1017
1018 /*
1019 * Detect the PHY type, and its address.
1020 */
1021 static int __init at91ether_phy_detect(struct at91_private *lp)
1022 {
1023 unsigned int phyid1, phyid2;
1024 unsigned long phy_id;
1025 unsigned short phy_address = 0;
1026
1027 while (phy_address < PHY_MAX_ADDR) {
1028 /* Read the PHY ID registers */
1029 enable_mdi(lp);
1030 read_phy(lp, phy_address, MII_PHYSID1, &phyid1);
1031 read_phy(lp, phy_address, MII_PHYSID2, &phyid2);
1032 disable_mdi(lp);
1033
1034 phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
1035 switch (phy_id) {
1036 case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
1037 case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
1038 case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */
1039 case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
1040 case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
1041 case MII_DP83847_ID: /* National Semiconductor DP83847: */
1042 case MII_DP83848_ID: /* National Semiconductor DP83848: */
1043 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
1044 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
1045 case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
1046 case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
1047 /* store detected values */
1048 lp->phy_type = phy_id; /* Type of PHY connected */
1049 lp->phy_address = phy_address; /* MDI address of PHY */
1050 return 1;
1051 }
1052
1053 phy_address++;
1054 }
1055
1056 return 0; /* not detected */
1057 }
1058
1059
1060 /*
1061 * Detect MAC & PHY and perform ethernet interface initialization
1062 */
1063 static int __init at91ether_probe(struct platform_device *pdev)
1064 {
1065 struct macb_platform_data *board_data = pdev->dev.platform_data;
1066 struct resource *regs;
1067 struct net_device *dev;
1068 struct at91_private *lp;
1069 int res;
1070
1071 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1072 if (!regs)
1073 return -ENOENT;
1074
1075 dev = alloc_etherdev(sizeof(struct at91_private));
1076 if (!dev)
1077 return -ENOMEM;
1078
1079 lp = netdev_priv(dev);
1080 lp->board_data = *board_data;
1081 spin_lock_init(&lp->lock);
1082
1083 dev->base_addr = regs->start; /* physical base address */
1084 lp->emac_base = ioremap(regs->start, regs->end - regs->start + 1);
1085 if (!lp->emac_base) {
1086 res = -ENOMEM;
1087 goto err_free_dev;
1088 }
1089
1090 /* Clock */
1091 lp->ether_clk = clk_get(&pdev->dev, "ether_clk");
1092 if (IS_ERR(lp->ether_clk)) {
1093 res = PTR_ERR(lp->ether_clk);
1094 goto err_ioumap;
1095 }
1096 clk_enable(lp->ether_clk);
1097
1098 /* Install the interrupt handler */
1099 dev->irq = platform_get_irq(pdev, 0);
1100 if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) {
1101 res = -EBUSY;
1102 goto err_disable_clock;
1103 }
1104
1105 /* Allocate memory for DMA Receive descriptors */
1106 lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
1107 if (lp->dlist == NULL) {
1108 res = -ENOMEM;
1109 goto err_free_irq;
1110 }
1111
1112 ether_setup(dev);
1113 dev->netdev_ops = &at91ether_netdev_ops;
1114 dev->ethtool_ops = &at91ether_ethtool_ops;
1115 platform_set_drvdata(pdev, dev);
1116 SET_NETDEV_DEV(dev, &pdev->dev);
1117
1118 get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */
1119 update_mac_address(dev); /* Program ethernet address into MAC */
1120
1121 at91_emac_write(lp, MACB_NCR, 0);
1122
1123 if (board_data->is_rmii)
1124 at91_emac_write(lp, MACB_NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG) | MACB_BIT(RM9200_RMII));
1125 else
1126 at91_emac_write(lp, MACB_NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
1127
1128 /* Detect PHY */
1129 if (!at91ether_phy_detect(lp)) {
1130 printk(KERN_ERR "at91_ether: Could not detect ethernet PHY\n");
1131 res = -ENODEV;
1132 goto err_free_dmamem;
1133 }
1134
1135 initialize_phy(lp);
1136
1137 lp->mii.dev = dev; /* Support for ethtool */
1138 lp->mii.mdio_read = mdio_read;
1139 lp->mii.mdio_write = mdio_write;
1140 lp->mii.phy_id = lp->phy_address;
1141 lp->mii.phy_id_mask = 0x1f;
1142 lp->mii.reg_num_mask = 0x1f;
1143
1144 /* Register the network interface */
1145 res = register_netdev(dev);
1146 if (res)
1147 goto err_free_dmamem;
1148
1149 /* Determine current link speed */
1150 spin_lock_irq(&lp->lock);
1151 enable_mdi(lp);
1152 update_linkspeed(dev, 0);
1153 disable_mdi(lp);
1154 spin_unlock_irq(&lp->lock);
1155 netif_carrier_off(dev); /* will be enabled in open() */
1156
1157 /* If board has no PHY IRQ, use a timer to poll the PHY */
1158 if (gpio_is_valid(lp->board_data.phy_irq_pin)) {
1159 gpio_request(board_data->phy_irq_pin, "ethernet_phy");
1160 } else {
1161 /* If board has no PHY IRQ, use a timer to poll the PHY */
1162 init_timer(&lp->check_timer);
1163 lp->check_timer.data = (unsigned long)dev;
1164 lp->check_timer.function = at91ether_check_link;
1165 }
1166
1167 /* Display ethernet banner */
1168 printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%pM)\n",
1169 dev->name, (uint) dev->base_addr, dev->irq,
1170 at91_emac_read(lp, MACB_NCFGR) & MACB_BIT(SPD) ? "100-" : "10-",
1171 at91_emac_read(lp, MACB_NCFGR) & MACB_BIT(FD) ? "FullDuplex" : "HalfDuplex",
1172 dev->dev_addr);
1173 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID))
1174 printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
1175 else if (lp->phy_type == MII_LXT971A_ID)
1176 printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name);
1177 else if (lp->phy_type == MII_RTL8201_ID)
1178 printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name);
1179 else if (lp->phy_type == MII_BCM5221_ID)
1180 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
1181 else if (lp->phy_type == MII_DP83847_ID)
1182 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
1183 else if (lp->phy_type == MII_DP83848_ID)
1184 printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name);
1185 else if (lp->phy_type == MII_AC101L_ID)
1186 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
1187 else if (lp->phy_type == MII_KS8721_ID)
1188 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
1189 else if (lp->phy_type == MII_T78Q21x3_ID)
1190 printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name);
1191 else if (lp->phy_type == MII_LAN83C185_ID)
1192 printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name);
1193
1194 clk_disable(lp->ether_clk); /* Disable Peripheral clock */
1195
1196 return 0;
1197
1198
1199 err_free_dmamem:
1200 platform_set_drvdata(pdev, NULL);
1201 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1202 err_free_irq:
1203 free_irq(dev->irq, dev);
1204 err_disable_clock:
1205 clk_disable(lp->ether_clk);
1206 clk_put(lp->ether_clk);
1207 err_ioumap:
1208 iounmap(lp->emac_base);
1209 err_free_dev:
1210 free_netdev(dev);
1211 return res;
1212 }
1213
1214 static int __devexit at91ether_remove(struct platform_device *pdev)
1215 {
1216 struct net_device *dev = platform_get_drvdata(pdev);
1217 struct at91_private *lp = netdev_priv(dev);
1218
1219 if (gpio_is_valid(lp->board_data.phy_irq_pin))
1220 gpio_free(lp->board_data.phy_irq_pin);
1221
1222 unregister_netdev(dev);
1223 free_irq(dev->irq, dev);
1224 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1225 clk_put(lp->ether_clk);
1226
1227 platform_set_drvdata(pdev, NULL);
1228 free_netdev(dev);
1229 return 0;
1230 }
1231
1232 #ifdef CONFIG_PM
1233
1234 static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
1235 {
1236 struct net_device *net_dev = platform_get_drvdata(pdev);
1237 struct at91_private *lp = netdev_priv(net_dev);
1238
1239 if (netif_running(net_dev)) {
1240 if (gpio_is_valid(lp->board_data.phy_irq_pin)) {
1241 int phy_irq = gpio_to_irq(lp->board_data.phy_irq_pin);
1242 disable_irq(phy_irq);
1243 }
1244
1245 netif_stop_queue(net_dev);
1246 netif_device_detach(net_dev);
1247
1248 clk_disable(lp->ether_clk);
1249 }
1250 return 0;
1251 }
1252
1253 static int at91ether_resume(struct platform_device *pdev)
1254 {
1255 struct net_device *net_dev = platform_get_drvdata(pdev);
1256 struct at91_private *lp = netdev_priv(net_dev);
1257
1258 if (netif_running(net_dev)) {
1259 clk_enable(lp->ether_clk);
1260
1261 netif_device_attach(net_dev);
1262 netif_start_queue(net_dev);
1263
1264 if (gpio_is_valid(lp->board_data.phy_irq_pin)) {
1265 int phy_irq = gpio_to_irq(lp->board_data.phy_irq_pin);
1266 enable_irq(phy_irq);
1267 }
1268 }
1269 return 0;
1270 }
1271
1272 #else
1273 #define at91ether_suspend NULL
1274 #define at91ether_resume NULL
1275 #endif
1276
1277 static struct platform_driver at91ether_driver = {
1278 .remove = __devexit_p(at91ether_remove),
1279 .suspend = at91ether_suspend,
1280 .resume = at91ether_resume,
1281 .driver = {
1282 .name = DRV_NAME,
1283 .owner = THIS_MODULE,
1284 },
1285 };
1286
1287 static int __init at91ether_init(void)
1288 {
1289 return platform_driver_probe(&at91ether_driver, at91ether_probe);
1290 }
1291
1292 static void __exit at91ether_exit(void)
1293 {
1294 platform_driver_unregister(&at91ether_driver);
1295 }
1296
1297 module_init(at91ether_init)
1298 module_exit(at91ether_exit)
1299
1300 MODULE_LICENSE("GPL");
1301 MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
1302 MODULE_AUTHOR("Andrew Victor");
1303 MODULE_ALIAS("platform:" DRV_NAME);
kernel source for telekom puls (alcatel/mediatek)