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net/at91_ether: use pclk member instead of ether_clk
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / cadence / at91_ether.c
1 /*
2 * Ethernet driver for the Atmel AT91RM9200 (Thunder)
3 *
4 * Copyright (C) 2003 SAN People (Pty) Ltd
5 *
6 * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
7 * Initial version by Rick Bronson 01/11/2003
8 *
9 * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
10 * (Polaroid Corporation)
11 *
12 * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 */
19
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/mii.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/skbuff.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/ethtool.h>
29 #include <linux/platform_data/macb.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/gfp.h>
33 #include <linux/phy.h>
34
35 #include <asm/io.h>
36 #include <asm/uaccess.h>
37 #include <asm/mach-types.h>
38
39 #include <asm/gpio.h>
40 #include <mach/board.h>
41
42 #include "at91_ether.h"
43 #include "macb.h"
44
45 #define DRV_NAME "at91_ether"
46 #define DRV_VERSION "1.0"
47
48 #define LINK_POLL_INTERVAL (HZ)
49
50 /* ........................... PHY INTERFACE ........................... */
51
52 /*
53 * Enable the MDIO bit in MAC control register
54 * When not called from an interrupt-handler, access to the PHY must be
55 * protected by a spinlock.
56 */
57 static void enable_mdi(struct macb *lp)
58 {
59 unsigned long ctl;
60
61 ctl = macb_readl(lp, NCR);
62 macb_writel(lp, NCR, ctl | MACB_BIT(MPE)); /* enable management port */
63 }
64
65 /*
66 * Disable the MDIO bit in the MAC control register
67 */
68 static void disable_mdi(struct macb *lp)
69 {
70 unsigned long ctl;
71
72 ctl = macb_readl(lp, NCR);
73 macb_writel(lp, NCR, ctl & ~MACB_BIT(MPE)); /* disable management port */
74 }
75
76 /*
77 * Wait until the PHY operation is complete.
78 */
79 static inline void at91_phy_wait(struct macb *lp)
80 {
81 unsigned long timeout = jiffies + 2;
82
83 while (!(macb_readl(lp, NSR) & MACB_BIT(IDLE))) {
84 if (time_after(jiffies, timeout)) {
85 printk("at91_ether: MIO timeout\n");
86 break;
87 }
88 cpu_relax();
89 }
90 }
91
92 /*
93 * Write value to the a PHY register
94 * Note: MDI interface is assumed to already have been enabled.
95 */
96 static void write_phy(struct macb *lp, unsigned char phy_addr, unsigned char address, unsigned int value)
97 {
98 macb_writel(lp, MAN, MACB_BF(SOF, MACB_MAN_SOF) | MACB_BF(CODE, MACB_MAN_CODE)
99 | MACB_BF(RW, MACB_MAN_WRITE) | ((phy_addr & 0x1f) << 23)
100 | (address << 18) | (value & ((1<<MACB_DATA_SIZE) - 1)));
101
102 /* Wait until IDLE bit in Network Status register is cleared */
103 at91_phy_wait(lp);
104 }
105
106 /*
107 * Read value stored in a PHY register.
108 * Note: MDI interface is assumed to already have been enabled.
109 */
110 static void read_phy(struct macb *lp, unsigned char phy_addr, unsigned char address, unsigned int *value)
111 {
112 macb_writel(lp, MAN, MACB_BF(SOF, MACB_MAN_SOF) | MACB_BF(CODE, MACB_MAN_CODE)
113 | MACB_BF(RW, MACB_MAN_READ) | ((phy_addr & 0x1f) << 23)
114 | (address << 18));
115
116 /* Wait until IDLE bit in Network Status register is cleared */
117 at91_phy_wait(lp);
118
119 *value = macb_readl(lp, MAN) & ((1<<MACB_DATA_SIZE) - 1);
120 }
121
122 /* ........................... PHY MANAGEMENT .......................... */
123
124 /*
125 * Access the PHY to determine the current link speed and mode, and update the
126 * MAC accordingly.
127 * If no link or auto-negotiation is busy, then no changes are made.
128 */
129 static void update_linkspeed(struct net_device *dev, int silent)
130 {
131 struct macb *lp = netdev_priv(dev);
132 unsigned int bmsr, bmcr, lpa, mac_cfg;
133 unsigned int speed, duplex;
134
135 if (!mii_link_ok(&lp->mii)) { /* no link */
136 netif_carrier_off(dev);
137 if (!silent)
138 printk(KERN_INFO "%s: Link down.\n", dev->name);
139 return;
140 }
141
142 /* Link up, or auto-negotiation still in progress */
143 read_phy(lp, lp->phy_address, MII_BMSR, &bmsr);
144 read_phy(lp, lp->phy_address, MII_BMCR, &bmcr);
145 if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */
146 if (!(bmsr & BMSR_ANEGCOMPLETE))
147 return; /* Do nothing - another interrupt generated when negotiation complete */
148
149 read_phy(lp, lp->phy_address, MII_LPA, &lpa);
150 if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100;
151 else speed = SPEED_10;
152 if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL;
153 else duplex = DUPLEX_HALF;
154 } else {
155 speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
156 duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
157 }
158
159 /* Update the MAC */
160 mac_cfg = macb_readl(lp, NCFGR) & ~(MACB_BIT(SPD) | MACB_BIT(FD));
161 if (speed == SPEED_100) {
162 if (duplex == DUPLEX_FULL) /* 100 Full Duplex */
163 mac_cfg |= MACB_BIT(SPD) | MACB_BIT(FD);
164 else /* 100 Half Duplex */
165 mac_cfg |= MACB_BIT(SPD);
166 } else {
167 if (duplex == DUPLEX_FULL) /* 10 Full Duplex */
168 mac_cfg |= MACB_BIT(FD);
169 else {} /* 10 Half Duplex */
170 }
171 macb_writel(lp, NCFGR, mac_cfg);
172
173 if (!silent)
174 printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
175 netif_carrier_on(dev);
176 }
177
178 /*
179 * Handle interrupts from the PHY
180 */
181 static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id)
182 {
183 struct net_device *dev = (struct net_device *) dev_id;
184 struct macb *lp = netdev_priv(dev);
185 unsigned int phy;
186
187 /*
188 * This hander is triggered on both edges, but the PHY chips expect
189 * level-triggering. We therefore have to check if the PHY actually has
190 * an IRQ pending.
191 */
192 enable_mdi(lp);
193 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
194 read_phy(lp, lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */
195 if (!(phy & (1 << 0)))
196 goto done;
197 }
198 else if (lp->phy_type == MII_LXT971A_ID) {
199 read_phy(lp, lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */
200 if (!(phy & (1 << 2)))
201 goto done;
202 }
203 else if (lp->phy_type == MII_BCM5221_ID) {
204 read_phy(lp, lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */
205 if (!(phy & (1 << 0)))
206 goto done;
207 }
208 else if (lp->phy_type == MII_KS8721_ID) {
209 read_phy(lp, lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */
210 if (!(phy & ((1 << 2) | 1)))
211 goto done;
212 }
213 else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */
214 read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &phy);
215 if (!(phy & ((1 << 2) | 1)))
216 goto done;
217 }
218 else if (lp->phy_type == MII_DP83848_ID) {
219 read_phy(lp, lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */
220 if (!(phy & (1 << 7)))
221 goto done;
222 }
223
224 update_linkspeed(dev, 0);
225
226 done:
227 disable_mdi(lp);
228
229 return IRQ_HANDLED;
230 }
231
232 /*
233 * Initialize and enable the PHY interrupt for link-state changes
234 */
235 static void enable_phyirq(struct net_device *dev)
236 {
237 struct macb *lp = netdev_priv(dev);
238 unsigned int dsintr, irq_number;
239 int status;
240
241 if (!gpio_is_valid(lp->board_data.phy_irq_pin)) {
242 /*
243 * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
244 * or board does not have it connected.
245 */
246 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
247 return;
248 }
249
250 irq_number = gpio_to_irq(lp->board_data.phy_irq_pin);
251 status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev);
252 if (status) {
253 printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status);
254 return;
255 }
256
257 spin_lock_irq(&lp->lock);
258 enable_mdi(lp);
259
260 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
261 read_phy(lp, lp->phy_address, MII_DSINTR_REG, &dsintr);
262 dsintr = dsintr & ~0xf00; /* clear bits 8..11 */
263 write_phy(lp, lp->phy_address, MII_DSINTR_REG, dsintr);
264 }
265 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
266 read_phy(lp, lp->phy_address, MII_ISINTE_REG, &dsintr);
267 dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */
268 write_phy(lp, lp->phy_address, MII_ISINTE_REG, dsintr);
269 }
270 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
271 dsintr = (1 << 15) | ( 1 << 14);
272 write_phy(lp, lp->phy_address, MII_BCMINTR_REG, dsintr);
273 }
274 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
275 dsintr = (1 << 10) | ( 1 << 8);
276 write_phy(lp, lp->phy_address, MII_TPISTATUS, dsintr);
277 }
278 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
279 read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &dsintr);
280 dsintr = dsintr | 0x500; /* set bits 8, 10 */
281 write_phy(lp, lp->phy_address, MII_T78Q21INT_REG, dsintr);
282 }
283 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
284 read_phy(lp, lp->phy_address, MII_DPMISR_REG, &dsintr);
285 dsintr = dsintr | 0x3c; /* set bits 2..5 */
286 write_phy(lp, lp->phy_address, MII_DPMISR_REG, dsintr);
287 read_phy(lp, lp->phy_address, MII_DPMICR_REG, &dsintr);
288 dsintr = dsintr | 0x3; /* set bits 0,1 */
289 write_phy(lp, lp->phy_address, MII_DPMICR_REG, dsintr);
290 }
291
292 disable_mdi(lp);
293 spin_unlock_irq(&lp->lock);
294 }
295
296 /*
297 * Disable the PHY interrupt
298 */
299 static void disable_phyirq(struct net_device *dev)
300 {
301 struct macb *lp = netdev_priv(dev);
302 unsigned int dsintr;
303 unsigned int irq_number;
304
305 if (!gpio_is_valid(lp->board_data.phy_irq_pin)) {
306 del_timer_sync(&lp->check_timer);
307 return;
308 }
309
310 spin_lock_irq(&lp->lock);
311 enable_mdi(lp);
312
313 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
314 read_phy(lp, lp->phy_address, MII_DSINTR_REG, &dsintr);
315 dsintr = dsintr | 0xf00; /* set bits 8..11 */
316 write_phy(lp, lp->phy_address, MII_DSINTR_REG, dsintr);
317 }
318 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
319 read_phy(lp, lp->phy_address, MII_ISINTE_REG, &dsintr);
320 dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */
321 write_phy(lp, lp->phy_address, MII_ISINTE_REG, dsintr);
322 }
323 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
324 read_phy(lp, lp->phy_address, MII_BCMINTR_REG, &dsintr);
325 dsintr = ~(1 << 14);
326 write_phy(lp, lp->phy_address, MII_BCMINTR_REG, dsintr);
327 }
328 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
329 read_phy(lp, lp->phy_address, MII_TPISTATUS, &dsintr);
330 dsintr = ~((1 << 10) | (1 << 8));
331 write_phy(lp, lp->phy_address, MII_TPISTATUS, dsintr);
332 }
333 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
334 read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &dsintr);
335 dsintr = dsintr & ~0x500; /* clear bits 8, 10 */
336 write_phy(lp, lp->phy_address, MII_T78Q21INT_REG, dsintr);
337 }
338 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
339 read_phy(lp, lp->phy_address, MII_DPMICR_REG, &dsintr);
340 dsintr = dsintr & ~0x3; /* clear bits 0, 1 */
341 write_phy(lp, lp->phy_address, MII_DPMICR_REG, dsintr);
342 read_phy(lp, lp->phy_address, MII_DPMISR_REG, &dsintr);
343 dsintr = dsintr & ~0x3c; /* clear bits 2..5 */
344 write_phy(lp, lp->phy_address, MII_DPMISR_REG, dsintr);
345 }
346
347 disable_mdi(lp);
348 spin_unlock_irq(&lp->lock);
349
350 irq_number = gpio_to_irq(lp->board_data.phy_irq_pin);
351 free_irq(irq_number, dev); /* Free interrupt handler */
352 }
353
354 /*
355 * Perform a software reset of the PHY.
356 */
357 #if 0
358 static void reset_phy(struct net_device *dev)
359 {
360 struct macb *lp = netdev_priv(dev);
361 unsigned int bmcr;
362
363 spin_lock_irq(&lp->lock);
364 enable_mdi(lp);
365
366 /* Perform PHY reset */
367 write_phy(lp, lp->phy_address, MII_BMCR, BMCR_RESET);
368
369 /* Wait until PHY reset is complete */
370 do {
371 read_phy(lp, lp->phy_address, MII_BMCR, &bmcr);
372 } while (!(bmcr & BMCR_RESET));
373
374 disable_mdi(lp);
375 spin_unlock_irq(&lp->lock);
376 }
377 #endif
378
379 static void at91ether_check_link(unsigned long dev_id)
380 {
381 struct net_device *dev = (struct net_device *) dev_id;
382 struct macb *lp = netdev_priv(dev);
383
384 enable_mdi(lp);
385 update_linkspeed(dev, 1);
386 disable_mdi(lp);
387
388 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
389 }
390
391 /*
392 * Perform any PHY-specific initialization.
393 */
394 static void __init initialize_phy(struct macb *lp)
395 {
396 unsigned int val;
397
398 spin_lock_irq(&lp->lock);
399 enable_mdi(lp);
400
401 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
402 read_phy(lp, lp->phy_address, MII_DSCR_REG, &val);
403 if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */
404 lp->phy_media = PORT_FIBRE;
405 } else if (machine_is_csb337()) {
406 /* mix link activity status into LED2 link state */
407 write_phy(lp, lp->phy_address, MII_LEDCTRL_REG, 0x0d22);
408 } else if (machine_is_ecbat91())
409 write_phy(lp, lp->phy_address, MII_LEDCTRL_REG, 0x156A);
410
411 disable_mdi(lp);
412 spin_unlock_irq(&lp->lock);
413 }
414
415 /* ......................... ADDRESS MANAGEMENT ........................ */
416
417 /*
418 * NOTE: Your bootloader must always set the MAC address correctly before
419 * booting into Linux.
420 *
421 * - It must always set the MAC address after reset, even if it doesn't
422 * happen to access the Ethernet while it's booting. Some versions of
423 * U-Boot on the AT91RM9200-DK do not do this.
424 *
425 * - Likewise it must store the addresses in the correct byte order.
426 * MicroMonitor (uMon) on the CSB337 does this incorrectly (and
427 * continues to do so, for bug-compatibility).
428 */
429
430 static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo)
431 {
432 char addr[6];
433
434 if (machine_is_csb337()) {
435 addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */
436 addr[4] = (lo & 0xff00) >> 8;
437 addr[3] = (lo & 0xff0000) >> 16;
438 addr[2] = (lo & 0xff000000) >> 24;
439 addr[1] = (hi & 0xff);
440 addr[0] = (hi & 0xff00) >> 8;
441 }
442 else {
443 addr[0] = (lo & 0xff);
444 addr[1] = (lo & 0xff00) >> 8;
445 addr[2] = (lo & 0xff0000) >> 16;
446 addr[3] = (lo & 0xff000000) >> 24;
447 addr[4] = (hi & 0xff);
448 addr[5] = (hi & 0xff00) >> 8;
449 }
450
451 if (is_valid_ether_addr(addr)) {
452 memcpy(dev->dev_addr, &addr, 6);
453 return 1;
454 }
455 return 0;
456 }
457
458 /*
459 * Set the ethernet MAC address in dev->dev_addr
460 */
461 static void __init get_mac_address(struct net_device *dev)
462 {
463 struct macb *lp = netdev_priv(dev);
464
465 /* Check Specific-Address 1 */
466 if (unpack_mac_address(dev, macb_readl(lp, SA1T), macb_readl(lp, SA1B)))
467 return;
468 /* Check Specific-Address 2 */
469 if (unpack_mac_address(dev, macb_readl(lp, SA2T), macb_readl(lp, SA2B)))
470 return;
471 /* Check Specific-Address 3 */
472 if (unpack_mac_address(dev, macb_readl(lp, SA3T), macb_readl(lp, SA3B)))
473 return;
474 /* Check Specific-Address 4 */
475 if (unpack_mac_address(dev, macb_readl(lp, SA4T), macb_readl(lp, SA4B)))
476 return;
477
478 printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n");
479 }
480
481 /*
482 * Program the hardware MAC address from dev->dev_addr.
483 */
484 static void update_mac_address(struct net_device *dev)
485 {
486 struct macb *lp = netdev_priv(dev);
487
488 macb_writel(lp, SA1B, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16)
489 | (dev->dev_addr[1] << 8) | (dev->dev_addr[0]));
490 macb_writel(lp, SA1T, (dev->dev_addr[5] << 8) | (dev->dev_addr[4]));
491
492 macb_writel(lp, SA2B, 0);
493 macb_writel(lp, SA2T, 0);
494 }
495
496 /*
497 * Store the new hardware address in dev->dev_addr, and update the MAC.
498 */
499 static int set_mac_address(struct net_device *dev, void* addr)
500 {
501 struct sockaddr *address = addr;
502
503 if (!is_valid_ether_addr(address->sa_data))
504 return -EADDRNOTAVAIL;
505
506 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
507 update_mac_address(dev);
508
509 printk("%s: Setting MAC address to %pM\n", dev->name,
510 dev->dev_addr);
511
512 return 0;
513 }
514
515 static int inline hash_bit_value(int bitnr, __u8 *addr)
516 {
517 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
518 return 1;
519 return 0;
520 }
521
522 /*
523 * The hash address register is 64 bits long and takes up two locations in the memory map.
524 * The least significant bits are stored in EMAC_HSL and the most significant
525 * bits in EMAC_HSH.
526 *
527 * The unicast hash enable and the multicast hash enable bits in the network configuration
528 * register enable the reception of hash matched frames. The destination address is
529 * reduced to a 6 bit index into the 64 bit hash register using the following hash function.
530 * The hash function is an exclusive or of every sixth bit of the destination address.
531 * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
532 * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
533 * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
534 * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
535 * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
536 * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
537 * da[0] represents the least significant bit of the first byte received, that is, the multicast/
538 * unicast indicator, and da[47] represents the most significant bit of the last byte
539 * received.
540 * If the hash index points to a bit that is set in the hash register then the frame will be
541 * matched according to whether the frame is multicast or unicast.
542 * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and
543 * the hash index points to a bit set in the hash register.
544 * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the
545 * hash index points to a bit set in the hash register.
546 * To receive all multicast frames, the hash register should be set with all ones and the
547 * multicast hash enable bit should be set in the network configuration register.
548 */
549
550 /*
551 * Return the hash index value for the specified address.
552 */
553 static int hash_get_index(__u8 *addr)
554 {
555 int i, j, bitval;
556 int hash_index = 0;
557
558 for (j = 0; j < 6; j++) {
559 for (i = 0, bitval = 0; i < 8; i++)
560 bitval ^= hash_bit_value(i*6 + j, addr);
561
562 hash_index |= (bitval << j);
563 }
564
565 return hash_index;
566 }
567
568 /*
569 * Add multicast addresses to the internal multicast-hash table.
570 */
571 static void at91ether_sethashtable(struct net_device *dev)
572 {
573 struct macb *lp = netdev_priv(dev);
574 struct netdev_hw_addr *ha;
575 unsigned long mc_filter[2];
576 unsigned int bitnr;
577
578 mc_filter[0] = mc_filter[1] = 0;
579
580 netdev_for_each_mc_addr(ha, dev) {
581 bitnr = hash_get_index(ha->addr);
582 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
583 }
584
585 macb_writel(lp, HRB, mc_filter[0]);
586 macb_writel(lp, HRT, mc_filter[1]);
587 }
588
589 /*
590 * Enable/Disable promiscuous and multicast modes.
591 */
592 static void at91ether_set_multicast_list(struct net_device *dev)
593 {
594 struct macb *lp = netdev_priv(dev);
595 unsigned long cfg;
596
597 cfg = macb_readl(lp, NCFGR);
598
599 if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */
600 cfg |= MACB_BIT(CAF);
601 else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */
602 cfg &= ~MACB_BIT(CAF);
603
604 if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */
605 macb_writel(lp, HRT, -1);
606 macb_writel(lp, HRB, -1);
607 cfg |= MACB_BIT(NCFGR_MTI);
608 } else if (!netdev_mc_empty(dev)) { /* Enable specific multicasts */
609 at91ether_sethashtable(dev);
610 cfg |= MACB_BIT(NCFGR_MTI);
611 } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */
612 macb_writel(lp, HRT, 0);
613 macb_writel(lp, HRB, 0);
614 cfg &= ~MACB_BIT(NCFGR_MTI);
615 }
616
617 macb_writel(lp, NCFGR, cfg);
618 }
619
620 /* ......................... ETHTOOL SUPPORT ........................... */
621
622 static int mdio_read(struct net_device *dev, int phy_id, int location)
623 {
624 struct macb *lp = netdev_priv(dev);
625 unsigned int value;
626
627 read_phy(lp, phy_id, location, &value);
628 return value;
629 }
630
631 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
632 {
633 struct macb *lp = netdev_priv(dev);
634
635 write_phy(lp, phy_id, location, value);
636 }
637
638 static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
639 {
640 struct macb *lp = netdev_priv(dev);
641 int ret;
642
643 spin_lock_irq(&lp->lock);
644 enable_mdi(lp);
645
646 ret = mii_ethtool_gset(&lp->mii, cmd);
647
648 disable_mdi(lp);
649 spin_unlock_irq(&lp->lock);
650
651 if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */
652 cmd->supported = SUPPORTED_FIBRE;
653 cmd->port = PORT_FIBRE;
654 }
655
656 return ret;
657 }
658
659 static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
660 {
661 struct macb *lp = netdev_priv(dev);
662 int ret;
663
664 spin_lock_irq(&lp->lock);
665 enable_mdi(lp);
666
667 ret = mii_ethtool_sset(&lp->mii, cmd);
668
669 disable_mdi(lp);
670 spin_unlock_irq(&lp->lock);
671
672 return ret;
673 }
674
675 static int at91ether_nwayreset(struct net_device *dev)
676 {
677 struct macb *lp = netdev_priv(dev);
678 int ret;
679
680 spin_lock_irq(&lp->lock);
681 enable_mdi(lp);
682
683 ret = mii_nway_restart(&lp->mii);
684
685 disable_mdi(lp);
686 spin_unlock_irq(&lp->lock);
687
688 return ret;
689 }
690
691 static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
692 {
693 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
694 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
695 strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
696 }
697
698 static const struct ethtool_ops at91ether_ethtool_ops = {
699 .get_settings = at91ether_get_settings,
700 .set_settings = at91ether_set_settings,
701 .get_drvinfo = at91ether_get_drvinfo,
702 .nway_reset = at91ether_nwayreset,
703 .get_link = ethtool_op_get_link,
704 };
705
706 static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
707 {
708 struct macb *lp = netdev_priv(dev);
709 int res;
710
711 if (!netif_running(dev))
712 return -EINVAL;
713
714 spin_lock_irq(&lp->lock);
715 enable_mdi(lp);
716 res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL);
717 disable_mdi(lp);
718 spin_unlock_irq(&lp->lock);
719
720 return res;
721 }
722
723 /* ................................ MAC ................................ */
724
725 /*
726 * Initialize and start the Receiver and Transmit subsystems
727 */
728 static void at91ether_start(struct net_device *dev)
729 {
730 struct macb *lp = netdev_priv(dev);
731 struct recv_desc_bufs *dlist, *dlist_phys;
732 int i;
733 unsigned long ctl;
734
735 dlist = lp->dlist;
736 dlist_phys = lp->dlist_phys;
737
738 for (i = 0; i < MAX_RX_DESCR; i++) {
739 dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0];
740 dlist->descriptors[i].size = 0;
741 }
742
743 /* Set the Wrap bit on the last descriptor */
744 dlist->descriptors[i-1].addr |= MACB_BIT(RX_WRAP);
745
746 /* Reset buffer index */
747 lp->rxBuffIndex = 0;
748
749 /* Program address of descriptor list in Rx Buffer Queue register */
750 macb_writel(lp, RBQP, (unsigned long) dlist_phys);
751
752 /* Enable Receive and Transmit */
753 ctl = macb_readl(lp, NCR);
754 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
755 }
756
757 /*
758 * Open the ethernet interface
759 */
760 static int at91ether_open(struct net_device *dev)
761 {
762 struct macb *lp = netdev_priv(dev);
763 unsigned long ctl;
764
765 if (!is_valid_ether_addr(dev->dev_addr))
766 return -EADDRNOTAVAIL;
767
768 clk_enable(lp->pclk); /* Re-enable Peripheral clock */
769
770 /* Clear internal statistics */
771 ctl = macb_readl(lp, NCR);
772 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
773
774 /* Update the MAC address (incase user has changed it) */
775 update_mac_address(dev);
776
777 /* Enable PHY interrupt */
778 enable_phyirq(dev);
779
780 /* Enable MAC interrupts */
781 macb_writel(lp, IER, MACB_BIT(RCOMP) | MACB_BIT(RXUBR)
782 | MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE) | MACB_BIT(TCOMP)
783 | MACB_BIT(ISR_ROVR) | MACB_BIT(HRESP));
784
785 /* Determine current link speed */
786 spin_lock_irq(&lp->lock);
787 enable_mdi(lp);
788 update_linkspeed(dev, 0);
789 disable_mdi(lp);
790 spin_unlock_irq(&lp->lock);
791
792 at91ether_start(dev);
793 netif_start_queue(dev);
794 return 0;
795 }
796
797 /*
798 * Close the interface
799 */
800 static int at91ether_close(struct net_device *dev)
801 {
802 struct macb *lp = netdev_priv(dev);
803 unsigned long ctl;
804
805 /* Disable Receiver and Transmitter */
806 ctl = macb_readl(lp, NCR);
807 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
808
809 /* Disable PHY interrupt */
810 disable_phyirq(dev);
811
812 /* Disable MAC interrupts */
813 macb_writel(lp, IDR, MACB_BIT(RCOMP) | MACB_BIT(RXUBR)
814 | MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)
815 | MACB_BIT(TCOMP) | MACB_BIT(ISR_ROVR)
816 | MACB_BIT(HRESP));
817
818 netif_stop_queue(dev);
819
820 clk_disable(lp->pclk); /* Disable Peripheral clock */
821
822 return 0;
823 }
824
825 /*
826 * Transmit packet.
827 */
828 static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
829 {
830 struct macb *lp = netdev_priv(dev);
831
832 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
833 netif_stop_queue(dev);
834
835 /* Store packet information (to free when Tx completed) */
836 lp->skb = skb;
837 lp->skb_length = skb->len;
838 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
839 dev->stats.tx_bytes += skb->len;
840
841 /* Set address of the data in the Transmit Address register */
842 macb_writel(lp, TAR, lp->skb_physaddr);
843 /* Set length of the packet in the Transmit Control register */
844 macb_writel(lp, TCR, skb->len);
845
846 } else {
847 printk(KERN_ERR "at91_ether.c: at91ether_start_xmit() called, but device is busy!\n");
848 return NETDEV_TX_BUSY; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
849 on this skb, he also reports -ENETDOWN and printk's, so either
850 we free and return(0) or don't free and return 1 */
851 }
852
853 return NETDEV_TX_OK;
854 }
855
856 /*
857 * Update the current statistics from the internal statistics registers.
858 */
859 static struct net_device_stats *at91ether_stats(struct net_device *dev)
860 {
861 struct macb *lp = netdev_priv(dev);
862 int ale, lenerr, seqe, lcol, ecol;
863
864 if (netif_running(dev)) {
865 dev->stats.rx_packets += macb_readl(lp, FRO); /* Good frames received */
866 ale = macb_readl(lp, ALE);
867 dev->stats.rx_frame_errors += ale; /* Alignment errors */
868 lenerr = macb_readl(lp, ELE) + macb_readl(lp, USF);
869 dev->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */
870 seqe = macb_readl(lp, FCSE);
871 dev->stats.rx_crc_errors += seqe; /* CRC error */
872 dev->stats.rx_fifo_errors += macb_readl(lp, RRE);/* Receive buffer not available */
873 dev->stats.rx_errors += (ale + lenerr + seqe
874 + macb_readl(lp, RSE) + macb_readl(lp, RJA));
875
876 dev->stats.tx_packets += macb_readl(lp, FTO); /* Frames successfully transmitted */
877 dev->stats.tx_fifo_errors += macb_readl(lp, TUND); /* Transmit FIFO underruns */
878 dev->stats.tx_carrier_errors += macb_readl(lp, CSE); /* Carrier Sense errors */
879 dev->stats.tx_heartbeat_errors += macb_readl(lp, STE);/* Heartbeat error */
880
881 lcol = macb_readl(lp, LCOL);
882 ecol = macb_readl(lp, EXCOL);
883 dev->stats.tx_window_errors += lcol; /* Late collisions */
884 dev->stats.tx_aborted_errors += ecol; /* 16 collisions */
885
886 dev->stats.collisions += (macb_readl(lp, SCF) + macb_readl(lp, MCF) + lcol + ecol);
887 }
888 return &dev->stats;
889 }
890
891 /*
892 * Extract received frame from buffer descriptors and sent to upper layers.
893 * (Called from interrupt context)
894 */
895 static void at91ether_rx(struct net_device *dev)
896 {
897 struct macb *lp = netdev_priv(dev);
898 struct recv_desc_bufs *dlist;
899 unsigned char *p_recv;
900 struct sk_buff *skb;
901 unsigned int pktlen;
902
903 dlist = lp->dlist;
904 while (dlist->descriptors[lp->rxBuffIndex].addr & MACB_BIT(RX_USED)) {
905 p_recv = dlist->recv_buf[lp->rxBuffIndex];
906 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */
907 skb = netdev_alloc_skb(dev, pktlen + 2);
908 if (skb != NULL) {
909 skb_reserve(skb, 2);
910 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
911
912 skb->protocol = eth_type_trans(skb, dev);
913 dev->stats.rx_bytes += pktlen;
914 netif_rx(skb);
915 }
916 else {
917 dev->stats.rx_dropped += 1;
918 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
919 }
920
921 if (dlist->descriptors[lp->rxBuffIndex].size & MACB_BIT(RX_MHASH_MATCH))
922 dev->stats.multicast++;
923
924 dlist->descriptors[lp->rxBuffIndex].addr &= ~MACB_BIT(RX_USED); /* reset ownership bit */
925 if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */
926 lp->rxBuffIndex = 0;
927 else
928 lp->rxBuffIndex++;
929 }
930 }
931
932 /*
933 * MAC interrupt handler
934 */
935 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
936 {
937 struct net_device *dev = (struct net_device *) dev_id;
938 struct macb *lp = netdev_priv(dev);
939 unsigned long intstatus, ctl;
940
941 /* MAC Interrupt Status register indicates what interrupts are pending.
942 It is automatically cleared once read. */
943 intstatus = macb_readl(lp, ISR);
944
945 if (intstatus & MACB_BIT(RCOMP)) /* Receive complete */
946 at91ether_rx(dev);
947
948 if (intstatus & MACB_BIT(TCOMP)) { /* Transmit complete */
949 /* The TCOM bit is set even if the transmission failed. */
950 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
951 dev->stats.tx_errors += 1;
952
953 if (lp->skb) {
954 dev_kfree_skb_irq(lp->skb);
955 lp->skb = NULL;
956 dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE);
957 }
958 netif_wake_queue(dev);
959 }
960
961 /* Work-around for Errata #11 */
962 if (intstatus & MACB_BIT(RXUBR)) {
963 ctl = macb_readl(lp, NCR);
964 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
965 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
966 }
967
968 if (intstatus & MACB_BIT(ISR_ROVR))
969 printk("%s: ROVR error\n", dev->name);
970
971 return IRQ_HANDLED;
972 }
973
974 #ifdef CONFIG_NET_POLL_CONTROLLER
975 static void at91ether_poll_controller(struct net_device *dev)
976 {
977 unsigned long flags;
978
979 local_irq_save(flags);
980 at91ether_interrupt(dev->irq, dev);
981 local_irq_restore(flags);
982 }
983 #endif
984
985 static const struct net_device_ops at91ether_netdev_ops = {
986 .ndo_open = at91ether_open,
987 .ndo_stop = at91ether_close,
988 .ndo_start_xmit = at91ether_start_xmit,
989 .ndo_get_stats = at91ether_stats,
990 .ndo_set_rx_mode = at91ether_set_multicast_list,
991 .ndo_set_mac_address = set_mac_address,
992 .ndo_do_ioctl = at91ether_ioctl,
993 .ndo_validate_addr = eth_validate_addr,
994 .ndo_change_mtu = eth_change_mtu,
995 #ifdef CONFIG_NET_POLL_CONTROLLER
996 .ndo_poll_controller = at91ether_poll_controller,
997 #endif
998 };
999
1000 /*
1001 * Detect the PHY type, and its address.
1002 */
1003 static int __init at91ether_phy_detect(struct macb *lp)
1004 {
1005 unsigned int phyid1, phyid2;
1006 unsigned long phy_id;
1007 unsigned short phy_address = 0;
1008
1009 while (phy_address < PHY_MAX_ADDR) {
1010 /* Read the PHY ID registers */
1011 enable_mdi(lp);
1012 read_phy(lp, phy_address, MII_PHYSID1, &phyid1);
1013 read_phy(lp, phy_address, MII_PHYSID2, &phyid2);
1014 disable_mdi(lp);
1015
1016 phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
1017 switch (phy_id) {
1018 case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
1019 case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
1020 case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */
1021 case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
1022 case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
1023 case MII_DP83847_ID: /* National Semiconductor DP83847: */
1024 case MII_DP83848_ID: /* National Semiconductor DP83848: */
1025 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
1026 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
1027 case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
1028 case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
1029 /* store detected values */
1030 lp->phy_type = phy_id; /* Type of PHY connected */
1031 lp->phy_address = phy_address; /* MDI address of PHY */
1032 return 1;
1033 }
1034
1035 phy_address++;
1036 }
1037
1038 return 0; /* not detected */
1039 }
1040
1041
1042 /*
1043 * Detect MAC & PHY and perform ethernet interface initialization
1044 */
1045 static int __init at91ether_probe(struct platform_device *pdev)
1046 {
1047 struct macb_platform_data *board_data = pdev->dev.platform_data;
1048 struct resource *regs;
1049 struct net_device *dev;
1050 struct macb *lp;
1051 int res;
1052
1053 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1054 if (!regs)
1055 return -ENOENT;
1056
1057 dev = alloc_etherdev(sizeof(struct macb));
1058 if (!dev)
1059 return -ENOMEM;
1060
1061 lp = netdev_priv(dev);
1062 lp->board_data = *board_data;
1063 spin_lock_init(&lp->lock);
1064
1065 dev->base_addr = regs->start; /* physical base address */
1066 lp->regs = ioremap(regs->start, regs->end - regs->start + 1);
1067 if (!lp->regs) {
1068 res = -ENOMEM;
1069 goto err_free_dev;
1070 }
1071
1072 /* Clock */
1073 lp->pclk = clk_get(&pdev->dev, "ether_clk");
1074 if (IS_ERR(lp->pclk)) {
1075 res = PTR_ERR(lp->pclk);
1076 goto err_ioumap;
1077 }
1078 clk_enable(lp->pclk);
1079
1080 /* Install the interrupt handler */
1081 dev->irq = platform_get_irq(pdev, 0);
1082 if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) {
1083 res = -EBUSY;
1084 goto err_disable_clock;
1085 }
1086
1087 /* Allocate memory for DMA Receive descriptors */
1088 lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
1089 if (lp->dlist == NULL) {
1090 res = -ENOMEM;
1091 goto err_free_irq;
1092 }
1093
1094 ether_setup(dev);
1095 dev->netdev_ops = &at91ether_netdev_ops;
1096 dev->ethtool_ops = &at91ether_ethtool_ops;
1097 platform_set_drvdata(pdev, dev);
1098 SET_NETDEV_DEV(dev, &pdev->dev);
1099
1100 get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */
1101 update_mac_address(dev); /* Program ethernet address into MAC */
1102
1103 macb_writel(lp, NCR, 0);
1104
1105 if (board_data->is_rmii)
1106 macb_writel(lp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG) | MACB_BIT(RM9200_RMII));
1107 else
1108 macb_writel(lp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
1109
1110 /* Detect PHY */
1111 if (!at91ether_phy_detect(lp)) {
1112 printk(KERN_ERR "at91_ether: Could not detect ethernet PHY\n");
1113 res = -ENODEV;
1114 goto err_free_dmamem;
1115 }
1116
1117 initialize_phy(lp);
1118
1119 lp->mii.dev = dev; /* Support for ethtool */
1120 lp->mii.mdio_read = mdio_read;
1121 lp->mii.mdio_write = mdio_write;
1122 lp->mii.phy_id = lp->phy_address;
1123 lp->mii.phy_id_mask = 0x1f;
1124 lp->mii.reg_num_mask = 0x1f;
1125
1126 /* Register the network interface */
1127 res = register_netdev(dev);
1128 if (res)
1129 goto err_free_dmamem;
1130
1131 /* Determine current link speed */
1132 spin_lock_irq(&lp->lock);
1133 enable_mdi(lp);
1134 update_linkspeed(dev, 0);
1135 disable_mdi(lp);
1136 spin_unlock_irq(&lp->lock);
1137 netif_carrier_off(dev); /* will be enabled in open() */
1138
1139 /* If board has no PHY IRQ, use a timer to poll the PHY */
1140 if (gpio_is_valid(lp->board_data.phy_irq_pin)) {
1141 gpio_request(board_data->phy_irq_pin, "ethernet_phy");
1142 } else {
1143 /* If board has no PHY IRQ, use a timer to poll the PHY */
1144 init_timer(&lp->check_timer);
1145 lp->check_timer.data = (unsigned long)dev;
1146 lp->check_timer.function = at91ether_check_link;
1147 }
1148
1149 /* Display ethernet banner */
1150 printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%pM)\n",
1151 dev->name, (uint) dev->base_addr, dev->irq,
1152 macb_readl(lp, NCFGR) & MACB_BIT(SPD) ? "100-" : "10-",
1153 macb_readl(lp, NCFGR) & MACB_BIT(FD) ? "FullDuplex" : "HalfDuplex",
1154 dev->dev_addr);
1155 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID))
1156 printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
1157 else if (lp->phy_type == MII_LXT971A_ID)
1158 printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name);
1159 else if (lp->phy_type == MII_RTL8201_ID)
1160 printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name);
1161 else if (lp->phy_type == MII_BCM5221_ID)
1162 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
1163 else if (lp->phy_type == MII_DP83847_ID)
1164 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
1165 else if (lp->phy_type == MII_DP83848_ID)
1166 printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name);
1167 else if (lp->phy_type == MII_AC101L_ID)
1168 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
1169 else if (lp->phy_type == MII_KS8721_ID)
1170 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
1171 else if (lp->phy_type == MII_T78Q21x3_ID)
1172 printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name);
1173 else if (lp->phy_type == MII_LAN83C185_ID)
1174 printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name);
1175
1176 clk_disable(lp->pclk); /* Disable Peripheral clock */
1177
1178 return 0;
1179
1180
1181 err_free_dmamem:
1182 platform_set_drvdata(pdev, NULL);
1183 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1184 err_free_irq:
1185 free_irq(dev->irq, dev);
1186 err_disable_clock:
1187 clk_disable(lp->pclk);
1188 clk_put(lp->pclk);
1189 err_ioumap:
1190 iounmap(lp->regs);
1191 err_free_dev:
1192 free_netdev(dev);
1193 return res;
1194 }
1195
1196 static int __devexit at91ether_remove(struct platform_device *pdev)
1197 {
1198 struct net_device *dev = platform_get_drvdata(pdev);
1199 struct macb *lp = netdev_priv(dev);
1200
1201 if (gpio_is_valid(lp->board_data.phy_irq_pin))
1202 gpio_free(lp->board_data.phy_irq_pin);
1203
1204 unregister_netdev(dev);
1205 free_irq(dev->irq, dev);
1206 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1207 clk_put(lp->pclk);
1208
1209 platform_set_drvdata(pdev, NULL);
1210 free_netdev(dev);
1211 return 0;
1212 }
1213
1214 #ifdef CONFIG_PM
1215
1216 static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
1217 {
1218 struct net_device *net_dev = platform_get_drvdata(pdev);
1219 struct macb *lp = netdev_priv(net_dev);
1220
1221 if (netif_running(net_dev)) {
1222 if (gpio_is_valid(lp->board_data.phy_irq_pin)) {
1223 int phy_irq = gpio_to_irq(lp->board_data.phy_irq_pin);
1224 disable_irq(phy_irq);
1225 }
1226
1227 netif_stop_queue(net_dev);
1228 netif_device_detach(net_dev);
1229
1230 clk_disable(lp->pclk);
1231 }
1232 return 0;
1233 }
1234
1235 static int at91ether_resume(struct platform_device *pdev)
1236 {
1237 struct net_device *net_dev = platform_get_drvdata(pdev);
1238 struct macb *lp = netdev_priv(net_dev);
1239
1240 if (netif_running(net_dev)) {
1241 clk_enable(lp->pclk);
1242
1243 netif_device_attach(net_dev);
1244 netif_start_queue(net_dev);
1245
1246 if (gpio_is_valid(lp->board_data.phy_irq_pin)) {
1247 int phy_irq = gpio_to_irq(lp->board_data.phy_irq_pin);
1248 enable_irq(phy_irq);
1249 }
1250 }
1251 return 0;
1252 }
1253
1254 #else
1255 #define at91ether_suspend NULL
1256 #define at91ether_resume NULL
1257 #endif
1258
1259 static struct platform_driver at91ether_driver = {
1260 .remove = __devexit_p(at91ether_remove),
1261 .suspend = at91ether_suspend,
1262 .resume = at91ether_resume,
1263 .driver = {
1264 .name = DRV_NAME,
1265 .owner = THIS_MODULE,
1266 },
1267 };
1268
1269 static int __init at91ether_init(void)
1270 {
1271 return platform_driver_probe(&at91ether_driver, at91ether_probe);
1272 }
1273
1274 static void __exit at91ether_exit(void)
1275 {
1276 platform_driver_unregister(&at91ether_driver);
1277 }
1278
1279 module_init(at91ether_init)
1280 module_exit(at91ether_exit)
1281
1282 MODULE_LICENSE("GPL");
1283 MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
1284 MODULE_AUTHOR("Andrew Victor");
1285 MODULE_ALIAS("platform:" DRV_NAME);
kernel source for telekom puls (alcatel/mediatek)