2 * Linux network driver for Brocade Converged Network Adapter.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
18 #include <linux/bitops.h>
19 #include <linux/netdevice.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_vlan.h>
25 #include <linux/if_ether.h>
27 #include <linux/prefetch.h>
33 static DEFINE_MUTEX(bnad_fwimg_mutex
);
38 static uint bnad_msix_disable
;
39 module_param(bnad_msix_disable
, uint
, 0444);
40 MODULE_PARM_DESC(bnad_msix_disable
, "Disable MSIX mode");
42 static uint bnad_ioc_auto_recover
= 1;
43 module_param(bnad_ioc_auto_recover
, uint
, 0444);
44 MODULE_PARM_DESC(bnad_ioc_auto_recover
, "Enable / Disable auto recovery");
49 u32 bnad_rxqs_per_cq
= 2;
51 static const u8 bnad_bcast_addr
[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
56 #define BNAD_TX_UNMAPQ_DEPTH (bnad->txq_depth * 2)
58 #define BNAD_RX_UNMAPQ_DEPTH (bnad->rxq_depth)
60 #define BNAD_GET_MBOX_IRQ(_bnad) \
61 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
62 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
63 ((_bnad)->pcidev->irq))
65 #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _depth) \
67 (_res_info)->res_type = BNA_RES_T_MEM; \
68 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
69 (_res_info)->res_u.mem_info.num = (_num); \
70 (_res_info)->res_u.mem_info.len = \
71 sizeof(struct bnad_unmap_q) + \
72 (sizeof(struct bnad_skb_unmap) * ((_depth) - 1)); \
75 #define BNAD_TXRX_SYNC_MDELAY 250 /* 250 msecs */
78 * Reinitialize completions in CQ, once Rx is taken down
81 bnad_cq_cmpl_init(struct bnad
*bnad
, struct bna_ccb
*ccb
)
83 struct bna_cq_entry
*cmpl
, *next_cmpl
;
84 unsigned int wi_range
, wis
= 0, ccb_prod
= 0;
87 BNA_CQ_QPGE_PTR_GET(ccb_prod
, ccb
->sw_qpt
, cmpl
,
90 for (i
= 0; i
< ccb
->q_depth
; i
++) {
92 if (likely(--wi_range
))
95 BNA_QE_INDX_ADD(ccb_prod
, wis
, ccb
->q_depth
);
97 BNA_CQ_QPGE_PTR_GET(ccb_prod
, ccb
->sw_qpt
,
106 bnad_pci_unmap_skb(struct device
*pdev
, struct bnad_skb_unmap
*array
,
107 u32 index
, u32 depth
, struct sk_buff
*skb
, u32 frag
)
110 array
[index
].skb
= NULL
;
112 dma_unmap_single(pdev
, dma_unmap_addr(&array
[index
], dma_addr
),
113 skb_headlen(skb
), DMA_TO_DEVICE
);
114 dma_unmap_addr_set(&array
[index
], dma_addr
, 0);
115 BNA_QE_INDX_ADD(index
, 1, depth
);
117 for (j
= 0; j
< frag
; j
++) {
118 dma_unmap_page(pdev
, dma_unmap_addr(&array
[index
], dma_addr
),
119 skb_shinfo(skb
)->frags
[j
].size
, DMA_TO_DEVICE
);
120 dma_unmap_addr_set(&array
[index
], dma_addr
, 0);
121 BNA_QE_INDX_ADD(index
, 1, depth
);
128 * Frees all pending Tx Bufs
129 * At this point no activity is expected on the Q,
130 * so DMA unmap & freeing is fine.
133 bnad_free_all_txbufs(struct bnad
*bnad
,
137 struct bnad_unmap_q
*unmap_q
= tcb
->unmap_q
;
138 struct bnad_skb_unmap
*unmap_array
;
139 struct sk_buff
*skb
= NULL
;
142 unmap_array
= unmap_q
->unmap_array
;
144 for (q
= 0; q
< unmap_q
->q_depth
; q
++) {
145 skb
= unmap_array
[q
].skb
;
150 unmap_cons
= bnad_pci_unmap_skb(&bnad
->pcidev
->dev
, unmap_array
,
151 unmap_cons
, unmap_q
->q_depth
, skb
,
152 skb_shinfo(skb
)->nr_frags
);
154 dev_kfree_skb_any(skb
);
158 /* Data Path Handlers */
161 * bnad_free_txbufs : Frees the Tx bufs on Tx completion
162 * Can be called in a) Interrupt context
167 bnad_free_txbufs(struct bnad
*bnad
,
170 u32 unmap_cons
, sent_packets
= 0, sent_bytes
= 0;
171 u16 wis
, updated_hw_cons
;
172 struct bnad_unmap_q
*unmap_q
= tcb
->unmap_q
;
173 struct bnad_skb_unmap
*unmap_array
;
177 * Just return if TX is stopped. This check is useful
178 * when bnad_free_txbufs() runs out of a tasklet scheduled
179 * before bnad_cb_tx_cleanup() cleared BNAD_TXQ_TX_STARTED bit
180 * but this routine runs actually after the cleanup has been
183 if (!test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
))
186 updated_hw_cons
= *(tcb
->hw_consumer_index
);
188 wis
= BNA_Q_INDEX_CHANGE(tcb
->consumer_index
,
189 updated_hw_cons
, tcb
->q_depth
);
191 BUG_ON(!(wis
<= BNA_QE_IN_USE_CNT(tcb
, tcb
->q_depth
)));
193 unmap_array
= unmap_q
->unmap_array
;
194 unmap_cons
= unmap_q
->consumer_index
;
196 prefetch(&unmap_array
[unmap_cons
+ 1]);
198 skb
= unmap_array
[unmap_cons
].skb
;
201 sent_bytes
+= skb
->len
;
202 wis
-= BNA_TXQ_WI_NEEDED(1 + skb_shinfo(skb
)->nr_frags
);
204 unmap_cons
= bnad_pci_unmap_skb(&bnad
->pcidev
->dev
, unmap_array
,
205 unmap_cons
, unmap_q
->q_depth
, skb
,
206 skb_shinfo(skb
)->nr_frags
);
208 dev_kfree_skb_any(skb
);
211 /* Update consumer pointers. */
212 tcb
->consumer_index
= updated_hw_cons
;
213 unmap_q
->consumer_index
= unmap_cons
;
215 tcb
->txq
->tx_packets
+= sent_packets
;
216 tcb
->txq
->tx_bytes
+= sent_bytes
;
221 /* Tx Free Tasklet function */
222 /* Frees for all the tcb's in all the Tx's */
224 * Scheduled from sending context, so that
225 * the fat Tx lock is not held for too long
226 * in the sending context.
229 bnad_tx_free_tasklet(unsigned long bnad_ptr
)
231 struct bnad
*bnad
= (struct bnad
*)bnad_ptr
;
236 for (i
= 0; i
< bnad
->num_tx
; i
++) {
237 for (j
= 0; j
< bnad
->num_txq_per_tx
; j
++) {
238 tcb
= bnad
->tx_info
[i
].tcb
[j
];
241 if (((u16
) (*tcb
->hw_consumer_index
) !=
242 tcb
->consumer_index
) &&
243 (!test_and_set_bit(BNAD_TXQ_FREE_SENT
,
245 acked
= bnad_free_txbufs(bnad
, tcb
);
246 if (likely(test_bit(BNAD_TXQ_TX_STARTED
,
248 bna_ib_ack(tcb
->i_dbell
, acked
);
249 smp_mb__before_clear_bit();
250 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
252 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED
,
255 if (netif_queue_stopped(bnad
->netdev
)) {
256 if (acked
&& netif_carrier_ok(bnad
->netdev
) &&
257 BNA_QE_FREE_CNT(tcb
, tcb
->q_depth
) >=
258 BNAD_NETIF_WAKE_THRESHOLD
) {
259 netif_wake_queue(bnad
->netdev
);
261 /* Counters for individual TxQs? */
262 BNAD_UPDATE_CTR(bnad
,
271 bnad_tx(struct bnad
*bnad
, struct bna_tcb
*tcb
)
273 struct net_device
*netdev
= bnad
->netdev
;
276 if (test_and_set_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
))
279 sent
= bnad_free_txbufs(bnad
, tcb
);
281 if (netif_queue_stopped(netdev
) &&
282 netif_carrier_ok(netdev
) &&
283 BNA_QE_FREE_CNT(tcb
, tcb
->q_depth
) >=
284 BNAD_NETIF_WAKE_THRESHOLD
) {
285 if (test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)) {
286 netif_wake_queue(netdev
);
287 BNAD_UPDATE_CTR(bnad
, netif_queue_wakeup
);
292 if (likely(test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)))
293 bna_ib_ack(tcb
->i_dbell
, sent
);
295 smp_mb__before_clear_bit();
296 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
301 /* MSIX Tx Completion Handler */
303 bnad_msix_tx(int irq
, void *data
)
305 struct bna_tcb
*tcb
= (struct bna_tcb
*)data
;
306 struct bnad
*bnad
= tcb
->bnad
;
314 bnad_reset_rcb(struct bnad
*bnad
, struct bna_rcb
*rcb
)
316 struct bnad_unmap_q
*unmap_q
= rcb
->unmap_q
;
318 rcb
->producer_index
= 0;
319 rcb
->consumer_index
= 0;
321 unmap_q
->producer_index
= 0;
322 unmap_q
->consumer_index
= 0;
326 bnad_free_all_rxbufs(struct bnad
*bnad
, struct bna_rcb
*rcb
)
328 struct bnad_unmap_q
*unmap_q
;
329 struct bnad_skb_unmap
*unmap_array
;
333 unmap_q
= rcb
->unmap_q
;
334 unmap_array
= unmap_q
->unmap_array
;
335 for (unmap_cons
= 0; unmap_cons
< unmap_q
->q_depth
; unmap_cons
++) {
336 skb
= unmap_array
[unmap_cons
].skb
;
339 unmap_array
[unmap_cons
].skb
= NULL
;
340 dma_unmap_single(&bnad
->pcidev
->dev
,
341 dma_unmap_addr(&unmap_array
[unmap_cons
],
343 rcb
->rxq
->buffer_size
,
347 bnad_reset_rcb(bnad
, rcb
);
351 bnad_alloc_n_post_rxbufs(struct bnad
*bnad
, struct bna_rcb
*rcb
)
353 u16 to_alloc
, alloced
, unmap_prod
, wi_range
;
354 struct bnad_unmap_q
*unmap_q
= rcb
->unmap_q
;
355 struct bnad_skb_unmap
*unmap_array
;
356 struct bna_rxq_entry
*rxent
;
362 BNA_QE_FREE_CNT(unmap_q
, unmap_q
->q_depth
);
364 unmap_array
= unmap_q
->unmap_array
;
365 unmap_prod
= unmap_q
->producer_index
;
367 BNA_RXQ_QPGE_PTR_GET(unmap_prod
, rcb
->sw_qpt
, rxent
, wi_range
);
371 BNA_RXQ_QPGE_PTR_GET(unmap_prod
, rcb
->sw_qpt
, rxent
,
373 skb
= netdev_alloc_skb_ip_align(bnad
->netdev
,
374 rcb
->rxq
->buffer_size
);
375 if (unlikely(!skb
)) {
376 BNAD_UPDATE_CTR(bnad
, rxbuf_alloc_failed
);
377 rcb
->rxq
->rxbuf_alloc_failed
++;
380 unmap_array
[unmap_prod
].skb
= skb
;
381 dma_addr
= dma_map_single(&bnad
->pcidev
->dev
, skb
->data
,
382 rcb
->rxq
->buffer_size
,
384 dma_unmap_addr_set(&unmap_array
[unmap_prod
], dma_addr
,
386 BNA_SET_DMA_ADDR(dma_addr
, &rxent
->host_addr
);
387 BNA_QE_INDX_ADD(unmap_prod
, 1, unmap_q
->q_depth
);
395 if (likely(alloced
)) {
396 unmap_q
->producer_index
= unmap_prod
;
397 rcb
->producer_index
= unmap_prod
;
399 if (likely(test_bit(BNAD_RXQ_STARTED
, &rcb
->flags
)))
400 bna_rxq_prod_indx_doorbell(rcb
);
405 bnad_refill_rxq(struct bnad
*bnad
, struct bna_rcb
*rcb
)
407 struct bnad_unmap_q
*unmap_q
= rcb
->unmap_q
;
409 if (!test_and_set_bit(BNAD_RXQ_REFILL
, &rcb
->flags
)) {
410 if (BNA_QE_FREE_CNT(unmap_q
, unmap_q
->q_depth
)
411 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT
)
412 bnad_alloc_n_post_rxbufs(bnad
, rcb
);
413 smp_mb__before_clear_bit();
414 clear_bit(BNAD_RXQ_REFILL
, &rcb
->flags
);
419 bnad_poll_cq(struct bnad
*bnad
, struct bna_ccb
*ccb
, int budget
)
421 struct bna_cq_entry
*cmpl
, *next_cmpl
;
422 struct bna_rcb
*rcb
= NULL
;
423 unsigned int wi_range
, packets
= 0, wis
= 0;
424 struct bnad_unmap_q
*unmap_q
;
425 struct bnad_skb_unmap
*unmap_array
;
427 u32 flags
, unmap_cons
;
428 struct bna_pkt_rate
*pkt_rt
= &ccb
->pkt_rate
;
429 struct bnad_rx_ctrl
*rx_ctrl
= (struct bnad_rx_ctrl
*)(ccb
->ctrl
);
431 set_bit(BNAD_FP_IN_RX_PATH
, &rx_ctrl
->flags
);
433 if (!test_bit(BNAD_RXQ_STARTED
, &ccb
->rcb
[0]->flags
)) {
434 clear_bit(BNAD_FP_IN_RX_PATH
, &rx_ctrl
->flags
);
438 prefetch(bnad
->netdev
);
439 BNA_CQ_QPGE_PTR_GET(ccb
->producer_index
, ccb
->sw_qpt
, cmpl
,
441 BUG_ON(!(wi_range
<= ccb
->q_depth
));
442 while (cmpl
->valid
&& packets
< budget
) {
444 BNA_UPDATE_PKT_CNT(pkt_rt
, ntohs(cmpl
->length
));
446 if (bna_is_small_rxq(cmpl
->rxq_id
))
451 unmap_q
= rcb
->unmap_q
;
452 unmap_array
= unmap_q
->unmap_array
;
453 unmap_cons
= unmap_q
->consumer_index
;
455 skb
= unmap_array
[unmap_cons
].skb
;
457 unmap_array
[unmap_cons
].skb
= NULL
;
458 dma_unmap_single(&bnad
->pcidev
->dev
,
459 dma_unmap_addr(&unmap_array
[unmap_cons
],
461 rcb
->rxq
->buffer_size
,
463 BNA_QE_INDX_ADD(unmap_q
->consumer_index
, 1, unmap_q
->q_depth
);
465 /* Should be more efficient ? Performance ? */
466 BNA_QE_INDX_ADD(rcb
->consumer_index
, 1, rcb
->q_depth
);
469 if (likely(--wi_range
))
470 next_cmpl
= cmpl
+ 1;
472 BNA_QE_INDX_ADD(ccb
->producer_index
, wis
, ccb
->q_depth
);
474 BNA_CQ_QPGE_PTR_GET(ccb
->producer_index
, ccb
->sw_qpt
,
475 next_cmpl
, wi_range
);
476 BUG_ON(!(wi_range
<= ccb
->q_depth
));
480 flags
= ntohl(cmpl
->flags
);
483 (BNA_CQ_EF_MAC_ERROR
| BNA_CQ_EF_FCS_ERROR
|
484 BNA_CQ_EF_TOO_LONG
))) {
485 dev_kfree_skb_any(skb
);
486 rcb
->rxq
->rx_packets_with_error
++;
490 skb_put(skb
, ntohs(cmpl
->length
));
492 ((bnad
->netdev
->features
& NETIF_F_RXCSUM
) &&
493 (((flags
& BNA_CQ_EF_IPV4
) &&
494 (flags
& BNA_CQ_EF_L3_CKSUM_OK
)) ||
495 (flags
& BNA_CQ_EF_IPV6
)) &&
496 (flags
& (BNA_CQ_EF_TCP
| BNA_CQ_EF_UDP
)) &&
497 (flags
& BNA_CQ_EF_L4_CKSUM_OK
)))
498 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
500 skb_checksum_none_assert(skb
);
502 rcb
->rxq
->rx_packets
++;
503 rcb
->rxq
->rx_bytes
+= skb
->len
;
504 skb
->protocol
= eth_type_trans(skb
, bnad
->netdev
);
506 if (flags
& BNA_CQ_EF_VLAN
)
507 __vlan_hwaccel_put_tag(skb
, ntohs(cmpl
->vlan_tag
));
509 if (skb
->ip_summed
== CHECKSUM_UNNECESSARY
)
510 napi_gro_receive(&rx_ctrl
->napi
, skb
);
512 netif_receive_skb(skb
);
520 BNA_QE_INDX_ADD(ccb
->producer_index
, wis
, ccb
->q_depth
);
522 if (likely(test_bit(BNAD_RXQ_STARTED
, &ccb
->rcb
[0]->flags
)))
523 bna_ib_ack_disable_irq(ccb
->i_dbell
, packets
);
525 bnad_refill_rxq(bnad
, ccb
->rcb
[0]);
527 bnad_refill_rxq(bnad
, ccb
->rcb
[1]);
529 clear_bit(BNAD_FP_IN_RX_PATH
, &rx_ctrl
->flags
);
535 bnad_netif_rx_schedule_poll(struct bnad
*bnad
, struct bna_ccb
*ccb
)
537 struct bnad_rx_ctrl
*rx_ctrl
= (struct bnad_rx_ctrl
*)(ccb
->ctrl
);
538 struct napi_struct
*napi
= &rx_ctrl
->napi
;
540 if (likely(napi_schedule_prep(napi
))) {
541 __napi_schedule(napi
);
542 rx_ctrl
->rx_schedule
++;
546 /* MSIX Rx Path Handler */
548 bnad_msix_rx(int irq
, void *data
)
550 struct bna_ccb
*ccb
= (struct bna_ccb
*)data
;
553 ((struct bnad_rx_ctrl
*)(ccb
->ctrl
))->rx_intr_ctr
++;
554 bnad_netif_rx_schedule_poll(ccb
->bnad
, ccb
);
560 /* Interrupt handlers */
562 /* Mbox Interrupt Handlers */
564 bnad_msix_mbox_handler(int irq
, void *data
)
568 struct bnad
*bnad
= (struct bnad
*)data
;
570 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
571 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
))) {
572 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
576 bna_intr_status_get(&bnad
->bna
, intr_status
);
578 if (BNA_IS_MBOX_ERR_INTR(&bnad
->bna
, intr_status
))
579 bna_mbox_handler(&bnad
->bna
, intr_status
);
581 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
587 bnad_isr(int irq
, void *data
)
592 struct bnad
*bnad
= (struct bnad
*)data
;
593 struct bnad_rx_info
*rx_info
;
594 struct bnad_rx_ctrl
*rx_ctrl
;
595 struct bna_tcb
*tcb
= NULL
;
597 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
598 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
))) {
599 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
603 bna_intr_status_get(&bnad
->bna
, intr_status
);
605 if (unlikely(!intr_status
)) {
606 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
610 if (BNA_IS_MBOX_ERR_INTR(&bnad
->bna
, intr_status
))
611 bna_mbox_handler(&bnad
->bna
, intr_status
);
613 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
615 if (!BNA_IS_INTX_DATA_INTR(intr_status
))
618 /* Process data interrupts */
620 for (i
= 0; i
< bnad
->num_tx
; i
++) {
621 for (j
= 0; j
< bnad
->num_txq_per_tx
; j
++) {
622 tcb
= bnad
->tx_info
[i
].tcb
[j
];
623 if (tcb
&& test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
))
624 bnad_tx(bnad
, bnad
->tx_info
[i
].tcb
[j
]);
628 for (i
= 0; i
< bnad
->num_rx
; i
++) {
629 rx_info
= &bnad
->rx_info
[i
];
632 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
633 rx_ctrl
= &rx_info
->rx_ctrl
[j
];
635 bnad_netif_rx_schedule_poll(bnad
,
643 * Called in interrupt / callback context
644 * with bna_lock held, so cfg_flags access is OK
647 bnad_enable_mbox_irq(struct bnad
*bnad
)
649 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
);
651 BNAD_UPDATE_CTR(bnad
, mbox_intr_enabled
);
655 * Called with bnad->bna_lock held b'cos of
656 * bnad->cfg_flags access.
659 bnad_disable_mbox_irq(struct bnad
*bnad
)
661 set_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
);
663 BNAD_UPDATE_CTR(bnad
, mbox_intr_disabled
);
667 bnad_set_netdev_perm_addr(struct bnad
*bnad
)
669 struct net_device
*netdev
= bnad
->netdev
;
671 memcpy(netdev
->perm_addr
, &bnad
->perm_addr
, netdev
->addr_len
);
672 if (is_zero_ether_addr(netdev
->dev_addr
))
673 memcpy(netdev
->dev_addr
, &bnad
->perm_addr
, netdev
->addr_len
);
676 /* Control Path Handlers */
680 bnad_cb_mbox_intr_enable(struct bnad
*bnad
)
682 bnad_enable_mbox_irq(bnad
);
686 bnad_cb_mbox_intr_disable(struct bnad
*bnad
)
688 bnad_disable_mbox_irq(bnad
);
692 bnad_cb_ioceth_ready(struct bnad
*bnad
)
694 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_SUCCESS
;
695 complete(&bnad
->bnad_completions
.ioc_comp
);
699 bnad_cb_ioceth_failed(struct bnad
*bnad
)
701 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_FAIL
;
702 complete(&bnad
->bnad_completions
.ioc_comp
);
706 bnad_cb_ioceth_disabled(struct bnad
*bnad
)
708 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_SUCCESS
;
709 complete(&bnad
->bnad_completions
.ioc_comp
);
713 bnad_cb_enet_disabled(void *arg
)
715 struct bnad
*bnad
= (struct bnad
*)arg
;
717 netif_carrier_off(bnad
->netdev
);
718 complete(&bnad
->bnad_completions
.enet_comp
);
722 bnad_cb_ethport_link_status(struct bnad
*bnad
,
723 enum bna_link_status link_status
)
727 link_up
= (link_status
== BNA_LINK_UP
) || (link_status
== BNA_CEE_UP
);
729 if (link_status
== BNA_CEE_UP
) {
730 if (!test_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
))
731 BNAD_UPDATE_CTR(bnad
, cee_toggle
);
732 set_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
);
734 if (test_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
))
735 BNAD_UPDATE_CTR(bnad
, cee_toggle
);
736 clear_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
);
740 if (!netif_carrier_ok(bnad
->netdev
)) {
742 printk(KERN_WARNING
"bna: %s link up\n",
744 netif_carrier_on(bnad
->netdev
);
745 BNAD_UPDATE_CTR(bnad
, link_toggle
);
746 for (tx_id
= 0; tx_id
< bnad
->num_tx
; tx_id
++) {
747 for (tcb_id
= 0; tcb_id
< bnad
->num_txq_per_tx
;
749 struct bna_tcb
*tcb
=
750 bnad
->tx_info
[tx_id
].tcb
[tcb_id
];
757 if (test_bit(BNAD_TXQ_TX_STARTED
,
761 * Transmit Schedule */
762 printk(KERN_INFO
"bna: %s %d "
769 BNAD_UPDATE_CTR(bnad
,
775 BNAD_UPDATE_CTR(bnad
,
782 if (netif_carrier_ok(bnad
->netdev
)) {
783 printk(KERN_WARNING
"bna: %s link down\n",
785 netif_carrier_off(bnad
->netdev
);
786 BNAD_UPDATE_CTR(bnad
, link_toggle
);
792 bnad_cb_tx_disabled(void *arg
, struct bna_tx
*tx
)
794 struct bnad
*bnad
= (struct bnad
*)arg
;
796 complete(&bnad
->bnad_completions
.tx_comp
);
800 bnad_cb_tcb_setup(struct bnad
*bnad
, struct bna_tcb
*tcb
)
802 struct bnad_tx_info
*tx_info
=
803 (struct bnad_tx_info
*)tcb
->txq
->tx
->priv
;
804 struct bnad_unmap_q
*unmap_q
= tcb
->unmap_q
;
806 tx_info
->tcb
[tcb
->id
] = tcb
;
807 unmap_q
->producer_index
= 0;
808 unmap_q
->consumer_index
= 0;
809 unmap_q
->q_depth
= BNAD_TX_UNMAPQ_DEPTH
;
813 bnad_cb_tcb_destroy(struct bnad
*bnad
, struct bna_tcb
*tcb
)
815 struct bnad_tx_info
*tx_info
=
816 (struct bnad_tx_info
*)tcb
->txq
->tx
->priv
;
817 struct bnad_unmap_q
*unmap_q
= tcb
->unmap_q
;
819 while (test_and_set_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
))
822 bnad_free_all_txbufs(bnad
, tcb
);
824 unmap_q
->producer_index
= 0;
825 unmap_q
->consumer_index
= 0;
827 smp_mb__before_clear_bit();
828 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
830 tx_info
->tcb
[tcb
->id
] = NULL
;
834 bnad_cb_rcb_setup(struct bnad
*bnad
, struct bna_rcb
*rcb
)
836 struct bnad_unmap_q
*unmap_q
= rcb
->unmap_q
;
838 unmap_q
->producer_index
= 0;
839 unmap_q
->consumer_index
= 0;
840 unmap_q
->q_depth
= BNAD_RX_UNMAPQ_DEPTH
;
844 bnad_cb_rcb_destroy(struct bnad
*bnad
, struct bna_rcb
*rcb
)
846 bnad_free_all_rxbufs(bnad
, rcb
);
850 bnad_cb_ccb_setup(struct bnad
*bnad
, struct bna_ccb
*ccb
)
852 struct bnad_rx_info
*rx_info
=
853 (struct bnad_rx_info
*)ccb
->cq
->rx
->priv
;
855 rx_info
->rx_ctrl
[ccb
->id
].ccb
= ccb
;
856 ccb
->ctrl
= &rx_info
->rx_ctrl
[ccb
->id
];
860 bnad_cb_ccb_destroy(struct bnad
*bnad
, struct bna_ccb
*ccb
)
862 struct bnad_rx_info
*rx_info
=
863 (struct bnad_rx_info
*)ccb
->cq
->rx
->priv
;
865 rx_info
->rx_ctrl
[ccb
->id
].ccb
= NULL
;
869 bnad_cb_tx_stall(struct bnad
*bnad
, struct bna_tx
*tx
)
871 struct bnad_tx_info
*tx_info
=
872 (struct bnad_tx_info
*)tx
->priv
;
877 for (i
= 0; i
< BNAD_MAX_TXQ_PER_TX
; i
++) {
878 tcb
= tx_info
->tcb
[i
];
882 clear_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
);
883 netif_stop_subqueue(bnad
->netdev
, txq_id
);
884 printk(KERN_INFO
"bna: %s %d TXQ_STOPPED\n",
885 bnad
->netdev
->name
, txq_id
);
890 bnad_cb_tx_resume(struct bnad
*bnad
, struct bna_tx
*tx
)
892 struct bnad_tx_info
*tx_info
= (struct bnad_tx_info
*)tx
->priv
;
894 struct bnad_unmap_q
*unmap_q
;
898 for (i
= 0; i
< BNAD_MAX_TXQ_PER_TX
; i
++) {
899 tcb
= tx_info
->tcb
[i
];
904 unmap_q
= tcb
->unmap_q
;
906 if (test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
))
909 while (test_and_set_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
))
912 bnad_free_all_txbufs(bnad
, tcb
);
914 unmap_q
->producer_index
= 0;
915 unmap_q
->consumer_index
= 0;
917 smp_mb__before_clear_bit();
918 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
920 set_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
);
922 if (netif_carrier_ok(bnad
->netdev
)) {
923 printk(KERN_INFO
"bna: %s %d TXQ_STARTED\n",
924 bnad
->netdev
->name
, txq_id
);
925 netif_wake_subqueue(bnad
->netdev
, txq_id
);
926 BNAD_UPDATE_CTR(bnad
, netif_queue_wakeup
);
931 * Workaround for first ioceth enable failure & we
932 * get a 0 MAC address. We try to get the MAC address
935 if (is_zero_ether_addr(&bnad
->perm_addr
.mac
[0])) {
936 bna_enet_perm_mac_get(&bnad
->bna
.enet
, &bnad
->perm_addr
);
937 bnad_set_netdev_perm_addr(bnad
);
942 bnad_cb_tx_cleanup(struct bnad
*bnad
, struct bna_tx
*tx
)
944 struct bnad_tx_info
*tx_info
= (struct bnad_tx_info
*)tx
->priv
;
948 for (i
= 0; i
< BNAD_MAX_TXQ_PER_TX
; i
++) {
949 tcb
= tx_info
->tcb
[i
];
954 mdelay(BNAD_TXRX_SYNC_MDELAY
);
955 bna_tx_cleanup_complete(tx
);
959 bnad_cb_rx_cleanup(struct bnad
*bnad
, struct bna_rx
*rx
)
961 struct bnad_rx_info
*rx_info
= (struct bnad_rx_info
*)rx
->priv
;
963 struct bnad_rx_ctrl
*rx_ctrl
;
966 mdelay(BNAD_TXRX_SYNC_MDELAY
);
968 for (i
= 0; i
< BNAD_MAX_RXP_PER_RX
; i
++) {
969 rx_ctrl
= &rx_info
->rx_ctrl
[i
];
974 clear_bit(BNAD_RXQ_STARTED
, &ccb
->rcb
[0]->flags
);
977 clear_bit(BNAD_RXQ_STARTED
, &ccb
->rcb
[1]->flags
);
979 while (test_bit(BNAD_FP_IN_RX_PATH
, &rx_ctrl
->flags
))
983 bna_rx_cleanup_complete(rx
);
987 bnad_cb_rx_post(struct bnad
*bnad
, struct bna_rx
*rx
)
989 struct bnad_rx_info
*rx_info
= (struct bnad_rx_info
*)rx
->priv
;
992 struct bnad_rx_ctrl
*rx_ctrl
;
993 struct bnad_unmap_q
*unmap_q
;
997 for (i
= 0; i
< BNAD_MAX_RXP_PER_RX
; i
++) {
998 rx_ctrl
= &rx_info
->rx_ctrl
[i
];
1003 bnad_cq_cmpl_init(bnad
, ccb
);
1005 for (j
= 0; j
< BNAD_MAX_RXQ_PER_RXP
; j
++) {
1009 bnad_free_all_rxbufs(bnad
, rcb
);
1011 set_bit(BNAD_RXQ_STARTED
, &rcb
->flags
);
1012 unmap_q
= rcb
->unmap_q
;
1014 /* Now allocate & post buffers for this RCB */
1015 /* !!Allocation in callback context */
1016 if (!test_and_set_bit(BNAD_RXQ_REFILL
, &rcb
->flags
)) {
1017 if (BNA_QE_FREE_CNT(unmap_q
, unmap_q
->q_depth
)
1018 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT
)
1019 bnad_alloc_n_post_rxbufs(bnad
, rcb
);
1020 smp_mb__before_clear_bit();
1021 clear_bit(BNAD_RXQ_REFILL
, &rcb
->flags
);
1028 bnad_cb_rx_disabled(void *arg
, struct bna_rx
*rx
)
1030 struct bnad
*bnad
= (struct bnad
*)arg
;
1032 complete(&bnad
->bnad_completions
.rx_comp
);
1036 bnad_cb_rx_mcast_add(struct bnad
*bnad
, struct bna_rx
*rx
)
1038 bnad
->bnad_completions
.mcast_comp_status
= BNA_CB_SUCCESS
;
1039 complete(&bnad
->bnad_completions
.mcast_comp
);
1043 bnad_cb_stats_get(struct bnad
*bnad
, enum bna_cb_status status
,
1044 struct bna_stats
*stats
)
1046 if (status
== BNA_CB_SUCCESS
)
1047 BNAD_UPDATE_CTR(bnad
, hw_stats_updates
);
1049 if (!netif_running(bnad
->netdev
) ||
1050 !test_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
))
1053 mod_timer(&bnad
->stats_timer
,
1054 jiffies
+ msecs_to_jiffies(BNAD_STATS_TIMER_FREQ
));
1058 bnad_cb_enet_mtu_set(struct bnad
*bnad
)
1060 bnad
->bnad_completions
.mtu_comp_status
= BNA_CB_SUCCESS
;
1061 complete(&bnad
->bnad_completions
.mtu_comp
);
1064 /* Resource allocation, free functions */
1067 bnad_mem_free(struct bnad
*bnad
,
1068 struct bna_mem_info
*mem_info
)
1073 if (mem_info
->mdl
== NULL
)
1076 for (i
= 0; i
< mem_info
->num
; i
++) {
1077 if (mem_info
->mdl
[i
].kva
!= NULL
) {
1078 if (mem_info
->mem_type
== BNA_MEM_T_DMA
) {
1079 BNA_GET_DMA_ADDR(&(mem_info
->mdl
[i
].dma
),
1081 dma_free_coherent(&bnad
->pcidev
->dev
,
1082 mem_info
->mdl
[i
].len
,
1083 mem_info
->mdl
[i
].kva
, dma_pa
);
1085 kfree(mem_info
->mdl
[i
].kva
);
1088 kfree(mem_info
->mdl
);
1089 mem_info
->mdl
= NULL
;
1093 bnad_mem_alloc(struct bnad
*bnad
,
1094 struct bna_mem_info
*mem_info
)
1099 if ((mem_info
->num
== 0) || (mem_info
->len
== 0)) {
1100 mem_info
->mdl
= NULL
;
1104 mem_info
->mdl
= kcalloc(mem_info
->num
, sizeof(struct bna_mem_descr
),
1106 if (mem_info
->mdl
== NULL
)
1109 if (mem_info
->mem_type
== BNA_MEM_T_DMA
) {
1110 for (i
= 0; i
< mem_info
->num
; i
++) {
1111 mem_info
->mdl
[i
].len
= mem_info
->len
;
1112 mem_info
->mdl
[i
].kva
=
1113 dma_alloc_coherent(&bnad
->pcidev
->dev
,
1114 mem_info
->len
, &dma_pa
,
1117 if (mem_info
->mdl
[i
].kva
== NULL
)
1120 BNA_SET_DMA_ADDR(dma_pa
,
1121 &(mem_info
->mdl
[i
].dma
));
1124 for (i
= 0; i
< mem_info
->num
; i
++) {
1125 mem_info
->mdl
[i
].len
= mem_info
->len
;
1126 mem_info
->mdl
[i
].kva
= kzalloc(mem_info
->len
,
1128 if (mem_info
->mdl
[i
].kva
== NULL
)
1136 bnad_mem_free(bnad
, mem_info
);
1140 /* Free IRQ for Mailbox */
1142 bnad_mbox_irq_free(struct bnad
*bnad
)
1145 unsigned long flags
;
1147 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1148 bnad_disable_mbox_irq(bnad
);
1149 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1151 irq
= BNAD_GET_MBOX_IRQ(bnad
);
1152 free_irq(irq
, bnad
);
1156 * Allocates IRQ for Mailbox, but keep it disabled
1157 * This will be enabled once we get the mbox enable callback
1161 bnad_mbox_irq_alloc(struct bnad
*bnad
)
1164 unsigned long irq_flags
, flags
;
1166 irq_handler_t irq_handler
;
1168 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1169 if (bnad
->cfg_flags
& BNAD_CF_MSIX
) {
1170 irq_handler
= (irq_handler_t
)bnad_msix_mbox_handler
;
1171 irq
= bnad
->msix_table
[BNAD_MAILBOX_MSIX_INDEX
].vector
;
1174 irq_handler
= (irq_handler_t
)bnad_isr
;
1175 irq
= bnad
->pcidev
->irq
;
1176 irq_flags
= IRQF_SHARED
;
1179 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1180 sprintf(bnad
->mbox_irq_name
, "%s", BNAD_NAME
);
1183 * Set the Mbox IRQ disable flag, so that the IRQ handler
1184 * called from request_irq() for SHARED IRQs do not execute
1186 set_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
);
1188 BNAD_UPDATE_CTR(bnad
, mbox_intr_disabled
);
1190 err
= request_irq(irq
, irq_handler
, irq_flags
,
1191 bnad
->mbox_irq_name
, bnad
);
1197 bnad_txrx_irq_free(struct bnad
*bnad
, struct bna_intr_info
*intr_info
)
1199 kfree(intr_info
->idl
);
1200 intr_info
->idl
= NULL
;
1203 /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1205 bnad_txrx_irq_alloc(struct bnad
*bnad
, enum bnad_intr_source src
,
1206 u32 txrx_id
, struct bna_intr_info
*intr_info
)
1208 int i
, vector_start
= 0;
1210 unsigned long flags
;
1212 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1213 cfg_flags
= bnad
->cfg_flags
;
1214 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1216 if (cfg_flags
& BNAD_CF_MSIX
) {
1217 intr_info
->intr_type
= BNA_INTR_T_MSIX
;
1218 intr_info
->idl
= kcalloc(intr_info
->num
,
1219 sizeof(struct bna_intr_descr
),
1221 if (!intr_info
->idl
)
1226 vector_start
= BNAD_MAILBOX_MSIX_VECTORS
+ txrx_id
;
1230 vector_start
= BNAD_MAILBOX_MSIX_VECTORS
+
1231 (bnad
->num_tx
* bnad
->num_txq_per_tx
) +
1239 for (i
= 0; i
< intr_info
->num
; i
++)
1240 intr_info
->idl
[i
].vector
= vector_start
+ i
;
1242 intr_info
->intr_type
= BNA_INTR_T_INTX
;
1244 intr_info
->idl
= kcalloc(intr_info
->num
,
1245 sizeof(struct bna_intr_descr
),
1247 if (!intr_info
->idl
)
1252 intr_info
->idl
[0].vector
= BNAD_INTX_TX_IB_BITMASK
;
1256 intr_info
->idl
[0].vector
= BNAD_INTX_RX_IB_BITMASK
;
1264 * NOTE: Should be called for MSIX only
1265 * Unregisters Tx MSIX vector(s) from the kernel
1268 bnad_tx_msix_unregister(struct bnad
*bnad
, struct bnad_tx_info
*tx_info
,
1274 for (i
= 0; i
< num_txqs
; i
++) {
1275 if (tx_info
->tcb
[i
] == NULL
)
1278 vector_num
= tx_info
->tcb
[i
]->intr_vector
;
1279 free_irq(bnad
->msix_table
[vector_num
].vector
, tx_info
->tcb
[i
]);
1284 * NOTE: Should be called for MSIX only
1285 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1288 bnad_tx_msix_register(struct bnad
*bnad
, struct bnad_tx_info
*tx_info
,
1289 u32 tx_id
, int num_txqs
)
1295 for (i
= 0; i
< num_txqs
; i
++) {
1296 vector_num
= tx_info
->tcb
[i
]->intr_vector
;
1297 sprintf(tx_info
->tcb
[i
]->name
, "%s TXQ %d", bnad
->netdev
->name
,
1298 tx_id
+ tx_info
->tcb
[i
]->id
);
1299 err
= request_irq(bnad
->msix_table
[vector_num
].vector
,
1300 (irq_handler_t
)bnad_msix_tx
, 0,
1301 tx_info
->tcb
[i
]->name
,
1311 bnad_tx_msix_unregister(bnad
, tx_info
, (i
- 1));
1316 * NOTE: Should be called for MSIX only
1317 * Unregisters Rx MSIX vector(s) from the kernel
1320 bnad_rx_msix_unregister(struct bnad
*bnad
, struct bnad_rx_info
*rx_info
,
1326 for (i
= 0; i
< num_rxps
; i
++) {
1327 if (rx_info
->rx_ctrl
[i
].ccb
== NULL
)
1330 vector_num
= rx_info
->rx_ctrl
[i
].ccb
->intr_vector
;
1331 free_irq(bnad
->msix_table
[vector_num
].vector
,
1332 rx_info
->rx_ctrl
[i
].ccb
);
1337 * NOTE: Should be called for MSIX only
1338 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1341 bnad_rx_msix_register(struct bnad
*bnad
, struct bnad_rx_info
*rx_info
,
1342 u32 rx_id
, int num_rxps
)
1348 for (i
= 0; i
< num_rxps
; i
++) {
1349 vector_num
= rx_info
->rx_ctrl
[i
].ccb
->intr_vector
;
1350 sprintf(rx_info
->rx_ctrl
[i
].ccb
->name
, "%s CQ %d",
1352 rx_id
+ rx_info
->rx_ctrl
[i
].ccb
->id
);
1353 err
= request_irq(bnad
->msix_table
[vector_num
].vector
,
1354 (irq_handler_t
)bnad_msix_rx
, 0,
1355 rx_info
->rx_ctrl
[i
].ccb
->name
,
1356 rx_info
->rx_ctrl
[i
].ccb
);
1365 bnad_rx_msix_unregister(bnad
, rx_info
, (i
- 1));
1369 /* Free Tx object Resources */
1371 bnad_tx_res_free(struct bnad
*bnad
, struct bna_res_info
*res_info
)
1375 for (i
= 0; i
< BNA_TX_RES_T_MAX
; i
++) {
1376 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1377 bnad_mem_free(bnad
, &res_info
[i
].res_u
.mem_info
);
1378 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1379 bnad_txrx_irq_free(bnad
, &res_info
[i
].res_u
.intr_info
);
1383 /* Allocates memory and interrupt resources for Tx object */
1385 bnad_tx_res_alloc(struct bnad
*bnad
, struct bna_res_info
*res_info
,
1390 for (i
= 0; i
< BNA_TX_RES_T_MAX
; i
++) {
1391 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1392 err
= bnad_mem_alloc(bnad
,
1393 &res_info
[i
].res_u
.mem_info
);
1394 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1395 err
= bnad_txrx_irq_alloc(bnad
, BNAD_INTR_TX
, tx_id
,
1396 &res_info
[i
].res_u
.intr_info
);
1403 bnad_tx_res_free(bnad
, res_info
);
1407 /* Free Rx object Resources */
1409 bnad_rx_res_free(struct bnad
*bnad
, struct bna_res_info
*res_info
)
1413 for (i
= 0; i
< BNA_RX_RES_T_MAX
; i
++) {
1414 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1415 bnad_mem_free(bnad
, &res_info
[i
].res_u
.mem_info
);
1416 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1417 bnad_txrx_irq_free(bnad
, &res_info
[i
].res_u
.intr_info
);
1421 /* Allocates memory and interrupt resources for Rx object */
1423 bnad_rx_res_alloc(struct bnad
*bnad
, struct bna_res_info
*res_info
,
1428 /* All memory needs to be allocated before setup_ccbs */
1429 for (i
= 0; i
< BNA_RX_RES_T_MAX
; i
++) {
1430 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1431 err
= bnad_mem_alloc(bnad
,
1432 &res_info
[i
].res_u
.mem_info
);
1433 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1434 err
= bnad_txrx_irq_alloc(bnad
, BNAD_INTR_RX
, rx_id
,
1435 &res_info
[i
].res_u
.intr_info
);
1442 bnad_rx_res_free(bnad
, res_info
);
1446 /* Timer callbacks */
1449 bnad_ioc_timeout(unsigned long data
)
1451 struct bnad
*bnad
= (struct bnad
*)data
;
1452 unsigned long flags
;
1454 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1455 bfa_nw_ioc_timeout((void *) &bnad
->bna
.ioceth
.ioc
);
1456 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1460 bnad_ioc_hb_check(unsigned long data
)
1462 struct bnad
*bnad
= (struct bnad
*)data
;
1463 unsigned long flags
;
1465 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1466 bfa_nw_ioc_hb_check((void *) &bnad
->bna
.ioceth
.ioc
);
1467 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1471 bnad_iocpf_timeout(unsigned long data
)
1473 struct bnad
*bnad
= (struct bnad
*)data
;
1474 unsigned long flags
;
1476 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1477 bfa_nw_iocpf_timeout((void *) &bnad
->bna
.ioceth
.ioc
);
1478 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1482 bnad_iocpf_sem_timeout(unsigned long data
)
1484 struct bnad
*bnad
= (struct bnad
*)data
;
1485 unsigned long flags
;
1487 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1488 bfa_nw_iocpf_sem_timeout((void *) &bnad
->bna
.ioceth
.ioc
);
1489 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1493 * All timer routines use bnad->bna_lock to protect against
1494 * the following race, which may occur in case of no locking:
1502 /* b) Dynamic Interrupt Moderation Timer */
1504 bnad_dim_timeout(unsigned long data
)
1506 struct bnad
*bnad
= (struct bnad
*)data
;
1507 struct bnad_rx_info
*rx_info
;
1508 struct bnad_rx_ctrl
*rx_ctrl
;
1510 unsigned long flags
;
1512 if (!netif_carrier_ok(bnad
->netdev
))
1515 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1516 for (i
= 0; i
< bnad
->num_rx
; i
++) {
1517 rx_info
= &bnad
->rx_info
[i
];
1520 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
1521 rx_ctrl
= &rx_info
->rx_ctrl
[j
];
1524 bna_rx_dim_update(rx_ctrl
->ccb
);
1528 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1529 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
))
1530 mod_timer(&bnad
->dim_timer
,
1531 jiffies
+ msecs_to_jiffies(BNAD_DIM_TIMER_FREQ
));
1532 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1535 /* c) Statistics Timer */
1537 bnad_stats_timeout(unsigned long data
)
1539 struct bnad
*bnad
= (struct bnad
*)data
;
1540 unsigned long flags
;
1542 if (!netif_running(bnad
->netdev
) ||
1543 !test_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
))
1546 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1547 bna_hw_stats_get(&bnad
->bna
);
1548 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1552 * Set up timer for DIM
1553 * Called with bnad->bna_lock held
1556 bnad_dim_timer_start(struct bnad
*bnad
)
1558 if (bnad
->cfg_flags
& BNAD_CF_DIM_ENABLED
&&
1559 !test_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
)) {
1560 setup_timer(&bnad
->dim_timer
, bnad_dim_timeout
,
1561 (unsigned long)bnad
);
1562 set_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
);
1563 mod_timer(&bnad
->dim_timer
,
1564 jiffies
+ msecs_to_jiffies(BNAD_DIM_TIMER_FREQ
));
1569 * Set up timer for statistics
1570 * Called with mutex_lock(&bnad->conf_mutex) held
1573 bnad_stats_timer_start(struct bnad
*bnad
)
1575 unsigned long flags
;
1577 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1578 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
)) {
1579 setup_timer(&bnad
->stats_timer
, bnad_stats_timeout
,
1580 (unsigned long)bnad
);
1581 mod_timer(&bnad
->stats_timer
,
1582 jiffies
+ msecs_to_jiffies(BNAD_STATS_TIMER_FREQ
));
1584 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1588 * Stops the stats timer
1589 * Called with mutex_lock(&bnad->conf_mutex) held
1592 bnad_stats_timer_stop(struct bnad
*bnad
)
1595 unsigned long flags
;
1597 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1598 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
))
1600 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1602 del_timer_sync(&bnad
->stats_timer
);
1608 bnad_netdev_mc_list_get(struct net_device
*netdev
, u8
*mc_list
)
1610 int i
= 1; /* Index 0 has broadcast address */
1611 struct netdev_hw_addr
*mc_addr
;
1613 netdev_for_each_mc_addr(mc_addr
, netdev
) {
1614 memcpy(&mc_list
[i
* ETH_ALEN
], &mc_addr
->addr
[0],
1621 bnad_napi_poll_rx(struct napi_struct
*napi
, int budget
)
1623 struct bnad_rx_ctrl
*rx_ctrl
=
1624 container_of(napi
, struct bnad_rx_ctrl
, napi
);
1625 struct bnad
*bnad
= rx_ctrl
->bnad
;
1628 rx_ctrl
->rx_poll_ctr
++;
1630 if (!netif_carrier_ok(bnad
->netdev
))
1633 rcvd
= bnad_poll_cq(bnad
, rx_ctrl
->ccb
, budget
);
1638 napi_complete(napi
);
1640 rx_ctrl
->rx_complete
++;
1643 bnad_enable_rx_irq_unsafe(rx_ctrl
->ccb
);
1648 #define BNAD_NAPI_POLL_QUOTA 64
1650 bnad_napi_init(struct bnad
*bnad
, u32 rx_id
)
1652 struct bnad_rx_ctrl
*rx_ctrl
;
1655 /* Initialize & enable NAPI */
1656 for (i
= 0; i
< bnad
->num_rxp_per_rx
; i
++) {
1657 rx_ctrl
= &bnad
->rx_info
[rx_id
].rx_ctrl
[i
];
1658 netif_napi_add(bnad
->netdev
, &rx_ctrl
->napi
,
1659 bnad_napi_poll_rx
, BNAD_NAPI_POLL_QUOTA
);
1664 bnad_napi_enable(struct bnad
*bnad
, u32 rx_id
)
1666 struct bnad_rx_ctrl
*rx_ctrl
;
1669 /* Initialize & enable NAPI */
1670 for (i
= 0; i
< bnad
->num_rxp_per_rx
; i
++) {
1671 rx_ctrl
= &bnad
->rx_info
[rx_id
].rx_ctrl
[i
];
1673 napi_enable(&rx_ctrl
->napi
);
1678 bnad_napi_disable(struct bnad
*bnad
, u32 rx_id
)
1682 /* First disable and then clean up */
1683 for (i
= 0; i
< bnad
->num_rxp_per_rx
; i
++) {
1684 napi_disable(&bnad
->rx_info
[rx_id
].rx_ctrl
[i
].napi
);
1685 netif_napi_del(&bnad
->rx_info
[rx_id
].rx_ctrl
[i
].napi
);
1689 /* Should be held with conf_lock held */
1691 bnad_cleanup_tx(struct bnad
*bnad
, u32 tx_id
)
1693 struct bnad_tx_info
*tx_info
= &bnad
->tx_info
[tx_id
];
1694 struct bna_res_info
*res_info
= &bnad
->tx_res_info
[tx_id
].res_info
[0];
1695 unsigned long flags
;
1700 init_completion(&bnad
->bnad_completions
.tx_comp
);
1701 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1702 bna_tx_disable(tx_info
->tx
, BNA_HARD_CLEANUP
, bnad_cb_tx_disabled
);
1703 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1704 wait_for_completion(&bnad
->bnad_completions
.tx_comp
);
1706 if (tx_info
->tcb
[0]->intr_type
== BNA_INTR_T_MSIX
)
1707 bnad_tx_msix_unregister(bnad
, tx_info
,
1708 bnad
->num_txq_per_tx
);
1711 tasklet_kill(&bnad
->tx_free_tasklet
);
1713 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1714 bna_tx_destroy(tx_info
->tx
);
1715 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1720 bnad_tx_res_free(bnad
, res_info
);
1723 /* Should be held with conf_lock held */
1725 bnad_setup_tx(struct bnad
*bnad
, u32 tx_id
)
1728 struct bnad_tx_info
*tx_info
= &bnad
->tx_info
[tx_id
];
1729 struct bna_res_info
*res_info
= &bnad
->tx_res_info
[tx_id
].res_info
[0];
1730 struct bna_intr_info
*intr_info
=
1731 &res_info
[BNA_TX_RES_INTR_T_TXCMPL
].res_u
.intr_info
;
1732 struct bna_tx_config
*tx_config
= &bnad
->tx_config
[tx_id
];
1733 static const struct bna_tx_event_cbfn tx_cbfn
= {
1734 .tcb_setup_cbfn
= bnad_cb_tcb_setup
,
1735 .tcb_destroy_cbfn
= bnad_cb_tcb_destroy
,
1736 .tx_stall_cbfn
= bnad_cb_tx_stall
,
1737 .tx_resume_cbfn
= bnad_cb_tx_resume
,
1738 .tx_cleanup_cbfn
= bnad_cb_tx_cleanup
,
1742 unsigned long flags
;
1744 tx_info
->tx_id
= tx_id
;
1746 /* Initialize the Tx object configuration */
1747 tx_config
->num_txq
= bnad
->num_txq_per_tx
;
1748 tx_config
->txq_depth
= bnad
->txq_depth
;
1749 tx_config
->tx_type
= BNA_TX_T_REGULAR
;
1750 tx_config
->coalescing_timeo
= bnad
->tx_coalescing_timeo
;
1752 /* Get BNA's resource requirement for one tx object */
1753 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1754 bna_tx_res_req(bnad
->num_txq_per_tx
,
1755 bnad
->txq_depth
, res_info
);
1756 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1758 /* Fill Unmap Q memory requirements */
1759 BNAD_FILL_UNMAPQ_MEM_REQ(
1760 &res_info
[BNA_TX_RES_MEM_T_UNMAPQ
],
1761 bnad
->num_txq_per_tx
,
1762 BNAD_TX_UNMAPQ_DEPTH
);
1764 /* Allocate resources */
1765 err
= bnad_tx_res_alloc(bnad
, res_info
, tx_id
);
1769 /* Ask BNA to create one Tx object, supplying required resources */
1770 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1771 tx
= bna_tx_create(&bnad
->bna
, bnad
, tx_config
, &tx_cbfn
, res_info
,
1773 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1778 /* Register ISR for the Tx object */
1779 if (intr_info
->intr_type
== BNA_INTR_T_MSIX
) {
1780 err
= bnad_tx_msix_register(bnad
, tx_info
,
1781 tx_id
, bnad
->num_txq_per_tx
);
1786 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1788 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1793 bnad_tx_res_free(bnad
, res_info
);
1797 /* Setup the rx config for bna_rx_create */
1798 /* bnad decides the configuration */
1800 bnad_init_rx_config(struct bnad
*bnad
, struct bna_rx_config
*rx_config
)
1802 rx_config
->rx_type
= BNA_RX_T_REGULAR
;
1803 rx_config
->num_paths
= bnad
->num_rxp_per_rx
;
1804 rx_config
->coalescing_timeo
= bnad
->rx_coalescing_timeo
;
1806 if (bnad
->num_rxp_per_rx
> 1) {
1807 rx_config
->rss_status
= BNA_STATUS_T_ENABLED
;
1808 rx_config
->rss_config
.hash_type
=
1809 (BFI_ENET_RSS_IPV6
|
1810 BFI_ENET_RSS_IPV6_TCP
|
1812 BFI_ENET_RSS_IPV4_TCP
);
1813 rx_config
->rss_config
.hash_mask
=
1814 bnad
->num_rxp_per_rx
- 1;
1815 get_random_bytes(rx_config
->rss_config
.toeplitz_hash_key
,
1816 sizeof(rx_config
->rss_config
.toeplitz_hash_key
));
1818 rx_config
->rss_status
= BNA_STATUS_T_DISABLED
;
1819 memset(&rx_config
->rss_config
, 0,
1820 sizeof(rx_config
->rss_config
));
1822 rx_config
->rxp_type
= BNA_RXP_SLR
;
1823 rx_config
->q_depth
= bnad
->rxq_depth
;
1825 rx_config
->small_buff_size
= BFI_SMALL_RXBUF_SIZE
;
1827 rx_config
->vlan_strip_status
= BNA_STATUS_T_ENABLED
;
1831 bnad_rx_ctrl_init(struct bnad
*bnad
, u32 rx_id
)
1833 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[rx_id
];
1836 for (i
= 0; i
< bnad
->num_rxp_per_rx
; i
++)
1837 rx_info
->rx_ctrl
[i
].bnad
= bnad
;
1840 /* Called with mutex_lock(&bnad->conf_mutex) held */
1842 bnad_cleanup_rx(struct bnad
*bnad
, u32 rx_id
)
1844 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[rx_id
];
1845 struct bna_rx_config
*rx_config
= &bnad
->rx_config
[rx_id
];
1846 struct bna_res_info
*res_info
= &bnad
->rx_res_info
[rx_id
].res_info
[0];
1847 unsigned long flags
;
1854 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1855 if (bnad
->cfg_flags
& BNAD_CF_DIM_ENABLED
&&
1856 test_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
)) {
1857 clear_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
);
1860 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1862 del_timer_sync(&bnad
->dim_timer
);
1865 init_completion(&bnad
->bnad_completions
.rx_comp
);
1866 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1867 bna_rx_disable(rx_info
->rx
, BNA_HARD_CLEANUP
, bnad_cb_rx_disabled
);
1868 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1869 wait_for_completion(&bnad
->bnad_completions
.rx_comp
);
1871 if (rx_info
->rx_ctrl
[0].ccb
->intr_type
== BNA_INTR_T_MSIX
)
1872 bnad_rx_msix_unregister(bnad
, rx_info
, rx_config
->num_paths
);
1874 bnad_napi_disable(bnad
, rx_id
);
1876 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1877 bna_rx_destroy(rx_info
->rx
);
1878 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1883 bnad_rx_res_free(bnad
, res_info
);
1886 /* Called with mutex_lock(&bnad->conf_mutex) held */
1888 bnad_setup_rx(struct bnad
*bnad
, u32 rx_id
)
1891 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[rx_id
];
1892 struct bna_res_info
*res_info
= &bnad
->rx_res_info
[rx_id
].res_info
[0];
1893 struct bna_intr_info
*intr_info
=
1894 &res_info
[BNA_RX_RES_T_INTR
].res_u
.intr_info
;
1895 struct bna_rx_config
*rx_config
= &bnad
->rx_config
[rx_id
];
1896 static const struct bna_rx_event_cbfn rx_cbfn
= {
1897 .rcb_setup_cbfn
= bnad_cb_rcb_setup
,
1898 .rcb_destroy_cbfn
= bnad_cb_rcb_destroy
,
1899 .ccb_setup_cbfn
= bnad_cb_ccb_setup
,
1900 .ccb_destroy_cbfn
= bnad_cb_ccb_destroy
,
1901 .rx_cleanup_cbfn
= bnad_cb_rx_cleanup
,
1902 .rx_post_cbfn
= bnad_cb_rx_post
,
1905 unsigned long flags
;
1907 rx_info
->rx_id
= rx_id
;
1909 /* Initialize the Rx object configuration */
1910 bnad_init_rx_config(bnad
, rx_config
);
1912 /* Get BNA's resource requirement for one Rx object */
1913 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1914 bna_rx_res_req(rx_config
, res_info
);
1915 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1917 /* Fill Unmap Q memory requirements */
1918 BNAD_FILL_UNMAPQ_MEM_REQ(
1919 &res_info
[BNA_RX_RES_MEM_T_UNMAPQ
],
1920 rx_config
->num_paths
+
1921 ((rx_config
->rxp_type
== BNA_RXP_SINGLE
) ? 0 :
1922 rx_config
->num_paths
), BNAD_RX_UNMAPQ_DEPTH
);
1924 /* Allocate resource */
1925 err
= bnad_rx_res_alloc(bnad
, res_info
, rx_id
);
1929 bnad_rx_ctrl_init(bnad
, rx_id
);
1931 /* Ask BNA to create one Rx object, supplying required resources */
1932 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1933 rx
= bna_rx_create(&bnad
->bna
, bnad
, rx_config
, &rx_cbfn
, res_info
,
1935 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1943 * Init NAPI, so that state is set to NAPI_STATE_SCHED,
1944 * so that IRQ handler cannot schedule NAPI at this point.
1946 bnad_napi_init(bnad
, rx_id
);
1948 /* Register ISR for the Rx object */
1949 if (intr_info
->intr_type
== BNA_INTR_T_MSIX
) {
1950 err
= bnad_rx_msix_register(bnad
, rx_info
, rx_id
,
1951 rx_config
->num_paths
);
1956 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1958 /* Set up Dynamic Interrupt Moderation Vector */
1959 if (bnad
->cfg_flags
& BNAD_CF_DIM_ENABLED
)
1960 bna_rx_dim_reconfig(&bnad
->bna
, bna_napi_dim_vector
);
1962 /* Enable VLAN filtering only on the default Rx */
1963 bna_rx_vlanfilter_enable(rx
);
1965 /* Start the DIM timer */
1966 bnad_dim_timer_start(bnad
);
1970 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1972 /* Enable scheduling of NAPI */
1973 bnad_napi_enable(bnad
, rx_id
);
1978 bnad_cleanup_rx(bnad
, rx_id
);
1982 /* Called with conf_lock & bnad->bna_lock held */
1984 bnad_tx_coalescing_timeo_set(struct bnad
*bnad
)
1986 struct bnad_tx_info
*tx_info
;
1988 tx_info
= &bnad
->tx_info
[0];
1992 bna_tx_coalescing_timeo_set(tx_info
->tx
, bnad
->tx_coalescing_timeo
);
1995 /* Called with conf_lock & bnad->bna_lock held */
1997 bnad_rx_coalescing_timeo_set(struct bnad
*bnad
)
1999 struct bnad_rx_info
*rx_info
;
2002 for (i
= 0; i
< bnad
->num_rx
; i
++) {
2003 rx_info
= &bnad
->rx_info
[i
];
2006 bna_rx_coalescing_timeo_set(rx_info
->rx
,
2007 bnad
->rx_coalescing_timeo
);
2012 * Called with bnad->bna_lock held
2015 bnad_mac_addr_set_locked(struct bnad
*bnad
, u8
*mac_addr
)
2019 if (!is_valid_ether_addr(mac_addr
))
2020 return -EADDRNOTAVAIL
;
2022 /* If datapath is down, pretend everything went through */
2023 if (!bnad
->rx_info
[0].rx
)
2026 ret
= bna_rx_ucast_set(bnad
->rx_info
[0].rx
, mac_addr
, NULL
);
2027 if (ret
!= BNA_CB_SUCCESS
)
2028 return -EADDRNOTAVAIL
;
2033 /* Should be called with conf_lock held */
2035 bnad_enable_default_bcast(struct bnad
*bnad
)
2037 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[0];
2039 unsigned long flags
;
2041 init_completion(&bnad
->bnad_completions
.mcast_comp
);
2043 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2044 ret
= bna_rx_mcast_add(rx_info
->rx
, (u8
*)bnad_bcast_addr
,
2045 bnad_cb_rx_mcast_add
);
2046 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2048 if (ret
== BNA_CB_SUCCESS
)
2049 wait_for_completion(&bnad
->bnad_completions
.mcast_comp
);
2053 if (bnad
->bnad_completions
.mcast_comp_status
!= BNA_CB_SUCCESS
)
2059 /* Called with mutex_lock(&bnad->conf_mutex) held */
2061 bnad_restore_vlans(struct bnad
*bnad
, u32 rx_id
)
2064 unsigned long flags
;
2066 for_each_set_bit(vid
, bnad
->active_vlans
, VLAN_N_VID
) {
2067 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2068 bna_rx_vlan_add(bnad
->rx_info
[rx_id
].rx
, vid
);
2069 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2073 /* Statistics utilities */
2075 bnad_netdev_qstats_fill(struct bnad
*bnad
, struct rtnl_link_stats64
*stats
)
2079 for (i
= 0; i
< bnad
->num_rx
; i
++) {
2080 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
2081 if (bnad
->rx_info
[i
].rx_ctrl
[j
].ccb
) {
2082 stats
->rx_packets
+= bnad
->rx_info
[i
].
2083 rx_ctrl
[j
].ccb
->rcb
[0]->rxq
->rx_packets
;
2084 stats
->rx_bytes
+= bnad
->rx_info
[i
].
2085 rx_ctrl
[j
].ccb
->rcb
[0]->rxq
->rx_bytes
;
2086 if (bnad
->rx_info
[i
].rx_ctrl
[j
].ccb
->rcb
[1] &&
2087 bnad
->rx_info
[i
].rx_ctrl
[j
].ccb
->
2089 stats
->rx_packets
+=
2090 bnad
->rx_info
[i
].rx_ctrl
[j
].
2091 ccb
->rcb
[1]->rxq
->rx_packets
;
2093 bnad
->rx_info
[i
].rx_ctrl
[j
].
2094 ccb
->rcb
[1]->rxq
->rx_bytes
;
2099 for (i
= 0; i
< bnad
->num_tx
; i
++) {
2100 for (j
= 0; j
< bnad
->num_txq_per_tx
; j
++) {
2101 if (bnad
->tx_info
[i
].tcb
[j
]) {
2102 stats
->tx_packets
+=
2103 bnad
->tx_info
[i
].tcb
[j
]->txq
->tx_packets
;
2105 bnad
->tx_info
[i
].tcb
[j
]->txq
->tx_bytes
;
2112 * Must be called with the bna_lock held.
2115 bnad_netdev_hwstats_fill(struct bnad
*bnad
, struct rtnl_link_stats64
*stats
)
2117 struct bfi_enet_stats_mac
*mac_stats
;
2121 mac_stats
= &bnad
->stats
.bna_stats
->hw_stats
.mac_stats
;
2123 mac_stats
->rx_fcs_error
+ mac_stats
->rx_alignment_error
+
2124 mac_stats
->rx_frame_length_error
+ mac_stats
->rx_code_error
+
2125 mac_stats
->rx_undersize
;
2126 stats
->tx_errors
= mac_stats
->tx_fcs_error
+
2127 mac_stats
->tx_undersize
;
2128 stats
->rx_dropped
= mac_stats
->rx_drop
;
2129 stats
->tx_dropped
= mac_stats
->tx_drop
;
2130 stats
->multicast
= mac_stats
->rx_multicast
;
2131 stats
->collisions
= mac_stats
->tx_total_collision
;
2133 stats
->rx_length_errors
= mac_stats
->rx_frame_length_error
;
2135 /* receive ring buffer overflow ?? */
2137 stats
->rx_crc_errors
= mac_stats
->rx_fcs_error
;
2138 stats
->rx_frame_errors
= mac_stats
->rx_alignment_error
;
2139 /* recv'r fifo overrun */
2140 bmap
= bna_rx_rid_mask(&bnad
->bna
);
2141 for (i
= 0; bmap
; i
++) {
2143 stats
->rx_fifo_errors
+=
2144 bnad
->stats
.bna_stats
->
2145 hw_stats
.rxf_stats
[i
].frame_drops
;
2153 bnad_mbox_irq_sync(struct bnad
*bnad
)
2156 unsigned long flags
;
2158 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2159 if (bnad
->cfg_flags
& BNAD_CF_MSIX
)
2160 irq
= bnad
->msix_table
[BNAD_MAILBOX_MSIX_INDEX
].vector
;
2162 irq
= bnad
->pcidev
->irq
;
2163 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2165 synchronize_irq(irq
);
2168 /* Utility used by bnad_start_xmit, for doing TSO */
2170 bnad_tso_prepare(struct bnad
*bnad
, struct sk_buff
*skb
)
2174 if (skb_header_cloned(skb
)) {
2175 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
2177 BNAD_UPDATE_CTR(bnad
, tso_err
);
2183 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2184 * excluding the length field.
2186 if (skb
->protocol
== htons(ETH_P_IP
)) {
2187 struct iphdr
*iph
= ip_hdr(skb
);
2189 /* Do we really need these? */
2193 tcp_hdr(skb
)->check
=
2194 ~csum_tcpudp_magic(iph
->saddr
, iph
->daddr
, 0,
2196 BNAD_UPDATE_CTR(bnad
, tso4
);
2198 struct ipv6hdr
*ipv6h
= ipv6_hdr(skb
);
2200 ipv6h
->payload_len
= 0;
2201 tcp_hdr(skb
)->check
=
2202 ~csum_ipv6_magic(&ipv6h
->saddr
, &ipv6h
->daddr
, 0,
2204 BNAD_UPDATE_CTR(bnad
, tso6
);
2211 * Initialize Q numbers depending on Rx Paths
2212 * Called with bnad->bna_lock held, because of cfg_flags
2216 bnad_q_num_init(struct bnad
*bnad
)
2220 rxps
= min((uint
)num_online_cpus(),
2221 (uint
)(BNAD_MAX_RX
* BNAD_MAX_RXP_PER_RX
));
2223 if (!(bnad
->cfg_flags
& BNAD_CF_MSIX
))
2224 rxps
= 1; /* INTx */
2228 bnad
->num_rxp_per_rx
= rxps
;
2229 bnad
->num_txq_per_tx
= BNAD_TXQ_NUM
;
2233 * Adjusts the Q numbers, given a number of msix vectors
2234 * Give preference to RSS as opposed to Tx priority Queues,
2235 * in such a case, just use 1 Tx Q
2236 * Called with bnad->bna_lock held b'cos of cfg_flags access
2239 bnad_q_num_adjust(struct bnad
*bnad
, int msix_vectors
, int temp
)
2241 bnad
->num_txq_per_tx
= 1;
2242 if ((msix_vectors
>= (bnad
->num_tx
* bnad
->num_txq_per_tx
) +
2243 bnad_rxqs_per_cq
+ BNAD_MAILBOX_MSIX_VECTORS
) &&
2244 (bnad
->cfg_flags
& BNAD_CF_MSIX
)) {
2245 bnad
->num_rxp_per_rx
= msix_vectors
-
2246 (bnad
->num_tx
* bnad
->num_txq_per_tx
) -
2247 BNAD_MAILBOX_MSIX_VECTORS
;
2249 bnad
->num_rxp_per_rx
= 1;
2252 /* Enable / disable ioceth */
2254 bnad_ioceth_disable(struct bnad
*bnad
)
2256 unsigned long flags
;
2259 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2260 init_completion(&bnad
->bnad_completions
.ioc_comp
);
2261 bna_ioceth_disable(&bnad
->bna
.ioceth
, BNA_HARD_CLEANUP
);
2262 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2264 wait_for_completion_timeout(&bnad
->bnad_completions
.ioc_comp
,
2265 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT
));
2267 err
= bnad
->bnad_completions
.ioc_comp_status
;
2272 bnad_ioceth_enable(struct bnad
*bnad
)
2275 unsigned long flags
;
2277 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2278 init_completion(&bnad
->bnad_completions
.ioc_comp
);
2279 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_WAITING
;
2280 bna_ioceth_enable(&bnad
->bna
.ioceth
);
2281 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2283 wait_for_completion_timeout(&bnad
->bnad_completions
.ioc_comp
,
2284 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT
));
2286 err
= bnad
->bnad_completions
.ioc_comp_status
;
2291 /* Free BNA resources */
2293 bnad_res_free(struct bnad
*bnad
, struct bna_res_info
*res_info
,
2298 for (i
= 0; i
< res_val_max
; i
++)
2299 bnad_mem_free(bnad
, &res_info
[i
].res_u
.mem_info
);
2302 /* Allocates memory and interrupt resources for BNA */
2304 bnad_res_alloc(struct bnad
*bnad
, struct bna_res_info
*res_info
,
2309 for (i
= 0; i
< res_val_max
; i
++) {
2310 err
= bnad_mem_alloc(bnad
, &res_info
[i
].res_u
.mem_info
);
2317 bnad_res_free(bnad
, res_info
, res_val_max
);
2321 /* Interrupt enable / disable */
2323 bnad_enable_msix(struct bnad
*bnad
)
2326 unsigned long flags
;
2328 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2329 if (!(bnad
->cfg_flags
& BNAD_CF_MSIX
)) {
2330 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2333 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2335 if (bnad
->msix_table
)
2339 kcalloc(bnad
->msix_num
, sizeof(struct msix_entry
), GFP_KERNEL
);
2341 if (!bnad
->msix_table
)
2344 for (i
= 0; i
< bnad
->msix_num
; i
++)
2345 bnad
->msix_table
[i
].entry
= i
;
2347 ret
= pci_enable_msix(bnad
->pcidev
, bnad
->msix_table
, bnad
->msix_num
);
2349 /* Not enough MSI-X vectors. */
2350 pr_warn("BNA: %d MSI-X vectors allocated < %d requested\n",
2351 ret
, bnad
->msix_num
);
2353 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2354 /* ret = #of vectors that we got */
2355 bnad_q_num_adjust(bnad
, (ret
- BNAD_MAILBOX_MSIX_VECTORS
) / 2,
2356 (ret
- BNAD_MAILBOX_MSIX_VECTORS
) / 2);
2357 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2359 bnad
->msix_num
= BNAD_NUM_TXQ
+ BNAD_NUM_RXP
+
2360 BNAD_MAILBOX_MSIX_VECTORS
;
2362 if (bnad
->msix_num
> ret
)
2365 /* Try once more with adjusted numbers */
2366 /* If this fails, fall back to INTx */
2367 ret
= pci_enable_msix(bnad
->pcidev
, bnad
->msix_table
,
2375 pci_intx(bnad
->pcidev
, 0);
2380 pr_warn("BNA: MSI-X enable failed - operating in INTx mode\n");
2382 kfree(bnad
->msix_table
);
2383 bnad
->msix_table
= NULL
;
2385 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2386 bnad
->cfg_flags
&= ~BNAD_CF_MSIX
;
2387 bnad_q_num_init(bnad
);
2388 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2392 bnad_disable_msix(struct bnad
*bnad
)
2395 unsigned long flags
;
2397 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2398 cfg_flags
= bnad
->cfg_flags
;
2399 if (bnad
->cfg_flags
& BNAD_CF_MSIX
)
2400 bnad
->cfg_flags
&= ~BNAD_CF_MSIX
;
2401 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2403 if (cfg_flags
& BNAD_CF_MSIX
) {
2404 pci_disable_msix(bnad
->pcidev
);
2405 kfree(bnad
->msix_table
);
2406 bnad
->msix_table
= NULL
;
2410 /* Netdev entry points */
2412 bnad_open(struct net_device
*netdev
)
2415 struct bnad
*bnad
= netdev_priv(netdev
);
2416 struct bna_pause_config pause_config
;
2418 unsigned long flags
;
2420 mutex_lock(&bnad
->conf_mutex
);
2423 err
= bnad_setup_tx(bnad
, 0);
2428 err
= bnad_setup_rx(bnad
, 0);
2433 pause_config
.tx_pause
= 0;
2434 pause_config
.rx_pause
= 0;
2436 mtu
= ETH_HLEN
+ VLAN_HLEN
+ bnad
->netdev
->mtu
+ ETH_FCS_LEN
;
2438 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2439 bna_enet_mtu_set(&bnad
->bna
.enet
, mtu
, NULL
);
2440 bna_enet_pause_config(&bnad
->bna
.enet
, &pause_config
, NULL
);
2441 bna_enet_enable(&bnad
->bna
.enet
);
2442 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2444 /* Enable broadcast */
2445 bnad_enable_default_bcast(bnad
);
2447 /* Restore VLANs, if any */
2448 bnad_restore_vlans(bnad
, 0);
2450 /* Set the UCAST address */
2451 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2452 bnad_mac_addr_set_locked(bnad
, netdev
->dev_addr
);
2453 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2455 /* Start the stats timer */
2456 bnad_stats_timer_start(bnad
);
2458 mutex_unlock(&bnad
->conf_mutex
);
2463 bnad_cleanup_tx(bnad
, 0);
2466 mutex_unlock(&bnad
->conf_mutex
);
2471 bnad_stop(struct net_device
*netdev
)
2473 struct bnad
*bnad
= netdev_priv(netdev
);
2474 unsigned long flags
;
2476 mutex_lock(&bnad
->conf_mutex
);
2478 /* Stop the stats timer */
2479 bnad_stats_timer_stop(bnad
);
2481 init_completion(&bnad
->bnad_completions
.enet_comp
);
2483 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2484 bna_enet_disable(&bnad
->bna
.enet
, BNA_HARD_CLEANUP
,
2485 bnad_cb_enet_disabled
);
2486 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2488 wait_for_completion(&bnad
->bnad_completions
.enet_comp
);
2490 bnad_cleanup_tx(bnad
, 0);
2491 bnad_cleanup_rx(bnad
, 0);
2493 /* Synchronize mailbox IRQ */
2494 bnad_mbox_irq_sync(bnad
);
2496 mutex_unlock(&bnad
->conf_mutex
);
2503 * bnad_start_xmit : Netdev entry point for Transmit
2504 * Called under lock held by net_device
2507 bnad_start_xmit(struct sk_buff
*skb
, struct net_device
*netdev
)
2509 struct bnad
*bnad
= netdev_priv(netdev
);
2511 struct bna_tcb
*tcb
= bnad
->tx_info
[0].tcb
[txq_id
];
2513 u16 txq_prod
, vlan_tag
= 0;
2514 u32 unmap_prod
, wis
, wis_used
, wi_range
;
2515 u32 vectors
, vect_id
, i
, acked
;
2520 struct bnad_unmap_q
*unmap_q
= tcb
->unmap_q
;
2521 dma_addr_t dma_addr
;
2522 struct bna_txq_entry
*txqent
;
2525 if (unlikely(skb
->len
<= ETH_HLEN
)) {
2527 BNAD_UPDATE_CTR(bnad
, tx_skb_too_short
);
2528 return NETDEV_TX_OK
;
2530 if (unlikely(skb_headlen(skb
) > BFI_TX_MAX_DATA_PER_VECTOR
)) {
2532 BNAD_UPDATE_CTR(bnad
, tx_skb_headlen_too_long
);
2533 return NETDEV_TX_OK
;
2535 if (unlikely(skb_headlen(skb
) == 0)) {
2537 BNAD_UPDATE_CTR(bnad
, tx_skb_headlen_zero
);
2538 return NETDEV_TX_OK
;
2542 * Takes care of the Tx that is scheduled between clearing the flag
2543 * and the netif_tx_stop_all_queues() call.
2545 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
))) {
2547 BNAD_UPDATE_CTR(bnad
, tx_skb_stopping
);
2548 return NETDEV_TX_OK
;
2551 vectors
= 1 + skb_shinfo(skb
)->nr_frags
;
2552 if (unlikely(vectors
> BFI_TX_MAX_VECTORS_PER_PKT
)) {
2554 BNAD_UPDATE_CTR(bnad
, tx_skb_max_vectors
);
2555 return NETDEV_TX_OK
;
2557 wis
= BNA_TXQ_WI_NEEDED(vectors
); /* 4 vectors per work item */
2559 if (unlikely(wis
> BNA_QE_FREE_CNT(tcb
, tcb
->q_depth
) ||
2560 vectors
> BNA_QE_FREE_CNT(unmap_q
, unmap_q
->q_depth
))) {
2561 if ((u16
) (*tcb
->hw_consumer_index
) !=
2562 tcb
->consumer_index
&&
2563 !test_and_set_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
)) {
2564 acked
= bnad_free_txbufs(bnad
, tcb
);
2565 if (likely(test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)))
2566 bna_ib_ack(tcb
->i_dbell
, acked
);
2567 smp_mb__before_clear_bit();
2568 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
2570 netif_stop_queue(netdev
);
2571 BNAD_UPDATE_CTR(bnad
, netif_queue_stop
);
2576 * Check again to deal with race condition between
2577 * netif_stop_queue here, and netif_wake_queue in
2578 * interrupt handler which is not inside netif tx lock.
2581 (wis
> BNA_QE_FREE_CNT(tcb
, tcb
->q_depth
) ||
2582 vectors
> BNA_QE_FREE_CNT(unmap_q
, unmap_q
->q_depth
))) {
2583 BNAD_UPDATE_CTR(bnad
, netif_queue_stop
);
2584 return NETDEV_TX_BUSY
;
2586 netif_wake_queue(netdev
);
2587 BNAD_UPDATE_CTR(bnad
, netif_queue_wakeup
);
2591 unmap_prod
= unmap_q
->producer_index
;
2594 txq_prod
= tcb
->producer_index
;
2595 BNA_TXQ_QPGE_PTR_GET(txq_prod
, tcb
->sw_qpt
, txqent
, wi_range
);
2596 txqent
->hdr
.wi
.reserved
= 0;
2597 txqent
->hdr
.wi
.num_vectors
= vectors
;
2599 if (vlan_tx_tag_present(skb
)) {
2600 vlan_tag
= (u16
) vlan_tx_tag_get(skb
);
2601 flags
|= (BNA_TXQ_WI_CF_INS_PRIO
| BNA_TXQ_WI_CF_INS_VLAN
);
2603 if (test_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
)) {
2605 (tcb
->priority
& 0x7) << 13 | (vlan_tag
& 0x1fff);
2606 flags
|= (BNA_TXQ_WI_CF_INS_PRIO
| BNA_TXQ_WI_CF_INS_VLAN
);
2609 txqent
->hdr
.wi
.vlan_tag
= htons(vlan_tag
);
2611 if (skb_is_gso(skb
)) {
2612 gso_size
= skb_shinfo(skb
)->gso_size
;
2614 if (unlikely(gso_size
> netdev
->mtu
)) {
2616 BNAD_UPDATE_CTR(bnad
, tx_skb_mss_too_long
);
2617 return NETDEV_TX_OK
;
2619 if (unlikely((gso_size
+ skb_transport_offset(skb
) +
2620 tcp_hdrlen(skb
)) >= skb
->len
)) {
2621 txqent
->hdr
.wi
.opcode
=
2622 __constant_htons(BNA_TXQ_WI_SEND
);
2623 txqent
->hdr
.wi
.lso_mss
= 0;
2624 BNAD_UPDATE_CTR(bnad
, tx_skb_tso_too_short
);
2626 txqent
->hdr
.wi
.opcode
=
2627 __constant_htons(BNA_TXQ_WI_SEND_LSO
);
2628 txqent
->hdr
.wi
.lso_mss
= htons(gso_size
);
2631 err
= bnad_tso_prepare(bnad
, skb
);
2632 if (unlikely(err
)) {
2634 BNAD_UPDATE_CTR(bnad
, tx_skb_tso_prepare
);
2635 return NETDEV_TX_OK
;
2637 flags
|= (BNA_TXQ_WI_CF_IP_CKSUM
| BNA_TXQ_WI_CF_TCP_CKSUM
);
2638 txqent
->hdr
.wi
.l4_hdr_size_n_offset
=
2639 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2640 (tcp_hdrlen(skb
) >> 2,
2641 skb_transport_offset(skb
)));
2643 txqent
->hdr
.wi
.opcode
= __constant_htons(BNA_TXQ_WI_SEND
);
2644 txqent
->hdr
.wi
.lso_mss
= 0;
2646 if (unlikely(skb
->len
> (netdev
->mtu
+ ETH_HLEN
))) {
2648 BNAD_UPDATE_CTR(bnad
, tx_skb_non_tso_too_long
);
2649 return NETDEV_TX_OK
;
2652 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2655 if (skb
->protocol
== __constant_htons(ETH_P_IP
))
2656 proto
= ip_hdr(skb
)->protocol
;
2657 else if (skb
->protocol
==
2658 __constant_htons(ETH_P_IPV6
)) {
2659 /* nexthdr may not be TCP immediately. */
2660 proto
= ipv6_hdr(skb
)->nexthdr
;
2662 if (proto
== IPPROTO_TCP
) {
2663 flags
|= BNA_TXQ_WI_CF_TCP_CKSUM
;
2664 txqent
->hdr
.wi
.l4_hdr_size_n_offset
=
2665 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2666 (0, skb_transport_offset(skb
)));
2668 BNAD_UPDATE_CTR(bnad
, tcpcsum_offload
);
2670 if (unlikely(skb_headlen(skb
) <
2671 skb_transport_offset(skb
) + tcp_hdrlen(skb
))) {
2673 BNAD_UPDATE_CTR(bnad
, tx_skb_tcp_hdr
);
2674 return NETDEV_TX_OK
;
2677 } else if (proto
== IPPROTO_UDP
) {
2678 flags
|= BNA_TXQ_WI_CF_UDP_CKSUM
;
2679 txqent
->hdr
.wi
.l4_hdr_size_n_offset
=
2680 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2681 (0, skb_transport_offset(skb
)));
2683 BNAD_UPDATE_CTR(bnad
, udpcsum_offload
);
2684 if (unlikely(skb_headlen(skb
) <
2685 skb_transport_offset(skb
) +
2686 sizeof(struct udphdr
))) {
2688 BNAD_UPDATE_CTR(bnad
, tx_skb_udp_hdr
);
2689 return NETDEV_TX_OK
;
2693 BNAD_UPDATE_CTR(bnad
, tx_skb_csum_err
);
2694 return NETDEV_TX_OK
;
2697 txqent
->hdr
.wi
.l4_hdr_size_n_offset
= 0;
2701 txqent
->hdr
.wi
.flags
= htons(flags
);
2703 txqent
->hdr
.wi
.frame_length
= htonl(skb
->len
);
2705 unmap_q
->unmap_array
[unmap_prod
].skb
= skb
;
2706 len
= skb_headlen(skb
);
2707 txqent
->vector
[0].length
= htons(len
);
2708 dma_addr
= dma_map_single(&bnad
->pcidev
->dev
, skb
->data
,
2709 skb_headlen(skb
), DMA_TO_DEVICE
);
2710 dma_unmap_addr_set(&unmap_q
->unmap_array
[unmap_prod
], dma_addr
,
2713 BNA_SET_DMA_ADDR(dma_addr
, &txqent
->vector
[0].host_addr
);
2714 BNA_QE_INDX_ADD(unmap_prod
, 1, unmap_q
->q_depth
);
2719 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
2720 struct skb_frag_struct
*frag
= &skb_shinfo(skb
)->frags
[i
];
2721 u16 size
= frag
->size
;
2723 if (unlikely(size
== 0)) {
2724 unmap_prod
= unmap_q
->producer_index
;
2726 unmap_prod
= bnad_pci_unmap_skb(&bnad
->pcidev
->dev
,
2727 unmap_q
->unmap_array
,
2728 unmap_prod
, unmap_q
->q_depth
, skb
,
2731 BNAD_UPDATE_CTR(bnad
, tx_skb_frag_zero
);
2732 return NETDEV_TX_OK
;
2737 if (++vect_id
== BFI_TX_MAX_VECTORS_PER_WI
) {
2742 BNA_QE_INDX_ADD(txq_prod
, wis_used
,
2745 BNA_TXQ_QPGE_PTR_GET(txq_prod
, tcb
->sw_qpt
,
2749 txqent
->hdr
.wi_ext
.opcode
=
2750 __constant_htons(BNA_TXQ_WI_EXTENSION
);
2753 BUG_ON(!(size
<= BFI_TX_MAX_DATA_PER_VECTOR
));
2754 txqent
->vector
[vect_id
].length
= htons(size
);
2755 dma_addr
= skb_frag_dma_map(&bnad
->pcidev
->dev
, frag
,
2756 0, size
, DMA_TO_DEVICE
);
2757 dma_unmap_addr_set(&unmap_q
->unmap_array
[unmap_prod
], dma_addr
,
2759 BNA_SET_DMA_ADDR(dma_addr
, &txqent
->vector
[vect_id
].host_addr
);
2760 BNA_QE_INDX_ADD(unmap_prod
, 1, unmap_q
->q_depth
);
2763 if (unlikely(len
!= skb
->len
)) {
2764 unmap_prod
= unmap_q
->producer_index
;
2766 unmap_prod
= bnad_pci_unmap_skb(&bnad
->pcidev
->dev
,
2767 unmap_q
->unmap_array
, unmap_prod
,
2768 unmap_q
->q_depth
, skb
,
2769 skb_shinfo(skb
)->nr_frags
);
2771 BNAD_UPDATE_CTR(bnad
, tx_skb_len_mismatch
);
2772 return NETDEV_TX_OK
;
2775 unmap_q
->producer_index
= unmap_prod
;
2776 BNA_QE_INDX_ADD(txq_prod
, wis_used
, tcb
->q_depth
);
2777 tcb
->producer_index
= txq_prod
;
2781 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)))
2782 return NETDEV_TX_OK
;
2784 bna_txq_prod_indx_doorbell(tcb
);
2787 if ((u16
) (*tcb
->hw_consumer_index
) != tcb
->consumer_index
)
2788 tasklet_schedule(&bnad
->tx_free_tasklet
);
2790 return NETDEV_TX_OK
;
2794 * Used spin_lock to synchronize reading of stats structures, which
2795 * is written by BNA under the same lock.
2797 static struct rtnl_link_stats64
*
2798 bnad_get_stats64(struct net_device
*netdev
, struct rtnl_link_stats64
*stats
)
2800 struct bnad
*bnad
= netdev_priv(netdev
);
2801 unsigned long flags
;
2803 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2805 bnad_netdev_qstats_fill(bnad
, stats
);
2806 bnad_netdev_hwstats_fill(bnad
, stats
);
2808 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2814 bnad_set_rx_mode(struct net_device
*netdev
)
2816 struct bnad
*bnad
= netdev_priv(netdev
);
2817 u32 new_mask
, valid_mask
;
2818 unsigned long flags
;
2820 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2822 new_mask
= valid_mask
= 0;
2824 if (netdev
->flags
& IFF_PROMISC
) {
2825 if (!(bnad
->cfg_flags
& BNAD_CF_PROMISC
)) {
2826 new_mask
= BNAD_RXMODE_PROMISC_DEFAULT
;
2827 valid_mask
= BNAD_RXMODE_PROMISC_DEFAULT
;
2828 bnad
->cfg_flags
|= BNAD_CF_PROMISC
;
2831 if (bnad
->cfg_flags
& BNAD_CF_PROMISC
) {
2832 new_mask
= ~BNAD_RXMODE_PROMISC_DEFAULT
;
2833 valid_mask
= BNAD_RXMODE_PROMISC_DEFAULT
;
2834 bnad
->cfg_flags
&= ~BNAD_CF_PROMISC
;
2838 if (netdev
->flags
& IFF_ALLMULTI
) {
2839 if (!(bnad
->cfg_flags
& BNAD_CF_ALLMULTI
)) {
2840 new_mask
|= BNA_RXMODE_ALLMULTI
;
2841 valid_mask
|= BNA_RXMODE_ALLMULTI
;
2842 bnad
->cfg_flags
|= BNAD_CF_ALLMULTI
;
2845 if (bnad
->cfg_flags
& BNAD_CF_ALLMULTI
) {
2846 new_mask
&= ~BNA_RXMODE_ALLMULTI
;
2847 valid_mask
|= BNA_RXMODE_ALLMULTI
;
2848 bnad
->cfg_flags
&= ~BNAD_CF_ALLMULTI
;
2852 if (bnad
->rx_info
[0].rx
== NULL
)
2855 bna_rx_mode_set(bnad
->rx_info
[0].rx
, new_mask
, valid_mask
, NULL
);
2857 if (!netdev_mc_empty(netdev
)) {
2859 int mc_count
= netdev_mc_count(netdev
);
2861 /* Index 0 holds the broadcast address */
2863 kzalloc((mc_count
+ 1) * ETH_ALEN
,
2868 memcpy(&mcaddr_list
[0], &bnad_bcast_addr
[0], ETH_ALEN
);
2870 /* Copy rest of the MC addresses */
2871 bnad_netdev_mc_list_get(netdev
, mcaddr_list
);
2873 bna_rx_mcast_listset(bnad
->rx_info
[0].rx
, mc_count
+ 1,
2876 /* Should we enable BNAD_CF_ALLMULTI for err != 0 ? */
2880 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2884 * bna_lock is used to sync writes to netdev->addr
2885 * conf_lock cannot be used since this call may be made
2886 * in a non-blocking context.
2889 bnad_set_mac_address(struct net_device
*netdev
, void *mac_addr
)
2892 struct bnad
*bnad
= netdev_priv(netdev
);
2893 struct sockaddr
*sa
= (struct sockaddr
*)mac_addr
;
2894 unsigned long flags
;
2896 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2898 err
= bnad_mac_addr_set_locked(bnad
, sa
->sa_data
);
2901 memcpy(netdev
->dev_addr
, sa
->sa_data
, netdev
->addr_len
);
2903 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2909 bnad_mtu_set(struct bnad
*bnad
, int mtu
)
2911 unsigned long flags
;
2913 init_completion(&bnad
->bnad_completions
.mtu_comp
);
2915 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2916 bna_enet_mtu_set(&bnad
->bna
.enet
, mtu
, bnad_cb_enet_mtu_set
);
2917 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2919 wait_for_completion(&bnad
->bnad_completions
.mtu_comp
);
2921 return bnad
->bnad_completions
.mtu_comp_status
;
2925 bnad_change_mtu(struct net_device
*netdev
, int new_mtu
)
2927 int err
, mtu
= netdev
->mtu
;
2928 struct bnad
*bnad
= netdev_priv(netdev
);
2930 if (new_mtu
+ ETH_HLEN
< ETH_ZLEN
|| new_mtu
> BNAD_JUMBO_MTU
)
2933 mutex_lock(&bnad
->conf_mutex
);
2935 netdev
->mtu
= new_mtu
;
2937 mtu
= ETH_HLEN
+ VLAN_HLEN
+ new_mtu
+ ETH_FCS_LEN
;
2938 err
= bnad_mtu_set(bnad
, mtu
);
2942 mutex_unlock(&bnad
->conf_mutex
);
2947 bnad_vlan_rx_add_vid(struct net_device
*netdev
,
2950 struct bnad
*bnad
= netdev_priv(netdev
);
2951 unsigned long flags
;
2953 if (!bnad
->rx_info
[0].rx
)
2956 mutex_lock(&bnad
->conf_mutex
);
2958 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2959 bna_rx_vlan_add(bnad
->rx_info
[0].rx
, vid
);
2960 set_bit(vid
, bnad
->active_vlans
);
2961 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2963 mutex_unlock(&bnad
->conf_mutex
);
2967 bnad_vlan_rx_kill_vid(struct net_device
*netdev
,
2970 struct bnad
*bnad
= netdev_priv(netdev
);
2971 unsigned long flags
;
2973 if (!bnad
->rx_info
[0].rx
)
2976 mutex_lock(&bnad
->conf_mutex
);
2978 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2979 clear_bit(vid
, bnad
->active_vlans
);
2980 bna_rx_vlan_del(bnad
->rx_info
[0].rx
, vid
);
2981 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2983 mutex_unlock(&bnad
->conf_mutex
);
2986 #ifdef CONFIG_NET_POLL_CONTROLLER
2988 bnad_netpoll(struct net_device
*netdev
)
2990 struct bnad
*bnad
= netdev_priv(netdev
);
2991 struct bnad_rx_info
*rx_info
;
2992 struct bnad_rx_ctrl
*rx_ctrl
;
2996 if (!(bnad
->cfg_flags
& BNAD_CF_MSIX
)) {
2997 bna_intx_disable(&bnad
->bna
, curr_mask
);
2998 bnad_isr(bnad
->pcidev
->irq
, netdev
);
2999 bna_intx_enable(&bnad
->bna
, curr_mask
);
3002 * Tx processing may happen in sending context, so no need
3003 * to explicitly process completions here
3007 for (i
= 0; i
< bnad
->num_rx
; i
++) {
3008 rx_info
= &bnad
->rx_info
[i
];
3011 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
3012 rx_ctrl
= &rx_info
->rx_ctrl
[j
];
3014 bnad_netif_rx_schedule_poll(bnad
,
3022 static const struct net_device_ops bnad_netdev_ops
= {
3023 .ndo_open
= bnad_open
,
3024 .ndo_stop
= bnad_stop
,
3025 .ndo_start_xmit
= bnad_start_xmit
,
3026 .ndo_get_stats64
= bnad_get_stats64
,
3027 .ndo_set_rx_mode
= bnad_set_rx_mode
,
3028 .ndo_validate_addr
= eth_validate_addr
,
3029 .ndo_set_mac_address
= bnad_set_mac_address
,
3030 .ndo_change_mtu
= bnad_change_mtu
,
3031 .ndo_vlan_rx_add_vid
= bnad_vlan_rx_add_vid
,
3032 .ndo_vlan_rx_kill_vid
= bnad_vlan_rx_kill_vid
,
3033 #ifdef CONFIG_NET_POLL_CONTROLLER
3034 .ndo_poll_controller
= bnad_netpoll
3039 bnad_netdev_init(struct bnad
*bnad
, bool using_dac
)
3041 struct net_device
*netdev
= bnad
->netdev
;
3043 netdev
->hw_features
= NETIF_F_SG
| NETIF_F_RXCSUM
|
3044 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
3045 NETIF_F_TSO
| NETIF_F_TSO6
| NETIF_F_HW_VLAN_TX
;
3047 netdev
->vlan_features
= NETIF_F_SG
| NETIF_F_HIGHDMA
|
3048 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
3049 NETIF_F_TSO
| NETIF_F_TSO6
;
3051 netdev
->features
|= netdev
->hw_features
|
3052 NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_FILTER
;
3055 netdev
->features
|= NETIF_F_HIGHDMA
;
3057 netdev
->mem_start
= bnad
->mmio_start
;
3058 netdev
->mem_end
= bnad
->mmio_start
+ bnad
->mmio_len
- 1;
3060 netdev
->netdev_ops
= &bnad_netdev_ops
;
3061 bnad_set_ethtool_ops(netdev
);
3065 * 1. Initialize the bnad structure
3066 * 2. Setup netdev pointer in pci_dev
3067 * 3. Initialze Tx free tasklet
3068 * 4. Initialize no. of TxQ & CQs & MSIX vectors
3071 bnad_init(struct bnad
*bnad
,
3072 struct pci_dev
*pdev
, struct net_device
*netdev
)
3074 unsigned long flags
;
3076 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
3077 pci_set_drvdata(pdev
, netdev
);
3079 bnad
->netdev
= netdev
;
3080 bnad
->pcidev
= pdev
;
3081 bnad
->mmio_start
= pci_resource_start(pdev
, 0);
3082 bnad
->mmio_len
= pci_resource_len(pdev
, 0);
3083 bnad
->bar0
= ioremap_nocache(bnad
->mmio_start
, bnad
->mmio_len
);
3085 dev_err(&pdev
->dev
, "ioremap for bar0 failed\n");
3086 pci_set_drvdata(pdev
, NULL
);
3089 pr_info("bar0 mapped to %p, len %llu\n", bnad
->bar0
,
3090 (unsigned long long) bnad
->mmio_len
);
3092 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3093 if (!bnad_msix_disable
)
3094 bnad
->cfg_flags
= BNAD_CF_MSIX
;
3096 bnad
->cfg_flags
|= BNAD_CF_DIM_ENABLED
;
3098 bnad_q_num_init(bnad
);
3099 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3101 bnad
->msix_num
= (bnad
->num_tx
* bnad
->num_txq_per_tx
) +
3102 (bnad
->num_rx
* bnad
->num_rxp_per_rx
) +
3103 BNAD_MAILBOX_MSIX_VECTORS
;
3105 bnad
->txq_depth
= BNAD_TXQ_DEPTH
;
3106 bnad
->rxq_depth
= BNAD_RXQ_DEPTH
;
3108 bnad
->tx_coalescing_timeo
= BFI_TX_COALESCING_TIMEO
;
3109 bnad
->rx_coalescing_timeo
= BFI_RX_COALESCING_TIMEO
;
3111 tasklet_init(&bnad
->tx_free_tasklet
, bnad_tx_free_tasklet
,
3112 (unsigned long)bnad
);
3118 * Must be called after bnad_pci_uninit()
3119 * so that iounmap() and pci_set_drvdata(NULL)
3120 * happens only after PCI uninitialization.
3123 bnad_uninit(struct bnad
*bnad
)
3126 iounmap(bnad
->bar0
);
3127 pci_set_drvdata(bnad
->pcidev
, NULL
);
3132 a) Per ioceth mutes used for serializing configuration
3133 changes from OS interface
3134 b) spin lock used to protect bna state machine
3137 bnad_lock_init(struct bnad
*bnad
)
3139 spin_lock_init(&bnad
->bna_lock
);
3140 mutex_init(&bnad
->conf_mutex
);
3144 bnad_lock_uninit(struct bnad
*bnad
)
3146 mutex_destroy(&bnad
->conf_mutex
);
3149 /* PCI Initialization */
3151 bnad_pci_init(struct bnad
*bnad
,
3152 struct pci_dev
*pdev
, bool *using_dac
)
3156 err
= pci_enable_device(pdev
);
3159 err
= pci_request_regions(pdev
, BNAD_NAME
);
3161 goto disable_device
;
3162 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
3163 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
3166 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
3168 err
= dma_set_coherent_mask(&pdev
->dev
,
3171 goto release_regions
;
3175 pci_set_master(pdev
);
3179 pci_release_regions(pdev
);
3181 pci_disable_device(pdev
);
3187 bnad_pci_uninit(struct pci_dev
*pdev
)
3189 pci_release_regions(pdev
);
3190 pci_disable_device(pdev
);
3193 static int __devinit
3194 bnad_pci_probe(struct pci_dev
*pdev
,
3195 const struct pci_device_id
*pcidev_id
)
3201 struct net_device
*netdev
;
3202 struct bfa_pcidev pcidev_info
;
3203 unsigned long flags
;
3205 pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
3206 pdev
, pcidev_id
, PCI_FUNC(pdev
->devfn
));
3208 mutex_lock(&bnad_fwimg_mutex
);
3209 if (!cna_get_firmware_buf(pdev
)) {
3210 mutex_unlock(&bnad_fwimg_mutex
);
3211 pr_warn("Failed to load Firmware Image!\n");
3214 mutex_unlock(&bnad_fwimg_mutex
);
3217 * Allocates sizeof(struct net_device + struct bnad)
3218 * bnad = netdev->priv
3220 netdev
= alloc_etherdev(sizeof(struct bnad
));
3222 dev_err(&pdev
->dev
, "netdev allocation failed\n");
3226 bnad
= netdev_priv(netdev
);
3228 bnad_lock_init(bnad
);
3230 mutex_lock(&bnad
->conf_mutex
);
3232 * PCI initialization
3233 * Output : using_dac = 1 for 64 bit DMA
3234 * = 0 for 32 bit DMA
3236 err
= bnad_pci_init(bnad
, pdev
, &using_dac
);
3241 * Initialize bnad structure
3242 * Setup relation between pci_dev & netdev
3243 * Init Tx free tasklet
3245 err
= bnad_init(bnad
, pdev
, netdev
);
3249 /* Initialize netdev structure, set up ethtool ops */
3250 bnad_netdev_init(bnad
, using_dac
);
3252 /* Set link to down state */
3253 netif_carrier_off(netdev
);
3255 /* Get resource requirement form bna */
3256 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3257 bna_res_req(&bnad
->res_info
[0]);
3258 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3260 /* Allocate resources from bna */
3261 err
= bnad_res_alloc(bnad
, &bnad
->res_info
[0], BNA_RES_T_MAX
);
3267 /* Setup pcidev_info for bna_init() */
3268 pcidev_info
.pci_slot
= PCI_SLOT(bnad
->pcidev
->devfn
);
3269 pcidev_info
.pci_func
= PCI_FUNC(bnad
->pcidev
->devfn
);
3270 pcidev_info
.device_id
= bnad
->pcidev
->device
;
3271 pcidev_info
.pci_bar_kva
= bnad
->bar0
;
3273 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3274 bna_init(bna
, bnad
, &pcidev_info
, &bnad
->res_info
[0]);
3275 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3277 bnad
->stats
.bna_stats
= &bna
->stats
;
3279 bnad_enable_msix(bnad
);
3280 err
= bnad_mbox_irq_alloc(bnad
);
3286 setup_timer(&bnad
->bna
.ioceth
.ioc
.ioc_timer
, bnad_ioc_timeout
,
3287 ((unsigned long)bnad
));
3288 setup_timer(&bnad
->bna
.ioceth
.ioc
.hb_timer
, bnad_ioc_hb_check
,
3289 ((unsigned long)bnad
));
3290 setup_timer(&bnad
->bna
.ioceth
.ioc
.iocpf_timer
, bnad_iocpf_timeout
,
3291 ((unsigned long)bnad
));
3292 setup_timer(&bnad
->bna
.ioceth
.ioc
.sem_timer
, bnad_iocpf_sem_timeout
,
3293 ((unsigned long)bnad
));
3295 /* Now start the timer before calling IOC */
3296 mod_timer(&bnad
->bna
.ioceth
.ioc
.iocpf_timer
,
3297 jiffies
+ msecs_to_jiffies(BNA_IOC_TIMER_FREQ
));
3301 * If the call back comes with error, we bail out.
3302 * This is a catastrophic error.
3304 err
= bnad_ioceth_enable(bnad
);
3306 pr_err("BNA: Initialization failed err=%d\n",
3311 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3312 if (bna_num_txq_set(bna
, BNAD_NUM_TXQ
+ 1) ||
3313 bna_num_rxp_set(bna
, BNAD_NUM_RXP
+ 1)) {
3314 bnad_q_num_adjust(bnad
, bna_attr(bna
)->num_txq
- 1,
3315 bna_attr(bna
)->num_rxp
- 1);
3316 if (bna_num_txq_set(bna
, BNAD_NUM_TXQ
+ 1) ||
3317 bna_num_rxp_set(bna
, BNAD_NUM_RXP
+ 1))
3320 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3322 goto disable_ioceth
;
3324 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3325 bna_mod_res_req(&bnad
->bna
, &bnad
->mod_res_info
[0]);
3326 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3328 err
= bnad_res_alloc(bnad
, &bnad
->mod_res_info
[0], BNA_MOD_RES_T_MAX
);
3331 goto disable_ioceth
;
3334 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3335 bna_mod_init(&bnad
->bna
, &bnad
->mod_res_info
[0]);
3336 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3338 /* Get the burnt-in mac */
3339 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3340 bna_enet_perm_mac_get(&bna
->enet
, &bnad
->perm_addr
);
3341 bnad_set_netdev_perm_addr(bnad
);
3342 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3344 mutex_unlock(&bnad
->conf_mutex
);
3346 /* Finally, reguister with net_device layer */
3347 err
= register_netdev(netdev
);
3349 pr_err("BNA : Registering with netdev failed\n");
3352 set_bit(BNAD_RF_NETDEV_REGISTERED
, &bnad
->run_flags
);
3357 mutex_unlock(&bnad
->conf_mutex
);
3361 bnad_res_free(bnad
, &bnad
->mod_res_info
[0], BNA_MOD_RES_T_MAX
);
3363 bnad_ioceth_disable(bnad
);
3364 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.ioc_timer
);
3365 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.sem_timer
);
3366 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.hb_timer
);
3367 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3369 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3370 bnad_mbox_irq_free(bnad
);
3371 bnad_disable_msix(bnad
);
3373 bnad_res_free(bnad
, &bnad
->res_info
[0], BNA_RES_T_MAX
);
3377 bnad_pci_uninit(pdev
);
3379 mutex_unlock(&bnad
->conf_mutex
);
3380 bnad_lock_uninit(bnad
);
3381 free_netdev(netdev
);
3385 static void __devexit
3386 bnad_pci_remove(struct pci_dev
*pdev
)
3388 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3391 unsigned long flags
;
3396 pr_info("%s bnad_pci_remove\n", netdev
->name
);
3397 bnad
= netdev_priv(netdev
);
3400 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED
, &bnad
->run_flags
))
3401 unregister_netdev(netdev
);
3403 mutex_lock(&bnad
->conf_mutex
);
3404 bnad_ioceth_disable(bnad
);
3405 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.ioc_timer
);
3406 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.sem_timer
);
3407 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.hb_timer
);
3408 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3410 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3412 bnad_res_free(bnad
, &bnad
->mod_res_info
[0], BNA_MOD_RES_T_MAX
);
3413 bnad_res_free(bnad
, &bnad
->res_info
[0], BNA_RES_T_MAX
);
3414 bnad_mbox_irq_free(bnad
);
3415 bnad_disable_msix(bnad
);
3416 bnad_pci_uninit(pdev
);
3417 mutex_unlock(&bnad
->conf_mutex
);
3418 bnad_lock_uninit(bnad
);
3420 free_netdev(netdev
);
3423 static DEFINE_PCI_DEVICE_TABLE(bnad_pci_id_table
) = {
3425 PCI_DEVICE(PCI_VENDOR_ID_BROCADE
,
3426 PCI_DEVICE_ID_BROCADE_CT
),
3427 .class = PCI_CLASS_NETWORK_ETHERNET
<< 8,
3428 .class_mask
= 0xffff00
3432 MODULE_DEVICE_TABLE(pci
, bnad_pci_id_table
);
3434 static struct pci_driver bnad_pci_driver
= {
3436 .id_table
= bnad_pci_id_table
,
3437 .probe
= bnad_pci_probe
,
3438 .remove
= __devexit_p(bnad_pci_remove
),
3442 bnad_module_init(void)
3446 pr_info("Brocade 10G Ethernet driver - version: %s\n",
3449 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover
);
3451 err
= pci_register_driver(&bnad_pci_driver
);
3453 pr_err("bna : PCI registration failed in module init "
3462 bnad_module_exit(void)
3464 pci_unregister_driver(&bnad_pci_driver
);
3467 release_firmware(bfi_fw
);
3470 module_init(bnad_module_init
);
3471 module_exit(bnad_module_exit
);
3473 MODULE_AUTHOR("Brocade");
3474 MODULE_LICENSE("GPL");
3475 MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver");
3476 MODULE_VERSION(BNAD_VERSION
);
3477 MODULE_FIRMWARE(CNA_FW_FILE_CT
);