2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2014 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/sched/signal.h>
24 #include <linux/types.h>
25 #include <linux/compiler.h>
26 #include <linux/slab.h>
27 #include <linux/delay.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
41 #include <linux/if_vlan.h>
43 #include <linux/tcp.h>
44 #include <linux/workqueue.h>
45 #include <linux/prefetch.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/firmware.h>
48 #include <linux/ssb/ssb_driver_gige.h>
49 #include <linux/hwmon.h>
50 #include <linux/hwmon-sysfs.h>
52 #include <net/checksum.h>
56 #include <asm/byteorder.h>
57 #include <linux/uaccess.h>
59 #include <uapi/linux/net_tstamp.h>
60 #include <linux/ptp_clock_kernel.h>
63 #include <asm/idprom.h>
72 /* Functions & macros to verify TG3_FLAGS types */
74 static inline int _tg3_flag(enum TG3_FLAGS flag
, unsigned long *bits
)
76 return test_bit(flag
, bits
);
79 static inline void _tg3_flag_set(enum TG3_FLAGS flag
, unsigned long *bits
)
84 static inline void _tg3_flag_clear(enum TG3_FLAGS flag
, unsigned long *bits
)
86 clear_bit(flag
, bits
);
89 #define tg3_flag(tp, flag) \
90 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
91 #define tg3_flag_set(tp, flag) \
92 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
93 #define tg3_flag_clear(tp, flag) \
94 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
96 #define DRV_MODULE_NAME "tg3"
98 #define TG3_MIN_NUM 137
99 #define DRV_MODULE_VERSION \
100 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
101 #define DRV_MODULE_RELDATE "May 11, 2014"
103 #define RESET_KIND_SHUTDOWN 0
104 #define RESET_KIND_INIT 1
105 #define RESET_KIND_SUSPEND 2
107 #define TG3_DEF_RX_MODE 0
108 #define TG3_DEF_TX_MODE 0
109 #define TG3_DEF_MSG_ENABLE \
119 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
121 /* length of time before we decide the hardware is borked,
122 * and dev->tx_timeout() should be called to fix the problem
125 #define TG3_TX_TIMEOUT (5 * HZ)
127 /* hardware minimum and maximum for a single frame's data payload */
128 #define TG3_MIN_MTU ETH_ZLEN
129 #define TG3_MAX_MTU(tp) \
130 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
132 /* These numbers seem to be hard coded in the NIC firmware somehow.
133 * You can't change the ring sizes, but you can change where you place
134 * them in the NIC onboard memory.
136 #define TG3_RX_STD_RING_SIZE(tp) \
137 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
138 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
139 #define TG3_DEF_RX_RING_PENDING 200
140 #define TG3_RX_JMB_RING_SIZE(tp) \
141 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
142 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
143 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
145 /* Do not place this n-ring entries value into the tp struct itself,
146 * we really want to expose these constants to GCC so that modulo et
147 * al. operations are done with shifts and masks instead of with
148 * hw multiply/modulo instructions. Another solution would be to
149 * replace things like '% foo' with '& (foo - 1)'.
152 #define TG3_TX_RING_SIZE 512
153 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
155 #define TG3_RX_STD_RING_BYTES(tp) \
156 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
157 #define TG3_RX_JMB_RING_BYTES(tp) \
158 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
159 #define TG3_RX_RCB_RING_BYTES(tp) \
160 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
161 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
163 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
165 #define TG3_DMA_BYTE_ENAB 64
167 #define TG3_RX_STD_DMA_SZ 1536
168 #define TG3_RX_JMB_DMA_SZ 9046
170 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
172 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
173 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
175 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
176 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
178 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
179 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
181 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
182 * that are at least dword aligned when used in PCIX mode. The driver
183 * works around this bug by double copying the packet. This workaround
184 * is built into the normal double copy length check for efficiency.
186 * However, the double copy is only necessary on those architectures
187 * where unaligned memory accesses are inefficient. For those architectures
188 * where unaligned memory accesses incur little penalty, we can reintegrate
189 * the 5701 in the normal rx path. Doing so saves a device structure
190 * dereference by hardcoding the double copy threshold in place.
192 #define TG3_RX_COPY_THRESHOLD 256
193 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
194 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
196 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
199 #if (NET_IP_ALIGN != 0)
200 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
202 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
205 /* minimum number of free TX descriptors required to wake up TX process */
206 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
207 #define TG3_TX_BD_DMA_MAX_2K 2048
208 #define TG3_TX_BD_DMA_MAX_4K 4096
210 #define TG3_RAW_IP_ALIGN 2
212 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
213 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
215 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
216 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
218 #define FIRMWARE_TG3 "tigon/tg3.bin"
219 #define FIRMWARE_TG357766 "tigon/tg357766.bin"
220 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
221 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
223 static char version
[] =
224 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")";
226 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
227 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
228 MODULE_LICENSE("GPL");
229 MODULE_VERSION(DRV_MODULE_VERSION
);
230 MODULE_FIRMWARE(FIRMWARE_TG3
);
231 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
232 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
234 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
235 module_param(tg3_debug
, int, 0);
236 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
238 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
239 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
241 static const struct pci_device_id tg3_pci_tbl
[] = {
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
),
261 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
|
262 TG3_DRV_DATA_FLAG_5705_10_100
},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
),
264 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
|
265 TG3_DRV_DATA_FLAG_5705_10_100
},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
),
268 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
|
269 TG3_DRV_DATA_FLAG_5705_10_100
},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750
)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
),
276 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
),
282 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
290 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5787M
,
291 PCI_VENDOR_ID_LENOVO
,
292 TG3PCI_SUBDEVICE_ID_LENOVO_5787M
),
293 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
),
296 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_G
)},
314 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_F
)},
315 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
,
316 PCI_VENDOR_ID_AI
, TG3PCI_SUBDEVICE_ID_ACER_57780_A
),
317 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
318 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
,
319 PCI_VENDOR_ID_AI
, TG3PCI_SUBDEVICE_ID_ACER_57780_B
),
320 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
323 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
),
324 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57788
)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5717
)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5717_C
)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5718
)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57781
)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57785
)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57761
)},
332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57765
)},
333 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57791
),
334 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
335 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57795
),
336 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5719
)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5720
)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57762
)},
340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57766
)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5762
)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5725
)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5727
)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57764
)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57767
)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57787
)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57782
)},
348 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57786
)},
349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
350 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
354 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
355 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
356 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
360 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
362 static const struct {
363 const char string
[ETH_GSTRING_LEN
];
364 } ethtool_stats_keys
[] = {
367 { "rx_ucast_packets" },
368 { "rx_mcast_packets" },
369 { "rx_bcast_packets" },
371 { "rx_align_errors" },
372 { "rx_xon_pause_rcvd" },
373 { "rx_xoff_pause_rcvd" },
374 { "rx_mac_ctrl_rcvd" },
375 { "rx_xoff_entered" },
376 { "rx_frame_too_long_errors" },
378 { "rx_undersize_packets" },
379 { "rx_in_length_errors" },
380 { "rx_out_length_errors" },
381 { "rx_64_or_less_octet_packets" },
382 { "rx_65_to_127_octet_packets" },
383 { "rx_128_to_255_octet_packets" },
384 { "rx_256_to_511_octet_packets" },
385 { "rx_512_to_1023_octet_packets" },
386 { "rx_1024_to_1522_octet_packets" },
387 { "rx_1523_to_2047_octet_packets" },
388 { "rx_2048_to_4095_octet_packets" },
389 { "rx_4096_to_8191_octet_packets" },
390 { "rx_8192_to_9022_octet_packets" },
397 { "tx_flow_control" },
399 { "tx_single_collisions" },
400 { "tx_mult_collisions" },
402 { "tx_excessive_collisions" },
403 { "tx_late_collisions" },
404 { "tx_collide_2times" },
405 { "tx_collide_3times" },
406 { "tx_collide_4times" },
407 { "tx_collide_5times" },
408 { "tx_collide_6times" },
409 { "tx_collide_7times" },
410 { "tx_collide_8times" },
411 { "tx_collide_9times" },
412 { "tx_collide_10times" },
413 { "tx_collide_11times" },
414 { "tx_collide_12times" },
415 { "tx_collide_13times" },
416 { "tx_collide_14times" },
417 { "tx_collide_15times" },
418 { "tx_ucast_packets" },
419 { "tx_mcast_packets" },
420 { "tx_bcast_packets" },
421 { "tx_carrier_sense_errors" },
425 { "dma_writeq_full" },
426 { "dma_write_prioq_full" },
430 { "rx_threshold_hit" },
432 { "dma_readq_full" },
433 { "dma_read_prioq_full" },
434 { "tx_comp_queue_full" },
436 { "ring_set_send_prod_index" },
437 { "ring_status_update" },
439 { "nic_avoided_irqs" },
440 { "nic_tx_threshold_hit" },
442 { "mbuf_lwm_thresh_hit" },
445 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
446 #define TG3_NVRAM_TEST 0
447 #define TG3_LINK_TEST 1
448 #define TG3_REGISTER_TEST 2
449 #define TG3_MEMORY_TEST 3
450 #define TG3_MAC_LOOPB_TEST 4
451 #define TG3_PHY_LOOPB_TEST 5
452 #define TG3_EXT_LOOPB_TEST 6
453 #define TG3_INTERRUPT_TEST 7
456 static const struct {
457 const char string
[ETH_GSTRING_LEN
];
458 } ethtool_test_keys
[] = {
459 [TG3_NVRAM_TEST
] = { "nvram test (online) " },
460 [TG3_LINK_TEST
] = { "link test (online) " },
461 [TG3_REGISTER_TEST
] = { "register test (offline)" },
462 [TG3_MEMORY_TEST
] = { "memory test (offline)" },
463 [TG3_MAC_LOOPB_TEST
] = { "mac loopback test (offline)" },
464 [TG3_PHY_LOOPB_TEST
] = { "phy loopback test (offline)" },
465 [TG3_EXT_LOOPB_TEST
] = { "ext loopback test (offline)" },
466 [TG3_INTERRUPT_TEST
] = { "interrupt test (offline)" },
469 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
472 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
474 writel(val
, tp
->regs
+ off
);
477 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
479 return readl(tp
->regs
+ off
);
482 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
484 writel(val
, tp
->aperegs
+ off
);
487 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
489 return readl(tp
->aperegs
+ off
);
492 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
496 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
497 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
498 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
499 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
502 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
504 writel(val
, tp
->regs
+ off
);
505 readl(tp
->regs
+ off
);
508 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
513 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
514 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
515 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
516 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
520 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
524 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
525 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
526 TG3_64BIT_REG_LOW
, val
);
529 if (off
== TG3_RX_STD_PROD_IDX_REG
) {
530 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
531 TG3_64BIT_REG_LOW
, val
);
535 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
536 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
537 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
538 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
540 /* In indirect mode when disabling interrupts, we also need
541 * to clear the interrupt bit in the GRC local ctrl register.
543 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
545 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
546 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
550 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
555 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
556 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
557 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
558 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
562 /* usec_wait specifies the wait time in usec when writing to certain registers
563 * where it is unsafe to read back the register without some delay.
564 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
565 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
567 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
569 if (tg3_flag(tp
, PCIX_TARGET_HWBUG
) || tg3_flag(tp
, ICH_WORKAROUND
))
570 /* Non-posted methods */
571 tp
->write32(tp
, off
, val
);
574 tg3_write32(tp
, off
, val
);
579 /* Wait again after the read for the posted method to guarantee that
580 * the wait time is met.
586 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
588 tp
->write32_mbox(tp
, off
, val
);
589 if (tg3_flag(tp
, FLUSH_POSTED_WRITES
) ||
590 (!tg3_flag(tp
, MBOX_WRITE_REORDER
) &&
591 !tg3_flag(tp
, ICH_WORKAROUND
)))
592 tp
->read32_mbox(tp
, off
);
595 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
597 void __iomem
*mbox
= tp
->regs
+ off
;
599 if (tg3_flag(tp
, TXD_MBOX_HWBUG
))
601 if (tg3_flag(tp
, MBOX_WRITE_REORDER
) ||
602 tg3_flag(tp
, FLUSH_POSTED_WRITES
))
606 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
608 return readl(tp
->regs
+ off
+ GRCMBOX_BASE
);
611 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
613 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
616 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
617 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
618 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
619 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
620 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
622 #define tw32(reg, val) tp->write32(tp, reg, val)
623 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
624 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
625 #define tr32(reg) tp->read32(tp, reg)
627 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
631 if (tg3_asic_rev(tp
) == ASIC_REV_5906
&&
632 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
635 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
636 if (tg3_flag(tp
, SRAM_USE_CONFIG
)) {
637 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
638 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
640 /* Always leave this as zero. */
641 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
643 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
644 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
646 /* Always leave this as zero. */
647 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
649 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
652 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
656 if (tg3_asic_rev(tp
) == ASIC_REV_5906
&&
657 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
662 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
663 if (tg3_flag(tp
, SRAM_USE_CONFIG
)) {
664 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
665 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
667 /* Always leave this as zero. */
668 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
670 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
671 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
673 /* Always leave this as zero. */
674 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
676 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
679 static void tg3_ape_lock_init(struct tg3
*tp
)
684 if (tg3_asic_rev(tp
) == ASIC_REV_5761
)
685 regbase
= TG3_APE_LOCK_GRANT
;
687 regbase
= TG3_APE_PER_LOCK_GRANT
;
689 /* Make sure the driver hasn't any stale locks. */
690 for (i
= TG3_APE_LOCK_PHY0
; i
<= TG3_APE_LOCK_GPIO
; i
++) {
692 case TG3_APE_LOCK_PHY0
:
693 case TG3_APE_LOCK_PHY1
:
694 case TG3_APE_LOCK_PHY2
:
695 case TG3_APE_LOCK_PHY3
:
696 bit
= APE_LOCK_GRANT_DRIVER
;
700 bit
= APE_LOCK_GRANT_DRIVER
;
702 bit
= 1 << tp
->pci_fn
;
704 tg3_ape_write32(tp
, regbase
+ 4 * i
, bit
);
709 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
713 u32 status
, req
, gnt
, bit
;
715 if (!tg3_flag(tp
, ENABLE_APE
))
719 case TG3_APE_LOCK_GPIO
:
720 if (tg3_asic_rev(tp
) == ASIC_REV_5761
)
722 case TG3_APE_LOCK_GRC
:
723 case TG3_APE_LOCK_MEM
:
725 bit
= APE_LOCK_REQ_DRIVER
;
727 bit
= 1 << tp
->pci_fn
;
729 case TG3_APE_LOCK_PHY0
:
730 case TG3_APE_LOCK_PHY1
:
731 case TG3_APE_LOCK_PHY2
:
732 case TG3_APE_LOCK_PHY3
:
733 bit
= APE_LOCK_REQ_DRIVER
;
739 if (tg3_asic_rev(tp
) == ASIC_REV_5761
) {
740 req
= TG3_APE_LOCK_REQ
;
741 gnt
= TG3_APE_LOCK_GRANT
;
743 req
= TG3_APE_PER_LOCK_REQ
;
744 gnt
= TG3_APE_PER_LOCK_GRANT
;
749 tg3_ape_write32(tp
, req
+ off
, bit
);
751 /* Wait for up to 1 millisecond to acquire lock. */
752 for (i
= 0; i
< 100; i
++) {
753 status
= tg3_ape_read32(tp
, gnt
+ off
);
756 if (pci_channel_offline(tp
->pdev
))
763 /* Revoke the lock request. */
764 tg3_ape_write32(tp
, gnt
+ off
, bit
);
771 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
775 if (!tg3_flag(tp
, ENABLE_APE
))
779 case TG3_APE_LOCK_GPIO
:
780 if (tg3_asic_rev(tp
) == ASIC_REV_5761
)
782 case TG3_APE_LOCK_GRC
:
783 case TG3_APE_LOCK_MEM
:
785 bit
= APE_LOCK_GRANT_DRIVER
;
787 bit
= 1 << tp
->pci_fn
;
789 case TG3_APE_LOCK_PHY0
:
790 case TG3_APE_LOCK_PHY1
:
791 case TG3_APE_LOCK_PHY2
:
792 case TG3_APE_LOCK_PHY3
:
793 bit
= APE_LOCK_GRANT_DRIVER
;
799 if (tg3_asic_rev(tp
) == ASIC_REV_5761
)
800 gnt
= TG3_APE_LOCK_GRANT
;
802 gnt
= TG3_APE_PER_LOCK_GRANT
;
804 tg3_ape_write32(tp
, gnt
+ 4 * locknum
, bit
);
807 static int tg3_ape_event_lock(struct tg3
*tp
, u32 timeout_us
)
812 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
815 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
816 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
819 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
822 timeout_us
-= (timeout_us
> 10) ? 10 : timeout_us
;
825 return timeout_us
? 0 : -EBUSY
;
828 #ifdef CONFIG_TIGON3_HWMON
829 static int tg3_ape_wait_for_event(struct tg3
*tp
, u32 timeout_us
)
833 for (i
= 0; i
< timeout_us
/ 10; i
++) {
834 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
836 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
842 return i
== timeout_us
/ 10;
845 static int tg3_ape_scratchpad_read(struct tg3
*tp
, u32
*data
, u32 base_off
,
849 u32 i
, bufoff
, msgoff
, maxlen
, apedata
;
851 if (!tg3_flag(tp
, APE_HAS_NCSI
))
854 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
855 if (apedata
!= APE_SEG_SIG_MAGIC
)
858 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
859 if (!(apedata
& APE_FW_STATUS_READY
))
862 bufoff
= tg3_ape_read32(tp
, TG3_APE_SEG_MSG_BUF_OFF
) +
864 msgoff
= bufoff
+ 2 * sizeof(u32
);
865 maxlen
= tg3_ape_read32(tp
, TG3_APE_SEG_MSG_BUF_LEN
);
870 /* Cap xfer sizes to scratchpad limits. */
871 length
= (len
> maxlen
) ? maxlen
: len
;
874 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
875 if (!(apedata
& APE_FW_STATUS_READY
))
878 /* Wait for up to 1 msec for APE to service previous event. */
879 err
= tg3_ape_event_lock(tp
, 1000);
883 apedata
= APE_EVENT_STATUS_DRIVER_EVNT
|
884 APE_EVENT_STATUS_SCRTCHPD_READ
|
885 APE_EVENT_STATUS_EVENT_PENDING
;
886 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
, apedata
);
888 tg3_ape_write32(tp
, bufoff
, base_off
);
889 tg3_ape_write32(tp
, bufoff
+ sizeof(u32
), length
);
891 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
892 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
896 if (tg3_ape_wait_for_event(tp
, 30000))
899 for (i
= 0; length
; i
+= 4, length
-= 4) {
900 u32 val
= tg3_ape_read32(tp
, msgoff
+ i
);
901 memcpy(data
, &val
, sizeof(u32
));
910 static int tg3_ape_send_event(struct tg3
*tp
, u32 event
)
915 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
916 if (apedata
!= APE_SEG_SIG_MAGIC
)
919 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
920 if (!(apedata
& APE_FW_STATUS_READY
))
923 /* Wait for up to 1 millisecond for APE to service previous event. */
924 err
= tg3_ape_event_lock(tp
, 1000);
928 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
929 event
| APE_EVENT_STATUS_EVENT_PENDING
);
931 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
932 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
937 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
942 if (!tg3_flag(tp
, ENABLE_APE
))
946 case RESET_KIND_INIT
:
947 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
948 APE_HOST_SEG_SIG_MAGIC
);
949 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
950 APE_HOST_SEG_LEN_MAGIC
);
951 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
952 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
953 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
954 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM
, TG3_MIN_NUM
));
955 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
956 APE_HOST_BEHAV_NO_PHYLOCK
);
957 tg3_ape_write32(tp
, TG3_APE_HOST_DRVR_STATE
,
958 TG3_APE_HOST_DRVR_STATE_START
);
960 event
= APE_EVENT_STATUS_STATE_START
;
962 case RESET_KIND_SHUTDOWN
:
963 /* With the interface we are currently using,
964 * APE does not track driver state. Wiping
965 * out the HOST SEGMENT SIGNATURE forces
966 * the APE to assume OS absent status.
968 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
970 if (device_may_wakeup(&tp
->pdev
->dev
) &&
971 tg3_flag(tp
, WOL_ENABLE
)) {
972 tg3_ape_write32(tp
, TG3_APE_HOST_WOL_SPEED
,
973 TG3_APE_HOST_WOL_SPEED_AUTO
);
974 apedata
= TG3_APE_HOST_DRVR_STATE_WOL
;
976 apedata
= TG3_APE_HOST_DRVR_STATE_UNLOAD
;
978 tg3_ape_write32(tp
, TG3_APE_HOST_DRVR_STATE
, apedata
);
980 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
986 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
988 tg3_ape_send_event(tp
, event
);
991 static void tg3_disable_ints(struct tg3
*tp
)
995 tw32(TG3PCI_MISC_HOST_CTRL
,
996 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
997 for (i
= 0; i
< tp
->irq_max
; i
++)
998 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 0x00000001);
1001 static void tg3_enable_ints(struct tg3
*tp
)
1008 tw32(TG3PCI_MISC_HOST_CTRL
,
1009 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
1011 tp
->coal_now
= tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
;
1012 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
1013 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
1015 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
1016 if (tg3_flag(tp
, 1SHOT_MSI
))
1017 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
1019 tp
->coal_now
|= tnapi
->coal_now
;
1022 /* Force an initial interrupt */
1023 if (!tg3_flag(tp
, TAGGED_STATUS
) &&
1024 (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
))
1025 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
1027 tw32(HOSTCC_MODE
, tp
->coal_now
);
1029 tp
->coal_now
&= ~(tp
->napi
[0].coal_now
| tp
->napi
[1].coal_now
);
1032 static inline unsigned int tg3_has_work(struct tg3_napi
*tnapi
)
1034 struct tg3
*tp
= tnapi
->tp
;
1035 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
1036 unsigned int work_exists
= 0;
1038 /* check for phy events */
1039 if (!(tg3_flag(tp
, USE_LINKCHG_REG
) || tg3_flag(tp
, POLL_SERDES
))) {
1040 if (sblk
->status
& SD_STATUS_LINK_CHG
)
1044 /* check for TX work to do */
1045 if (sblk
->idx
[0].tx_consumer
!= tnapi
->tx_cons
)
1048 /* check for RX work to do */
1049 if (tnapi
->rx_rcb_prod_idx
&&
1050 *(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
1057 * similar to tg3_enable_ints, but it accurately determines whether there
1058 * is new work pending and can return without flushing the PIO write
1059 * which reenables interrupts
1061 static void tg3_int_reenable(struct tg3_napi
*tnapi
)
1063 struct tg3
*tp
= tnapi
->tp
;
1065 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
1068 /* When doing tagged status, this work check is unnecessary.
1069 * The last_tag we write above tells the chip which piece of
1070 * work we've completed.
1072 if (!tg3_flag(tp
, TAGGED_STATUS
) && tg3_has_work(tnapi
))
1073 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
1074 HOSTCC_MODE_ENABLE
| tnapi
->coal_now
);
1077 static void tg3_switch_clocks(struct tg3
*tp
)
1080 u32 orig_clock_ctrl
;
1082 if (tg3_flag(tp
, CPMU_PRESENT
) || tg3_flag(tp
, 5780_CLASS
))
1085 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
1087 orig_clock_ctrl
= clock_ctrl
;
1088 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
1089 CLOCK_CTRL_CLKRUN_OENABLE
|
1091 tp
->pci_clock_ctrl
= clock_ctrl
;
1093 if (tg3_flag(tp
, 5705_PLUS
)) {
1094 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
1095 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
1096 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
1098 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
1099 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
1101 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
1103 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
1104 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
1107 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
1110 #define PHY_BUSY_LOOPS 5000
1112 static int __tg3_readphy(struct tg3
*tp
, unsigned int phy_addr
, int reg
,
1119 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
1121 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
1125 tg3_ape_lock(tp
, tp
->phy_ape_lock
);
1129 frame_val
= ((phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
1130 MI_COM_PHY_ADDR_MASK
);
1131 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
1132 MI_COM_REG_ADDR_MASK
);
1133 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
1135 tw32_f(MAC_MI_COM
, frame_val
);
1137 loops
= PHY_BUSY_LOOPS
;
1138 while (loops
!= 0) {
1140 frame_val
= tr32(MAC_MI_COM
);
1142 if ((frame_val
& MI_COM_BUSY
) == 0) {
1144 frame_val
= tr32(MAC_MI_COM
);
1152 *val
= frame_val
& MI_COM_DATA_MASK
;
1156 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
1157 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1161 tg3_ape_unlock(tp
, tp
->phy_ape_lock
);
1166 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
1168 return __tg3_readphy(tp
, tp
->phy_addr
, reg
, val
);
1171 static int __tg3_writephy(struct tg3
*tp
, unsigned int phy_addr
, int reg
,
1178 if ((tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
1179 (reg
== MII_CTRL1000
|| reg
== MII_TG3_AUX_CTRL
))
1182 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
1184 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
1188 tg3_ape_lock(tp
, tp
->phy_ape_lock
);
1190 frame_val
= ((phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
1191 MI_COM_PHY_ADDR_MASK
);
1192 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
1193 MI_COM_REG_ADDR_MASK
);
1194 frame_val
|= (val
& MI_COM_DATA_MASK
);
1195 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
1197 tw32_f(MAC_MI_COM
, frame_val
);
1199 loops
= PHY_BUSY_LOOPS
;
1200 while (loops
!= 0) {
1202 frame_val
= tr32(MAC_MI_COM
);
1203 if ((frame_val
& MI_COM_BUSY
) == 0) {
1205 frame_val
= tr32(MAC_MI_COM
);
1215 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
1216 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1220 tg3_ape_unlock(tp
, tp
->phy_ape_lock
);
1225 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
1227 return __tg3_writephy(tp
, tp
->phy_addr
, reg
, val
);
1230 static int tg3_phy_cl45_write(struct tg3
*tp
, u32 devad
, u32 addr
, u32 val
)
1234 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
, devad
);
1238 err
= tg3_writephy(tp
, MII_TG3_MMD_ADDRESS
, addr
);
1242 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
,
1243 MII_TG3_MMD_CTRL_DATA_NOINC
| devad
);
1247 err
= tg3_writephy(tp
, MII_TG3_MMD_ADDRESS
, val
);
1253 static int tg3_phy_cl45_read(struct tg3
*tp
, u32 devad
, u32 addr
, u32
*val
)
1257 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
, devad
);
1261 err
= tg3_writephy(tp
, MII_TG3_MMD_ADDRESS
, addr
);
1265 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
,
1266 MII_TG3_MMD_CTRL_DATA_NOINC
| devad
);
1270 err
= tg3_readphy(tp
, MII_TG3_MMD_ADDRESS
, val
);
1276 static int tg3_phydsp_read(struct tg3
*tp
, u32 reg
, u32
*val
)
1280 err
= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1282 err
= tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1287 static int tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
1291 err
= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1293 err
= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1298 static int tg3_phy_auxctl_read(struct tg3
*tp
, int reg
, u32
*val
)
1302 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
1303 (reg
<< MII_TG3_AUXCTL_MISC_RDSEL_SHIFT
) |
1304 MII_TG3_AUXCTL_SHDWSEL_MISC
);
1306 err
= tg3_readphy(tp
, MII_TG3_AUX_CTRL
, val
);
1311 static int tg3_phy_auxctl_write(struct tg3
*tp
, int reg
, u32 set
)
1313 if (reg
== MII_TG3_AUXCTL_SHDWSEL_MISC
)
1314 set
|= MII_TG3_AUXCTL_MISC_WREN
;
1316 return tg3_writephy(tp
, MII_TG3_AUX_CTRL
, set
| reg
);
1319 static int tg3_phy_toggle_auxctl_smdsp(struct tg3
*tp
, bool enable
)
1324 err
= tg3_phy_auxctl_read(tp
, MII_TG3_AUXCTL_SHDWSEL_AUXCTL
, &val
);
1330 val
|= MII_TG3_AUXCTL_ACTL_SMDSP_ENA
;
1332 val
&= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA
;
1334 err
= tg3_phy_auxctl_write((tp
), MII_TG3_AUXCTL_SHDWSEL_AUXCTL
,
1335 val
| MII_TG3_AUXCTL_ACTL_TX_6DB
);
1340 static int tg3_phy_shdw_write(struct tg3
*tp
, int reg
, u32 val
)
1342 return tg3_writephy(tp
, MII_TG3_MISC_SHDW
,
1343 reg
| val
| MII_TG3_MISC_SHDW_WREN
);
1346 static int tg3_bmcr_reset(struct tg3
*tp
)
1351 /* OK, reset it, and poll the BMCR_RESET bit until it
1352 * clears or we time out.
1354 phy_control
= BMCR_RESET
;
1355 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
1361 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
1365 if ((phy_control
& BMCR_RESET
) == 0) {
1377 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
1379 struct tg3
*tp
= bp
->priv
;
1382 spin_lock_bh(&tp
->lock
);
1384 if (__tg3_readphy(tp
, mii_id
, reg
, &val
))
1387 spin_unlock_bh(&tp
->lock
);
1392 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
1394 struct tg3
*tp
= bp
->priv
;
1397 spin_lock_bh(&tp
->lock
);
1399 if (__tg3_writephy(tp
, mii_id
, reg
, val
))
1402 spin_unlock_bh(&tp
->lock
);
1407 static void tg3_mdio_config_5785(struct tg3
*tp
)
1410 struct phy_device
*phydev
;
1412 phydev
= mdiobus_get_phy(tp
->mdio_bus
, tp
->phy_addr
);
1413 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1414 case PHY_ID_BCM50610
:
1415 case PHY_ID_BCM50610M
:
1416 val
= MAC_PHYCFG2_50610_LED_MODES
;
1418 case PHY_ID_BCMAC131
:
1419 val
= MAC_PHYCFG2_AC131_LED_MODES
;
1421 case PHY_ID_RTL8211C
:
1422 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
1424 case PHY_ID_RTL8201E
:
1425 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
1431 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
1432 tw32(MAC_PHYCFG2
, val
);
1434 val
= tr32(MAC_PHYCFG1
);
1435 val
&= ~(MAC_PHYCFG1_RGMII_INT
|
1436 MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
);
1437 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
;
1438 tw32(MAC_PHYCFG1
, val
);
1443 if (!tg3_flag(tp
, RGMII_INBAND_DISABLE
))
1444 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
1445 MAC_PHYCFG2_FMODE_MASK_MASK
|
1446 MAC_PHYCFG2_GMODE_MASK_MASK
|
1447 MAC_PHYCFG2_ACT_MASK_MASK
|
1448 MAC_PHYCFG2_QUAL_MASK_MASK
|
1449 MAC_PHYCFG2_INBAND_ENABLE
;
1451 tw32(MAC_PHYCFG2
, val
);
1453 val
= tr32(MAC_PHYCFG1
);
1454 val
&= ~(MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
|
1455 MAC_PHYCFG1_RGMII_EXT_RX_DEC
| MAC_PHYCFG1_RGMII_SND_STAT_EN
);
1456 if (!tg3_flag(tp
, RGMII_INBAND_DISABLE
)) {
1457 if (tg3_flag(tp
, RGMII_EXT_IBND_RX_EN
))
1458 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
1459 if (tg3_flag(tp
, RGMII_EXT_IBND_TX_EN
))
1460 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
1462 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
|
1463 MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
;
1464 tw32(MAC_PHYCFG1
, val
);
1466 val
= tr32(MAC_EXT_RGMII_MODE
);
1467 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
1468 MAC_RGMII_MODE_RX_QUALITY
|
1469 MAC_RGMII_MODE_RX_ACTIVITY
|
1470 MAC_RGMII_MODE_RX_ENG_DET
|
1471 MAC_RGMII_MODE_TX_ENABLE
|
1472 MAC_RGMII_MODE_TX_LOWPWR
|
1473 MAC_RGMII_MODE_TX_RESET
);
1474 if (!tg3_flag(tp
, RGMII_INBAND_DISABLE
)) {
1475 if (tg3_flag(tp
, RGMII_EXT_IBND_RX_EN
))
1476 val
|= MAC_RGMII_MODE_RX_INT_B
|
1477 MAC_RGMII_MODE_RX_QUALITY
|
1478 MAC_RGMII_MODE_RX_ACTIVITY
|
1479 MAC_RGMII_MODE_RX_ENG_DET
;
1480 if (tg3_flag(tp
, RGMII_EXT_IBND_TX_EN
))
1481 val
|= MAC_RGMII_MODE_TX_ENABLE
|
1482 MAC_RGMII_MODE_TX_LOWPWR
|
1483 MAC_RGMII_MODE_TX_RESET
;
1485 tw32(MAC_EXT_RGMII_MODE
, val
);
1488 static void tg3_mdio_start(struct tg3
*tp
)
1490 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
1491 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1494 if (tg3_flag(tp
, MDIOBUS_INITED
) &&
1495 tg3_asic_rev(tp
) == ASIC_REV_5785
)
1496 tg3_mdio_config_5785(tp
);
1499 static int tg3_mdio_init(struct tg3
*tp
)
1503 struct phy_device
*phydev
;
1505 if (tg3_flag(tp
, 5717_PLUS
)) {
1508 tp
->phy_addr
= tp
->pci_fn
+ 1;
1510 if (tg3_chip_rev_id(tp
) != CHIPREV_ID_5717_A0
)
1511 is_serdes
= tr32(SG_DIG_STATUS
) & SG_DIG_IS_SERDES
;
1513 is_serdes
= tr32(TG3_CPMU_PHY_STRAP
) &
1514 TG3_CPMU_PHY_STRAP_IS_SERDES
;
1517 } else if (tg3_flag(tp
, IS_SSB_CORE
) && tg3_flag(tp
, ROBOSWITCH
)) {
1520 addr
= ssb_gige_get_phyaddr(tp
->pdev
);
1523 tp
->phy_addr
= addr
;
1525 tp
->phy_addr
= TG3_PHY_MII_ADDR
;
1529 if (!tg3_flag(tp
, USE_PHYLIB
) || tg3_flag(tp
, MDIOBUS_INITED
))
1532 tp
->mdio_bus
= mdiobus_alloc();
1533 if (tp
->mdio_bus
== NULL
)
1536 tp
->mdio_bus
->name
= "tg3 mdio bus";
1537 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1538 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1539 tp
->mdio_bus
->priv
= tp
;
1540 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1541 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1542 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1543 tp
->mdio_bus
->phy_mask
= ~(1 << tp
->phy_addr
);
1545 /* The bus registration will look for all the PHYs on the mdio bus.
1546 * Unfortunately, it does not ensure the PHY is powered up before
1547 * accessing the PHY ID registers. A chip reset is the
1548 * quickest way to bring the device back to an operational state..
1550 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1553 i
= mdiobus_register(tp
->mdio_bus
);
1555 dev_warn(&tp
->pdev
->dev
, "mdiobus_reg failed (0x%x)\n", i
);
1556 mdiobus_free(tp
->mdio_bus
);
1560 phydev
= mdiobus_get_phy(tp
->mdio_bus
, tp
->phy_addr
);
1562 if (!phydev
|| !phydev
->drv
) {
1563 dev_warn(&tp
->pdev
->dev
, "No PHY devices\n");
1564 mdiobus_unregister(tp
->mdio_bus
);
1565 mdiobus_free(tp
->mdio_bus
);
1569 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1570 case PHY_ID_BCM57780
:
1571 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1572 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1574 case PHY_ID_BCM50610
:
1575 case PHY_ID_BCM50610M
:
1576 phydev
->dev_flags
|= PHY_BRCM_CLEAR_RGMII_MODE
|
1577 PHY_BRCM_RX_REFCLK_UNUSED
|
1578 PHY_BRCM_DIS_TXCRXC_NOENRGY
|
1579 PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1580 if (tg3_flag(tp
, RGMII_INBAND_DISABLE
))
1581 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1582 if (tg3_flag(tp
, RGMII_EXT_IBND_RX_EN
))
1583 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1584 if (tg3_flag(tp
, RGMII_EXT_IBND_TX_EN
))
1585 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1587 case PHY_ID_RTL8211C
:
1588 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1590 case PHY_ID_RTL8201E
:
1591 case PHY_ID_BCMAC131
:
1592 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1593 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1594 tp
->phy_flags
|= TG3_PHYFLG_IS_FET
;
1598 tg3_flag_set(tp
, MDIOBUS_INITED
);
1600 if (tg3_asic_rev(tp
) == ASIC_REV_5785
)
1601 tg3_mdio_config_5785(tp
);
1606 static void tg3_mdio_fini(struct tg3
*tp
)
1608 if (tg3_flag(tp
, MDIOBUS_INITED
)) {
1609 tg3_flag_clear(tp
, MDIOBUS_INITED
);
1610 mdiobus_unregister(tp
->mdio_bus
);
1611 mdiobus_free(tp
->mdio_bus
);
1615 /* tp->lock is held. */
1616 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1620 val
= tr32(GRC_RX_CPU_EVENT
);
1621 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1622 tw32_f(GRC_RX_CPU_EVENT
, val
);
1624 tp
->last_event_jiffies
= jiffies
;
1627 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1629 /* tp->lock is held. */
1630 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1633 unsigned int delay_cnt
;
1636 /* If enough time has passed, no wait is necessary. */
1637 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1638 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1640 if (time_remain
< 0)
1643 /* Check if we can shorten the wait time. */
1644 delay_cnt
= jiffies_to_usecs(time_remain
);
1645 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1646 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1647 delay_cnt
= (delay_cnt
>> 3) + 1;
1649 for (i
= 0; i
< delay_cnt
; i
++) {
1650 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1652 if (pci_channel_offline(tp
->pdev
))
1659 /* tp->lock is held. */
1660 static void tg3_phy_gather_ump_data(struct tg3
*tp
, u32
*data
)
1665 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1667 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1668 val
|= (reg
& 0xffff);
1672 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1674 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1675 val
|= (reg
& 0xffff);
1679 if (!(tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)) {
1680 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1682 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1683 val
|= (reg
& 0xffff);
1687 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1694 /* tp->lock is held. */
1695 static void tg3_ump_link_report(struct tg3
*tp
)
1699 if (!tg3_flag(tp
, 5780_CLASS
) || !tg3_flag(tp
, ENABLE_ASF
))
1702 tg3_phy_gather_ump_data(tp
, data
);
1704 tg3_wait_for_event_ack(tp
);
1706 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1707 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1708 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 0x0, data
[0]);
1709 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 0x4, data
[1]);
1710 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 0x8, data
[2]);
1711 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 0xc, data
[3]);
1713 tg3_generate_fw_event(tp
);
1716 /* tp->lock is held. */
1717 static void tg3_stop_fw(struct tg3
*tp
)
1719 if (tg3_flag(tp
, ENABLE_ASF
) && !tg3_flag(tp
, ENABLE_APE
)) {
1720 /* Wait for RX cpu to ACK the previous event. */
1721 tg3_wait_for_event_ack(tp
);
1723 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
1725 tg3_generate_fw_event(tp
);
1727 /* Wait for RX cpu to ACK this event. */
1728 tg3_wait_for_event_ack(tp
);
1732 /* tp->lock is held. */
1733 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
1735 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
1736 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
1738 if (tg3_flag(tp
, ASF_NEW_HANDSHAKE
)) {
1740 case RESET_KIND_INIT
:
1741 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1745 case RESET_KIND_SHUTDOWN
:
1746 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1750 case RESET_KIND_SUSPEND
:
1751 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1761 /* tp->lock is held. */
1762 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
1764 if (tg3_flag(tp
, ASF_NEW_HANDSHAKE
)) {
1766 case RESET_KIND_INIT
:
1767 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1768 DRV_STATE_START_DONE
);
1771 case RESET_KIND_SHUTDOWN
:
1772 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1773 DRV_STATE_UNLOAD_DONE
);
1782 /* tp->lock is held. */
1783 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
1785 if (tg3_flag(tp
, ENABLE_ASF
)) {
1787 case RESET_KIND_INIT
:
1788 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1792 case RESET_KIND_SHUTDOWN
:
1793 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1797 case RESET_KIND_SUSPEND
:
1798 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1808 static int tg3_poll_fw(struct tg3
*tp
)
1813 if (tg3_flag(tp
, NO_FWARE_REPORTED
))
1816 if (tg3_flag(tp
, IS_SSB_CORE
)) {
1817 /* We don't use firmware. */
1821 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
1822 /* Wait up to 20ms for init done. */
1823 for (i
= 0; i
< 200; i
++) {
1824 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
1826 if (pci_channel_offline(tp
->pdev
))
1834 /* Wait for firmware initialization to complete. */
1835 for (i
= 0; i
< 100000; i
++) {
1836 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
1837 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
1839 if (pci_channel_offline(tp
->pdev
)) {
1840 if (!tg3_flag(tp
, NO_FWARE_REPORTED
)) {
1841 tg3_flag_set(tp
, NO_FWARE_REPORTED
);
1842 netdev_info(tp
->dev
, "No firmware running\n");
1851 /* Chip might not be fitted with firmware. Some Sun onboard
1852 * parts are configured like that. So don't signal the timeout
1853 * of the above loop as an error, but do report the lack of
1854 * running firmware once.
1856 if (i
>= 100000 && !tg3_flag(tp
, NO_FWARE_REPORTED
)) {
1857 tg3_flag_set(tp
, NO_FWARE_REPORTED
);
1859 netdev_info(tp
->dev
, "No firmware running\n");
1862 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_57765_A0
) {
1863 /* The 57765 A0 needs a little more
1864 * time to do some important work.
1872 static void tg3_link_report(struct tg3
*tp
)
1874 if (!netif_carrier_ok(tp
->dev
)) {
1875 netif_info(tp
, link
, tp
->dev
, "Link is down\n");
1876 tg3_ump_link_report(tp
);
1877 } else if (netif_msg_link(tp
)) {
1878 netdev_info(tp
->dev
, "Link is up at %d Mbps, %s duplex\n",
1879 (tp
->link_config
.active_speed
== SPEED_1000
?
1881 (tp
->link_config
.active_speed
== SPEED_100
?
1883 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1886 netdev_info(tp
->dev
, "Flow control is %s for TX and %s for RX\n",
1887 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1889 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1892 if (tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
)
1893 netdev_info(tp
->dev
, "EEE is %s\n",
1894 tp
->setlpicnt
? "enabled" : "disabled");
1896 tg3_ump_link_report(tp
);
1899 tp
->link_up
= netif_carrier_ok(tp
->dev
);
1902 static u32
tg3_decode_flowctrl_1000T(u32 adv
)
1906 if (adv
& ADVERTISE_PAUSE_CAP
) {
1907 flowctrl
|= FLOW_CTRL_RX
;
1908 if (!(adv
& ADVERTISE_PAUSE_ASYM
))
1909 flowctrl
|= FLOW_CTRL_TX
;
1910 } else if (adv
& ADVERTISE_PAUSE_ASYM
)
1911 flowctrl
|= FLOW_CTRL_TX
;
1916 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1920 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1921 miireg
= ADVERTISE_1000XPAUSE
;
1922 else if (flow_ctrl
& FLOW_CTRL_TX
)
1923 miireg
= ADVERTISE_1000XPSE_ASYM
;
1924 else if (flow_ctrl
& FLOW_CTRL_RX
)
1925 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1932 static u32
tg3_decode_flowctrl_1000X(u32 adv
)
1936 if (adv
& ADVERTISE_1000XPAUSE
) {
1937 flowctrl
|= FLOW_CTRL_RX
;
1938 if (!(adv
& ADVERTISE_1000XPSE_ASYM
))
1939 flowctrl
|= FLOW_CTRL_TX
;
1940 } else if (adv
& ADVERTISE_1000XPSE_ASYM
)
1941 flowctrl
|= FLOW_CTRL_TX
;
1946 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1950 if (lcladv
& rmtadv
& ADVERTISE_1000XPAUSE
) {
1951 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1952 } else if (lcladv
& rmtadv
& ADVERTISE_1000XPSE_ASYM
) {
1953 if (lcladv
& ADVERTISE_1000XPAUSE
)
1955 if (rmtadv
& ADVERTISE_1000XPAUSE
)
1962 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1966 u32 old_rx_mode
= tp
->rx_mode
;
1967 u32 old_tx_mode
= tp
->tx_mode
;
1969 if (tg3_flag(tp
, USE_PHYLIB
))
1970 autoneg
= mdiobus_get_phy(tp
->mdio_bus
, tp
->phy_addr
)->autoneg
;
1972 autoneg
= tp
->link_config
.autoneg
;
1974 if (autoneg
== AUTONEG_ENABLE
&& tg3_flag(tp
, PAUSE_AUTONEG
)) {
1975 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
1976 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1978 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1980 flowctrl
= tp
->link_config
.flowctrl
;
1982 tp
->link_config
.active_flowctrl
= flowctrl
;
1984 if (flowctrl
& FLOW_CTRL_RX
)
1985 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1987 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1989 if (old_rx_mode
!= tp
->rx_mode
)
1990 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1992 if (flowctrl
& FLOW_CTRL_TX
)
1993 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1995 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1997 if (old_tx_mode
!= tp
->tx_mode
)
1998 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
2001 static void tg3_adjust_link(struct net_device
*dev
)
2003 u8 oldflowctrl
, linkmesg
= 0;
2004 u32 mac_mode
, lcl_adv
, rmt_adv
;
2005 struct tg3
*tp
= netdev_priv(dev
);
2006 struct phy_device
*phydev
= mdiobus_get_phy(tp
->mdio_bus
, tp
->phy_addr
);
2008 spin_lock_bh(&tp
->lock
);
2010 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
2011 MAC_MODE_HALF_DUPLEX
);
2013 oldflowctrl
= tp
->link_config
.active_flowctrl
;
2019 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
2020 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
2021 else if (phydev
->speed
== SPEED_1000
||
2022 tg3_asic_rev(tp
) != ASIC_REV_5785
)
2023 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
2025 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
2027 if (phydev
->duplex
== DUPLEX_HALF
)
2028 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
2030 lcl_adv
= mii_advertise_flowctrl(
2031 tp
->link_config
.flowctrl
);
2034 rmt_adv
= LPA_PAUSE_CAP
;
2035 if (phydev
->asym_pause
)
2036 rmt_adv
|= LPA_PAUSE_ASYM
;
2039 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
2041 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
2043 if (mac_mode
!= tp
->mac_mode
) {
2044 tp
->mac_mode
= mac_mode
;
2045 tw32_f(MAC_MODE
, tp
->mac_mode
);
2049 if (tg3_asic_rev(tp
) == ASIC_REV_5785
) {
2050 if (phydev
->speed
== SPEED_10
)
2052 MAC_MI_STAT_10MBPS_MODE
|
2053 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
2055 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
2058 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
2059 tw32(MAC_TX_LENGTHS
,
2060 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
2061 (6 << TX_LENGTHS_IPG_SHIFT
) |
2062 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
2064 tw32(MAC_TX_LENGTHS
,
2065 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
2066 (6 << TX_LENGTHS_IPG_SHIFT
) |
2067 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
2069 if (phydev
->link
!= tp
->old_link
||
2070 phydev
->speed
!= tp
->link_config
.active_speed
||
2071 phydev
->duplex
!= tp
->link_config
.active_duplex
||
2072 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
2075 tp
->old_link
= phydev
->link
;
2076 tp
->link_config
.active_speed
= phydev
->speed
;
2077 tp
->link_config
.active_duplex
= phydev
->duplex
;
2079 spin_unlock_bh(&tp
->lock
);
2082 tg3_link_report(tp
);
2085 static int tg3_phy_init(struct tg3
*tp
)
2087 struct phy_device
*phydev
;
2089 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
)
2092 /* Bring the PHY back to a known state. */
2095 phydev
= mdiobus_get_phy(tp
->mdio_bus
, tp
->phy_addr
);
2097 /* Attach the MAC to the PHY. */
2098 phydev
= phy_connect(tp
->dev
, phydev_name(phydev
),
2099 tg3_adjust_link
, phydev
->interface
);
2100 if (IS_ERR(phydev
)) {
2101 dev_err(&tp
->pdev
->dev
, "Could not attach to PHY\n");
2102 return PTR_ERR(phydev
);
2105 /* Mask with MAC supported features. */
2106 switch (phydev
->interface
) {
2107 case PHY_INTERFACE_MODE_GMII
:
2108 case PHY_INTERFACE_MODE_RGMII
:
2109 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
2110 phydev
->supported
&= (PHY_GBIT_FEATURES
|
2112 SUPPORTED_Asym_Pause
);
2116 case PHY_INTERFACE_MODE_MII
:
2117 phydev
->supported
&= (PHY_BASIC_FEATURES
|
2119 SUPPORTED_Asym_Pause
);
2122 phy_disconnect(mdiobus_get_phy(tp
->mdio_bus
, tp
->phy_addr
));
2126 tp
->phy_flags
|= TG3_PHYFLG_IS_CONNECTED
;
2128 phydev
->advertising
= phydev
->supported
;
2130 phy_attached_info(phydev
);
2135 static void tg3_phy_start(struct tg3
*tp
)
2137 struct phy_device
*phydev
;
2139 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
2142 phydev
= mdiobus_get_phy(tp
->mdio_bus
, tp
->phy_addr
);
2144 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
2145 tp
->phy_flags
&= ~TG3_PHYFLG_IS_LOW_POWER
;
2146 phydev
->speed
= tp
->link_config
.speed
;
2147 phydev
->duplex
= tp
->link_config
.duplex
;
2148 phydev
->autoneg
= tp
->link_config
.autoneg
;
2149 phydev
->advertising
= tp
->link_config
.advertising
;
2154 phy_start_aneg(phydev
);
2157 static void tg3_phy_stop(struct tg3
*tp
)
2159 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
2162 phy_stop(mdiobus_get_phy(tp
->mdio_bus
, tp
->phy_addr
));
2165 static void tg3_phy_fini(struct tg3
*tp
)
2167 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
2168 phy_disconnect(mdiobus_get_phy(tp
->mdio_bus
, tp
->phy_addr
));
2169 tp
->phy_flags
&= ~TG3_PHYFLG_IS_CONNECTED
;
2173 static int tg3_phy_set_extloopbk(struct tg3
*tp
)
2178 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
)
2181 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
2182 /* Cannot do read-modify-write on 5401 */
2183 err
= tg3_phy_auxctl_write(tp
,
2184 MII_TG3_AUXCTL_SHDWSEL_AUXCTL
,
2185 MII_TG3_AUXCTL_ACTL_EXTLOOPBK
|
2190 err
= tg3_phy_auxctl_read(tp
,
2191 MII_TG3_AUXCTL_SHDWSEL_AUXCTL
, &val
);
2195 val
|= MII_TG3_AUXCTL_ACTL_EXTLOOPBK
;
2196 err
= tg3_phy_auxctl_write(tp
,
2197 MII_TG3_AUXCTL_SHDWSEL_AUXCTL
, val
);
2203 static void tg3_phy_fet_toggle_apd(struct tg3
*tp
, bool enable
)
2207 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
2210 tg3_writephy(tp
, MII_TG3_FET_TEST
,
2211 phytest
| MII_TG3_FET_SHADOW_EN
);
2212 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, &phy
)) {
2214 phy
|= MII_TG3_FET_SHDW_AUXSTAT2_APD
;
2216 phy
&= ~MII_TG3_FET_SHDW_AUXSTAT2_APD
;
2217 tg3_writephy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, phy
);
2219 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
2223 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
2227 if (!tg3_flag(tp
, 5705_PLUS
) ||
2228 (tg3_flag(tp
, 5717_PLUS
) &&
2229 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)))
2232 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
2233 tg3_phy_fet_toggle_apd(tp
, enable
);
2237 reg
= MII_TG3_MISC_SHDW_SCR5_LPED
|
2238 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
2239 MII_TG3_MISC_SHDW_SCR5_SDTL
|
2240 MII_TG3_MISC_SHDW_SCR5_C125OE
;
2241 if (tg3_asic_rev(tp
) != ASIC_REV_5784
|| !enable
)
2242 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
2244 tg3_phy_shdw_write(tp
, MII_TG3_MISC_SHDW_SCR5_SEL
, reg
);
2247 reg
= MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
2249 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
2251 tg3_phy_shdw_write(tp
, MII_TG3_MISC_SHDW_APD_SEL
, reg
);
2254 static void tg3_phy_toggle_automdix(struct tg3
*tp
, bool enable
)
2258 if (!tg3_flag(tp
, 5705_PLUS
) ||
2259 (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
2262 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
2265 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &ephy
)) {
2266 u32 reg
= MII_TG3_FET_SHDW_MISCCTRL
;
2268 tg3_writephy(tp
, MII_TG3_FET_TEST
,
2269 ephy
| MII_TG3_FET_SHADOW_EN
);
2270 if (!tg3_readphy(tp
, reg
, &phy
)) {
2272 phy
|= MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
2274 phy
&= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
2275 tg3_writephy(tp
, reg
, phy
);
2277 tg3_writephy(tp
, MII_TG3_FET_TEST
, ephy
);
2282 ret
= tg3_phy_auxctl_read(tp
,
2283 MII_TG3_AUXCTL_SHDWSEL_MISC
, &phy
);
2286 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
2288 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
2289 tg3_phy_auxctl_write(tp
,
2290 MII_TG3_AUXCTL_SHDWSEL_MISC
, phy
);
2295 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
2300 if (tp
->phy_flags
& TG3_PHYFLG_NO_ETH_WIRE_SPEED
)
2303 ret
= tg3_phy_auxctl_read(tp
, MII_TG3_AUXCTL_SHDWSEL_MISC
, &val
);
2305 tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_MISC
,
2306 val
| MII_TG3_AUXCTL_MISC_WIRESPD_EN
);
2309 static void tg3_phy_apply_otp(struct tg3
*tp
)
2318 if (tg3_phy_toggle_auxctl_smdsp(tp
, true))
2321 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
2322 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
2323 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
2325 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
2326 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
2327 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
2329 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
2330 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
2331 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
2333 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
2334 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
2336 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
2337 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
2339 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
2340 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
2341 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
2343 tg3_phy_toggle_auxctl_smdsp(tp
, false);
2346 static void tg3_eee_pull_config(struct tg3
*tp
, struct ethtool_eee
*eee
)
2349 struct ethtool_eee
*dest
= &tp
->eee
;
2351 if (!(tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
))
2357 if (tg3_phy_cl45_read(tp
, MDIO_MMD_AN
, TG3_CL45_D7_EEERES_STAT
, &val
))
2360 /* Pull eee_active */
2361 if (val
== TG3_CL45_D7_EEERES_STAT_LP_1000T
||
2362 val
== TG3_CL45_D7_EEERES_STAT_LP_100TX
) {
2363 dest
->eee_active
= 1;
2365 dest
->eee_active
= 0;
2367 /* Pull lp advertised settings */
2368 if (tg3_phy_cl45_read(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_LPABLE
, &val
))
2370 dest
->lp_advertised
= mmd_eee_adv_to_ethtool_adv_t(val
);
2372 /* Pull advertised and eee_enabled settings */
2373 if (tg3_phy_cl45_read(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
, &val
))
2375 dest
->eee_enabled
= !!val
;
2376 dest
->advertised
= mmd_eee_adv_to_ethtool_adv_t(val
);
2378 /* Pull tx_lpi_enabled */
2379 val
= tr32(TG3_CPMU_EEE_MODE
);
2380 dest
->tx_lpi_enabled
= !!(val
& TG3_CPMU_EEEMD_LPI_IN_TX
);
2382 /* Pull lpi timer value */
2383 dest
->tx_lpi_timer
= tr32(TG3_CPMU_EEE_DBTMR1
) & 0xffff;
2386 static void tg3_phy_eee_adjust(struct tg3
*tp
, bool current_link_up
)
2390 if (!(tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
))
2395 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
2397 tp
->link_config
.active_duplex
== DUPLEX_FULL
&&
2398 (tp
->link_config
.active_speed
== SPEED_100
||
2399 tp
->link_config
.active_speed
== SPEED_1000
)) {
2402 if (tp
->link_config
.active_speed
== SPEED_1000
)
2403 eeectl
= TG3_CPMU_EEE_CTRL_EXIT_16_5_US
;
2405 eeectl
= TG3_CPMU_EEE_CTRL_EXIT_36_US
;
2407 tw32(TG3_CPMU_EEE_CTRL
, eeectl
);
2409 tg3_eee_pull_config(tp
, NULL
);
2410 if (tp
->eee
.eee_active
)
2414 if (!tp
->setlpicnt
) {
2415 if (current_link_up
&&
2416 !tg3_phy_toggle_auxctl_smdsp(tp
, true)) {
2417 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP26
, 0x0000);
2418 tg3_phy_toggle_auxctl_smdsp(tp
, false);
2421 val
= tr32(TG3_CPMU_EEE_MODE
);
2422 tw32(TG3_CPMU_EEE_MODE
, val
& ~TG3_CPMU_EEEMD_LPI_ENABLE
);
2426 static void tg3_phy_eee_enable(struct tg3
*tp
)
2430 if (tp
->link_config
.active_speed
== SPEED_1000
&&
2431 (tg3_asic_rev(tp
) == ASIC_REV_5717
||
2432 tg3_asic_rev(tp
) == ASIC_REV_5719
||
2433 tg3_flag(tp
, 57765_CLASS
)) &&
2434 !tg3_phy_toggle_auxctl_smdsp(tp
, true)) {
2435 val
= MII_TG3_DSP_TAP26_ALNOKO
|
2436 MII_TG3_DSP_TAP26_RMRXSTO
;
2437 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP26
, val
);
2438 tg3_phy_toggle_auxctl_smdsp(tp
, false);
2441 val
= tr32(TG3_CPMU_EEE_MODE
);
2442 tw32(TG3_CPMU_EEE_MODE
, val
| TG3_CPMU_EEEMD_LPI_ENABLE
);
2445 static int tg3_wait_macro_done(struct tg3
*tp
)
2452 if (!tg3_readphy(tp
, MII_TG3_DSP_CONTROL
, &tmp32
)) {
2453 if ((tmp32
& 0x1000) == 0)
2463 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
2465 static const u32 test_pat
[4][6] = {
2466 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2467 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2468 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2469 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2473 for (chan
= 0; chan
< 4; chan
++) {
2476 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
2477 (chan
* 0x2000) | 0x0200);
2478 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0002);
2480 for (i
= 0; i
< 6; i
++)
2481 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
2484 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0202);
2485 if (tg3_wait_macro_done(tp
)) {
2490 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
2491 (chan
* 0x2000) | 0x0200);
2492 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0082);
2493 if (tg3_wait_macro_done(tp
)) {
2498 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0802);
2499 if (tg3_wait_macro_done(tp
)) {
2504 for (i
= 0; i
< 6; i
+= 2) {
2507 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
2508 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
2509 tg3_wait_macro_done(tp
)) {
2515 if (low
!= test_pat
[chan
][i
] ||
2516 high
!= test_pat
[chan
][i
+1]) {
2517 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
2518 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
2519 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
2529 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
2533 for (chan
= 0; chan
< 4; chan
++) {
2536 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
2537 (chan
* 0x2000) | 0x0200);
2538 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0002);
2539 for (i
= 0; i
< 6; i
++)
2540 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
2541 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0202);
2542 if (tg3_wait_macro_done(tp
))
2549 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
2551 u32 reg32
, phy9_orig
;
2552 int retries
, do_phy_reset
, err
;
2558 err
= tg3_bmcr_reset(tp
);
2564 /* Disable transmitter and interrupt. */
2565 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
2569 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
2571 /* Set full-duplex, 1000 mbps. */
2572 tg3_writephy(tp
, MII_BMCR
,
2573 BMCR_FULLDPLX
| BMCR_SPEED1000
);
2575 /* Set to master mode. */
2576 if (tg3_readphy(tp
, MII_CTRL1000
, &phy9_orig
))
2579 tg3_writephy(tp
, MII_CTRL1000
,
2580 CTL1000_AS_MASTER
| CTL1000_ENABLE_MASTER
);
2582 err
= tg3_phy_toggle_auxctl_smdsp(tp
, true);
2586 /* Block the PHY control access. */
2587 tg3_phydsp_write(tp
, 0x8005, 0x0800);
2589 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
2592 } while (--retries
);
2594 err
= tg3_phy_reset_chanpat(tp
);
2598 tg3_phydsp_write(tp
, 0x8005, 0x0000);
2600 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
2601 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0000);
2603 tg3_phy_toggle_auxctl_smdsp(tp
, false);
2605 tg3_writephy(tp
, MII_CTRL1000
, phy9_orig
);
2607 err
= tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
);
2612 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
2617 static void tg3_carrier_off(struct tg3
*tp
)
2619 netif_carrier_off(tp
->dev
);
2620 tp
->link_up
= false;
2623 static void tg3_warn_mgmt_link_flap(struct tg3
*tp
)
2625 if (tg3_flag(tp
, ENABLE_ASF
))
2626 netdev_warn(tp
->dev
,
2627 "Management side-band traffic will be interrupted during phy settings change\n");
2630 /* This will reset the tigon3 PHY if there is no valid
2631 * link unless the FORCE argument is non-zero.
2633 static int tg3_phy_reset(struct tg3
*tp
)
2638 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
2639 val
= tr32(GRC_MISC_CFG
);
2640 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
2643 err
= tg3_readphy(tp
, MII_BMSR
, &val
);
2644 err
|= tg3_readphy(tp
, MII_BMSR
, &val
);
2648 if (netif_running(tp
->dev
) && tp
->link_up
) {
2649 netif_carrier_off(tp
->dev
);
2650 tg3_link_report(tp
);
2653 if (tg3_asic_rev(tp
) == ASIC_REV_5703
||
2654 tg3_asic_rev(tp
) == ASIC_REV_5704
||
2655 tg3_asic_rev(tp
) == ASIC_REV_5705
) {
2656 err
= tg3_phy_reset_5703_4_5(tp
);
2663 if (tg3_asic_rev(tp
) == ASIC_REV_5784
&&
2664 tg3_chip_rev(tp
) != CHIPREV_5784_AX
) {
2665 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
2666 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
2668 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
2671 err
= tg3_bmcr_reset(tp
);
2675 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
2676 val
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
2677 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, val
);
2679 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
2682 if (tg3_chip_rev(tp
) == CHIPREV_5784_AX
||
2683 tg3_chip_rev(tp
) == CHIPREV_5761_AX
) {
2684 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2685 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
2686 CPMU_LSPD_1000MB_MACCLK_12_5
) {
2687 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2689 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2693 if (tg3_flag(tp
, 5717_PLUS
) &&
2694 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
))
2697 tg3_phy_apply_otp(tp
);
2699 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
2700 tg3_phy_toggle_apd(tp
, true);
2702 tg3_phy_toggle_apd(tp
, false);
2705 if ((tp
->phy_flags
& TG3_PHYFLG_ADC_BUG
) &&
2706 !tg3_phy_toggle_auxctl_smdsp(tp
, true)) {
2707 tg3_phydsp_write(tp
, 0x201f, 0x2aaa);
2708 tg3_phydsp_write(tp
, 0x000a, 0x0323);
2709 tg3_phy_toggle_auxctl_smdsp(tp
, false);
2712 if (tp
->phy_flags
& TG3_PHYFLG_5704_A0_BUG
) {
2713 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
2714 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
2717 if (tp
->phy_flags
& TG3_PHYFLG_BER_BUG
) {
2718 if (!tg3_phy_toggle_auxctl_smdsp(tp
, true)) {
2719 tg3_phydsp_write(tp
, 0x000a, 0x310b);
2720 tg3_phydsp_write(tp
, 0x201f, 0x9506);
2721 tg3_phydsp_write(tp
, 0x401f, 0x14e2);
2722 tg3_phy_toggle_auxctl_smdsp(tp
, false);
2724 } else if (tp
->phy_flags
& TG3_PHYFLG_JITTER_BUG
) {
2725 if (!tg3_phy_toggle_auxctl_smdsp(tp
, true)) {
2726 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
2727 if (tp
->phy_flags
& TG3_PHYFLG_ADJUST_TRIM
) {
2728 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
2729 tg3_writephy(tp
, MII_TG3_TEST1
,
2730 MII_TG3_TEST1_TRIM_EN
| 0x4);
2732 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
2734 tg3_phy_toggle_auxctl_smdsp(tp
, false);
2738 /* Set Extended packet length bit (bit 14) on all chips that */
2739 /* support jumbo frames */
2740 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
2741 /* Cannot do read-modify-write on 5401 */
2742 tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_AUXCTL
, 0x4c20);
2743 } else if (tg3_flag(tp
, JUMBO_CAPABLE
)) {
2744 /* Set bit 14 with read-modify-write to preserve other bits */
2745 err
= tg3_phy_auxctl_read(tp
,
2746 MII_TG3_AUXCTL_SHDWSEL_AUXCTL
, &val
);
2748 tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_AUXCTL
,
2749 val
| MII_TG3_AUXCTL_ACTL_EXTPKTLEN
);
2752 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2753 * jumbo frames transmission.
2755 if (tg3_flag(tp
, JUMBO_CAPABLE
)) {
2756 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &val
))
2757 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2758 val
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
2761 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
2762 /* adjust output voltage */
2763 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x12);
2766 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5762_A0
)
2767 tg3_phydsp_write(tp
, 0xffb, 0x4000);
2769 tg3_phy_toggle_automdix(tp
, true);
2770 tg3_phy_set_wirespeed(tp
);
2774 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2775 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2776 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2777 TG3_GPIO_MSG_NEED_VAUX)
2778 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2779 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2780 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2781 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2782 (TG3_GPIO_MSG_DRVR_PRES << 12))
2784 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2785 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2786 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2787 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2788 (TG3_GPIO_MSG_NEED_VAUX << 12))
2790 static inline u32
tg3_set_function_status(struct tg3
*tp
, u32 newstat
)
2794 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
2795 tg3_asic_rev(tp
) == ASIC_REV_5719
)
2796 status
= tg3_ape_read32(tp
, TG3_APE_GPIO_MSG
);
2798 status
= tr32(TG3_CPMU_DRV_STATUS
);
2800 shift
= TG3_APE_GPIO_MSG_SHIFT
+ 4 * tp
->pci_fn
;
2801 status
&= ~(TG3_GPIO_MSG_MASK
<< shift
);
2802 status
|= (newstat
<< shift
);
2804 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
2805 tg3_asic_rev(tp
) == ASIC_REV_5719
)
2806 tg3_ape_write32(tp
, TG3_APE_GPIO_MSG
, status
);
2808 tw32(TG3_CPMU_DRV_STATUS
, status
);
2810 return status
>> TG3_APE_GPIO_MSG_SHIFT
;
2813 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3
*tp
)
2815 if (!tg3_flag(tp
, IS_NIC
))
2818 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
2819 tg3_asic_rev(tp
) == ASIC_REV_5719
||
2820 tg3_asic_rev(tp
) == ASIC_REV_5720
) {
2821 if (tg3_ape_lock(tp
, TG3_APE_LOCK_GPIO
))
2824 tg3_set_function_status(tp
, TG3_GPIO_MSG_DRVR_PRES
);
2826 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
,
2827 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2829 tg3_ape_unlock(tp
, TG3_APE_LOCK_GPIO
);
2831 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
,
2832 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2838 static void tg3_pwrsrc_die_with_vmain(struct tg3
*tp
)
2842 if (!tg3_flag(tp
, IS_NIC
) ||
2843 tg3_asic_rev(tp
) == ASIC_REV_5700
||
2844 tg3_asic_rev(tp
) == ASIC_REV_5701
)
2847 grc_local_ctrl
= tp
->grc_local_ctrl
| GRC_LCLCTRL_GPIO_OE1
;
2849 tw32_wait_f(GRC_LOCAL_CTRL
,
2850 grc_local_ctrl
| GRC_LCLCTRL_GPIO_OUTPUT1
,
2851 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2853 tw32_wait_f(GRC_LOCAL_CTRL
,
2855 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2857 tw32_wait_f(GRC_LOCAL_CTRL
,
2858 grc_local_ctrl
| GRC_LCLCTRL_GPIO_OUTPUT1
,
2859 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2862 static void tg3_pwrsrc_switch_to_vaux(struct tg3
*tp
)
2864 if (!tg3_flag(tp
, IS_NIC
))
2867 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
2868 tg3_asic_rev(tp
) == ASIC_REV_5701
) {
2869 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2870 (GRC_LCLCTRL_GPIO_OE0
|
2871 GRC_LCLCTRL_GPIO_OE1
|
2872 GRC_LCLCTRL_GPIO_OE2
|
2873 GRC_LCLCTRL_GPIO_OUTPUT0
|
2874 GRC_LCLCTRL_GPIO_OUTPUT1
),
2875 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2876 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
2877 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
2878 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2879 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
2880 GRC_LCLCTRL_GPIO_OE1
|
2881 GRC_LCLCTRL_GPIO_OE2
|
2882 GRC_LCLCTRL_GPIO_OUTPUT0
|
2883 GRC_LCLCTRL_GPIO_OUTPUT1
|
2885 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
,
2886 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2888 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
2889 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
,
2890 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2892 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
2893 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
,
2894 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2897 u32 grc_local_ctrl
= 0;
2899 /* Workaround to prevent overdrawing Amps. */
2900 if (tg3_asic_rev(tp
) == ASIC_REV_5714
) {
2901 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
2902 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2904 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2907 /* On 5753 and variants, GPIO2 cannot be used. */
2908 no_gpio2
= tp
->nic_sram_data_cfg
&
2909 NIC_SRAM_DATA_CFG_NO_GPIO2
;
2911 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
2912 GRC_LCLCTRL_GPIO_OE1
|
2913 GRC_LCLCTRL_GPIO_OE2
|
2914 GRC_LCLCTRL_GPIO_OUTPUT1
|
2915 GRC_LCLCTRL_GPIO_OUTPUT2
;
2917 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
2918 GRC_LCLCTRL_GPIO_OUTPUT2
);
2920 tw32_wait_f(GRC_LOCAL_CTRL
,
2921 tp
->grc_local_ctrl
| grc_local_ctrl
,
2922 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2924 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2926 tw32_wait_f(GRC_LOCAL_CTRL
,
2927 tp
->grc_local_ctrl
| grc_local_ctrl
,
2928 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2931 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2932 tw32_wait_f(GRC_LOCAL_CTRL
,
2933 tp
->grc_local_ctrl
| grc_local_ctrl
,
2934 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2939 static void tg3_frob_aux_power_5717(struct tg3
*tp
, bool wol_enable
)
2943 /* Serialize power state transitions */
2944 if (tg3_ape_lock(tp
, TG3_APE_LOCK_GPIO
))
2947 if (tg3_flag(tp
, ENABLE_ASF
) || tg3_flag(tp
, ENABLE_APE
) || wol_enable
)
2948 msg
= TG3_GPIO_MSG_NEED_VAUX
;
2950 msg
= tg3_set_function_status(tp
, msg
);
2952 if (msg
& TG3_GPIO_MSG_ALL_DRVR_PRES_MASK
)
2955 if (msg
& TG3_GPIO_MSG_ALL_NEED_VAUX_MASK
)
2956 tg3_pwrsrc_switch_to_vaux(tp
);
2958 tg3_pwrsrc_die_with_vmain(tp
);
2961 tg3_ape_unlock(tp
, TG3_APE_LOCK_GPIO
);
2964 static void tg3_frob_aux_power(struct tg3
*tp
, bool include_wol
)
2966 bool need_vaux
= false;
2968 /* The GPIOs do something completely different on 57765. */
2969 if (!tg3_flag(tp
, IS_NIC
) || tg3_flag(tp
, 57765_CLASS
))
2972 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
2973 tg3_asic_rev(tp
) == ASIC_REV_5719
||
2974 tg3_asic_rev(tp
) == ASIC_REV_5720
) {
2975 tg3_frob_aux_power_5717(tp
, include_wol
?
2976 tg3_flag(tp
, WOL_ENABLE
) != 0 : 0);
2980 if (tp
->pdev_peer
&& tp
->pdev_peer
!= tp
->pdev
) {
2981 struct net_device
*dev_peer
;
2983 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
2985 /* remove_one() may have been run on the peer. */
2987 struct tg3
*tp_peer
= netdev_priv(dev_peer
);
2989 if (tg3_flag(tp_peer
, INIT_COMPLETE
))
2992 if ((include_wol
&& tg3_flag(tp_peer
, WOL_ENABLE
)) ||
2993 tg3_flag(tp_peer
, ENABLE_ASF
))
2998 if ((include_wol
&& tg3_flag(tp
, WOL_ENABLE
)) ||
2999 tg3_flag(tp
, ENABLE_ASF
))
3003 tg3_pwrsrc_switch_to_vaux(tp
);
3005 tg3_pwrsrc_die_with_vmain(tp
);
3008 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
3010 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
3012 else if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
) {
3013 if (speed
!= SPEED_10
)
3015 } else if (speed
== SPEED_10
)
3021 static bool tg3_phy_power_bug(struct tg3
*tp
)
3023 switch (tg3_asic_rev(tp
)) {
3028 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
3037 if ((tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
3046 static bool tg3_phy_led_bug(struct tg3
*tp
)
3048 switch (tg3_asic_rev(tp
)) {
3051 if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
3060 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
3064 if (tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
)
3067 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
3068 if (tg3_asic_rev(tp
) == ASIC_REV_5704
) {
3069 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3070 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
3073 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
3074 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
3075 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
3080 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
3082 val
= tr32(GRC_MISC_CFG
);
3083 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
3086 } else if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
3088 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
3091 tg3_writephy(tp
, MII_ADVERTISE
, 0);
3092 tg3_writephy(tp
, MII_BMCR
,
3093 BMCR_ANENABLE
| BMCR_ANRESTART
);
3095 tg3_writephy(tp
, MII_TG3_FET_TEST
,
3096 phytest
| MII_TG3_FET_SHADOW_EN
);
3097 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXMODE4
, &phy
)) {
3098 phy
|= MII_TG3_FET_SHDW_AUXMODE4_SBPD
;
3100 MII_TG3_FET_SHDW_AUXMODE4
,
3103 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
3106 } else if (do_low_power
) {
3107 if (!tg3_phy_led_bug(tp
))
3108 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
3109 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
3111 val
= MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
3112 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
3113 MII_TG3_AUXCTL_PCTL_VREG_11V
;
3114 tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_PWRCTL
, val
);
3117 /* The PHY should not be powered down on some chips because
3120 if (tg3_phy_power_bug(tp
))
3123 if (tg3_chip_rev(tp
) == CHIPREV_5784_AX
||
3124 tg3_chip_rev(tp
) == CHIPREV_5761_AX
) {
3125 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
3126 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
3127 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
3128 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
3131 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3134 /* tp->lock is held. */
3135 static int tg3_nvram_lock(struct tg3
*tp
)
3137 if (tg3_flag(tp
, NVRAM
)) {
3140 if (tp
->nvram_lock_cnt
== 0) {
3141 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
3142 for (i
= 0; i
< 8000; i
++) {
3143 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
3148 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
3152 tp
->nvram_lock_cnt
++;
3157 /* tp->lock is held. */
3158 static void tg3_nvram_unlock(struct tg3
*tp
)
3160 if (tg3_flag(tp
, NVRAM
)) {
3161 if (tp
->nvram_lock_cnt
> 0)
3162 tp
->nvram_lock_cnt
--;
3163 if (tp
->nvram_lock_cnt
== 0)
3164 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
3168 /* tp->lock is held. */
3169 static void tg3_enable_nvram_access(struct tg3
*tp
)
3171 if (tg3_flag(tp
, 5750_PLUS
) && !tg3_flag(tp
, PROTECTED_NVRAM
)) {
3172 u32 nvaccess
= tr32(NVRAM_ACCESS
);
3174 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
3178 /* tp->lock is held. */
3179 static void tg3_disable_nvram_access(struct tg3
*tp
)
3181 if (tg3_flag(tp
, 5750_PLUS
) && !tg3_flag(tp
, PROTECTED_NVRAM
)) {
3182 u32 nvaccess
= tr32(NVRAM_ACCESS
);
3184 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
3188 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
3189 u32 offset
, u32
*val
)
3194 if (offset
> EEPROM_ADDR_ADDR_MASK
|| (offset
% 4) != 0)
3197 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
3198 EEPROM_ADDR_DEVID_MASK
|
3200 tw32(GRC_EEPROM_ADDR
,
3202 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
3203 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
3204 EEPROM_ADDR_ADDR_MASK
) |
3205 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
3207 for (i
= 0; i
< 1000; i
++) {
3208 tmp
= tr32(GRC_EEPROM_ADDR
);
3210 if (tmp
& EEPROM_ADDR_COMPLETE
)
3214 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
3217 tmp
= tr32(GRC_EEPROM_DATA
);
3220 * The data will always be opposite the native endian
3221 * format. Perform a blind byteswap to compensate.
3228 #define NVRAM_CMD_TIMEOUT 5000
3230 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
3234 tw32(NVRAM_CMD
, nvram_cmd
);
3235 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
3236 usleep_range(10, 40);
3237 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
3243 if (i
== NVRAM_CMD_TIMEOUT
)
3249 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
3251 if (tg3_flag(tp
, NVRAM
) &&
3252 tg3_flag(tp
, NVRAM_BUFFERED
) &&
3253 tg3_flag(tp
, FLASH
) &&
3254 !tg3_flag(tp
, NO_NVRAM_ADDR_TRANS
) &&
3255 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
3257 addr
= ((addr
/ tp
->nvram_pagesize
) <<
3258 ATMEL_AT45DB0X1B_PAGE_POS
) +
3259 (addr
% tp
->nvram_pagesize
);
3264 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
3266 if (tg3_flag(tp
, NVRAM
) &&
3267 tg3_flag(tp
, NVRAM_BUFFERED
) &&
3268 tg3_flag(tp
, FLASH
) &&
3269 !tg3_flag(tp
, NO_NVRAM_ADDR_TRANS
) &&
3270 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
3272 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
3273 tp
->nvram_pagesize
) +
3274 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
3279 /* NOTE: Data read in from NVRAM is byteswapped according to
3280 * the byteswapping settings for all other register accesses.
3281 * tg3 devices are BE devices, so on a BE machine, the data
3282 * returned will be exactly as it is seen in NVRAM. On a LE
3283 * machine, the 32-bit value will be byteswapped.
3285 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
3289 if (!tg3_flag(tp
, NVRAM
))
3290 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
3292 offset
= tg3_nvram_phys_addr(tp
, offset
);
3294 if (offset
> NVRAM_ADDR_MSK
)
3297 ret
= tg3_nvram_lock(tp
);
3301 tg3_enable_nvram_access(tp
);
3303 tw32(NVRAM_ADDR
, offset
);
3304 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
3305 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
3308 *val
= tr32(NVRAM_RDDATA
);
3310 tg3_disable_nvram_access(tp
);
3312 tg3_nvram_unlock(tp
);
3317 /* Ensures NVRAM data is in bytestream format. */
3318 static int tg3_nvram_read_be32(struct tg3
*tp
, u32 offset
, __be32
*val
)
3321 int res
= tg3_nvram_read(tp
, offset
, &v
);
3323 *val
= cpu_to_be32(v
);
3327 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
3328 u32 offset
, u32 len
, u8
*buf
)
3333 for (i
= 0; i
< len
; i
+= 4) {
3339 memcpy(&data
, buf
+ i
, 4);
3342 * The SEEPROM interface expects the data to always be opposite
3343 * the native endian format. We accomplish this by reversing
3344 * all the operations that would have been performed on the
3345 * data from a call to tg3_nvram_read_be32().
3347 tw32(GRC_EEPROM_DATA
, swab32(be32_to_cpu(data
)));
3349 val
= tr32(GRC_EEPROM_ADDR
);
3350 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
3352 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
3354 tw32(GRC_EEPROM_ADDR
, val
|
3355 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
3356 (addr
& EEPROM_ADDR_ADDR_MASK
) |
3360 for (j
= 0; j
< 1000; j
++) {
3361 val
= tr32(GRC_EEPROM_ADDR
);
3363 if (val
& EEPROM_ADDR_COMPLETE
)
3367 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
3376 /* offset and length are dword aligned */
3377 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
3381 u32 pagesize
= tp
->nvram_pagesize
;
3382 u32 pagemask
= pagesize
- 1;
3386 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
3392 u32 phy_addr
, page_off
, size
;
3394 phy_addr
= offset
& ~pagemask
;
3396 for (j
= 0; j
< pagesize
; j
+= 4) {
3397 ret
= tg3_nvram_read_be32(tp
, phy_addr
+ j
,
3398 (__be32
*) (tmp
+ j
));
3405 page_off
= offset
& pagemask
;
3412 memcpy(tmp
+ page_off
, buf
, size
);
3414 offset
= offset
+ (pagesize
- page_off
);
3416 tg3_enable_nvram_access(tp
);
3419 * Before we can erase the flash page, we need
3420 * to issue a special "write enable" command.
3422 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
3424 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
3427 /* Erase the target page */
3428 tw32(NVRAM_ADDR
, phy_addr
);
3430 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
3431 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
3433 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
3436 /* Issue another write enable to start the write. */
3437 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
3439 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
3442 for (j
= 0; j
< pagesize
; j
+= 4) {
3445 data
= *((__be32
*) (tmp
+ j
));
3447 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
3449 tw32(NVRAM_ADDR
, phy_addr
+ j
);
3451 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
3455 nvram_cmd
|= NVRAM_CMD_FIRST
;
3456 else if (j
== (pagesize
- 4))
3457 nvram_cmd
|= NVRAM_CMD_LAST
;
3459 ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
);
3467 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
3468 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
3475 /* offset and length are dword aligned */
3476 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
3481 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
3482 u32 page_off
, phy_addr
, nvram_cmd
;
3485 memcpy(&data
, buf
+ i
, 4);
3486 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
3488 page_off
= offset
% tp
->nvram_pagesize
;
3490 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
3492 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
3494 if (page_off
== 0 || i
== 0)
3495 nvram_cmd
|= NVRAM_CMD_FIRST
;
3496 if (page_off
== (tp
->nvram_pagesize
- 4))
3497 nvram_cmd
|= NVRAM_CMD_LAST
;
3500 nvram_cmd
|= NVRAM_CMD_LAST
;
3502 if ((nvram_cmd
& NVRAM_CMD_FIRST
) ||
3503 !tg3_flag(tp
, FLASH
) ||
3504 !tg3_flag(tp
, 57765_PLUS
))
3505 tw32(NVRAM_ADDR
, phy_addr
);
3507 if (tg3_asic_rev(tp
) != ASIC_REV_5752
&&
3508 !tg3_flag(tp
, 5755_PLUS
) &&
3509 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
3510 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
3513 cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
3514 ret
= tg3_nvram_exec_cmd(tp
, cmd
);
3518 if (!tg3_flag(tp
, FLASH
)) {
3519 /* We always do complete word writes to eeprom. */
3520 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
3523 ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
);
3530 /* offset and length are dword aligned */
3531 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
3535 if (tg3_flag(tp
, EEPROM_WRITE_PROT
)) {
3536 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
3537 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
3541 if (!tg3_flag(tp
, NVRAM
)) {
3542 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
3546 ret
= tg3_nvram_lock(tp
);
3550 tg3_enable_nvram_access(tp
);
3551 if (tg3_flag(tp
, 5750_PLUS
) && !tg3_flag(tp
, PROTECTED_NVRAM
))
3552 tw32(NVRAM_WRITE1
, 0x406);
3554 grc_mode
= tr32(GRC_MODE
);
3555 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
3557 if (tg3_flag(tp
, NVRAM_BUFFERED
) || !tg3_flag(tp
, FLASH
)) {
3558 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
3561 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
3565 grc_mode
= tr32(GRC_MODE
);
3566 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
3568 tg3_disable_nvram_access(tp
);
3569 tg3_nvram_unlock(tp
);
3572 if (tg3_flag(tp
, EEPROM_WRITE_PROT
)) {
3573 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
3580 #define RX_CPU_SCRATCH_BASE 0x30000
3581 #define RX_CPU_SCRATCH_SIZE 0x04000
3582 #define TX_CPU_SCRATCH_BASE 0x34000
3583 #define TX_CPU_SCRATCH_SIZE 0x04000
3585 /* tp->lock is held. */
3586 static int tg3_pause_cpu(struct tg3
*tp
, u32 cpu_base
)
3589 const int iters
= 10000;
3591 for (i
= 0; i
< iters
; i
++) {
3592 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
3593 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
3594 if (tr32(cpu_base
+ CPU_MODE
) & CPU_MODE_HALT
)
3596 if (pci_channel_offline(tp
->pdev
))
3600 return (i
== iters
) ? -EBUSY
: 0;
3603 /* tp->lock is held. */
3604 static int tg3_rxcpu_pause(struct tg3
*tp
)
3606 int rc
= tg3_pause_cpu(tp
, RX_CPU_BASE
);
3608 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
3609 tw32_f(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
3615 /* tp->lock is held. */
3616 static int tg3_txcpu_pause(struct tg3
*tp
)
3618 return tg3_pause_cpu(tp
, TX_CPU_BASE
);
3621 /* tp->lock is held. */
3622 static void tg3_resume_cpu(struct tg3
*tp
, u32 cpu_base
)
3624 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
3625 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
3628 /* tp->lock is held. */
3629 static void tg3_rxcpu_resume(struct tg3
*tp
)
3631 tg3_resume_cpu(tp
, RX_CPU_BASE
);
3634 /* tp->lock is held. */
3635 static int tg3_halt_cpu(struct tg3
*tp
, u32 cpu_base
)
3639 BUG_ON(cpu_base
== TX_CPU_BASE
&& tg3_flag(tp
, 5705_PLUS
));
3641 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
3642 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
3644 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
3647 if (cpu_base
== RX_CPU_BASE
) {
3648 rc
= tg3_rxcpu_pause(tp
);
3651 * There is only an Rx CPU for the 5750 derivative in the
3654 if (tg3_flag(tp
, IS_SSB_CORE
))
3657 rc
= tg3_txcpu_pause(tp
);
3661 netdev_err(tp
->dev
, "%s timed out, %s CPU\n",
3662 __func__
, cpu_base
== RX_CPU_BASE
? "RX" : "TX");
3666 /* Clear firmware's nvram arbitration. */
3667 if (tg3_flag(tp
, NVRAM
))
3668 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
3672 static int tg3_fw_data_len(struct tg3
*tp
,
3673 const struct tg3_firmware_hdr
*fw_hdr
)
3677 /* Non fragmented firmware have one firmware header followed by a
3678 * contiguous chunk of data to be written. The length field in that
3679 * header is not the length of data to be written but the complete
3680 * length of the bss. The data length is determined based on
3681 * tp->fw->size minus headers.
3683 * Fragmented firmware have a main header followed by multiple
3684 * fragments. Each fragment is identical to non fragmented firmware
3685 * with a firmware header followed by a contiguous chunk of data. In
3686 * the main header, the length field is unused and set to 0xffffffff.
3687 * In each fragment header the length is the entire size of that
3688 * fragment i.e. fragment data + header length. Data length is
3689 * therefore length field in the header minus TG3_FW_HDR_LEN.
3691 if (tp
->fw_len
== 0xffffffff)
3692 fw_len
= be32_to_cpu(fw_hdr
->len
);
3694 fw_len
= tp
->fw
->size
;
3696 return (fw_len
- TG3_FW_HDR_LEN
) / sizeof(u32
);
3699 /* tp->lock is held. */
3700 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
,
3701 u32 cpu_scratch_base
, int cpu_scratch_size
,
3702 const struct tg3_firmware_hdr
*fw_hdr
)
3705 void (*write_op
)(struct tg3
*, u32
, u32
);
3706 int total_len
= tp
->fw
->size
;
3708 if (cpu_base
== TX_CPU_BASE
&& tg3_flag(tp
, 5705_PLUS
)) {
3710 "%s: Trying to load TX cpu firmware which is 5705\n",
3715 if (tg3_flag(tp
, 5705_PLUS
) && tg3_asic_rev(tp
) != ASIC_REV_57766
)
3716 write_op
= tg3_write_mem
;
3718 write_op
= tg3_write_indirect_reg32
;
3720 if (tg3_asic_rev(tp
) != ASIC_REV_57766
) {
3721 /* It is possible that bootcode is still loading at this point.
3722 * Get the nvram lock first before halting the cpu.
3724 int lock_err
= tg3_nvram_lock(tp
);
3725 err
= tg3_halt_cpu(tp
, cpu_base
);
3727 tg3_nvram_unlock(tp
);
3731 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
3732 write_op(tp
, cpu_scratch_base
+ i
, 0);
3733 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
3734 tw32(cpu_base
+ CPU_MODE
,
3735 tr32(cpu_base
+ CPU_MODE
) | CPU_MODE_HALT
);
3737 /* Subtract additional main header for fragmented firmware and
3738 * advance to the first fragment
3740 total_len
-= TG3_FW_HDR_LEN
;
3745 u32
*fw_data
= (u32
*)(fw_hdr
+ 1);
3746 for (i
= 0; i
< tg3_fw_data_len(tp
, fw_hdr
); i
++)
3747 write_op(tp
, cpu_scratch_base
+
3748 (be32_to_cpu(fw_hdr
->base_addr
) & 0xffff) +
3750 be32_to_cpu(fw_data
[i
]));
3752 total_len
-= be32_to_cpu(fw_hdr
->len
);
3754 /* Advance to next fragment */
3755 fw_hdr
= (struct tg3_firmware_hdr
*)
3756 ((void *)fw_hdr
+ be32_to_cpu(fw_hdr
->len
));
3757 } while (total_len
> 0);
3765 /* tp->lock is held. */
3766 static int tg3_pause_cpu_and_set_pc(struct tg3
*tp
, u32 cpu_base
, u32 pc
)
3769 const int iters
= 5;
3771 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
3772 tw32_f(cpu_base
+ CPU_PC
, pc
);
3774 for (i
= 0; i
< iters
; i
++) {
3775 if (tr32(cpu_base
+ CPU_PC
) == pc
)
3777 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
3778 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
3779 tw32_f(cpu_base
+ CPU_PC
, pc
);
3783 return (i
== iters
) ? -EBUSY
: 0;
3786 /* tp->lock is held. */
3787 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
3789 const struct tg3_firmware_hdr
*fw_hdr
;
3792 fw_hdr
= (struct tg3_firmware_hdr
*)tp
->fw
->data
;
3794 /* Firmware blob starts with version numbers, followed by
3795 start address and length. We are setting complete length.
3796 length = end_address_of_bss - start_address_of_text.
3797 Remainder is the blob to be loaded contiguously
3798 from start address. */
3800 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
3801 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
3806 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
3807 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
3812 /* Now startup only the RX cpu. */
3813 err
= tg3_pause_cpu_and_set_pc(tp
, RX_CPU_BASE
,
3814 be32_to_cpu(fw_hdr
->base_addr
));
3816 netdev_err(tp
->dev
, "%s fails to set RX CPU PC, is %08x "
3817 "should be %08x\n", __func__
,
3818 tr32(RX_CPU_BASE
+ CPU_PC
),
3819 be32_to_cpu(fw_hdr
->base_addr
));
3823 tg3_rxcpu_resume(tp
);
3828 static int tg3_validate_rxcpu_state(struct tg3
*tp
)
3830 const int iters
= 1000;
3834 /* Wait for boot code to complete initialization and enter service
3835 * loop. It is then safe to download service patches
3837 for (i
= 0; i
< iters
; i
++) {
3838 if (tr32(RX_CPU_HWBKPT
) == TG3_SBROM_IN_SERVICE_LOOP
)
3845 netdev_err(tp
->dev
, "Boot code not ready for service patches\n");
3849 val
= tg3_read_indirect_reg32(tp
, TG3_57766_FW_HANDSHAKE
);
3851 netdev_warn(tp
->dev
,
3852 "Other patches exist. Not downloading EEE patch\n");
3859 /* tp->lock is held. */
3860 static void tg3_load_57766_firmware(struct tg3
*tp
)
3862 struct tg3_firmware_hdr
*fw_hdr
;
3864 if (!tg3_flag(tp
, NO_NVRAM
))
3867 if (tg3_validate_rxcpu_state(tp
))
3873 /* This firmware blob has a different format than older firmware
3874 * releases as given below. The main difference is we have fragmented
3875 * data to be written to non-contiguous locations.
3877 * In the beginning we have a firmware header identical to other
3878 * firmware which consists of version, base addr and length. The length
3879 * here is unused and set to 0xffffffff.
3881 * This is followed by a series of firmware fragments which are
3882 * individually identical to previous firmware. i.e. they have the
3883 * firmware header and followed by data for that fragment. The version
3884 * field of the individual fragment header is unused.
3887 fw_hdr
= (struct tg3_firmware_hdr
*)tp
->fw
->data
;
3888 if (be32_to_cpu(fw_hdr
->base_addr
) != TG3_57766_FW_BASE_ADDR
)
3891 if (tg3_rxcpu_pause(tp
))
3894 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3895 tg3_load_firmware_cpu(tp
, 0, TG3_57766_FW_BASE_ADDR
, 0, fw_hdr
);
3897 tg3_rxcpu_resume(tp
);
3900 /* tp->lock is held. */
3901 static int tg3_load_tso_firmware(struct tg3
*tp
)
3903 const struct tg3_firmware_hdr
*fw_hdr
;
3904 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
3907 if (!tg3_flag(tp
, FW_TSO
))
3910 fw_hdr
= (struct tg3_firmware_hdr
*)tp
->fw
->data
;
3912 /* Firmware blob starts with version numbers, followed by
3913 start address and length. We are setting complete length.
3914 length = end_address_of_bss - start_address_of_text.
3915 Remainder is the blob to be loaded contiguously
3916 from start address. */
3918 cpu_scratch_size
= tp
->fw_len
;
3920 if (tg3_asic_rev(tp
) == ASIC_REV_5705
) {
3921 cpu_base
= RX_CPU_BASE
;
3922 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
3924 cpu_base
= TX_CPU_BASE
;
3925 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
3926 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
3929 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
3930 cpu_scratch_base
, cpu_scratch_size
,
3935 /* Now startup the cpu. */
3936 err
= tg3_pause_cpu_and_set_pc(tp
, cpu_base
,
3937 be32_to_cpu(fw_hdr
->base_addr
));
3940 "%s fails to set CPU PC, is %08x should be %08x\n",
3941 __func__
, tr32(cpu_base
+ CPU_PC
),
3942 be32_to_cpu(fw_hdr
->base_addr
));
3946 tg3_resume_cpu(tp
, cpu_base
);
3950 /* tp->lock is held. */
3951 static void __tg3_set_one_mac_addr(struct tg3
*tp
, u8
*mac_addr
, int index
)
3953 u32 addr_high
, addr_low
;
3955 addr_high
= ((mac_addr
[0] << 8) | mac_addr
[1]);
3956 addr_low
= ((mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
3957 (mac_addr
[4] << 8) | mac_addr
[5]);
3960 tw32(MAC_ADDR_0_HIGH
+ (index
* 8), addr_high
);
3961 tw32(MAC_ADDR_0_LOW
+ (index
* 8), addr_low
);
3964 tw32(MAC_EXTADDR_0_HIGH
+ (index
* 8), addr_high
);
3965 tw32(MAC_EXTADDR_0_LOW
+ (index
* 8), addr_low
);
3969 /* tp->lock is held. */
3970 static void __tg3_set_mac_addr(struct tg3
*tp
, bool skip_mac_1
)
3975 for (i
= 0; i
< 4; i
++) {
3976 if (i
== 1 && skip_mac_1
)
3978 __tg3_set_one_mac_addr(tp
, tp
->dev
->dev_addr
, i
);
3981 if (tg3_asic_rev(tp
) == ASIC_REV_5703
||
3982 tg3_asic_rev(tp
) == ASIC_REV_5704
) {
3983 for (i
= 4; i
< 16; i
++)
3984 __tg3_set_one_mac_addr(tp
, tp
->dev
->dev_addr
, i
);
3987 addr_high
= (tp
->dev
->dev_addr
[0] +
3988 tp
->dev
->dev_addr
[1] +
3989 tp
->dev
->dev_addr
[2] +
3990 tp
->dev
->dev_addr
[3] +
3991 tp
->dev
->dev_addr
[4] +
3992 tp
->dev
->dev_addr
[5]) &
3993 TX_BACKOFF_SEED_MASK
;
3994 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
3997 static void tg3_enable_register_access(struct tg3
*tp
)
4000 * Make sure register accesses (indirect or otherwise) will function
4003 pci_write_config_dword(tp
->pdev
,
4004 TG3PCI_MISC_HOST_CTRL
, tp
->misc_host_ctrl
);
4007 static int tg3_power_up(struct tg3
*tp
)
4011 tg3_enable_register_access(tp
);
4013 err
= pci_set_power_state(tp
->pdev
, PCI_D0
);
4015 /* Switch out of Vaux if it is a NIC */
4016 tg3_pwrsrc_switch_to_vmain(tp
);
4018 netdev_err(tp
->dev
, "Transition to D0 failed\n");
4024 static int tg3_setup_phy(struct tg3
*, bool);
4026 static int tg3_power_down_prepare(struct tg3
*tp
)
4029 bool device_should_wake
, do_low_power
;
4031 tg3_enable_register_access(tp
);
4033 /* Restore the CLKREQ setting. */
4034 if (tg3_flag(tp
, CLKREQ_BUG
))
4035 pcie_capability_set_word(tp
->pdev
, PCI_EXP_LNKCTL
,
4036 PCI_EXP_LNKCTL_CLKREQ_EN
);
4038 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
4039 tw32(TG3PCI_MISC_HOST_CTRL
,
4040 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
4042 device_should_wake
= device_may_wakeup(&tp
->pdev
->dev
) &&
4043 tg3_flag(tp
, WOL_ENABLE
);
4045 if (tg3_flag(tp
, USE_PHYLIB
)) {
4046 do_low_power
= false;
4047 if ((tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) &&
4048 !(tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
4049 struct phy_device
*phydev
;
4050 u32 phyid
, advertising
;
4052 phydev
= mdiobus_get_phy(tp
->mdio_bus
, tp
->phy_addr
);
4054 tp
->phy_flags
|= TG3_PHYFLG_IS_LOW_POWER
;
4056 tp
->link_config
.speed
= phydev
->speed
;
4057 tp
->link_config
.duplex
= phydev
->duplex
;
4058 tp
->link_config
.autoneg
= phydev
->autoneg
;
4059 tp
->link_config
.advertising
= phydev
->advertising
;
4061 advertising
= ADVERTISED_TP
|
4063 ADVERTISED_Autoneg
|
4064 ADVERTISED_10baseT_Half
;
4066 if (tg3_flag(tp
, ENABLE_ASF
) || device_should_wake
) {
4067 if (tg3_flag(tp
, WOL_SPEED_100MB
))
4069 ADVERTISED_100baseT_Half
|
4070 ADVERTISED_100baseT_Full
|
4071 ADVERTISED_10baseT_Full
;
4073 advertising
|= ADVERTISED_10baseT_Full
;
4076 phydev
->advertising
= advertising
;
4078 phy_start_aneg(phydev
);
4080 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
4081 if (phyid
!= PHY_ID_BCMAC131
) {
4082 phyid
&= PHY_BCM_OUI_MASK
;
4083 if (phyid
== PHY_BCM_OUI_1
||
4084 phyid
== PHY_BCM_OUI_2
||
4085 phyid
== PHY_BCM_OUI_3
)
4086 do_low_power
= true;
4090 do_low_power
= true;
4092 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
))
4093 tp
->phy_flags
|= TG3_PHYFLG_IS_LOW_POWER
;
4095 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
4096 tg3_setup_phy(tp
, false);
4099 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
4102 val
= tr32(GRC_VCPU_EXT_CTRL
);
4103 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
4104 } else if (!tg3_flag(tp
, ENABLE_ASF
)) {
4108 for (i
= 0; i
< 200; i
++) {
4109 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
4110 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
4115 if (tg3_flag(tp
, WOL_CAP
))
4116 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
4117 WOL_DRV_STATE_SHUTDOWN
|
4121 if (device_should_wake
) {
4124 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
4126 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
)) {
4127 tg3_phy_auxctl_write(tp
,
4128 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
,
4129 MII_TG3_AUXCTL_PCTL_WOL_EN
|
4130 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
4131 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC
);
4135 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
4136 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
4137 else if (tp
->phy_flags
&
4138 TG3_PHYFLG_KEEP_LINK_ON_PWRDN
) {
4139 if (tp
->link_config
.active_speed
== SPEED_1000
)
4140 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
4142 mac_mode
= MAC_MODE_PORT_MODE_MII
;
4144 mac_mode
= MAC_MODE_PORT_MODE_MII
;
4146 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
4147 if (tg3_asic_rev(tp
) == ASIC_REV_5700
) {
4148 u32 speed
= tg3_flag(tp
, WOL_SPEED_100MB
) ?
4149 SPEED_100
: SPEED_10
;
4150 if (tg3_5700_link_polarity(tp
, speed
))
4151 mac_mode
|= MAC_MODE_LINK_POLARITY
;
4153 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
4156 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
4159 if (!tg3_flag(tp
, 5750_PLUS
))
4160 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
4162 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
4163 if ((tg3_flag(tp
, 5705_PLUS
) && !tg3_flag(tp
, 5780_CLASS
)) &&
4164 (tg3_flag(tp
, ENABLE_ASF
) || tg3_flag(tp
, ENABLE_APE
)))
4165 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
4167 if (tg3_flag(tp
, ENABLE_APE
))
4168 mac_mode
|= MAC_MODE_APE_TX_EN
|
4169 MAC_MODE_APE_RX_EN
|
4170 MAC_MODE_TDE_ENABLE
;
4172 tw32_f(MAC_MODE
, mac_mode
);
4175 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
4179 if (!tg3_flag(tp
, WOL_SPEED_100MB
) &&
4180 (tg3_asic_rev(tp
) == ASIC_REV_5700
||
4181 tg3_asic_rev(tp
) == ASIC_REV_5701
)) {
4184 base_val
= tp
->pci_clock_ctrl
;
4185 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
4186 CLOCK_CTRL_TXCLK_DISABLE
);
4188 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
4189 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
4190 } else if (tg3_flag(tp
, 5780_CLASS
) ||
4191 tg3_flag(tp
, CPMU_PRESENT
) ||
4192 tg3_asic_rev(tp
) == ASIC_REV_5906
) {
4194 } else if (!(tg3_flag(tp
, 5750_PLUS
) && tg3_flag(tp
, ENABLE_ASF
))) {
4195 u32 newbits1
, newbits2
;
4197 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
4198 tg3_asic_rev(tp
) == ASIC_REV_5701
) {
4199 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
4200 CLOCK_CTRL_TXCLK_DISABLE
|
4202 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
4203 } else if (tg3_flag(tp
, 5705_PLUS
)) {
4204 newbits1
= CLOCK_CTRL_625_CORE
;
4205 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
4207 newbits1
= CLOCK_CTRL_ALTCLK
;
4208 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
4211 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
4214 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
4217 if (!tg3_flag(tp
, 5705_PLUS
)) {
4220 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
4221 tg3_asic_rev(tp
) == ASIC_REV_5701
) {
4222 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
4223 CLOCK_CTRL_TXCLK_DISABLE
|
4224 CLOCK_CTRL_44MHZ_CORE
);
4226 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
4229 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
4230 tp
->pci_clock_ctrl
| newbits3
, 40);
4234 if (!(device_should_wake
) && !tg3_flag(tp
, ENABLE_ASF
))
4235 tg3_power_down_phy(tp
, do_low_power
);
4237 tg3_frob_aux_power(tp
, true);
4239 /* Workaround for unstable PLL clock */
4240 if ((!tg3_flag(tp
, IS_SSB_CORE
)) &&
4241 ((tg3_chip_rev(tp
) == CHIPREV_5750_AX
) ||
4242 (tg3_chip_rev(tp
) == CHIPREV_5750_BX
))) {
4243 u32 val
= tr32(0x7d00);
4245 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4247 if (!tg3_flag(tp
, ENABLE_ASF
)) {
4250 err
= tg3_nvram_lock(tp
);
4251 tg3_halt_cpu(tp
, RX_CPU_BASE
);
4253 tg3_nvram_unlock(tp
);
4257 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
4259 tg3_ape_driver_state_change(tp
, RESET_KIND_SHUTDOWN
);
4264 static void tg3_power_down(struct tg3
*tp
)
4266 pci_wake_from_d3(tp
->pdev
, tg3_flag(tp
, WOL_ENABLE
));
4267 pci_set_power_state(tp
->pdev
, PCI_D3hot
);
4270 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
4272 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
4273 case MII_TG3_AUX_STAT_10HALF
:
4275 *duplex
= DUPLEX_HALF
;
4278 case MII_TG3_AUX_STAT_10FULL
:
4280 *duplex
= DUPLEX_FULL
;
4283 case MII_TG3_AUX_STAT_100HALF
:
4285 *duplex
= DUPLEX_HALF
;
4288 case MII_TG3_AUX_STAT_100FULL
:
4290 *duplex
= DUPLEX_FULL
;
4293 case MII_TG3_AUX_STAT_1000HALF
:
4294 *speed
= SPEED_1000
;
4295 *duplex
= DUPLEX_HALF
;
4298 case MII_TG3_AUX_STAT_1000FULL
:
4299 *speed
= SPEED_1000
;
4300 *duplex
= DUPLEX_FULL
;
4304 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
4305 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
4307 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
4311 *speed
= SPEED_UNKNOWN
;
4312 *duplex
= DUPLEX_UNKNOWN
;
4317 static int tg3_phy_autoneg_cfg(struct tg3
*tp
, u32 advertise
, u32 flowctrl
)
4322 new_adv
= ADVERTISE_CSMA
;
4323 new_adv
|= ethtool_adv_to_mii_adv_t(advertise
) & ADVERTISE_ALL
;
4324 new_adv
|= mii_advertise_flowctrl(flowctrl
);
4326 err
= tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
4330 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
4331 new_adv
= ethtool_adv_to_mii_ctrl1000_t(advertise
);
4333 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
||
4334 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B0
)
4335 new_adv
|= CTL1000_AS_MASTER
| CTL1000_ENABLE_MASTER
;
4337 err
= tg3_writephy(tp
, MII_CTRL1000
, new_adv
);
4342 if (!(tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
))
4345 tw32(TG3_CPMU_EEE_MODE
,
4346 tr32(TG3_CPMU_EEE_MODE
) & ~TG3_CPMU_EEEMD_LPI_ENABLE
);
4348 err
= tg3_phy_toggle_auxctl_smdsp(tp
, true);
4353 /* Advertise 100-BaseTX EEE ability */
4354 if (advertise
& ADVERTISED_100baseT_Full
)
4355 val
|= MDIO_AN_EEE_ADV_100TX
;
4356 /* Advertise 1000-BaseT EEE ability */
4357 if (advertise
& ADVERTISED_1000baseT_Full
)
4358 val
|= MDIO_AN_EEE_ADV_1000T
;
4360 if (!tp
->eee
.eee_enabled
) {
4362 tp
->eee
.advertised
= 0;
4364 tp
->eee
.advertised
= advertise
&
4365 (ADVERTISED_100baseT_Full
|
4366 ADVERTISED_1000baseT_Full
);
4369 err
= tg3_phy_cl45_write(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
, val
);
4373 switch (tg3_asic_rev(tp
)) {
4375 case ASIC_REV_57765
:
4376 case ASIC_REV_57766
:
4378 /* If we advertised any eee advertisements above... */
4380 val
= MII_TG3_DSP_TAP26_ALNOKO
|
4381 MII_TG3_DSP_TAP26_RMRXSTO
|
4382 MII_TG3_DSP_TAP26_OPCSINPT
;
4383 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP26
, val
);
4387 if (!tg3_phydsp_read(tp
, MII_TG3_DSP_CH34TP2
, &val
))
4388 tg3_phydsp_write(tp
, MII_TG3_DSP_CH34TP2
, val
|
4389 MII_TG3_DSP_CH34TP2_HIBW01
);
4392 err2
= tg3_phy_toggle_auxctl_smdsp(tp
, false);
4401 static void tg3_phy_copper_begin(struct tg3
*tp
)
4403 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
||
4404 (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
4407 if ((tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) &&
4408 !(tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
)) {
4409 adv
= ADVERTISED_10baseT_Half
|
4410 ADVERTISED_10baseT_Full
;
4411 if (tg3_flag(tp
, WOL_SPEED_100MB
))
4412 adv
|= ADVERTISED_100baseT_Half
|
4413 ADVERTISED_100baseT_Full
;
4414 if (tp
->phy_flags
& TG3_PHYFLG_1G_ON_VAUX_OK
) {
4415 if (!(tp
->phy_flags
&
4416 TG3_PHYFLG_DISABLE_1G_HD_ADV
))
4417 adv
|= ADVERTISED_1000baseT_Half
;
4418 adv
|= ADVERTISED_1000baseT_Full
;
4421 fc
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
4423 adv
= tp
->link_config
.advertising
;
4424 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
4425 adv
&= ~(ADVERTISED_1000baseT_Half
|
4426 ADVERTISED_1000baseT_Full
);
4428 fc
= tp
->link_config
.flowctrl
;
4431 tg3_phy_autoneg_cfg(tp
, adv
, fc
);
4433 if ((tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) &&
4434 (tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
)) {
4435 /* Normally during power down we want to autonegotiate
4436 * the lowest possible speed for WOL. However, to avoid
4437 * link flap, we leave it untouched.
4442 tg3_writephy(tp
, MII_BMCR
,
4443 BMCR_ANENABLE
| BMCR_ANRESTART
);
4446 u32 bmcr
, orig_bmcr
;
4448 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
4449 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
4451 if (tg3_asic_rev(tp
) == ASIC_REV_5714
) {
4452 /* With autoneg disabled, 5715 only links up when the
4453 * advertisement register has the configured speed
4456 tg3_writephy(tp
, MII_ADVERTISE
, ADVERTISE_ALL
);
4460 switch (tp
->link_config
.speed
) {
4466 bmcr
|= BMCR_SPEED100
;
4470 bmcr
|= BMCR_SPEED1000
;
4474 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
4475 bmcr
|= BMCR_FULLDPLX
;
4477 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
4478 (bmcr
!= orig_bmcr
)) {
4479 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
4480 for (i
= 0; i
< 1500; i
++) {
4484 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
4485 tg3_readphy(tp
, MII_BMSR
, &tmp
))
4487 if (!(tmp
& BMSR_LSTATUS
)) {
4492 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4498 static int tg3_phy_pull_config(struct tg3
*tp
)
4503 err
= tg3_readphy(tp
, MII_BMCR
, &val
);
4507 if (!(val
& BMCR_ANENABLE
)) {
4508 tp
->link_config
.autoneg
= AUTONEG_DISABLE
;
4509 tp
->link_config
.advertising
= 0;
4510 tg3_flag_clear(tp
, PAUSE_AUTONEG
);
4514 switch (val
& (BMCR_SPEED1000
| BMCR_SPEED100
)) {
4516 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
4519 tp
->link_config
.speed
= SPEED_10
;
4522 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
4525 tp
->link_config
.speed
= SPEED_100
;
4527 case BMCR_SPEED1000
:
4528 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
4529 tp
->link_config
.speed
= SPEED_1000
;
4537 if (val
& BMCR_FULLDPLX
)
4538 tp
->link_config
.duplex
= DUPLEX_FULL
;
4540 tp
->link_config
.duplex
= DUPLEX_HALF
;
4542 tp
->link_config
.flowctrl
= FLOW_CTRL_RX
| FLOW_CTRL_TX
;
4548 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
4549 tp
->link_config
.advertising
= ADVERTISED_Autoneg
;
4550 tg3_flag_set(tp
, PAUSE_AUTONEG
);
4552 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
4555 err
= tg3_readphy(tp
, MII_ADVERTISE
, &val
);
4559 adv
= mii_adv_to_ethtool_adv_t(val
& ADVERTISE_ALL
);
4560 tp
->link_config
.advertising
|= adv
| ADVERTISED_TP
;
4562 tp
->link_config
.flowctrl
= tg3_decode_flowctrl_1000T(val
);
4564 tp
->link_config
.advertising
|= ADVERTISED_FIBRE
;
4567 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
4570 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
4571 err
= tg3_readphy(tp
, MII_CTRL1000
, &val
);
4575 adv
= mii_ctrl1000_to_ethtool_adv_t(val
);
4577 err
= tg3_readphy(tp
, MII_ADVERTISE
, &val
);
4581 adv
= tg3_decode_flowctrl_1000X(val
);
4582 tp
->link_config
.flowctrl
= adv
;
4584 val
&= (ADVERTISE_1000XHALF
| ADVERTISE_1000XFULL
);
4585 adv
= mii_adv_to_ethtool_adv_x(val
);
4588 tp
->link_config
.advertising
|= adv
;
4595 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
4599 /* Turn off tap power management. */
4600 /* Set Extended packet length bit */
4601 err
= tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_AUXCTL
, 0x4c20);
4603 err
|= tg3_phydsp_write(tp
, 0x0012, 0x1804);
4604 err
|= tg3_phydsp_write(tp
, 0x0013, 0x1204);
4605 err
|= tg3_phydsp_write(tp
, 0x8006, 0x0132);
4606 err
|= tg3_phydsp_write(tp
, 0x8006, 0x0232);
4607 err
|= tg3_phydsp_write(tp
, 0x201f, 0x0a20);
4614 static bool tg3_phy_eee_config_ok(struct tg3
*tp
)
4616 struct ethtool_eee eee
;
4618 if (!(tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
))
4621 tg3_eee_pull_config(tp
, &eee
);
4623 if (tp
->eee
.eee_enabled
) {
4624 if (tp
->eee
.advertised
!= eee
.advertised
||
4625 tp
->eee
.tx_lpi_timer
!= eee
.tx_lpi_timer
||
4626 tp
->eee
.tx_lpi_enabled
!= eee
.tx_lpi_enabled
)
4629 /* EEE is disabled but we're advertising */
4637 static bool tg3_phy_copper_an_config_ok(struct tg3
*tp
, u32
*lcladv
)
4639 u32 advmsk
, tgtadv
, advertising
;
4641 advertising
= tp
->link_config
.advertising
;
4642 tgtadv
= ethtool_adv_to_mii_adv_t(advertising
) & ADVERTISE_ALL
;
4644 advmsk
= ADVERTISE_ALL
;
4645 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
4646 tgtadv
|= mii_advertise_flowctrl(tp
->link_config
.flowctrl
);
4647 advmsk
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4650 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
4653 if ((*lcladv
& advmsk
) != tgtadv
)
4656 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
4659 tgtadv
= ethtool_adv_to_mii_ctrl1000_t(advertising
);
4661 if (tg3_readphy(tp
, MII_CTRL1000
, &tg3_ctrl
))
4665 (tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
||
4666 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B0
)) {
4667 tgtadv
|= CTL1000_AS_MASTER
| CTL1000_ENABLE_MASTER
;
4668 tg3_ctrl
&= (ADVERTISE_1000HALF
| ADVERTISE_1000FULL
|
4669 CTL1000_AS_MASTER
| CTL1000_ENABLE_MASTER
);
4671 tg3_ctrl
&= (ADVERTISE_1000HALF
| ADVERTISE_1000FULL
);
4674 if (tg3_ctrl
!= tgtadv
)
4681 static bool tg3_phy_copper_fetch_rmtadv(struct tg3
*tp
, u32
*rmtadv
)
4685 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
4688 if (tg3_readphy(tp
, MII_STAT1000
, &val
))
4691 lpeth
= mii_stat1000_to_ethtool_lpa_t(val
);
4694 if (tg3_readphy(tp
, MII_LPA
, rmtadv
))
4697 lpeth
|= mii_lpa_to_ethtool_lpa_t(*rmtadv
);
4698 tp
->link_config
.rmt_adv
= lpeth
;
4703 static bool tg3_test_and_report_link_chg(struct tg3
*tp
, bool curr_link_up
)
4705 if (curr_link_up
!= tp
->link_up
) {
4707 netif_carrier_on(tp
->dev
);
4709 netif_carrier_off(tp
->dev
);
4710 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
4711 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4714 tg3_link_report(tp
);
4721 static void tg3_clear_mac_status(struct tg3
*tp
)
4726 MAC_STATUS_SYNC_CHANGED
|
4727 MAC_STATUS_CFG_CHANGED
|
4728 MAC_STATUS_MI_COMPLETION
|
4729 MAC_STATUS_LNKSTATE_CHANGED
);
4733 static void tg3_setup_eee(struct tg3
*tp
)
4737 val
= TG3_CPMU_EEE_LNKIDL_PCIE_NL0
|
4738 TG3_CPMU_EEE_LNKIDL_UART_IDL
;
4739 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_57765_A0
)
4740 val
|= TG3_CPMU_EEE_LNKIDL_APE_TX_MT
;
4742 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL
, val
);
4744 tw32_f(TG3_CPMU_EEE_CTRL
,
4745 TG3_CPMU_EEE_CTRL_EXIT_20_1_US
);
4747 val
= TG3_CPMU_EEEMD_ERLY_L1_XIT_DET
|
4748 (tp
->eee
.tx_lpi_enabled
? TG3_CPMU_EEEMD_LPI_IN_TX
: 0) |
4749 TG3_CPMU_EEEMD_LPI_IN_RX
|
4750 TG3_CPMU_EEEMD_EEE_ENABLE
;
4752 if (tg3_asic_rev(tp
) != ASIC_REV_5717
)
4753 val
|= TG3_CPMU_EEEMD_SND_IDX_DET_EN
;
4755 if (tg3_flag(tp
, ENABLE_APE
))
4756 val
|= TG3_CPMU_EEEMD_APE_TX_DET_EN
;
4758 tw32_f(TG3_CPMU_EEE_MODE
, tp
->eee
.eee_enabled
? val
: 0);
4760 tw32_f(TG3_CPMU_EEE_DBTMR1
,
4761 TG3_CPMU_DBTMR1_PCIEXIT_2047US
|
4762 (tp
->eee
.tx_lpi_timer
& 0xffff));
4764 tw32_f(TG3_CPMU_EEE_DBTMR2
,
4765 TG3_CPMU_DBTMR2_APE_TX_2047US
|
4766 TG3_CPMU_DBTMR2_TXIDXEQ_2047US
);
4769 static int tg3_setup_copper_phy(struct tg3
*tp
, bool force_reset
)
4771 bool current_link_up
;
4773 u32 lcl_adv
, rmt_adv
;
4778 tg3_clear_mac_status(tp
);
4780 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
4782 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
4786 tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_PWRCTL
, 0);
4788 /* Some third-party PHYs need to be reset on link going
4791 if ((tg3_asic_rev(tp
) == ASIC_REV_5703
||
4792 tg3_asic_rev(tp
) == ASIC_REV_5704
||
4793 tg3_asic_rev(tp
) == ASIC_REV_5705
) &&
4795 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4796 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
4797 !(bmsr
& BMSR_LSTATUS
))
4803 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
4804 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4805 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
4806 !tg3_flag(tp
, INIT_COMPLETE
))
4809 if (!(bmsr
& BMSR_LSTATUS
)) {
4810 err
= tg3_init_5401phy_dsp(tp
);
4814 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4815 for (i
= 0; i
< 1000; i
++) {
4817 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
4818 (bmsr
& BMSR_LSTATUS
)) {
4824 if ((tp
->phy_id
& TG3_PHY_ID_REV_MASK
) ==
4825 TG3_PHY_REV_BCM5401_B0
&&
4826 !(bmsr
& BMSR_LSTATUS
) &&
4827 tp
->link_config
.active_speed
== SPEED_1000
) {
4828 err
= tg3_phy_reset(tp
);
4830 err
= tg3_init_5401phy_dsp(tp
);
4835 } else if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
||
4836 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B0
) {
4837 /* 5701 {A0,B0} CRC bug workaround */
4838 tg3_writephy(tp
, 0x15, 0x0a75);
4839 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8c68);
4840 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
4841 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8c68);
4844 /* Clear pending interrupts... */
4845 tg3_readphy(tp
, MII_TG3_ISTAT
, &val
);
4846 tg3_readphy(tp
, MII_TG3_ISTAT
, &val
);
4848 if (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
)
4849 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
4850 else if (!(tp
->phy_flags
& TG3_PHYFLG_IS_FET
))
4851 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
4853 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
4854 tg3_asic_rev(tp
) == ASIC_REV_5701
) {
4855 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
4856 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
4857 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
4859 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
4862 current_link_up
= false;
4863 current_speed
= SPEED_UNKNOWN
;
4864 current_duplex
= DUPLEX_UNKNOWN
;
4865 tp
->phy_flags
&= ~TG3_PHYFLG_MDIX_STATE
;
4866 tp
->link_config
.rmt_adv
= 0;
4868 if (tp
->phy_flags
& TG3_PHYFLG_CAPACITIVE_COUPLING
) {
4869 err
= tg3_phy_auxctl_read(tp
,
4870 MII_TG3_AUXCTL_SHDWSEL_MISCTEST
,
4872 if (!err
&& !(val
& (1 << 10))) {
4873 tg3_phy_auxctl_write(tp
,
4874 MII_TG3_AUXCTL_SHDWSEL_MISCTEST
,
4881 for (i
= 0; i
< 100; i
++) {
4882 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4883 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
4884 (bmsr
& BMSR_LSTATUS
))
4889 if (bmsr
& BMSR_LSTATUS
) {
4892 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
4893 for (i
= 0; i
< 2000; i
++) {
4895 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
4900 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
4905 for (i
= 0; i
< 200; i
++) {
4906 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4907 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
4909 if (bmcr
&& bmcr
!= 0x7fff)
4917 tp
->link_config
.active_speed
= current_speed
;
4918 tp
->link_config
.active_duplex
= current_duplex
;
4920 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
4921 bool eee_config_ok
= tg3_phy_eee_config_ok(tp
);
4923 if ((bmcr
& BMCR_ANENABLE
) &&
4925 tg3_phy_copper_an_config_ok(tp
, &lcl_adv
) &&
4926 tg3_phy_copper_fetch_rmtadv(tp
, &rmt_adv
))
4927 current_link_up
= true;
4929 /* EEE settings changes take effect only after a phy
4930 * reset. If we have skipped a reset due to Link Flap
4931 * Avoidance being enabled, do it now.
4933 if (!eee_config_ok
&&
4934 (tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
) &&
4940 if (!(bmcr
& BMCR_ANENABLE
) &&
4941 tp
->link_config
.speed
== current_speed
&&
4942 tp
->link_config
.duplex
== current_duplex
) {
4943 current_link_up
= true;
4947 if (current_link_up
&&
4948 tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
4951 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
4952 reg
= MII_TG3_FET_GEN_STAT
;
4953 bit
= MII_TG3_FET_GEN_STAT_MDIXSTAT
;
4955 reg
= MII_TG3_EXT_STAT
;
4956 bit
= MII_TG3_EXT_STAT_MDIX
;
4959 if (!tg3_readphy(tp
, reg
, &val
) && (val
& bit
))
4960 tp
->phy_flags
|= TG3_PHYFLG_MDIX_STATE
;
4962 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
4967 if (!current_link_up
|| (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
4968 tg3_phy_copper_begin(tp
);
4970 if (tg3_flag(tp
, ROBOSWITCH
)) {
4971 current_link_up
= true;
4972 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4973 current_speed
= SPEED_1000
;
4974 current_duplex
= DUPLEX_FULL
;
4975 tp
->link_config
.active_speed
= current_speed
;
4976 tp
->link_config
.active_duplex
= current_duplex
;
4979 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4980 if ((!tg3_readphy(tp
, MII_BMSR
, &bmsr
) && (bmsr
& BMSR_LSTATUS
)) ||
4981 (tp
->mac_mode
& MAC_MODE_PORT_INT_LPBACK
))
4982 current_link_up
= true;
4985 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
4986 if (current_link_up
) {
4987 if (tp
->link_config
.active_speed
== SPEED_100
||
4988 tp
->link_config
.active_speed
== SPEED_10
)
4989 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
4991 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
4992 } else if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
)
4993 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
4995 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
4997 /* In order for the 5750 core in BCM4785 chip to work properly
4998 * in RGMII mode, the Led Control Register must be set up.
5000 if (tg3_flag(tp
, RGMII_MODE
)) {
5001 u32 led_ctrl
= tr32(MAC_LED_CTRL
);
5002 led_ctrl
&= ~(LED_CTRL_1000MBPS_ON
| LED_CTRL_100MBPS_ON
);
5004 if (tp
->link_config
.active_speed
== SPEED_10
)
5005 led_ctrl
|= LED_CTRL_LNKLED_OVERRIDE
;
5006 else if (tp
->link_config
.active_speed
== SPEED_100
)
5007 led_ctrl
|= (LED_CTRL_LNKLED_OVERRIDE
|
5008 LED_CTRL_100MBPS_ON
);
5009 else if (tp
->link_config
.active_speed
== SPEED_1000
)
5010 led_ctrl
|= (LED_CTRL_LNKLED_OVERRIDE
|
5011 LED_CTRL_1000MBPS_ON
);
5013 tw32(MAC_LED_CTRL
, led_ctrl
);
5017 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
5018 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
5019 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
5021 if (tg3_asic_rev(tp
) == ASIC_REV_5700
) {
5022 if (current_link_up
&&
5023 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
5024 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
5026 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
5029 /* ??? Without this setting Netgear GA302T PHY does not
5030 * ??? send/receive packets...
5032 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
&&
5033 tg3_chip_rev_id(tp
) == CHIPREV_ID_5700_ALTIMA
) {
5034 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
5035 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
5039 tw32_f(MAC_MODE
, tp
->mac_mode
);
5042 tg3_phy_eee_adjust(tp
, current_link_up
);
5044 if (tg3_flag(tp
, USE_LINKCHG_REG
)) {
5045 /* Polled via timer. */
5046 tw32_f(MAC_EVENT
, 0);
5048 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
5052 if (tg3_asic_rev(tp
) == ASIC_REV_5700
&&
5054 tp
->link_config
.active_speed
== SPEED_1000
&&
5055 (tg3_flag(tp
, PCIX_MODE
) || tg3_flag(tp
, PCI_HIGH_SPEED
))) {
5058 (MAC_STATUS_SYNC_CHANGED
|
5059 MAC_STATUS_CFG_CHANGED
));
5062 NIC_SRAM_FIRMWARE_MBOX
,
5063 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
5066 /* Prevent send BD corruption. */
5067 if (tg3_flag(tp
, CLKREQ_BUG
)) {
5068 if (tp
->link_config
.active_speed
== SPEED_100
||
5069 tp
->link_config
.active_speed
== SPEED_10
)
5070 pcie_capability_clear_word(tp
->pdev
, PCI_EXP_LNKCTL
,
5071 PCI_EXP_LNKCTL_CLKREQ_EN
);
5073 pcie_capability_set_word(tp
->pdev
, PCI_EXP_LNKCTL
,
5074 PCI_EXP_LNKCTL_CLKREQ_EN
);
5077 tg3_test_and_report_link_chg(tp
, current_link_up
);
5082 struct tg3_fiber_aneginfo
{
5084 #define ANEG_STATE_UNKNOWN 0
5085 #define ANEG_STATE_AN_ENABLE 1
5086 #define ANEG_STATE_RESTART_INIT 2
5087 #define ANEG_STATE_RESTART 3
5088 #define ANEG_STATE_DISABLE_LINK_OK 4
5089 #define ANEG_STATE_ABILITY_DETECT_INIT 5
5090 #define ANEG_STATE_ABILITY_DETECT 6
5091 #define ANEG_STATE_ACK_DETECT_INIT 7
5092 #define ANEG_STATE_ACK_DETECT 8
5093 #define ANEG_STATE_COMPLETE_ACK_INIT 9
5094 #define ANEG_STATE_COMPLETE_ACK 10
5095 #define ANEG_STATE_IDLE_DETECT_INIT 11
5096 #define ANEG_STATE_IDLE_DETECT 12
5097 #define ANEG_STATE_LINK_OK 13
5098 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5099 #define ANEG_STATE_NEXT_PAGE_WAIT 15
5102 #define MR_AN_ENABLE 0x00000001
5103 #define MR_RESTART_AN 0x00000002
5104 #define MR_AN_COMPLETE 0x00000004
5105 #define MR_PAGE_RX 0x00000008
5106 #define MR_NP_LOADED 0x00000010
5107 #define MR_TOGGLE_TX 0x00000020
5108 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5109 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5110 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5111 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5112 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5113 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5114 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5115 #define MR_TOGGLE_RX 0x00002000
5116 #define MR_NP_RX 0x00004000
5118 #define MR_LINK_OK 0x80000000
5120 unsigned long link_time
, cur_time
;
5122 u32 ability_match_cfg
;
5123 int ability_match_count
;
5125 char ability_match
, idle_match
, ack_match
;
5127 u32 txconfig
, rxconfig
;
5128 #define ANEG_CFG_NP 0x00000080
5129 #define ANEG_CFG_ACK 0x00000040
5130 #define ANEG_CFG_RF2 0x00000020
5131 #define ANEG_CFG_RF1 0x00000010
5132 #define ANEG_CFG_PS2 0x00000001
5133 #define ANEG_CFG_PS1 0x00008000
5134 #define ANEG_CFG_HD 0x00004000
5135 #define ANEG_CFG_FD 0x00002000
5136 #define ANEG_CFG_INVAL 0x00001f06
5141 #define ANEG_TIMER_ENAB 2
5142 #define ANEG_FAILED -1
5144 #define ANEG_STATE_SETTLE_TIME 10000
5146 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
5147 struct tg3_fiber_aneginfo
*ap
)
5150 unsigned long delta
;
5154 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
5158 ap
->ability_match_cfg
= 0;
5159 ap
->ability_match_count
= 0;
5160 ap
->ability_match
= 0;
5166 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
5167 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
5169 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
5170 ap
->ability_match_cfg
= rx_cfg_reg
;
5171 ap
->ability_match
= 0;
5172 ap
->ability_match_count
= 0;
5174 if (++ap
->ability_match_count
> 1) {
5175 ap
->ability_match
= 1;
5176 ap
->ability_match_cfg
= rx_cfg_reg
;
5179 if (rx_cfg_reg
& ANEG_CFG_ACK
)
5187 ap
->ability_match_cfg
= 0;
5188 ap
->ability_match_count
= 0;
5189 ap
->ability_match
= 0;
5195 ap
->rxconfig
= rx_cfg_reg
;
5198 switch (ap
->state
) {
5199 case ANEG_STATE_UNKNOWN
:
5200 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
5201 ap
->state
= ANEG_STATE_AN_ENABLE
;
5204 case ANEG_STATE_AN_ENABLE
:
5205 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
5206 if (ap
->flags
& MR_AN_ENABLE
) {
5209 ap
->ability_match_cfg
= 0;
5210 ap
->ability_match_count
= 0;
5211 ap
->ability_match
= 0;
5215 ap
->state
= ANEG_STATE_RESTART_INIT
;
5217 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
5221 case ANEG_STATE_RESTART_INIT
:
5222 ap
->link_time
= ap
->cur_time
;
5223 ap
->flags
&= ~(MR_NP_LOADED
);
5225 tw32(MAC_TX_AUTO_NEG
, 0);
5226 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
5227 tw32_f(MAC_MODE
, tp
->mac_mode
);
5230 ret
= ANEG_TIMER_ENAB
;
5231 ap
->state
= ANEG_STATE_RESTART
;
5234 case ANEG_STATE_RESTART
:
5235 delta
= ap
->cur_time
- ap
->link_time
;
5236 if (delta
> ANEG_STATE_SETTLE_TIME
)
5237 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
5239 ret
= ANEG_TIMER_ENAB
;
5242 case ANEG_STATE_DISABLE_LINK_OK
:
5246 case ANEG_STATE_ABILITY_DETECT_INIT
:
5247 ap
->flags
&= ~(MR_TOGGLE_TX
);
5248 ap
->txconfig
= ANEG_CFG_FD
;
5249 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
5250 if (flowctrl
& ADVERTISE_1000XPAUSE
)
5251 ap
->txconfig
|= ANEG_CFG_PS1
;
5252 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
5253 ap
->txconfig
|= ANEG_CFG_PS2
;
5254 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
5255 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
5256 tw32_f(MAC_MODE
, tp
->mac_mode
);
5259 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
5262 case ANEG_STATE_ABILITY_DETECT
:
5263 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0)
5264 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
5267 case ANEG_STATE_ACK_DETECT_INIT
:
5268 ap
->txconfig
|= ANEG_CFG_ACK
;
5269 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
5270 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
5271 tw32_f(MAC_MODE
, tp
->mac_mode
);
5274 ap
->state
= ANEG_STATE_ACK_DETECT
;
5277 case ANEG_STATE_ACK_DETECT
:
5278 if (ap
->ack_match
!= 0) {
5279 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
5280 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
5281 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
5283 ap
->state
= ANEG_STATE_AN_ENABLE
;
5285 } else if (ap
->ability_match
!= 0 &&
5286 ap
->rxconfig
== 0) {
5287 ap
->state
= ANEG_STATE_AN_ENABLE
;
5291 case ANEG_STATE_COMPLETE_ACK_INIT
:
5292 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
5296 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
5297 MR_LP_ADV_HALF_DUPLEX
|
5298 MR_LP_ADV_SYM_PAUSE
|
5299 MR_LP_ADV_ASYM_PAUSE
|
5300 MR_LP_ADV_REMOTE_FAULT1
|
5301 MR_LP_ADV_REMOTE_FAULT2
|
5302 MR_LP_ADV_NEXT_PAGE
|
5305 if (ap
->rxconfig
& ANEG_CFG_FD
)
5306 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
5307 if (ap
->rxconfig
& ANEG_CFG_HD
)
5308 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
5309 if (ap
->rxconfig
& ANEG_CFG_PS1
)
5310 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
5311 if (ap
->rxconfig
& ANEG_CFG_PS2
)
5312 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
5313 if (ap
->rxconfig
& ANEG_CFG_RF1
)
5314 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
5315 if (ap
->rxconfig
& ANEG_CFG_RF2
)
5316 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
5317 if (ap
->rxconfig
& ANEG_CFG_NP
)
5318 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
5320 ap
->link_time
= ap
->cur_time
;
5322 ap
->flags
^= (MR_TOGGLE_TX
);
5323 if (ap
->rxconfig
& 0x0008)
5324 ap
->flags
|= MR_TOGGLE_RX
;
5325 if (ap
->rxconfig
& ANEG_CFG_NP
)
5326 ap
->flags
|= MR_NP_RX
;
5327 ap
->flags
|= MR_PAGE_RX
;
5329 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
5330 ret
= ANEG_TIMER_ENAB
;
5333 case ANEG_STATE_COMPLETE_ACK
:
5334 if (ap
->ability_match
!= 0 &&
5335 ap
->rxconfig
== 0) {
5336 ap
->state
= ANEG_STATE_AN_ENABLE
;
5339 delta
= ap
->cur_time
- ap
->link_time
;
5340 if (delta
> ANEG_STATE_SETTLE_TIME
) {
5341 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
5342 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
5344 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
5345 !(ap
->flags
& MR_NP_RX
)) {
5346 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
5354 case ANEG_STATE_IDLE_DETECT_INIT
:
5355 ap
->link_time
= ap
->cur_time
;
5356 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
5357 tw32_f(MAC_MODE
, tp
->mac_mode
);
5360 ap
->state
= ANEG_STATE_IDLE_DETECT
;
5361 ret
= ANEG_TIMER_ENAB
;
5364 case ANEG_STATE_IDLE_DETECT
:
5365 if (ap
->ability_match
!= 0 &&
5366 ap
->rxconfig
== 0) {
5367 ap
->state
= ANEG_STATE_AN_ENABLE
;
5370 delta
= ap
->cur_time
- ap
->link_time
;
5371 if (delta
> ANEG_STATE_SETTLE_TIME
) {
5372 /* XXX another gem from the Broadcom driver :( */
5373 ap
->state
= ANEG_STATE_LINK_OK
;
5377 case ANEG_STATE_LINK_OK
:
5378 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
5382 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
5383 /* ??? unimplemented */
5386 case ANEG_STATE_NEXT_PAGE_WAIT
:
5387 /* ??? unimplemented */
5398 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
5401 struct tg3_fiber_aneginfo aninfo
;
5402 int status
= ANEG_FAILED
;
5406 tw32_f(MAC_TX_AUTO_NEG
, 0);
5408 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
5409 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
5412 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
5415 memset(&aninfo
, 0, sizeof(aninfo
));
5416 aninfo
.flags
|= MR_AN_ENABLE
;
5417 aninfo
.state
= ANEG_STATE_UNKNOWN
;
5418 aninfo
.cur_time
= 0;
5420 while (++tick
< 195000) {
5421 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
5422 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
5428 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
5429 tw32_f(MAC_MODE
, tp
->mac_mode
);
5432 *txflags
= aninfo
.txconfig
;
5433 *rxflags
= aninfo
.flags
;
5435 if (status
== ANEG_DONE
&&
5436 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
5437 MR_LP_ADV_FULL_DUPLEX
)))
5443 static void tg3_init_bcm8002(struct tg3
*tp
)
5445 u32 mac_status
= tr32(MAC_STATUS
);
5448 /* Reset when initting first time or we have a link. */
5449 if (tg3_flag(tp
, INIT_COMPLETE
) &&
5450 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
5453 /* Set PLL lock range. */
5454 tg3_writephy(tp
, 0x16, 0x8007);
5457 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
5459 /* Wait for reset to complete. */
5460 /* XXX schedule_timeout() ... */
5461 for (i
= 0; i
< 500; i
++)
5464 /* Config mode; select PMA/Ch 1 regs. */
5465 tg3_writephy(tp
, 0x10, 0x8411);
5467 /* Enable auto-lock and comdet, select txclk for tx. */
5468 tg3_writephy(tp
, 0x11, 0x0a10);
5470 tg3_writephy(tp
, 0x18, 0x00a0);
5471 tg3_writephy(tp
, 0x16, 0x41ff);
5473 /* Assert and deassert POR. */
5474 tg3_writephy(tp
, 0x13, 0x0400);
5476 tg3_writephy(tp
, 0x13, 0x0000);
5478 tg3_writephy(tp
, 0x11, 0x0a50);
5480 tg3_writephy(tp
, 0x11, 0x0a10);
5482 /* Wait for signal to stabilize */
5483 /* XXX schedule_timeout() ... */
5484 for (i
= 0; i
< 15000; i
++)
5487 /* Deselect the channel register so we can read the PHYID
5490 tg3_writephy(tp
, 0x10, 0x8011);
5493 static bool tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
5496 bool current_link_up
;
5497 u32 sg_dig_ctrl
, sg_dig_status
;
5498 u32 serdes_cfg
, expected_sg_dig_ctrl
;
5499 int workaround
, port_a
;
5502 expected_sg_dig_ctrl
= 0;
5505 current_link_up
= false;
5507 if (tg3_chip_rev_id(tp
) != CHIPREV_ID_5704_A0
&&
5508 tg3_chip_rev_id(tp
) != CHIPREV_ID_5704_A1
) {
5510 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
5513 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5514 /* preserve bits 20-23 for voltage regulator */
5515 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
5518 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
5520 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
5521 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
5523 u32 val
= serdes_cfg
;
5529 tw32_f(MAC_SERDES_CFG
, val
);
5532 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
5534 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
5535 tg3_setup_flow_control(tp
, 0, 0);
5536 current_link_up
= true;
5541 /* Want auto-negotiation. */
5542 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
5544 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
5545 if (flowctrl
& ADVERTISE_1000XPAUSE
)
5546 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
5547 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
5548 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
5550 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
5551 if ((tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
) &&
5552 tp
->serdes_counter
&&
5553 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
5554 MAC_STATUS_RCVD_CFG
)) ==
5555 MAC_STATUS_PCS_SYNCED
)) {
5556 tp
->serdes_counter
--;
5557 current_link_up
= true;
5562 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
5563 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
5565 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
5567 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
5568 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
5569 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
5570 MAC_STATUS_SIGNAL_DET
)) {
5571 sg_dig_status
= tr32(SG_DIG_STATUS
);
5572 mac_status
= tr32(MAC_STATUS
);
5574 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
5575 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
5576 u32 local_adv
= 0, remote_adv
= 0;
5578 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
5579 local_adv
|= ADVERTISE_1000XPAUSE
;
5580 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
5581 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
5583 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
5584 remote_adv
|= LPA_1000XPAUSE
;
5585 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
5586 remote_adv
|= LPA_1000XPAUSE_ASYM
;
5588 tp
->link_config
.rmt_adv
=
5589 mii_adv_to_ethtool_adv_x(remote_adv
);
5591 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
5592 current_link_up
= true;
5593 tp
->serdes_counter
= 0;
5594 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
5595 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
5596 if (tp
->serdes_counter
)
5597 tp
->serdes_counter
--;
5600 u32 val
= serdes_cfg
;
5607 tw32_f(MAC_SERDES_CFG
, val
);
5610 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
5613 /* Link parallel detection - link is up */
5614 /* only if we have PCS_SYNC and not */
5615 /* receiving config code words */
5616 mac_status
= tr32(MAC_STATUS
);
5617 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
5618 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
5619 tg3_setup_flow_control(tp
, 0, 0);
5620 current_link_up
= true;
5622 TG3_PHYFLG_PARALLEL_DETECT
;
5623 tp
->serdes_counter
=
5624 SERDES_PARALLEL_DET_TIMEOUT
;
5626 goto restart_autoneg
;
5630 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
5631 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
5635 return current_link_up
;
5638 static bool tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
5640 bool current_link_up
= false;
5642 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
5645 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
5646 u32 txflags
, rxflags
;
5649 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
5650 u32 local_adv
= 0, remote_adv
= 0;
5652 if (txflags
& ANEG_CFG_PS1
)
5653 local_adv
|= ADVERTISE_1000XPAUSE
;
5654 if (txflags
& ANEG_CFG_PS2
)
5655 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
5657 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
5658 remote_adv
|= LPA_1000XPAUSE
;
5659 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
5660 remote_adv
|= LPA_1000XPAUSE_ASYM
;
5662 tp
->link_config
.rmt_adv
=
5663 mii_adv_to_ethtool_adv_x(remote_adv
);
5665 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
5667 current_link_up
= true;
5669 for (i
= 0; i
< 30; i
++) {
5672 (MAC_STATUS_SYNC_CHANGED
|
5673 MAC_STATUS_CFG_CHANGED
));
5675 if ((tr32(MAC_STATUS
) &
5676 (MAC_STATUS_SYNC_CHANGED
|
5677 MAC_STATUS_CFG_CHANGED
)) == 0)
5681 mac_status
= tr32(MAC_STATUS
);
5682 if (!current_link_up
&&
5683 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
5684 !(mac_status
& MAC_STATUS_RCVD_CFG
))
5685 current_link_up
= true;
5687 tg3_setup_flow_control(tp
, 0, 0);
5689 /* Forcing 1000FD link up. */
5690 current_link_up
= true;
5692 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
5695 tw32_f(MAC_MODE
, tp
->mac_mode
);
5700 return current_link_up
;
5703 static int tg3_setup_fiber_phy(struct tg3
*tp
, bool force_reset
)
5706 u16 orig_active_speed
;
5707 u8 orig_active_duplex
;
5709 bool current_link_up
;
5712 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
5713 orig_active_speed
= tp
->link_config
.active_speed
;
5714 orig_active_duplex
= tp
->link_config
.active_duplex
;
5716 if (!tg3_flag(tp
, HW_AUTONEG
) &&
5718 tg3_flag(tp
, INIT_COMPLETE
)) {
5719 mac_status
= tr32(MAC_STATUS
);
5720 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
5721 MAC_STATUS_SIGNAL_DET
|
5722 MAC_STATUS_CFG_CHANGED
|
5723 MAC_STATUS_RCVD_CFG
);
5724 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
5725 MAC_STATUS_SIGNAL_DET
)) {
5726 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
5727 MAC_STATUS_CFG_CHANGED
));
5732 tw32_f(MAC_TX_AUTO_NEG
, 0);
5734 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
5735 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
5736 tw32_f(MAC_MODE
, tp
->mac_mode
);
5739 if (tp
->phy_id
== TG3_PHY_ID_BCM8002
)
5740 tg3_init_bcm8002(tp
);
5742 /* Enable link change event even when serdes polling. */
5743 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
5746 current_link_up
= false;
5747 tp
->link_config
.rmt_adv
= 0;
5748 mac_status
= tr32(MAC_STATUS
);
5750 if (tg3_flag(tp
, HW_AUTONEG
))
5751 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
5753 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
5755 tp
->napi
[0].hw_status
->status
=
5756 (SD_STATUS_UPDATED
|
5757 (tp
->napi
[0].hw_status
->status
& ~SD_STATUS_LINK_CHG
));
5759 for (i
= 0; i
< 100; i
++) {
5760 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
5761 MAC_STATUS_CFG_CHANGED
));
5763 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
5764 MAC_STATUS_CFG_CHANGED
|
5765 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
5769 mac_status
= tr32(MAC_STATUS
);
5770 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
5771 current_link_up
= false;
5772 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
5773 tp
->serdes_counter
== 0) {
5774 tw32_f(MAC_MODE
, (tp
->mac_mode
|
5775 MAC_MODE_SEND_CONFIGS
));
5777 tw32_f(MAC_MODE
, tp
->mac_mode
);
5781 if (current_link_up
) {
5782 tp
->link_config
.active_speed
= SPEED_1000
;
5783 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
5784 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
5785 LED_CTRL_LNKLED_OVERRIDE
|
5786 LED_CTRL_1000MBPS_ON
));
5788 tp
->link_config
.active_speed
= SPEED_UNKNOWN
;
5789 tp
->link_config
.active_duplex
= DUPLEX_UNKNOWN
;
5790 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
5791 LED_CTRL_LNKLED_OVERRIDE
|
5792 LED_CTRL_TRAFFIC_OVERRIDE
));
5795 if (!tg3_test_and_report_link_chg(tp
, current_link_up
)) {
5796 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
5797 if (orig_pause_cfg
!= now_pause_cfg
||
5798 orig_active_speed
!= tp
->link_config
.active_speed
||
5799 orig_active_duplex
!= tp
->link_config
.active_duplex
)
5800 tg3_link_report(tp
);
5806 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, bool force_reset
)
5810 u16 current_speed
= SPEED_UNKNOWN
;
5811 u8 current_duplex
= DUPLEX_UNKNOWN
;
5812 bool current_link_up
= false;
5813 u32 local_adv
, remote_adv
, sgsr
;
5815 if ((tg3_asic_rev(tp
) == ASIC_REV_5719
||
5816 tg3_asic_rev(tp
) == ASIC_REV_5720
) &&
5817 !tg3_readphy(tp
, SERDES_TG3_1000X_STATUS
, &sgsr
) &&
5818 (sgsr
& SERDES_TG3_SGMII_MODE
)) {
5823 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
5825 if (!(sgsr
& SERDES_TG3_LINK_UP
)) {
5826 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
5828 current_link_up
= true;
5829 if (sgsr
& SERDES_TG3_SPEED_1000
) {
5830 current_speed
= SPEED_1000
;
5831 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
5832 } else if (sgsr
& SERDES_TG3_SPEED_100
) {
5833 current_speed
= SPEED_100
;
5834 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
5836 current_speed
= SPEED_10
;
5837 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
5840 if (sgsr
& SERDES_TG3_FULL_DUPLEX
)
5841 current_duplex
= DUPLEX_FULL
;
5843 current_duplex
= DUPLEX_HALF
;
5846 tw32_f(MAC_MODE
, tp
->mac_mode
);
5849 tg3_clear_mac_status(tp
);
5851 goto fiber_setup_done
;
5854 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
5855 tw32_f(MAC_MODE
, tp
->mac_mode
);
5858 tg3_clear_mac_status(tp
);
5863 tp
->link_config
.rmt_adv
= 0;
5865 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
5866 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
5867 if (tg3_asic_rev(tp
) == ASIC_REV_5714
) {
5868 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
5869 bmsr
|= BMSR_LSTATUS
;
5871 bmsr
&= ~BMSR_LSTATUS
;
5874 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
5876 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
5877 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
)) {
5878 /* do nothing, just check for link up at the end */
5879 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
5882 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
5883 newadv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
5884 ADVERTISE_1000XPAUSE
|
5885 ADVERTISE_1000XPSE_ASYM
|
5888 newadv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
5889 newadv
|= ethtool_adv_to_mii_adv_x(tp
->link_config
.advertising
);
5891 if ((newadv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
5892 tg3_writephy(tp
, MII_ADVERTISE
, newadv
);
5893 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
5894 tg3_writephy(tp
, MII_BMCR
, bmcr
);
5896 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
5897 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
5898 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
5905 bmcr
&= ~BMCR_SPEED1000
;
5906 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
5908 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
5909 new_bmcr
|= BMCR_FULLDPLX
;
5911 if (new_bmcr
!= bmcr
) {
5912 /* BMCR_SPEED1000 is a reserved bit that needs
5913 * to be set on write.
5915 new_bmcr
|= BMCR_SPEED1000
;
5917 /* Force a linkdown */
5921 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
5922 adv
&= ~(ADVERTISE_1000XFULL
|
5923 ADVERTISE_1000XHALF
|
5925 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
5926 tg3_writephy(tp
, MII_BMCR
, bmcr
|
5930 tg3_carrier_off(tp
);
5932 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
5934 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
5935 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
5936 if (tg3_asic_rev(tp
) == ASIC_REV_5714
) {
5937 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
5938 bmsr
|= BMSR_LSTATUS
;
5940 bmsr
&= ~BMSR_LSTATUS
;
5942 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
5946 if (bmsr
& BMSR_LSTATUS
) {
5947 current_speed
= SPEED_1000
;
5948 current_link_up
= true;
5949 if (bmcr
& BMCR_FULLDPLX
)
5950 current_duplex
= DUPLEX_FULL
;
5952 current_duplex
= DUPLEX_HALF
;
5957 if (bmcr
& BMCR_ANENABLE
) {
5960 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
5961 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
5962 common
= local_adv
& remote_adv
;
5963 if (common
& (ADVERTISE_1000XHALF
|
5964 ADVERTISE_1000XFULL
)) {
5965 if (common
& ADVERTISE_1000XFULL
)
5966 current_duplex
= DUPLEX_FULL
;
5968 current_duplex
= DUPLEX_HALF
;
5970 tp
->link_config
.rmt_adv
=
5971 mii_adv_to_ethtool_adv_x(remote_adv
);
5972 } else if (!tg3_flag(tp
, 5780_CLASS
)) {
5973 /* Link is up via parallel detect */
5975 current_link_up
= false;
5981 if (current_link_up
&& current_duplex
== DUPLEX_FULL
)
5982 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
5984 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
5985 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
5986 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
5988 tw32_f(MAC_MODE
, tp
->mac_mode
);
5991 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
5993 tp
->link_config
.active_speed
= current_speed
;
5994 tp
->link_config
.active_duplex
= current_duplex
;
5996 tg3_test_and_report_link_chg(tp
, current_link_up
);
6000 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
6002 if (tp
->serdes_counter
) {
6003 /* Give autoneg time to complete. */
6004 tp
->serdes_counter
--;
6009 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
6012 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
6013 if (bmcr
& BMCR_ANENABLE
) {
6016 /* Select shadow register 0x1f */
6017 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x7c00);
6018 tg3_readphy(tp
, MII_TG3_MISC_SHDW
, &phy1
);
6020 /* Select expansion interrupt status register */
6021 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
6022 MII_TG3_DSP_EXP1_INT_STAT
);
6023 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
6024 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
6026 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
6027 /* We have signal detect and not receiving
6028 * config code words, link is up by parallel
6032 bmcr
&= ~BMCR_ANENABLE
;
6033 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
6034 tg3_writephy(tp
, MII_BMCR
, bmcr
);
6035 tp
->phy_flags
|= TG3_PHYFLG_PARALLEL_DETECT
;
6038 } else if (tp
->link_up
&&
6039 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
6040 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
)) {
6043 /* Select expansion interrupt status register */
6044 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
6045 MII_TG3_DSP_EXP1_INT_STAT
);
6046 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
6050 /* Config code words received, turn on autoneg. */
6051 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
6052 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
6054 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
6060 static int tg3_setup_phy(struct tg3
*tp
, bool force_reset
)
6065 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
6066 err
= tg3_setup_fiber_phy(tp
, force_reset
);
6067 else if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
6068 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
6070 err
= tg3_setup_copper_phy(tp
, force_reset
);
6072 if (tg3_chip_rev(tp
) == CHIPREV_5784_AX
) {
6075 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
6076 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
6078 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
6083 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
6084 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
6085 tw32(GRC_MISC_CFG
, val
);
6088 val
= (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
6089 (6 << TX_LENGTHS_IPG_SHIFT
);
6090 if (tg3_asic_rev(tp
) == ASIC_REV_5720
||
6091 tg3_asic_rev(tp
) == ASIC_REV_5762
)
6092 val
|= tr32(MAC_TX_LENGTHS
) &
6093 (TX_LENGTHS_JMB_FRM_LEN_MSK
|
6094 TX_LENGTHS_CNT_DWN_VAL_MSK
);
6096 if (tp
->link_config
.active_speed
== SPEED_1000
&&
6097 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
6098 tw32(MAC_TX_LENGTHS
, val
|
6099 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
));
6101 tw32(MAC_TX_LENGTHS
, val
|
6102 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
6104 if (!tg3_flag(tp
, 5705_PLUS
)) {
6106 tw32(HOSTCC_STAT_COAL_TICKS
,
6107 tp
->coal
.stats_block_coalesce_usecs
);
6109 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
6113 if (tg3_flag(tp
, ASPM_WORKAROUND
)) {
6114 val
= tr32(PCIE_PWR_MGMT_THRESH
);
6116 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
6119 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
6120 tw32(PCIE_PWR_MGMT_THRESH
, val
);
6126 /* tp->lock must be held */
6127 static u64
tg3_refclk_read(struct tg3
*tp
)
6129 u64 stamp
= tr32(TG3_EAV_REF_CLCK_LSB
);
6130 return stamp
| (u64
)tr32(TG3_EAV_REF_CLCK_MSB
) << 32;
6133 /* tp->lock must be held */
6134 static void tg3_refclk_write(struct tg3
*tp
, u64 newval
)
6136 u32 clock_ctl
= tr32(TG3_EAV_REF_CLCK_CTL
);
6138 tw32(TG3_EAV_REF_CLCK_CTL
, clock_ctl
| TG3_EAV_REF_CLCK_CTL_STOP
);
6139 tw32(TG3_EAV_REF_CLCK_LSB
, newval
& 0xffffffff);
6140 tw32(TG3_EAV_REF_CLCK_MSB
, newval
>> 32);
6141 tw32_f(TG3_EAV_REF_CLCK_CTL
, clock_ctl
| TG3_EAV_REF_CLCK_CTL_RESUME
);
6144 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
);
6145 static inline void tg3_full_unlock(struct tg3
*tp
);
6146 static int tg3_get_ts_info(struct net_device
*dev
, struct ethtool_ts_info
*info
)
6148 struct tg3
*tp
= netdev_priv(dev
);
6150 info
->so_timestamping
= SOF_TIMESTAMPING_TX_SOFTWARE
|
6151 SOF_TIMESTAMPING_RX_SOFTWARE
|
6152 SOF_TIMESTAMPING_SOFTWARE
;
6154 if (tg3_flag(tp
, PTP_CAPABLE
)) {
6155 info
->so_timestamping
|= SOF_TIMESTAMPING_TX_HARDWARE
|
6156 SOF_TIMESTAMPING_RX_HARDWARE
|
6157 SOF_TIMESTAMPING_RAW_HARDWARE
;
6161 info
->phc_index
= ptp_clock_index(tp
->ptp_clock
);
6163 info
->phc_index
= -1;
6165 info
->tx_types
= (1 << HWTSTAMP_TX_OFF
) | (1 << HWTSTAMP_TX_ON
);
6167 info
->rx_filters
= (1 << HWTSTAMP_FILTER_NONE
) |
6168 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT
) |
6169 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT
) |
6170 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT
);
6174 static int tg3_ptp_adjfreq(struct ptp_clock_info
*ptp
, s32 ppb
)
6176 struct tg3
*tp
= container_of(ptp
, struct tg3
, ptp_info
);
6177 bool neg_adj
= false;
6185 /* Frequency adjustment is performed using hardware with a 24 bit
6186 * accumulator and a programmable correction value. On each clk, the
6187 * correction value gets added to the accumulator and when it
6188 * overflows, the time counter is incremented/decremented.
6190 * So conversion from ppb to correction value is
6191 * ppb * (1 << 24) / 1000000000
6193 correction
= div_u64((u64
)ppb
* (1 << 24), 1000000000ULL) &
6194 TG3_EAV_REF_CLK_CORRECT_MASK
;
6196 tg3_full_lock(tp
, 0);
6199 tw32(TG3_EAV_REF_CLK_CORRECT_CTL
,
6200 TG3_EAV_REF_CLK_CORRECT_EN
|
6201 (neg_adj
? TG3_EAV_REF_CLK_CORRECT_NEG
: 0) | correction
);
6203 tw32(TG3_EAV_REF_CLK_CORRECT_CTL
, 0);
6205 tg3_full_unlock(tp
);
6210 static int tg3_ptp_adjtime(struct ptp_clock_info
*ptp
, s64 delta
)
6212 struct tg3
*tp
= container_of(ptp
, struct tg3
, ptp_info
);
6214 tg3_full_lock(tp
, 0);
6215 tp
->ptp_adjust
+= delta
;
6216 tg3_full_unlock(tp
);
6221 static int tg3_ptp_gettime(struct ptp_clock_info
*ptp
, struct timespec64
*ts
)
6224 struct tg3
*tp
= container_of(ptp
, struct tg3
, ptp_info
);
6226 tg3_full_lock(tp
, 0);
6227 ns
= tg3_refclk_read(tp
);
6228 ns
+= tp
->ptp_adjust
;
6229 tg3_full_unlock(tp
);
6231 *ts
= ns_to_timespec64(ns
);
6236 static int tg3_ptp_settime(struct ptp_clock_info
*ptp
,
6237 const struct timespec64
*ts
)
6240 struct tg3
*tp
= container_of(ptp
, struct tg3
, ptp_info
);
6242 ns
= timespec64_to_ns(ts
);
6244 tg3_full_lock(tp
, 0);
6245 tg3_refclk_write(tp
, ns
);
6247 tg3_full_unlock(tp
);
6252 static int tg3_ptp_enable(struct ptp_clock_info
*ptp
,
6253 struct ptp_clock_request
*rq
, int on
)
6255 struct tg3
*tp
= container_of(ptp
, struct tg3
, ptp_info
);
6260 case PTP_CLK_REQ_PEROUT
:
6261 if (rq
->perout
.index
!= 0)
6264 tg3_full_lock(tp
, 0);
6265 clock_ctl
= tr32(TG3_EAV_REF_CLCK_CTL
);
6266 clock_ctl
&= ~TG3_EAV_CTL_TSYNC_GPIO_MASK
;
6271 nsec
= rq
->perout
.start
.sec
* 1000000000ULL +
6272 rq
->perout
.start
.nsec
;
6274 if (rq
->perout
.period
.sec
|| rq
->perout
.period
.nsec
) {
6275 netdev_warn(tp
->dev
,
6276 "Device supports only a one-shot timesync output, period must be 0\n");
6281 if (nsec
& (1ULL << 63)) {
6282 netdev_warn(tp
->dev
,
6283 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6288 tw32(TG3_EAV_WATCHDOG0_LSB
, (nsec
& 0xffffffff));
6289 tw32(TG3_EAV_WATCHDOG0_MSB
,
6290 TG3_EAV_WATCHDOG0_EN
|
6291 ((nsec
>> 32) & TG3_EAV_WATCHDOG_MSB_MASK
));
6293 tw32(TG3_EAV_REF_CLCK_CTL
,
6294 clock_ctl
| TG3_EAV_CTL_TSYNC_WDOG0
);
6296 tw32(TG3_EAV_WATCHDOG0_MSB
, 0);
6297 tw32(TG3_EAV_REF_CLCK_CTL
, clock_ctl
);
6301 tg3_full_unlock(tp
);
6311 static const struct ptp_clock_info tg3_ptp_caps
= {
6312 .owner
= THIS_MODULE
,
6313 .name
= "tg3 clock",
6314 .max_adj
= 250000000,
6320 .adjfreq
= tg3_ptp_adjfreq
,
6321 .adjtime
= tg3_ptp_adjtime
,
6322 .gettime64
= tg3_ptp_gettime
,
6323 .settime64
= tg3_ptp_settime
,
6324 .enable
= tg3_ptp_enable
,
6327 static void tg3_hwclock_to_timestamp(struct tg3
*tp
, u64 hwclock
,
6328 struct skb_shared_hwtstamps
*timestamp
)
6330 memset(timestamp
, 0, sizeof(struct skb_shared_hwtstamps
));
6331 timestamp
->hwtstamp
= ns_to_ktime((hwclock
& TG3_TSTAMP_MASK
) +
6335 /* tp->lock must be held */
6336 static void tg3_ptp_init(struct tg3
*tp
)
6338 if (!tg3_flag(tp
, PTP_CAPABLE
))
6341 /* Initialize the hardware clock to the system time. */
6342 tg3_refclk_write(tp
, ktime_to_ns(ktime_get_real()));
6344 tp
->ptp_info
= tg3_ptp_caps
;
6347 /* tp->lock must be held */
6348 static void tg3_ptp_resume(struct tg3
*tp
)
6350 if (!tg3_flag(tp
, PTP_CAPABLE
))
6353 tg3_refclk_write(tp
, ktime_to_ns(ktime_get_real()) + tp
->ptp_adjust
);
6357 static void tg3_ptp_fini(struct tg3
*tp
)
6359 if (!tg3_flag(tp
, PTP_CAPABLE
) || !tp
->ptp_clock
)
6362 ptp_clock_unregister(tp
->ptp_clock
);
6363 tp
->ptp_clock
= NULL
;
6367 static inline int tg3_irq_sync(struct tg3
*tp
)
6369 return tp
->irq_sync
;
6372 static inline void tg3_rd32_loop(struct tg3
*tp
, u32
*dst
, u32 off
, u32 len
)
6376 dst
= (u32
*)((u8
*)dst
+ off
);
6377 for (i
= 0; i
< len
; i
+= sizeof(u32
))
6378 *dst
++ = tr32(off
+ i
);
6381 static void tg3_dump_legacy_regs(struct tg3
*tp
, u32
*regs
)
6383 tg3_rd32_loop(tp
, regs
, TG3PCI_VENDOR
, 0xb0);
6384 tg3_rd32_loop(tp
, regs
, MAILBOX_INTERRUPT_0
, 0x200);
6385 tg3_rd32_loop(tp
, regs
, MAC_MODE
, 0x4f0);
6386 tg3_rd32_loop(tp
, regs
, SNDDATAI_MODE
, 0xe0);
6387 tg3_rd32_loop(tp
, regs
, SNDDATAC_MODE
, 0x04);
6388 tg3_rd32_loop(tp
, regs
, SNDBDS_MODE
, 0x80);
6389 tg3_rd32_loop(tp
, regs
, SNDBDI_MODE
, 0x48);
6390 tg3_rd32_loop(tp
, regs
, SNDBDC_MODE
, 0x04);
6391 tg3_rd32_loop(tp
, regs
, RCVLPC_MODE
, 0x20);
6392 tg3_rd32_loop(tp
, regs
, RCVLPC_SELLST_BASE
, 0x15c);
6393 tg3_rd32_loop(tp
, regs
, RCVDBDI_MODE
, 0x0c);
6394 tg3_rd32_loop(tp
, regs
, RCVDBDI_JUMBO_BD
, 0x3c);
6395 tg3_rd32_loop(tp
, regs
, RCVDBDI_BD_PROD_IDX_0
, 0x44);
6396 tg3_rd32_loop(tp
, regs
, RCVDCC_MODE
, 0x04);
6397 tg3_rd32_loop(tp
, regs
, RCVBDI_MODE
, 0x20);
6398 tg3_rd32_loop(tp
, regs
, RCVCC_MODE
, 0x14);
6399 tg3_rd32_loop(tp
, regs
, RCVLSC_MODE
, 0x08);
6400 tg3_rd32_loop(tp
, regs
, MBFREE_MODE
, 0x08);
6401 tg3_rd32_loop(tp
, regs
, HOSTCC_MODE
, 0x100);
6403 if (tg3_flag(tp
, SUPPORT_MSIX
))
6404 tg3_rd32_loop(tp
, regs
, HOSTCC_RXCOL_TICKS_VEC1
, 0x180);
6406 tg3_rd32_loop(tp
, regs
, MEMARB_MODE
, 0x10);
6407 tg3_rd32_loop(tp
, regs
, BUFMGR_MODE
, 0x58);
6408 tg3_rd32_loop(tp
, regs
, RDMAC_MODE
, 0x08);
6409 tg3_rd32_loop(tp
, regs
, WDMAC_MODE
, 0x08);
6410 tg3_rd32_loop(tp
, regs
, RX_CPU_MODE
, 0x04);
6411 tg3_rd32_loop(tp
, regs
, RX_CPU_STATE
, 0x04);
6412 tg3_rd32_loop(tp
, regs
, RX_CPU_PGMCTR
, 0x04);
6413 tg3_rd32_loop(tp
, regs
, RX_CPU_HWBKPT
, 0x04);
6415 if (!tg3_flag(tp
, 5705_PLUS
)) {
6416 tg3_rd32_loop(tp
, regs
, TX_CPU_MODE
, 0x04);
6417 tg3_rd32_loop(tp
, regs
, TX_CPU_STATE
, 0x04);
6418 tg3_rd32_loop(tp
, regs
, TX_CPU_PGMCTR
, 0x04);
6421 tg3_rd32_loop(tp
, regs
, GRCMBOX_INTERRUPT_0
, 0x110);
6422 tg3_rd32_loop(tp
, regs
, FTQ_RESET
, 0x120);
6423 tg3_rd32_loop(tp
, regs
, MSGINT_MODE
, 0x0c);
6424 tg3_rd32_loop(tp
, regs
, DMAC_MODE
, 0x04);
6425 tg3_rd32_loop(tp
, regs
, GRC_MODE
, 0x4c);
6427 if (tg3_flag(tp
, NVRAM
))
6428 tg3_rd32_loop(tp
, regs
, NVRAM_CMD
, 0x24);
6431 static void tg3_dump_state(struct tg3
*tp
)
6436 regs
= kzalloc(TG3_REG_BLK_SIZE
, GFP_ATOMIC
);
6440 if (tg3_flag(tp
, PCI_EXPRESS
)) {
6441 /* Read up to but not including private PCI registers */
6442 for (i
= 0; i
< TG3_PCIE_TLDLPL_PORT
; i
+= sizeof(u32
))
6443 regs
[i
/ sizeof(u32
)] = tr32(i
);
6445 tg3_dump_legacy_regs(tp
, regs
);
6447 for (i
= 0; i
< TG3_REG_BLK_SIZE
/ sizeof(u32
); i
+= 4) {
6448 if (!regs
[i
+ 0] && !regs
[i
+ 1] &&
6449 !regs
[i
+ 2] && !regs
[i
+ 3])
6452 netdev_err(tp
->dev
, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6454 regs
[i
+ 0], regs
[i
+ 1], regs
[i
+ 2], regs
[i
+ 3]);
6459 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6460 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6462 /* SW status block */
6464 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6466 tnapi
->hw_status
->status
,
6467 tnapi
->hw_status
->status_tag
,
6468 tnapi
->hw_status
->rx_jumbo_consumer
,
6469 tnapi
->hw_status
->rx_consumer
,
6470 tnapi
->hw_status
->rx_mini_consumer
,
6471 tnapi
->hw_status
->idx
[0].rx_producer
,
6472 tnapi
->hw_status
->idx
[0].tx_consumer
);
6475 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6477 tnapi
->last_tag
, tnapi
->last_irq_tag
,
6478 tnapi
->tx_prod
, tnapi
->tx_cons
, tnapi
->tx_pending
,
6480 tnapi
->prodring
.rx_std_prod_idx
,
6481 tnapi
->prodring
.rx_std_cons_idx
,
6482 tnapi
->prodring
.rx_jmb_prod_idx
,
6483 tnapi
->prodring
.rx_jmb_cons_idx
);
6487 /* This is called whenever we suspect that the system chipset is re-
6488 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6489 * is bogus tx completions. We try to recover by setting the
6490 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6493 static void tg3_tx_recover(struct tg3
*tp
)
6495 BUG_ON(tg3_flag(tp
, MBOX_WRITE_REORDER
) ||
6496 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
6498 netdev_warn(tp
->dev
,
6499 "The system may be re-ordering memory-mapped I/O "
6500 "cycles to the network device, attempting to recover. "
6501 "Please report the problem to the driver maintainer "
6502 "and include system chipset information.\n");
6504 tg3_flag_set(tp
, TX_RECOVERY_PENDING
);
6507 static inline u32
tg3_tx_avail(struct tg3_napi
*tnapi
)
6509 /* Tell compiler to fetch tx indices from memory. */
6511 return tnapi
->tx_pending
-
6512 ((tnapi
->tx_prod
- tnapi
->tx_cons
) & (TG3_TX_RING_SIZE
- 1));
6515 /* Tigon3 never reports partial packet sends. So we do not
6516 * need special logic to handle SKBs that have not had all
6517 * of their frags sent yet, like SunGEM does.
6519 static void tg3_tx(struct tg3_napi
*tnapi
)
6521 struct tg3
*tp
= tnapi
->tp
;
6522 u32 hw_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
6523 u32 sw_idx
= tnapi
->tx_cons
;
6524 struct netdev_queue
*txq
;
6525 int index
= tnapi
- tp
->napi
;
6526 unsigned int pkts_compl
= 0, bytes_compl
= 0;
6528 if (tg3_flag(tp
, ENABLE_TSS
))
6531 txq
= netdev_get_tx_queue(tp
->dev
, index
);
6533 while (sw_idx
!= hw_idx
) {
6534 struct tg3_tx_ring_info
*ri
= &tnapi
->tx_buffers
[sw_idx
];
6535 struct sk_buff
*skb
= ri
->skb
;
6538 if (unlikely(skb
== NULL
)) {
6543 if (tnapi
->tx_ring
[sw_idx
].len_flags
& TXD_FLAG_HWTSTAMP
) {
6544 struct skb_shared_hwtstamps timestamp
;
6545 u64 hwclock
= tr32(TG3_TX_TSTAMP_LSB
);
6546 hwclock
|= (u64
)tr32(TG3_TX_TSTAMP_MSB
) << 32;
6548 tg3_hwclock_to_timestamp(tp
, hwclock
, ×tamp
);
6550 skb_tstamp_tx(skb
, ×tamp
);
6553 pci_unmap_single(tp
->pdev
,
6554 dma_unmap_addr(ri
, mapping
),
6560 while (ri
->fragmented
) {
6561 ri
->fragmented
= false;
6562 sw_idx
= NEXT_TX(sw_idx
);
6563 ri
= &tnapi
->tx_buffers
[sw_idx
];
6566 sw_idx
= NEXT_TX(sw_idx
);
6568 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
6569 ri
= &tnapi
->tx_buffers
[sw_idx
];
6570 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
6573 pci_unmap_page(tp
->pdev
,
6574 dma_unmap_addr(ri
, mapping
),
6575 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
6578 while (ri
->fragmented
) {
6579 ri
->fragmented
= false;
6580 sw_idx
= NEXT_TX(sw_idx
);
6581 ri
= &tnapi
->tx_buffers
[sw_idx
];
6584 sw_idx
= NEXT_TX(sw_idx
);
6588 bytes_compl
+= skb
->len
;
6590 dev_consume_skb_any(skb
);
6592 if (unlikely(tx_bug
)) {
6598 netdev_tx_completed_queue(txq
, pkts_compl
, bytes_compl
);
6600 tnapi
->tx_cons
= sw_idx
;
6602 /* Need to make the tx_cons update visible to tg3_start_xmit()
6603 * before checking for netif_queue_stopped(). Without the
6604 * memory barrier, there is a small possibility that tg3_start_xmit()
6605 * will miss it and cause the queue to be stopped forever.
6609 if (unlikely(netif_tx_queue_stopped(txq
) &&
6610 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))) {
6611 __netif_tx_lock(txq
, smp_processor_id());
6612 if (netif_tx_queue_stopped(txq
) &&
6613 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))
6614 netif_tx_wake_queue(txq
);
6615 __netif_tx_unlock(txq
);
6619 static void tg3_frag_free(bool is_frag
, void *data
)
6622 skb_free_frag(data
);
6627 static void tg3_rx_data_free(struct tg3
*tp
, struct ring_info
*ri
, u32 map_sz
)
6629 unsigned int skb_size
= SKB_DATA_ALIGN(map_sz
+ TG3_RX_OFFSET(tp
)) +
6630 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
6635 pci_unmap_single(tp
->pdev
, dma_unmap_addr(ri
, mapping
),
6636 map_sz
, PCI_DMA_FROMDEVICE
);
6637 tg3_frag_free(skb_size
<= PAGE_SIZE
, ri
->data
);
6642 /* Returns size of skb allocated or < 0 on error.
6644 * We only need to fill in the address because the other members
6645 * of the RX descriptor are invariant, see tg3_init_rings.
6647 * Note the purposeful assymetry of cpu vs. chip accesses. For
6648 * posting buffers we only dirty the first cache line of the RX
6649 * descriptor (containing the address). Whereas for the RX status
6650 * buffers the cpu only reads the last cacheline of the RX descriptor
6651 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6653 static int tg3_alloc_rx_data(struct tg3
*tp
, struct tg3_rx_prodring_set
*tpr
,
6654 u32 opaque_key
, u32 dest_idx_unmasked
,
6655 unsigned int *frag_size
)
6657 struct tg3_rx_buffer_desc
*desc
;
6658 struct ring_info
*map
;
6661 int skb_size
, data_size
, dest_idx
;
6663 switch (opaque_key
) {
6664 case RXD_OPAQUE_RING_STD
:
6665 dest_idx
= dest_idx_unmasked
& tp
->rx_std_ring_mask
;
6666 desc
= &tpr
->rx_std
[dest_idx
];
6667 map
= &tpr
->rx_std_buffers
[dest_idx
];
6668 data_size
= tp
->rx_pkt_map_sz
;
6671 case RXD_OPAQUE_RING_JUMBO
:
6672 dest_idx
= dest_idx_unmasked
& tp
->rx_jmb_ring_mask
;
6673 desc
= &tpr
->rx_jmb
[dest_idx
].std
;
6674 map
= &tpr
->rx_jmb_buffers
[dest_idx
];
6675 data_size
= TG3_RX_JMB_MAP_SZ
;
6682 /* Do not overwrite any of the map or rp information
6683 * until we are sure we can commit to a new buffer.
6685 * Callers depend upon this behavior and assume that
6686 * we leave everything unchanged if we fail.
6688 skb_size
= SKB_DATA_ALIGN(data_size
+ TG3_RX_OFFSET(tp
)) +
6689 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
6690 if (skb_size
<= PAGE_SIZE
) {
6691 data
= netdev_alloc_frag(skb_size
);
6692 *frag_size
= skb_size
;
6694 data
= kmalloc(skb_size
, GFP_ATOMIC
);
6700 mapping
= pci_map_single(tp
->pdev
,
6701 data
+ TG3_RX_OFFSET(tp
),
6703 PCI_DMA_FROMDEVICE
);
6704 if (unlikely(pci_dma_mapping_error(tp
->pdev
, mapping
))) {
6705 tg3_frag_free(skb_size
<= PAGE_SIZE
, data
);
6710 dma_unmap_addr_set(map
, mapping
, mapping
);
6712 desc
->addr_hi
= ((u64
)mapping
>> 32);
6713 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
6718 /* We only need to move over in the address because the other
6719 * members of the RX descriptor are invariant. See notes above
6720 * tg3_alloc_rx_data for full details.
6722 static void tg3_recycle_rx(struct tg3_napi
*tnapi
,
6723 struct tg3_rx_prodring_set
*dpr
,
6724 u32 opaque_key
, int src_idx
,
6725 u32 dest_idx_unmasked
)
6727 struct tg3
*tp
= tnapi
->tp
;
6728 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
6729 struct ring_info
*src_map
, *dest_map
;
6730 struct tg3_rx_prodring_set
*spr
= &tp
->napi
[0].prodring
;
6733 switch (opaque_key
) {
6734 case RXD_OPAQUE_RING_STD
:
6735 dest_idx
= dest_idx_unmasked
& tp
->rx_std_ring_mask
;
6736 dest_desc
= &dpr
->rx_std
[dest_idx
];
6737 dest_map
= &dpr
->rx_std_buffers
[dest_idx
];
6738 src_desc
= &spr
->rx_std
[src_idx
];
6739 src_map
= &spr
->rx_std_buffers
[src_idx
];
6742 case RXD_OPAQUE_RING_JUMBO
:
6743 dest_idx
= dest_idx_unmasked
& tp
->rx_jmb_ring_mask
;
6744 dest_desc
= &dpr
->rx_jmb
[dest_idx
].std
;
6745 dest_map
= &dpr
->rx_jmb_buffers
[dest_idx
];
6746 src_desc
= &spr
->rx_jmb
[src_idx
].std
;
6747 src_map
= &spr
->rx_jmb_buffers
[src_idx
];
6754 dest_map
->data
= src_map
->data
;
6755 dma_unmap_addr_set(dest_map
, mapping
,
6756 dma_unmap_addr(src_map
, mapping
));
6757 dest_desc
->addr_hi
= src_desc
->addr_hi
;
6758 dest_desc
->addr_lo
= src_desc
->addr_lo
;
6760 /* Ensure that the update to the skb happens after the physical
6761 * addresses have been transferred to the new BD location.
6765 src_map
->data
= NULL
;
6768 /* The RX ring scheme is composed of multiple rings which post fresh
6769 * buffers to the chip, and one special ring the chip uses to report
6770 * status back to the host.
6772 * The special ring reports the status of received packets to the
6773 * host. The chip does not write into the original descriptor the
6774 * RX buffer was obtained from. The chip simply takes the original
6775 * descriptor as provided by the host, updates the status and length
6776 * field, then writes this into the next status ring entry.
6778 * Each ring the host uses to post buffers to the chip is described
6779 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6780 * it is first placed into the on-chip ram. When the packet's length
6781 * is known, it walks down the TG3_BDINFO entries to select the ring.
6782 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6783 * which is within the range of the new packet's length is chosen.
6785 * The "separate ring for rx status" scheme may sound queer, but it makes
6786 * sense from a cache coherency perspective. If only the host writes
6787 * to the buffer post rings, and only the chip writes to the rx status
6788 * rings, then cache lines never move beyond shared-modified state.
6789 * If both the host and chip were to write into the same ring, cache line
6790 * eviction could occur since both entities want it in an exclusive state.
6792 static int tg3_rx(struct tg3_napi
*tnapi
, int budget
)
6794 struct tg3
*tp
= tnapi
->tp
;
6795 u32 work_mask
, rx_std_posted
= 0;
6796 u32 std_prod_idx
, jmb_prod_idx
;
6797 u32 sw_idx
= tnapi
->rx_rcb_ptr
;
6800 struct tg3_rx_prodring_set
*tpr
= &tnapi
->prodring
;
6802 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
6804 * We need to order the read of hw_idx and the read of
6805 * the opaque cookie.
6810 std_prod_idx
= tpr
->rx_std_prod_idx
;
6811 jmb_prod_idx
= tpr
->rx_jmb_prod_idx
;
6812 while (sw_idx
!= hw_idx
&& budget
> 0) {
6813 struct ring_info
*ri
;
6814 struct tg3_rx_buffer_desc
*desc
= &tnapi
->rx_rcb
[sw_idx
];
6816 struct sk_buff
*skb
;
6817 dma_addr_t dma_addr
;
6818 u32 opaque_key
, desc_idx
, *post_ptr
;
6822 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
6823 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
6824 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
6825 ri
= &tp
->napi
[0].prodring
.rx_std_buffers
[desc_idx
];
6826 dma_addr
= dma_unmap_addr(ri
, mapping
);
6828 post_ptr
= &std_prod_idx
;
6830 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
6831 ri
= &tp
->napi
[0].prodring
.rx_jmb_buffers
[desc_idx
];
6832 dma_addr
= dma_unmap_addr(ri
, mapping
);
6834 post_ptr
= &jmb_prod_idx
;
6836 goto next_pkt_nopost
;
6838 work_mask
|= opaque_key
;
6840 if (desc
->err_vlan
& RXD_ERR_MASK
) {
6842 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
6843 desc_idx
, *post_ptr
);
6845 /* Other statistics kept track of by card. */
6850 prefetch(data
+ TG3_RX_OFFSET(tp
));
6851 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
6854 if ((desc
->type_flags
& RXD_FLAG_PTPSTAT_MASK
) ==
6855 RXD_FLAG_PTPSTAT_PTPV1
||
6856 (desc
->type_flags
& RXD_FLAG_PTPSTAT_MASK
) ==
6857 RXD_FLAG_PTPSTAT_PTPV2
) {
6858 tstamp
= tr32(TG3_RX_TSTAMP_LSB
);
6859 tstamp
|= (u64
)tr32(TG3_RX_TSTAMP_MSB
) << 32;
6862 if (len
> TG3_RX_COPY_THRESH(tp
)) {
6864 unsigned int frag_size
;
6866 skb_size
= tg3_alloc_rx_data(tp
, tpr
, opaque_key
,
6867 *post_ptr
, &frag_size
);
6871 pci_unmap_single(tp
->pdev
, dma_addr
, skb_size
,
6872 PCI_DMA_FROMDEVICE
);
6874 /* Ensure that the update to the data happens
6875 * after the usage of the old DMA mapping.
6881 skb
= build_skb(data
, frag_size
);
6883 tg3_frag_free(frag_size
!= 0, data
);
6884 goto drop_it_no_recycle
;
6886 skb_reserve(skb
, TG3_RX_OFFSET(tp
));
6888 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
6889 desc_idx
, *post_ptr
);
6891 skb
= netdev_alloc_skb(tp
->dev
,
6892 len
+ TG3_RAW_IP_ALIGN
);
6894 goto drop_it_no_recycle
;
6896 skb_reserve(skb
, TG3_RAW_IP_ALIGN
);
6897 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
6899 data
+ TG3_RX_OFFSET(tp
),
6901 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
6906 tg3_hwclock_to_timestamp(tp
, tstamp
,
6907 skb_hwtstamps(skb
));
6909 if ((tp
->dev
->features
& NETIF_F_RXCSUM
) &&
6910 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
6911 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
6912 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
6913 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
6915 skb_checksum_none_assert(skb
);
6917 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
6919 if (len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
6920 skb
->protocol
!= htons(ETH_P_8021Q
) &&
6921 skb
->protocol
!= htons(ETH_P_8021AD
)) {
6922 dev_kfree_skb_any(skb
);
6923 goto drop_it_no_recycle
;
6926 if (desc
->type_flags
& RXD_FLAG_VLAN
&&
6927 !(tp
->rx_mode
& RX_MODE_KEEP_VLAN_TAG
))
6928 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
),
6929 desc
->err_vlan
& RXD_VLAN_MASK
);
6931 napi_gro_receive(&tnapi
->napi
, skb
);
6939 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
6940 tpr
->rx_std_prod_idx
= std_prod_idx
&
6941 tp
->rx_std_ring_mask
;
6942 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
6943 tpr
->rx_std_prod_idx
);
6944 work_mask
&= ~RXD_OPAQUE_RING_STD
;
6949 sw_idx
&= tp
->rx_ret_ring_mask
;
6951 /* Refresh hw_idx to see if there is new work */
6952 if (sw_idx
== hw_idx
) {
6953 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
6958 /* ACK the status ring. */
6959 tnapi
->rx_rcb_ptr
= sw_idx
;
6960 tw32_rx_mbox(tnapi
->consmbox
, sw_idx
);
6962 /* Refill RX ring(s). */
6963 if (!tg3_flag(tp
, ENABLE_RSS
)) {
6964 /* Sync BD data before updating mailbox */
6967 if (work_mask
& RXD_OPAQUE_RING_STD
) {
6968 tpr
->rx_std_prod_idx
= std_prod_idx
&
6969 tp
->rx_std_ring_mask
;
6970 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
6971 tpr
->rx_std_prod_idx
);
6973 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
6974 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
&
6975 tp
->rx_jmb_ring_mask
;
6976 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
6977 tpr
->rx_jmb_prod_idx
);
6980 } else if (work_mask
) {
6981 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6982 * updated before the producer indices can be updated.
6986 tpr
->rx_std_prod_idx
= std_prod_idx
& tp
->rx_std_ring_mask
;
6987 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
& tp
->rx_jmb_ring_mask
;
6989 if (tnapi
!= &tp
->napi
[1]) {
6990 tp
->rx_refill
= true;
6991 napi_schedule(&tp
->napi
[1].napi
);
6998 static void tg3_poll_link(struct tg3
*tp
)
7000 /* handle link change and other phy events */
7001 if (!(tg3_flag(tp
, USE_LINKCHG_REG
) || tg3_flag(tp
, POLL_SERDES
))) {
7002 struct tg3_hw_status
*sblk
= tp
->napi
[0].hw_status
;
7004 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
7005 sblk
->status
= SD_STATUS_UPDATED
|
7006 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
7007 spin_lock(&tp
->lock
);
7008 if (tg3_flag(tp
, USE_PHYLIB
)) {
7010 (MAC_STATUS_SYNC_CHANGED
|
7011 MAC_STATUS_CFG_CHANGED
|
7012 MAC_STATUS_MI_COMPLETION
|
7013 MAC_STATUS_LNKSTATE_CHANGED
));
7016 tg3_setup_phy(tp
, false);
7017 spin_unlock(&tp
->lock
);
7022 static int tg3_rx_prodring_xfer(struct tg3
*tp
,
7023 struct tg3_rx_prodring_set
*dpr
,
7024 struct tg3_rx_prodring_set
*spr
)
7026 u32 si
, di
, cpycnt
, src_prod_idx
;
7030 src_prod_idx
= spr
->rx_std_prod_idx
;
7032 /* Make sure updates to the rx_std_buffers[] entries and the
7033 * standard producer index are seen in the correct order.
7037 if (spr
->rx_std_cons_idx
== src_prod_idx
)
7040 if (spr
->rx_std_cons_idx
< src_prod_idx
)
7041 cpycnt
= src_prod_idx
- spr
->rx_std_cons_idx
;
7043 cpycnt
= tp
->rx_std_ring_mask
+ 1 -
7044 spr
->rx_std_cons_idx
;
7046 cpycnt
= min(cpycnt
,
7047 tp
->rx_std_ring_mask
+ 1 - dpr
->rx_std_prod_idx
);
7049 si
= spr
->rx_std_cons_idx
;
7050 di
= dpr
->rx_std_prod_idx
;
7052 for (i
= di
; i
< di
+ cpycnt
; i
++) {
7053 if (dpr
->rx_std_buffers
[i
].data
) {
7063 /* Ensure that updates to the rx_std_buffers ring and the
7064 * shadowed hardware producer ring from tg3_recycle_skb() are
7065 * ordered correctly WRT the skb check above.
7069 memcpy(&dpr
->rx_std_buffers
[di
],
7070 &spr
->rx_std_buffers
[si
],
7071 cpycnt
* sizeof(struct ring_info
));
7073 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
7074 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
7075 sbd
= &spr
->rx_std
[si
];
7076 dbd
= &dpr
->rx_std
[di
];
7077 dbd
->addr_hi
= sbd
->addr_hi
;
7078 dbd
->addr_lo
= sbd
->addr_lo
;
7081 spr
->rx_std_cons_idx
= (spr
->rx_std_cons_idx
+ cpycnt
) &
7082 tp
->rx_std_ring_mask
;
7083 dpr
->rx_std_prod_idx
= (dpr
->rx_std_prod_idx
+ cpycnt
) &
7084 tp
->rx_std_ring_mask
;
7088 src_prod_idx
= spr
->rx_jmb_prod_idx
;
7090 /* Make sure updates to the rx_jmb_buffers[] entries and
7091 * the jumbo producer index are seen in the correct order.
7095 if (spr
->rx_jmb_cons_idx
== src_prod_idx
)
7098 if (spr
->rx_jmb_cons_idx
< src_prod_idx
)
7099 cpycnt
= src_prod_idx
- spr
->rx_jmb_cons_idx
;
7101 cpycnt
= tp
->rx_jmb_ring_mask
+ 1 -
7102 spr
->rx_jmb_cons_idx
;
7104 cpycnt
= min(cpycnt
,
7105 tp
->rx_jmb_ring_mask
+ 1 - dpr
->rx_jmb_prod_idx
);
7107 si
= spr
->rx_jmb_cons_idx
;
7108 di
= dpr
->rx_jmb_prod_idx
;
7110 for (i
= di
; i
< di
+ cpycnt
; i
++) {
7111 if (dpr
->rx_jmb_buffers
[i
].data
) {
7121 /* Ensure that updates to the rx_jmb_buffers ring and the
7122 * shadowed hardware producer ring from tg3_recycle_skb() are
7123 * ordered correctly WRT the skb check above.
7127 memcpy(&dpr
->rx_jmb_buffers
[di
],
7128 &spr
->rx_jmb_buffers
[si
],
7129 cpycnt
* sizeof(struct ring_info
));
7131 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
7132 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
7133 sbd
= &spr
->rx_jmb
[si
].std
;
7134 dbd
= &dpr
->rx_jmb
[di
].std
;
7135 dbd
->addr_hi
= sbd
->addr_hi
;
7136 dbd
->addr_lo
= sbd
->addr_lo
;
7139 spr
->rx_jmb_cons_idx
= (spr
->rx_jmb_cons_idx
+ cpycnt
) &
7140 tp
->rx_jmb_ring_mask
;
7141 dpr
->rx_jmb_prod_idx
= (dpr
->rx_jmb_prod_idx
+ cpycnt
) &
7142 tp
->rx_jmb_ring_mask
;
7148 static int tg3_poll_work(struct tg3_napi
*tnapi
, int work_done
, int budget
)
7150 struct tg3
*tp
= tnapi
->tp
;
7152 /* run TX completion thread */
7153 if (tnapi
->hw_status
->idx
[0].tx_consumer
!= tnapi
->tx_cons
) {
7155 if (unlikely(tg3_flag(tp
, TX_RECOVERY_PENDING
)))
7159 if (!tnapi
->rx_rcb_prod_idx
)
7162 /* run RX thread, within the bounds set by NAPI.
7163 * All RX "locking" is done by ensuring outside
7164 * code synchronizes with tg3->napi.poll()
7166 if (*(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
7167 work_done
+= tg3_rx(tnapi
, budget
- work_done
);
7169 if (tg3_flag(tp
, ENABLE_RSS
) && tnapi
== &tp
->napi
[1]) {
7170 struct tg3_rx_prodring_set
*dpr
= &tp
->napi
[0].prodring
;
7172 u32 std_prod_idx
= dpr
->rx_std_prod_idx
;
7173 u32 jmb_prod_idx
= dpr
->rx_jmb_prod_idx
;
7175 tp
->rx_refill
= false;
7176 for (i
= 1; i
<= tp
->rxq_cnt
; i
++)
7177 err
|= tg3_rx_prodring_xfer(tp
, dpr
,
7178 &tp
->napi
[i
].prodring
);
7182 if (std_prod_idx
!= dpr
->rx_std_prod_idx
)
7183 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
7184 dpr
->rx_std_prod_idx
);
7186 if (jmb_prod_idx
!= dpr
->rx_jmb_prod_idx
)
7187 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
7188 dpr
->rx_jmb_prod_idx
);
7193 tw32_f(HOSTCC_MODE
, tp
->coal_now
);
7199 static inline void tg3_reset_task_schedule(struct tg3
*tp
)
7201 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING
, tp
->tg3_flags
))
7202 schedule_work(&tp
->reset_task
);
7205 static inline void tg3_reset_task_cancel(struct tg3
*tp
)
7207 cancel_work_sync(&tp
->reset_task
);
7208 tg3_flag_clear(tp
, RESET_TASK_PENDING
);
7209 tg3_flag_clear(tp
, TX_RECOVERY_PENDING
);
7212 static int tg3_poll_msix(struct napi_struct
*napi
, int budget
)
7214 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
7215 struct tg3
*tp
= tnapi
->tp
;
7217 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
7220 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
7222 if (unlikely(tg3_flag(tp
, TX_RECOVERY_PENDING
)))
7225 if (unlikely(work_done
>= budget
))
7228 /* tp->last_tag is used in tg3_int_reenable() below
7229 * to tell the hw how much work has been processed,
7230 * so we must read it before checking for more work.
7232 tnapi
->last_tag
= sblk
->status_tag
;
7233 tnapi
->last_irq_tag
= tnapi
->last_tag
;
7236 /* check for RX/TX work to do */
7237 if (likely(sblk
->idx
[0].tx_consumer
== tnapi
->tx_cons
&&
7238 *(tnapi
->rx_rcb_prod_idx
) == tnapi
->rx_rcb_ptr
)) {
7240 /* This test here is not race free, but will reduce
7241 * the number of interrupts by looping again.
7243 if (tnapi
== &tp
->napi
[1] && tp
->rx_refill
)
7246 napi_complete_done(napi
, work_done
);
7247 /* Reenable interrupts. */
7248 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
7250 /* This test here is synchronized by napi_schedule()
7251 * and napi_complete() to close the race condition.
7253 if (unlikely(tnapi
== &tp
->napi
[1] && tp
->rx_refill
)) {
7254 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
7255 HOSTCC_MODE_ENABLE
|
7266 /* work_done is guaranteed to be less than budget. */
7267 napi_complete(napi
);
7268 tg3_reset_task_schedule(tp
);
7272 static void tg3_process_error(struct tg3
*tp
)
7275 bool real_error
= false;
7277 if (tg3_flag(tp
, ERROR_PROCESSED
))
7280 /* Check Flow Attention register */
7281 val
= tr32(HOSTCC_FLOW_ATTN
);
7282 if (val
& ~HOSTCC_FLOW_ATTN_MBUF_LWM
) {
7283 netdev_err(tp
->dev
, "FLOW Attention error. Resetting chip.\n");
7287 if (tr32(MSGINT_STATUS
) & ~MSGINT_STATUS_MSI_REQ
) {
7288 netdev_err(tp
->dev
, "MSI Status error. Resetting chip.\n");
7292 if (tr32(RDMAC_STATUS
) || tr32(WDMAC_STATUS
)) {
7293 netdev_err(tp
->dev
, "DMA Status error. Resetting chip.\n");
7302 tg3_flag_set(tp
, ERROR_PROCESSED
);
7303 tg3_reset_task_schedule(tp
);
7306 static int tg3_poll(struct napi_struct
*napi
, int budget
)
7308 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
7309 struct tg3
*tp
= tnapi
->tp
;
7311 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
7314 if (sblk
->status
& SD_STATUS_ERROR
)
7315 tg3_process_error(tp
);
7319 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
7321 if (unlikely(tg3_flag(tp
, TX_RECOVERY_PENDING
)))
7324 if (unlikely(work_done
>= budget
))
7327 if (tg3_flag(tp
, TAGGED_STATUS
)) {
7328 /* tp->last_tag is used in tg3_int_reenable() below
7329 * to tell the hw how much work has been processed,
7330 * so we must read it before checking for more work.
7332 tnapi
->last_tag
= sblk
->status_tag
;
7333 tnapi
->last_irq_tag
= tnapi
->last_tag
;
7336 sblk
->status
&= ~SD_STATUS_UPDATED
;
7338 if (likely(!tg3_has_work(tnapi
))) {
7339 napi_complete_done(napi
, work_done
);
7340 tg3_int_reenable(tnapi
);
7348 /* work_done is guaranteed to be less than budget. */
7349 napi_complete(napi
);
7350 tg3_reset_task_schedule(tp
);
7354 static void tg3_napi_disable(struct tg3
*tp
)
7358 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--)
7359 napi_disable(&tp
->napi
[i
].napi
);
7362 static void tg3_napi_enable(struct tg3
*tp
)
7366 for (i
= 0; i
< tp
->irq_cnt
; i
++)
7367 napi_enable(&tp
->napi
[i
].napi
);
7370 static void tg3_napi_init(struct tg3
*tp
)
7374 netif_napi_add(tp
->dev
, &tp
->napi
[0].napi
, tg3_poll
, 64);
7375 for (i
= 1; i
< tp
->irq_cnt
; i
++)
7376 netif_napi_add(tp
->dev
, &tp
->napi
[i
].napi
, tg3_poll_msix
, 64);
7379 static void tg3_napi_fini(struct tg3
*tp
)
7383 for (i
= 0; i
< tp
->irq_cnt
; i
++)
7384 netif_napi_del(&tp
->napi
[i
].napi
);
7387 static inline void tg3_netif_stop(struct tg3
*tp
)
7389 netif_trans_update(tp
->dev
); /* prevent tx timeout */
7390 tg3_napi_disable(tp
);
7391 netif_carrier_off(tp
->dev
);
7392 netif_tx_disable(tp
->dev
);
7395 /* tp->lock must be held */
7396 static inline void tg3_netif_start(struct tg3
*tp
)
7400 /* NOTE: unconditional netif_tx_wake_all_queues is only
7401 * appropriate so long as all callers are assured to
7402 * have free tx slots (such as after tg3_init_hw)
7404 netif_tx_wake_all_queues(tp
->dev
);
7407 netif_carrier_on(tp
->dev
);
7409 tg3_napi_enable(tp
);
7410 tp
->napi
[0].hw_status
->status
|= SD_STATUS_UPDATED
;
7411 tg3_enable_ints(tp
);
7414 static void tg3_irq_quiesce(struct tg3
*tp
)
7415 __releases(tp
->lock
)
7416 __acquires(tp
->lock
)
7420 BUG_ON(tp
->irq_sync
);
7425 spin_unlock_bh(&tp
->lock
);
7427 for (i
= 0; i
< tp
->irq_cnt
; i
++)
7428 synchronize_irq(tp
->napi
[i
].irq_vec
);
7430 spin_lock_bh(&tp
->lock
);
7433 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7434 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7435 * with as well. Most of the time, this is not necessary except when
7436 * shutting down the device.
7438 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
7440 spin_lock_bh(&tp
->lock
);
7442 tg3_irq_quiesce(tp
);
7445 static inline void tg3_full_unlock(struct tg3
*tp
)
7447 spin_unlock_bh(&tp
->lock
);
7450 /* One-shot MSI handler - Chip automatically disables interrupt
7451 * after sending MSI so driver doesn't have to do it.
7453 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
7455 struct tg3_napi
*tnapi
= dev_id
;
7456 struct tg3
*tp
= tnapi
->tp
;
7458 prefetch(tnapi
->hw_status
);
7460 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
7462 if (likely(!tg3_irq_sync(tp
)))
7463 napi_schedule(&tnapi
->napi
);
7468 /* MSI ISR - No need to check for interrupt sharing and no need to
7469 * flush status block and interrupt mailbox. PCI ordering rules
7470 * guarantee that MSI will arrive after the status block.
7472 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
7474 struct tg3_napi
*tnapi
= dev_id
;
7475 struct tg3
*tp
= tnapi
->tp
;
7477 prefetch(tnapi
->hw_status
);
7479 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
7481 * Writing any value to intr-mbox-0 clears PCI INTA# and
7482 * chip-internal interrupt pending events.
7483 * Writing non-zero to intr-mbox-0 additional tells the
7484 * NIC to stop sending us irqs, engaging "in-intr-handler"
7487 tw32_mailbox(tnapi
->int_mbox
, 0x00000001);
7488 if (likely(!tg3_irq_sync(tp
)))
7489 napi_schedule(&tnapi
->napi
);
7491 return IRQ_RETVAL(1);
7494 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
7496 struct tg3_napi
*tnapi
= dev_id
;
7497 struct tg3
*tp
= tnapi
->tp
;
7498 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
7499 unsigned int handled
= 1;
7501 /* In INTx mode, it is possible for the interrupt to arrive at
7502 * the CPU before the status block posted prior to the interrupt.
7503 * Reading the PCI State register will confirm whether the
7504 * interrupt is ours and will flush the status block.
7506 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
7507 if (tg3_flag(tp
, CHIP_RESETTING
) ||
7508 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
7515 * Writing any value to intr-mbox-0 clears PCI INTA# and
7516 * chip-internal interrupt pending events.
7517 * Writing non-zero to intr-mbox-0 additional tells the
7518 * NIC to stop sending us irqs, engaging "in-intr-handler"
7521 * Flush the mailbox to de-assert the IRQ immediately to prevent
7522 * spurious interrupts. The flush impacts performance but
7523 * excessive spurious interrupts can be worse in some cases.
7525 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
7526 if (tg3_irq_sync(tp
))
7528 sblk
->status
&= ~SD_STATUS_UPDATED
;
7529 if (likely(tg3_has_work(tnapi
))) {
7530 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
7531 napi_schedule(&tnapi
->napi
);
7533 /* No work, shared interrupt perhaps? re-enable
7534 * interrupts, and flush that PCI write
7536 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
7540 return IRQ_RETVAL(handled
);
7543 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
7545 struct tg3_napi
*tnapi
= dev_id
;
7546 struct tg3
*tp
= tnapi
->tp
;
7547 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
7548 unsigned int handled
= 1;
7550 /* In INTx mode, it is possible for the interrupt to arrive at
7551 * the CPU before the status block posted prior to the interrupt.
7552 * Reading the PCI State register will confirm whether the
7553 * interrupt is ours and will flush the status block.
7555 if (unlikely(sblk
->status_tag
== tnapi
->last_irq_tag
)) {
7556 if (tg3_flag(tp
, CHIP_RESETTING
) ||
7557 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
7564 * writing any value to intr-mbox-0 clears PCI INTA# and
7565 * chip-internal interrupt pending events.
7566 * writing non-zero to intr-mbox-0 additional tells the
7567 * NIC to stop sending us irqs, engaging "in-intr-handler"
7570 * Flush the mailbox to de-assert the IRQ immediately to prevent
7571 * spurious interrupts. The flush impacts performance but
7572 * excessive spurious interrupts can be worse in some cases.
7574 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
7577 * In a shared interrupt configuration, sometimes other devices'
7578 * interrupts will scream. We record the current status tag here
7579 * so that the above check can report that the screaming interrupts
7580 * are unhandled. Eventually they will be silenced.
7582 tnapi
->last_irq_tag
= sblk
->status_tag
;
7584 if (tg3_irq_sync(tp
))
7587 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
7589 napi_schedule(&tnapi
->napi
);
7592 return IRQ_RETVAL(handled
);
7595 /* ISR for interrupt test */
7596 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
7598 struct tg3_napi
*tnapi
= dev_id
;
7599 struct tg3
*tp
= tnapi
->tp
;
7600 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
7602 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
7603 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
7604 tg3_disable_ints(tp
);
7605 return IRQ_RETVAL(1);
7607 return IRQ_RETVAL(0);
7610 #ifdef CONFIG_NET_POLL_CONTROLLER
7611 static void tg3_poll_controller(struct net_device
*dev
)
7614 struct tg3
*tp
= netdev_priv(dev
);
7616 if (tg3_irq_sync(tp
))
7619 for (i
= 0; i
< tp
->irq_cnt
; i
++)
7620 tg3_interrupt(tp
->napi
[i
].irq_vec
, &tp
->napi
[i
]);
7624 static void tg3_tx_timeout(struct net_device
*dev
)
7626 struct tg3
*tp
= netdev_priv(dev
);
7628 if (netif_msg_tx_err(tp
)) {
7629 netdev_err(dev
, "transmit timed out, resetting\n");
7633 tg3_reset_task_schedule(tp
);
7636 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7637 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
7639 u32 base
= (u32
) mapping
& 0xffffffff;
7641 return base
+ len
+ 8 < base
;
7644 /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7645 * of any 4GB boundaries: 4G, 8G, etc
7647 static inline int tg3_4g_tso_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
7650 if (tg3_asic_rev(tp
) == ASIC_REV_5762
&& mss
) {
7651 u32 base
= (u32
) mapping
& 0xffffffff;
7653 return ((base
+ len
+ (mss
& 0x3fff)) < base
);
7658 /* Test for DMA addresses > 40-bit */
7659 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
7662 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7663 if (tg3_flag(tp
, 40BIT_DMA_BUG
))
7664 return ((u64
) mapping
+ len
) > DMA_BIT_MASK(40);
7671 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc
*txbd
,
7672 dma_addr_t mapping
, u32 len
, u32 flags
,
7675 txbd
->addr_hi
= ((u64
) mapping
>> 32);
7676 txbd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
7677 txbd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | (flags
& 0x0000ffff);
7678 txbd
->vlan_tag
= (mss
<< TXD_MSS_SHIFT
) | (vlan
<< TXD_VLAN_TAG_SHIFT
);
7681 static bool tg3_tx_frag_set(struct tg3_napi
*tnapi
, u32
*entry
, u32
*budget
,
7682 dma_addr_t map
, u32 len
, u32 flags
,
7685 struct tg3
*tp
= tnapi
->tp
;
7688 if (tg3_flag(tp
, SHORT_DMA_BUG
) && len
<= 8)
7691 if (tg3_4g_overflow_test(map
, len
))
7694 if (tg3_4g_tso_overflow_test(tp
, map
, len
, mss
))
7697 if (tg3_40bit_overflow_test(tp
, map
, len
))
7700 if (tp
->dma_limit
) {
7701 u32 prvidx
= *entry
;
7702 u32 tmp_flag
= flags
& ~TXD_FLAG_END
;
7703 while (len
> tp
->dma_limit
&& *budget
) {
7704 u32 frag_len
= tp
->dma_limit
;
7705 len
-= tp
->dma_limit
;
7707 /* Avoid the 8byte DMA problem */
7709 len
+= tp
->dma_limit
/ 2;
7710 frag_len
= tp
->dma_limit
/ 2;
7713 tnapi
->tx_buffers
[*entry
].fragmented
= true;
7715 tg3_tx_set_bd(&tnapi
->tx_ring
[*entry
], map
,
7716 frag_len
, tmp_flag
, mss
, vlan
);
7719 *entry
= NEXT_TX(*entry
);
7726 tg3_tx_set_bd(&tnapi
->tx_ring
[*entry
], map
,
7727 len
, flags
, mss
, vlan
);
7729 *entry
= NEXT_TX(*entry
);
7732 tnapi
->tx_buffers
[prvidx
].fragmented
= false;
7736 tg3_tx_set_bd(&tnapi
->tx_ring
[*entry
], map
,
7737 len
, flags
, mss
, vlan
);
7738 *entry
= NEXT_TX(*entry
);
7744 static void tg3_tx_skb_unmap(struct tg3_napi
*tnapi
, u32 entry
, int last
)
7747 struct sk_buff
*skb
;
7748 struct tg3_tx_ring_info
*txb
= &tnapi
->tx_buffers
[entry
];
7753 pci_unmap_single(tnapi
->tp
->pdev
,
7754 dma_unmap_addr(txb
, mapping
),
7758 while (txb
->fragmented
) {
7759 txb
->fragmented
= false;
7760 entry
= NEXT_TX(entry
);
7761 txb
= &tnapi
->tx_buffers
[entry
];
7764 for (i
= 0; i
<= last
; i
++) {
7765 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
7767 entry
= NEXT_TX(entry
);
7768 txb
= &tnapi
->tx_buffers
[entry
];
7770 pci_unmap_page(tnapi
->tp
->pdev
,
7771 dma_unmap_addr(txb
, mapping
),
7772 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
7774 while (txb
->fragmented
) {
7775 txb
->fragmented
= false;
7776 entry
= NEXT_TX(entry
);
7777 txb
= &tnapi
->tx_buffers
[entry
];
7782 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7783 static int tigon3_dma_hwbug_workaround(struct tg3_napi
*tnapi
,
7784 struct sk_buff
**pskb
,
7785 u32
*entry
, u32
*budget
,
7786 u32 base_flags
, u32 mss
, u32 vlan
)
7788 struct tg3
*tp
= tnapi
->tp
;
7789 struct sk_buff
*new_skb
, *skb
= *pskb
;
7790 dma_addr_t new_addr
= 0;
7793 if (tg3_asic_rev(tp
) != ASIC_REV_5701
)
7794 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
7796 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
7798 new_skb
= skb_copy_expand(skb
,
7799 skb_headroom(skb
) + more_headroom
,
7800 skb_tailroom(skb
), GFP_ATOMIC
);
7806 /* New SKB is guaranteed to be linear. */
7807 new_addr
= pci_map_single(tp
->pdev
, new_skb
->data
, new_skb
->len
,
7809 /* Make sure the mapping succeeded */
7810 if (pci_dma_mapping_error(tp
->pdev
, new_addr
)) {
7811 dev_kfree_skb_any(new_skb
);
7814 u32 save_entry
= *entry
;
7816 base_flags
|= TXD_FLAG_END
;
7818 tnapi
->tx_buffers
[*entry
].skb
= new_skb
;
7819 dma_unmap_addr_set(&tnapi
->tx_buffers
[*entry
],
7822 if (tg3_tx_frag_set(tnapi
, entry
, budget
, new_addr
,
7823 new_skb
->len
, base_flags
,
7825 tg3_tx_skb_unmap(tnapi
, save_entry
, -1);
7826 dev_kfree_skb_any(new_skb
);
7832 dev_consume_skb_any(skb
);
7837 static bool tg3_tso_bug_gso_check(struct tg3_napi
*tnapi
, struct sk_buff
*skb
)
7839 /* Check if we will never have enough descriptors,
7840 * as gso_segs can be more than current ring size
7842 return skb_shinfo(skb
)->gso_segs
< tnapi
->tx_pending
/ 3;
7845 static netdev_tx_t
tg3_start_xmit(struct sk_buff
*, struct net_device
*);
7847 /* Use GSO to workaround all TSO packets that meet HW bug conditions
7848 * indicated in tg3_tx_frag_set()
7850 static int tg3_tso_bug(struct tg3
*tp
, struct tg3_napi
*tnapi
,
7851 struct netdev_queue
*txq
, struct sk_buff
*skb
)
7853 struct sk_buff
*segs
, *nskb
;
7854 u32 frag_cnt_est
= skb_shinfo(skb
)->gso_segs
* 3;
7856 /* Estimate the number of fragments in the worst case */
7857 if (unlikely(tg3_tx_avail(tnapi
) <= frag_cnt_est
)) {
7858 netif_tx_stop_queue(txq
);
7860 /* netif_tx_stop_queue() must be done before checking
7861 * checking tx index in tg3_tx_avail() below, because in
7862 * tg3_tx(), we update tx index before checking for
7863 * netif_tx_queue_stopped().
7866 if (tg3_tx_avail(tnapi
) <= frag_cnt_est
)
7867 return NETDEV_TX_BUSY
;
7869 netif_tx_wake_queue(txq
);
7872 segs
= skb_gso_segment(skb
, tp
->dev
->features
&
7873 ~(NETIF_F_TSO
| NETIF_F_TSO6
));
7874 if (IS_ERR(segs
) || !segs
)
7875 goto tg3_tso_bug_end
;
7881 tg3_start_xmit(nskb
, tp
->dev
);
7885 dev_consume_skb_any(skb
);
7887 return NETDEV_TX_OK
;
7890 /* hard_start_xmit for all devices */
7891 static netdev_tx_t
tg3_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
7893 struct tg3
*tp
= netdev_priv(dev
);
7894 u32 len
, entry
, base_flags
, mss
, vlan
= 0;
7896 int i
= -1, would_hit_hwbug
;
7898 struct tg3_napi
*tnapi
;
7899 struct netdev_queue
*txq
;
7901 struct iphdr
*iph
= NULL
;
7902 struct tcphdr
*tcph
= NULL
;
7903 __sum16 tcp_csum
= 0, ip_csum
= 0;
7904 __be16 ip_tot_len
= 0;
7906 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
7907 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
7908 if (tg3_flag(tp
, ENABLE_TSS
))
7911 budget
= tg3_tx_avail(tnapi
);
7913 /* We are running in BH disabled context with netif_tx_lock
7914 * and TX reclaim runs via tp->napi.poll inside of a software
7915 * interrupt. Furthermore, IRQ processing runs lockless so we have
7916 * no IRQ context deadlocks to worry about either. Rejoice!
7918 if (unlikely(budget
<= (skb_shinfo(skb
)->nr_frags
+ 1))) {
7919 if (!netif_tx_queue_stopped(txq
)) {
7920 netif_tx_stop_queue(txq
);
7922 /* This is a hard error, log it. */
7924 "BUG! Tx Ring full when queue awake!\n");
7926 return NETDEV_TX_BUSY
;
7929 entry
= tnapi
->tx_prod
;
7932 mss
= skb_shinfo(skb
)->gso_size
;
7934 u32 tcp_opt_len
, hdr_len
;
7936 if (skb_cow_head(skb
, 0))
7940 tcp_opt_len
= tcp_optlen(skb
);
7942 hdr_len
= skb_transport_offset(skb
) + tcp_hdrlen(skb
) - ETH_HLEN
;
7944 /* HW/FW can not correctly segment packets that have been
7945 * vlan encapsulated.
7947 if (skb
->protocol
== htons(ETH_P_8021Q
) ||
7948 skb
->protocol
== htons(ETH_P_8021AD
)) {
7949 if (tg3_tso_bug_gso_check(tnapi
, skb
))
7950 return tg3_tso_bug(tp
, tnapi
, txq
, skb
);
7954 if (!skb_is_gso_v6(skb
)) {
7955 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
7956 tg3_flag(tp
, TSO_BUG
)) {
7957 if (tg3_tso_bug_gso_check(tnapi
, skb
))
7958 return tg3_tso_bug(tp
, tnapi
, txq
, skb
);
7961 ip_csum
= iph
->check
;
7962 ip_tot_len
= iph
->tot_len
;
7964 iph
->tot_len
= htons(mss
+ hdr_len
);
7967 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
7968 TXD_FLAG_CPU_POST_DMA
);
7970 tcph
= tcp_hdr(skb
);
7971 tcp_csum
= tcph
->check
;
7973 if (tg3_flag(tp
, HW_TSO_1
) ||
7974 tg3_flag(tp
, HW_TSO_2
) ||
7975 tg3_flag(tp
, HW_TSO_3
)) {
7977 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
7979 tcph
->check
= ~csum_tcpudp_magic(iph
->saddr
, iph
->daddr
,
7983 if (tg3_flag(tp
, HW_TSO_3
)) {
7984 mss
|= (hdr_len
& 0xc) << 12;
7986 base_flags
|= 0x00000010;
7987 base_flags
|= (hdr_len
& 0x3e0) << 5;
7988 } else if (tg3_flag(tp
, HW_TSO_2
))
7989 mss
|= hdr_len
<< 9;
7990 else if (tg3_flag(tp
, HW_TSO_1
) ||
7991 tg3_asic_rev(tp
) == ASIC_REV_5705
) {
7992 if (tcp_opt_len
|| iph
->ihl
> 5) {
7995 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
7996 mss
|= (tsflags
<< 11);
7999 if (tcp_opt_len
|| iph
->ihl
> 5) {
8002 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
8003 base_flags
|= tsflags
<< 12;
8006 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
8007 /* HW/FW can not correctly checksum packets that have been
8008 * vlan encapsulated.
8010 if (skb
->protocol
== htons(ETH_P_8021Q
) ||
8011 skb
->protocol
== htons(ETH_P_8021AD
)) {
8012 if (skb_checksum_help(skb
))
8015 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
8019 if (tg3_flag(tp
, USE_JUMBO_BDFLAG
) &&
8020 !mss
&& skb
->len
> VLAN_ETH_FRAME_LEN
)
8021 base_flags
|= TXD_FLAG_JMB_PKT
;
8023 if (skb_vlan_tag_present(skb
)) {
8024 base_flags
|= TXD_FLAG_VLAN
;
8025 vlan
= skb_vlan_tag_get(skb
);
8028 if ((unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
)) &&
8029 tg3_flag(tp
, TX_TSTAMP_EN
)) {
8030 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
8031 base_flags
|= TXD_FLAG_HWTSTAMP
;
8034 len
= skb_headlen(skb
);
8036 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
8037 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
8041 tnapi
->tx_buffers
[entry
].skb
= skb
;
8042 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
8044 would_hit_hwbug
= 0;
8046 if (tg3_flag(tp
, 5701_DMA_BUG
))
8047 would_hit_hwbug
= 1;
8049 if (tg3_tx_frag_set(tnapi
, &entry
, &budget
, mapping
, len
, base_flags
|
8050 ((skb_shinfo(skb
)->nr_frags
== 0) ? TXD_FLAG_END
: 0),
8052 would_hit_hwbug
= 1;
8053 } else if (skb_shinfo(skb
)->nr_frags
> 0) {
8056 if (!tg3_flag(tp
, HW_TSO_1
) &&
8057 !tg3_flag(tp
, HW_TSO_2
) &&
8058 !tg3_flag(tp
, HW_TSO_3
))
8061 /* Now loop through additional data
8062 * fragments, and queue them.
8064 last
= skb_shinfo(skb
)->nr_frags
- 1;
8065 for (i
= 0; i
<= last
; i
++) {
8066 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
8068 len
= skb_frag_size(frag
);
8069 mapping
= skb_frag_dma_map(&tp
->pdev
->dev
, frag
, 0,
8070 len
, DMA_TO_DEVICE
);
8072 tnapi
->tx_buffers
[entry
].skb
= NULL
;
8073 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
8075 if (dma_mapping_error(&tp
->pdev
->dev
, mapping
))
8079 tg3_tx_frag_set(tnapi
, &entry
, &budget
, mapping
,
8081 ((i
== last
) ? TXD_FLAG_END
: 0),
8083 would_hit_hwbug
= 1;
8089 if (would_hit_hwbug
) {
8090 tg3_tx_skb_unmap(tnapi
, tnapi
->tx_prod
, i
);
8092 if (mss
&& tg3_tso_bug_gso_check(tnapi
, skb
)) {
8093 /* If it's a TSO packet, do GSO instead of
8094 * allocating and copying to a large linear SKB
8097 iph
->check
= ip_csum
;
8098 iph
->tot_len
= ip_tot_len
;
8100 tcph
->check
= tcp_csum
;
8101 return tg3_tso_bug(tp
, tnapi
, txq
, skb
);
8104 /* If the workaround fails due to memory/mapping
8105 * failure, silently drop this packet.
8107 entry
= tnapi
->tx_prod
;
8108 budget
= tg3_tx_avail(tnapi
);
8109 if (tigon3_dma_hwbug_workaround(tnapi
, &skb
, &entry
, &budget
,
8110 base_flags
, mss
, vlan
))
8114 skb_tx_timestamp(skb
);
8115 netdev_tx_sent_queue(txq
, skb
->len
);
8117 /* Sync BD data before updating mailbox */
8120 tnapi
->tx_prod
= entry
;
8121 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
8122 netif_tx_stop_queue(txq
);
8124 /* netif_tx_stop_queue() must be done before checking
8125 * checking tx index in tg3_tx_avail() below, because in
8126 * tg3_tx(), we update tx index before checking for
8127 * netif_tx_queue_stopped().
8130 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
8131 netif_tx_wake_queue(txq
);
8134 if (!skb
->xmit_more
|| netif_xmit_stopped(txq
)) {
8135 /* Packets are ready, update Tx producer idx on card. */
8136 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
8140 return NETDEV_TX_OK
;
8143 tg3_tx_skb_unmap(tnapi
, tnapi
->tx_prod
, --i
);
8144 tnapi
->tx_buffers
[tnapi
->tx_prod
].skb
= NULL
;
8146 dev_kfree_skb_any(skb
);
8149 return NETDEV_TX_OK
;
8152 static void tg3_mac_loopback(struct tg3
*tp
, bool enable
)
8155 tp
->mac_mode
&= ~(MAC_MODE_HALF_DUPLEX
|
8156 MAC_MODE_PORT_MODE_MASK
);
8158 tp
->mac_mode
|= MAC_MODE_PORT_INT_LPBACK
;
8160 if (!tg3_flag(tp
, 5705_PLUS
))
8161 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
8163 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
8164 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
8166 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
8168 tp
->mac_mode
&= ~MAC_MODE_PORT_INT_LPBACK
;
8170 if (tg3_flag(tp
, 5705_PLUS
) ||
8171 (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) ||
8172 tg3_asic_rev(tp
) == ASIC_REV_5700
)
8173 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
8176 tw32(MAC_MODE
, tp
->mac_mode
);
8180 static int tg3_phy_lpbk_set(struct tg3
*tp
, u32 speed
, bool extlpbk
)
8182 u32 val
, bmcr
, mac_mode
, ptest
= 0;
8184 tg3_phy_toggle_apd(tp
, false);
8185 tg3_phy_toggle_automdix(tp
, false);
8187 if (extlpbk
&& tg3_phy_set_extloopbk(tp
))
8190 bmcr
= BMCR_FULLDPLX
;
8195 bmcr
|= BMCR_SPEED100
;
8199 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
8201 bmcr
|= BMCR_SPEED100
;
8204 bmcr
|= BMCR_SPEED1000
;
8209 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_FET
)) {
8210 tg3_readphy(tp
, MII_CTRL1000
, &val
);
8211 val
|= CTL1000_AS_MASTER
|
8212 CTL1000_ENABLE_MASTER
;
8213 tg3_writephy(tp
, MII_CTRL1000
, val
);
8215 ptest
= MII_TG3_FET_PTEST_TRIM_SEL
|
8216 MII_TG3_FET_PTEST_TRIM_2
;
8217 tg3_writephy(tp
, MII_TG3_FET_PTEST
, ptest
);
8220 bmcr
|= BMCR_LOOPBACK
;
8222 tg3_writephy(tp
, MII_BMCR
, bmcr
);
8224 /* The write needs to be flushed for the FETs */
8225 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
)
8226 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
8230 if ((tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
8231 tg3_asic_rev(tp
) == ASIC_REV_5785
) {
8232 tg3_writephy(tp
, MII_TG3_FET_PTEST
, ptest
|
8233 MII_TG3_FET_PTEST_FRC_TX_LINK
|
8234 MII_TG3_FET_PTEST_FRC_TX_LOCK
);
8236 /* The write needs to be flushed for the AC131 */
8237 tg3_readphy(tp
, MII_TG3_FET_PTEST
, &val
);
8240 /* Reset to prevent losing 1st rx packet intermittently */
8241 if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
8242 tg3_flag(tp
, 5780_CLASS
)) {
8243 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8245 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8248 mac_mode
= tp
->mac_mode
&
8249 ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
8250 if (speed
== SPEED_1000
)
8251 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
8253 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
8255 if (tg3_asic_rev(tp
) == ASIC_REV_5700
) {
8256 u32 masked_phy_id
= tp
->phy_id
& TG3_PHY_ID_MASK
;
8258 if (masked_phy_id
== TG3_PHY_ID_BCM5401
)
8259 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
8260 else if (masked_phy_id
== TG3_PHY_ID_BCM5411
)
8261 mac_mode
|= MAC_MODE_LINK_POLARITY
;
8263 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
8264 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
8267 tw32(MAC_MODE
, mac_mode
);
8273 static void tg3_set_loopback(struct net_device
*dev
, netdev_features_t features
)
8275 struct tg3
*tp
= netdev_priv(dev
);
8277 if (features
& NETIF_F_LOOPBACK
) {
8278 if (tp
->mac_mode
& MAC_MODE_PORT_INT_LPBACK
)
8281 spin_lock_bh(&tp
->lock
);
8282 tg3_mac_loopback(tp
, true);
8283 netif_carrier_on(tp
->dev
);
8284 spin_unlock_bh(&tp
->lock
);
8285 netdev_info(dev
, "Internal MAC loopback mode enabled.\n");
8287 if (!(tp
->mac_mode
& MAC_MODE_PORT_INT_LPBACK
))
8290 spin_lock_bh(&tp
->lock
);
8291 tg3_mac_loopback(tp
, false);
8292 /* Force link status check */
8293 tg3_setup_phy(tp
, true);
8294 spin_unlock_bh(&tp
->lock
);
8295 netdev_info(dev
, "Internal MAC loopback mode disabled.\n");
8299 static netdev_features_t
tg3_fix_features(struct net_device
*dev
,
8300 netdev_features_t features
)
8302 struct tg3
*tp
= netdev_priv(dev
);
8304 if (dev
->mtu
> ETH_DATA_LEN
&& tg3_flag(tp
, 5780_CLASS
))
8305 features
&= ~NETIF_F_ALL_TSO
;
8310 static int tg3_set_features(struct net_device
*dev
, netdev_features_t features
)
8312 netdev_features_t changed
= dev
->features
^ features
;
8314 if ((changed
& NETIF_F_LOOPBACK
) && netif_running(dev
))
8315 tg3_set_loopback(dev
, features
);
8320 static void tg3_rx_prodring_free(struct tg3
*tp
,
8321 struct tg3_rx_prodring_set
*tpr
)
8325 if (tpr
!= &tp
->napi
[0].prodring
) {
8326 for (i
= tpr
->rx_std_cons_idx
; i
!= tpr
->rx_std_prod_idx
;
8327 i
= (i
+ 1) & tp
->rx_std_ring_mask
)
8328 tg3_rx_data_free(tp
, &tpr
->rx_std_buffers
[i
],
8331 if (tg3_flag(tp
, JUMBO_CAPABLE
)) {
8332 for (i
= tpr
->rx_jmb_cons_idx
;
8333 i
!= tpr
->rx_jmb_prod_idx
;
8334 i
= (i
+ 1) & tp
->rx_jmb_ring_mask
) {
8335 tg3_rx_data_free(tp
, &tpr
->rx_jmb_buffers
[i
],
8343 for (i
= 0; i
<= tp
->rx_std_ring_mask
; i
++)
8344 tg3_rx_data_free(tp
, &tpr
->rx_std_buffers
[i
],
8347 if (tg3_flag(tp
, JUMBO_CAPABLE
) && !tg3_flag(tp
, 5780_CLASS
)) {
8348 for (i
= 0; i
<= tp
->rx_jmb_ring_mask
; i
++)
8349 tg3_rx_data_free(tp
, &tpr
->rx_jmb_buffers
[i
],
8354 /* Initialize rx rings for packet processing.
8356 * The chip has been shut down and the driver detached from
8357 * the networking, so no interrupts or new tx packets will
8358 * end up in the driver. tp->{tx,}lock are held and thus
8361 static int tg3_rx_prodring_alloc(struct tg3
*tp
,
8362 struct tg3_rx_prodring_set
*tpr
)
8364 u32 i
, rx_pkt_dma_sz
;
8366 tpr
->rx_std_cons_idx
= 0;
8367 tpr
->rx_std_prod_idx
= 0;
8368 tpr
->rx_jmb_cons_idx
= 0;
8369 tpr
->rx_jmb_prod_idx
= 0;
8371 if (tpr
!= &tp
->napi
[0].prodring
) {
8372 memset(&tpr
->rx_std_buffers
[0], 0,
8373 TG3_RX_STD_BUFF_RING_SIZE(tp
));
8374 if (tpr
->rx_jmb_buffers
)
8375 memset(&tpr
->rx_jmb_buffers
[0], 0,
8376 TG3_RX_JMB_BUFF_RING_SIZE(tp
));
8380 /* Zero out all descriptors. */
8381 memset(tpr
->rx_std
, 0, TG3_RX_STD_RING_BYTES(tp
));
8383 rx_pkt_dma_sz
= TG3_RX_STD_DMA_SZ
;
8384 if (tg3_flag(tp
, 5780_CLASS
) &&
8385 tp
->dev
->mtu
> ETH_DATA_LEN
)
8386 rx_pkt_dma_sz
= TG3_RX_JMB_DMA_SZ
;
8387 tp
->rx_pkt_map_sz
= TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz
);
8389 /* Initialize invariants of the rings, we only set this
8390 * stuff once. This works because the card does not
8391 * write into the rx buffer posting rings.
8393 for (i
= 0; i
<= tp
->rx_std_ring_mask
; i
++) {
8394 struct tg3_rx_buffer_desc
*rxd
;
8396 rxd
= &tpr
->rx_std
[i
];
8397 rxd
->idx_len
= rx_pkt_dma_sz
<< RXD_LEN_SHIFT
;
8398 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
8399 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
8400 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
8403 /* Now allocate fresh SKBs for each rx ring. */
8404 for (i
= 0; i
< tp
->rx_pending
; i
++) {
8405 unsigned int frag_size
;
8407 if (tg3_alloc_rx_data(tp
, tpr
, RXD_OPAQUE_RING_STD
, i
,
8409 netdev_warn(tp
->dev
,
8410 "Using a smaller RX standard ring. Only "
8411 "%d out of %d buffers were allocated "
8412 "successfully\n", i
, tp
->rx_pending
);
8420 if (!tg3_flag(tp
, JUMBO_CAPABLE
) || tg3_flag(tp
, 5780_CLASS
))
8423 memset(tpr
->rx_jmb
, 0, TG3_RX_JMB_RING_BYTES(tp
));
8425 if (!tg3_flag(tp
, JUMBO_RING_ENABLE
))
8428 for (i
= 0; i
<= tp
->rx_jmb_ring_mask
; i
++) {
8429 struct tg3_rx_buffer_desc
*rxd
;
8431 rxd
= &tpr
->rx_jmb
[i
].std
;
8432 rxd
->idx_len
= TG3_RX_JMB_DMA_SZ
<< RXD_LEN_SHIFT
;
8433 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
8435 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
8436 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
8439 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
8440 unsigned int frag_size
;
8442 if (tg3_alloc_rx_data(tp
, tpr
, RXD_OPAQUE_RING_JUMBO
, i
,
8444 netdev_warn(tp
->dev
,
8445 "Using a smaller RX jumbo ring. Only %d "
8446 "out of %d buffers were allocated "
8447 "successfully\n", i
, tp
->rx_jumbo_pending
);
8450 tp
->rx_jumbo_pending
= i
;
8459 tg3_rx_prodring_free(tp
, tpr
);
8463 static void tg3_rx_prodring_fini(struct tg3
*tp
,
8464 struct tg3_rx_prodring_set
*tpr
)
8466 kfree(tpr
->rx_std_buffers
);
8467 tpr
->rx_std_buffers
= NULL
;
8468 kfree(tpr
->rx_jmb_buffers
);
8469 tpr
->rx_jmb_buffers
= NULL
;
8471 dma_free_coherent(&tp
->pdev
->dev
, TG3_RX_STD_RING_BYTES(tp
),
8472 tpr
->rx_std
, tpr
->rx_std_mapping
);
8476 dma_free_coherent(&tp
->pdev
->dev
, TG3_RX_JMB_RING_BYTES(tp
),
8477 tpr
->rx_jmb
, tpr
->rx_jmb_mapping
);
8482 static int tg3_rx_prodring_init(struct tg3
*tp
,
8483 struct tg3_rx_prodring_set
*tpr
)
8485 tpr
->rx_std_buffers
= kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp
),
8487 if (!tpr
->rx_std_buffers
)
8490 tpr
->rx_std
= dma_alloc_coherent(&tp
->pdev
->dev
,
8491 TG3_RX_STD_RING_BYTES(tp
),
8492 &tpr
->rx_std_mapping
,
8497 if (tg3_flag(tp
, JUMBO_CAPABLE
) && !tg3_flag(tp
, 5780_CLASS
)) {
8498 tpr
->rx_jmb_buffers
= kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp
),
8500 if (!tpr
->rx_jmb_buffers
)
8503 tpr
->rx_jmb
= dma_alloc_coherent(&tp
->pdev
->dev
,
8504 TG3_RX_JMB_RING_BYTES(tp
),
8505 &tpr
->rx_jmb_mapping
,
8514 tg3_rx_prodring_fini(tp
, tpr
);
8518 /* Free up pending packets in all rx/tx rings.
8520 * The chip has been shut down and the driver detached from
8521 * the networking, so no interrupts or new tx packets will
8522 * end up in the driver. tp->{tx,}lock is not held and we are not
8523 * in an interrupt context and thus may sleep.
8525 static void tg3_free_rings(struct tg3
*tp
)
8529 for (j
= 0; j
< tp
->irq_cnt
; j
++) {
8530 struct tg3_napi
*tnapi
= &tp
->napi
[j
];
8532 tg3_rx_prodring_free(tp
, &tnapi
->prodring
);
8534 if (!tnapi
->tx_buffers
)
8537 for (i
= 0; i
< TG3_TX_RING_SIZE
; i
++) {
8538 struct sk_buff
*skb
= tnapi
->tx_buffers
[i
].skb
;
8543 tg3_tx_skb_unmap(tnapi
, i
,
8544 skb_shinfo(skb
)->nr_frags
- 1);
8546 dev_consume_skb_any(skb
);
8548 netdev_tx_reset_queue(netdev_get_tx_queue(tp
->dev
, j
));
8552 /* Initialize tx/rx rings for packet processing.
8554 * The chip has been shut down and the driver detached from
8555 * the networking, so no interrupts or new tx packets will
8556 * end up in the driver. tp->{tx,}lock are held and thus
8559 static int tg3_init_rings(struct tg3
*tp
)
8563 /* Free up all the SKBs. */
8566 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8567 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8569 tnapi
->last_tag
= 0;
8570 tnapi
->last_irq_tag
= 0;
8571 tnapi
->hw_status
->status
= 0;
8572 tnapi
->hw_status
->status_tag
= 0;
8573 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
8578 memset(tnapi
->tx_ring
, 0, TG3_TX_RING_BYTES
);
8580 tnapi
->rx_rcb_ptr
= 0;
8582 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
8584 if (tnapi
->prodring
.rx_std
&&
8585 tg3_rx_prodring_alloc(tp
, &tnapi
->prodring
)) {
8594 static void tg3_mem_tx_release(struct tg3
*tp
)
8598 for (i
= 0; i
< tp
->irq_max
; i
++) {
8599 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8601 if (tnapi
->tx_ring
) {
8602 dma_free_coherent(&tp
->pdev
->dev
, TG3_TX_RING_BYTES
,
8603 tnapi
->tx_ring
, tnapi
->tx_desc_mapping
);
8604 tnapi
->tx_ring
= NULL
;
8607 kfree(tnapi
->tx_buffers
);
8608 tnapi
->tx_buffers
= NULL
;
8612 static int tg3_mem_tx_acquire(struct tg3
*tp
)
8615 struct tg3_napi
*tnapi
= &tp
->napi
[0];
8617 /* If multivector TSS is enabled, vector 0 does not handle
8618 * tx interrupts. Don't allocate any resources for it.
8620 if (tg3_flag(tp
, ENABLE_TSS
))
8623 for (i
= 0; i
< tp
->txq_cnt
; i
++, tnapi
++) {
8624 tnapi
->tx_buffers
= kzalloc(sizeof(struct tg3_tx_ring_info
) *
8625 TG3_TX_RING_SIZE
, GFP_KERNEL
);
8626 if (!tnapi
->tx_buffers
)
8629 tnapi
->tx_ring
= dma_alloc_coherent(&tp
->pdev
->dev
,
8631 &tnapi
->tx_desc_mapping
,
8633 if (!tnapi
->tx_ring
)
8640 tg3_mem_tx_release(tp
);
8644 static void tg3_mem_rx_release(struct tg3
*tp
)
8648 for (i
= 0; i
< tp
->irq_max
; i
++) {
8649 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8651 tg3_rx_prodring_fini(tp
, &tnapi
->prodring
);
8656 dma_free_coherent(&tp
->pdev
->dev
,
8657 TG3_RX_RCB_RING_BYTES(tp
),
8659 tnapi
->rx_rcb_mapping
);
8660 tnapi
->rx_rcb
= NULL
;
8664 static int tg3_mem_rx_acquire(struct tg3
*tp
)
8666 unsigned int i
, limit
;
8668 limit
= tp
->rxq_cnt
;
8670 /* If RSS is enabled, we need a (dummy) producer ring
8671 * set on vector zero. This is the true hw prodring.
8673 if (tg3_flag(tp
, ENABLE_RSS
))
8676 for (i
= 0; i
< limit
; i
++) {
8677 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8679 if (tg3_rx_prodring_init(tp
, &tnapi
->prodring
))
8682 /* If multivector RSS is enabled, vector 0
8683 * does not handle rx or tx interrupts.
8684 * Don't allocate any resources for it.
8686 if (!i
&& tg3_flag(tp
, ENABLE_RSS
))
8689 tnapi
->rx_rcb
= dma_zalloc_coherent(&tp
->pdev
->dev
,
8690 TG3_RX_RCB_RING_BYTES(tp
),
8691 &tnapi
->rx_rcb_mapping
,
8700 tg3_mem_rx_release(tp
);
8705 * Must not be invoked with interrupt sources disabled and
8706 * the hardware shutdown down.
8708 static void tg3_free_consistent(struct tg3
*tp
)
8712 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8713 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8715 if (tnapi
->hw_status
) {
8716 dma_free_coherent(&tp
->pdev
->dev
, TG3_HW_STATUS_SIZE
,
8718 tnapi
->status_mapping
);
8719 tnapi
->hw_status
= NULL
;
8723 tg3_mem_rx_release(tp
);
8724 tg3_mem_tx_release(tp
);
8726 /* Protect tg3_get_stats64() from reading freed tp->hw_stats. */
8727 tg3_full_lock(tp
, 0);
8729 dma_free_coherent(&tp
->pdev
->dev
, sizeof(struct tg3_hw_stats
),
8730 tp
->hw_stats
, tp
->stats_mapping
);
8731 tp
->hw_stats
= NULL
;
8733 tg3_full_unlock(tp
);
8737 * Must not be invoked with interrupt sources disabled and
8738 * the hardware shutdown down. Can sleep.
8740 static int tg3_alloc_consistent(struct tg3
*tp
)
8744 tp
->hw_stats
= dma_zalloc_coherent(&tp
->pdev
->dev
,
8745 sizeof(struct tg3_hw_stats
),
8746 &tp
->stats_mapping
, GFP_KERNEL
);
8750 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8751 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8752 struct tg3_hw_status
*sblk
;
8754 tnapi
->hw_status
= dma_zalloc_coherent(&tp
->pdev
->dev
,
8756 &tnapi
->status_mapping
,
8758 if (!tnapi
->hw_status
)
8761 sblk
= tnapi
->hw_status
;
8763 if (tg3_flag(tp
, ENABLE_RSS
)) {
8764 u16
*prodptr
= NULL
;
8767 * When RSS is enabled, the status block format changes
8768 * slightly. The "rx_jumbo_consumer", "reserved",
8769 * and "rx_mini_consumer" members get mapped to the
8770 * other three rx return ring producer indexes.
8774 prodptr
= &sblk
->idx
[0].rx_producer
;
8777 prodptr
= &sblk
->rx_jumbo_consumer
;
8780 prodptr
= &sblk
->reserved
;
8783 prodptr
= &sblk
->rx_mini_consumer
;
8786 tnapi
->rx_rcb_prod_idx
= prodptr
;
8788 tnapi
->rx_rcb_prod_idx
= &sblk
->idx
[0].rx_producer
;
8792 if (tg3_mem_tx_acquire(tp
) || tg3_mem_rx_acquire(tp
))
8798 tg3_free_consistent(tp
);
8802 #define MAX_WAIT_CNT 1000
8804 /* To stop a block, clear the enable bit and poll till it
8805 * clears. tp->lock is held.
8807 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, bool silent
)
8812 if (tg3_flag(tp
, 5705_PLUS
)) {
8819 /* We can't enable/disable these bits of the
8820 * 5705/5750, just say success.
8833 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
8834 if (pci_channel_offline(tp
->pdev
)) {
8835 dev_err(&tp
->pdev
->dev
,
8836 "tg3_stop_block device offline, "
8837 "ofs=%lx enable_bit=%x\n",
8844 if ((val
& enable_bit
) == 0)
8848 if (i
== MAX_WAIT_CNT
&& !silent
) {
8849 dev_err(&tp
->pdev
->dev
,
8850 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8858 /* tp->lock is held. */
8859 static int tg3_abort_hw(struct tg3
*tp
, bool silent
)
8863 tg3_disable_ints(tp
);
8865 if (pci_channel_offline(tp
->pdev
)) {
8866 tp
->rx_mode
&= ~(RX_MODE_ENABLE
| TX_MODE_ENABLE
);
8867 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
8872 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
8873 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8876 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
8877 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
8878 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
8879 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
8880 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
8881 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
8883 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
8884 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
8885 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
8886 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
8887 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
8888 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
8889 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
8891 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
8892 tw32_f(MAC_MODE
, tp
->mac_mode
);
8895 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
8896 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
8898 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
8900 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
8903 if (i
>= MAX_WAIT_CNT
) {
8904 dev_err(&tp
->pdev
->dev
,
8905 "%s timed out, TX_MODE_ENABLE will not clear "
8906 "MAC_TX_MODE=%08x\n", __func__
, tr32(MAC_TX_MODE
));
8910 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
8911 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
8912 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
8914 tw32(FTQ_RESET
, 0xffffffff);
8915 tw32(FTQ_RESET
, 0x00000000);
8917 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
8918 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
8921 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8922 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8923 if (tnapi
->hw_status
)
8924 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
8930 /* Save PCI command register before chip reset */
8931 static void tg3_save_pci_state(struct tg3
*tp
)
8933 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
8936 /* Restore PCI state after chip reset */
8937 static void tg3_restore_pci_state(struct tg3
*tp
)
8941 /* Re-enable indirect register accesses. */
8942 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
8943 tp
->misc_host_ctrl
);
8945 /* Set MAX PCI retry to zero. */
8946 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
8947 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5704_A0
&&
8948 tg3_flag(tp
, PCIX_MODE
))
8949 val
|= PCISTATE_RETRY_SAME_DMA
;
8950 /* Allow reads and writes to the APE register and memory space. */
8951 if (tg3_flag(tp
, ENABLE_APE
))
8952 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
8953 PCISTATE_ALLOW_APE_SHMEM_WR
|
8954 PCISTATE_ALLOW_APE_PSPACE_WR
;
8955 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
8957 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
8959 if (!tg3_flag(tp
, PCI_EXPRESS
)) {
8960 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
8961 tp
->pci_cacheline_sz
);
8962 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
8966 /* Make sure PCI-X relaxed ordering bit is clear. */
8967 if (tg3_flag(tp
, PCIX_MODE
)) {
8970 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8972 pcix_cmd
&= ~PCI_X_CMD_ERO
;
8973 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8977 if (tg3_flag(tp
, 5780_CLASS
)) {
8979 /* Chip reset on 5780 will reset MSI enable bit,
8980 * so need to restore it.
8982 if (tg3_flag(tp
, USING_MSI
)) {
8985 pci_read_config_word(tp
->pdev
,
8986 tp
->msi_cap
+ PCI_MSI_FLAGS
,
8988 pci_write_config_word(tp
->pdev
,
8989 tp
->msi_cap
+ PCI_MSI_FLAGS
,
8990 ctrl
| PCI_MSI_FLAGS_ENABLE
);
8991 val
= tr32(MSGINT_MODE
);
8992 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
8997 static void tg3_override_clk(struct tg3
*tp
)
9001 switch (tg3_asic_rev(tp
)) {
9003 val
= tr32(TG3_CPMU_CLCK_ORIDE_ENABLE
);
9004 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE
, val
|
9005 TG3_CPMU_MAC_ORIDE_ENABLE
);
9010 tw32(TG3_CPMU_CLCK_ORIDE
, CPMU_CLCK_ORIDE_MAC_ORIDE_EN
);
9018 static void tg3_restore_clk(struct tg3
*tp
)
9022 switch (tg3_asic_rev(tp
)) {
9024 val
= tr32(TG3_CPMU_CLCK_ORIDE_ENABLE
);
9025 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE
,
9026 val
& ~TG3_CPMU_MAC_ORIDE_ENABLE
);
9031 val
= tr32(TG3_CPMU_CLCK_ORIDE
);
9032 tw32(TG3_CPMU_CLCK_ORIDE
, val
& ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN
);
9040 /* tp->lock is held. */
9041 static int tg3_chip_reset(struct tg3
*tp
)
9042 __releases(tp
->lock
)
9043 __acquires(tp
->lock
)
9046 void (*write_op
)(struct tg3
*, u32
, u32
);
9049 if (!pci_device_is_present(tp
->pdev
))
9054 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
9056 /* No matching tg3_nvram_unlock() after this because
9057 * chip reset below will undo the nvram lock.
9059 tp
->nvram_lock_cnt
= 0;
9061 /* GRC_MISC_CFG core clock reset will clear the memory
9062 * enable bit in PCI register 4 and the MSI enable bit
9063 * on some chips, so we save relevant registers here.
9065 tg3_save_pci_state(tp
);
9067 if (tg3_asic_rev(tp
) == ASIC_REV_5752
||
9068 tg3_flag(tp
, 5755_PLUS
))
9069 tw32(GRC_FASTBOOT_PC
, 0);
9072 * We must avoid the readl() that normally takes place.
9073 * It locks machines, causes machine checks, and other
9074 * fun things. So, temporarily disable the 5701
9075 * hardware workaround, while we do the reset.
9077 write_op
= tp
->write32
;
9078 if (write_op
== tg3_write_flush_reg32
)
9079 tp
->write32
= tg3_write32
;
9081 /* Prevent the irq handler from reading or writing PCI registers
9082 * during chip reset when the memory enable bit in the PCI command
9083 * register may be cleared. The chip does not generate interrupt
9084 * at this time, but the irq handler may still be called due to irq
9085 * sharing or irqpoll.
9087 tg3_flag_set(tp
, CHIP_RESETTING
);
9088 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
9089 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9090 if (tnapi
->hw_status
) {
9091 tnapi
->hw_status
->status
= 0;
9092 tnapi
->hw_status
->status_tag
= 0;
9094 tnapi
->last_tag
= 0;
9095 tnapi
->last_irq_tag
= 0;
9099 tg3_full_unlock(tp
);
9101 for (i
= 0; i
< tp
->irq_cnt
; i
++)
9102 synchronize_irq(tp
->napi
[i
].irq_vec
);
9104 tg3_full_lock(tp
, 0);
9106 if (tg3_asic_rev(tp
) == ASIC_REV_57780
) {
9107 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
9108 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
9112 val
= GRC_MISC_CFG_CORECLK_RESET
;
9114 if (tg3_flag(tp
, PCI_EXPRESS
)) {
9115 /* Force PCIe 1.0a mode */
9116 if (tg3_asic_rev(tp
) != ASIC_REV_5785
&&
9117 !tg3_flag(tp
, 57765_PLUS
) &&
9118 tr32(TG3_PCIE_PHY_TSTCTL
) ==
9119 (TG3_PCIE_PHY_TSTCTL_PCIE10
| TG3_PCIE_PHY_TSTCTL_PSCRAM
))
9120 tw32(TG3_PCIE_PHY_TSTCTL
, TG3_PCIE_PHY_TSTCTL_PSCRAM
);
9122 if (tg3_chip_rev_id(tp
) != CHIPREV_ID_5750_A0
) {
9123 tw32(GRC_MISC_CFG
, (1 << 29));
9128 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
9129 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
9130 tw32(GRC_VCPU_EXT_CTRL
,
9131 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
9134 /* Set the clock to the highest frequency to avoid timeouts. With link
9135 * aware mode, the clock speed could be slow and bootcode does not
9136 * complete within the expected time. Override the clock to allow the
9137 * bootcode to finish sooner and then restore it.
9139 tg3_override_clk(tp
);
9141 /* Manage gphy power for all CPMU absent PCIe devices. */
9142 if (tg3_flag(tp
, 5705_PLUS
) && !tg3_flag(tp
, CPMU_PRESENT
))
9143 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
9145 tw32(GRC_MISC_CFG
, val
);
9147 /* restore 5701 hardware bug workaround write method */
9148 tp
->write32
= write_op
;
9150 /* Unfortunately, we have to delay before the PCI read back.
9151 * Some 575X chips even will not respond to a PCI cfg access
9152 * when the reset command is given to the chip.
9154 * How do these hardware designers expect things to work
9155 * properly if the PCI write is posted for a long period
9156 * of time? It is always necessary to have some method by
9157 * which a register read back can occur to push the write
9158 * out which does the reset.
9160 * For most tg3 variants the trick below was working.
9165 /* Flush PCI posted writes. The normal MMIO registers
9166 * are inaccessible at this time so this is the only
9167 * way to make this reliably (actually, this is no longer
9168 * the case, see above). I tried to use indirect
9169 * register read/write but this upset some 5701 variants.
9171 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
9175 if (tg3_flag(tp
, PCI_EXPRESS
) && pci_is_pcie(tp
->pdev
)) {
9178 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5750_A0
) {
9182 /* Wait for link training to complete. */
9183 for (j
= 0; j
< 5000; j
++)
9186 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
9187 pci_write_config_dword(tp
->pdev
, 0xc4,
9188 cfg_val
| (1 << 15));
9191 /* Clear the "no snoop" and "relaxed ordering" bits. */
9192 val16
= PCI_EXP_DEVCTL_RELAX_EN
| PCI_EXP_DEVCTL_NOSNOOP_EN
;
9194 * Older PCIe devices only support the 128 byte
9195 * MPS setting. Enforce the restriction.
9197 if (!tg3_flag(tp
, CPMU_PRESENT
))
9198 val16
|= PCI_EXP_DEVCTL_PAYLOAD
;
9199 pcie_capability_clear_word(tp
->pdev
, PCI_EXP_DEVCTL
, val16
);
9201 /* Clear error status */
9202 pcie_capability_write_word(tp
->pdev
, PCI_EXP_DEVSTA
,
9203 PCI_EXP_DEVSTA_CED
|
9204 PCI_EXP_DEVSTA_NFED
|
9205 PCI_EXP_DEVSTA_FED
|
9206 PCI_EXP_DEVSTA_URD
);
9209 tg3_restore_pci_state(tp
);
9211 tg3_flag_clear(tp
, CHIP_RESETTING
);
9212 tg3_flag_clear(tp
, ERROR_PROCESSED
);
9215 if (tg3_flag(tp
, 5780_CLASS
))
9216 val
= tr32(MEMARB_MODE
);
9217 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
9219 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5750_A3
) {
9221 tw32(0x5000, 0x400);
9224 if (tg3_flag(tp
, IS_SSB_CORE
)) {
9226 * BCM4785: In order to avoid repercussions from using
9227 * potentially defective internal ROM, stop the Rx RISC CPU,
9228 * which is not required.
9231 tg3_halt_cpu(tp
, RX_CPU_BASE
);
9234 err
= tg3_poll_fw(tp
);
9238 tw32(GRC_MODE
, tp
->grc_mode
);
9240 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5705_A0
) {
9243 tw32(0xc4, val
| (1 << 15));
9246 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
9247 tg3_asic_rev(tp
) == ASIC_REV_5705
) {
9248 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
9249 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5705_A0
)
9250 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
9251 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
9254 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
9255 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
9257 } else if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
9258 tp
->mac_mode
= MAC_MODE_PORT_MODE_GMII
;
9263 tw32_f(MAC_MODE
, val
);
9266 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
9270 if (tg3_flag(tp
, PCI_EXPRESS
) &&
9271 tg3_chip_rev_id(tp
) != CHIPREV_ID_5750_A0
&&
9272 tg3_asic_rev(tp
) != ASIC_REV_5785
&&
9273 !tg3_flag(tp
, 57765_PLUS
)) {
9276 tw32(0x7c00, val
| (1 << 25));
9279 tg3_restore_clk(tp
);
9281 /* Reprobe ASF enable state. */
9282 tg3_flag_clear(tp
, ENABLE_ASF
);
9283 tp
->phy_flags
&= ~(TG3_PHYFLG_1G_ON_VAUX_OK
|
9284 TG3_PHYFLG_KEEP_LINK_ON_PWRDN
);
9286 tg3_flag_clear(tp
, ASF_NEW_HANDSHAKE
);
9287 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
9288 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
9291 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
9292 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
9293 tg3_flag_set(tp
, ENABLE_ASF
);
9294 tp
->last_event_jiffies
= jiffies
;
9295 if (tg3_flag(tp
, 5750_PLUS
))
9296 tg3_flag_set(tp
, ASF_NEW_HANDSHAKE
);
9298 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &nic_cfg
);
9299 if (nic_cfg
& NIC_SRAM_1G_ON_VAUX_OK
)
9300 tp
->phy_flags
|= TG3_PHYFLG_1G_ON_VAUX_OK
;
9301 if (nic_cfg
& NIC_SRAM_LNK_FLAP_AVOID
)
9302 tp
->phy_flags
|= TG3_PHYFLG_KEEP_LINK_ON_PWRDN
;
9309 static void tg3_get_nstats(struct tg3
*, struct rtnl_link_stats64
*);
9310 static void tg3_get_estats(struct tg3
*, struct tg3_ethtool_stats
*);
9311 static void __tg3_set_rx_mode(struct net_device
*);
9313 /* tp->lock is held. */
9314 static int tg3_halt(struct tg3
*tp
, int kind
, bool silent
)
9320 tg3_write_sig_pre_reset(tp
, kind
);
9322 tg3_abort_hw(tp
, silent
);
9323 err
= tg3_chip_reset(tp
);
9325 __tg3_set_mac_addr(tp
, false);
9327 tg3_write_sig_legacy(tp
, kind
);
9328 tg3_write_sig_post_reset(tp
, kind
);
9331 /* Save the stats across chip resets... */
9332 tg3_get_nstats(tp
, &tp
->net_stats_prev
);
9333 tg3_get_estats(tp
, &tp
->estats_prev
);
9335 /* And make sure the next sample is new data */
9336 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
9342 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
9344 struct tg3
*tp
= netdev_priv(dev
);
9345 struct sockaddr
*addr
= p
;
9347 bool skip_mac_1
= false;
9349 if (!is_valid_ether_addr(addr
->sa_data
))
9350 return -EADDRNOTAVAIL
;
9352 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
9354 if (!netif_running(dev
))
9357 if (tg3_flag(tp
, ENABLE_ASF
)) {
9358 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
9360 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
9361 addr0_low
= tr32(MAC_ADDR_0_LOW
);
9362 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
9363 addr1_low
= tr32(MAC_ADDR_1_LOW
);
9365 /* Skip MAC addr 1 if ASF is using it. */
9366 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
9367 !(addr1_high
== 0 && addr1_low
== 0))
9370 spin_lock_bh(&tp
->lock
);
9371 __tg3_set_mac_addr(tp
, skip_mac_1
);
9372 __tg3_set_rx_mode(dev
);
9373 spin_unlock_bh(&tp
->lock
);
9378 /* tp->lock is held. */
9379 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
9380 dma_addr_t mapping
, u32 maxlen_flags
,
9384 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
9385 ((u64
) mapping
>> 32));
9387 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
9388 ((u64
) mapping
& 0xffffffff));
9390 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
9393 if (!tg3_flag(tp
, 5705_PLUS
))
9395 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
9400 static void tg3_coal_tx_init(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
9404 if (!tg3_flag(tp
, ENABLE_TSS
)) {
9405 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
9406 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
9407 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
9409 tw32(HOSTCC_TXCOL_TICKS
, 0);
9410 tw32(HOSTCC_TXMAX_FRAMES
, 0);
9411 tw32(HOSTCC_TXCOAL_MAXF_INT
, 0);
9413 for (; i
< tp
->txq_cnt
; i
++) {
9416 reg
= HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18;
9417 tw32(reg
, ec
->tx_coalesce_usecs
);
9418 reg
= HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18;
9419 tw32(reg
, ec
->tx_max_coalesced_frames
);
9420 reg
= HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
9421 tw32(reg
, ec
->tx_max_coalesced_frames_irq
);
9425 for (; i
< tp
->irq_max
- 1; i
++) {
9426 tw32(HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18, 0);
9427 tw32(HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
9428 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
9432 static void tg3_coal_rx_init(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
9435 u32 limit
= tp
->rxq_cnt
;
9437 if (!tg3_flag(tp
, ENABLE_RSS
)) {
9438 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
9439 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
9440 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
9443 tw32(HOSTCC_RXCOL_TICKS
, 0);
9444 tw32(HOSTCC_RXMAX_FRAMES
, 0);
9445 tw32(HOSTCC_RXCOAL_MAXF_INT
, 0);
9448 for (; i
< limit
; i
++) {
9451 reg
= HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18;
9452 tw32(reg
, ec
->rx_coalesce_usecs
);
9453 reg
= HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18;
9454 tw32(reg
, ec
->rx_max_coalesced_frames
);
9455 reg
= HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
9456 tw32(reg
, ec
->rx_max_coalesced_frames_irq
);
9459 for (; i
< tp
->irq_max
- 1; i
++) {
9460 tw32(HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18, 0);
9461 tw32(HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
9462 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
9466 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
9468 tg3_coal_tx_init(tp
, ec
);
9469 tg3_coal_rx_init(tp
, ec
);
9471 if (!tg3_flag(tp
, 5705_PLUS
)) {
9472 u32 val
= ec
->stats_block_coalesce_usecs
;
9474 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
9475 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
9480 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
9484 /* tp->lock is held. */
9485 static void tg3_tx_rcbs_disable(struct tg3
*tp
)
9489 /* Disable all transmit rings but the first. */
9490 if (!tg3_flag(tp
, 5705_PLUS
))
9491 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 16;
9492 else if (tg3_flag(tp
, 5717_PLUS
))
9493 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 4;
9494 else if (tg3_flag(tp
, 57765_CLASS
) ||
9495 tg3_asic_rev(tp
) == ASIC_REV_5762
)
9496 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 2;
9498 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
9500 for (txrcb
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
9501 txrcb
< limit
; txrcb
+= TG3_BDINFO_SIZE
)
9502 tg3_write_mem(tp
, txrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
9503 BDINFO_FLAGS_DISABLED
);
9506 /* tp->lock is held. */
9507 static void tg3_tx_rcbs_init(struct tg3
*tp
)
9510 u32 txrcb
= NIC_SRAM_SEND_RCB
;
9512 if (tg3_flag(tp
, ENABLE_TSS
))
9515 for (; i
< tp
->irq_max
; i
++, txrcb
+= TG3_BDINFO_SIZE
) {
9516 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9518 if (!tnapi
->tx_ring
)
9521 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
9522 (TG3_TX_RING_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
),
9523 NIC_SRAM_TX_BUFFER_DESC
);
9527 /* tp->lock is held. */
9528 static void tg3_rx_ret_rcbs_disable(struct tg3
*tp
)
9532 /* Disable all receive return rings but the first. */
9533 if (tg3_flag(tp
, 5717_PLUS
))
9534 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 17;
9535 else if (!tg3_flag(tp
, 5705_PLUS
))
9536 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 16;
9537 else if (tg3_asic_rev(tp
) == ASIC_REV_5755
||
9538 tg3_asic_rev(tp
) == ASIC_REV_5762
||
9539 tg3_flag(tp
, 57765_CLASS
))
9540 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 4;
9542 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
9544 for (rxrcb
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
9545 rxrcb
< limit
; rxrcb
+= TG3_BDINFO_SIZE
)
9546 tg3_write_mem(tp
, rxrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
9547 BDINFO_FLAGS_DISABLED
);
9550 /* tp->lock is held. */
9551 static void tg3_rx_ret_rcbs_init(struct tg3
*tp
)
9554 u32 rxrcb
= NIC_SRAM_RCV_RET_RCB
;
9556 if (tg3_flag(tp
, ENABLE_RSS
))
9559 for (; i
< tp
->irq_max
; i
++, rxrcb
+= TG3_BDINFO_SIZE
) {
9560 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9565 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
9566 (tp
->rx_ret_ring_mask
+ 1) <<
9567 BDINFO_FLAGS_MAXLEN_SHIFT
, 0);
9571 /* tp->lock is held. */
9572 static void tg3_rings_reset(struct tg3
*tp
)
9576 struct tg3_napi
*tnapi
= &tp
->napi
[0];
9578 tg3_tx_rcbs_disable(tp
);
9580 tg3_rx_ret_rcbs_disable(tp
);
9582 /* Disable interrupts */
9583 tw32_mailbox_f(tp
->napi
[0].int_mbox
, 1);
9584 tp
->napi
[0].chk_msi_cnt
= 0;
9585 tp
->napi
[0].last_rx_cons
= 0;
9586 tp
->napi
[0].last_tx_cons
= 0;
9588 /* Zero mailbox registers. */
9589 if (tg3_flag(tp
, SUPPORT_MSIX
)) {
9590 for (i
= 1; i
< tp
->irq_max
; i
++) {
9591 tp
->napi
[i
].tx_prod
= 0;
9592 tp
->napi
[i
].tx_cons
= 0;
9593 if (tg3_flag(tp
, ENABLE_TSS
))
9594 tw32_mailbox(tp
->napi
[i
].prodmbox
, 0);
9595 tw32_rx_mbox(tp
->napi
[i
].consmbox
, 0);
9596 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 1);
9597 tp
->napi
[i
].chk_msi_cnt
= 0;
9598 tp
->napi
[i
].last_rx_cons
= 0;
9599 tp
->napi
[i
].last_tx_cons
= 0;
9601 if (!tg3_flag(tp
, ENABLE_TSS
))
9602 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
9604 tp
->napi
[0].tx_prod
= 0;
9605 tp
->napi
[0].tx_cons
= 0;
9606 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
9607 tw32_rx_mbox(tp
->napi
[0].consmbox
, 0);
9610 /* Make sure the NIC-based send BD rings are disabled. */
9611 if (!tg3_flag(tp
, 5705_PLUS
)) {
9612 u32 mbox
= MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
9613 for (i
= 0; i
< 16; i
++)
9614 tw32_tx_mbox(mbox
+ i
* 8, 0);
9617 /* Clear status block in ram. */
9618 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
9620 /* Set status block DMA address */
9621 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
9622 ((u64
) tnapi
->status_mapping
>> 32));
9623 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
9624 ((u64
) tnapi
->status_mapping
& 0xffffffff));
9626 stblk
= HOSTCC_STATBLCK_RING1
;
9628 for (i
= 1, tnapi
++; i
< tp
->irq_cnt
; i
++, tnapi
++) {
9629 u64 mapping
= (u64
)tnapi
->status_mapping
;
9630 tw32(stblk
+ TG3_64BIT_REG_HIGH
, mapping
>> 32);
9631 tw32(stblk
+ TG3_64BIT_REG_LOW
, mapping
& 0xffffffff);
9634 /* Clear status block in ram. */
9635 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
9638 tg3_tx_rcbs_init(tp
);
9639 tg3_rx_ret_rcbs_init(tp
);
9642 static void tg3_setup_rxbd_thresholds(struct tg3
*tp
)
9644 u32 val
, bdcache_maxcnt
, host_rep_thresh
, nic_rep_thresh
;
9646 if (!tg3_flag(tp
, 5750_PLUS
) ||
9647 tg3_flag(tp
, 5780_CLASS
) ||
9648 tg3_asic_rev(tp
) == ASIC_REV_5750
||
9649 tg3_asic_rev(tp
) == ASIC_REV_5752
||
9650 tg3_flag(tp
, 57765_PLUS
))
9651 bdcache_maxcnt
= TG3_SRAM_RX_STD_BDCACHE_SIZE_5700
;
9652 else if (tg3_asic_rev(tp
) == ASIC_REV_5755
||
9653 tg3_asic_rev(tp
) == ASIC_REV_5787
)
9654 bdcache_maxcnt
= TG3_SRAM_RX_STD_BDCACHE_SIZE_5755
;
9656 bdcache_maxcnt
= TG3_SRAM_RX_STD_BDCACHE_SIZE_5906
;
9658 nic_rep_thresh
= min(bdcache_maxcnt
/ 2, tp
->rx_std_max_post
);
9659 host_rep_thresh
= max_t(u32
, tp
->rx_pending
/ 8, 1);
9661 val
= min(nic_rep_thresh
, host_rep_thresh
);
9662 tw32(RCVBDI_STD_THRESH
, val
);
9664 if (tg3_flag(tp
, 57765_PLUS
))
9665 tw32(STD_REPLENISH_LWM
, bdcache_maxcnt
);
9667 if (!tg3_flag(tp
, JUMBO_CAPABLE
) || tg3_flag(tp
, 5780_CLASS
))
9670 bdcache_maxcnt
= TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700
;
9672 host_rep_thresh
= max_t(u32
, tp
->rx_jumbo_pending
/ 8, 1);
9674 val
= min(bdcache_maxcnt
/ 2, host_rep_thresh
);
9675 tw32(RCVBDI_JUMBO_THRESH
, val
);
9677 if (tg3_flag(tp
, 57765_PLUS
))
9678 tw32(JMB_REPLENISH_LWM
, bdcache_maxcnt
);
9681 static inline u32
calc_crc(unsigned char *buf
, int len
)
9689 for (j
= 0; j
< len
; j
++) {
9692 for (k
= 0; k
< 8; k
++) {
9705 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
9707 /* accept or reject all multicast frames */
9708 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
9709 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
9710 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
9711 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
9714 static void __tg3_set_rx_mode(struct net_device
*dev
)
9716 struct tg3
*tp
= netdev_priv(dev
);
9719 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
9720 RX_MODE_KEEP_VLAN_TAG
);
9722 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9723 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9726 if (!tg3_flag(tp
, ENABLE_ASF
))
9727 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9730 if (dev
->flags
& IFF_PROMISC
) {
9731 /* Promiscuous mode. */
9732 rx_mode
|= RX_MODE_PROMISC
;
9733 } else if (dev
->flags
& IFF_ALLMULTI
) {
9734 /* Accept all multicast. */
9735 tg3_set_multi(tp
, 1);
9736 } else if (netdev_mc_empty(dev
)) {
9737 /* Reject all multicast. */
9738 tg3_set_multi(tp
, 0);
9740 /* Accept one or more multicast(s). */
9741 struct netdev_hw_addr
*ha
;
9742 u32 mc_filter
[4] = { 0, };
9747 netdev_for_each_mc_addr(ha
, dev
) {
9748 crc
= calc_crc(ha
->addr
, ETH_ALEN
);
9750 regidx
= (bit
& 0x60) >> 5;
9752 mc_filter
[regidx
] |= (1 << bit
);
9755 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
9756 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
9757 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
9758 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
9761 if (netdev_uc_count(dev
) > TG3_MAX_UCAST_ADDR(tp
)) {
9762 rx_mode
|= RX_MODE_PROMISC
;
9763 } else if (!(dev
->flags
& IFF_PROMISC
)) {
9764 /* Add all entries into to the mac addr filter list */
9766 struct netdev_hw_addr
*ha
;
9768 netdev_for_each_uc_addr(ha
, dev
) {
9769 __tg3_set_one_mac_addr(tp
, ha
->addr
,
9770 i
+ TG3_UCAST_ADDR_IDX(tp
));
9775 if (rx_mode
!= tp
->rx_mode
) {
9776 tp
->rx_mode
= rx_mode
;
9777 tw32_f(MAC_RX_MODE
, rx_mode
);
9782 static void tg3_rss_init_dflt_indir_tbl(struct tg3
*tp
, u32 qcnt
)
9786 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++)
9787 tp
->rss_ind_tbl
[i
] = ethtool_rxfh_indir_default(i
, qcnt
);
9790 static void tg3_rss_check_indir_tbl(struct tg3
*tp
)
9794 if (!tg3_flag(tp
, SUPPORT_MSIX
))
9797 if (tp
->rxq_cnt
== 1) {
9798 memset(&tp
->rss_ind_tbl
[0], 0, sizeof(tp
->rss_ind_tbl
));
9802 /* Validate table against current IRQ count */
9803 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++) {
9804 if (tp
->rss_ind_tbl
[i
] >= tp
->rxq_cnt
)
9808 if (i
!= TG3_RSS_INDIR_TBL_SIZE
)
9809 tg3_rss_init_dflt_indir_tbl(tp
, tp
->rxq_cnt
);
9812 static void tg3_rss_write_indir_tbl(struct tg3
*tp
)
9815 u32 reg
= MAC_RSS_INDIR_TBL_0
;
9817 while (i
< TG3_RSS_INDIR_TBL_SIZE
) {
9818 u32 val
= tp
->rss_ind_tbl
[i
];
9820 for (; i
% 8; i
++) {
9822 val
|= tp
->rss_ind_tbl
[i
];
9829 static inline u32
tg3_lso_rd_dma_workaround_bit(struct tg3
*tp
)
9831 if (tg3_asic_rev(tp
) == ASIC_REV_5719
)
9832 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719
;
9834 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720
;
9837 /* tp->lock is held. */
9838 static int tg3_reset_hw(struct tg3
*tp
, bool reset_phy
)
9840 u32 val
, rdmac_mode
;
9842 struct tg3_rx_prodring_set
*tpr
= &tp
->napi
[0].prodring
;
9844 tg3_disable_ints(tp
);
9848 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
9850 if (tg3_flag(tp
, INIT_COMPLETE
))
9851 tg3_abort_hw(tp
, 1);
9853 if ((tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
) &&
9854 !(tp
->phy_flags
& TG3_PHYFLG_USER_CONFIGURED
)) {
9855 tg3_phy_pull_config(tp
);
9856 tg3_eee_pull_config(tp
, NULL
);
9857 tp
->phy_flags
|= TG3_PHYFLG_USER_CONFIGURED
;
9860 /* Enable MAC control of LPI */
9861 if (tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
)
9867 err
= tg3_chip_reset(tp
);
9871 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
9873 if (tg3_chip_rev(tp
) == CHIPREV_5784_AX
) {
9874 val
= tr32(TG3_CPMU_CTRL
);
9875 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
9876 tw32(TG3_CPMU_CTRL
, val
);
9878 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
9879 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
9880 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
9881 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
9883 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
9884 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
9885 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
9886 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
9888 val
= tr32(TG3_CPMU_HST_ACC
);
9889 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
9890 val
|= CPMU_HST_ACC_MACCLK_6_25
;
9891 tw32(TG3_CPMU_HST_ACC
, val
);
9894 if (tg3_asic_rev(tp
) == ASIC_REV_57780
) {
9895 val
= tr32(PCIE_PWR_MGMT_THRESH
) & ~PCIE_PWR_MGMT_L1_THRESH_MSK
;
9896 val
|= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
|
9897 PCIE_PWR_MGMT_L1_THRESH_4MS
;
9898 tw32(PCIE_PWR_MGMT_THRESH
, val
);
9900 val
= tr32(TG3_PCIE_EIDLE_DELAY
) & ~TG3_PCIE_EIDLE_DELAY_MASK
;
9901 tw32(TG3_PCIE_EIDLE_DELAY
, val
| TG3_PCIE_EIDLE_DELAY_13_CLKS
);
9903 tw32(TG3_CORR_ERR_STAT
, TG3_CORR_ERR_STAT_CLEAR
);
9905 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
9906 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
9909 if (tg3_flag(tp
, L1PLLPD_EN
)) {
9910 u32 grc_mode
= tr32(GRC_MODE
);
9912 /* Access the lower 1K of PL PCIE block registers. */
9913 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
9914 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
9916 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
);
9917 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
,
9918 val
| TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN
);
9920 tw32(GRC_MODE
, grc_mode
);
9923 if (tg3_flag(tp
, 57765_CLASS
)) {
9924 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_57765_A0
) {
9925 u32 grc_mode
= tr32(GRC_MODE
);
9927 /* Access the lower 1K of PL PCIE block registers. */
9928 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
9929 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
9931 val
= tr32(TG3_PCIE_TLDLPL_PORT
+
9932 TG3_PCIE_PL_LO_PHYCTL5
);
9933 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
,
9934 val
| TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ
);
9936 tw32(GRC_MODE
, grc_mode
);
9939 if (tg3_chip_rev(tp
) != CHIPREV_57765_AX
) {
9942 /* Fix transmit hangs */
9943 val
= tr32(TG3_CPMU_PADRNG_CTL
);
9944 val
|= TG3_CPMU_PADRNG_CTL_RDIV2
;
9945 tw32(TG3_CPMU_PADRNG_CTL
, val
);
9947 grc_mode
= tr32(GRC_MODE
);
9949 /* Access the lower 1K of DL PCIE block registers. */
9950 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
9951 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_DL_SEL
);
9953 val
= tr32(TG3_PCIE_TLDLPL_PORT
+
9954 TG3_PCIE_DL_LO_FTSMAX
);
9955 val
&= ~TG3_PCIE_DL_LO_FTSMAX_MSK
;
9956 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_DL_LO_FTSMAX
,
9957 val
| TG3_PCIE_DL_LO_FTSMAX_VAL
);
9959 tw32(GRC_MODE
, grc_mode
);
9962 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
9963 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
9964 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
9965 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
9968 /* This works around an issue with Athlon chipsets on
9969 * B3 tigon3 silicon. This bit has no effect on any
9970 * other revision. But do not set this on PCI Express
9971 * chips and don't even touch the clocks if the CPMU is present.
9973 if (!tg3_flag(tp
, CPMU_PRESENT
)) {
9974 if (!tg3_flag(tp
, PCI_EXPRESS
))
9975 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
9976 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
9979 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5704_A0
&&
9980 tg3_flag(tp
, PCIX_MODE
)) {
9981 val
= tr32(TG3PCI_PCISTATE
);
9982 val
|= PCISTATE_RETRY_SAME_DMA
;
9983 tw32(TG3PCI_PCISTATE
, val
);
9986 if (tg3_flag(tp
, ENABLE_APE
)) {
9987 /* Allow reads and writes to the
9988 * APE register and memory space.
9990 val
= tr32(TG3PCI_PCISTATE
);
9991 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
9992 PCISTATE_ALLOW_APE_SHMEM_WR
|
9993 PCISTATE_ALLOW_APE_PSPACE_WR
;
9994 tw32(TG3PCI_PCISTATE
, val
);
9997 if (tg3_chip_rev(tp
) == CHIPREV_5704_BX
) {
9998 /* Enable some hw fixes. */
9999 val
= tr32(TG3PCI_MSI_DATA
);
10000 val
|= (1 << 26) | (1 << 28) | (1 << 29);
10001 tw32(TG3PCI_MSI_DATA
, val
);
10004 /* Descriptor ring init may make accesses to the
10005 * NIC SRAM area to setup the TX descriptors, so we
10006 * can only do this after the hardware has been
10007 * successfully reset.
10009 err
= tg3_init_rings(tp
);
10013 if (tg3_flag(tp
, 57765_PLUS
)) {
10014 val
= tr32(TG3PCI_DMA_RW_CTRL
) &
10015 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
10016 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_57765_A0
)
10017 val
&= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK
;
10018 if (!tg3_flag(tp
, 57765_CLASS
) &&
10019 tg3_asic_rev(tp
) != ASIC_REV_5717
&&
10020 tg3_asic_rev(tp
) != ASIC_REV_5762
)
10021 val
|= DMA_RWCTRL_TAGGED_STAT_WA
;
10022 tw32(TG3PCI_DMA_RW_CTRL
, val
| tp
->dma_rwctrl
);
10023 } else if (tg3_asic_rev(tp
) != ASIC_REV_5784
&&
10024 tg3_asic_rev(tp
) != ASIC_REV_5761
) {
10025 /* This value is determined during the probe time DMA
10026 * engine test, tg3_test_dma.
10028 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
10031 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
10032 GRC_MODE_4X_NIC_SEND_RINGS
|
10033 GRC_MODE_NO_TX_PHDR_CSUM
|
10034 GRC_MODE_NO_RX_PHDR_CSUM
);
10035 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
10037 /* Pseudo-header checksum is done by hardware logic and not
10038 * the offload processers, so make the chip do the pseudo-
10039 * header checksums on receive. For transmit it is more
10040 * convenient to do the pseudo-header checksum in software
10041 * as Linux does that on transmit for us in all cases.
10043 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
10045 val
= GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
;
10047 tw32(TG3_RX_PTP_CTL
,
10048 tp
->rxptpctl
| TG3_RX_PTP_CTL_HWTS_INTERLOCK
);
10050 if (tg3_flag(tp
, PTP_CAPABLE
))
10051 val
|= GRC_MODE_TIME_SYNC_ENABLE
;
10053 tw32(GRC_MODE
, tp
->grc_mode
| val
);
10055 /* On one of the AMD platform, MRRS is restricted to 4000 because of
10056 * south bridge limitation. As a workaround, Driver is setting MRRS
10057 * to 2048 instead of default 4096.
10059 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
10060 tp
->pdev
->subsystem_device
== TG3PCI_SUBDEVICE_ID_DELL_5762
) {
10061 val
= tr32(TG3PCI_DEV_STATUS_CTRL
) & ~MAX_READ_REQ_MASK
;
10062 tw32(TG3PCI_DEV_STATUS_CTRL
, val
| MAX_READ_REQ_SIZE_2048
);
10065 /* Setup the timer prescalar register. Clock is always 66Mhz. */
10066 val
= tr32(GRC_MISC_CFG
);
10068 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
10069 tw32(GRC_MISC_CFG
, val
);
10071 /* Initialize MBUF/DESC pool. */
10072 if (tg3_flag(tp
, 5750_PLUS
)) {
10074 } else if (tg3_asic_rev(tp
) != ASIC_REV_5705
) {
10075 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
10076 if (tg3_asic_rev(tp
) == ASIC_REV_5704
)
10077 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
10079 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
10080 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
10081 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
10082 } else if (tg3_flag(tp
, TSO_CAPABLE
)) {
10085 fw_len
= tp
->fw_len
;
10086 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
10087 tw32(BUFMGR_MB_POOL_ADDR
,
10088 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
10089 tw32(BUFMGR_MB_POOL_SIZE
,
10090 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
10093 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
10094 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
10095 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
10096 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
10097 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
10098 tw32(BUFMGR_MB_HIGH_WATER
,
10099 tp
->bufmgr_config
.mbuf_high_water
);
10101 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
10102 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
10103 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
10104 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
10105 tw32(BUFMGR_MB_HIGH_WATER
,
10106 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
10108 tw32(BUFMGR_DMA_LOW_WATER
,
10109 tp
->bufmgr_config
.dma_low_water
);
10110 tw32(BUFMGR_DMA_HIGH_WATER
,
10111 tp
->bufmgr_config
.dma_high_water
);
10113 val
= BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
;
10114 if (tg3_asic_rev(tp
) == ASIC_REV_5719
)
10115 val
|= BUFMGR_MODE_NO_TX_UNDERRUN
;
10116 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
10117 tg3_asic_rev(tp
) == ASIC_REV_5762
||
10118 tg3_chip_rev_id(tp
) == CHIPREV_ID_5719_A0
||
10119 tg3_chip_rev_id(tp
) == CHIPREV_ID_5720_A0
)
10120 val
|= BUFMGR_MODE_MBLOW_ATTN_ENAB
;
10121 tw32(BUFMGR_MODE
, val
);
10122 for (i
= 0; i
< 2000; i
++) {
10123 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
10128 netdev_err(tp
->dev
, "%s cannot enable BUFMGR\n", __func__
);
10132 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5906_A1
)
10133 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
10135 tg3_setup_rxbd_thresholds(tp
);
10137 /* Initialize TG3_BDINFO's at:
10138 * RCVDBDI_STD_BD: standard eth size rx ring
10139 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10140 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10143 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10144 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10145 * ring attribute flags
10146 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10148 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10149 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10151 * The size of each ring is fixed in the firmware, but the location is
10154 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
10155 ((u64
) tpr
->rx_std_mapping
>> 32));
10156 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
10157 ((u64
) tpr
->rx_std_mapping
& 0xffffffff));
10158 if (!tg3_flag(tp
, 5717_PLUS
))
10159 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
10160 NIC_SRAM_RX_BUFFER_DESC
);
10162 /* Disable the mini ring */
10163 if (!tg3_flag(tp
, 5705_PLUS
))
10164 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
10165 BDINFO_FLAGS_DISABLED
);
10167 /* Program the jumbo buffer descriptor ring control
10168 * blocks on those devices that have them.
10170 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5719_A0
||
10171 (tg3_flag(tp
, JUMBO_CAPABLE
) && !tg3_flag(tp
, 5780_CLASS
))) {
10173 if (tg3_flag(tp
, JUMBO_RING_ENABLE
)) {
10174 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
10175 ((u64
) tpr
->rx_jmb_mapping
>> 32));
10176 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
10177 ((u64
) tpr
->rx_jmb_mapping
& 0xffffffff));
10178 val
= TG3_RX_JMB_RING_SIZE(tp
) <<
10179 BDINFO_FLAGS_MAXLEN_SHIFT
;
10180 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
10181 val
| BDINFO_FLAGS_USE_EXT_RECV
);
10182 if (!tg3_flag(tp
, USE_JUMBO_BDFLAG
) ||
10183 tg3_flag(tp
, 57765_CLASS
) ||
10184 tg3_asic_rev(tp
) == ASIC_REV_5762
)
10185 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
10186 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
10188 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
10189 BDINFO_FLAGS_DISABLED
);
10192 if (tg3_flag(tp
, 57765_PLUS
)) {
10193 val
= TG3_RX_STD_RING_SIZE(tp
);
10194 val
<<= BDINFO_FLAGS_MAXLEN_SHIFT
;
10195 val
|= (TG3_RX_STD_DMA_SZ
<< 2);
10197 val
= TG3_RX_STD_DMA_SZ
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
10199 val
= TG3_RX_STD_MAX_SIZE_5700
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
10201 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
, val
);
10203 tpr
->rx_std_prod_idx
= tp
->rx_pending
;
10204 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
, tpr
->rx_std_prod_idx
);
10206 tpr
->rx_jmb_prod_idx
=
10207 tg3_flag(tp
, JUMBO_RING_ENABLE
) ? tp
->rx_jumbo_pending
: 0;
10208 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
, tpr
->rx_jmb_prod_idx
);
10210 tg3_rings_reset(tp
);
10212 /* Initialize MAC address and backoff seed. */
10213 __tg3_set_mac_addr(tp
, false);
10215 /* MTU + ethernet header + FCS + optional VLAN tag */
10216 tw32(MAC_RX_MTU_SIZE
,
10217 tp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
);
10219 /* The slot time is changed by tg3_setup_phy if we
10220 * run at gigabit with half duplex.
10222 val
= (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
10223 (6 << TX_LENGTHS_IPG_SHIFT
) |
10224 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
);
10226 if (tg3_asic_rev(tp
) == ASIC_REV_5720
||
10227 tg3_asic_rev(tp
) == ASIC_REV_5762
)
10228 val
|= tr32(MAC_TX_LENGTHS
) &
10229 (TX_LENGTHS_JMB_FRM_LEN_MSK
|
10230 TX_LENGTHS_CNT_DWN_VAL_MSK
);
10232 tw32(MAC_TX_LENGTHS
, val
);
10234 /* Receive rules. */
10235 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
10236 tw32(RCVLPC_CONFIG
, 0x0181);
10238 /* Calculate RDMAC_MODE setting early, we need it to determine
10239 * the RCVLPC_STATE_ENABLE mask.
10241 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
10242 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
10243 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
10244 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
10245 RDMAC_MODE_LNGREAD_ENAB
);
10247 if (tg3_asic_rev(tp
) == ASIC_REV_5717
)
10248 rdmac_mode
|= RDMAC_MODE_MULT_DMA_RD_DIS
;
10250 if (tg3_asic_rev(tp
) == ASIC_REV_5784
||
10251 tg3_asic_rev(tp
) == ASIC_REV_5785
||
10252 tg3_asic_rev(tp
) == ASIC_REV_57780
)
10253 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
10254 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
10255 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
10257 if (tg3_asic_rev(tp
) == ASIC_REV_5705
&&
10258 tg3_chip_rev_id(tp
) != CHIPREV_ID_5705_A0
) {
10259 if (tg3_flag(tp
, TSO_CAPABLE
) &&
10260 tg3_asic_rev(tp
) == ASIC_REV_5705
) {
10261 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
10262 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
10263 !tg3_flag(tp
, IS_5788
)) {
10264 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
10268 if (tg3_flag(tp
, PCI_EXPRESS
))
10269 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
10271 if (tg3_asic_rev(tp
) == ASIC_REV_57766
) {
10273 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
10274 rdmac_mode
|= RDMAC_MODE_JMB_2K_MMRR
;
10275 tp
->dma_limit
= TG3_TX_BD_DMA_MAX_2K
;
10279 if (tg3_flag(tp
, HW_TSO_1
) ||
10280 tg3_flag(tp
, HW_TSO_2
) ||
10281 tg3_flag(tp
, HW_TSO_3
))
10282 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
10284 if (tg3_flag(tp
, 57765_PLUS
) ||
10285 tg3_asic_rev(tp
) == ASIC_REV_5785
||
10286 tg3_asic_rev(tp
) == ASIC_REV_57780
)
10287 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
10289 if (tg3_asic_rev(tp
) == ASIC_REV_5720
||
10290 tg3_asic_rev(tp
) == ASIC_REV_5762
)
10291 rdmac_mode
|= tr32(RDMAC_MODE
) & RDMAC_MODE_H2BNC_VLAN_DET
;
10293 if (tg3_asic_rev(tp
) == ASIC_REV_5761
||
10294 tg3_asic_rev(tp
) == ASIC_REV_5784
||
10295 tg3_asic_rev(tp
) == ASIC_REV_5785
||
10296 tg3_asic_rev(tp
) == ASIC_REV_57780
||
10297 tg3_flag(tp
, 57765_PLUS
)) {
10300 if (tg3_asic_rev(tp
) == ASIC_REV_5762
)
10301 tgtreg
= TG3_RDMA_RSRVCTRL_REG2
;
10303 tgtreg
= TG3_RDMA_RSRVCTRL_REG
;
10305 val
= tr32(tgtreg
);
10306 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5719_A0
||
10307 tg3_asic_rev(tp
) == ASIC_REV_5762
) {
10308 val
&= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK
|
10309 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK
|
10310 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK
);
10311 val
|= TG3_RDMA_RSRVCTRL_TXMRGN_320B
|
10312 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K
|
10313 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K
;
10315 tw32(tgtreg
, val
| TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX
);
10318 if (tg3_asic_rev(tp
) == ASIC_REV_5719
||
10319 tg3_asic_rev(tp
) == ASIC_REV_5720
||
10320 tg3_asic_rev(tp
) == ASIC_REV_5762
) {
10323 if (tg3_asic_rev(tp
) == ASIC_REV_5762
)
10324 tgtreg
= TG3_LSO_RD_DMA_CRPTEN_CTRL2
;
10326 tgtreg
= TG3_LSO_RD_DMA_CRPTEN_CTRL
;
10328 val
= tr32(tgtreg
);
10330 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K
|
10331 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K
);
10334 /* Receive/send statistics. */
10335 if (tg3_flag(tp
, 5750_PLUS
)) {
10336 val
= tr32(RCVLPC_STATS_ENABLE
);
10337 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
10338 tw32(RCVLPC_STATS_ENABLE
, val
);
10339 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
10340 tg3_flag(tp
, TSO_CAPABLE
)) {
10341 val
= tr32(RCVLPC_STATS_ENABLE
);
10342 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
10343 tw32(RCVLPC_STATS_ENABLE
, val
);
10345 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
10347 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
10348 tw32(SNDDATAI_STATSENAB
, 0xffffff);
10349 tw32(SNDDATAI_STATSCTRL
,
10350 (SNDDATAI_SCTRL_ENABLE
|
10351 SNDDATAI_SCTRL_FASTUPD
));
10353 /* Setup host coalescing engine. */
10354 tw32(HOSTCC_MODE
, 0);
10355 for (i
= 0; i
< 2000; i
++) {
10356 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
10361 __tg3_set_coalesce(tp
, &tp
->coal
);
10363 if (!tg3_flag(tp
, 5705_PLUS
)) {
10364 /* Status/statistics block address. See tg3_timer,
10365 * the tg3_periodic_fetch_stats call there, and
10366 * tg3_get_stats to see how this works for 5705/5750 chips.
10368 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
10369 ((u64
) tp
->stats_mapping
>> 32));
10370 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
10371 ((u64
) tp
->stats_mapping
& 0xffffffff));
10372 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
10374 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
10376 /* Clear statistics and status block memory areas */
10377 for (i
= NIC_SRAM_STATS_BLK
;
10378 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
10379 i
+= sizeof(u32
)) {
10380 tg3_write_mem(tp
, i
, 0);
10385 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
10387 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
10388 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
10389 if (!tg3_flag(tp
, 5705_PLUS
))
10390 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
10392 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
10393 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
10394 /* reset to prevent losing 1st rx packet intermittently */
10395 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
10399 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
10400 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
|
10401 MAC_MODE_FHDE_ENABLE
;
10402 if (tg3_flag(tp
, ENABLE_APE
))
10403 tp
->mac_mode
|= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
10404 if (!tg3_flag(tp
, 5705_PLUS
) &&
10405 !(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
10406 tg3_asic_rev(tp
) != ASIC_REV_5700
)
10407 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
10408 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
10411 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10412 * If TG3_FLAG_IS_NIC is zero, we should read the
10413 * register to preserve the GPIO settings for LOMs. The GPIOs,
10414 * whether used as inputs or outputs, are set by boot code after
10417 if (!tg3_flag(tp
, IS_NIC
)) {
10420 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
10421 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
10422 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
10424 if (tg3_asic_rev(tp
) == ASIC_REV_5752
)
10425 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
10426 GRC_LCLCTRL_GPIO_OUTPUT3
;
10428 if (tg3_asic_rev(tp
) == ASIC_REV_5755
)
10429 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
10431 tp
->grc_local_ctrl
&= ~gpio_mask
;
10432 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
10434 /* GPIO1 must be driven high for eeprom write protect */
10435 if (tg3_flag(tp
, EEPROM_WRITE_PROT
))
10436 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
10437 GRC_LCLCTRL_GPIO_OUTPUT1
);
10439 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
10442 if (tg3_flag(tp
, USING_MSIX
)) {
10443 val
= tr32(MSGINT_MODE
);
10444 val
|= MSGINT_MODE_ENABLE
;
10445 if (tp
->irq_cnt
> 1)
10446 val
|= MSGINT_MODE_MULTIVEC_EN
;
10447 if (!tg3_flag(tp
, 1SHOT_MSI
))
10448 val
|= MSGINT_MODE_ONE_SHOT_DISABLE
;
10449 tw32(MSGINT_MODE
, val
);
10452 if (!tg3_flag(tp
, 5705_PLUS
)) {
10453 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
10457 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
10458 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
10459 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
10460 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
10461 WDMAC_MODE_LNGREAD_ENAB
);
10463 if (tg3_asic_rev(tp
) == ASIC_REV_5705
&&
10464 tg3_chip_rev_id(tp
) != CHIPREV_ID_5705_A0
) {
10465 if (tg3_flag(tp
, TSO_CAPABLE
) &&
10466 (tg3_chip_rev_id(tp
) == CHIPREV_ID_5705_A1
||
10467 tg3_chip_rev_id(tp
) == CHIPREV_ID_5705_A2
)) {
10469 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
10470 !tg3_flag(tp
, IS_5788
)) {
10471 val
|= WDMAC_MODE_RX_ACCEL
;
10475 /* Enable host coalescing bug fix */
10476 if (tg3_flag(tp
, 5755_PLUS
))
10477 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
10479 if (tg3_asic_rev(tp
) == ASIC_REV_5785
)
10480 val
|= WDMAC_MODE_BURST_ALL_DATA
;
10482 tw32_f(WDMAC_MODE
, val
);
10485 if (tg3_flag(tp
, PCIX_MODE
)) {
10488 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
10490 if (tg3_asic_rev(tp
) == ASIC_REV_5703
) {
10491 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
10492 pcix_cmd
|= PCI_X_CMD_READ_2K
;
10493 } else if (tg3_asic_rev(tp
) == ASIC_REV_5704
) {
10494 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
10495 pcix_cmd
|= PCI_X_CMD_READ_2K
;
10497 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
10501 tw32_f(RDMAC_MODE
, rdmac_mode
);
10504 if (tg3_asic_rev(tp
) == ASIC_REV_5719
||
10505 tg3_asic_rev(tp
) == ASIC_REV_5720
) {
10506 for (i
= 0; i
< TG3_NUM_RDMA_CHANNELS
; i
++) {
10507 if (tr32(TG3_RDMA_LENGTH
+ (i
<< 2)) > TG3_MAX_MTU(tp
))
10510 if (i
< TG3_NUM_RDMA_CHANNELS
) {
10511 val
= tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL
);
10512 val
|= tg3_lso_rd_dma_workaround_bit(tp
);
10513 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL
, val
);
10514 tg3_flag_set(tp
, 5719_5720_RDMA_BUG
);
10518 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
10519 if (!tg3_flag(tp
, 5705_PLUS
))
10520 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
10522 if (tg3_asic_rev(tp
) == ASIC_REV_5761
)
10523 tw32(SNDDATAC_MODE
,
10524 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
10526 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
10528 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
10529 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
10530 val
= RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
;
10531 if (tg3_flag(tp
, LRG_PROD_RING_CAP
))
10532 val
|= RCVDBDI_MODE_LRG_RING_SZ
;
10533 tw32(RCVDBDI_MODE
, val
);
10534 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
10535 if (tg3_flag(tp
, HW_TSO_1
) ||
10536 tg3_flag(tp
, HW_TSO_2
) ||
10537 tg3_flag(tp
, HW_TSO_3
))
10538 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
10539 val
= SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
;
10540 if (tg3_flag(tp
, ENABLE_TSS
))
10541 val
|= SNDBDI_MODE_MULTI_TXQ_EN
;
10542 tw32(SNDBDI_MODE
, val
);
10543 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
10545 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
) {
10546 err
= tg3_load_5701_a0_firmware_fix(tp
);
10551 if (tg3_asic_rev(tp
) == ASIC_REV_57766
) {
10552 /* Ignore any errors for the firmware download. If download
10553 * fails, the device will operate with EEE disabled
10555 tg3_load_57766_firmware(tp
);
10558 if (tg3_flag(tp
, TSO_CAPABLE
)) {
10559 err
= tg3_load_tso_firmware(tp
);
10564 tp
->tx_mode
= TX_MODE_ENABLE
;
10566 if (tg3_flag(tp
, 5755_PLUS
) ||
10567 tg3_asic_rev(tp
) == ASIC_REV_5906
)
10568 tp
->tx_mode
|= TX_MODE_MBUF_LOCKUP_FIX
;
10570 if (tg3_asic_rev(tp
) == ASIC_REV_5720
||
10571 tg3_asic_rev(tp
) == ASIC_REV_5762
) {
10572 val
= TX_MODE_JMB_FRM_LEN
| TX_MODE_CNT_DN_MODE
;
10573 tp
->tx_mode
&= ~val
;
10574 tp
->tx_mode
|= tr32(MAC_TX_MODE
) & val
;
10577 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
10580 if (tg3_flag(tp
, ENABLE_RSS
)) {
10583 tg3_rss_write_indir_tbl(tp
);
10585 netdev_rss_key_fill(rss_key
, 10 * sizeof(u32
));
10587 for (i
= 0; i
< 10 ; i
++)
10588 tw32(MAC_RSS_HASH_KEY_0
+ i
*4, rss_key
[i
]);
10591 tp
->rx_mode
= RX_MODE_ENABLE
;
10592 if (tg3_flag(tp
, 5755_PLUS
))
10593 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
10595 if (tg3_asic_rev(tp
) == ASIC_REV_5762
)
10596 tp
->rx_mode
|= RX_MODE_IPV4_FRAG_FIX
;
10598 if (tg3_flag(tp
, ENABLE_RSS
))
10599 tp
->rx_mode
|= RX_MODE_RSS_ENABLE
|
10600 RX_MODE_RSS_ITBL_HASH_BITS_7
|
10601 RX_MODE_RSS_IPV6_HASH_EN
|
10602 RX_MODE_RSS_TCP_IPV6_HASH_EN
|
10603 RX_MODE_RSS_IPV4_HASH_EN
|
10604 RX_MODE_RSS_TCP_IPV4_HASH_EN
;
10606 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
10609 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
10611 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
10612 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
10613 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
10616 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
10619 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
10620 if ((tg3_asic_rev(tp
) == ASIC_REV_5704
) &&
10621 !(tp
->phy_flags
& TG3_PHYFLG_SERDES_PREEMPHASIS
)) {
10622 /* Set drive transmission level to 1.2V */
10623 /* only if the signal pre-emphasis bit is not set */
10624 val
= tr32(MAC_SERDES_CFG
);
10627 tw32(MAC_SERDES_CFG
, val
);
10629 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5703_A1
)
10630 tw32(MAC_SERDES_CFG
, 0x616000);
10633 /* Prevent chip from dropping frames when flow control
10636 if (tg3_flag(tp
, 57765_CLASS
))
10640 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, val
);
10642 if (tg3_asic_rev(tp
) == ASIC_REV_5704
&&
10643 (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
10644 /* Use hardware link auto-negotiation */
10645 tg3_flag_set(tp
, HW_AUTONEG
);
10648 if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
10649 tg3_asic_rev(tp
) == ASIC_REV_5714
) {
10652 tmp
= tr32(SERDES_RX_CTRL
);
10653 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
10654 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
10655 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
10656 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
10659 if (!tg3_flag(tp
, USE_PHYLIB
)) {
10660 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
10661 tp
->phy_flags
&= ~TG3_PHYFLG_IS_LOW_POWER
;
10663 err
= tg3_setup_phy(tp
, false);
10667 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
10668 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
)) {
10671 /* Clear CRC stats. */
10672 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
10673 tg3_writephy(tp
, MII_TG3_TEST1
,
10674 tmp
| MII_TG3_TEST1_CRC_EN
);
10675 tg3_readphy(tp
, MII_TG3_RXR_COUNTERS
, &tmp
);
10680 __tg3_set_rx_mode(tp
->dev
);
10682 /* Initialize receive rules. */
10683 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
10684 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
10685 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
10686 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
10688 if (tg3_flag(tp
, 5705_PLUS
) && !tg3_flag(tp
, 5780_CLASS
))
10692 if (tg3_flag(tp
, ENABLE_ASF
))
10696 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
10698 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
10700 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
10702 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
10704 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
10706 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
10708 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
10710 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
10712 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
10714 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
10716 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
10718 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
10720 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10722 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10730 if (tg3_flag(tp
, ENABLE_APE
))
10731 /* Write our heartbeat update interval to APE. */
10732 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
10733 APE_HOST_HEARTBEAT_INT_DISABLE
);
10735 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
10740 /* Called at device open time to get the chip ready for
10741 * packet processing. Invoked with tp->lock held.
10743 static int tg3_init_hw(struct tg3
*tp
, bool reset_phy
)
10745 /* Chip may have been just powered on. If so, the boot code may still
10746 * be running initialization. Wait for it to finish to avoid races in
10747 * accessing the hardware.
10749 tg3_enable_register_access(tp
);
10752 tg3_switch_clocks(tp
);
10754 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
10756 return tg3_reset_hw(tp
, reset_phy
);
10759 #ifdef CONFIG_TIGON3_HWMON
10760 static void tg3_sd_scan_scratchpad(struct tg3
*tp
, struct tg3_ocir
*ocir
)
10764 for (i
= 0; i
< TG3_SD_NUM_RECS
; i
++, ocir
++) {
10765 u32 off
= i
* TG3_OCIR_LEN
, len
= TG3_OCIR_LEN
;
10767 tg3_ape_scratchpad_read(tp
, (u32
*) ocir
, off
, len
);
10770 if (ocir
->signature
!= TG3_OCIR_SIG_MAGIC
||
10771 !(ocir
->version_flags
& TG3_OCIR_FLAG_ACTIVE
))
10772 memset(ocir
, 0, TG3_OCIR_LEN
);
10776 /* sysfs attributes for hwmon */
10777 static ssize_t
tg3_show_temp(struct device
*dev
,
10778 struct device_attribute
*devattr
, char *buf
)
10780 struct sensor_device_attribute
*attr
= to_sensor_dev_attr(devattr
);
10781 struct tg3
*tp
= dev_get_drvdata(dev
);
10784 spin_lock_bh(&tp
->lock
);
10785 tg3_ape_scratchpad_read(tp
, &temperature
, attr
->index
,
10786 sizeof(temperature
));
10787 spin_unlock_bh(&tp
->lock
);
10788 return sprintf(buf
, "%u\n", temperature
* 1000);
10792 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, tg3_show_temp
, NULL
,
10793 TG3_TEMP_SENSOR_OFFSET
);
10794 static SENSOR_DEVICE_ATTR(temp1_crit
, S_IRUGO
, tg3_show_temp
, NULL
,
10795 TG3_TEMP_CAUTION_OFFSET
);
10796 static SENSOR_DEVICE_ATTR(temp1_max
, S_IRUGO
, tg3_show_temp
, NULL
,
10797 TG3_TEMP_MAX_OFFSET
);
10799 static struct attribute
*tg3_attrs
[] = {
10800 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
10801 &sensor_dev_attr_temp1_crit
.dev_attr
.attr
,
10802 &sensor_dev_attr_temp1_max
.dev_attr
.attr
,
10805 ATTRIBUTE_GROUPS(tg3
);
10807 static void tg3_hwmon_close(struct tg3
*tp
)
10809 if (tp
->hwmon_dev
) {
10810 hwmon_device_unregister(tp
->hwmon_dev
);
10811 tp
->hwmon_dev
= NULL
;
10815 static void tg3_hwmon_open(struct tg3
*tp
)
10819 struct pci_dev
*pdev
= tp
->pdev
;
10820 struct tg3_ocir ocirs
[TG3_SD_NUM_RECS
];
10822 tg3_sd_scan_scratchpad(tp
, ocirs
);
10824 for (i
= 0; i
< TG3_SD_NUM_RECS
; i
++) {
10825 if (!ocirs
[i
].src_data_length
)
10828 size
+= ocirs
[i
].src_hdr_length
;
10829 size
+= ocirs
[i
].src_data_length
;
10835 tp
->hwmon_dev
= hwmon_device_register_with_groups(&pdev
->dev
, "tg3",
10837 if (IS_ERR(tp
->hwmon_dev
)) {
10838 tp
->hwmon_dev
= NULL
;
10839 dev_err(&pdev
->dev
, "Cannot register hwmon device, aborting\n");
10843 static inline void tg3_hwmon_close(struct tg3
*tp
) { }
10844 static inline void tg3_hwmon_open(struct tg3
*tp
) { }
10845 #endif /* CONFIG_TIGON3_HWMON */
10848 #define TG3_STAT_ADD32(PSTAT, REG) \
10849 do { u32 __val = tr32(REG); \
10850 (PSTAT)->low += __val; \
10851 if ((PSTAT)->low < __val) \
10852 (PSTAT)->high += 1; \
10855 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
10857 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
10862 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
10863 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
10864 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
10865 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
10866 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
10867 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
10868 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
10869 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
10870 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
10871 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
10872 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
10873 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
10874 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
10875 if (unlikely(tg3_flag(tp
, 5719_5720_RDMA_BUG
) &&
10876 (sp
->tx_ucast_packets
.low
+ sp
->tx_mcast_packets
.low
+
10877 sp
->tx_bcast_packets
.low
) > TG3_NUM_RDMA_CHANNELS
)) {
10880 val
= tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL
);
10881 val
&= ~tg3_lso_rd_dma_workaround_bit(tp
);
10882 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL
, val
);
10883 tg3_flag_clear(tp
, 5719_5720_RDMA_BUG
);
10886 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
10887 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
10888 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
10889 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
10890 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
10891 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
10892 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
10893 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
10894 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
10895 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
10896 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
10897 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
10898 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
10899 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
10901 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
10902 if (tg3_asic_rev(tp
) != ASIC_REV_5717
&&
10903 tg3_asic_rev(tp
) != ASIC_REV_5762
&&
10904 tg3_chip_rev_id(tp
) != CHIPREV_ID_5719_A0
&&
10905 tg3_chip_rev_id(tp
) != CHIPREV_ID_5720_A0
) {
10906 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
10908 u32 val
= tr32(HOSTCC_FLOW_ATTN
);
10909 val
= (val
& HOSTCC_FLOW_ATTN_MBUF_LWM
) ? 1 : 0;
10911 tw32(HOSTCC_FLOW_ATTN
, HOSTCC_FLOW_ATTN_MBUF_LWM
);
10912 sp
->rx_discards
.low
+= val
;
10913 if (sp
->rx_discards
.low
< val
)
10914 sp
->rx_discards
.high
+= 1;
10916 sp
->mbuf_lwm_thresh_hit
= sp
->rx_discards
;
10918 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
10921 static void tg3_chk_missed_msi(struct tg3
*tp
)
10925 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
10926 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
10928 if (tg3_has_work(tnapi
)) {
10929 if (tnapi
->last_rx_cons
== tnapi
->rx_rcb_ptr
&&
10930 tnapi
->last_tx_cons
== tnapi
->tx_cons
) {
10931 if (tnapi
->chk_msi_cnt
< 1) {
10932 tnapi
->chk_msi_cnt
++;
10938 tnapi
->chk_msi_cnt
= 0;
10939 tnapi
->last_rx_cons
= tnapi
->rx_rcb_ptr
;
10940 tnapi
->last_tx_cons
= tnapi
->tx_cons
;
10944 static void tg3_timer(unsigned long __opaque
)
10946 struct tg3
*tp
= (struct tg3
*) __opaque
;
10948 spin_lock(&tp
->lock
);
10950 if (tp
->irq_sync
|| tg3_flag(tp
, RESET_TASK_PENDING
)) {
10951 spin_unlock(&tp
->lock
);
10952 goto restart_timer
;
10955 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
10956 tg3_flag(tp
, 57765_CLASS
))
10957 tg3_chk_missed_msi(tp
);
10959 if (tg3_flag(tp
, FLUSH_POSTED_WRITES
)) {
10960 /* BCM4785: Flush posted writes from GbE to host memory. */
10964 if (!tg3_flag(tp
, TAGGED_STATUS
)) {
10965 /* All of this garbage is because when using non-tagged
10966 * IRQ status the mailbox/status_block protocol the chip
10967 * uses with the cpu is race prone.
10969 if (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
) {
10970 tw32(GRC_LOCAL_CTRL
,
10971 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
10973 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
10974 HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
);
10977 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
10978 spin_unlock(&tp
->lock
);
10979 tg3_reset_task_schedule(tp
);
10980 goto restart_timer
;
10984 /* This part only runs once per second. */
10985 if (!--tp
->timer_counter
) {
10986 if (tg3_flag(tp
, 5705_PLUS
))
10987 tg3_periodic_fetch_stats(tp
);
10989 if (tp
->setlpicnt
&& !--tp
->setlpicnt
)
10990 tg3_phy_eee_enable(tp
);
10992 if (tg3_flag(tp
, USE_LINKCHG_REG
)) {
10996 mac_stat
= tr32(MAC_STATUS
);
10999 if (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
) {
11000 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
11002 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
11006 tg3_setup_phy(tp
, false);
11007 } else if (tg3_flag(tp
, POLL_SERDES
)) {
11008 u32 mac_stat
= tr32(MAC_STATUS
);
11009 int need_setup
= 0;
11012 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
11015 if (!tp
->link_up
&&
11016 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
11017 MAC_STATUS_SIGNAL_DET
))) {
11021 if (!tp
->serdes_counter
) {
11024 ~MAC_MODE_PORT_MODE_MASK
));
11026 tw32_f(MAC_MODE
, tp
->mac_mode
);
11029 tg3_setup_phy(tp
, false);
11031 } else if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
11032 tg3_flag(tp
, 5780_CLASS
)) {
11033 tg3_serdes_parallel_detect(tp
);
11034 } else if (tg3_flag(tp
, POLL_CPMU_LINK
)) {
11035 u32 cpmu
= tr32(TG3_CPMU_STATUS
);
11036 bool link_up
= !((cpmu
& TG3_CPMU_STATUS_LINK_MASK
) ==
11037 TG3_CPMU_STATUS_LINK_MASK
);
11039 if (link_up
!= tp
->link_up
)
11040 tg3_setup_phy(tp
, false);
11043 tp
->timer_counter
= tp
->timer_multiplier
;
11046 /* Heartbeat is only sent once every 2 seconds.
11048 * The heartbeat is to tell the ASF firmware that the host
11049 * driver is still alive. In the event that the OS crashes,
11050 * ASF needs to reset the hardware to free up the FIFO space
11051 * that may be filled with rx packets destined for the host.
11052 * If the FIFO is full, ASF will no longer function properly.
11054 * Unintended resets have been reported on real time kernels
11055 * where the timer doesn't run on time. Netpoll will also have
11058 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
11059 * to check the ring condition when the heartbeat is expiring
11060 * before doing the reset. This will prevent most unintended
11063 if (!--tp
->asf_counter
) {
11064 if (tg3_flag(tp
, ENABLE_ASF
) && !tg3_flag(tp
, ENABLE_APE
)) {
11065 tg3_wait_for_event_ack(tp
);
11067 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
11068 FWCMD_NICDRV_ALIVE3
);
11069 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
11070 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
,
11071 TG3_FW_UPDATE_TIMEOUT_SEC
);
11073 tg3_generate_fw_event(tp
);
11075 tp
->asf_counter
= tp
->asf_multiplier
;
11078 spin_unlock(&tp
->lock
);
11081 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
11082 add_timer(&tp
->timer
);
11085 static void tg3_timer_init(struct tg3
*tp
)
11087 if (tg3_flag(tp
, TAGGED_STATUS
) &&
11088 tg3_asic_rev(tp
) != ASIC_REV_5717
&&
11089 !tg3_flag(tp
, 57765_CLASS
))
11090 tp
->timer_offset
= HZ
;
11092 tp
->timer_offset
= HZ
/ 10;
11094 BUG_ON(tp
->timer_offset
> HZ
);
11096 tp
->timer_multiplier
= (HZ
/ tp
->timer_offset
);
11097 tp
->asf_multiplier
= (HZ
/ tp
->timer_offset
) *
11098 TG3_FW_UPDATE_FREQ_SEC
;
11100 init_timer(&tp
->timer
);
11101 tp
->timer
.data
= (unsigned long) tp
;
11102 tp
->timer
.function
= tg3_timer
;
11105 static void tg3_timer_start(struct tg3
*tp
)
11107 tp
->asf_counter
= tp
->asf_multiplier
;
11108 tp
->timer_counter
= tp
->timer_multiplier
;
11110 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
11111 add_timer(&tp
->timer
);
11114 static void tg3_timer_stop(struct tg3
*tp
)
11116 del_timer_sync(&tp
->timer
);
11119 /* Restart hardware after configuration changes, self-test, etc.
11120 * Invoked with tp->lock held.
11122 static int tg3_restart_hw(struct tg3
*tp
, bool reset_phy
)
11123 __releases(tp
->lock
)
11124 __acquires(tp
->lock
)
11128 err
= tg3_init_hw(tp
, reset_phy
);
11130 netdev_err(tp
->dev
,
11131 "Failed to re-initialize device, aborting\n");
11132 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
11133 tg3_full_unlock(tp
);
11134 tg3_timer_stop(tp
);
11136 tg3_napi_enable(tp
);
11137 dev_close(tp
->dev
);
11138 tg3_full_lock(tp
, 0);
11143 static void tg3_reset_task(struct work_struct
*work
)
11145 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
11149 tg3_full_lock(tp
, 0);
11151 if (!netif_running(tp
->dev
)) {
11152 tg3_flag_clear(tp
, RESET_TASK_PENDING
);
11153 tg3_full_unlock(tp
);
11158 tg3_full_unlock(tp
);
11162 tg3_netif_stop(tp
);
11164 tg3_full_lock(tp
, 1);
11166 if (tg3_flag(tp
, TX_RECOVERY_PENDING
)) {
11167 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
11168 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
11169 tg3_flag_set(tp
, MBOX_WRITE_REORDER
);
11170 tg3_flag_clear(tp
, TX_RECOVERY_PENDING
);
11173 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
11174 err
= tg3_init_hw(tp
, true);
11178 tg3_netif_start(tp
);
11181 tg3_full_unlock(tp
);
11186 tg3_flag_clear(tp
, RESET_TASK_PENDING
);
11190 static int tg3_request_irq(struct tg3
*tp
, int irq_num
)
11193 unsigned long flags
;
11195 struct tg3_napi
*tnapi
= &tp
->napi
[irq_num
];
11197 if (tp
->irq_cnt
== 1)
11198 name
= tp
->dev
->name
;
11200 name
= &tnapi
->irq_lbl
[0];
11201 if (tnapi
->tx_buffers
&& tnapi
->rx_rcb
)
11202 snprintf(name
, IFNAMSIZ
,
11203 "%s-txrx-%d", tp
->dev
->name
, irq_num
);
11204 else if (tnapi
->tx_buffers
)
11205 snprintf(name
, IFNAMSIZ
,
11206 "%s-tx-%d", tp
->dev
->name
, irq_num
);
11207 else if (tnapi
->rx_rcb
)
11208 snprintf(name
, IFNAMSIZ
,
11209 "%s-rx-%d", tp
->dev
->name
, irq_num
);
11211 snprintf(name
, IFNAMSIZ
,
11212 "%s-%d", tp
->dev
->name
, irq_num
);
11213 name
[IFNAMSIZ
-1] = 0;
11216 if (tg3_flag(tp
, USING_MSI
) || tg3_flag(tp
, USING_MSIX
)) {
11218 if (tg3_flag(tp
, 1SHOT_MSI
))
11219 fn
= tg3_msi_1shot
;
11222 fn
= tg3_interrupt
;
11223 if (tg3_flag(tp
, TAGGED_STATUS
))
11224 fn
= tg3_interrupt_tagged
;
11225 flags
= IRQF_SHARED
;
11228 return request_irq(tnapi
->irq_vec
, fn
, flags
, name
, tnapi
);
11231 static int tg3_test_interrupt(struct tg3
*tp
)
11233 struct tg3_napi
*tnapi
= &tp
->napi
[0];
11234 struct net_device
*dev
= tp
->dev
;
11235 int err
, i
, intr_ok
= 0;
11238 if (!netif_running(dev
))
11241 tg3_disable_ints(tp
);
11243 free_irq(tnapi
->irq_vec
, tnapi
);
11246 * Turn off MSI one shot mode. Otherwise this test has no
11247 * observable way to know whether the interrupt was delivered.
11249 if (tg3_flag(tp
, 57765_PLUS
)) {
11250 val
= tr32(MSGINT_MODE
) | MSGINT_MODE_ONE_SHOT_DISABLE
;
11251 tw32(MSGINT_MODE
, val
);
11254 err
= request_irq(tnapi
->irq_vec
, tg3_test_isr
,
11255 IRQF_SHARED
, dev
->name
, tnapi
);
11259 tnapi
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
11260 tg3_enable_ints(tp
);
11262 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
11265 for (i
= 0; i
< 5; i
++) {
11266 u32 int_mbox
, misc_host_ctrl
;
11268 int_mbox
= tr32_mailbox(tnapi
->int_mbox
);
11269 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
11271 if ((int_mbox
!= 0) ||
11272 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
11277 if (tg3_flag(tp
, 57765_PLUS
) &&
11278 tnapi
->hw_status
->status_tag
!= tnapi
->last_tag
)
11279 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
11284 tg3_disable_ints(tp
);
11286 free_irq(tnapi
->irq_vec
, tnapi
);
11288 err
= tg3_request_irq(tp
, 0);
11294 /* Reenable MSI one shot mode. */
11295 if (tg3_flag(tp
, 57765_PLUS
) && tg3_flag(tp
, 1SHOT_MSI
)) {
11296 val
= tr32(MSGINT_MODE
) & ~MSGINT_MODE_ONE_SHOT_DISABLE
;
11297 tw32(MSGINT_MODE
, val
);
11305 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11306 * successfully restored
11308 static int tg3_test_msi(struct tg3
*tp
)
11313 if (!tg3_flag(tp
, USING_MSI
))
11316 /* Turn off SERR reporting in case MSI terminates with Master
11319 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
11320 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
11321 pci_cmd
& ~PCI_COMMAND_SERR
);
11323 err
= tg3_test_interrupt(tp
);
11325 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
11330 /* other failures */
11334 /* MSI test failed, go back to INTx mode */
11335 netdev_warn(tp
->dev
, "No interrupt was generated using MSI. Switching "
11336 "to INTx mode. Please report this failure to the PCI "
11337 "maintainer and include system chipset information\n");
11339 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
11341 pci_disable_msi(tp
->pdev
);
11343 tg3_flag_clear(tp
, USING_MSI
);
11344 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
11346 err
= tg3_request_irq(tp
, 0);
11350 /* Need to reset the chip because the MSI cycle may have terminated
11351 * with Master Abort.
11353 tg3_full_lock(tp
, 1);
11355 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
11356 err
= tg3_init_hw(tp
, true);
11358 tg3_full_unlock(tp
);
11361 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
11366 static int tg3_request_firmware(struct tg3
*tp
)
11368 const struct tg3_firmware_hdr
*fw_hdr
;
11370 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
11371 netdev_err(tp
->dev
, "Failed to load firmware \"%s\"\n",
11376 fw_hdr
= (struct tg3_firmware_hdr
*)tp
->fw
->data
;
11378 /* Firmware blob starts with version numbers, followed by
11379 * start address and _full_ length including BSS sections
11380 * (which must be longer than the actual data, of course
11383 tp
->fw_len
= be32_to_cpu(fw_hdr
->len
); /* includes bss */
11384 if (tp
->fw_len
< (tp
->fw
->size
- TG3_FW_HDR_LEN
)) {
11385 netdev_err(tp
->dev
, "bogus length %d in \"%s\"\n",
11386 tp
->fw_len
, tp
->fw_needed
);
11387 release_firmware(tp
->fw
);
11392 /* We no longer need firmware; we have it. */
11393 tp
->fw_needed
= NULL
;
11397 static u32
tg3_irq_count(struct tg3
*tp
)
11399 u32 irq_cnt
= max(tp
->rxq_cnt
, tp
->txq_cnt
);
11402 /* We want as many rx rings enabled as there are cpus.
11403 * In multiqueue MSI-X mode, the first MSI-X vector
11404 * only deals with link interrupts, etc, so we add
11405 * one to the number of vectors we are requesting.
11407 irq_cnt
= min_t(unsigned, irq_cnt
+ 1, tp
->irq_max
);
11413 static bool tg3_enable_msix(struct tg3
*tp
)
11416 struct msix_entry msix_ent
[TG3_IRQ_MAX_VECS
];
11418 tp
->txq_cnt
= tp
->txq_req
;
11419 tp
->rxq_cnt
= tp
->rxq_req
;
11421 tp
->rxq_cnt
= netif_get_num_default_rss_queues();
11422 if (tp
->rxq_cnt
> tp
->rxq_max
)
11423 tp
->rxq_cnt
= tp
->rxq_max
;
11425 /* Disable multiple TX rings by default. Simple round-robin hardware
11426 * scheduling of the TX rings can cause starvation of rings with
11427 * small packets when other rings have TSO or jumbo packets.
11432 tp
->irq_cnt
= tg3_irq_count(tp
);
11434 for (i
= 0; i
< tp
->irq_max
; i
++) {
11435 msix_ent
[i
].entry
= i
;
11436 msix_ent
[i
].vector
= 0;
11439 rc
= pci_enable_msix_range(tp
->pdev
, msix_ent
, 1, tp
->irq_cnt
);
11442 } else if (rc
< tp
->irq_cnt
) {
11443 netdev_notice(tp
->dev
, "Requested %d MSI-X vectors, received %d\n",
11446 tp
->rxq_cnt
= max(rc
- 1, 1);
11448 tp
->txq_cnt
= min(tp
->rxq_cnt
, tp
->txq_max
);
11451 for (i
= 0; i
< tp
->irq_max
; i
++)
11452 tp
->napi
[i
].irq_vec
= msix_ent
[i
].vector
;
11454 if (netif_set_real_num_rx_queues(tp
->dev
, tp
->rxq_cnt
)) {
11455 pci_disable_msix(tp
->pdev
);
11459 if (tp
->irq_cnt
== 1)
11462 tg3_flag_set(tp
, ENABLE_RSS
);
11464 if (tp
->txq_cnt
> 1)
11465 tg3_flag_set(tp
, ENABLE_TSS
);
11467 netif_set_real_num_tx_queues(tp
->dev
, tp
->txq_cnt
);
11472 static void tg3_ints_init(struct tg3
*tp
)
11474 if ((tg3_flag(tp
, SUPPORT_MSI
) || tg3_flag(tp
, SUPPORT_MSIX
)) &&
11475 !tg3_flag(tp
, TAGGED_STATUS
)) {
11476 /* All MSI supporting chips should support tagged
11477 * status. Assert that this is the case.
11479 netdev_warn(tp
->dev
,
11480 "MSI without TAGGED_STATUS? Not using MSI\n");
11484 if (tg3_flag(tp
, SUPPORT_MSIX
) && tg3_enable_msix(tp
))
11485 tg3_flag_set(tp
, USING_MSIX
);
11486 else if (tg3_flag(tp
, SUPPORT_MSI
) && pci_enable_msi(tp
->pdev
) == 0)
11487 tg3_flag_set(tp
, USING_MSI
);
11489 if (tg3_flag(tp
, USING_MSI
) || tg3_flag(tp
, USING_MSIX
)) {
11490 u32 msi_mode
= tr32(MSGINT_MODE
);
11491 if (tg3_flag(tp
, USING_MSIX
) && tp
->irq_cnt
> 1)
11492 msi_mode
|= MSGINT_MODE_MULTIVEC_EN
;
11493 if (!tg3_flag(tp
, 1SHOT_MSI
))
11494 msi_mode
|= MSGINT_MODE_ONE_SHOT_DISABLE
;
11495 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
11498 if (!tg3_flag(tp
, USING_MSIX
)) {
11500 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
11503 if (tp
->irq_cnt
== 1) {
11506 netif_set_real_num_tx_queues(tp
->dev
, 1);
11507 netif_set_real_num_rx_queues(tp
->dev
, 1);
11511 static void tg3_ints_fini(struct tg3
*tp
)
11513 if (tg3_flag(tp
, USING_MSIX
))
11514 pci_disable_msix(tp
->pdev
);
11515 else if (tg3_flag(tp
, USING_MSI
))
11516 pci_disable_msi(tp
->pdev
);
11517 tg3_flag_clear(tp
, USING_MSI
);
11518 tg3_flag_clear(tp
, USING_MSIX
);
11519 tg3_flag_clear(tp
, ENABLE_RSS
);
11520 tg3_flag_clear(tp
, ENABLE_TSS
);
11523 static int tg3_start(struct tg3
*tp
, bool reset_phy
, bool test_irq
,
11526 struct net_device
*dev
= tp
->dev
;
11530 * Setup interrupts first so we know how
11531 * many NAPI resources to allocate
11535 tg3_rss_check_indir_tbl(tp
);
11537 /* The placement of this call is tied
11538 * to the setup and use of Host TX descriptors.
11540 err
= tg3_alloc_consistent(tp
);
11542 goto out_ints_fini
;
11546 tg3_napi_enable(tp
);
11548 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
11549 err
= tg3_request_irq(tp
, i
);
11551 for (i
--; i
>= 0; i
--) {
11552 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
11554 free_irq(tnapi
->irq_vec
, tnapi
);
11556 goto out_napi_fini
;
11560 tg3_full_lock(tp
, 0);
11563 tg3_ape_driver_state_change(tp
, RESET_KIND_INIT
);
11565 err
= tg3_init_hw(tp
, reset_phy
);
11567 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
11568 tg3_free_rings(tp
);
11571 tg3_full_unlock(tp
);
11576 if (test_irq
&& tg3_flag(tp
, USING_MSI
)) {
11577 err
= tg3_test_msi(tp
);
11580 tg3_full_lock(tp
, 0);
11581 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
11582 tg3_free_rings(tp
);
11583 tg3_full_unlock(tp
);
11585 goto out_napi_fini
;
11588 if (!tg3_flag(tp
, 57765_PLUS
) && tg3_flag(tp
, USING_MSI
)) {
11589 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
11591 tw32(PCIE_TRANSACTION_CFG
,
11592 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
11598 tg3_hwmon_open(tp
);
11600 tg3_full_lock(tp
, 0);
11602 tg3_timer_start(tp
);
11603 tg3_flag_set(tp
, INIT_COMPLETE
);
11604 tg3_enable_ints(tp
);
11606 tg3_ptp_resume(tp
);
11608 tg3_full_unlock(tp
);
11610 netif_tx_start_all_queues(dev
);
11613 * Reset loopback feature if it was turned on while the device was down
11614 * make sure that it's installed properly now.
11616 if (dev
->features
& NETIF_F_LOOPBACK
)
11617 tg3_set_loopback(dev
, dev
->features
);
11622 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
11623 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
11624 free_irq(tnapi
->irq_vec
, tnapi
);
11628 tg3_napi_disable(tp
);
11630 tg3_free_consistent(tp
);
11638 static void tg3_stop(struct tg3
*tp
)
11642 tg3_reset_task_cancel(tp
);
11643 tg3_netif_stop(tp
);
11645 tg3_timer_stop(tp
);
11647 tg3_hwmon_close(tp
);
11651 tg3_full_lock(tp
, 1);
11653 tg3_disable_ints(tp
);
11655 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
11656 tg3_free_rings(tp
);
11657 tg3_flag_clear(tp
, INIT_COMPLETE
);
11659 tg3_full_unlock(tp
);
11661 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
11662 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
11663 free_irq(tnapi
->irq_vec
, tnapi
);
11670 tg3_free_consistent(tp
);
11673 static int tg3_open(struct net_device
*dev
)
11675 struct tg3
*tp
= netdev_priv(dev
);
11678 if (tp
->pcierr_recovery
) {
11679 netdev_err(dev
, "Failed to open device. PCI error recovery "
11684 if (tp
->fw_needed
) {
11685 err
= tg3_request_firmware(tp
);
11686 if (tg3_asic_rev(tp
) == ASIC_REV_57766
) {
11688 netdev_warn(tp
->dev
, "EEE capability disabled\n");
11689 tp
->phy_flags
&= ~TG3_PHYFLG_EEE_CAP
;
11690 } else if (!(tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
)) {
11691 netdev_warn(tp
->dev
, "EEE capability restored\n");
11692 tp
->phy_flags
|= TG3_PHYFLG_EEE_CAP
;
11694 } else if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
) {
11698 netdev_warn(tp
->dev
, "TSO capability disabled\n");
11699 tg3_flag_clear(tp
, TSO_CAPABLE
);
11700 } else if (!tg3_flag(tp
, TSO_CAPABLE
)) {
11701 netdev_notice(tp
->dev
, "TSO capability restored\n");
11702 tg3_flag_set(tp
, TSO_CAPABLE
);
11706 tg3_carrier_off(tp
);
11708 err
= tg3_power_up(tp
);
11712 tg3_full_lock(tp
, 0);
11714 tg3_disable_ints(tp
);
11715 tg3_flag_clear(tp
, INIT_COMPLETE
);
11717 tg3_full_unlock(tp
);
11719 err
= tg3_start(tp
,
11720 !(tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
),
11723 tg3_frob_aux_power(tp
, false);
11724 pci_set_power_state(tp
->pdev
, PCI_D3hot
);
11730 static int tg3_close(struct net_device
*dev
)
11732 struct tg3
*tp
= netdev_priv(dev
);
11734 if (tp
->pcierr_recovery
) {
11735 netdev_err(dev
, "Failed to close device. PCI error recovery "
11742 if (pci_device_is_present(tp
->pdev
)) {
11743 tg3_power_down_prepare(tp
);
11745 tg3_carrier_off(tp
);
11750 static inline u64
get_stat64(tg3_stat64_t
*val
)
11752 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
11755 static u64
tg3_calc_crc_errors(struct tg3
*tp
)
11757 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
11759 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
11760 (tg3_asic_rev(tp
) == ASIC_REV_5700
||
11761 tg3_asic_rev(tp
) == ASIC_REV_5701
)) {
11764 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
11765 tg3_writephy(tp
, MII_TG3_TEST1
,
11766 val
| MII_TG3_TEST1_CRC_EN
);
11767 tg3_readphy(tp
, MII_TG3_RXR_COUNTERS
, &val
);
11771 tp
->phy_crc_errors
+= val
;
11773 return tp
->phy_crc_errors
;
11776 return get_stat64(&hw_stats
->rx_fcs_errors
);
11779 #define ESTAT_ADD(member) \
11780 estats->member = old_estats->member + \
11781 get_stat64(&hw_stats->member)
11783 static void tg3_get_estats(struct tg3
*tp
, struct tg3_ethtool_stats
*estats
)
11785 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
11786 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
11788 ESTAT_ADD(rx_octets
);
11789 ESTAT_ADD(rx_fragments
);
11790 ESTAT_ADD(rx_ucast_packets
);
11791 ESTAT_ADD(rx_mcast_packets
);
11792 ESTAT_ADD(rx_bcast_packets
);
11793 ESTAT_ADD(rx_fcs_errors
);
11794 ESTAT_ADD(rx_align_errors
);
11795 ESTAT_ADD(rx_xon_pause_rcvd
);
11796 ESTAT_ADD(rx_xoff_pause_rcvd
);
11797 ESTAT_ADD(rx_mac_ctrl_rcvd
);
11798 ESTAT_ADD(rx_xoff_entered
);
11799 ESTAT_ADD(rx_frame_too_long_errors
);
11800 ESTAT_ADD(rx_jabbers
);
11801 ESTAT_ADD(rx_undersize_packets
);
11802 ESTAT_ADD(rx_in_length_errors
);
11803 ESTAT_ADD(rx_out_length_errors
);
11804 ESTAT_ADD(rx_64_or_less_octet_packets
);
11805 ESTAT_ADD(rx_65_to_127_octet_packets
);
11806 ESTAT_ADD(rx_128_to_255_octet_packets
);
11807 ESTAT_ADD(rx_256_to_511_octet_packets
);
11808 ESTAT_ADD(rx_512_to_1023_octet_packets
);
11809 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
11810 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
11811 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
11812 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
11813 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
11815 ESTAT_ADD(tx_octets
);
11816 ESTAT_ADD(tx_collisions
);
11817 ESTAT_ADD(tx_xon_sent
);
11818 ESTAT_ADD(tx_xoff_sent
);
11819 ESTAT_ADD(tx_flow_control
);
11820 ESTAT_ADD(tx_mac_errors
);
11821 ESTAT_ADD(tx_single_collisions
);
11822 ESTAT_ADD(tx_mult_collisions
);
11823 ESTAT_ADD(tx_deferred
);
11824 ESTAT_ADD(tx_excessive_collisions
);
11825 ESTAT_ADD(tx_late_collisions
);
11826 ESTAT_ADD(tx_collide_2times
);
11827 ESTAT_ADD(tx_collide_3times
);
11828 ESTAT_ADD(tx_collide_4times
);
11829 ESTAT_ADD(tx_collide_5times
);
11830 ESTAT_ADD(tx_collide_6times
);
11831 ESTAT_ADD(tx_collide_7times
);
11832 ESTAT_ADD(tx_collide_8times
);
11833 ESTAT_ADD(tx_collide_9times
);
11834 ESTAT_ADD(tx_collide_10times
);
11835 ESTAT_ADD(tx_collide_11times
);
11836 ESTAT_ADD(tx_collide_12times
);
11837 ESTAT_ADD(tx_collide_13times
);
11838 ESTAT_ADD(tx_collide_14times
);
11839 ESTAT_ADD(tx_collide_15times
);
11840 ESTAT_ADD(tx_ucast_packets
);
11841 ESTAT_ADD(tx_mcast_packets
);
11842 ESTAT_ADD(tx_bcast_packets
);
11843 ESTAT_ADD(tx_carrier_sense_errors
);
11844 ESTAT_ADD(tx_discards
);
11845 ESTAT_ADD(tx_errors
);
11847 ESTAT_ADD(dma_writeq_full
);
11848 ESTAT_ADD(dma_write_prioq_full
);
11849 ESTAT_ADD(rxbds_empty
);
11850 ESTAT_ADD(rx_discards
);
11851 ESTAT_ADD(rx_errors
);
11852 ESTAT_ADD(rx_threshold_hit
);
11854 ESTAT_ADD(dma_readq_full
);
11855 ESTAT_ADD(dma_read_prioq_full
);
11856 ESTAT_ADD(tx_comp_queue_full
);
11858 ESTAT_ADD(ring_set_send_prod_index
);
11859 ESTAT_ADD(ring_status_update
);
11860 ESTAT_ADD(nic_irqs
);
11861 ESTAT_ADD(nic_avoided_irqs
);
11862 ESTAT_ADD(nic_tx_threshold_hit
);
11864 ESTAT_ADD(mbuf_lwm_thresh_hit
);
11867 static void tg3_get_nstats(struct tg3
*tp
, struct rtnl_link_stats64
*stats
)
11869 struct rtnl_link_stats64
*old_stats
= &tp
->net_stats_prev
;
11870 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
11872 stats
->rx_packets
= old_stats
->rx_packets
+
11873 get_stat64(&hw_stats
->rx_ucast_packets
) +
11874 get_stat64(&hw_stats
->rx_mcast_packets
) +
11875 get_stat64(&hw_stats
->rx_bcast_packets
);
11877 stats
->tx_packets
= old_stats
->tx_packets
+
11878 get_stat64(&hw_stats
->tx_ucast_packets
) +
11879 get_stat64(&hw_stats
->tx_mcast_packets
) +
11880 get_stat64(&hw_stats
->tx_bcast_packets
);
11882 stats
->rx_bytes
= old_stats
->rx_bytes
+
11883 get_stat64(&hw_stats
->rx_octets
);
11884 stats
->tx_bytes
= old_stats
->tx_bytes
+
11885 get_stat64(&hw_stats
->tx_octets
);
11887 stats
->rx_errors
= old_stats
->rx_errors
+
11888 get_stat64(&hw_stats
->rx_errors
);
11889 stats
->tx_errors
= old_stats
->tx_errors
+
11890 get_stat64(&hw_stats
->tx_errors
) +
11891 get_stat64(&hw_stats
->tx_mac_errors
) +
11892 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
11893 get_stat64(&hw_stats
->tx_discards
);
11895 stats
->multicast
= old_stats
->multicast
+
11896 get_stat64(&hw_stats
->rx_mcast_packets
);
11897 stats
->collisions
= old_stats
->collisions
+
11898 get_stat64(&hw_stats
->tx_collisions
);
11900 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
11901 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
11902 get_stat64(&hw_stats
->rx_undersize_packets
);
11904 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
11905 get_stat64(&hw_stats
->rx_align_errors
);
11906 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
11907 get_stat64(&hw_stats
->tx_discards
);
11908 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
11909 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
11911 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
11912 tg3_calc_crc_errors(tp
);
11914 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
11915 get_stat64(&hw_stats
->rx_discards
);
11917 stats
->rx_dropped
= tp
->rx_dropped
;
11918 stats
->tx_dropped
= tp
->tx_dropped
;
11921 static int tg3_get_regs_len(struct net_device
*dev
)
11923 return TG3_REG_BLK_SIZE
;
11926 static void tg3_get_regs(struct net_device
*dev
,
11927 struct ethtool_regs
*regs
, void *_p
)
11929 struct tg3
*tp
= netdev_priv(dev
);
11933 memset(_p
, 0, TG3_REG_BLK_SIZE
);
11935 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
11938 tg3_full_lock(tp
, 0);
11940 tg3_dump_legacy_regs(tp
, (u32
*)_p
);
11942 tg3_full_unlock(tp
);
11945 static int tg3_get_eeprom_len(struct net_device
*dev
)
11947 struct tg3
*tp
= netdev_priv(dev
);
11949 return tp
->nvram_size
;
11952 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
11954 struct tg3
*tp
= netdev_priv(dev
);
11955 int ret
, cpmu_restore
= 0;
11957 u32 i
, offset
, len
, b_offset
, b_count
, cpmu_val
= 0;
11960 if (tg3_flag(tp
, NO_NVRAM
))
11963 offset
= eeprom
->offset
;
11967 eeprom
->magic
= TG3_EEPROM_MAGIC
;
11969 /* Override clock, link aware and link idle modes */
11970 if (tg3_flag(tp
, CPMU_PRESENT
)) {
11971 cpmu_val
= tr32(TG3_CPMU_CTRL
);
11972 if (cpmu_val
& (CPMU_CTRL_LINK_AWARE_MODE
|
11973 CPMU_CTRL_LINK_IDLE_MODE
)) {
11974 tw32(TG3_CPMU_CTRL
, cpmu_val
&
11975 ~(CPMU_CTRL_LINK_AWARE_MODE
|
11976 CPMU_CTRL_LINK_IDLE_MODE
));
11980 tg3_override_clk(tp
);
11983 /* adjustments to start on required 4 byte boundary */
11984 b_offset
= offset
& 3;
11985 b_count
= 4 - b_offset
;
11986 if (b_count
> len
) {
11987 /* i.e. offset=1 len=2 */
11990 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &val
);
11993 memcpy(data
, ((char *)&val
) + b_offset
, b_count
);
11996 eeprom
->len
+= b_count
;
11999 /* read bytes up to the last 4 byte boundary */
12000 pd
= &data
[eeprom
->len
];
12001 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
12002 ret
= tg3_nvram_read_be32(tp
, offset
+ i
, &val
);
12009 memcpy(pd
+ i
, &val
, 4);
12010 if (need_resched()) {
12011 if (signal_pending(current
)) {
12022 /* read last bytes not ending on 4 byte boundary */
12023 pd
= &data
[eeprom
->len
];
12025 b_offset
= offset
+ len
- b_count
;
12026 ret
= tg3_nvram_read_be32(tp
, b_offset
, &val
);
12029 memcpy(pd
, &val
, b_count
);
12030 eeprom
->len
+= b_count
;
12035 /* Restore clock, link aware and link idle modes */
12036 tg3_restore_clk(tp
);
12038 tw32(TG3_CPMU_CTRL
, cpmu_val
);
12043 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
12045 struct tg3
*tp
= netdev_priv(dev
);
12047 u32 offset
, len
, b_offset
, odd_len
;
12049 __be32 start
= 0, end
;
12051 if (tg3_flag(tp
, NO_NVRAM
) ||
12052 eeprom
->magic
!= TG3_EEPROM_MAGIC
)
12055 offset
= eeprom
->offset
;
12058 if ((b_offset
= (offset
& 3))) {
12059 /* adjustments to start on required 4 byte boundary */
12060 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &start
);
12071 /* adjustments to end on required 4 byte boundary */
12073 len
= (len
+ 3) & ~3;
12074 ret
= tg3_nvram_read_be32(tp
, offset
+len
-4, &end
);
12080 if (b_offset
|| odd_len
) {
12081 buf
= kmalloc(len
, GFP_KERNEL
);
12085 memcpy(buf
, &start
, 4);
12087 memcpy(buf
+len
-4, &end
, 4);
12088 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
12091 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
12099 static int tg3_get_link_ksettings(struct net_device
*dev
,
12100 struct ethtool_link_ksettings
*cmd
)
12102 struct tg3
*tp
= netdev_priv(dev
);
12103 u32 supported
, advertising
;
12105 if (tg3_flag(tp
, USE_PHYLIB
)) {
12106 struct phy_device
*phydev
;
12107 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
12109 phydev
= mdiobus_get_phy(tp
->mdio_bus
, tp
->phy_addr
);
12110 phy_ethtool_ksettings_get(phydev
, cmd
);
12115 supported
= (SUPPORTED_Autoneg
);
12117 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
12118 supported
|= (SUPPORTED_1000baseT_Half
|
12119 SUPPORTED_1000baseT_Full
);
12121 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
12122 supported
|= (SUPPORTED_100baseT_Half
|
12123 SUPPORTED_100baseT_Full
|
12124 SUPPORTED_10baseT_Half
|
12125 SUPPORTED_10baseT_Full
|
12127 cmd
->base
.port
= PORT_TP
;
12129 supported
|= SUPPORTED_FIBRE
;
12130 cmd
->base
.port
= PORT_FIBRE
;
12132 ethtool_convert_legacy_u32_to_link_mode(cmd
->link_modes
.supported
,
12135 advertising
= tp
->link_config
.advertising
;
12136 if (tg3_flag(tp
, PAUSE_AUTONEG
)) {
12137 if (tp
->link_config
.flowctrl
& FLOW_CTRL_RX
) {
12138 if (tp
->link_config
.flowctrl
& FLOW_CTRL_TX
) {
12139 advertising
|= ADVERTISED_Pause
;
12141 advertising
|= ADVERTISED_Pause
|
12142 ADVERTISED_Asym_Pause
;
12144 } else if (tp
->link_config
.flowctrl
& FLOW_CTRL_TX
) {
12145 advertising
|= ADVERTISED_Asym_Pause
;
12148 ethtool_convert_legacy_u32_to_link_mode(cmd
->link_modes
.advertising
,
12151 if (netif_running(dev
) && tp
->link_up
) {
12152 cmd
->base
.speed
= tp
->link_config
.active_speed
;
12153 cmd
->base
.duplex
= tp
->link_config
.active_duplex
;
12154 ethtool_convert_legacy_u32_to_link_mode(
12155 cmd
->link_modes
.lp_advertising
,
12156 tp
->link_config
.rmt_adv
);
12158 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
12159 if (tp
->phy_flags
& TG3_PHYFLG_MDIX_STATE
)
12160 cmd
->base
.eth_tp_mdix
= ETH_TP_MDI_X
;
12162 cmd
->base
.eth_tp_mdix
= ETH_TP_MDI
;
12165 cmd
->base
.speed
= SPEED_UNKNOWN
;
12166 cmd
->base
.duplex
= DUPLEX_UNKNOWN
;
12167 cmd
->base
.eth_tp_mdix
= ETH_TP_MDI_INVALID
;
12169 cmd
->base
.phy_address
= tp
->phy_addr
;
12170 cmd
->base
.autoneg
= tp
->link_config
.autoneg
;
12174 static int tg3_set_link_ksettings(struct net_device
*dev
,
12175 const struct ethtool_link_ksettings
*cmd
)
12177 struct tg3
*tp
= netdev_priv(dev
);
12178 u32 speed
= cmd
->base
.speed
;
12181 if (tg3_flag(tp
, USE_PHYLIB
)) {
12182 struct phy_device
*phydev
;
12183 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
12185 phydev
= mdiobus_get_phy(tp
->mdio_bus
, tp
->phy_addr
);
12186 return phy_ethtool_ksettings_set(phydev
, cmd
);
12189 if (cmd
->base
.autoneg
!= AUTONEG_ENABLE
&&
12190 cmd
->base
.autoneg
!= AUTONEG_DISABLE
)
12193 if (cmd
->base
.autoneg
== AUTONEG_DISABLE
&&
12194 cmd
->base
.duplex
!= DUPLEX_FULL
&&
12195 cmd
->base
.duplex
!= DUPLEX_HALF
)
12198 ethtool_convert_link_mode_to_legacy_u32(&advertising
,
12199 cmd
->link_modes
.advertising
);
12201 if (cmd
->base
.autoneg
== AUTONEG_ENABLE
) {
12202 u32 mask
= ADVERTISED_Autoneg
|
12204 ADVERTISED_Asym_Pause
;
12206 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
12207 mask
|= ADVERTISED_1000baseT_Half
|
12208 ADVERTISED_1000baseT_Full
;
12210 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
12211 mask
|= ADVERTISED_100baseT_Half
|
12212 ADVERTISED_100baseT_Full
|
12213 ADVERTISED_10baseT_Half
|
12214 ADVERTISED_10baseT_Full
|
12217 mask
|= ADVERTISED_FIBRE
;
12219 if (advertising
& ~mask
)
12222 mask
&= (ADVERTISED_1000baseT_Half
|
12223 ADVERTISED_1000baseT_Full
|
12224 ADVERTISED_100baseT_Half
|
12225 ADVERTISED_100baseT_Full
|
12226 ADVERTISED_10baseT_Half
|
12227 ADVERTISED_10baseT_Full
);
12229 advertising
&= mask
;
12231 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) {
12232 if (speed
!= SPEED_1000
)
12235 if (cmd
->base
.duplex
!= DUPLEX_FULL
)
12238 if (speed
!= SPEED_100
&&
12244 tg3_full_lock(tp
, 0);
12246 tp
->link_config
.autoneg
= cmd
->base
.autoneg
;
12247 if (cmd
->base
.autoneg
== AUTONEG_ENABLE
) {
12248 tp
->link_config
.advertising
= (advertising
|
12249 ADVERTISED_Autoneg
);
12250 tp
->link_config
.speed
= SPEED_UNKNOWN
;
12251 tp
->link_config
.duplex
= DUPLEX_UNKNOWN
;
12253 tp
->link_config
.advertising
= 0;
12254 tp
->link_config
.speed
= speed
;
12255 tp
->link_config
.duplex
= cmd
->base
.duplex
;
12258 tp
->phy_flags
|= TG3_PHYFLG_USER_CONFIGURED
;
12260 tg3_warn_mgmt_link_flap(tp
);
12262 if (netif_running(dev
))
12263 tg3_setup_phy(tp
, true);
12265 tg3_full_unlock(tp
);
12270 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
12272 struct tg3
*tp
= netdev_priv(dev
);
12274 strlcpy(info
->driver
, DRV_MODULE_NAME
, sizeof(info
->driver
));
12275 strlcpy(info
->version
, DRV_MODULE_VERSION
, sizeof(info
->version
));
12276 strlcpy(info
->fw_version
, tp
->fw_ver
, sizeof(info
->fw_version
));
12277 strlcpy(info
->bus_info
, pci_name(tp
->pdev
), sizeof(info
->bus_info
));
12280 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
12282 struct tg3
*tp
= netdev_priv(dev
);
12284 if (tg3_flag(tp
, WOL_CAP
) && device_can_wakeup(&tp
->pdev
->dev
))
12285 wol
->supported
= WAKE_MAGIC
;
12287 wol
->supported
= 0;
12289 if (tg3_flag(tp
, WOL_ENABLE
) && device_can_wakeup(&tp
->pdev
->dev
))
12290 wol
->wolopts
= WAKE_MAGIC
;
12291 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
12294 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
12296 struct tg3
*tp
= netdev_priv(dev
);
12297 struct device
*dp
= &tp
->pdev
->dev
;
12299 if (wol
->wolopts
& ~WAKE_MAGIC
)
12301 if ((wol
->wolopts
& WAKE_MAGIC
) &&
12302 !(tg3_flag(tp
, WOL_CAP
) && device_can_wakeup(dp
)))
12305 device_set_wakeup_enable(dp
, wol
->wolopts
& WAKE_MAGIC
);
12307 if (device_may_wakeup(dp
))
12308 tg3_flag_set(tp
, WOL_ENABLE
);
12310 tg3_flag_clear(tp
, WOL_ENABLE
);
12315 static u32
tg3_get_msglevel(struct net_device
*dev
)
12317 struct tg3
*tp
= netdev_priv(dev
);
12318 return tp
->msg_enable
;
12321 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
12323 struct tg3
*tp
= netdev_priv(dev
);
12324 tp
->msg_enable
= value
;
12327 static int tg3_nway_reset(struct net_device
*dev
)
12329 struct tg3
*tp
= netdev_priv(dev
);
12332 if (!netif_running(dev
))
12335 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
12338 tg3_warn_mgmt_link_flap(tp
);
12340 if (tg3_flag(tp
, USE_PHYLIB
)) {
12341 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
12343 r
= phy_start_aneg(mdiobus_get_phy(tp
->mdio_bus
, tp
->phy_addr
));
12347 spin_lock_bh(&tp
->lock
);
12349 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
12350 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
12351 ((bmcr
& BMCR_ANENABLE
) ||
12352 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
))) {
12353 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
12357 spin_unlock_bh(&tp
->lock
);
12363 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
12365 struct tg3
*tp
= netdev_priv(dev
);
12367 ering
->rx_max_pending
= tp
->rx_std_ring_mask
;
12368 if (tg3_flag(tp
, JUMBO_RING_ENABLE
))
12369 ering
->rx_jumbo_max_pending
= tp
->rx_jmb_ring_mask
;
12371 ering
->rx_jumbo_max_pending
= 0;
12373 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
12375 ering
->rx_pending
= tp
->rx_pending
;
12376 if (tg3_flag(tp
, JUMBO_RING_ENABLE
))
12377 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
12379 ering
->rx_jumbo_pending
= 0;
12381 ering
->tx_pending
= tp
->napi
[0].tx_pending
;
12384 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
12386 struct tg3
*tp
= netdev_priv(dev
);
12387 int i
, irq_sync
= 0, err
= 0;
12389 if ((ering
->rx_pending
> tp
->rx_std_ring_mask
) ||
12390 (ering
->rx_jumbo_pending
> tp
->rx_jmb_ring_mask
) ||
12391 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
12392 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
12393 (tg3_flag(tp
, TSO_BUG
) &&
12394 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
12397 if (netif_running(dev
)) {
12399 tg3_netif_stop(tp
);
12403 tg3_full_lock(tp
, irq_sync
);
12405 tp
->rx_pending
= ering
->rx_pending
;
12407 if (tg3_flag(tp
, MAX_RXPEND_64
) &&
12408 tp
->rx_pending
> 63)
12409 tp
->rx_pending
= 63;
12411 if (tg3_flag(tp
, JUMBO_RING_ENABLE
))
12412 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
12414 for (i
= 0; i
< tp
->irq_max
; i
++)
12415 tp
->napi
[i
].tx_pending
= ering
->tx_pending
;
12417 if (netif_running(dev
)) {
12418 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
12419 err
= tg3_restart_hw(tp
, false);
12421 tg3_netif_start(tp
);
12424 tg3_full_unlock(tp
);
12426 if (irq_sync
&& !err
)
12432 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
12434 struct tg3
*tp
= netdev_priv(dev
);
12436 epause
->autoneg
= !!tg3_flag(tp
, PAUSE_AUTONEG
);
12438 if (tp
->link_config
.flowctrl
& FLOW_CTRL_RX
)
12439 epause
->rx_pause
= 1;
12441 epause
->rx_pause
= 0;
12443 if (tp
->link_config
.flowctrl
& FLOW_CTRL_TX
)
12444 epause
->tx_pause
= 1;
12446 epause
->tx_pause
= 0;
12449 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
12451 struct tg3
*tp
= netdev_priv(dev
);
12454 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)
12455 tg3_warn_mgmt_link_flap(tp
);
12457 if (tg3_flag(tp
, USE_PHYLIB
)) {
12459 struct phy_device
*phydev
;
12461 phydev
= mdiobus_get_phy(tp
->mdio_bus
, tp
->phy_addr
);
12463 if (!(phydev
->supported
& SUPPORTED_Pause
) ||
12464 (!(phydev
->supported
& SUPPORTED_Asym_Pause
) &&
12465 (epause
->rx_pause
!= epause
->tx_pause
)))
12468 tp
->link_config
.flowctrl
= 0;
12469 if (epause
->rx_pause
) {
12470 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
12472 if (epause
->tx_pause
) {
12473 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
12474 newadv
= ADVERTISED_Pause
;
12476 newadv
= ADVERTISED_Pause
|
12477 ADVERTISED_Asym_Pause
;
12478 } else if (epause
->tx_pause
) {
12479 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
12480 newadv
= ADVERTISED_Asym_Pause
;
12484 if (epause
->autoneg
)
12485 tg3_flag_set(tp
, PAUSE_AUTONEG
);
12487 tg3_flag_clear(tp
, PAUSE_AUTONEG
);
12489 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
12490 u32 oldadv
= phydev
->advertising
&
12491 (ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
12492 if (oldadv
!= newadv
) {
12493 phydev
->advertising
&=
12494 ~(ADVERTISED_Pause
|
12495 ADVERTISED_Asym_Pause
);
12496 phydev
->advertising
|= newadv
;
12497 if (phydev
->autoneg
) {
12499 * Always renegotiate the link to
12500 * inform our link partner of our
12501 * flow control settings, even if the
12502 * flow control is forced. Let
12503 * tg3_adjust_link() do the final
12504 * flow control setup.
12506 return phy_start_aneg(phydev
);
12510 if (!epause
->autoneg
)
12511 tg3_setup_flow_control(tp
, 0, 0);
12513 tp
->link_config
.advertising
&=
12514 ~(ADVERTISED_Pause
|
12515 ADVERTISED_Asym_Pause
);
12516 tp
->link_config
.advertising
|= newadv
;
12521 if (netif_running(dev
)) {
12522 tg3_netif_stop(tp
);
12526 tg3_full_lock(tp
, irq_sync
);
12528 if (epause
->autoneg
)
12529 tg3_flag_set(tp
, PAUSE_AUTONEG
);
12531 tg3_flag_clear(tp
, PAUSE_AUTONEG
);
12532 if (epause
->rx_pause
)
12533 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
12535 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
12536 if (epause
->tx_pause
)
12537 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
12539 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
12541 if (netif_running(dev
)) {
12542 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
12543 err
= tg3_restart_hw(tp
, false);
12545 tg3_netif_start(tp
);
12548 tg3_full_unlock(tp
);
12551 tp
->phy_flags
|= TG3_PHYFLG_USER_CONFIGURED
;
12556 static int tg3_get_sset_count(struct net_device
*dev
, int sset
)
12560 return TG3_NUM_TEST
;
12562 return TG3_NUM_STATS
;
12564 return -EOPNOTSUPP
;
12568 static int tg3_get_rxnfc(struct net_device
*dev
, struct ethtool_rxnfc
*info
,
12569 u32
*rules __always_unused
)
12571 struct tg3
*tp
= netdev_priv(dev
);
12573 if (!tg3_flag(tp
, SUPPORT_MSIX
))
12574 return -EOPNOTSUPP
;
12576 switch (info
->cmd
) {
12577 case ETHTOOL_GRXRINGS
:
12578 if (netif_running(tp
->dev
))
12579 info
->data
= tp
->rxq_cnt
;
12581 info
->data
= num_online_cpus();
12582 if (info
->data
> TG3_RSS_MAX_NUM_QS
)
12583 info
->data
= TG3_RSS_MAX_NUM_QS
;
12589 return -EOPNOTSUPP
;
12593 static u32
tg3_get_rxfh_indir_size(struct net_device
*dev
)
12596 struct tg3
*tp
= netdev_priv(dev
);
12598 if (tg3_flag(tp
, SUPPORT_MSIX
))
12599 size
= TG3_RSS_INDIR_TBL_SIZE
;
12604 static int tg3_get_rxfh(struct net_device
*dev
, u32
*indir
, u8
*key
, u8
*hfunc
)
12606 struct tg3
*tp
= netdev_priv(dev
);
12610 *hfunc
= ETH_RSS_HASH_TOP
;
12614 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++)
12615 indir
[i
] = tp
->rss_ind_tbl
[i
];
12620 static int tg3_set_rxfh(struct net_device
*dev
, const u32
*indir
, const u8
*key
,
12623 struct tg3
*tp
= netdev_priv(dev
);
12626 /* We require at least one supported parameter to be changed and no
12627 * change in any of the unsupported parameters
12630 (hfunc
!= ETH_RSS_HASH_NO_CHANGE
&& hfunc
!= ETH_RSS_HASH_TOP
))
12631 return -EOPNOTSUPP
;
12636 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++)
12637 tp
->rss_ind_tbl
[i
] = indir
[i
];
12639 if (!netif_running(dev
) || !tg3_flag(tp
, ENABLE_RSS
))
12642 /* It is legal to write the indirection
12643 * table while the device is running.
12645 tg3_full_lock(tp
, 0);
12646 tg3_rss_write_indir_tbl(tp
);
12647 tg3_full_unlock(tp
);
12652 static void tg3_get_channels(struct net_device
*dev
,
12653 struct ethtool_channels
*channel
)
12655 struct tg3
*tp
= netdev_priv(dev
);
12656 u32 deflt_qs
= netif_get_num_default_rss_queues();
12658 channel
->max_rx
= tp
->rxq_max
;
12659 channel
->max_tx
= tp
->txq_max
;
12661 if (netif_running(dev
)) {
12662 channel
->rx_count
= tp
->rxq_cnt
;
12663 channel
->tx_count
= tp
->txq_cnt
;
12666 channel
->rx_count
= tp
->rxq_req
;
12668 channel
->rx_count
= min(deflt_qs
, tp
->rxq_max
);
12671 channel
->tx_count
= tp
->txq_req
;
12673 channel
->tx_count
= min(deflt_qs
, tp
->txq_max
);
12677 static int tg3_set_channels(struct net_device
*dev
,
12678 struct ethtool_channels
*channel
)
12680 struct tg3
*tp
= netdev_priv(dev
);
12682 if (!tg3_flag(tp
, SUPPORT_MSIX
))
12683 return -EOPNOTSUPP
;
12685 if (channel
->rx_count
> tp
->rxq_max
||
12686 channel
->tx_count
> tp
->txq_max
)
12689 tp
->rxq_req
= channel
->rx_count
;
12690 tp
->txq_req
= channel
->tx_count
;
12692 if (!netif_running(dev
))
12697 tg3_carrier_off(tp
);
12699 tg3_start(tp
, true, false, false);
12704 static void tg3_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
12706 switch (stringset
) {
12708 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
12711 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
12714 WARN_ON(1); /* we need a WARN() */
12719 static int tg3_set_phys_id(struct net_device
*dev
,
12720 enum ethtool_phys_id_state state
)
12722 struct tg3
*tp
= netdev_priv(dev
);
12724 if (!netif_running(tp
->dev
))
12728 case ETHTOOL_ID_ACTIVE
:
12729 return 1; /* cycle on/off once per second */
12731 case ETHTOOL_ID_ON
:
12732 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
12733 LED_CTRL_1000MBPS_ON
|
12734 LED_CTRL_100MBPS_ON
|
12735 LED_CTRL_10MBPS_ON
|
12736 LED_CTRL_TRAFFIC_OVERRIDE
|
12737 LED_CTRL_TRAFFIC_BLINK
|
12738 LED_CTRL_TRAFFIC_LED
);
12741 case ETHTOOL_ID_OFF
:
12742 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
12743 LED_CTRL_TRAFFIC_OVERRIDE
);
12746 case ETHTOOL_ID_INACTIVE
:
12747 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
12754 static void tg3_get_ethtool_stats(struct net_device
*dev
,
12755 struct ethtool_stats
*estats
, u64
*tmp_stats
)
12757 struct tg3
*tp
= netdev_priv(dev
);
12760 tg3_get_estats(tp
, (struct tg3_ethtool_stats
*)tmp_stats
);
12762 memset(tmp_stats
, 0, sizeof(struct tg3_ethtool_stats
));
12765 static __be32
*tg3_vpd_readblock(struct tg3
*tp
, u32
*vpdlen
)
12769 u32 offset
= 0, len
= 0;
12772 if (tg3_flag(tp
, NO_NVRAM
) || tg3_nvram_read(tp
, 0, &magic
))
12775 if (magic
== TG3_EEPROM_MAGIC
) {
12776 for (offset
= TG3_NVM_DIR_START
;
12777 offset
< TG3_NVM_DIR_END
;
12778 offset
+= TG3_NVM_DIRENT_SIZE
) {
12779 if (tg3_nvram_read(tp
, offset
, &val
))
12782 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) ==
12783 TG3_NVM_DIRTYPE_EXTVPD
)
12787 if (offset
!= TG3_NVM_DIR_END
) {
12788 len
= (val
& TG3_NVM_DIRTYPE_LENMSK
) * 4;
12789 if (tg3_nvram_read(tp
, offset
+ 4, &offset
))
12792 offset
= tg3_nvram_logical_addr(tp
, offset
);
12796 if (!offset
|| !len
) {
12797 offset
= TG3_NVM_VPD_OFF
;
12798 len
= TG3_NVM_VPD_LEN
;
12801 buf
= kmalloc(len
, GFP_KERNEL
);
12805 if (magic
== TG3_EEPROM_MAGIC
) {
12806 for (i
= 0; i
< len
; i
+= 4) {
12807 /* The data is in little-endian format in NVRAM.
12808 * Use the big-endian read routines to preserve
12809 * the byte order as it exists in NVRAM.
12811 if (tg3_nvram_read_be32(tp
, offset
+ i
, &buf
[i
/4]))
12817 unsigned int pos
= 0;
12819 ptr
= (u8
*)&buf
[0];
12820 for (i
= 0; pos
< len
&& i
< 3; i
++, pos
+= cnt
, ptr
+= cnt
) {
12821 cnt
= pci_read_vpd(tp
->pdev
, pos
,
12823 if (cnt
== -ETIMEDOUT
|| cnt
== -EINTR
)
12841 #define NVRAM_TEST_SIZE 0x100
12842 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12843 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12844 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12845 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12846 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12847 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12848 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12849 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12851 static int tg3_test_nvram(struct tg3
*tp
)
12853 u32 csum
, magic
, len
;
12855 int i
, j
, k
, err
= 0, size
;
12857 if (tg3_flag(tp
, NO_NVRAM
))
12860 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
12863 if (magic
== TG3_EEPROM_MAGIC
)
12864 size
= NVRAM_TEST_SIZE
;
12865 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
12866 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
12867 TG3_EEPROM_SB_FORMAT_1
) {
12868 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
12869 case TG3_EEPROM_SB_REVISION_0
:
12870 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
12872 case TG3_EEPROM_SB_REVISION_2
:
12873 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
12875 case TG3_EEPROM_SB_REVISION_3
:
12876 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
12878 case TG3_EEPROM_SB_REVISION_4
:
12879 size
= NVRAM_SELFBOOT_FORMAT1_4_SIZE
;
12881 case TG3_EEPROM_SB_REVISION_5
:
12882 size
= NVRAM_SELFBOOT_FORMAT1_5_SIZE
;
12884 case TG3_EEPROM_SB_REVISION_6
:
12885 size
= NVRAM_SELFBOOT_FORMAT1_6_SIZE
;
12892 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
12893 size
= NVRAM_SELFBOOT_HW_SIZE
;
12897 buf
= kmalloc(size
, GFP_KERNEL
);
12902 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
12903 err
= tg3_nvram_read_be32(tp
, i
, &buf
[j
]);
12910 /* Selfboot format */
12911 magic
= be32_to_cpu(buf
[0]);
12912 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
12913 TG3_EEPROM_MAGIC_FW
) {
12914 u8
*buf8
= (u8
*) buf
, csum8
= 0;
12916 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
12917 TG3_EEPROM_SB_REVISION_2
) {
12918 /* For rev 2, the csum doesn't include the MBA. */
12919 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
12921 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
12924 for (i
= 0; i
< size
; i
++)
12937 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
12938 TG3_EEPROM_MAGIC_HW
) {
12939 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
12940 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
12941 u8
*buf8
= (u8
*) buf
;
12943 /* Separate the parity bits and the data bytes. */
12944 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
12945 if ((i
== 0) || (i
== 8)) {
12949 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
12950 parity
[k
++] = buf8
[i
] & msk
;
12952 } else if (i
== 16) {
12956 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
12957 parity
[k
++] = buf8
[i
] & msk
;
12960 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
12961 parity
[k
++] = buf8
[i
] & msk
;
12964 data
[j
++] = buf8
[i
];
12968 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
12969 u8 hw8
= hweight8(data
[i
]);
12971 if ((hw8
& 0x1) && parity
[i
])
12973 else if (!(hw8
& 0x1) && !parity
[i
])
12982 /* Bootstrap checksum at offset 0x10 */
12983 csum
= calc_crc((unsigned char *) buf
, 0x10);
12984 if (csum
!= le32_to_cpu(buf
[0x10/4]))
12987 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12988 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
12989 if (csum
!= le32_to_cpu(buf
[0xfc/4]))
12994 buf
= tg3_vpd_readblock(tp
, &len
);
12998 i
= pci_vpd_find_tag((u8
*)buf
, 0, len
, PCI_VPD_LRDT_RO_DATA
);
13000 j
= pci_vpd_lrdt_size(&((u8
*)buf
)[i
]);
13004 if (i
+ PCI_VPD_LRDT_TAG_SIZE
+ j
> len
)
13007 i
+= PCI_VPD_LRDT_TAG_SIZE
;
13008 j
= pci_vpd_find_info_keyword((u8
*)buf
, i
, j
,
13009 PCI_VPD_RO_KEYWORD_CHKSUM
);
13013 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
13015 for (i
= 0; i
<= j
; i
++)
13016 csum8
+= ((u8
*)buf
)[i
];
13030 #define TG3_SERDES_TIMEOUT_SEC 2
13031 #define TG3_COPPER_TIMEOUT_SEC 6
13033 static int tg3_test_link(struct tg3
*tp
)
13037 if (!netif_running(tp
->dev
))
13040 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
13041 max
= TG3_SERDES_TIMEOUT_SEC
;
13043 max
= TG3_COPPER_TIMEOUT_SEC
;
13045 for (i
= 0; i
< max
; i
++) {
13049 if (msleep_interruptible(1000))
13056 /* Only test the commonly used registers */
13057 static int tg3_test_registers(struct tg3
*tp
)
13059 int i
, is_5705
, is_5750
;
13060 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
13064 #define TG3_FL_5705 0x1
13065 #define TG3_FL_NOT_5705 0x2
13066 #define TG3_FL_NOT_5788 0x4
13067 #define TG3_FL_NOT_5750 0x8
13071 /* MAC Control Registers */
13072 { MAC_MODE
, TG3_FL_NOT_5705
,
13073 0x00000000, 0x00ef6f8c },
13074 { MAC_MODE
, TG3_FL_5705
,
13075 0x00000000, 0x01ef6b8c },
13076 { MAC_STATUS
, TG3_FL_NOT_5705
,
13077 0x03800107, 0x00000000 },
13078 { MAC_STATUS
, TG3_FL_5705
,
13079 0x03800100, 0x00000000 },
13080 { MAC_ADDR_0_HIGH
, 0x0000,
13081 0x00000000, 0x0000ffff },
13082 { MAC_ADDR_0_LOW
, 0x0000,
13083 0x00000000, 0xffffffff },
13084 { MAC_RX_MTU_SIZE
, 0x0000,
13085 0x00000000, 0x0000ffff },
13086 { MAC_TX_MODE
, 0x0000,
13087 0x00000000, 0x00000070 },
13088 { MAC_TX_LENGTHS
, 0x0000,
13089 0x00000000, 0x00003fff },
13090 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
13091 0x00000000, 0x000007fc },
13092 { MAC_RX_MODE
, TG3_FL_5705
,
13093 0x00000000, 0x000007dc },
13094 { MAC_HASH_REG_0
, 0x0000,
13095 0x00000000, 0xffffffff },
13096 { MAC_HASH_REG_1
, 0x0000,
13097 0x00000000, 0xffffffff },
13098 { MAC_HASH_REG_2
, 0x0000,
13099 0x00000000, 0xffffffff },
13100 { MAC_HASH_REG_3
, 0x0000,
13101 0x00000000, 0xffffffff },
13103 /* Receive Data and Receive BD Initiator Control Registers. */
13104 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
13105 0x00000000, 0xffffffff },
13106 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
13107 0x00000000, 0xffffffff },
13108 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
13109 0x00000000, 0x00000003 },
13110 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
13111 0x00000000, 0xffffffff },
13112 { RCVDBDI_STD_BD
+0, 0x0000,
13113 0x00000000, 0xffffffff },
13114 { RCVDBDI_STD_BD
+4, 0x0000,
13115 0x00000000, 0xffffffff },
13116 { RCVDBDI_STD_BD
+8, 0x0000,
13117 0x00000000, 0xffff0002 },
13118 { RCVDBDI_STD_BD
+0xc, 0x0000,
13119 0x00000000, 0xffffffff },
13121 /* Receive BD Initiator Control Registers. */
13122 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
13123 0x00000000, 0xffffffff },
13124 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
13125 0x00000000, 0x000003ff },
13126 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
13127 0x00000000, 0xffffffff },
13129 /* Host Coalescing Control Registers. */
13130 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
13131 0x00000000, 0x00000004 },
13132 { HOSTCC_MODE
, TG3_FL_5705
,
13133 0x00000000, 0x000000f6 },
13134 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
13135 0x00000000, 0xffffffff },
13136 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
13137 0x00000000, 0x000003ff },
13138 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
13139 0x00000000, 0xffffffff },
13140 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
13141 0x00000000, 0x000003ff },
13142 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
13143 0x00000000, 0xffffffff },
13144 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
13145 0x00000000, 0x000000ff },
13146 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
13147 0x00000000, 0xffffffff },
13148 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
13149 0x00000000, 0x000000ff },
13150 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
13151 0x00000000, 0xffffffff },
13152 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
13153 0x00000000, 0xffffffff },
13154 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
13155 0x00000000, 0xffffffff },
13156 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
13157 0x00000000, 0x000000ff },
13158 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
13159 0x00000000, 0xffffffff },
13160 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
13161 0x00000000, 0x000000ff },
13162 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
13163 0x00000000, 0xffffffff },
13164 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
13165 0x00000000, 0xffffffff },
13166 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
13167 0x00000000, 0xffffffff },
13168 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
13169 0x00000000, 0xffffffff },
13170 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
13171 0x00000000, 0xffffffff },
13172 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
13173 0xffffffff, 0x00000000 },
13174 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
13175 0xffffffff, 0x00000000 },
13177 /* Buffer Manager Control Registers. */
13178 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
13179 0x00000000, 0x007fff80 },
13180 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
13181 0x00000000, 0x007fffff },
13182 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
13183 0x00000000, 0x0000003f },
13184 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
13185 0x00000000, 0x000001ff },
13186 { BUFMGR_MB_HIGH_WATER
, 0x0000,
13187 0x00000000, 0x000001ff },
13188 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
13189 0xffffffff, 0x00000000 },
13190 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
13191 0xffffffff, 0x00000000 },
13193 /* Mailbox Registers */
13194 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
13195 0x00000000, 0x000001ff },
13196 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
13197 0x00000000, 0x000001ff },
13198 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
13199 0x00000000, 0x000007ff },
13200 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
13201 0x00000000, 0x000001ff },
13203 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13206 is_5705
= is_5750
= 0;
13207 if (tg3_flag(tp
, 5705_PLUS
)) {
13209 if (tg3_flag(tp
, 5750_PLUS
))
13213 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
13214 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
13217 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
13220 if (tg3_flag(tp
, IS_5788
) &&
13221 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
13224 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
13227 offset
= (u32
) reg_tbl
[i
].offset
;
13228 read_mask
= reg_tbl
[i
].read_mask
;
13229 write_mask
= reg_tbl
[i
].write_mask
;
13231 /* Save the original register content */
13232 save_val
= tr32(offset
);
13234 /* Determine the read-only value. */
13235 read_val
= save_val
& read_mask
;
13237 /* Write zero to the register, then make sure the read-only bits
13238 * are not changed and the read/write bits are all zeros.
13242 val
= tr32(offset
);
13244 /* Test the read-only and read/write bits. */
13245 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
13248 /* Write ones to all the bits defined by RdMask and WrMask, then
13249 * make sure the read-only bits are not changed and the
13250 * read/write bits are all ones.
13252 tw32(offset
, read_mask
| write_mask
);
13254 val
= tr32(offset
);
13256 /* Test the read-only bits. */
13257 if ((val
& read_mask
) != read_val
)
13260 /* Test the read/write bits. */
13261 if ((val
& write_mask
) != write_mask
)
13264 tw32(offset
, save_val
);
13270 if (netif_msg_hw(tp
))
13271 netdev_err(tp
->dev
,
13272 "Register test failed at offset %x\n", offset
);
13273 tw32(offset
, save_val
);
13277 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
13279 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
13283 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
13284 for (j
= 0; j
< len
; j
+= 4) {
13287 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
13288 tg3_read_mem(tp
, offset
+ j
, &val
);
13289 if (val
!= test_pattern
[i
])
13296 static int tg3_test_memory(struct tg3
*tp
)
13298 static struct mem_entry
{
13301 } mem_tbl_570x
[] = {
13302 { 0x00000000, 0x00b50},
13303 { 0x00002000, 0x1c000},
13304 { 0xffffffff, 0x00000}
13305 }, mem_tbl_5705
[] = {
13306 { 0x00000100, 0x0000c},
13307 { 0x00000200, 0x00008},
13308 { 0x00004000, 0x00800},
13309 { 0x00006000, 0x01000},
13310 { 0x00008000, 0x02000},
13311 { 0x00010000, 0x0e000},
13312 { 0xffffffff, 0x00000}
13313 }, mem_tbl_5755
[] = {
13314 { 0x00000200, 0x00008},
13315 { 0x00004000, 0x00800},
13316 { 0x00006000, 0x00800},
13317 { 0x00008000, 0x02000},
13318 { 0x00010000, 0x0c000},
13319 { 0xffffffff, 0x00000}
13320 }, mem_tbl_5906
[] = {
13321 { 0x00000200, 0x00008},
13322 { 0x00004000, 0x00400},
13323 { 0x00006000, 0x00400},
13324 { 0x00008000, 0x01000},
13325 { 0x00010000, 0x01000},
13326 { 0xffffffff, 0x00000}
13327 }, mem_tbl_5717
[] = {
13328 { 0x00000200, 0x00008},
13329 { 0x00010000, 0x0a000},
13330 { 0x00020000, 0x13c00},
13331 { 0xffffffff, 0x00000}
13332 }, mem_tbl_57765
[] = {
13333 { 0x00000200, 0x00008},
13334 { 0x00004000, 0x00800},
13335 { 0x00006000, 0x09800},
13336 { 0x00010000, 0x0a000},
13337 { 0xffffffff, 0x00000}
13339 struct mem_entry
*mem_tbl
;
13343 if (tg3_flag(tp
, 5717_PLUS
))
13344 mem_tbl
= mem_tbl_5717
;
13345 else if (tg3_flag(tp
, 57765_CLASS
) ||
13346 tg3_asic_rev(tp
) == ASIC_REV_5762
)
13347 mem_tbl
= mem_tbl_57765
;
13348 else if (tg3_flag(tp
, 5755_PLUS
))
13349 mem_tbl
= mem_tbl_5755
;
13350 else if (tg3_asic_rev(tp
) == ASIC_REV_5906
)
13351 mem_tbl
= mem_tbl_5906
;
13352 else if (tg3_flag(tp
, 5705_PLUS
))
13353 mem_tbl
= mem_tbl_5705
;
13355 mem_tbl
= mem_tbl_570x
;
13357 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
13358 err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
, mem_tbl
[i
].len
);
13366 #define TG3_TSO_MSS 500
13368 #define TG3_TSO_IP_HDR_LEN 20
13369 #define TG3_TSO_TCP_HDR_LEN 20
13370 #define TG3_TSO_TCP_OPT_LEN 12
13372 static const u8 tg3_tso_header
[] = {
13374 0x45, 0x00, 0x00, 0x00,
13375 0x00, 0x00, 0x40, 0x00,
13376 0x40, 0x06, 0x00, 0x00,
13377 0x0a, 0x00, 0x00, 0x01,
13378 0x0a, 0x00, 0x00, 0x02,
13379 0x0d, 0x00, 0xe0, 0x00,
13380 0x00, 0x00, 0x01, 0x00,
13381 0x00, 0x00, 0x02, 0x00,
13382 0x80, 0x10, 0x10, 0x00,
13383 0x14, 0x09, 0x00, 0x00,
13384 0x01, 0x01, 0x08, 0x0a,
13385 0x11, 0x11, 0x11, 0x11,
13386 0x11, 0x11, 0x11, 0x11,
13389 static int tg3_run_loopback(struct tg3
*tp
, u32 pktsz
, bool tso_loopback
)
13391 u32 rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
13392 u32 base_flags
= 0, mss
= 0, desc_idx
, coal_now
, data_off
, val
;
13394 struct sk_buff
*skb
;
13395 u8
*tx_data
, *rx_data
;
13397 int num_pkts
, tx_len
, rx_len
, i
, err
;
13398 struct tg3_rx_buffer_desc
*desc
;
13399 struct tg3_napi
*tnapi
, *rnapi
;
13400 struct tg3_rx_prodring_set
*tpr
= &tp
->napi
[0].prodring
;
13402 tnapi
= &tp
->napi
[0];
13403 rnapi
= &tp
->napi
[0];
13404 if (tp
->irq_cnt
> 1) {
13405 if (tg3_flag(tp
, ENABLE_RSS
))
13406 rnapi
= &tp
->napi
[1];
13407 if (tg3_flag(tp
, ENABLE_TSS
))
13408 tnapi
= &tp
->napi
[1];
13410 coal_now
= tnapi
->coal_now
| rnapi
->coal_now
;
13415 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
13419 tx_data
= skb_put(skb
, tx_len
);
13420 memcpy(tx_data
, tp
->dev
->dev_addr
, ETH_ALEN
);
13421 memset(tx_data
+ ETH_ALEN
, 0x0, 8);
13423 tw32(MAC_RX_MTU_SIZE
, tx_len
+ ETH_FCS_LEN
);
13425 if (tso_loopback
) {
13426 struct iphdr
*iph
= (struct iphdr
*)&tx_data
[ETH_HLEN
];
13428 u32 hdr_len
= TG3_TSO_IP_HDR_LEN
+ TG3_TSO_TCP_HDR_LEN
+
13429 TG3_TSO_TCP_OPT_LEN
;
13431 memcpy(tx_data
+ ETH_ALEN
* 2, tg3_tso_header
,
13432 sizeof(tg3_tso_header
));
13435 val
= tx_len
- ETH_ALEN
* 2 - sizeof(tg3_tso_header
);
13436 num_pkts
= DIV_ROUND_UP(val
, TG3_TSO_MSS
);
13438 /* Set the total length field in the IP header */
13439 iph
->tot_len
= htons((u16
)(mss
+ hdr_len
));
13441 base_flags
= (TXD_FLAG_CPU_PRE_DMA
|
13442 TXD_FLAG_CPU_POST_DMA
);
13444 if (tg3_flag(tp
, HW_TSO_1
) ||
13445 tg3_flag(tp
, HW_TSO_2
) ||
13446 tg3_flag(tp
, HW_TSO_3
)) {
13448 val
= ETH_HLEN
+ TG3_TSO_IP_HDR_LEN
;
13449 th
= (struct tcphdr
*)&tx_data
[val
];
13452 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
13454 if (tg3_flag(tp
, HW_TSO_3
)) {
13455 mss
|= (hdr_len
& 0xc) << 12;
13456 if (hdr_len
& 0x10)
13457 base_flags
|= 0x00000010;
13458 base_flags
|= (hdr_len
& 0x3e0) << 5;
13459 } else if (tg3_flag(tp
, HW_TSO_2
))
13460 mss
|= hdr_len
<< 9;
13461 else if (tg3_flag(tp
, HW_TSO_1
) ||
13462 tg3_asic_rev(tp
) == ASIC_REV_5705
) {
13463 mss
|= (TG3_TSO_TCP_OPT_LEN
<< 9);
13465 base_flags
|= (TG3_TSO_TCP_OPT_LEN
<< 10);
13468 data_off
= ETH_ALEN
* 2 + sizeof(tg3_tso_header
);
13471 data_off
= ETH_HLEN
;
13473 if (tg3_flag(tp
, USE_JUMBO_BDFLAG
) &&
13474 tx_len
> VLAN_ETH_FRAME_LEN
)
13475 base_flags
|= TXD_FLAG_JMB_PKT
;
13478 for (i
= data_off
; i
< tx_len
; i
++)
13479 tx_data
[i
] = (u8
) (i
& 0xff);
13481 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
13482 if (pci_dma_mapping_error(tp
->pdev
, map
)) {
13483 dev_kfree_skb(skb
);
13487 val
= tnapi
->tx_prod
;
13488 tnapi
->tx_buffers
[val
].skb
= skb
;
13489 dma_unmap_addr_set(&tnapi
->tx_buffers
[val
], mapping
, map
);
13491 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
13496 rx_start_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
13498 budget
= tg3_tx_avail(tnapi
);
13499 if (tg3_tx_frag_set(tnapi
, &val
, &budget
, map
, tx_len
,
13500 base_flags
| TXD_FLAG_END
, mss
, 0)) {
13501 tnapi
->tx_buffers
[val
].skb
= NULL
;
13502 dev_kfree_skb(skb
);
13508 /* Sync BD data before updating mailbox */
13511 tw32_tx_mbox(tnapi
->prodmbox
, tnapi
->tx_prod
);
13512 tr32_mailbox(tnapi
->prodmbox
);
13516 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13517 for (i
= 0; i
< 35; i
++) {
13518 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
13523 tx_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
13524 rx_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
13525 if ((tx_idx
== tnapi
->tx_prod
) &&
13526 (rx_idx
== (rx_start_idx
+ num_pkts
)))
13530 tg3_tx_skb_unmap(tnapi
, tnapi
->tx_prod
- 1, -1);
13531 dev_kfree_skb(skb
);
13533 if (tx_idx
!= tnapi
->tx_prod
)
13536 if (rx_idx
!= rx_start_idx
+ num_pkts
)
13540 while (rx_idx
!= rx_start_idx
) {
13541 desc
= &rnapi
->rx_rcb
[rx_start_idx
++];
13542 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
13543 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
13545 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
13546 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
13549 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
)
13552 if (!tso_loopback
) {
13553 if (rx_len
!= tx_len
)
13556 if (pktsz
<= TG3_RX_STD_DMA_SZ
- ETH_FCS_LEN
) {
13557 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
13560 if (opaque_key
!= RXD_OPAQUE_RING_JUMBO
)
13563 } else if ((desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
13564 (desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
13565 >> RXD_TCPCSUM_SHIFT
!= 0xffff) {
13569 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
13570 rx_data
= tpr
->rx_std_buffers
[desc_idx
].data
;
13571 map
= dma_unmap_addr(&tpr
->rx_std_buffers
[desc_idx
],
13573 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
13574 rx_data
= tpr
->rx_jmb_buffers
[desc_idx
].data
;
13575 map
= dma_unmap_addr(&tpr
->rx_jmb_buffers
[desc_idx
],
13580 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
,
13581 PCI_DMA_FROMDEVICE
);
13583 rx_data
+= TG3_RX_OFFSET(tp
);
13584 for (i
= data_off
; i
< rx_len
; i
++, val
++) {
13585 if (*(rx_data
+ i
) != (u8
) (val
& 0xff))
13592 /* tg3_free_rings will unmap and free the rx_data */
13597 #define TG3_STD_LOOPBACK_FAILED 1
13598 #define TG3_JMB_LOOPBACK_FAILED 2
13599 #define TG3_TSO_LOOPBACK_FAILED 4
13600 #define TG3_LOOPBACK_FAILED \
13601 (TG3_STD_LOOPBACK_FAILED | \
13602 TG3_JMB_LOOPBACK_FAILED | \
13603 TG3_TSO_LOOPBACK_FAILED)
13605 static int tg3_test_loopback(struct tg3
*tp
, u64
*data
, bool do_extlpbk
)
13609 u32 jmb_pkt_sz
= 9000;
13612 jmb_pkt_sz
= tp
->dma_limit
- ETH_HLEN
;
13614 eee_cap
= tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
;
13615 tp
->phy_flags
&= ~TG3_PHYFLG_EEE_CAP
;
13617 if (!netif_running(tp
->dev
)) {
13618 data
[TG3_MAC_LOOPB_TEST
] = TG3_LOOPBACK_FAILED
;
13619 data
[TG3_PHY_LOOPB_TEST
] = TG3_LOOPBACK_FAILED
;
13621 data
[TG3_EXT_LOOPB_TEST
] = TG3_LOOPBACK_FAILED
;
13625 err
= tg3_reset_hw(tp
, true);
13627 data
[TG3_MAC_LOOPB_TEST
] = TG3_LOOPBACK_FAILED
;
13628 data
[TG3_PHY_LOOPB_TEST
] = TG3_LOOPBACK_FAILED
;
13630 data
[TG3_EXT_LOOPB_TEST
] = TG3_LOOPBACK_FAILED
;
13634 if (tg3_flag(tp
, ENABLE_RSS
)) {
13637 /* Reroute all rx packets to the 1st queue */
13638 for (i
= MAC_RSS_INDIR_TBL_0
;
13639 i
< MAC_RSS_INDIR_TBL_0
+ TG3_RSS_INDIR_TBL_SIZE
; i
+= 4)
13643 /* HW errata - mac loopback fails in some cases on 5780.
13644 * Normal traffic and PHY loopback are not affected by
13645 * errata. Also, the MAC loopback test is deprecated for
13646 * all newer ASIC revisions.
13648 if (tg3_asic_rev(tp
) != ASIC_REV_5780
&&
13649 !tg3_flag(tp
, CPMU_PRESENT
)) {
13650 tg3_mac_loopback(tp
, true);
13652 if (tg3_run_loopback(tp
, ETH_FRAME_LEN
, false))
13653 data
[TG3_MAC_LOOPB_TEST
] |= TG3_STD_LOOPBACK_FAILED
;
13655 if (tg3_flag(tp
, JUMBO_RING_ENABLE
) &&
13656 tg3_run_loopback(tp
, jmb_pkt_sz
+ ETH_HLEN
, false))
13657 data
[TG3_MAC_LOOPB_TEST
] |= TG3_JMB_LOOPBACK_FAILED
;
13659 tg3_mac_loopback(tp
, false);
13662 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
13663 !tg3_flag(tp
, USE_PHYLIB
)) {
13666 tg3_phy_lpbk_set(tp
, 0, false);
13668 /* Wait for link */
13669 for (i
= 0; i
< 100; i
++) {
13670 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
13675 if (tg3_run_loopback(tp
, ETH_FRAME_LEN
, false))
13676 data
[TG3_PHY_LOOPB_TEST
] |= TG3_STD_LOOPBACK_FAILED
;
13677 if (tg3_flag(tp
, TSO_CAPABLE
) &&
13678 tg3_run_loopback(tp
, ETH_FRAME_LEN
, true))
13679 data
[TG3_PHY_LOOPB_TEST
] |= TG3_TSO_LOOPBACK_FAILED
;
13680 if (tg3_flag(tp
, JUMBO_RING_ENABLE
) &&
13681 tg3_run_loopback(tp
, jmb_pkt_sz
+ ETH_HLEN
, false))
13682 data
[TG3_PHY_LOOPB_TEST
] |= TG3_JMB_LOOPBACK_FAILED
;
13685 tg3_phy_lpbk_set(tp
, 0, true);
13687 /* All link indications report up, but the hardware
13688 * isn't really ready for about 20 msec. Double it
13693 if (tg3_run_loopback(tp
, ETH_FRAME_LEN
, false))
13694 data
[TG3_EXT_LOOPB_TEST
] |=
13695 TG3_STD_LOOPBACK_FAILED
;
13696 if (tg3_flag(tp
, TSO_CAPABLE
) &&
13697 tg3_run_loopback(tp
, ETH_FRAME_LEN
, true))
13698 data
[TG3_EXT_LOOPB_TEST
] |=
13699 TG3_TSO_LOOPBACK_FAILED
;
13700 if (tg3_flag(tp
, JUMBO_RING_ENABLE
) &&
13701 tg3_run_loopback(tp
, jmb_pkt_sz
+ ETH_HLEN
, false))
13702 data
[TG3_EXT_LOOPB_TEST
] |=
13703 TG3_JMB_LOOPBACK_FAILED
;
13706 /* Re-enable gphy autopowerdown. */
13707 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
13708 tg3_phy_toggle_apd(tp
, true);
13711 err
= (data
[TG3_MAC_LOOPB_TEST
] | data
[TG3_PHY_LOOPB_TEST
] |
13712 data
[TG3_EXT_LOOPB_TEST
]) ? -EIO
: 0;
13715 tp
->phy_flags
|= eee_cap
;
13720 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
13723 struct tg3
*tp
= netdev_priv(dev
);
13724 bool doextlpbk
= etest
->flags
& ETH_TEST_FL_EXTERNAL_LB
;
13726 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
13727 if (tg3_power_up(tp
)) {
13728 etest
->flags
|= ETH_TEST_FL_FAILED
;
13729 memset(data
, 1, sizeof(u64
) * TG3_NUM_TEST
);
13732 tg3_ape_driver_state_change(tp
, RESET_KIND_INIT
);
13735 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
13737 if (tg3_test_nvram(tp
) != 0) {
13738 etest
->flags
|= ETH_TEST_FL_FAILED
;
13739 data
[TG3_NVRAM_TEST
] = 1;
13741 if (!doextlpbk
&& tg3_test_link(tp
)) {
13742 etest
->flags
|= ETH_TEST_FL_FAILED
;
13743 data
[TG3_LINK_TEST
] = 1;
13745 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
13746 int err
, err2
= 0, irq_sync
= 0;
13748 if (netif_running(dev
)) {
13750 tg3_netif_stop(tp
);
13754 tg3_full_lock(tp
, irq_sync
);
13755 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
13756 err
= tg3_nvram_lock(tp
);
13757 tg3_halt_cpu(tp
, RX_CPU_BASE
);
13758 if (!tg3_flag(tp
, 5705_PLUS
))
13759 tg3_halt_cpu(tp
, TX_CPU_BASE
);
13761 tg3_nvram_unlock(tp
);
13763 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
13766 if (tg3_test_registers(tp
) != 0) {
13767 etest
->flags
|= ETH_TEST_FL_FAILED
;
13768 data
[TG3_REGISTER_TEST
] = 1;
13771 if (tg3_test_memory(tp
) != 0) {
13772 etest
->flags
|= ETH_TEST_FL_FAILED
;
13773 data
[TG3_MEMORY_TEST
] = 1;
13777 etest
->flags
|= ETH_TEST_FL_EXTERNAL_LB_DONE
;
13779 if (tg3_test_loopback(tp
, data
, doextlpbk
))
13780 etest
->flags
|= ETH_TEST_FL_FAILED
;
13782 tg3_full_unlock(tp
);
13784 if (tg3_test_interrupt(tp
) != 0) {
13785 etest
->flags
|= ETH_TEST_FL_FAILED
;
13786 data
[TG3_INTERRUPT_TEST
] = 1;
13789 tg3_full_lock(tp
, 0);
13791 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
13792 if (netif_running(dev
)) {
13793 tg3_flag_set(tp
, INIT_COMPLETE
);
13794 err2
= tg3_restart_hw(tp
, true);
13796 tg3_netif_start(tp
);
13799 tg3_full_unlock(tp
);
13801 if (irq_sync
&& !err2
)
13804 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
13805 tg3_power_down_prepare(tp
);
13809 static int tg3_hwtstamp_set(struct net_device
*dev
, struct ifreq
*ifr
)
13811 struct tg3
*tp
= netdev_priv(dev
);
13812 struct hwtstamp_config stmpconf
;
13814 if (!tg3_flag(tp
, PTP_CAPABLE
))
13815 return -EOPNOTSUPP
;
13817 if (copy_from_user(&stmpconf
, ifr
->ifr_data
, sizeof(stmpconf
)))
13820 if (stmpconf
.flags
)
13823 if (stmpconf
.tx_type
!= HWTSTAMP_TX_ON
&&
13824 stmpconf
.tx_type
!= HWTSTAMP_TX_OFF
)
13827 switch (stmpconf
.rx_filter
) {
13828 case HWTSTAMP_FILTER_NONE
:
13831 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
13832 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V1_EN
|
13833 TG3_RX_PTP_CTL_ALL_V1_EVENTS
;
13835 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
13836 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V1_EN
|
13837 TG3_RX_PTP_CTL_SYNC_EVNT
;
13839 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
13840 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V1_EN
|
13841 TG3_RX_PTP_CTL_DELAY_REQ
;
13843 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
13844 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_EN
|
13845 TG3_RX_PTP_CTL_ALL_V2_EVENTS
;
13847 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
13848 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN
|
13849 TG3_RX_PTP_CTL_ALL_V2_EVENTS
;
13851 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
13852 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN
|
13853 TG3_RX_PTP_CTL_ALL_V2_EVENTS
;
13855 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
13856 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_EN
|
13857 TG3_RX_PTP_CTL_SYNC_EVNT
;
13859 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
13860 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN
|
13861 TG3_RX_PTP_CTL_SYNC_EVNT
;
13863 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
13864 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN
|
13865 TG3_RX_PTP_CTL_SYNC_EVNT
;
13867 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
13868 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_EN
|
13869 TG3_RX_PTP_CTL_DELAY_REQ
;
13871 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
13872 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN
|
13873 TG3_RX_PTP_CTL_DELAY_REQ
;
13875 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
13876 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN
|
13877 TG3_RX_PTP_CTL_DELAY_REQ
;
13883 if (netif_running(dev
) && tp
->rxptpctl
)
13884 tw32(TG3_RX_PTP_CTL
,
13885 tp
->rxptpctl
| TG3_RX_PTP_CTL_HWTS_INTERLOCK
);
13887 if (stmpconf
.tx_type
== HWTSTAMP_TX_ON
)
13888 tg3_flag_set(tp
, TX_TSTAMP_EN
);
13890 tg3_flag_clear(tp
, TX_TSTAMP_EN
);
13892 return copy_to_user(ifr
->ifr_data
, &stmpconf
, sizeof(stmpconf
)) ?
13896 static int tg3_hwtstamp_get(struct net_device
*dev
, struct ifreq
*ifr
)
13898 struct tg3
*tp
= netdev_priv(dev
);
13899 struct hwtstamp_config stmpconf
;
13901 if (!tg3_flag(tp
, PTP_CAPABLE
))
13902 return -EOPNOTSUPP
;
13904 stmpconf
.flags
= 0;
13905 stmpconf
.tx_type
= (tg3_flag(tp
, TX_TSTAMP_EN
) ?
13906 HWTSTAMP_TX_ON
: HWTSTAMP_TX_OFF
);
13908 switch (tp
->rxptpctl
) {
13910 stmpconf
.rx_filter
= HWTSTAMP_FILTER_NONE
;
13912 case TG3_RX_PTP_CTL_RX_PTP_V1_EN
| TG3_RX_PTP_CTL_ALL_V1_EVENTS
:
13913 stmpconf
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
13915 case TG3_RX_PTP_CTL_RX_PTP_V1_EN
| TG3_RX_PTP_CTL_SYNC_EVNT
:
13916 stmpconf
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_SYNC
;
13918 case TG3_RX_PTP_CTL_RX_PTP_V1_EN
| TG3_RX_PTP_CTL_DELAY_REQ
:
13919 stmpconf
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
;
13921 case TG3_RX_PTP_CTL_RX_PTP_V2_EN
| TG3_RX_PTP_CTL_ALL_V2_EVENTS
:
13922 stmpconf
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
13924 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN
| TG3_RX_PTP_CTL_ALL_V2_EVENTS
:
13925 stmpconf
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L2_EVENT
;
13927 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN
| TG3_RX_PTP_CTL_ALL_V2_EVENTS
:
13928 stmpconf
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_EVENT
;
13930 case TG3_RX_PTP_CTL_RX_PTP_V2_EN
| TG3_RX_PTP_CTL_SYNC_EVNT
:
13931 stmpconf
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_SYNC
;
13933 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN
| TG3_RX_PTP_CTL_SYNC_EVNT
:
13934 stmpconf
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L2_SYNC
;
13936 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN
| TG3_RX_PTP_CTL_SYNC_EVNT
:
13937 stmpconf
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_SYNC
;
13939 case TG3_RX_PTP_CTL_RX_PTP_V2_EN
| TG3_RX_PTP_CTL_DELAY_REQ
:
13940 stmpconf
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
;
13942 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN
| TG3_RX_PTP_CTL_DELAY_REQ
:
13943 stmpconf
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
;
13945 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN
| TG3_RX_PTP_CTL_DELAY_REQ
:
13946 stmpconf
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
;
13953 return copy_to_user(ifr
->ifr_data
, &stmpconf
, sizeof(stmpconf
)) ?
13957 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
13959 struct mii_ioctl_data
*data
= if_mii(ifr
);
13960 struct tg3
*tp
= netdev_priv(dev
);
13963 if (tg3_flag(tp
, USE_PHYLIB
)) {
13964 struct phy_device
*phydev
;
13965 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
13967 phydev
= mdiobus_get_phy(tp
->mdio_bus
, tp
->phy_addr
);
13968 return phy_mii_ioctl(phydev
, ifr
, cmd
);
13973 data
->phy_id
= tp
->phy_addr
;
13976 case SIOCGMIIREG
: {
13979 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
13980 break; /* We have no PHY */
13982 if (!netif_running(dev
))
13985 spin_lock_bh(&tp
->lock
);
13986 err
= __tg3_readphy(tp
, data
->phy_id
& 0x1f,
13987 data
->reg_num
& 0x1f, &mii_regval
);
13988 spin_unlock_bh(&tp
->lock
);
13990 data
->val_out
= mii_regval
;
13996 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
13997 break; /* We have no PHY */
13999 if (!netif_running(dev
))
14002 spin_lock_bh(&tp
->lock
);
14003 err
= __tg3_writephy(tp
, data
->phy_id
& 0x1f,
14004 data
->reg_num
& 0x1f, data
->val_in
);
14005 spin_unlock_bh(&tp
->lock
);
14009 case SIOCSHWTSTAMP
:
14010 return tg3_hwtstamp_set(dev
, ifr
);
14012 case SIOCGHWTSTAMP
:
14013 return tg3_hwtstamp_get(dev
, ifr
);
14019 return -EOPNOTSUPP
;
14022 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
14024 struct tg3
*tp
= netdev_priv(dev
);
14026 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
14030 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
14032 struct tg3
*tp
= netdev_priv(dev
);
14033 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
14034 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
14036 if (!tg3_flag(tp
, 5705_PLUS
)) {
14037 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
14038 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
14039 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
14040 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
14043 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
14044 (!ec
->rx_coalesce_usecs
) ||
14045 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
14046 (!ec
->tx_coalesce_usecs
) ||
14047 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
14048 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
14049 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
14050 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
14051 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
14052 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
14053 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
14054 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
14057 /* Only copy relevant parameters, ignore all others. */
14058 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
14059 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
14060 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
14061 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
14062 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
14063 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
14064 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
14065 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
14066 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
14068 if (netif_running(dev
)) {
14069 tg3_full_lock(tp
, 0);
14070 __tg3_set_coalesce(tp
, &tp
->coal
);
14071 tg3_full_unlock(tp
);
14076 static int tg3_set_eee(struct net_device
*dev
, struct ethtool_eee
*edata
)
14078 struct tg3
*tp
= netdev_priv(dev
);
14080 if (!(tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
)) {
14081 netdev_warn(tp
->dev
, "Board does not support EEE!\n");
14082 return -EOPNOTSUPP
;
14085 if (edata
->advertised
!= tp
->eee
.advertised
) {
14086 netdev_warn(tp
->dev
,
14087 "Direct manipulation of EEE advertisement is not supported\n");
14091 if (edata
->tx_lpi_timer
> TG3_CPMU_DBTMR1_LNKIDLE_MAX
) {
14092 netdev_warn(tp
->dev
,
14093 "Maximal Tx Lpi timer supported is %#x(u)\n",
14094 TG3_CPMU_DBTMR1_LNKIDLE_MAX
);
14100 tp
->phy_flags
|= TG3_PHYFLG_USER_CONFIGURED
;
14101 tg3_warn_mgmt_link_flap(tp
);
14103 if (netif_running(tp
->dev
)) {
14104 tg3_full_lock(tp
, 0);
14107 tg3_full_unlock(tp
);
14113 static int tg3_get_eee(struct net_device
*dev
, struct ethtool_eee
*edata
)
14115 struct tg3
*tp
= netdev_priv(dev
);
14117 if (!(tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
)) {
14118 netdev_warn(tp
->dev
,
14119 "Board does not support EEE!\n");
14120 return -EOPNOTSUPP
;
14127 static const struct ethtool_ops tg3_ethtool_ops
= {
14128 .get_drvinfo
= tg3_get_drvinfo
,
14129 .get_regs_len
= tg3_get_regs_len
,
14130 .get_regs
= tg3_get_regs
,
14131 .get_wol
= tg3_get_wol
,
14132 .set_wol
= tg3_set_wol
,
14133 .get_msglevel
= tg3_get_msglevel
,
14134 .set_msglevel
= tg3_set_msglevel
,
14135 .nway_reset
= tg3_nway_reset
,
14136 .get_link
= ethtool_op_get_link
,
14137 .get_eeprom_len
= tg3_get_eeprom_len
,
14138 .get_eeprom
= tg3_get_eeprom
,
14139 .set_eeprom
= tg3_set_eeprom
,
14140 .get_ringparam
= tg3_get_ringparam
,
14141 .set_ringparam
= tg3_set_ringparam
,
14142 .get_pauseparam
= tg3_get_pauseparam
,
14143 .set_pauseparam
= tg3_set_pauseparam
,
14144 .self_test
= tg3_self_test
,
14145 .get_strings
= tg3_get_strings
,
14146 .set_phys_id
= tg3_set_phys_id
,
14147 .get_ethtool_stats
= tg3_get_ethtool_stats
,
14148 .get_coalesce
= tg3_get_coalesce
,
14149 .set_coalesce
= tg3_set_coalesce
,
14150 .get_sset_count
= tg3_get_sset_count
,
14151 .get_rxnfc
= tg3_get_rxnfc
,
14152 .get_rxfh_indir_size
= tg3_get_rxfh_indir_size
,
14153 .get_rxfh
= tg3_get_rxfh
,
14154 .set_rxfh
= tg3_set_rxfh
,
14155 .get_channels
= tg3_get_channels
,
14156 .set_channels
= tg3_set_channels
,
14157 .get_ts_info
= tg3_get_ts_info
,
14158 .get_eee
= tg3_get_eee
,
14159 .set_eee
= tg3_set_eee
,
14160 .get_link_ksettings
= tg3_get_link_ksettings
,
14161 .set_link_ksettings
= tg3_set_link_ksettings
,
14164 static void tg3_get_stats64(struct net_device
*dev
,
14165 struct rtnl_link_stats64
*stats
)
14167 struct tg3
*tp
= netdev_priv(dev
);
14169 spin_lock_bh(&tp
->lock
);
14170 if (!tp
->hw_stats
) {
14171 *stats
= tp
->net_stats_prev
;
14172 spin_unlock_bh(&tp
->lock
);
14176 tg3_get_nstats(tp
, stats
);
14177 spin_unlock_bh(&tp
->lock
);
14180 static void tg3_set_rx_mode(struct net_device
*dev
)
14182 struct tg3
*tp
= netdev_priv(dev
);
14184 if (!netif_running(dev
))
14187 tg3_full_lock(tp
, 0);
14188 __tg3_set_rx_mode(dev
);
14189 tg3_full_unlock(tp
);
14192 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
14195 dev
->mtu
= new_mtu
;
14197 if (new_mtu
> ETH_DATA_LEN
) {
14198 if (tg3_flag(tp
, 5780_CLASS
)) {
14199 netdev_update_features(dev
);
14200 tg3_flag_clear(tp
, TSO_CAPABLE
);
14202 tg3_flag_set(tp
, JUMBO_RING_ENABLE
);
14205 if (tg3_flag(tp
, 5780_CLASS
)) {
14206 tg3_flag_set(tp
, TSO_CAPABLE
);
14207 netdev_update_features(dev
);
14209 tg3_flag_clear(tp
, JUMBO_RING_ENABLE
);
14213 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
14215 struct tg3
*tp
= netdev_priv(dev
);
14217 bool reset_phy
= false;
14219 if (!netif_running(dev
)) {
14220 /* We'll just catch it later when the
14223 tg3_set_mtu(dev
, tp
, new_mtu
);
14229 tg3_netif_stop(tp
);
14231 tg3_set_mtu(dev
, tp
, new_mtu
);
14233 tg3_full_lock(tp
, 1);
14235 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
14237 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14238 * breaks all requests to 256 bytes.
14240 if (tg3_asic_rev(tp
) == ASIC_REV_57766
||
14241 tg3_asic_rev(tp
) == ASIC_REV_5717
||
14242 tg3_asic_rev(tp
) == ASIC_REV_5719
||
14243 tg3_asic_rev(tp
) == ASIC_REV_5720
)
14246 err
= tg3_restart_hw(tp
, reset_phy
);
14249 tg3_netif_start(tp
);
14251 tg3_full_unlock(tp
);
14259 static const struct net_device_ops tg3_netdev_ops
= {
14260 .ndo_open
= tg3_open
,
14261 .ndo_stop
= tg3_close
,
14262 .ndo_start_xmit
= tg3_start_xmit
,
14263 .ndo_get_stats64
= tg3_get_stats64
,
14264 .ndo_validate_addr
= eth_validate_addr
,
14265 .ndo_set_rx_mode
= tg3_set_rx_mode
,
14266 .ndo_set_mac_address
= tg3_set_mac_addr
,
14267 .ndo_do_ioctl
= tg3_ioctl
,
14268 .ndo_tx_timeout
= tg3_tx_timeout
,
14269 .ndo_change_mtu
= tg3_change_mtu
,
14270 .ndo_fix_features
= tg3_fix_features
,
14271 .ndo_set_features
= tg3_set_features
,
14272 #ifdef CONFIG_NET_POLL_CONTROLLER
14273 .ndo_poll_controller
= tg3_poll_controller
,
14277 static void tg3_get_eeprom_size(struct tg3
*tp
)
14279 u32 cursize
, val
, magic
;
14281 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
14283 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
14286 if ((magic
!= TG3_EEPROM_MAGIC
) &&
14287 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
14288 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
14292 * Size the chip by reading offsets at increasing powers of two.
14293 * When we encounter our validation signature, we know the addressing
14294 * has wrapped around, and thus have our chip size.
14298 while (cursize
< tp
->nvram_size
) {
14299 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
14308 tp
->nvram_size
= cursize
;
14311 static void tg3_get_nvram_size(struct tg3
*tp
)
14315 if (tg3_flag(tp
, NO_NVRAM
) || tg3_nvram_read(tp
, 0, &val
) != 0)
14318 /* Selfboot format */
14319 if (val
!= TG3_EEPROM_MAGIC
) {
14320 tg3_get_eeprom_size(tp
);
14324 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
14326 /* This is confusing. We want to operate on the
14327 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14328 * call will read from NVRAM and byteswap the data
14329 * according to the byteswapping settings for all
14330 * other register accesses. This ensures the data we
14331 * want will always reside in the lower 16-bits.
14332 * However, the data in NVRAM is in LE format, which
14333 * means the data from the NVRAM read will always be
14334 * opposite the endianness of the CPU. The 16-bit
14335 * byteswap then brings the data to CPU endianness.
14337 tp
->nvram_size
= swab16((u16
)(val
& 0x0000ffff)) * 1024;
14341 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
14344 static void tg3_get_nvram_info(struct tg3
*tp
)
14348 nvcfg1
= tr32(NVRAM_CFG1
);
14349 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
14350 tg3_flag_set(tp
, FLASH
);
14352 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
14353 tw32(NVRAM_CFG1
, nvcfg1
);
14356 if (tg3_asic_rev(tp
) == ASIC_REV_5750
||
14357 tg3_flag(tp
, 5780_CLASS
)) {
14358 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
14359 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
14360 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14361 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
14362 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14364 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
14365 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14366 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
14368 case FLASH_VENDOR_ATMEL_EEPROM
:
14369 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14370 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
14371 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14373 case FLASH_VENDOR_ST
:
14374 tp
->nvram_jedecnum
= JEDEC_ST
;
14375 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
14376 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14378 case FLASH_VENDOR_SAIFUN
:
14379 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
14380 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
14382 case FLASH_VENDOR_SST_SMALL
:
14383 case FLASH_VENDOR_SST_LARGE
:
14384 tp
->nvram_jedecnum
= JEDEC_SST
;
14385 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
14389 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14390 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
14391 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14395 static void tg3_nvram_get_pagesize(struct tg3
*tp
, u32 nvmcfg1
)
14397 switch (nvmcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
14398 case FLASH_5752PAGE_SIZE_256
:
14399 tp
->nvram_pagesize
= 256;
14401 case FLASH_5752PAGE_SIZE_512
:
14402 tp
->nvram_pagesize
= 512;
14404 case FLASH_5752PAGE_SIZE_1K
:
14405 tp
->nvram_pagesize
= 1024;
14407 case FLASH_5752PAGE_SIZE_2K
:
14408 tp
->nvram_pagesize
= 2048;
14410 case FLASH_5752PAGE_SIZE_4K
:
14411 tp
->nvram_pagesize
= 4096;
14413 case FLASH_5752PAGE_SIZE_264
:
14414 tp
->nvram_pagesize
= 264;
14416 case FLASH_5752PAGE_SIZE_528
:
14417 tp
->nvram_pagesize
= 528;
14422 static void tg3_get_5752_nvram_info(struct tg3
*tp
)
14426 nvcfg1
= tr32(NVRAM_CFG1
);
14428 /* NVRAM protection for TPM */
14429 if (nvcfg1
& (1 << 27))
14430 tg3_flag_set(tp
, PROTECTED_NVRAM
);
14432 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
14433 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
14434 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
14435 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14436 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14438 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
14439 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14440 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14441 tg3_flag_set(tp
, FLASH
);
14443 case FLASH_5752VENDOR_ST_M45PE10
:
14444 case FLASH_5752VENDOR_ST_M45PE20
:
14445 case FLASH_5752VENDOR_ST_M45PE40
:
14446 tp
->nvram_jedecnum
= JEDEC_ST
;
14447 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14448 tg3_flag_set(tp
, FLASH
);
14452 if (tg3_flag(tp
, FLASH
)) {
14453 tg3_nvram_get_pagesize(tp
, nvcfg1
);
14455 /* For eeprom, set pagesize to maximum eeprom size */
14456 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
14458 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
14459 tw32(NVRAM_CFG1
, nvcfg1
);
14463 static void tg3_get_5755_nvram_info(struct tg3
*tp
)
14465 u32 nvcfg1
, protect
= 0;
14467 nvcfg1
= tr32(NVRAM_CFG1
);
14469 /* NVRAM protection for TPM */
14470 if (nvcfg1
& (1 << 27)) {
14471 tg3_flag_set(tp
, PROTECTED_NVRAM
);
14475 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
14477 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
14478 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
14479 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
14480 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
14481 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14482 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14483 tg3_flag_set(tp
, FLASH
);
14484 tp
->nvram_pagesize
= 264;
14485 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
14486 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
14487 tp
->nvram_size
= (protect
? 0x3e200 :
14488 TG3_NVRAM_SIZE_512KB
);
14489 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
14490 tp
->nvram_size
= (protect
? 0x1f200 :
14491 TG3_NVRAM_SIZE_256KB
);
14493 tp
->nvram_size
= (protect
? 0x1f200 :
14494 TG3_NVRAM_SIZE_128KB
);
14496 case FLASH_5752VENDOR_ST_M45PE10
:
14497 case FLASH_5752VENDOR_ST_M45PE20
:
14498 case FLASH_5752VENDOR_ST_M45PE40
:
14499 tp
->nvram_jedecnum
= JEDEC_ST
;
14500 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14501 tg3_flag_set(tp
, FLASH
);
14502 tp
->nvram_pagesize
= 256;
14503 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
14504 tp
->nvram_size
= (protect
?
14505 TG3_NVRAM_SIZE_64KB
:
14506 TG3_NVRAM_SIZE_128KB
);
14507 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
14508 tp
->nvram_size
= (protect
?
14509 TG3_NVRAM_SIZE_64KB
:
14510 TG3_NVRAM_SIZE_256KB
);
14512 tp
->nvram_size
= (protect
?
14513 TG3_NVRAM_SIZE_128KB
:
14514 TG3_NVRAM_SIZE_512KB
);
14519 static void tg3_get_5787_nvram_info(struct tg3
*tp
)
14523 nvcfg1
= tr32(NVRAM_CFG1
);
14525 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
14526 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
14527 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
14528 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
14529 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
14530 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14531 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14532 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
14534 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
14535 tw32(NVRAM_CFG1
, nvcfg1
);
14537 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
14538 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
14539 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
14540 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
14541 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14542 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14543 tg3_flag_set(tp
, FLASH
);
14544 tp
->nvram_pagesize
= 264;
14546 case FLASH_5752VENDOR_ST_M45PE10
:
14547 case FLASH_5752VENDOR_ST_M45PE20
:
14548 case FLASH_5752VENDOR_ST_M45PE40
:
14549 tp
->nvram_jedecnum
= JEDEC_ST
;
14550 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14551 tg3_flag_set(tp
, FLASH
);
14552 tp
->nvram_pagesize
= 256;
14557 static void tg3_get_5761_nvram_info(struct tg3
*tp
)
14559 u32 nvcfg1
, protect
= 0;
14561 nvcfg1
= tr32(NVRAM_CFG1
);
14563 /* NVRAM protection for TPM */
14564 if (nvcfg1
& (1 << 27)) {
14565 tg3_flag_set(tp
, PROTECTED_NVRAM
);
14569 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
14571 case FLASH_5761VENDOR_ATMEL_ADB021D
:
14572 case FLASH_5761VENDOR_ATMEL_ADB041D
:
14573 case FLASH_5761VENDOR_ATMEL_ADB081D
:
14574 case FLASH_5761VENDOR_ATMEL_ADB161D
:
14575 case FLASH_5761VENDOR_ATMEL_MDB021D
:
14576 case FLASH_5761VENDOR_ATMEL_MDB041D
:
14577 case FLASH_5761VENDOR_ATMEL_MDB081D
:
14578 case FLASH_5761VENDOR_ATMEL_MDB161D
:
14579 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14580 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14581 tg3_flag_set(tp
, FLASH
);
14582 tg3_flag_set(tp
, NO_NVRAM_ADDR_TRANS
);
14583 tp
->nvram_pagesize
= 256;
14585 case FLASH_5761VENDOR_ST_A_M45PE20
:
14586 case FLASH_5761VENDOR_ST_A_M45PE40
:
14587 case FLASH_5761VENDOR_ST_A_M45PE80
:
14588 case FLASH_5761VENDOR_ST_A_M45PE16
:
14589 case FLASH_5761VENDOR_ST_M_M45PE20
:
14590 case FLASH_5761VENDOR_ST_M_M45PE40
:
14591 case FLASH_5761VENDOR_ST_M_M45PE80
:
14592 case FLASH_5761VENDOR_ST_M_M45PE16
:
14593 tp
->nvram_jedecnum
= JEDEC_ST
;
14594 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14595 tg3_flag_set(tp
, FLASH
);
14596 tp
->nvram_pagesize
= 256;
14601 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
14604 case FLASH_5761VENDOR_ATMEL_ADB161D
:
14605 case FLASH_5761VENDOR_ATMEL_MDB161D
:
14606 case FLASH_5761VENDOR_ST_A_M45PE16
:
14607 case FLASH_5761VENDOR_ST_M_M45PE16
:
14608 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
14610 case FLASH_5761VENDOR_ATMEL_ADB081D
:
14611 case FLASH_5761VENDOR_ATMEL_MDB081D
:
14612 case FLASH_5761VENDOR_ST_A_M45PE80
:
14613 case FLASH_5761VENDOR_ST_M_M45PE80
:
14614 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
14616 case FLASH_5761VENDOR_ATMEL_ADB041D
:
14617 case FLASH_5761VENDOR_ATMEL_MDB041D
:
14618 case FLASH_5761VENDOR_ST_A_M45PE40
:
14619 case FLASH_5761VENDOR_ST_M_M45PE40
:
14620 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
14622 case FLASH_5761VENDOR_ATMEL_ADB021D
:
14623 case FLASH_5761VENDOR_ATMEL_MDB021D
:
14624 case FLASH_5761VENDOR_ST_A_M45PE20
:
14625 case FLASH_5761VENDOR_ST_M_M45PE20
:
14626 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
14632 static void tg3_get_5906_nvram_info(struct tg3
*tp
)
14634 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14635 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14636 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
14639 static void tg3_get_57780_nvram_info(struct tg3
*tp
)
14643 nvcfg1
= tr32(NVRAM_CFG1
);
14645 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
14646 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
14647 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
14648 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14649 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14650 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
14652 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
14653 tw32(NVRAM_CFG1
, nvcfg1
);
14655 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
14656 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
14657 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
14658 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
14659 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
14660 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
14661 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
14662 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14663 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14664 tg3_flag_set(tp
, FLASH
);
14666 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
14667 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
14668 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
14669 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
14670 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
14672 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
14673 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
14674 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
14676 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
14677 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
14678 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
14682 case FLASH_5752VENDOR_ST_M45PE10
:
14683 case FLASH_5752VENDOR_ST_M45PE20
:
14684 case FLASH_5752VENDOR_ST_M45PE40
:
14685 tp
->nvram_jedecnum
= JEDEC_ST
;
14686 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14687 tg3_flag_set(tp
, FLASH
);
14689 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
14690 case FLASH_5752VENDOR_ST_M45PE10
:
14691 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
14693 case FLASH_5752VENDOR_ST_M45PE20
:
14694 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
14696 case FLASH_5752VENDOR_ST_M45PE40
:
14697 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
14702 tg3_flag_set(tp
, NO_NVRAM
);
14706 tg3_nvram_get_pagesize(tp
, nvcfg1
);
14707 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
14708 tg3_flag_set(tp
, NO_NVRAM_ADDR_TRANS
);
14712 static void tg3_get_5717_nvram_info(struct tg3
*tp
)
14716 nvcfg1
= tr32(NVRAM_CFG1
);
14718 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
14719 case FLASH_5717VENDOR_ATMEL_EEPROM
:
14720 case FLASH_5717VENDOR_MICRO_EEPROM
:
14721 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14722 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14723 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
14725 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
14726 tw32(NVRAM_CFG1
, nvcfg1
);
14728 case FLASH_5717VENDOR_ATMEL_MDB011D
:
14729 case FLASH_5717VENDOR_ATMEL_ADB011B
:
14730 case FLASH_5717VENDOR_ATMEL_ADB011D
:
14731 case FLASH_5717VENDOR_ATMEL_MDB021D
:
14732 case FLASH_5717VENDOR_ATMEL_ADB021B
:
14733 case FLASH_5717VENDOR_ATMEL_ADB021D
:
14734 case FLASH_5717VENDOR_ATMEL_45USPT
:
14735 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14736 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14737 tg3_flag_set(tp
, FLASH
);
14739 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
14740 case FLASH_5717VENDOR_ATMEL_MDB021D
:
14741 /* Detect size with tg3_nvram_get_size() */
14743 case FLASH_5717VENDOR_ATMEL_ADB021B
:
14744 case FLASH_5717VENDOR_ATMEL_ADB021D
:
14745 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
14748 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
14752 case FLASH_5717VENDOR_ST_M_M25PE10
:
14753 case FLASH_5717VENDOR_ST_A_M25PE10
:
14754 case FLASH_5717VENDOR_ST_M_M45PE10
:
14755 case FLASH_5717VENDOR_ST_A_M45PE10
:
14756 case FLASH_5717VENDOR_ST_M_M25PE20
:
14757 case FLASH_5717VENDOR_ST_A_M25PE20
:
14758 case FLASH_5717VENDOR_ST_M_M45PE20
:
14759 case FLASH_5717VENDOR_ST_A_M45PE20
:
14760 case FLASH_5717VENDOR_ST_25USPT
:
14761 case FLASH_5717VENDOR_ST_45USPT
:
14762 tp
->nvram_jedecnum
= JEDEC_ST
;
14763 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14764 tg3_flag_set(tp
, FLASH
);
14766 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
14767 case FLASH_5717VENDOR_ST_M_M25PE20
:
14768 case FLASH_5717VENDOR_ST_M_M45PE20
:
14769 /* Detect size with tg3_nvram_get_size() */
14771 case FLASH_5717VENDOR_ST_A_M25PE20
:
14772 case FLASH_5717VENDOR_ST_A_M45PE20
:
14773 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
14776 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
14781 tg3_flag_set(tp
, NO_NVRAM
);
14785 tg3_nvram_get_pagesize(tp
, nvcfg1
);
14786 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
14787 tg3_flag_set(tp
, NO_NVRAM_ADDR_TRANS
);
14790 static void tg3_get_5720_nvram_info(struct tg3
*tp
)
14792 u32 nvcfg1
, nvmpinstrp
;
14794 nvcfg1
= tr32(NVRAM_CFG1
);
14795 nvmpinstrp
= nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
;
14797 if (tg3_asic_rev(tp
) == ASIC_REV_5762
) {
14798 if (!(nvcfg1
& NVRAM_CFG1_5762VENDOR_MASK
)) {
14799 tg3_flag_set(tp
, NO_NVRAM
);
14803 switch (nvmpinstrp
) {
14804 case FLASH_5762_EEPROM_HD
:
14805 nvmpinstrp
= FLASH_5720_EEPROM_HD
;
14807 case FLASH_5762_EEPROM_LD
:
14808 nvmpinstrp
= FLASH_5720_EEPROM_LD
;
14810 case FLASH_5720VENDOR_M_ST_M45PE20
:
14811 /* This pinstrap supports multiple sizes, so force it
14812 * to read the actual size from location 0xf0.
14814 nvmpinstrp
= FLASH_5720VENDOR_ST_45USPT
;
14819 switch (nvmpinstrp
) {
14820 case FLASH_5720_EEPROM_HD
:
14821 case FLASH_5720_EEPROM_LD
:
14822 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14823 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14825 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
14826 tw32(NVRAM_CFG1
, nvcfg1
);
14827 if (nvmpinstrp
== FLASH_5720_EEPROM_HD
)
14828 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
14830 tp
->nvram_pagesize
= ATMEL_AT24C02_CHIP_SIZE
;
14832 case FLASH_5720VENDOR_M_ATMEL_DB011D
:
14833 case FLASH_5720VENDOR_A_ATMEL_DB011B
:
14834 case FLASH_5720VENDOR_A_ATMEL_DB011D
:
14835 case FLASH_5720VENDOR_M_ATMEL_DB021D
:
14836 case FLASH_5720VENDOR_A_ATMEL_DB021B
:
14837 case FLASH_5720VENDOR_A_ATMEL_DB021D
:
14838 case FLASH_5720VENDOR_M_ATMEL_DB041D
:
14839 case FLASH_5720VENDOR_A_ATMEL_DB041B
:
14840 case FLASH_5720VENDOR_A_ATMEL_DB041D
:
14841 case FLASH_5720VENDOR_M_ATMEL_DB081D
:
14842 case FLASH_5720VENDOR_A_ATMEL_DB081D
:
14843 case FLASH_5720VENDOR_ATMEL_45USPT
:
14844 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14845 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14846 tg3_flag_set(tp
, FLASH
);
14848 switch (nvmpinstrp
) {
14849 case FLASH_5720VENDOR_M_ATMEL_DB021D
:
14850 case FLASH_5720VENDOR_A_ATMEL_DB021B
:
14851 case FLASH_5720VENDOR_A_ATMEL_DB021D
:
14852 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
14854 case FLASH_5720VENDOR_M_ATMEL_DB041D
:
14855 case FLASH_5720VENDOR_A_ATMEL_DB041B
:
14856 case FLASH_5720VENDOR_A_ATMEL_DB041D
:
14857 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
14859 case FLASH_5720VENDOR_M_ATMEL_DB081D
:
14860 case FLASH_5720VENDOR_A_ATMEL_DB081D
:
14861 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
14864 if (tg3_asic_rev(tp
) != ASIC_REV_5762
)
14865 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
14869 case FLASH_5720VENDOR_M_ST_M25PE10
:
14870 case FLASH_5720VENDOR_M_ST_M45PE10
:
14871 case FLASH_5720VENDOR_A_ST_M25PE10
:
14872 case FLASH_5720VENDOR_A_ST_M45PE10
:
14873 case FLASH_5720VENDOR_M_ST_M25PE20
:
14874 case FLASH_5720VENDOR_M_ST_M45PE20
:
14875 case FLASH_5720VENDOR_A_ST_M25PE20
:
14876 case FLASH_5720VENDOR_A_ST_M45PE20
:
14877 case FLASH_5720VENDOR_M_ST_M25PE40
:
14878 case FLASH_5720VENDOR_M_ST_M45PE40
:
14879 case FLASH_5720VENDOR_A_ST_M25PE40
:
14880 case FLASH_5720VENDOR_A_ST_M45PE40
:
14881 case FLASH_5720VENDOR_M_ST_M25PE80
:
14882 case FLASH_5720VENDOR_M_ST_M45PE80
:
14883 case FLASH_5720VENDOR_A_ST_M25PE80
:
14884 case FLASH_5720VENDOR_A_ST_M45PE80
:
14885 case FLASH_5720VENDOR_ST_25USPT
:
14886 case FLASH_5720VENDOR_ST_45USPT
:
14887 tp
->nvram_jedecnum
= JEDEC_ST
;
14888 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14889 tg3_flag_set(tp
, FLASH
);
14891 switch (nvmpinstrp
) {
14892 case FLASH_5720VENDOR_M_ST_M25PE20
:
14893 case FLASH_5720VENDOR_M_ST_M45PE20
:
14894 case FLASH_5720VENDOR_A_ST_M25PE20
:
14895 case FLASH_5720VENDOR_A_ST_M45PE20
:
14896 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
14898 case FLASH_5720VENDOR_M_ST_M25PE40
:
14899 case FLASH_5720VENDOR_M_ST_M45PE40
:
14900 case FLASH_5720VENDOR_A_ST_M25PE40
:
14901 case FLASH_5720VENDOR_A_ST_M45PE40
:
14902 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
14904 case FLASH_5720VENDOR_M_ST_M25PE80
:
14905 case FLASH_5720VENDOR_M_ST_M45PE80
:
14906 case FLASH_5720VENDOR_A_ST_M25PE80
:
14907 case FLASH_5720VENDOR_A_ST_M45PE80
:
14908 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
14911 if (tg3_asic_rev(tp
) != ASIC_REV_5762
)
14912 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
14917 tg3_flag_set(tp
, NO_NVRAM
);
14921 tg3_nvram_get_pagesize(tp
, nvcfg1
);
14922 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
14923 tg3_flag_set(tp
, NO_NVRAM_ADDR_TRANS
);
14925 if (tg3_asic_rev(tp
) == ASIC_REV_5762
) {
14928 if (tg3_nvram_read(tp
, 0, &val
))
14931 if (val
!= TG3_EEPROM_MAGIC
&&
14932 (val
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
)
14933 tg3_flag_set(tp
, NO_NVRAM
);
14937 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
14938 static void tg3_nvram_init(struct tg3
*tp
)
14940 if (tg3_flag(tp
, IS_SSB_CORE
)) {
14941 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14942 tg3_flag_clear(tp
, NVRAM
);
14943 tg3_flag_clear(tp
, NVRAM_BUFFERED
);
14944 tg3_flag_set(tp
, NO_NVRAM
);
14948 tw32_f(GRC_EEPROM_ADDR
,
14949 (EEPROM_ADDR_FSM_RESET
|
14950 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
14951 EEPROM_ADDR_CLKPERD_SHIFT
)));
14955 /* Enable seeprom accesses. */
14956 tw32_f(GRC_LOCAL_CTRL
,
14957 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
14960 if (tg3_asic_rev(tp
) != ASIC_REV_5700
&&
14961 tg3_asic_rev(tp
) != ASIC_REV_5701
) {
14962 tg3_flag_set(tp
, NVRAM
);
14964 if (tg3_nvram_lock(tp
)) {
14965 netdev_warn(tp
->dev
,
14966 "Cannot get nvram lock, %s failed\n",
14970 tg3_enable_nvram_access(tp
);
14972 tp
->nvram_size
= 0;
14974 if (tg3_asic_rev(tp
) == ASIC_REV_5752
)
14975 tg3_get_5752_nvram_info(tp
);
14976 else if (tg3_asic_rev(tp
) == ASIC_REV_5755
)
14977 tg3_get_5755_nvram_info(tp
);
14978 else if (tg3_asic_rev(tp
) == ASIC_REV_5787
||
14979 tg3_asic_rev(tp
) == ASIC_REV_5784
||
14980 tg3_asic_rev(tp
) == ASIC_REV_5785
)
14981 tg3_get_5787_nvram_info(tp
);
14982 else if (tg3_asic_rev(tp
) == ASIC_REV_5761
)
14983 tg3_get_5761_nvram_info(tp
);
14984 else if (tg3_asic_rev(tp
) == ASIC_REV_5906
)
14985 tg3_get_5906_nvram_info(tp
);
14986 else if (tg3_asic_rev(tp
) == ASIC_REV_57780
||
14987 tg3_flag(tp
, 57765_CLASS
))
14988 tg3_get_57780_nvram_info(tp
);
14989 else if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
14990 tg3_asic_rev(tp
) == ASIC_REV_5719
)
14991 tg3_get_5717_nvram_info(tp
);
14992 else if (tg3_asic_rev(tp
) == ASIC_REV_5720
||
14993 tg3_asic_rev(tp
) == ASIC_REV_5762
)
14994 tg3_get_5720_nvram_info(tp
);
14996 tg3_get_nvram_info(tp
);
14998 if (tp
->nvram_size
== 0)
14999 tg3_get_nvram_size(tp
);
15001 tg3_disable_nvram_access(tp
);
15002 tg3_nvram_unlock(tp
);
15005 tg3_flag_clear(tp
, NVRAM
);
15006 tg3_flag_clear(tp
, NVRAM_BUFFERED
);
15008 tg3_get_eeprom_size(tp
);
15012 struct subsys_tbl_ent
{
15013 u16 subsys_vendor
, subsys_devid
;
15017 static struct subsys_tbl_ent subsys_id_to_phy_id
[] = {
15018 /* Broadcom boards. */
15019 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
15020 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6
, TG3_PHY_ID_BCM5401
},
15021 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
15022 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5
, TG3_PHY_ID_BCM5701
},
15023 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
15024 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6
, TG3_PHY_ID_BCM8002
},
15025 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
15026 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9
, 0 },
15027 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
15028 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1
, TG3_PHY_ID_BCM5701
},
15029 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
15030 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8
, TG3_PHY_ID_BCM5701
},
15031 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
15032 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7
, 0 },
15033 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
15034 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10
, TG3_PHY_ID_BCM5701
},
15035 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
15036 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12
, TG3_PHY_ID_BCM5701
},
15037 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
15038 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1
, TG3_PHY_ID_BCM5703
},
15039 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
15040 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2
, TG3_PHY_ID_BCM5703
},
15043 { TG3PCI_SUBVENDOR_ID_3COM
,
15044 TG3PCI_SUBDEVICE_ID_3COM_3C996T
, TG3_PHY_ID_BCM5401
},
15045 { TG3PCI_SUBVENDOR_ID_3COM
,
15046 TG3PCI_SUBDEVICE_ID_3COM_3C996BT
, TG3_PHY_ID_BCM5701
},
15047 { TG3PCI_SUBVENDOR_ID_3COM
,
15048 TG3PCI_SUBDEVICE_ID_3COM_3C996SX
, 0 },
15049 { TG3PCI_SUBVENDOR_ID_3COM
,
15050 TG3PCI_SUBDEVICE_ID_3COM_3C1000T
, TG3_PHY_ID_BCM5701
},
15051 { TG3PCI_SUBVENDOR_ID_3COM
,
15052 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01
, TG3_PHY_ID_BCM5701
},
15055 { TG3PCI_SUBVENDOR_ID_DELL
,
15056 TG3PCI_SUBDEVICE_ID_DELL_VIPER
, TG3_PHY_ID_BCM5401
},
15057 { TG3PCI_SUBVENDOR_ID_DELL
,
15058 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR
, TG3_PHY_ID_BCM5401
},
15059 { TG3PCI_SUBVENDOR_ID_DELL
,
15060 TG3PCI_SUBDEVICE_ID_DELL_MERLOT
, TG3_PHY_ID_BCM5411
},
15061 { TG3PCI_SUBVENDOR_ID_DELL
,
15062 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT
, TG3_PHY_ID_BCM5411
},
15064 /* Compaq boards. */
15065 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
15066 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE
, TG3_PHY_ID_BCM5701
},
15067 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
15068 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2
, TG3_PHY_ID_BCM5701
},
15069 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
15070 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING
, 0 },
15071 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
15072 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780
, TG3_PHY_ID_BCM5701
},
15073 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
15074 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2
, TG3_PHY_ID_BCM5701
},
15077 { TG3PCI_SUBVENDOR_ID_IBM
,
15078 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2
, 0 }
15081 static struct subsys_tbl_ent
*tg3_lookup_by_subsys(struct tg3
*tp
)
15085 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
15086 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
15087 tp
->pdev
->subsystem_vendor
) &&
15088 (subsys_id_to_phy_id
[i
].subsys_devid
==
15089 tp
->pdev
->subsystem_device
))
15090 return &subsys_id_to_phy_id
[i
];
15095 static void tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
15099 tp
->phy_id
= TG3_PHY_ID_INVALID
;
15100 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
15102 /* Assume an onboard device and WOL capable by default. */
15103 tg3_flag_set(tp
, EEPROM_WRITE_PROT
);
15104 tg3_flag_set(tp
, WOL_CAP
);
15106 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
15107 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
15108 tg3_flag_clear(tp
, EEPROM_WRITE_PROT
);
15109 tg3_flag_set(tp
, IS_NIC
);
15111 val
= tr32(VCPU_CFGSHDW
);
15112 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
15113 tg3_flag_set(tp
, ASPM_WORKAROUND
);
15114 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
15115 (val
& VCPU_CFGSHDW_WOL_MAGPKT
)) {
15116 tg3_flag_set(tp
, WOL_ENABLE
);
15117 device_set_wakeup_enable(&tp
->pdev
->dev
, true);
15122 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
15123 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
15124 u32 nic_cfg
, led_cfg
;
15125 u32 cfg2
= 0, cfg4
= 0, cfg5
= 0;
15126 u32 nic_phy_id
, ver
, eeprom_phy_id
;
15127 int eeprom_phy_serdes
= 0;
15129 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
15130 tp
->nic_sram_data_cfg
= nic_cfg
;
15132 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
15133 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
15134 if (tg3_asic_rev(tp
) != ASIC_REV_5700
&&
15135 tg3_asic_rev(tp
) != ASIC_REV_5701
&&
15136 tg3_asic_rev(tp
) != ASIC_REV_5703
&&
15137 (ver
> 0) && (ver
< 0x100))
15138 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
15140 if (tg3_asic_rev(tp
) == ASIC_REV_5785
)
15141 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
15143 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
15144 tg3_asic_rev(tp
) == ASIC_REV_5719
||
15145 tg3_asic_rev(tp
) == ASIC_REV_5720
)
15146 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_5
, &cfg5
);
15148 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
15149 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
15150 eeprom_phy_serdes
= 1;
15152 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
15153 if (nic_phy_id
!= 0) {
15154 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
15155 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
15157 eeprom_phy_id
= (id1
>> 16) << 10;
15158 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
15159 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
15163 tp
->phy_id
= eeprom_phy_id
;
15164 if (eeprom_phy_serdes
) {
15165 if (!tg3_flag(tp
, 5705_PLUS
))
15166 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
15168 tp
->phy_flags
|= TG3_PHYFLG_MII_SERDES
;
15171 if (tg3_flag(tp
, 5750_PLUS
))
15172 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
15173 SHASTA_EXT_LED_MODE_MASK
);
15175 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
15179 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
15180 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
15183 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
15184 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
15187 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
15188 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
15190 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15191 * read on some older 5700/5701 bootcode.
15193 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
15194 tg3_asic_rev(tp
) == ASIC_REV_5701
)
15195 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
15199 case SHASTA_EXT_LED_SHARED
:
15200 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
15201 if (tg3_chip_rev_id(tp
) != CHIPREV_ID_5750_A0
&&
15202 tg3_chip_rev_id(tp
) != CHIPREV_ID_5750_A1
)
15203 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
15204 LED_CTRL_MODE_PHY_2
);
15206 if (tg3_flag(tp
, 5717_PLUS
) ||
15207 tg3_asic_rev(tp
) == ASIC_REV_5762
)
15208 tp
->led_ctrl
|= LED_CTRL_BLINK_RATE_OVERRIDE
|
15209 LED_CTRL_BLINK_RATE_MASK
;
15213 case SHASTA_EXT_LED_MAC
:
15214 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
15217 case SHASTA_EXT_LED_COMBO
:
15218 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
15219 if (tg3_chip_rev_id(tp
) != CHIPREV_ID_5750_A0
)
15220 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
15221 LED_CTRL_MODE_PHY_2
);
15226 if ((tg3_asic_rev(tp
) == ASIC_REV_5700
||
15227 tg3_asic_rev(tp
) == ASIC_REV_5701
) &&
15228 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
15229 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
15231 if (tg3_chip_rev(tp
) == CHIPREV_5784_AX
)
15232 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
15234 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
15235 tg3_flag_set(tp
, EEPROM_WRITE_PROT
);
15236 if ((tp
->pdev
->subsystem_vendor
==
15237 PCI_VENDOR_ID_ARIMA
) &&
15238 (tp
->pdev
->subsystem_device
== 0x205a ||
15239 tp
->pdev
->subsystem_device
== 0x2063))
15240 tg3_flag_clear(tp
, EEPROM_WRITE_PROT
);
15242 tg3_flag_clear(tp
, EEPROM_WRITE_PROT
);
15243 tg3_flag_set(tp
, IS_NIC
);
15246 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
15247 tg3_flag_set(tp
, ENABLE_ASF
);
15248 if (tg3_flag(tp
, 5750_PLUS
))
15249 tg3_flag_set(tp
, ASF_NEW_HANDSHAKE
);
15252 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
15253 tg3_flag(tp
, 5750_PLUS
))
15254 tg3_flag_set(tp
, ENABLE_APE
);
15256 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
&&
15257 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
15258 tg3_flag_clear(tp
, WOL_CAP
);
15260 if (tg3_flag(tp
, WOL_CAP
) &&
15261 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
)) {
15262 tg3_flag_set(tp
, WOL_ENABLE
);
15263 device_set_wakeup_enable(&tp
->pdev
->dev
, true);
15266 if (cfg2
& (1 << 17))
15267 tp
->phy_flags
|= TG3_PHYFLG_CAPACITIVE_COUPLING
;
15269 /* serdes signal pre-emphasis in register 0x590 set by */
15270 /* bootcode if bit 18 is set */
15271 if (cfg2
& (1 << 18))
15272 tp
->phy_flags
|= TG3_PHYFLG_SERDES_PREEMPHASIS
;
15274 if ((tg3_flag(tp
, 57765_PLUS
) ||
15275 (tg3_asic_rev(tp
) == ASIC_REV_5784
&&
15276 tg3_chip_rev(tp
) != CHIPREV_5784_AX
)) &&
15277 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
15278 tp
->phy_flags
|= TG3_PHYFLG_ENABLE_APD
;
15280 if (tg3_flag(tp
, PCI_EXPRESS
)) {
15283 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
15284 if (tg3_asic_rev(tp
) != ASIC_REV_5785
&&
15285 !tg3_flag(tp
, 57765_PLUS
) &&
15286 (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
))
15287 tg3_flag_set(tp
, ASPM_WORKAROUND
);
15288 if (cfg3
& NIC_SRAM_LNK_FLAP_AVOID
)
15289 tp
->phy_flags
|= TG3_PHYFLG_KEEP_LINK_ON_PWRDN
;
15290 if (cfg3
& NIC_SRAM_1G_ON_VAUX_OK
)
15291 tp
->phy_flags
|= TG3_PHYFLG_1G_ON_VAUX_OK
;
15294 if (cfg4
& NIC_SRAM_RGMII_INBAND_DISABLE
)
15295 tg3_flag_set(tp
, RGMII_INBAND_DISABLE
);
15296 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
15297 tg3_flag_set(tp
, RGMII_EXT_IBND_RX_EN
);
15298 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
15299 tg3_flag_set(tp
, RGMII_EXT_IBND_TX_EN
);
15301 if (cfg5
& NIC_SRAM_DISABLE_1G_HALF_ADV
)
15302 tp
->phy_flags
|= TG3_PHYFLG_DISABLE_1G_HD_ADV
;
15305 if (tg3_flag(tp
, WOL_CAP
))
15306 device_set_wakeup_enable(&tp
->pdev
->dev
,
15307 tg3_flag(tp
, WOL_ENABLE
));
15309 device_set_wakeup_capable(&tp
->pdev
->dev
, false);
15312 static int tg3_ape_otp_read(struct tg3
*tp
, u32 offset
, u32
*val
)
15315 u32 val2
, off
= offset
* 8;
15317 err
= tg3_nvram_lock(tp
);
15321 tg3_ape_write32(tp
, TG3_APE_OTP_ADDR
, off
| APE_OTP_ADDR_CPU_ENABLE
);
15322 tg3_ape_write32(tp
, TG3_APE_OTP_CTRL
, APE_OTP_CTRL_PROG_EN
|
15323 APE_OTP_CTRL_CMD_RD
| APE_OTP_CTRL_START
);
15324 tg3_ape_read32(tp
, TG3_APE_OTP_CTRL
);
15327 for (i
= 0; i
< 100; i
++) {
15328 val2
= tg3_ape_read32(tp
, TG3_APE_OTP_STATUS
);
15329 if (val2
& APE_OTP_STATUS_CMD_DONE
) {
15330 *val
= tg3_ape_read32(tp
, TG3_APE_OTP_RD_DATA
);
15336 tg3_ape_write32(tp
, TG3_APE_OTP_CTRL
, 0);
15338 tg3_nvram_unlock(tp
);
15339 if (val2
& APE_OTP_STATUS_CMD_DONE
)
15345 static int tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
15350 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
15351 tw32(OTP_CTRL
, cmd
);
15353 /* Wait for up to 1 ms for command to execute. */
15354 for (i
= 0; i
< 100; i
++) {
15355 val
= tr32(OTP_STATUS
);
15356 if (val
& OTP_STATUS_CMD_DONE
)
15361 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
15364 /* Read the gphy configuration from the OTP region of the chip. The gphy
15365 * configuration is a 32-bit value that straddles the alignment boundary.
15366 * We do two 32-bit reads and then shift and merge the results.
15368 static u32
tg3_read_otp_phycfg(struct tg3
*tp
)
15370 u32 bhalf_otp
, thalf_otp
;
15372 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
15374 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
15377 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
15379 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
15382 thalf_otp
= tr32(OTP_READ_DATA
);
15384 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
15386 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
15389 bhalf_otp
= tr32(OTP_READ_DATA
);
15391 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
15394 static void tg3_phy_init_link_config(struct tg3
*tp
)
15396 u32 adv
= ADVERTISED_Autoneg
;
15398 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
15399 if (!(tp
->phy_flags
& TG3_PHYFLG_DISABLE_1G_HD_ADV
))
15400 adv
|= ADVERTISED_1000baseT_Half
;
15401 adv
|= ADVERTISED_1000baseT_Full
;
15404 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
15405 adv
|= ADVERTISED_100baseT_Half
|
15406 ADVERTISED_100baseT_Full
|
15407 ADVERTISED_10baseT_Half
|
15408 ADVERTISED_10baseT_Full
|
15411 adv
|= ADVERTISED_FIBRE
;
15413 tp
->link_config
.advertising
= adv
;
15414 tp
->link_config
.speed
= SPEED_UNKNOWN
;
15415 tp
->link_config
.duplex
= DUPLEX_UNKNOWN
;
15416 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
15417 tp
->link_config
.active_speed
= SPEED_UNKNOWN
;
15418 tp
->link_config
.active_duplex
= DUPLEX_UNKNOWN
;
15423 static int tg3_phy_probe(struct tg3
*tp
)
15425 u32 hw_phy_id_1
, hw_phy_id_2
;
15426 u32 hw_phy_id
, hw_phy_id_masked
;
15429 /* flow control autonegotiation is default behavior */
15430 tg3_flag_set(tp
, PAUSE_AUTONEG
);
15431 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
15433 if (tg3_flag(tp
, ENABLE_APE
)) {
15434 switch (tp
->pci_fn
) {
15436 tp
->phy_ape_lock
= TG3_APE_LOCK_PHY0
;
15439 tp
->phy_ape_lock
= TG3_APE_LOCK_PHY1
;
15442 tp
->phy_ape_lock
= TG3_APE_LOCK_PHY2
;
15445 tp
->phy_ape_lock
= TG3_APE_LOCK_PHY3
;
15450 if (!tg3_flag(tp
, ENABLE_ASF
) &&
15451 !(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) &&
15452 !(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
15453 tp
->phy_flags
&= ~(TG3_PHYFLG_1G_ON_VAUX_OK
|
15454 TG3_PHYFLG_KEEP_LINK_ON_PWRDN
);
15456 if (tg3_flag(tp
, USE_PHYLIB
))
15457 return tg3_phy_init(tp
);
15459 /* Reading the PHY ID register can conflict with ASF
15460 * firmware access to the PHY hardware.
15463 if (tg3_flag(tp
, ENABLE_ASF
) || tg3_flag(tp
, ENABLE_APE
)) {
15464 hw_phy_id
= hw_phy_id_masked
= TG3_PHY_ID_INVALID
;
15466 /* Now read the physical PHY_ID from the chip and verify
15467 * that it is sane. If it doesn't look good, we fall back
15468 * to either the hard-coded table based PHY_ID and failing
15469 * that the value found in the eeprom area.
15471 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
15472 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
15474 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
15475 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
15476 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
15478 hw_phy_id_masked
= hw_phy_id
& TG3_PHY_ID_MASK
;
15481 if (!err
&& TG3_KNOWN_PHY_ID(hw_phy_id_masked
)) {
15482 tp
->phy_id
= hw_phy_id
;
15483 if (hw_phy_id_masked
== TG3_PHY_ID_BCM8002
)
15484 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
15486 tp
->phy_flags
&= ~TG3_PHYFLG_PHY_SERDES
;
15488 if (tp
->phy_id
!= TG3_PHY_ID_INVALID
) {
15489 /* Do nothing, phy ID already set up in
15490 * tg3_get_eeprom_hw_cfg().
15493 struct subsys_tbl_ent
*p
;
15495 /* No eeprom signature? Try the hardcoded
15496 * subsys device table.
15498 p
= tg3_lookup_by_subsys(tp
);
15500 tp
->phy_id
= p
->phy_id
;
15501 } else if (!tg3_flag(tp
, IS_SSB_CORE
)) {
15502 /* For now we saw the IDs 0xbc050cd0,
15503 * 0xbc050f80 and 0xbc050c30 on devices
15504 * connected to an BCM4785 and there are
15505 * probably more. Just assume that the phy is
15506 * supported when it is connected to a SSB core
15513 tp
->phy_id
== TG3_PHY_ID_BCM8002
)
15514 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
15518 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) &&
15519 (tg3_asic_rev(tp
) == ASIC_REV_5719
||
15520 tg3_asic_rev(tp
) == ASIC_REV_5720
||
15521 tg3_asic_rev(tp
) == ASIC_REV_57766
||
15522 tg3_asic_rev(tp
) == ASIC_REV_5762
||
15523 (tg3_asic_rev(tp
) == ASIC_REV_5717
&&
15524 tg3_chip_rev_id(tp
) != CHIPREV_ID_5717_A0
) ||
15525 (tg3_asic_rev(tp
) == ASIC_REV_57765
&&
15526 tg3_chip_rev_id(tp
) != CHIPREV_ID_57765_A0
))) {
15527 tp
->phy_flags
|= TG3_PHYFLG_EEE_CAP
;
15529 tp
->eee
.supported
= SUPPORTED_100baseT_Full
|
15530 SUPPORTED_1000baseT_Full
;
15531 tp
->eee
.advertised
= ADVERTISED_100baseT_Full
|
15532 ADVERTISED_1000baseT_Full
;
15533 tp
->eee
.eee_enabled
= 1;
15534 tp
->eee
.tx_lpi_enabled
= 1;
15535 tp
->eee
.tx_lpi_timer
= TG3_CPMU_DBTMR1_LNKIDLE_2047US
;
15538 tg3_phy_init_link_config(tp
);
15540 if (!(tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
) &&
15541 !(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) &&
15542 !tg3_flag(tp
, ENABLE_APE
) &&
15543 !tg3_flag(tp
, ENABLE_ASF
)) {
15546 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
15547 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
15548 (bmsr
& BMSR_LSTATUS
))
15549 goto skip_phy_reset
;
15551 err
= tg3_phy_reset(tp
);
15555 tg3_phy_set_wirespeed(tp
);
15557 if (!tg3_phy_copper_an_config_ok(tp
, &dummy
)) {
15558 tg3_phy_autoneg_cfg(tp
, tp
->link_config
.advertising
,
15559 tp
->link_config
.flowctrl
);
15561 tg3_writephy(tp
, MII_BMCR
,
15562 BMCR_ANENABLE
| BMCR_ANRESTART
);
15567 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
15568 err
= tg3_init_5401phy_dsp(tp
);
15572 err
= tg3_init_5401phy_dsp(tp
);
15578 static void tg3_read_vpd(struct tg3
*tp
)
15581 unsigned int block_end
, rosize
, len
;
15585 vpd_data
= (u8
*)tg3_vpd_readblock(tp
, &vpdlen
);
15589 i
= pci_vpd_find_tag(vpd_data
, 0, vpdlen
, PCI_VPD_LRDT_RO_DATA
);
15591 goto out_not_found
;
15593 rosize
= pci_vpd_lrdt_size(&vpd_data
[i
]);
15594 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+ rosize
;
15595 i
+= PCI_VPD_LRDT_TAG_SIZE
;
15597 if (block_end
> vpdlen
)
15598 goto out_not_found
;
15600 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
15601 PCI_VPD_RO_KEYWORD_MFR_ID
);
15603 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
15605 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
15606 if (j
+ len
> block_end
|| len
!= 4 ||
15607 memcmp(&vpd_data
[j
], "1028", 4))
15610 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
15611 PCI_VPD_RO_KEYWORD_VENDOR0
);
15615 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
15617 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
15618 if (j
+ len
> block_end
)
15621 if (len
>= sizeof(tp
->fw_ver
))
15622 len
= sizeof(tp
->fw_ver
) - 1;
15623 memset(tp
->fw_ver
, 0, sizeof(tp
->fw_ver
));
15624 snprintf(tp
->fw_ver
, sizeof(tp
->fw_ver
), "%.*s bc ", len
,
15629 i
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
15630 PCI_VPD_RO_KEYWORD_PARTNO
);
15632 goto out_not_found
;
15634 len
= pci_vpd_info_field_size(&vpd_data
[i
]);
15636 i
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
15637 if (len
> TG3_BPN_SIZE
||
15638 (len
+ i
) > vpdlen
)
15639 goto out_not_found
;
15641 memcpy(tp
->board_part_number
, &vpd_data
[i
], len
);
15645 if (tp
->board_part_number
[0])
15649 if (tg3_asic_rev(tp
) == ASIC_REV_5717
) {
15650 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
||
15651 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717_C
)
15652 strcpy(tp
->board_part_number
, "BCM5717");
15653 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
)
15654 strcpy(tp
->board_part_number
, "BCM5718");
15657 } else if (tg3_asic_rev(tp
) == ASIC_REV_57780
) {
15658 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57780
)
15659 strcpy(tp
->board_part_number
, "BCM57780");
15660 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57760
)
15661 strcpy(tp
->board_part_number
, "BCM57760");
15662 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
)
15663 strcpy(tp
->board_part_number
, "BCM57790");
15664 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57788
)
15665 strcpy(tp
->board_part_number
, "BCM57788");
15668 } else if (tg3_asic_rev(tp
) == ASIC_REV_57765
) {
15669 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
)
15670 strcpy(tp
->board_part_number
, "BCM57761");
15671 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
)
15672 strcpy(tp
->board_part_number
, "BCM57765");
15673 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
)
15674 strcpy(tp
->board_part_number
, "BCM57781");
15675 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
)
15676 strcpy(tp
->board_part_number
, "BCM57785");
15677 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
)
15678 strcpy(tp
->board_part_number
, "BCM57791");
15679 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
15680 strcpy(tp
->board_part_number
, "BCM57795");
15683 } else if (tg3_asic_rev(tp
) == ASIC_REV_57766
) {
15684 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57762
)
15685 strcpy(tp
->board_part_number
, "BCM57762");
15686 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57766
)
15687 strcpy(tp
->board_part_number
, "BCM57766");
15688 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57782
)
15689 strcpy(tp
->board_part_number
, "BCM57782");
15690 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57786
)
15691 strcpy(tp
->board_part_number
, "BCM57786");
15694 } else if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
15695 strcpy(tp
->board_part_number
, "BCM95906");
15698 strcpy(tp
->board_part_number
, "none");
15702 static int tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
15706 if (tg3_nvram_read(tp
, offset
, &val
) ||
15707 (val
& 0xfc000000) != 0x0c000000 ||
15708 tg3_nvram_read(tp
, offset
+ 4, &val
) ||
15715 static void tg3_read_bc_ver(struct tg3
*tp
)
15717 u32 val
, offset
, start
, ver_offset
;
15719 bool newver
= false;
15721 if (tg3_nvram_read(tp
, 0xc, &offset
) ||
15722 tg3_nvram_read(tp
, 0x4, &start
))
15725 offset
= tg3_nvram_logical_addr(tp
, offset
);
15727 if (tg3_nvram_read(tp
, offset
, &val
))
15730 if ((val
& 0xfc000000) == 0x0c000000) {
15731 if (tg3_nvram_read(tp
, offset
+ 4, &val
))
15738 dst_off
= strlen(tp
->fw_ver
);
15741 if (TG3_VER_SIZE
- dst_off
< 16 ||
15742 tg3_nvram_read(tp
, offset
+ 8, &ver_offset
))
15745 offset
= offset
+ ver_offset
- start
;
15746 for (i
= 0; i
< 16; i
+= 4) {
15748 if (tg3_nvram_read_be32(tp
, offset
+ i
, &v
))
15751 memcpy(tp
->fw_ver
+ dst_off
+ i
, &v
, sizeof(v
));
15756 if (tg3_nvram_read(tp
, TG3_NVM_PTREV_BCVER
, &ver_offset
))
15759 major
= (ver_offset
& TG3_NVM_BCVER_MAJMSK
) >>
15760 TG3_NVM_BCVER_MAJSFT
;
15761 minor
= ver_offset
& TG3_NVM_BCVER_MINMSK
;
15762 snprintf(&tp
->fw_ver
[dst_off
], TG3_VER_SIZE
- dst_off
,
15763 "v%d.%02d", major
, minor
);
15767 static void tg3_read_hwsb_ver(struct tg3
*tp
)
15769 u32 val
, major
, minor
;
15771 /* Use native endian representation */
15772 if (tg3_nvram_read(tp
, TG3_NVM_HWSB_CFG1
, &val
))
15775 major
= (val
& TG3_NVM_HWSB_CFG1_MAJMSK
) >>
15776 TG3_NVM_HWSB_CFG1_MAJSFT
;
15777 minor
= (val
& TG3_NVM_HWSB_CFG1_MINMSK
) >>
15778 TG3_NVM_HWSB_CFG1_MINSFT
;
15780 snprintf(&tp
->fw_ver
[0], 32, "sb v%d.%02d", major
, minor
);
15783 static void tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
15785 u32 offset
, major
, minor
, build
;
15787 strncat(tp
->fw_ver
, "sb", TG3_VER_SIZE
- strlen(tp
->fw_ver
) - 1);
15789 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
15792 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
15793 case TG3_EEPROM_SB_REVISION_0
:
15794 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
15796 case TG3_EEPROM_SB_REVISION_2
:
15797 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
15799 case TG3_EEPROM_SB_REVISION_3
:
15800 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
15802 case TG3_EEPROM_SB_REVISION_4
:
15803 offset
= TG3_EEPROM_SB_F1R4_EDH_OFF
;
15805 case TG3_EEPROM_SB_REVISION_5
:
15806 offset
= TG3_EEPROM_SB_F1R5_EDH_OFF
;
15808 case TG3_EEPROM_SB_REVISION_6
:
15809 offset
= TG3_EEPROM_SB_F1R6_EDH_OFF
;
15815 if (tg3_nvram_read(tp
, offset
, &val
))
15818 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
15819 TG3_EEPROM_SB_EDH_BLD_SHFT
;
15820 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
15821 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
15822 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
15824 if (minor
> 99 || build
> 26)
15827 offset
= strlen(tp
->fw_ver
);
15828 snprintf(&tp
->fw_ver
[offset
], TG3_VER_SIZE
- offset
,
15829 " v%d.%02d", major
, minor
);
15832 offset
= strlen(tp
->fw_ver
);
15833 if (offset
< TG3_VER_SIZE
- 1)
15834 tp
->fw_ver
[offset
] = 'a' + build
- 1;
15838 static void tg3_read_mgmtfw_ver(struct tg3
*tp
)
15840 u32 val
, offset
, start
;
15843 for (offset
= TG3_NVM_DIR_START
;
15844 offset
< TG3_NVM_DIR_END
;
15845 offset
+= TG3_NVM_DIRENT_SIZE
) {
15846 if (tg3_nvram_read(tp
, offset
, &val
))
15849 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
15853 if (offset
== TG3_NVM_DIR_END
)
15856 if (!tg3_flag(tp
, 5705_PLUS
))
15857 start
= 0x08000000;
15858 else if (tg3_nvram_read(tp
, offset
- 4, &start
))
15861 if (tg3_nvram_read(tp
, offset
+ 4, &offset
) ||
15862 !tg3_fw_img_is_valid(tp
, offset
) ||
15863 tg3_nvram_read(tp
, offset
+ 8, &val
))
15866 offset
+= val
- start
;
15868 vlen
= strlen(tp
->fw_ver
);
15870 tp
->fw_ver
[vlen
++] = ',';
15871 tp
->fw_ver
[vlen
++] = ' ';
15873 for (i
= 0; i
< 4; i
++) {
15875 if (tg3_nvram_read_be32(tp
, offset
, &v
))
15878 offset
+= sizeof(v
);
15880 if (vlen
> TG3_VER_SIZE
- sizeof(v
)) {
15881 memcpy(&tp
->fw_ver
[vlen
], &v
, TG3_VER_SIZE
- vlen
);
15885 memcpy(&tp
->fw_ver
[vlen
], &v
, sizeof(v
));
15890 static void tg3_probe_ncsi(struct tg3
*tp
)
15894 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
15895 if (apedata
!= APE_SEG_SIG_MAGIC
)
15898 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
15899 if (!(apedata
& APE_FW_STATUS_READY
))
15902 if (tg3_ape_read32(tp
, TG3_APE_FW_FEATURES
) & TG3_APE_FW_FEATURE_NCSI
)
15903 tg3_flag_set(tp
, APE_HAS_NCSI
);
15906 static void tg3_read_dash_ver(struct tg3
*tp
)
15912 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_VERSION
);
15914 if (tg3_flag(tp
, APE_HAS_NCSI
))
15916 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5725
)
15921 vlen
= strlen(tp
->fw_ver
);
15923 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " %s v%d.%d.%d.%d",
15925 (apedata
& APE_FW_VERSION_MAJMSK
) >> APE_FW_VERSION_MAJSFT
,
15926 (apedata
& APE_FW_VERSION_MINMSK
) >> APE_FW_VERSION_MINSFT
,
15927 (apedata
& APE_FW_VERSION_REVMSK
) >> APE_FW_VERSION_REVSFT
,
15928 (apedata
& APE_FW_VERSION_BLDMSK
));
15931 static void tg3_read_otp_ver(struct tg3
*tp
)
15935 if (tg3_asic_rev(tp
) != ASIC_REV_5762
)
15938 if (!tg3_ape_otp_read(tp
, OTP_ADDRESS_MAGIC0
, &val
) &&
15939 !tg3_ape_otp_read(tp
, OTP_ADDRESS_MAGIC0
+ 4, &val2
) &&
15940 TG3_OTP_MAGIC0_VALID(val
)) {
15941 u64 val64
= (u64
) val
<< 32 | val2
;
15945 for (i
= 0; i
< 7; i
++) {
15946 if ((val64
& 0xff) == 0)
15948 ver
= val64
& 0xff;
15951 vlen
= strlen(tp
->fw_ver
);
15952 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " .%02d", ver
);
15956 static void tg3_read_fw_ver(struct tg3
*tp
)
15959 bool vpd_vers
= false;
15961 if (tp
->fw_ver
[0] != 0)
15964 if (tg3_flag(tp
, NO_NVRAM
)) {
15965 strcat(tp
->fw_ver
, "sb");
15966 tg3_read_otp_ver(tp
);
15970 if (tg3_nvram_read(tp
, 0, &val
))
15973 if (val
== TG3_EEPROM_MAGIC
)
15974 tg3_read_bc_ver(tp
);
15975 else if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
15976 tg3_read_sb_ver(tp
, val
);
15977 else if ((val
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
15978 tg3_read_hwsb_ver(tp
);
15980 if (tg3_flag(tp
, ENABLE_ASF
)) {
15981 if (tg3_flag(tp
, ENABLE_APE
)) {
15982 tg3_probe_ncsi(tp
);
15984 tg3_read_dash_ver(tp
);
15985 } else if (!vpd_vers
) {
15986 tg3_read_mgmtfw_ver(tp
);
15990 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
15993 static inline u32
tg3_rx_ret_ring_size(struct tg3
*tp
)
15995 if (tg3_flag(tp
, LRG_PROD_RING_CAP
))
15996 return TG3_RX_RET_MAX_SIZE_5717
;
15997 else if (tg3_flag(tp
, JUMBO_CAPABLE
) && !tg3_flag(tp
, 5780_CLASS
))
15998 return TG3_RX_RET_MAX_SIZE_5700
;
16000 return TG3_RX_RET_MAX_SIZE_5705
;
16003 static const struct pci_device_id tg3_write_reorder_chipsets
[] = {
16004 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
16005 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
16006 { PCI_DEVICE(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8385_0
) },
16010 static struct pci_dev
*tg3_find_peer(struct tg3
*tp
)
16012 struct pci_dev
*peer
;
16013 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
16015 for (func
= 0; func
< 8; func
++) {
16016 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
16017 if (peer
&& peer
!= tp
->pdev
)
16021 /* 5704 can be configured in single-port mode, set peer to
16022 * tp->pdev in that case.
16030 * We don't need to keep the refcount elevated; there's no way
16031 * to remove one half of this device without removing the other
16038 static void tg3_detect_asic_rev(struct tg3
*tp
, u32 misc_ctrl_reg
)
16040 tp
->pci_chip_rev_id
= misc_ctrl_reg
>> MISC_HOST_CTRL_CHIPREV_SHIFT
;
16041 if (tg3_asic_rev(tp
) == ASIC_REV_USE_PROD_ID_REG
) {
16044 /* All devices that use the alternate
16045 * ASIC REV location have a CPMU.
16047 tg3_flag_set(tp
, CPMU_PRESENT
);
16049 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
||
16050 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717_C
||
16051 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
||
16052 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5719
||
16053 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5720
||
16054 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57767
||
16055 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57764
||
16056 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5762
||
16057 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5725
||
16058 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5727
||
16059 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57787
)
16060 reg
= TG3PCI_GEN2_PRODID_ASICREV
;
16061 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
||
16062 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
||
16063 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
||
16064 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
||
16065 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
16066 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
||
16067 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57762
||
16068 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57766
||
16069 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57782
||
16070 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57786
)
16071 reg
= TG3PCI_GEN15_PRODID_ASICREV
;
16073 reg
= TG3PCI_PRODID_ASICREV
;
16075 pci_read_config_dword(tp
->pdev
, reg
, &tp
->pci_chip_rev_id
);
16078 /* Wrong chip ID in 5752 A0. This code can be removed later
16079 * as A0 is not in production.
16081 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5752_A0_HW
)
16082 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
16084 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5717_C0
)
16085 tp
->pci_chip_rev_id
= CHIPREV_ID_5720_A0
;
16087 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
16088 tg3_asic_rev(tp
) == ASIC_REV_5719
||
16089 tg3_asic_rev(tp
) == ASIC_REV_5720
)
16090 tg3_flag_set(tp
, 5717_PLUS
);
16092 if (tg3_asic_rev(tp
) == ASIC_REV_57765
||
16093 tg3_asic_rev(tp
) == ASIC_REV_57766
)
16094 tg3_flag_set(tp
, 57765_CLASS
);
16096 if (tg3_flag(tp
, 57765_CLASS
) || tg3_flag(tp
, 5717_PLUS
) ||
16097 tg3_asic_rev(tp
) == ASIC_REV_5762
)
16098 tg3_flag_set(tp
, 57765_PLUS
);
16100 /* Intentionally exclude ASIC_REV_5906 */
16101 if (tg3_asic_rev(tp
) == ASIC_REV_5755
||
16102 tg3_asic_rev(tp
) == ASIC_REV_5787
||
16103 tg3_asic_rev(tp
) == ASIC_REV_5784
||
16104 tg3_asic_rev(tp
) == ASIC_REV_5761
||
16105 tg3_asic_rev(tp
) == ASIC_REV_5785
||
16106 tg3_asic_rev(tp
) == ASIC_REV_57780
||
16107 tg3_flag(tp
, 57765_PLUS
))
16108 tg3_flag_set(tp
, 5755_PLUS
);
16110 if (tg3_asic_rev(tp
) == ASIC_REV_5780
||
16111 tg3_asic_rev(tp
) == ASIC_REV_5714
)
16112 tg3_flag_set(tp
, 5780_CLASS
);
16114 if (tg3_asic_rev(tp
) == ASIC_REV_5750
||
16115 tg3_asic_rev(tp
) == ASIC_REV_5752
||
16116 tg3_asic_rev(tp
) == ASIC_REV_5906
||
16117 tg3_flag(tp
, 5755_PLUS
) ||
16118 tg3_flag(tp
, 5780_CLASS
))
16119 tg3_flag_set(tp
, 5750_PLUS
);
16121 if (tg3_asic_rev(tp
) == ASIC_REV_5705
||
16122 tg3_flag(tp
, 5750_PLUS
))
16123 tg3_flag_set(tp
, 5705_PLUS
);
16126 static bool tg3_10_100_only_device(struct tg3
*tp
,
16127 const struct pci_device_id
*ent
)
16129 u32 grc_misc_cfg
= tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
;
16131 if ((tg3_asic_rev(tp
) == ASIC_REV_5703
&&
16132 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
16133 (tp
->phy_flags
& TG3_PHYFLG_IS_FET
))
16136 if (ent
->driver_data
& TG3_DRV_DATA_FLAG_10_100_ONLY
) {
16137 if (tg3_asic_rev(tp
) == ASIC_REV_5705
) {
16138 if (ent
->driver_data
& TG3_DRV_DATA_FLAG_5705_10_100
)
16148 static int tg3_get_invariants(struct tg3
*tp
, const struct pci_device_id
*ent
)
16151 u32 pci_state_reg
, grc_misc_cfg
;
16156 /* Force memory write invalidate off. If we leave it on,
16157 * then on 5700_BX chips we have to enable a workaround.
16158 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16159 * to match the cacheline size. The Broadcom driver have this
16160 * workaround but turns MWI off all the times so never uses
16161 * it. This seems to suggest that the workaround is insufficient.
16163 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
16164 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
16165 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
16167 /* Important! -- Make sure register accesses are byteswapped
16168 * correctly. Also, for those chips that require it, make
16169 * sure that indirect register accesses are enabled before
16170 * the first operation.
16172 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
16174 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
16175 MISC_HOST_CTRL_CHIPREV
);
16176 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
16177 tp
->misc_host_ctrl
);
16179 tg3_detect_asic_rev(tp
, misc_ctrl_reg
);
16181 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16182 * we need to disable memory and use config. cycles
16183 * only to access all registers. The 5702/03 chips
16184 * can mistakenly decode the special cycles from the
16185 * ICH chipsets as memory write cycles, causing corruption
16186 * of register and memory space. Only certain ICH bridges
16187 * will drive special cycles with non-zero data during the
16188 * address phase which can fall within the 5703's address
16189 * range. This is not an ICH bug as the PCI spec allows
16190 * non-zero address during special cycles. However, only
16191 * these ICH bridges are known to drive non-zero addresses
16192 * during special cycles.
16194 * Since special cycles do not cross PCI bridges, we only
16195 * enable this workaround if the 5703 is on the secondary
16196 * bus of these ICH bridges.
16198 if ((tg3_chip_rev_id(tp
) == CHIPREV_ID_5703_A1
) ||
16199 (tg3_chip_rev_id(tp
) == CHIPREV_ID_5703_A2
)) {
16200 static struct tg3_dev_id
{
16204 } ich_chipsets
[] = {
16205 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
16207 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
16209 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
16211 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
16215 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
16216 struct pci_dev
*bridge
= NULL
;
16218 while (pci_id
->vendor
!= 0) {
16219 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
16225 if (pci_id
->rev
!= PCI_ANY_ID
) {
16226 if (bridge
->revision
> pci_id
->rev
)
16229 if (bridge
->subordinate
&&
16230 (bridge
->subordinate
->number
==
16231 tp
->pdev
->bus
->number
)) {
16232 tg3_flag_set(tp
, ICH_WORKAROUND
);
16233 pci_dev_put(bridge
);
16239 if (tg3_asic_rev(tp
) == ASIC_REV_5701
) {
16240 static struct tg3_dev_id
{
16243 } bridge_chipsets
[] = {
16244 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
16245 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
16248 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
16249 struct pci_dev
*bridge
= NULL
;
16251 while (pci_id
->vendor
!= 0) {
16252 bridge
= pci_get_device(pci_id
->vendor
,
16259 if (bridge
->subordinate
&&
16260 (bridge
->subordinate
->number
<=
16261 tp
->pdev
->bus
->number
) &&
16262 (bridge
->subordinate
->busn_res
.end
>=
16263 tp
->pdev
->bus
->number
)) {
16264 tg3_flag_set(tp
, 5701_DMA_BUG
);
16265 pci_dev_put(bridge
);
16271 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16272 * DMA addresses > 40-bit. This bridge may have other additional
16273 * 57xx devices behind it in some 4-port NIC designs for example.
16274 * Any tg3 device found behind the bridge will also need the 40-bit
16277 if (tg3_flag(tp
, 5780_CLASS
)) {
16278 tg3_flag_set(tp
, 40BIT_DMA_BUG
);
16279 tp
->msi_cap
= tp
->pdev
->msi_cap
;
16281 struct pci_dev
*bridge
= NULL
;
16284 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
16285 PCI_DEVICE_ID_SERVERWORKS_EPB
,
16287 if (bridge
&& bridge
->subordinate
&&
16288 (bridge
->subordinate
->number
<=
16289 tp
->pdev
->bus
->number
) &&
16290 (bridge
->subordinate
->busn_res
.end
>=
16291 tp
->pdev
->bus
->number
)) {
16292 tg3_flag_set(tp
, 40BIT_DMA_BUG
);
16293 pci_dev_put(bridge
);
16299 if (tg3_asic_rev(tp
) == ASIC_REV_5704
||
16300 tg3_asic_rev(tp
) == ASIC_REV_5714
)
16301 tp
->pdev_peer
= tg3_find_peer(tp
);
16303 /* Determine TSO capabilities */
16304 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5719_A0
)
16305 ; /* Do nothing. HW bug. */
16306 else if (tg3_flag(tp
, 57765_PLUS
))
16307 tg3_flag_set(tp
, HW_TSO_3
);
16308 else if (tg3_flag(tp
, 5755_PLUS
) ||
16309 tg3_asic_rev(tp
) == ASIC_REV_5906
)
16310 tg3_flag_set(tp
, HW_TSO_2
);
16311 else if (tg3_flag(tp
, 5750_PLUS
)) {
16312 tg3_flag_set(tp
, HW_TSO_1
);
16313 tg3_flag_set(tp
, TSO_BUG
);
16314 if (tg3_asic_rev(tp
) == ASIC_REV_5750
&&
16315 tg3_chip_rev_id(tp
) >= CHIPREV_ID_5750_C2
)
16316 tg3_flag_clear(tp
, TSO_BUG
);
16317 } else if (tg3_asic_rev(tp
) != ASIC_REV_5700
&&
16318 tg3_asic_rev(tp
) != ASIC_REV_5701
&&
16319 tg3_chip_rev_id(tp
) != CHIPREV_ID_5705_A0
) {
16320 tg3_flag_set(tp
, FW_TSO
);
16321 tg3_flag_set(tp
, TSO_BUG
);
16322 if (tg3_asic_rev(tp
) == ASIC_REV_5705
)
16323 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
16325 tp
->fw_needed
= FIRMWARE_TG3TSO
;
16328 /* Selectively allow TSO based on operating conditions */
16329 if (tg3_flag(tp
, HW_TSO_1
) ||
16330 tg3_flag(tp
, HW_TSO_2
) ||
16331 tg3_flag(tp
, HW_TSO_3
) ||
16332 tg3_flag(tp
, FW_TSO
)) {
16333 /* For firmware TSO, assume ASF is disabled.
16334 * We'll disable TSO later if we discover ASF
16335 * is enabled in tg3_get_eeprom_hw_cfg().
16337 tg3_flag_set(tp
, TSO_CAPABLE
);
16339 tg3_flag_clear(tp
, TSO_CAPABLE
);
16340 tg3_flag_clear(tp
, TSO_BUG
);
16341 tp
->fw_needed
= NULL
;
16344 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
)
16345 tp
->fw_needed
= FIRMWARE_TG3
;
16347 if (tg3_asic_rev(tp
) == ASIC_REV_57766
)
16348 tp
->fw_needed
= FIRMWARE_TG357766
;
16352 if (tg3_flag(tp
, 5750_PLUS
)) {
16353 tg3_flag_set(tp
, SUPPORT_MSI
);
16354 if (tg3_chip_rev(tp
) == CHIPREV_5750_AX
||
16355 tg3_chip_rev(tp
) == CHIPREV_5750_BX
||
16356 (tg3_asic_rev(tp
) == ASIC_REV_5714
&&
16357 tg3_chip_rev_id(tp
) <= CHIPREV_ID_5714_A2
&&
16358 tp
->pdev_peer
== tp
->pdev
))
16359 tg3_flag_clear(tp
, SUPPORT_MSI
);
16361 if (tg3_flag(tp
, 5755_PLUS
) ||
16362 tg3_asic_rev(tp
) == ASIC_REV_5906
) {
16363 tg3_flag_set(tp
, 1SHOT_MSI
);
16366 if (tg3_flag(tp
, 57765_PLUS
)) {
16367 tg3_flag_set(tp
, SUPPORT_MSIX
);
16368 tp
->irq_max
= TG3_IRQ_MAX_VECS
;
16374 if (tp
->irq_max
> 1) {
16375 tp
->rxq_max
= TG3_RSS_MAX_NUM_QS
;
16376 tg3_rss_init_dflt_indir_tbl(tp
, TG3_RSS_MAX_NUM_QS
);
16378 if (tg3_asic_rev(tp
) == ASIC_REV_5719
||
16379 tg3_asic_rev(tp
) == ASIC_REV_5720
)
16380 tp
->txq_max
= tp
->irq_max
- 1;
16383 if (tg3_flag(tp
, 5755_PLUS
) ||
16384 tg3_asic_rev(tp
) == ASIC_REV_5906
)
16385 tg3_flag_set(tp
, SHORT_DMA_BUG
);
16387 if (tg3_asic_rev(tp
) == ASIC_REV_5719
)
16388 tp
->dma_limit
= TG3_TX_BD_DMA_MAX_4K
;
16390 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
16391 tg3_asic_rev(tp
) == ASIC_REV_5719
||
16392 tg3_asic_rev(tp
) == ASIC_REV_5720
||
16393 tg3_asic_rev(tp
) == ASIC_REV_5762
)
16394 tg3_flag_set(tp
, LRG_PROD_RING_CAP
);
16396 if (tg3_flag(tp
, 57765_PLUS
) &&
16397 tg3_chip_rev_id(tp
) != CHIPREV_ID_5719_A0
)
16398 tg3_flag_set(tp
, USE_JUMBO_BDFLAG
);
16400 if (!tg3_flag(tp
, 5705_PLUS
) ||
16401 tg3_flag(tp
, 5780_CLASS
) ||
16402 tg3_flag(tp
, USE_JUMBO_BDFLAG
))
16403 tg3_flag_set(tp
, JUMBO_CAPABLE
);
16405 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
16408 if (pci_is_pcie(tp
->pdev
)) {
16411 tg3_flag_set(tp
, PCI_EXPRESS
);
16413 pcie_capability_read_word(tp
->pdev
, PCI_EXP_LNKCTL
, &lnkctl
);
16414 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
16415 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
16416 tg3_flag_clear(tp
, HW_TSO_2
);
16417 tg3_flag_clear(tp
, TSO_CAPABLE
);
16419 if (tg3_asic_rev(tp
) == ASIC_REV_5784
||
16420 tg3_asic_rev(tp
) == ASIC_REV_5761
||
16421 tg3_chip_rev_id(tp
) == CHIPREV_ID_57780_A0
||
16422 tg3_chip_rev_id(tp
) == CHIPREV_ID_57780_A1
)
16423 tg3_flag_set(tp
, CLKREQ_BUG
);
16424 } else if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5717_A0
) {
16425 tg3_flag_set(tp
, L1PLLPD_EN
);
16427 } else if (tg3_asic_rev(tp
) == ASIC_REV_5785
) {
16428 /* BCM5785 devices are effectively PCIe devices, and should
16429 * follow PCIe codepaths, but do not have a PCIe capabilities
16432 tg3_flag_set(tp
, PCI_EXPRESS
);
16433 } else if (!tg3_flag(tp
, 5705_PLUS
) ||
16434 tg3_flag(tp
, 5780_CLASS
)) {
16435 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
16436 if (!tp
->pcix_cap
) {
16437 dev_err(&tp
->pdev
->dev
,
16438 "Cannot find PCI-X capability, aborting\n");
16442 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
16443 tg3_flag_set(tp
, PCIX_MODE
);
16446 /* If we have an AMD 762 or VIA K8T800 chipset, write
16447 * reordering to the mailbox registers done by the host
16448 * controller can cause major troubles. We read back from
16449 * every mailbox register write to force the writes to be
16450 * posted to the chip in order.
16452 if (pci_dev_present(tg3_write_reorder_chipsets
) &&
16453 !tg3_flag(tp
, PCI_EXPRESS
))
16454 tg3_flag_set(tp
, MBOX_WRITE_REORDER
);
16456 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
16457 &tp
->pci_cacheline_sz
);
16458 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
16459 &tp
->pci_lat_timer
);
16460 if (tg3_asic_rev(tp
) == ASIC_REV_5703
&&
16461 tp
->pci_lat_timer
< 64) {
16462 tp
->pci_lat_timer
= 64;
16463 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
16464 tp
->pci_lat_timer
);
16467 /* Important! -- It is critical that the PCI-X hw workaround
16468 * situation is decided before the first MMIO register access.
16470 if (tg3_chip_rev(tp
) == CHIPREV_5700_BX
) {
16471 /* 5700 BX chips need to have their TX producer index
16472 * mailboxes written twice to workaround a bug.
16474 tg3_flag_set(tp
, TXD_MBOX_HWBUG
);
16476 /* If we are in PCI-X mode, enable register write workaround.
16478 * The workaround is to use indirect register accesses
16479 * for all chip writes not to mailbox registers.
16481 if (tg3_flag(tp
, PCIX_MODE
)) {
16484 tg3_flag_set(tp
, PCIX_TARGET_HWBUG
);
16486 /* The chip can have it's power management PCI config
16487 * space registers clobbered due to this bug.
16488 * So explicitly force the chip into D0 here.
16490 pci_read_config_dword(tp
->pdev
,
16491 tp
->pdev
->pm_cap
+ PCI_PM_CTRL
,
16493 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
16494 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
16495 pci_write_config_dword(tp
->pdev
,
16496 tp
->pdev
->pm_cap
+ PCI_PM_CTRL
,
16499 /* Also, force SERR#/PERR# in PCI command. */
16500 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
16501 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
16502 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
16506 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
16507 tg3_flag_set(tp
, PCI_HIGH_SPEED
);
16508 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
16509 tg3_flag_set(tp
, PCI_32BIT
);
16511 /* Chip-specific fixup from Broadcom driver */
16512 if ((tg3_chip_rev_id(tp
) == CHIPREV_ID_5704_A0
) &&
16513 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
16514 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
16515 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
16518 /* Default fast path register access methods */
16519 tp
->read32
= tg3_read32
;
16520 tp
->write32
= tg3_write32
;
16521 tp
->read32_mbox
= tg3_read32
;
16522 tp
->write32_mbox
= tg3_write32
;
16523 tp
->write32_tx_mbox
= tg3_write32
;
16524 tp
->write32_rx_mbox
= tg3_write32
;
16526 /* Various workaround register access methods */
16527 if (tg3_flag(tp
, PCIX_TARGET_HWBUG
))
16528 tp
->write32
= tg3_write_indirect_reg32
;
16529 else if (tg3_asic_rev(tp
) == ASIC_REV_5701
||
16530 (tg3_flag(tp
, PCI_EXPRESS
) &&
16531 tg3_chip_rev_id(tp
) == CHIPREV_ID_5750_A0
)) {
16533 * Back to back register writes can cause problems on these
16534 * chips, the workaround is to read back all reg writes
16535 * except those to mailbox regs.
16537 * See tg3_write_indirect_reg32().
16539 tp
->write32
= tg3_write_flush_reg32
;
16542 if (tg3_flag(tp
, TXD_MBOX_HWBUG
) || tg3_flag(tp
, MBOX_WRITE_REORDER
)) {
16543 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
16544 if (tg3_flag(tp
, MBOX_WRITE_REORDER
))
16545 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
16548 if (tg3_flag(tp
, ICH_WORKAROUND
)) {
16549 tp
->read32
= tg3_read_indirect_reg32
;
16550 tp
->write32
= tg3_write_indirect_reg32
;
16551 tp
->read32_mbox
= tg3_read_indirect_mbox
;
16552 tp
->write32_mbox
= tg3_write_indirect_mbox
;
16553 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
16554 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
16559 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
16560 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
16561 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
16563 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
16564 tp
->read32_mbox
= tg3_read32_mbox_5906
;
16565 tp
->write32_mbox
= tg3_write32_mbox_5906
;
16566 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
16567 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
16570 if (tp
->write32
== tg3_write_indirect_reg32
||
16571 (tg3_flag(tp
, PCIX_MODE
) &&
16572 (tg3_asic_rev(tp
) == ASIC_REV_5700
||
16573 tg3_asic_rev(tp
) == ASIC_REV_5701
)))
16574 tg3_flag_set(tp
, SRAM_USE_CONFIG
);
16576 /* The memory arbiter has to be enabled in order for SRAM accesses
16577 * to succeed. Normally on powerup the tg3 chip firmware will make
16578 * sure it is enabled, but other entities such as system netboot
16579 * code might disable it.
16581 val
= tr32(MEMARB_MODE
);
16582 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
16584 tp
->pci_fn
= PCI_FUNC(tp
->pdev
->devfn
) & 3;
16585 if (tg3_asic_rev(tp
) == ASIC_REV_5704
||
16586 tg3_flag(tp
, 5780_CLASS
)) {
16587 if (tg3_flag(tp
, PCIX_MODE
)) {
16588 pci_read_config_dword(tp
->pdev
,
16589 tp
->pcix_cap
+ PCI_X_STATUS
,
16591 tp
->pci_fn
= val
& 0x7;
16593 } else if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
16594 tg3_asic_rev(tp
) == ASIC_REV_5719
||
16595 tg3_asic_rev(tp
) == ASIC_REV_5720
) {
16596 tg3_read_mem(tp
, NIC_SRAM_CPMU_STATUS
, &val
);
16597 if ((val
& NIC_SRAM_CPMUSTAT_SIG_MSK
) != NIC_SRAM_CPMUSTAT_SIG
)
16598 val
= tr32(TG3_CPMU_STATUS
);
16600 if (tg3_asic_rev(tp
) == ASIC_REV_5717
)
16601 tp
->pci_fn
= (val
& TG3_CPMU_STATUS_FMSK_5717
) ? 1 : 0;
16603 tp
->pci_fn
= (val
& TG3_CPMU_STATUS_FMSK_5719
) >>
16604 TG3_CPMU_STATUS_FSHFT_5719
;
16607 if (tg3_flag(tp
, FLUSH_POSTED_WRITES
)) {
16608 tp
->write32_tx_mbox
= tg3_write_flush_reg32
;
16609 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
16612 /* Get eeprom hw config before calling tg3_set_power_state().
16613 * In particular, the TG3_FLAG_IS_NIC flag must be
16614 * determined before calling tg3_set_power_state() so that
16615 * we know whether or not to switch out of Vaux power.
16616 * When the flag is set, it means that GPIO1 is used for eeprom
16617 * write protect and also implies that it is a LOM where GPIOs
16618 * are not used to switch power.
16620 tg3_get_eeprom_hw_cfg(tp
);
16622 if (tg3_flag(tp
, FW_TSO
) && tg3_flag(tp
, ENABLE_ASF
)) {
16623 tg3_flag_clear(tp
, TSO_CAPABLE
);
16624 tg3_flag_clear(tp
, TSO_BUG
);
16625 tp
->fw_needed
= NULL
;
16628 if (tg3_flag(tp
, ENABLE_APE
)) {
16629 /* Allow reads and writes to the
16630 * APE register and memory space.
16632 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
16633 PCISTATE_ALLOW_APE_SHMEM_WR
|
16634 PCISTATE_ALLOW_APE_PSPACE_WR
;
16635 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
16638 tg3_ape_lock_init(tp
);
16641 /* Set up tp->grc_local_ctrl before calling
16642 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16643 * will bring 5700's external PHY out of reset.
16644 * It is also used as eeprom write protect on LOMs.
16646 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
16647 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
16648 tg3_flag(tp
, EEPROM_WRITE_PROT
))
16649 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
16650 GRC_LCLCTRL_GPIO_OUTPUT1
);
16651 /* Unused GPIO3 must be driven as output on 5752 because there
16652 * are no pull-up resistors on unused GPIO pins.
16654 else if (tg3_asic_rev(tp
) == ASIC_REV_5752
)
16655 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
16657 if (tg3_asic_rev(tp
) == ASIC_REV_5755
||
16658 tg3_asic_rev(tp
) == ASIC_REV_57780
||
16659 tg3_flag(tp
, 57765_CLASS
))
16660 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
16662 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
16663 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
16664 /* Turn off the debug UART. */
16665 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
16666 if (tg3_flag(tp
, IS_NIC
))
16667 /* Keep VMain power. */
16668 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
16669 GRC_LCLCTRL_GPIO_OUTPUT0
;
16672 if (tg3_asic_rev(tp
) == ASIC_REV_5762
)
16673 tp
->grc_local_ctrl
|=
16674 tr32(GRC_LOCAL_CTRL
) & GRC_LCLCTRL_GPIO_UART_SEL
;
16676 /* Switch out of Vaux if it is a NIC */
16677 tg3_pwrsrc_switch_to_vmain(tp
);
16679 /* Derive initial jumbo mode from MTU assigned in
16680 * ether_setup() via the alloc_etherdev() call
16682 if (tp
->dev
->mtu
> ETH_DATA_LEN
&& !tg3_flag(tp
, 5780_CLASS
))
16683 tg3_flag_set(tp
, JUMBO_RING_ENABLE
);
16685 /* Determine WakeOnLan speed to use. */
16686 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
16687 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
||
16688 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B0
||
16689 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B2
) {
16690 tg3_flag_clear(tp
, WOL_SPEED_100MB
);
16692 tg3_flag_set(tp
, WOL_SPEED_100MB
);
16695 if (tg3_asic_rev(tp
) == ASIC_REV_5906
)
16696 tp
->phy_flags
|= TG3_PHYFLG_IS_FET
;
16698 /* A few boards don't want Ethernet@WireSpeed phy feature */
16699 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
16700 (tg3_asic_rev(tp
) == ASIC_REV_5705
&&
16701 (tg3_chip_rev_id(tp
) != CHIPREV_ID_5705_A0
) &&
16702 (tg3_chip_rev_id(tp
) != CHIPREV_ID_5705_A1
)) ||
16703 (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) ||
16704 (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
16705 tp
->phy_flags
|= TG3_PHYFLG_NO_ETH_WIRE_SPEED
;
16707 if (tg3_chip_rev(tp
) == CHIPREV_5703_AX
||
16708 tg3_chip_rev(tp
) == CHIPREV_5704_AX
)
16709 tp
->phy_flags
|= TG3_PHYFLG_ADC_BUG
;
16710 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5704_A0
)
16711 tp
->phy_flags
|= TG3_PHYFLG_5704_A0_BUG
;
16713 if (tg3_flag(tp
, 5705_PLUS
) &&
16714 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
16715 tg3_asic_rev(tp
) != ASIC_REV_5785
&&
16716 tg3_asic_rev(tp
) != ASIC_REV_57780
&&
16717 !tg3_flag(tp
, 57765_PLUS
)) {
16718 if (tg3_asic_rev(tp
) == ASIC_REV_5755
||
16719 tg3_asic_rev(tp
) == ASIC_REV_5787
||
16720 tg3_asic_rev(tp
) == ASIC_REV_5784
||
16721 tg3_asic_rev(tp
) == ASIC_REV_5761
) {
16722 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
16723 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
16724 tp
->phy_flags
|= TG3_PHYFLG_JITTER_BUG
;
16725 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
16726 tp
->phy_flags
|= TG3_PHYFLG_ADJUST_TRIM
;
16728 tp
->phy_flags
|= TG3_PHYFLG_BER_BUG
;
16731 if (tg3_asic_rev(tp
) == ASIC_REV_5784
&&
16732 tg3_chip_rev(tp
) != CHIPREV_5784_AX
) {
16733 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
16734 if (tp
->phy_otp
== 0)
16735 tp
->phy_otp
= TG3_OTP_DEFAULT
;
16738 if (tg3_flag(tp
, CPMU_PRESENT
))
16739 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
16741 tp
->mi_mode
= MAC_MI_MODE_BASE
;
16743 tp
->coalesce_mode
= 0;
16744 if (tg3_chip_rev(tp
) != CHIPREV_5700_AX
&&
16745 tg3_chip_rev(tp
) != CHIPREV_5700_BX
)
16746 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
16748 /* Set these bits to enable statistics workaround. */
16749 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
16750 tg3_asic_rev(tp
) == ASIC_REV_5762
||
16751 tg3_chip_rev_id(tp
) == CHIPREV_ID_5719_A0
||
16752 tg3_chip_rev_id(tp
) == CHIPREV_ID_5720_A0
) {
16753 tp
->coalesce_mode
|= HOSTCC_MODE_ATTN
;
16754 tp
->grc_mode
|= GRC_MODE_IRQ_ON_FLOW_ATTN
;
16757 if (tg3_asic_rev(tp
) == ASIC_REV_5785
||
16758 tg3_asic_rev(tp
) == ASIC_REV_57780
)
16759 tg3_flag_set(tp
, USE_PHYLIB
);
16761 err
= tg3_mdio_init(tp
);
16765 /* Initialize data/descriptor byte/word swapping. */
16766 val
= tr32(GRC_MODE
);
16767 if (tg3_asic_rev(tp
) == ASIC_REV_5720
||
16768 tg3_asic_rev(tp
) == ASIC_REV_5762
)
16769 val
&= (GRC_MODE_BYTE_SWAP_B2HRX_DATA
|
16770 GRC_MODE_WORD_SWAP_B2HRX_DATA
|
16771 GRC_MODE_B2HRX_ENABLE
|
16772 GRC_MODE_HTX2B_ENABLE
|
16773 GRC_MODE_HOST_STACKUP
);
16775 val
&= GRC_MODE_HOST_STACKUP
;
16777 tw32(GRC_MODE
, val
| tp
->grc_mode
);
16779 tg3_switch_clocks(tp
);
16781 /* Clear this out for sanity. */
16782 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
16784 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16785 tw32(TG3PCI_REG_BASE_ADDR
, 0);
16787 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
16789 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
16790 !tg3_flag(tp
, PCIX_TARGET_HWBUG
)) {
16791 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
||
16792 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B0
||
16793 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B2
||
16794 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B5
) {
16795 void __iomem
*sram_base
;
16797 /* Write some dummy words into the SRAM status block
16798 * area, see if it reads back correctly. If the return
16799 * value is bad, force enable the PCIX workaround.
16801 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
16803 writel(0x00000000, sram_base
);
16804 writel(0x00000000, sram_base
+ 4);
16805 writel(0xffffffff, sram_base
+ 4);
16806 if (readl(sram_base
) != 0x00000000)
16807 tg3_flag_set(tp
, PCIX_TARGET_HWBUG
);
16812 tg3_nvram_init(tp
);
16814 /* If the device has an NVRAM, no need to load patch firmware */
16815 if (tg3_asic_rev(tp
) == ASIC_REV_57766
&&
16816 !tg3_flag(tp
, NO_NVRAM
))
16817 tp
->fw_needed
= NULL
;
16819 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
16820 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
16822 if (tg3_asic_rev(tp
) == ASIC_REV_5705
&&
16823 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
16824 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
16825 tg3_flag_set(tp
, IS_5788
);
16827 if (!tg3_flag(tp
, IS_5788
) &&
16828 tg3_asic_rev(tp
) != ASIC_REV_5700
)
16829 tg3_flag_set(tp
, TAGGED_STATUS
);
16830 if (tg3_flag(tp
, TAGGED_STATUS
)) {
16831 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
16832 HOSTCC_MODE_CLRTICK_TXBD
);
16834 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
16835 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
16836 tp
->misc_host_ctrl
);
16839 /* Preserve the APE MAC_MODE bits */
16840 if (tg3_flag(tp
, ENABLE_APE
))
16841 tp
->mac_mode
= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
16845 if (tg3_10_100_only_device(tp
, ent
))
16846 tp
->phy_flags
|= TG3_PHYFLG_10_100_ONLY
;
16848 err
= tg3_phy_probe(tp
);
16850 dev_err(&tp
->pdev
->dev
, "phy probe failed, err %d\n", err
);
16851 /* ... but do not return immediately ... */
16856 tg3_read_fw_ver(tp
);
16858 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
16859 tp
->phy_flags
&= ~TG3_PHYFLG_USE_MI_INTERRUPT
;
16861 if (tg3_asic_rev(tp
) == ASIC_REV_5700
)
16862 tp
->phy_flags
|= TG3_PHYFLG_USE_MI_INTERRUPT
;
16864 tp
->phy_flags
&= ~TG3_PHYFLG_USE_MI_INTERRUPT
;
16867 /* 5700 {AX,BX} chips have a broken status block link
16868 * change bit implementation, so we must use the
16869 * status register in those cases.
16871 if (tg3_asic_rev(tp
) == ASIC_REV_5700
)
16872 tg3_flag_set(tp
, USE_LINKCHG_REG
);
16874 tg3_flag_clear(tp
, USE_LINKCHG_REG
);
16876 /* The led_ctrl is set during tg3_phy_probe, here we might
16877 * have to force the link status polling mechanism based
16878 * upon subsystem IDs.
16880 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
16881 tg3_asic_rev(tp
) == ASIC_REV_5701
&&
16882 !(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
16883 tp
->phy_flags
|= TG3_PHYFLG_USE_MI_INTERRUPT
;
16884 tg3_flag_set(tp
, USE_LINKCHG_REG
);
16887 /* For all SERDES we poll the MAC status register. */
16888 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
16889 tg3_flag_set(tp
, POLL_SERDES
);
16891 tg3_flag_clear(tp
, POLL_SERDES
);
16893 if (tg3_flag(tp
, ENABLE_APE
) && tg3_flag(tp
, ENABLE_ASF
))
16894 tg3_flag_set(tp
, POLL_CPMU_LINK
);
16896 tp
->rx_offset
= NET_SKB_PAD
+ NET_IP_ALIGN
;
16897 tp
->rx_copy_thresh
= TG3_RX_COPY_THRESHOLD
;
16898 if (tg3_asic_rev(tp
) == ASIC_REV_5701
&&
16899 tg3_flag(tp
, PCIX_MODE
)) {
16900 tp
->rx_offset
= NET_SKB_PAD
;
16901 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16902 tp
->rx_copy_thresh
= ~(u16
)0;
16906 tp
->rx_std_ring_mask
= TG3_RX_STD_RING_SIZE(tp
) - 1;
16907 tp
->rx_jmb_ring_mask
= TG3_RX_JMB_RING_SIZE(tp
) - 1;
16908 tp
->rx_ret_ring_mask
= tg3_rx_ret_ring_size(tp
) - 1;
16910 tp
->rx_std_max_post
= tp
->rx_std_ring_mask
+ 1;
16912 /* Increment the rx prod index on the rx std ring by at most
16913 * 8 for these chips to workaround hw errata.
16915 if (tg3_asic_rev(tp
) == ASIC_REV_5750
||
16916 tg3_asic_rev(tp
) == ASIC_REV_5752
||
16917 tg3_asic_rev(tp
) == ASIC_REV_5755
)
16918 tp
->rx_std_max_post
= 8;
16920 if (tg3_flag(tp
, ASPM_WORKAROUND
))
16921 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
16922 PCIE_PWR_MGMT_L1_THRESH_MSK
;
16927 #ifdef CONFIG_SPARC
16928 static int tg3_get_macaddr_sparc(struct tg3
*tp
)
16930 struct net_device
*dev
= tp
->dev
;
16931 struct pci_dev
*pdev
= tp
->pdev
;
16932 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
16933 const unsigned char *addr
;
16936 addr
= of_get_property(dp
, "local-mac-address", &len
);
16937 if (addr
&& len
== ETH_ALEN
) {
16938 memcpy(dev
->dev_addr
, addr
, ETH_ALEN
);
16944 static int tg3_get_default_macaddr_sparc(struct tg3
*tp
)
16946 struct net_device
*dev
= tp
->dev
;
16948 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, ETH_ALEN
);
16953 static int tg3_get_device_address(struct tg3
*tp
)
16955 struct net_device
*dev
= tp
->dev
;
16956 u32 hi
, lo
, mac_offset
;
16960 #ifdef CONFIG_SPARC
16961 if (!tg3_get_macaddr_sparc(tp
))
16965 if (tg3_flag(tp
, IS_SSB_CORE
)) {
16966 err
= ssb_gige_get_macaddr(tp
->pdev
, &dev
->dev_addr
[0]);
16967 if (!err
&& is_valid_ether_addr(&dev
->dev_addr
[0]))
16972 if (tg3_asic_rev(tp
) == ASIC_REV_5704
||
16973 tg3_flag(tp
, 5780_CLASS
)) {
16974 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
16976 if (tg3_nvram_lock(tp
))
16977 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
16979 tg3_nvram_unlock(tp
);
16980 } else if (tg3_flag(tp
, 5717_PLUS
)) {
16981 if (tp
->pci_fn
& 1)
16983 if (tp
->pci_fn
> 1)
16984 mac_offset
+= 0x18c;
16985 } else if (tg3_asic_rev(tp
) == ASIC_REV_5906
)
16988 /* First try to get it from MAC address mailbox. */
16989 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
16990 if ((hi
>> 16) == 0x484b) {
16991 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
16992 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
16994 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
16995 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
16996 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
16997 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
16998 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
17000 /* Some old bootcode may report a 0 MAC address in SRAM */
17001 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
17004 /* Next, try NVRAM. */
17005 if (!tg3_flag(tp
, NO_NVRAM
) &&
17006 !tg3_nvram_read_be32(tp
, mac_offset
+ 0, &hi
) &&
17007 !tg3_nvram_read_be32(tp
, mac_offset
+ 4, &lo
)) {
17008 memcpy(&dev
->dev_addr
[0], ((char *)&hi
) + 2, 2);
17009 memcpy(&dev
->dev_addr
[2], (char *)&lo
, sizeof(lo
));
17011 /* Finally just fetch it out of the MAC control regs. */
17013 hi
= tr32(MAC_ADDR_0_HIGH
);
17014 lo
= tr32(MAC_ADDR_0_LOW
);
17016 dev
->dev_addr
[5] = lo
& 0xff;
17017 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
17018 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
17019 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
17020 dev
->dev_addr
[1] = hi
& 0xff;
17021 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
17025 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
17026 #ifdef CONFIG_SPARC
17027 if (!tg3_get_default_macaddr_sparc(tp
))
17035 #define BOUNDARY_SINGLE_CACHELINE 1
17036 #define BOUNDARY_MULTI_CACHELINE 2
17038 static u32
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
17040 int cacheline_size
;
17044 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
17046 cacheline_size
= 1024;
17048 cacheline_size
= (int) byte
* 4;
17050 /* On 5703 and later chips, the boundary bits have no
17053 if (tg3_asic_rev(tp
) != ASIC_REV_5700
&&
17054 tg3_asic_rev(tp
) != ASIC_REV_5701
&&
17055 !tg3_flag(tp
, PCI_EXPRESS
))
17058 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
17059 goal
= BOUNDARY_MULTI_CACHELINE
;
17061 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
17062 goal
= BOUNDARY_SINGLE_CACHELINE
;
17068 if (tg3_flag(tp
, 57765_PLUS
)) {
17069 val
= goal
? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
17076 /* PCI controllers on most RISC systems tend to disconnect
17077 * when a device tries to burst across a cache-line boundary.
17078 * Therefore, letting tg3 do so just wastes PCI bandwidth.
17080 * Unfortunately, for PCI-E there are only limited
17081 * write-side controls for this, and thus for reads
17082 * we will still get the disconnects. We'll also waste
17083 * these PCI cycles for both read and write for chips
17084 * other than 5700 and 5701 which do not implement the
17087 if (tg3_flag(tp
, PCIX_MODE
) && !tg3_flag(tp
, PCI_EXPRESS
)) {
17088 switch (cacheline_size
) {
17093 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
17094 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
17095 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
17097 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
17098 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
17103 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
17104 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
17108 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
17109 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
17112 } else if (tg3_flag(tp
, PCI_EXPRESS
)) {
17113 switch (cacheline_size
) {
17117 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
17118 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
17119 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
17125 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
17126 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
17130 switch (cacheline_size
) {
17132 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
17133 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
17134 DMA_RWCTRL_WRITE_BNDRY_16
);
17139 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
17140 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
17141 DMA_RWCTRL_WRITE_BNDRY_32
);
17146 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
17147 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
17148 DMA_RWCTRL_WRITE_BNDRY_64
);
17153 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
17154 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
17155 DMA_RWCTRL_WRITE_BNDRY_128
);
17160 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
17161 DMA_RWCTRL_WRITE_BNDRY_256
);
17164 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
17165 DMA_RWCTRL_WRITE_BNDRY_512
);
17169 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
17170 DMA_RWCTRL_WRITE_BNDRY_1024
);
17179 static int tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
,
17180 int size
, bool to_device
)
17182 struct tg3_internal_buffer_desc test_desc
;
17183 u32 sram_dma_descs
;
17186 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
17188 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
17189 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
17190 tw32(RDMAC_STATUS
, 0);
17191 tw32(WDMAC_STATUS
, 0);
17193 tw32(BUFMGR_MODE
, 0);
17194 tw32(FTQ_RESET
, 0);
17196 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
17197 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
17198 test_desc
.nic_mbuf
= 0x00002100;
17199 test_desc
.len
= size
;
17202 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17203 * the *second* time the tg3 driver was getting loaded after an
17206 * Broadcom tells me:
17207 * ...the DMA engine is connected to the GRC block and a DMA
17208 * reset may affect the GRC block in some unpredictable way...
17209 * The behavior of resets to individual blocks has not been tested.
17211 * Broadcom noted the GRC reset will also reset all sub-components.
17214 test_desc
.cqid_sqid
= (13 << 8) | 2;
17216 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
17219 test_desc
.cqid_sqid
= (16 << 8) | 7;
17221 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
17224 test_desc
.flags
= 0x00000005;
17226 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
17229 val
= *(((u32
*)&test_desc
) + i
);
17230 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
17231 sram_dma_descs
+ (i
* sizeof(u32
)));
17232 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
17234 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
17237 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
17239 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
17242 for (i
= 0; i
< 40; i
++) {
17246 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
17248 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
17249 if ((val
& 0xffff) == sram_dma_descs
) {
17260 #define TEST_BUFFER_SIZE 0x2000
17262 static const struct pci_device_id tg3_dma_wait_state_chipsets
[] = {
17263 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
17267 static int tg3_test_dma(struct tg3
*tp
)
17269 dma_addr_t buf_dma
;
17270 u32
*buf
, saved_dma_rwctrl
;
17273 buf
= dma_alloc_coherent(&tp
->pdev
->dev
, TEST_BUFFER_SIZE
,
17274 &buf_dma
, GFP_KERNEL
);
17280 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
17281 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
17283 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
17285 if (tg3_flag(tp
, 57765_PLUS
))
17288 if (tg3_flag(tp
, PCI_EXPRESS
)) {
17289 /* DMA read watermark not used on PCIE */
17290 tp
->dma_rwctrl
|= 0x00180000;
17291 } else if (!tg3_flag(tp
, PCIX_MODE
)) {
17292 if (tg3_asic_rev(tp
) == ASIC_REV_5705
||
17293 tg3_asic_rev(tp
) == ASIC_REV_5750
)
17294 tp
->dma_rwctrl
|= 0x003f0000;
17296 tp
->dma_rwctrl
|= 0x003f000f;
17298 if (tg3_asic_rev(tp
) == ASIC_REV_5703
||
17299 tg3_asic_rev(tp
) == ASIC_REV_5704
) {
17300 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
17301 u32 read_water
= 0x7;
17303 /* If the 5704 is behind the EPB bridge, we can
17304 * do the less restrictive ONE_DMA workaround for
17305 * better performance.
17307 if (tg3_flag(tp
, 40BIT_DMA_BUG
) &&
17308 tg3_asic_rev(tp
) == ASIC_REV_5704
)
17309 tp
->dma_rwctrl
|= 0x8000;
17310 else if (ccval
== 0x6 || ccval
== 0x7)
17311 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
17313 if (tg3_asic_rev(tp
) == ASIC_REV_5703
)
17315 /* Set bit 23 to enable PCIX hw bug fix */
17317 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
17318 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
17320 } else if (tg3_asic_rev(tp
) == ASIC_REV_5780
) {
17321 /* 5780 always in PCIX mode */
17322 tp
->dma_rwctrl
|= 0x00144000;
17323 } else if (tg3_asic_rev(tp
) == ASIC_REV_5714
) {
17324 /* 5714 always in PCIX mode */
17325 tp
->dma_rwctrl
|= 0x00148000;
17327 tp
->dma_rwctrl
|= 0x001b000f;
17330 if (tg3_flag(tp
, ONE_DMA_AT_ONCE
))
17331 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
17333 if (tg3_asic_rev(tp
) == ASIC_REV_5703
||
17334 tg3_asic_rev(tp
) == ASIC_REV_5704
)
17335 tp
->dma_rwctrl
&= 0xfffffff0;
17337 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
17338 tg3_asic_rev(tp
) == ASIC_REV_5701
) {
17339 /* Remove this if it causes problems for some boards. */
17340 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
17342 /* On 5700/5701 chips, we need to set this bit.
17343 * Otherwise the chip will issue cacheline transactions
17344 * to streamable DMA memory with not all the byte
17345 * enables turned on. This is an error on several
17346 * RISC PCI controllers, in particular sparc64.
17348 * On 5703/5704 chips, this bit has been reassigned
17349 * a different meaning. In particular, it is used
17350 * on those chips to enable a PCI-X workaround.
17352 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
17355 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
17358 if (tg3_asic_rev(tp
) != ASIC_REV_5700
&&
17359 tg3_asic_rev(tp
) != ASIC_REV_5701
)
17362 /* It is best to perform DMA test with maximum write burst size
17363 * to expose the 5700/5701 write DMA bug.
17365 saved_dma_rwctrl
= tp
->dma_rwctrl
;
17366 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
17367 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
17372 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
17375 /* Send the buffer to the chip. */
17376 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, true);
17378 dev_err(&tp
->pdev
->dev
,
17379 "%s: Buffer write failed. err = %d\n",
17384 /* Now read it back. */
17385 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, false);
17387 dev_err(&tp
->pdev
->dev
, "%s: Buffer read failed. "
17388 "err = %d\n", __func__
, ret
);
17393 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
17397 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
17398 DMA_RWCTRL_WRITE_BNDRY_16
) {
17399 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
17400 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
17401 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
17404 dev_err(&tp
->pdev
->dev
,
17405 "%s: Buffer corrupted on read back! "
17406 "(%d != %d)\n", __func__
, p
[i
], i
);
17412 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
17418 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
17419 DMA_RWCTRL_WRITE_BNDRY_16
) {
17420 /* DMA test passed without adjusting DMA boundary,
17421 * now look for chipsets that are known to expose the
17422 * DMA bug without failing the test.
17424 if (pci_dev_present(tg3_dma_wait_state_chipsets
)) {
17425 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
17426 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
17428 /* Safe to use the calculated DMA boundary. */
17429 tp
->dma_rwctrl
= saved_dma_rwctrl
;
17432 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
17436 dma_free_coherent(&tp
->pdev
->dev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
17441 static void tg3_init_bufmgr_config(struct tg3
*tp
)
17443 if (tg3_flag(tp
, 57765_PLUS
)) {
17444 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
17445 DEFAULT_MB_RDMA_LOW_WATER_5705
;
17446 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
17447 DEFAULT_MB_MACRX_LOW_WATER_57765
;
17448 tp
->bufmgr_config
.mbuf_high_water
=
17449 DEFAULT_MB_HIGH_WATER_57765
;
17451 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
17452 DEFAULT_MB_RDMA_LOW_WATER_5705
;
17453 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
17454 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765
;
17455 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
17456 DEFAULT_MB_HIGH_WATER_JUMBO_57765
;
17457 } else if (tg3_flag(tp
, 5705_PLUS
)) {
17458 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
17459 DEFAULT_MB_RDMA_LOW_WATER_5705
;
17460 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
17461 DEFAULT_MB_MACRX_LOW_WATER_5705
;
17462 tp
->bufmgr_config
.mbuf_high_water
=
17463 DEFAULT_MB_HIGH_WATER_5705
;
17464 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
17465 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
17466 DEFAULT_MB_MACRX_LOW_WATER_5906
;
17467 tp
->bufmgr_config
.mbuf_high_water
=
17468 DEFAULT_MB_HIGH_WATER_5906
;
17471 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
17472 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
17473 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
17474 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
17475 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
17476 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
17478 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
17479 DEFAULT_MB_RDMA_LOW_WATER
;
17480 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
17481 DEFAULT_MB_MACRX_LOW_WATER
;
17482 tp
->bufmgr_config
.mbuf_high_water
=
17483 DEFAULT_MB_HIGH_WATER
;
17485 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
17486 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
17487 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
17488 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
17489 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
17490 DEFAULT_MB_HIGH_WATER_JUMBO
;
17493 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
17494 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
17497 static char *tg3_phy_string(struct tg3
*tp
)
17499 switch (tp
->phy_id
& TG3_PHY_ID_MASK
) {
17500 case TG3_PHY_ID_BCM5400
: return "5400";
17501 case TG3_PHY_ID_BCM5401
: return "5401";
17502 case TG3_PHY_ID_BCM5411
: return "5411";
17503 case TG3_PHY_ID_BCM5701
: return "5701";
17504 case TG3_PHY_ID_BCM5703
: return "5703";
17505 case TG3_PHY_ID_BCM5704
: return "5704";
17506 case TG3_PHY_ID_BCM5705
: return "5705";
17507 case TG3_PHY_ID_BCM5750
: return "5750";
17508 case TG3_PHY_ID_BCM5752
: return "5752";
17509 case TG3_PHY_ID_BCM5714
: return "5714";
17510 case TG3_PHY_ID_BCM5780
: return "5780";
17511 case TG3_PHY_ID_BCM5755
: return "5755";
17512 case TG3_PHY_ID_BCM5787
: return "5787";
17513 case TG3_PHY_ID_BCM5784
: return "5784";
17514 case TG3_PHY_ID_BCM5756
: return "5722/5756";
17515 case TG3_PHY_ID_BCM5906
: return "5906";
17516 case TG3_PHY_ID_BCM5761
: return "5761";
17517 case TG3_PHY_ID_BCM5718C
: return "5718C";
17518 case TG3_PHY_ID_BCM5718S
: return "5718S";
17519 case TG3_PHY_ID_BCM57765
: return "57765";
17520 case TG3_PHY_ID_BCM5719C
: return "5719C";
17521 case TG3_PHY_ID_BCM5720C
: return "5720C";
17522 case TG3_PHY_ID_BCM5762
: return "5762C";
17523 case TG3_PHY_ID_BCM8002
: return "8002/serdes";
17524 case 0: return "serdes";
17525 default: return "unknown";
17529 static char *tg3_bus_string(struct tg3
*tp
, char *str
)
17531 if (tg3_flag(tp
, PCI_EXPRESS
)) {
17532 strcpy(str
, "PCI Express");
17534 } else if (tg3_flag(tp
, PCIX_MODE
)) {
17535 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
17537 strcpy(str
, "PCIX:");
17539 if ((clock_ctrl
== 7) ||
17540 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
17541 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
17542 strcat(str
, "133MHz");
17543 else if (clock_ctrl
== 0)
17544 strcat(str
, "33MHz");
17545 else if (clock_ctrl
== 2)
17546 strcat(str
, "50MHz");
17547 else if (clock_ctrl
== 4)
17548 strcat(str
, "66MHz");
17549 else if (clock_ctrl
== 6)
17550 strcat(str
, "100MHz");
17552 strcpy(str
, "PCI:");
17553 if (tg3_flag(tp
, PCI_HIGH_SPEED
))
17554 strcat(str
, "66MHz");
17556 strcat(str
, "33MHz");
17558 if (tg3_flag(tp
, PCI_32BIT
))
17559 strcat(str
, ":32-bit");
17561 strcat(str
, ":64-bit");
17565 static void tg3_init_coal(struct tg3
*tp
)
17567 struct ethtool_coalesce
*ec
= &tp
->coal
;
17569 memset(ec
, 0, sizeof(*ec
));
17570 ec
->cmd
= ETHTOOL_GCOALESCE
;
17571 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
17572 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
17573 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
17574 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
17575 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
17576 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
17577 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
17578 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
17579 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
17581 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
17582 HOSTCC_MODE_CLRTICK_TXBD
)) {
17583 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
17584 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
17585 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
17586 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
17589 if (tg3_flag(tp
, 5705_PLUS
)) {
17590 ec
->rx_coalesce_usecs_irq
= 0;
17591 ec
->tx_coalesce_usecs_irq
= 0;
17592 ec
->stats_block_coalesce_usecs
= 0;
17596 static int tg3_init_one(struct pci_dev
*pdev
,
17597 const struct pci_device_id
*ent
)
17599 struct net_device
*dev
;
17602 u32 sndmbx
, rcvmbx
, intmbx
;
17604 u64 dma_mask
, persist_dma_mask
;
17605 netdev_features_t features
= 0;
17607 printk_once(KERN_INFO
"%s\n", version
);
17609 err
= pci_enable_device(pdev
);
17611 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
17615 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
17617 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
17618 goto err_out_disable_pdev
;
17621 pci_set_master(pdev
);
17623 dev
= alloc_etherdev_mq(sizeof(*tp
), TG3_IRQ_MAX_VECS
);
17626 goto err_out_free_res
;
17629 SET_NETDEV_DEV(dev
, &pdev
->dev
);
17631 tp
= netdev_priv(dev
);
17634 tp
->rx_mode
= TG3_DEF_RX_MODE
;
17635 tp
->tx_mode
= TG3_DEF_TX_MODE
;
17637 tp
->pcierr_recovery
= false;
17640 tp
->msg_enable
= tg3_debug
;
17642 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
17644 if (pdev_is_ssb_gige_core(pdev
)) {
17645 tg3_flag_set(tp
, IS_SSB_CORE
);
17646 if (ssb_gige_must_flush_posted_writes(pdev
))
17647 tg3_flag_set(tp
, FLUSH_POSTED_WRITES
);
17648 if (ssb_gige_one_dma_at_once(pdev
))
17649 tg3_flag_set(tp
, ONE_DMA_AT_ONCE
);
17650 if (ssb_gige_have_roboswitch(pdev
)) {
17651 tg3_flag_set(tp
, USE_PHYLIB
);
17652 tg3_flag_set(tp
, ROBOSWITCH
);
17654 if (ssb_gige_is_rgmii(pdev
))
17655 tg3_flag_set(tp
, RGMII_MODE
);
17658 /* The word/byte swap controls here control register access byte
17659 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17662 tp
->misc_host_ctrl
=
17663 MISC_HOST_CTRL_MASK_PCI_INT
|
17664 MISC_HOST_CTRL_WORD_SWAP
|
17665 MISC_HOST_CTRL_INDIR_ACCESS
|
17666 MISC_HOST_CTRL_PCISTATE_RW
;
17668 /* The NONFRM (non-frame) byte/word swap controls take effect
17669 * on descriptor entries, anything which isn't packet data.
17671 * The StrongARM chips on the board (one for tx, one for rx)
17672 * are running in big-endian mode.
17674 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
17675 GRC_MODE_WSWAP_NONFRM_DATA
);
17676 #ifdef __BIG_ENDIAN
17677 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
17679 spin_lock_init(&tp
->lock
);
17680 spin_lock_init(&tp
->indirect_lock
);
17681 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
17683 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
17685 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
17687 goto err_out_free_dev
;
17690 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
17691 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761E
||
17692 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
||
17693 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761SE
||
17694 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
||
17695 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717_C
||
17696 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
||
17697 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5719
||
17698 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5720
||
17699 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57767
||
17700 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57764
||
17701 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5762
||
17702 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5725
||
17703 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5727
||
17704 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57787
) {
17705 tg3_flag_set(tp
, ENABLE_APE
);
17706 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
17707 if (!tp
->aperegs
) {
17708 dev_err(&pdev
->dev
,
17709 "Cannot map APE registers, aborting\n");
17711 goto err_out_iounmap
;
17715 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
17716 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
17718 dev
->ethtool_ops
= &tg3_ethtool_ops
;
17719 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
17720 dev
->netdev_ops
= &tg3_netdev_ops
;
17721 dev
->irq
= pdev
->irq
;
17723 err
= tg3_get_invariants(tp
, ent
);
17725 dev_err(&pdev
->dev
,
17726 "Problem fetching invariants of chip, aborting\n");
17727 goto err_out_apeunmap
;
17730 /* The EPB bridge inside 5714, 5715, and 5780 and any
17731 * device behind the EPB cannot support DMA addresses > 40-bit.
17732 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17733 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17734 * do DMA address check in tg3_start_xmit().
17736 if (tg3_flag(tp
, IS_5788
))
17737 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(32);
17738 else if (tg3_flag(tp
, 40BIT_DMA_BUG
)) {
17739 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
17740 #ifdef CONFIG_HIGHMEM
17741 dma_mask
= DMA_BIT_MASK(64);
17744 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
17746 /* Configure DMA attributes. */
17747 if (dma_mask
> DMA_BIT_MASK(32)) {
17748 err
= pci_set_dma_mask(pdev
, dma_mask
);
17750 features
|= NETIF_F_HIGHDMA
;
17751 err
= pci_set_consistent_dma_mask(pdev
,
17754 dev_err(&pdev
->dev
, "Unable to obtain 64 bit "
17755 "DMA for consistent allocations\n");
17756 goto err_out_apeunmap
;
17760 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
17761 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
17763 dev_err(&pdev
->dev
,
17764 "No usable DMA configuration, aborting\n");
17765 goto err_out_apeunmap
;
17769 tg3_init_bufmgr_config(tp
);
17771 /* 5700 B0 chips do not support checksumming correctly due
17772 * to hardware bugs.
17774 if (tg3_chip_rev_id(tp
) != CHIPREV_ID_5700_B0
) {
17775 features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_RXCSUM
;
17777 if (tg3_flag(tp
, 5755_PLUS
))
17778 features
|= NETIF_F_IPV6_CSUM
;
17781 /* TSO is on by default on chips that support hardware TSO.
17782 * Firmware TSO on older chips gives lower performance, so it
17783 * is off by default, but can be enabled using ethtool.
17785 if ((tg3_flag(tp
, HW_TSO_1
) ||
17786 tg3_flag(tp
, HW_TSO_2
) ||
17787 tg3_flag(tp
, HW_TSO_3
)) &&
17788 (features
& NETIF_F_IP_CSUM
))
17789 features
|= NETIF_F_TSO
;
17790 if (tg3_flag(tp
, HW_TSO_2
) || tg3_flag(tp
, HW_TSO_3
)) {
17791 if (features
& NETIF_F_IPV6_CSUM
)
17792 features
|= NETIF_F_TSO6
;
17793 if (tg3_flag(tp
, HW_TSO_3
) ||
17794 tg3_asic_rev(tp
) == ASIC_REV_5761
||
17795 (tg3_asic_rev(tp
) == ASIC_REV_5784
&&
17796 tg3_chip_rev(tp
) != CHIPREV_5784_AX
) ||
17797 tg3_asic_rev(tp
) == ASIC_REV_5785
||
17798 tg3_asic_rev(tp
) == ASIC_REV_57780
)
17799 features
|= NETIF_F_TSO_ECN
;
17802 dev
->features
|= features
| NETIF_F_HW_VLAN_CTAG_TX
|
17803 NETIF_F_HW_VLAN_CTAG_RX
;
17804 dev
->vlan_features
|= features
;
17807 * Add loopback capability only for a subset of devices that support
17808 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17809 * loopback for the remaining devices.
17811 if (tg3_asic_rev(tp
) != ASIC_REV_5780
&&
17812 !tg3_flag(tp
, CPMU_PRESENT
))
17813 /* Add the loopback capability */
17814 features
|= NETIF_F_LOOPBACK
;
17816 dev
->hw_features
|= features
;
17817 dev
->priv_flags
|= IFF_UNICAST_FLT
;
17819 /* MTU range: 60 - 9000 or 1500, depending on hardware */
17820 dev
->min_mtu
= TG3_MIN_MTU
;
17821 dev
->max_mtu
= TG3_MAX_MTU(tp
);
17823 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5705_A1
&&
17824 !tg3_flag(tp
, TSO_CAPABLE
) &&
17825 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
17826 tg3_flag_set(tp
, MAX_RXPEND_64
);
17827 tp
->rx_pending
= 63;
17830 err
= tg3_get_device_address(tp
);
17832 dev_err(&pdev
->dev
,
17833 "Could not obtain valid ethernet address, aborting\n");
17834 goto err_out_apeunmap
;
17837 intmbx
= MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
;
17838 rcvmbx
= MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
;
17839 sndmbx
= MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
17840 for (i
= 0; i
< tp
->irq_max
; i
++) {
17841 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
17844 tnapi
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
17846 tnapi
->int_mbox
= intmbx
;
17852 tnapi
->consmbox
= rcvmbx
;
17853 tnapi
->prodmbox
= sndmbx
;
17856 tnapi
->coal_now
= HOSTCC_MODE_COAL_VEC1_NOW
<< (i
- 1);
17858 tnapi
->coal_now
= HOSTCC_MODE_NOW
;
17860 if (!tg3_flag(tp
, SUPPORT_MSIX
))
17864 * If we support MSIX, we'll be using RSS. If we're using
17865 * RSS, the first vector only handles link interrupts and the
17866 * remaining vectors handle rx and tx interrupts. Reuse the
17867 * mailbox values for the next iteration. The values we setup
17868 * above are still useful for the single vectored mode.
17882 * Reset chip in case UNDI or EFI driver did not shutdown
17883 * DMA self test will enable WDMAC and we'll see (spurious)
17884 * pending DMA on the PCI bus at that point.
17886 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
17887 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
17888 tg3_full_lock(tp
, 0);
17889 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
17890 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
17891 tg3_full_unlock(tp
);
17894 err
= tg3_test_dma(tp
);
17896 dev_err(&pdev
->dev
, "DMA engine test failed, aborting\n");
17897 goto err_out_apeunmap
;
17902 pci_set_drvdata(pdev
, dev
);
17904 if (tg3_asic_rev(tp
) == ASIC_REV_5719
||
17905 tg3_asic_rev(tp
) == ASIC_REV_5720
||
17906 tg3_asic_rev(tp
) == ASIC_REV_5762
)
17907 tg3_flag_set(tp
, PTP_CAPABLE
);
17909 tg3_timer_init(tp
);
17911 tg3_carrier_off(tp
);
17913 err
= register_netdev(dev
);
17915 dev_err(&pdev
->dev
, "Cannot register net device, aborting\n");
17916 goto err_out_apeunmap
;
17919 if (tg3_flag(tp
, PTP_CAPABLE
)) {
17921 tp
->ptp_clock
= ptp_clock_register(&tp
->ptp_info
,
17923 if (IS_ERR(tp
->ptp_clock
))
17924 tp
->ptp_clock
= NULL
;
17927 netdev_info(dev
, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17928 tp
->board_part_number
,
17929 tg3_chip_rev_id(tp
),
17930 tg3_bus_string(tp
, str
),
17933 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
)) {
17936 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
17937 ethtype
= "10/100Base-TX";
17938 else if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
17939 ethtype
= "1000Base-SX";
17941 ethtype
= "10/100/1000Base-T";
17943 netdev_info(dev
, "attached PHY is %s (%s Ethernet) "
17944 "(WireSpeed[%d], EEE[%d])\n",
17945 tg3_phy_string(tp
), ethtype
,
17946 (tp
->phy_flags
& TG3_PHYFLG_NO_ETH_WIRE_SPEED
) == 0,
17947 (tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
) != 0);
17950 netdev_info(dev
, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
17951 (dev
->features
& NETIF_F_RXCSUM
) != 0,
17952 tg3_flag(tp
, USE_LINKCHG_REG
) != 0,
17953 (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
) != 0,
17954 tg3_flag(tp
, ENABLE_ASF
) != 0,
17955 tg3_flag(tp
, TSO_CAPABLE
) != 0);
17956 netdev_info(dev
, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17958 pdev
->dma_mask
== DMA_BIT_MASK(32) ? 32 :
17959 ((u64
)pdev
->dma_mask
) == DMA_BIT_MASK(40) ? 40 : 64);
17961 pci_save_state(pdev
);
17967 iounmap(tp
->aperegs
);
17968 tp
->aperegs
= NULL
;
17981 pci_release_regions(pdev
);
17983 err_out_disable_pdev
:
17984 if (pci_is_enabled(pdev
))
17985 pci_disable_device(pdev
);
17989 static void tg3_remove_one(struct pci_dev
*pdev
)
17991 struct net_device
*dev
= pci_get_drvdata(pdev
);
17994 struct tg3
*tp
= netdev_priv(dev
);
17998 release_firmware(tp
->fw
);
18000 tg3_reset_task_cancel(tp
);
18002 if (tg3_flag(tp
, USE_PHYLIB
)) {
18007 unregister_netdev(dev
);
18009 iounmap(tp
->aperegs
);
18010 tp
->aperegs
= NULL
;
18017 pci_release_regions(pdev
);
18018 pci_disable_device(pdev
);
18022 #ifdef CONFIG_PM_SLEEP
18023 static int tg3_suspend(struct device
*device
)
18025 struct pci_dev
*pdev
= to_pci_dev(device
);
18026 struct net_device
*dev
= pci_get_drvdata(pdev
);
18027 struct tg3
*tp
= netdev_priv(dev
);
18032 if (!netif_running(dev
))
18035 tg3_reset_task_cancel(tp
);
18037 tg3_netif_stop(tp
);
18039 tg3_timer_stop(tp
);
18041 tg3_full_lock(tp
, 1);
18042 tg3_disable_ints(tp
);
18043 tg3_full_unlock(tp
);
18045 netif_device_detach(dev
);
18047 tg3_full_lock(tp
, 0);
18048 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
18049 tg3_flag_clear(tp
, INIT_COMPLETE
);
18050 tg3_full_unlock(tp
);
18052 err
= tg3_power_down_prepare(tp
);
18056 tg3_full_lock(tp
, 0);
18058 tg3_flag_set(tp
, INIT_COMPLETE
);
18059 err2
= tg3_restart_hw(tp
, true);
18063 tg3_timer_start(tp
);
18065 netif_device_attach(dev
);
18066 tg3_netif_start(tp
);
18069 tg3_full_unlock(tp
);
18080 static int tg3_resume(struct device
*device
)
18082 struct pci_dev
*pdev
= to_pci_dev(device
);
18083 struct net_device
*dev
= pci_get_drvdata(pdev
);
18084 struct tg3
*tp
= netdev_priv(dev
);
18089 if (!netif_running(dev
))
18092 netif_device_attach(dev
);
18094 tg3_full_lock(tp
, 0);
18096 tg3_ape_driver_state_change(tp
, RESET_KIND_INIT
);
18098 tg3_flag_set(tp
, INIT_COMPLETE
);
18099 err
= tg3_restart_hw(tp
,
18100 !(tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
));
18104 tg3_timer_start(tp
);
18106 tg3_netif_start(tp
);
18109 tg3_full_unlock(tp
);
18118 #endif /* CONFIG_PM_SLEEP */
18120 static SIMPLE_DEV_PM_OPS(tg3_pm_ops
, tg3_suspend
, tg3_resume
);
18122 static void tg3_shutdown(struct pci_dev
*pdev
)
18124 struct net_device
*dev
= pci_get_drvdata(pdev
);
18125 struct tg3
*tp
= netdev_priv(dev
);
18128 netif_device_detach(dev
);
18130 if (netif_running(dev
))
18133 if (system_state
== SYSTEM_POWER_OFF
)
18134 tg3_power_down(tp
);
18140 * tg3_io_error_detected - called when PCI error is detected
18141 * @pdev: Pointer to PCI device
18142 * @state: The current pci connection state
18144 * This function is called after a PCI bus error affecting
18145 * this device has been detected.
18147 static pci_ers_result_t
tg3_io_error_detected(struct pci_dev
*pdev
,
18148 pci_channel_state_t state
)
18150 struct net_device
*netdev
= pci_get_drvdata(pdev
);
18151 struct tg3
*tp
= netdev_priv(netdev
);
18152 pci_ers_result_t err
= PCI_ERS_RESULT_NEED_RESET
;
18154 netdev_info(netdev
, "PCI I/O error detected\n");
18158 /* We probably don't have netdev yet */
18159 if (!netdev
|| !netif_running(netdev
))
18162 /* We needn't recover from permanent error */
18163 if (state
== pci_channel_io_frozen
)
18164 tp
->pcierr_recovery
= true;
18168 tg3_netif_stop(tp
);
18170 tg3_timer_stop(tp
);
18172 /* Want to make sure that the reset task doesn't run */
18173 tg3_reset_task_cancel(tp
);
18175 netif_device_detach(netdev
);
18177 /* Clean up software state, even if MMIO is blocked */
18178 tg3_full_lock(tp
, 0);
18179 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
18180 tg3_full_unlock(tp
);
18183 if (state
== pci_channel_io_perm_failure
) {
18185 tg3_napi_enable(tp
);
18188 err
= PCI_ERS_RESULT_DISCONNECT
;
18190 pci_disable_device(pdev
);
18199 * tg3_io_slot_reset - called after the pci bus has been reset.
18200 * @pdev: Pointer to PCI device
18202 * Restart the card from scratch, as if from a cold-boot.
18203 * At this point, the card has exprienced a hard reset,
18204 * followed by fixups by BIOS, and has its config space
18205 * set up identically to what it was at cold boot.
18207 static pci_ers_result_t
tg3_io_slot_reset(struct pci_dev
*pdev
)
18209 struct net_device
*netdev
= pci_get_drvdata(pdev
);
18210 struct tg3
*tp
= netdev_priv(netdev
);
18211 pci_ers_result_t rc
= PCI_ERS_RESULT_DISCONNECT
;
18216 if (pci_enable_device(pdev
)) {
18217 dev_err(&pdev
->dev
,
18218 "Cannot re-enable PCI device after reset.\n");
18222 pci_set_master(pdev
);
18223 pci_restore_state(pdev
);
18224 pci_save_state(pdev
);
18226 if (!netdev
|| !netif_running(netdev
)) {
18227 rc
= PCI_ERS_RESULT_RECOVERED
;
18231 err
= tg3_power_up(tp
);
18235 rc
= PCI_ERS_RESULT_RECOVERED
;
18238 if (rc
!= PCI_ERS_RESULT_RECOVERED
&& netdev
&& netif_running(netdev
)) {
18239 tg3_napi_enable(tp
);
18248 * tg3_io_resume - called when traffic can start flowing again.
18249 * @pdev: Pointer to PCI device
18251 * This callback is called when the error recovery driver tells
18252 * us that its OK to resume normal operation.
18254 static void tg3_io_resume(struct pci_dev
*pdev
)
18256 struct net_device
*netdev
= pci_get_drvdata(pdev
);
18257 struct tg3
*tp
= netdev_priv(netdev
);
18262 if (!netdev
|| !netif_running(netdev
))
18265 tg3_full_lock(tp
, 0);
18266 tg3_ape_driver_state_change(tp
, RESET_KIND_INIT
);
18267 tg3_flag_set(tp
, INIT_COMPLETE
);
18268 err
= tg3_restart_hw(tp
, true);
18270 tg3_full_unlock(tp
);
18271 netdev_err(netdev
, "Cannot restart hardware after reset.\n");
18275 netif_device_attach(netdev
);
18277 tg3_timer_start(tp
);
18279 tg3_netif_start(tp
);
18281 tg3_full_unlock(tp
);
18286 tp
->pcierr_recovery
= false;
18290 static const struct pci_error_handlers tg3_err_handler
= {
18291 .error_detected
= tg3_io_error_detected
,
18292 .slot_reset
= tg3_io_slot_reset
,
18293 .resume
= tg3_io_resume
18296 static struct pci_driver tg3_driver
= {
18297 .name
= DRV_MODULE_NAME
,
18298 .id_table
= tg3_pci_tbl
,
18299 .probe
= tg3_init_one
,
18300 .remove
= tg3_remove_one
,
18301 .err_handler
= &tg3_err_handler
,
18302 .driver
.pm
= &tg3_pm_ops
,
18303 .shutdown
= tg3_shutdown
,
18306 module_pci_driver(tg3_driver
);