1 /* bnx2x_reg.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * The registers description starts with the register Access type followed
10 * by size in bits. For example [RW 32]. The access types are:
14 * ST - Statistics register (clear on read)
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
24 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
25 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
26 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
27 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
28 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
29 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
30 /* [RW 1] Initiate the ATC array - reset all the valid bits */
31 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
32 /* [R 1] ATC initalization done */
33 #define ATC_REG_ATC_INIT_DONE 0x1100bc
34 /* [RC 6] Interrupt register #0 read clear */
35 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
36 /* [RW 5] Parity mask register #0 read/write */
37 #define ATC_REG_ATC_PRTY_MASK 0x1101d8
38 /* [RC 5] Parity register #0 read clear */
39 #define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0
40 /* [RW 19] Interrupt mask register #0 read/write */
41 #define BRB1_REG_BRB1_INT_MASK 0x60128
42 /* [R 19] Interrupt register #0 read */
43 #define BRB1_REG_BRB1_INT_STS 0x6011c
44 /* [RW 4] Parity mask register #0 read/write */
45 #define BRB1_REG_BRB1_PRTY_MASK 0x60138
46 /* [R 4] Parity register #0 read */
47 #define BRB1_REG_BRB1_PRTY_STS 0x6012c
48 /* [RC 4] Parity register #0 read clear */
49 #define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130
50 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
51 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
52 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
53 * following reset the first rbc access to this reg must be write; there can
54 * be no more rbc writes after the first one; there can be any number of rbc
55 * read following the first write; rbc access not following these rules will
56 * result in hang condition. */
57 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
58 /* [RW 10] The number of free blocks below which the full signal to class 0
60 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0
61 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230
62 /* [RW 11] The number of free blocks above which the full signal to class 0
64 #define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4
65 #define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234
66 /* [RW 11] The number of free blocks below which the full signal to class 1
68 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8
69 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238
70 /* [RW 11] The number of free blocks above which the full signal to class 1
72 #define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc
73 #define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c
74 /* [RW 11] The number of free blocks below which the full signal to the LB
76 #define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0
77 /* [RW 10] The number of free blocks above which the full signal to the LB
78 * port is de-asserted */
79 #define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4
80 /* [RW 10] The number of free blocks above which the High_llfc signal to
81 interface #n is de-asserted. */
82 #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
83 /* [RW 10] The number of free blocks below which the High_llfc signal to
84 interface #n is asserted. */
85 #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
86 /* [RW 11] The number of blocks guarantied for the LB port */
87 #define BRB1_REG_LB_GUARANTIED 0x601ec
88 /* [RW 11] The hysteresis on the guarantied buffer space for the Lb port
89 * before signaling XON. */
90 #define BRB1_REG_LB_GUARANTIED_HYST 0x60264
91 /* [RW 24] LL RAM data. */
92 #define BRB1_REG_LL_RAM 0x61000
93 /* [RW 10] The number of free blocks above which the Low_llfc signal to
94 interface #n is de-asserted. */
95 #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
96 /* [RW 10] The number of free blocks below which the Low_llfc signal to
97 interface #n is asserted. */
98 #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
99 /* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The
100 * register is applicable only when per_class_guaranty_mode is set. */
101 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244
102 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
103 * 1 before signaling XON. The register is applicable only when
104 * per_class_guaranty_mode is set. */
105 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254
106 /* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The
107 * register is applicable only when per_class_guaranty_mode is set. */
108 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248
109 /* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0
110 * before signaling XON. The register is applicable only when
111 * per_class_guaranty_mode is set. */
112 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258
113 /* [RW 11] The number of blocks guarantied for class 0in MAC1.The register
114 * is applicable only when per_class_guaranty_mode is set. */
115 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c
116 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
117 * 1 before signaling XON. The register is applicable only when
118 * per_class_guaranty_mode is set. */
119 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c
120 /* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The
121 * register is applicable only when per_class_guaranty_mode is set. */
122 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250
123 /* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC
124 * 1 before signaling XON. The register is applicable only when
125 * per_class_guaranty_mode is set. */
126 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260
127 /* [RW 11] The number of blocks guarantied for the MAC port. The register is
128 * applicable only when per_class_guaranty_mode is reset. */
129 #define BRB1_REG_MAC_GUARANTIED_0 0x601e8
130 #define BRB1_REG_MAC_GUARANTIED_1 0x60240
131 /* [R 24] The number of full blocks. */
132 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
133 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
135 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
136 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
137 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
138 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
140 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
141 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
142 /* [RW 10] The number of free blocks below which the pause signal to class 0
144 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0
145 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220
146 /* [RW 11] The number of free blocks above which the pause signal to class 0
148 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4
149 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224
150 /* [RW 11] The number of free blocks below which the pause signal to class 1
152 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8
153 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228
154 /* [RW 11] The number of free blocks above which the pause signal to class 1
156 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc
157 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c
158 /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
159 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
160 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
161 /* [RW 10] Write client 0: Assert pause threshold. */
162 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
163 /* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC
164 * guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC
165 * mode). 1=per-class guaranty mode (new mode). */
166 #define BRB1_REG_PER_CLASS_GUARANTY_MODE 0x60268
167 /* [R 24] The number of full blocks occpied by port. */
168 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
169 /* [RW 1] Reset the design by software. */
170 #define BRB1_REG_SOFT_RESET 0x600dc
171 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
172 #define CCM_REG_CAM_OCCUP 0xd0188
173 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
174 acknowledge output is deasserted; all other signals are treated as usual;
175 if 1 - normal activity. */
176 #define CCM_REG_CCM_CFC_IFEN 0xd003c
177 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
178 disregarded; valid is deasserted; all other signals are treated as usual;
179 if 1 - normal activity. */
180 #define CCM_REG_CCM_CQM_IFEN 0xd000c
181 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
182 Otherwise 0 is inserted. */
183 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0
184 /* [RW 11] Interrupt mask register #0 read/write */
185 #define CCM_REG_CCM_INT_MASK 0xd01e4
186 /* [R 11] Interrupt register #0 read */
187 #define CCM_REG_CCM_INT_STS 0xd01d8
188 /* [RW 27] Parity mask register #0 read/write */
189 #define CCM_REG_CCM_PRTY_MASK 0xd01f4
190 /* [R 27] Parity register #0 read */
191 #define CCM_REG_CCM_PRTY_STS 0xd01e8
192 /* [RC 27] Parity register #0 read clear */
193 #define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec
194 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
195 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
196 Is used to determine the number of the AG context REG-pairs written back;
197 when the input message Reg1WbFlg isn't set. */
198 #define CCM_REG_CCM_REG0_SZ 0xd00c4
199 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
200 disregarded; valid is deasserted; all other signals are treated as usual;
201 if 1 - normal activity. */
202 #define CCM_REG_CCM_STORM0_IFEN 0xd0004
203 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
204 disregarded; valid is deasserted; all other signals are treated as usual;
205 if 1 - normal activity. */
206 #define CCM_REG_CCM_STORM1_IFEN 0xd0008
207 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
208 disregarded; valid output is deasserted; all other signals are treated as
209 usual; if 1 - normal activity. */
210 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030
211 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
212 are disregarded; all other signals are treated as usual; if 1 - normal
214 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c
215 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
216 disregarded; valid output is deasserted; all other signals are treated as
217 usual; if 1 - normal activity. */
218 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038
219 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
220 input is disregarded; all other signals are treated as usual; if 1 -
222 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034
223 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
224 the initial credit value; read returns the current value of the credit
225 counter. Must be initialized to 1 at start-up. */
226 #define CCM_REG_CFC_INIT_CRD 0xd0204
227 /* [RW 2] Auxiliary counter flag Q number 1. */
228 #define CCM_REG_CNT_AUX1_Q 0xd00c8
229 /* [RW 2] Auxiliary counter flag Q number 2. */
230 #define CCM_REG_CNT_AUX2_Q 0xd00cc
231 /* [RW 28] The CM header value for QM request (primary). */
232 #define CCM_REG_CQM_CCM_HDR_P 0xd008c
233 /* [RW 28] The CM header value for QM request (secondary). */
234 #define CCM_REG_CQM_CCM_HDR_S 0xd0090
235 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
236 acknowledge output is deasserted; all other signals are treated as usual;
237 if 1 - normal activity. */
238 #define CCM_REG_CQM_CCM_IFEN 0xd0014
239 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
240 the initial credit value; read returns the current value of the credit
241 counter. Must be initialized to 32 at start-up. */
242 #define CCM_REG_CQM_INIT_CRD 0xd020c
243 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
244 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
245 prioritised); 2 stands for weight 2; tc. */
246 #define CCM_REG_CQM_P_WEIGHT 0xd00b8
247 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
248 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
249 prioritised); 2 stands for weight 2; tc. */
250 #define CCM_REG_CQM_S_WEIGHT 0xd00bc
251 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
252 acknowledge output is deasserted; all other signals are treated as usual;
253 if 1 - normal activity. */
254 #define CCM_REG_CSDM_IFEN 0xd0018
255 /* [RC 1] Set when the message length mismatch (relative to last indication)
256 at the SDM interface is detected. */
257 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170
258 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
259 weight 8 (the most prioritised); 1 stands for weight 1(least
260 prioritised); 2 stands for weight 2; tc. */
261 #define CCM_REG_CSDM_WEIGHT 0xd00b4
262 /* [RW 28] The CM header for QM formatting in case of an error in the QM
264 #define CCM_REG_ERR_CCM_HDR 0xd0094
265 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
266 #define CCM_REG_ERR_EVNT_ID 0xd0098
267 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
268 writes the initial credit value; read returns the current value of the
269 credit counter. Must be initialized to 64 at start-up. */
270 #define CCM_REG_FIC0_INIT_CRD 0xd0210
271 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
272 writes the initial credit value; read returns the current value of the
273 credit counter. Must be initialized to 64 at start-up. */
274 #define CCM_REG_FIC1_INIT_CRD 0xd0214
275 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
276 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
277 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
278 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
279 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
280 #define CCM_REG_GR_ARB_TYPE 0xd015c
281 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
282 highest priority is 3. It is supposed; that the Store channel priority is
283 the compliment to 4 of the rest priorities - Aggregation channel; Load
284 (FIC0) channel and Load (FIC1). */
285 #define CCM_REG_GR_LD0_PR 0xd0164
286 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
287 highest priority is 3. It is supposed; that the Store channel priority is
288 the compliment to 4 of the rest priorities - Aggregation channel; Load
289 (FIC0) channel and Load (FIC1). */
290 #define CCM_REG_GR_LD1_PR 0xd0168
291 /* [RW 2] General flags index. */
292 #define CCM_REG_INV_DONE_Q 0xd0108
293 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
294 context and sent to STORM; for a specific connection type. The double
295 REG-pairs are used in order to align to STORM context row size of 128
296 bits. The offset of these data in the STORM context is always 0. Index
297 _(0..15) stands for the connection type (one of 16). */
298 #define CCM_REG_N_SM_CTX_LD_0 0xd004c
299 #define CCM_REG_N_SM_CTX_LD_1 0xd0050
300 #define CCM_REG_N_SM_CTX_LD_2 0xd0054
301 #define CCM_REG_N_SM_CTX_LD_3 0xd0058
302 #define CCM_REG_N_SM_CTX_LD_4 0xd005c
303 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
304 acknowledge output is deasserted; all other signals are treated as usual;
305 if 1 - normal activity. */
306 #define CCM_REG_PBF_IFEN 0xd0028
307 /* [RC 1] Set when the message length mismatch (relative to last indication)
308 at the pbf interface is detected. */
309 #define CCM_REG_PBF_LENGTH_MIS 0xd0180
310 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
311 weight 8 (the most prioritised); 1 stands for weight 1(least
312 prioritised); 2 stands for weight 2; tc. */
313 #define CCM_REG_PBF_WEIGHT 0xd00ac
314 #define CCM_REG_PHYS_QNUM1_0 0xd0134
315 #define CCM_REG_PHYS_QNUM1_1 0xd0138
316 #define CCM_REG_PHYS_QNUM2_0 0xd013c
317 #define CCM_REG_PHYS_QNUM2_1 0xd0140
318 #define CCM_REG_PHYS_QNUM3_0 0xd0144
319 #define CCM_REG_PHYS_QNUM3_1 0xd0148
320 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
321 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
322 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
323 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
324 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
325 #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
326 #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
327 #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
328 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
329 disregarded; acknowledge output is deasserted; all other signals are
330 treated as usual; if 1 - normal activity. */
331 #define CCM_REG_STORM_CCM_IFEN 0xd0010
332 /* [RC 1] Set when the message length mismatch (relative to last indication)
333 at the STORM interface is detected. */
334 #define CCM_REG_STORM_LENGTH_MIS 0xd016c
335 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
336 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
337 weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
339 #define CCM_REG_STORM_WEIGHT 0xd009c
340 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
341 disregarded; acknowledge output is deasserted; all other signals are
342 treated as usual; if 1 - normal activity. */
343 #define CCM_REG_TSEM_IFEN 0xd001c
344 /* [RC 1] Set when the message length mismatch (relative to last indication)
345 at the tsem interface is detected. */
346 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174
347 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
348 weight 8 (the most prioritised); 1 stands for weight 1(least
349 prioritised); 2 stands for weight 2; tc. */
350 #define CCM_REG_TSEM_WEIGHT 0xd00a0
351 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
352 disregarded; acknowledge output is deasserted; all other signals are
353 treated as usual; if 1 - normal activity. */
354 #define CCM_REG_USEM_IFEN 0xd0024
355 /* [RC 1] Set when message length mismatch (relative to last indication) at
356 the usem interface is detected. */
357 #define CCM_REG_USEM_LENGTH_MIS 0xd017c
358 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
359 weight 8 (the most prioritised); 1 stands for weight 1(least
360 prioritised); 2 stands for weight 2; tc. */
361 #define CCM_REG_USEM_WEIGHT 0xd00a8
362 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
363 disregarded; acknowledge output is deasserted; all other signals are
364 treated as usual; if 1 - normal activity. */
365 #define CCM_REG_XSEM_IFEN 0xd0020
366 /* [RC 1] Set when the message length mismatch (relative to last indication)
367 at the xsem interface is detected. */
368 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178
369 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
370 weight 8 (the most prioritised); 1 stands for weight 1(least
371 prioritised); 2 stands for weight 2; tc. */
372 #define CCM_REG_XSEM_WEIGHT 0xd00a4
373 /* [RW 19] Indirect access to the descriptor table of the XX protection
374 mechanism. The fields are: [5:0] - message length; [12:6] - message
375 pointer; 18:13] - next pointer. */
376 #define CCM_REG_XX_DESCR_TABLE 0xd0300
377 #define CCM_REG_XX_DESCR_TABLE_SIZE 24
378 /* [R 7] Used to read the value of XX protection Free counter. */
379 #define CCM_REG_XX_FREE 0xd0184
380 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
381 of the Input Stage XX protection buffer by the XX protection pending
382 messages. Max credit available - 127. Write writes the initial credit
383 value; read returns the current value of the credit counter. Must be
384 initialized to maximum XX protected message size - 2 at start-up. */
385 #define CCM_REG_XX_INIT_CRD 0xd0220
386 /* [RW 7] The maximum number of pending messages; which may be stored in XX
387 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
388 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
390 #define CCM_REG_XX_MSG_NUM 0xd0224
391 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
392 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
393 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
394 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
396 #define CCM_REG_XX_TABLE 0xd0280
397 #define CDU_REG_CDU_CHK_MASK0 0x101000
398 #define CDU_REG_CDU_CHK_MASK1 0x101004
399 #define CDU_REG_CDU_CONTROL0 0x101008
400 #define CDU_REG_CDU_DEBUG 0x101010
401 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
402 /* [RW 7] Interrupt mask register #0 read/write */
403 #define CDU_REG_CDU_INT_MASK 0x10103c
404 /* [R 7] Interrupt register #0 read */
405 #define CDU_REG_CDU_INT_STS 0x101030
406 /* [RW 5] Parity mask register #0 read/write */
407 #define CDU_REG_CDU_PRTY_MASK 0x10104c
408 /* [R 5] Parity register #0 read */
409 #define CDU_REG_CDU_PRTY_STS 0x101040
410 /* [RC 5] Parity register #0 read clear */
411 #define CDU_REG_CDU_PRTY_STS_CLR 0x101044
412 /* [RC 32] logging of error data in case of a CDU load error:
413 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
414 ype_error; ctual_active; ctual_compressed_context}; */
415 #define CDU_REG_ERROR_DATA 0x101014
416 /* [WB 216] L1TT ram access. each entry has the following format :
417 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
418 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
419 #define CDU_REG_L1TT 0x101800
420 /* [WB 24] MATT ram access. each entry has the following
421 format:{RegionLength[11:0]; egionOffset[11:0]} */
422 #define CDU_REG_MATT 0x101100
423 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */
424 #define CDU_REG_MF_MODE 0x101050
425 /* [R 1] indication the initializing the activity counter by the hardware
427 #define CFC_REG_AC_INIT_DONE 0x104078
428 /* [RW 13] activity counter ram access */
429 #define CFC_REG_ACTIVITY_COUNTER 0x104400
430 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256
431 /* [R 1] indication the initializing the cams by the hardware was done. */
432 #define CFC_REG_CAM_INIT_DONE 0x10407c
433 /* [RW 2] Interrupt mask register #0 read/write */
434 #define CFC_REG_CFC_INT_MASK 0x104108
435 /* [R 2] Interrupt register #0 read */
436 #define CFC_REG_CFC_INT_STS 0x1040fc
437 /* [RC 2] Interrupt register #0 read clear */
438 #define CFC_REG_CFC_INT_STS_CLR 0x104100
439 /* [RW 4] Parity mask register #0 read/write */
440 #define CFC_REG_CFC_PRTY_MASK 0x104118
441 /* [R 4] Parity register #0 read */
442 #define CFC_REG_CFC_PRTY_STS 0x10410c
443 /* [RC 4] Parity register #0 read clear */
444 #define CFC_REG_CFC_PRTY_STS_CLR 0x104110
445 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
446 #define CFC_REG_CID_CAM 0x104800
447 #define CFC_REG_CONTROL0 0x104028
448 #define CFC_REG_DEBUG0 0x104050
449 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
450 vector) whether the cfc should be disabled upon it */
451 #define CFC_REG_DISABLE_ON_ERROR 0x104044
452 /* [RC 14] CFC error vector. when the CFC detects an internal error it will
453 set one of these bits. the bit description can be found in CFC
455 #define CFC_REG_ERROR_VECTOR 0x10403c
456 /* [WB 93] LCID info ram access */
457 #define CFC_REG_INFO_RAM 0x105000
458 #define CFC_REG_INFO_RAM_SIZE 1024
459 #define CFC_REG_INIT_REG 0x10404c
460 #define CFC_REG_INTERFACES 0x104058
461 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
462 field allows changing the priorities of the weighted-round-robin arbiter
463 which selects which CFC load client should be served next */
464 #define CFC_REG_LCREQ_WEIGHTS 0x104084
465 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
466 #define CFC_REG_LINK_LIST 0x104c00
467 #define CFC_REG_LINK_LIST_SIZE 256
468 /* [R 1] indication the initializing the link list by the hardware was done. */
469 #define CFC_REG_LL_INIT_DONE 0x104074
470 /* [R 9] Number of allocated LCIDs which are at empty state */
471 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020
472 /* [R 9] Number of Arriving LCIDs in Link List Block */
473 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
474 #define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120
475 /* [R 9] Number of Leaving LCIDs in Link List Block */
476 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
477 #define CFC_REG_WEAK_ENABLE_PF 0x104124
478 /* [RW 8] The event id for aggregated interrupt 0 */
479 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
480 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060
481 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064
482 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068
483 #define CSDM_REG_AGG_INT_EVENT_13 0xc206c
484 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070
485 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074
486 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078
487 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040
488 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044
489 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048
490 #define CSDM_REG_AGG_INT_EVENT_5 0xc204c
491 #define CSDM_REG_AGG_INT_EVENT_6 0xc2050
492 #define CSDM_REG_AGG_INT_EVENT_7 0xc2054
493 #define CSDM_REG_AGG_INT_EVENT_8 0xc2058
494 #define CSDM_REG_AGG_INT_EVENT_9 0xc205c
495 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
496 or auto-mask-mode (1) */
497 #define CSDM_REG_AGG_INT_MODE_10 0xc21e0
498 #define CSDM_REG_AGG_INT_MODE_11 0xc21e4
499 #define CSDM_REG_AGG_INT_MODE_12 0xc21e8
500 #define CSDM_REG_AGG_INT_MODE_13 0xc21ec
501 #define CSDM_REG_AGG_INT_MODE_14 0xc21f0
502 #define CSDM_REG_AGG_INT_MODE_15 0xc21f4
503 #define CSDM_REG_AGG_INT_MODE_16 0xc21f8
504 #define CSDM_REG_AGG_INT_MODE_6 0xc21d0
505 #define CSDM_REG_AGG_INT_MODE_7 0xc21d4
506 #define CSDM_REG_AGG_INT_MODE_8 0xc21d8
507 #define CSDM_REG_AGG_INT_MODE_9 0xc21dc
508 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
509 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
510 /* [RW 16] The maximum value of the completion counter #0 */
511 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
512 /* [RW 16] The maximum value of the completion counter #1 */
513 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
514 /* [RW 16] The maximum value of the completion counter #2 */
515 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
516 /* [RW 16] The maximum value of the completion counter #3 */
517 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
518 /* [RW 13] The start address in the internal RAM for the completion
520 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
521 /* [RW 32] Interrupt mask register #0 read/write */
522 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c
523 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
524 /* [R 32] Interrupt register #0 read */
525 #define CSDM_REG_CSDM_INT_STS_0 0xc2290
526 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0
527 /* [RW 11] Parity mask register #0 read/write */
528 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
529 /* [R 11] Parity register #0 read */
530 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0
531 /* [RC 11] Parity register #0 read clear */
532 #define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4
533 #define CSDM_REG_ENABLE_IN1 0xc2238
534 #define CSDM_REG_ENABLE_IN2 0xc223c
535 #define CSDM_REG_ENABLE_OUT1 0xc2240
536 #define CSDM_REG_ENABLE_OUT2 0xc2244
537 /* [RW 4] The initial number of messages that can be sent to the pxp control
538 interface without receiving any ACK. */
539 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
540 /* [ST 32] The number of ACK after placement messages received */
541 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
542 /* [ST 32] The number of packet end messages received from the parser */
543 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
544 /* [ST 32] The number of requests received from the pxp async if */
545 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
546 /* [ST 32] The number of commands received in queue 0 */
547 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
548 /* [ST 32] The number of commands received in queue 10 */
549 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
550 /* [ST 32] The number of commands received in queue 11 */
551 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
552 /* [ST 32] The number of commands received in queue 1 */
553 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
554 /* [ST 32] The number of commands received in queue 3 */
555 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
556 /* [ST 32] The number of commands received in queue 4 */
557 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
558 /* [ST 32] The number of commands received in queue 5 */
559 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
560 /* [ST 32] The number of commands received in queue 6 */
561 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
562 /* [ST 32] The number of commands received in queue 7 */
563 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
564 /* [ST 32] The number of commands received in queue 8 */
565 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
566 /* [ST 32] The number of commands received in queue 9 */
567 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
568 /* [RW 13] The start address in the internal RAM for queue counters */
569 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
570 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
571 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
572 /* [R 1] parser fifo empty in sdm_sync block */
573 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
574 /* [R 1] parser serial fifo empty in sdm_sync block */
575 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
576 /* [RW 32] Tick for timer counter. Applicable only when
577 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
578 #define CSDM_REG_TIMER_TICK 0xc2000
579 /* [RW 5] The number of time_slots in the arbitration cycle */
580 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034
581 /* [RW 3] The source that is associated with arbitration element 0. Source
582 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
583 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
584 #define CSEM_REG_ARB_ELEMENT0 0x200020
585 /* [RW 3] The source that is associated with arbitration element 1. Source
586 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
587 sleeping thread with priority 1; 4- sleeping thread with priority 2.
588 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
589 #define CSEM_REG_ARB_ELEMENT1 0x200024
590 /* [RW 3] The source that is associated with arbitration element 2. Source
591 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
592 sleeping thread with priority 1; 4- sleeping thread with priority 2.
593 Could not be equal to register ~csem_registers_arb_element0.arb_element0
594 and ~csem_registers_arb_element1.arb_element1 */
595 #define CSEM_REG_ARB_ELEMENT2 0x200028
596 /* [RW 3] The source that is associated with arbitration element 3. Source
597 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
598 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
599 not be equal to register ~csem_registers_arb_element0.arb_element0 and
600 ~csem_registers_arb_element1.arb_element1 and
601 ~csem_registers_arb_element2.arb_element2 */
602 #define CSEM_REG_ARB_ELEMENT3 0x20002c
603 /* [RW 3] The source that is associated with arbitration element 4. Source
604 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
605 sleeping thread with priority 1; 4- sleeping thread with priority 2.
606 Could not be equal to register ~csem_registers_arb_element0.arb_element0
607 and ~csem_registers_arb_element1.arb_element1 and
608 ~csem_registers_arb_element2.arb_element2 and
609 ~csem_registers_arb_element3.arb_element3 */
610 #define CSEM_REG_ARB_ELEMENT4 0x200030
611 /* [RW 32] Interrupt mask register #0 read/write */
612 #define CSEM_REG_CSEM_INT_MASK_0 0x200110
613 #define CSEM_REG_CSEM_INT_MASK_1 0x200120
614 /* [R 32] Interrupt register #0 read */
615 #define CSEM_REG_CSEM_INT_STS_0 0x200104
616 #define CSEM_REG_CSEM_INT_STS_1 0x200114
617 /* [RW 32] Parity mask register #0 read/write */
618 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
619 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
620 /* [R 32] Parity register #0 read */
621 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124
622 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134
623 /* [RC 32] Parity register #0 read clear */
624 #define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128
625 #define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138
626 #define CSEM_REG_ENABLE_IN 0x2000a4
627 #define CSEM_REG_ENABLE_OUT 0x2000a8
628 /* [RW 32] This address space contains all registers and memories that are
629 placed in SEM_FAST block. The SEM_FAST registers are described in
630 appendix B. In order to access the sem_fast registers the base address
631 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
632 #define CSEM_REG_FAST_MEMORY 0x220000
633 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
635 #define CSEM_REG_FIC0_DISABLE 0x200224
636 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
638 #define CSEM_REG_FIC1_DISABLE 0x200234
639 /* [RW 15] Interrupt table Read and write access to it is not possible in
640 the middle of the work */
641 #define CSEM_REG_INT_TABLE 0x200400
642 /* [ST 24] Statistics register. The number of messages that entered through
644 #define CSEM_REG_MSG_NUM_FIC0 0x200000
645 /* [ST 24] Statistics register. The number of messages that entered through
647 #define CSEM_REG_MSG_NUM_FIC1 0x200004
648 /* [ST 24] Statistics register. The number of messages that were sent to
650 #define CSEM_REG_MSG_NUM_FOC0 0x200008
651 /* [ST 24] Statistics register. The number of messages that were sent to
653 #define CSEM_REG_MSG_NUM_FOC1 0x20000c
654 /* [ST 24] Statistics register. The number of messages that were sent to
656 #define CSEM_REG_MSG_NUM_FOC2 0x200010
657 /* [ST 24] Statistics register. The number of messages that were sent to
659 #define CSEM_REG_MSG_NUM_FOC3 0x200014
660 /* [RW 1] Disables input messages from the passive buffer May be updated
661 during run_time by the microcode */
662 #define CSEM_REG_PAS_DISABLE 0x20024c
663 /* [WB 128] Debug only. Passive buffer memory */
664 #define CSEM_REG_PASSIVE_BUFFER 0x202000
665 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
666 #define CSEM_REG_PRAM 0x240000
667 /* [R 16] Valid sleeping threads indication have bit per thread */
668 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
669 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
670 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
671 /* [RW 16] List of free threads . There is a bit per thread. */
672 #define CSEM_REG_THREADS_LIST 0x2002e4
673 /* [RW 3] The arbitration scheme of time_slot 0 */
674 #define CSEM_REG_TS_0_AS 0x200038
675 /* [RW 3] The arbitration scheme of time_slot 10 */
676 #define CSEM_REG_TS_10_AS 0x200060
677 /* [RW 3] The arbitration scheme of time_slot 11 */
678 #define CSEM_REG_TS_11_AS 0x200064
679 /* [RW 3] The arbitration scheme of time_slot 12 */
680 #define CSEM_REG_TS_12_AS 0x200068
681 /* [RW 3] The arbitration scheme of time_slot 13 */
682 #define CSEM_REG_TS_13_AS 0x20006c
683 /* [RW 3] The arbitration scheme of time_slot 14 */
684 #define CSEM_REG_TS_14_AS 0x200070
685 /* [RW 3] The arbitration scheme of time_slot 15 */
686 #define CSEM_REG_TS_15_AS 0x200074
687 /* [RW 3] The arbitration scheme of time_slot 16 */
688 #define CSEM_REG_TS_16_AS 0x200078
689 /* [RW 3] The arbitration scheme of time_slot 17 */
690 #define CSEM_REG_TS_17_AS 0x20007c
691 /* [RW 3] The arbitration scheme of time_slot 18 */
692 #define CSEM_REG_TS_18_AS 0x200080
693 /* [RW 3] The arbitration scheme of time_slot 1 */
694 #define CSEM_REG_TS_1_AS 0x20003c
695 /* [RW 3] The arbitration scheme of time_slot 2 */
696 #define CSEM_REG_TS_2_AS 0x200040
697 /* [RW 3] The arbitration scheme of time_slot 3 */
698 #define CSEM_REG_TS_3_AS 0x200044
699 /* [RW 3] The arbitration scheme of time_slot 4 */
700 #define CSEM_REG_TS_4_AS 0x200048
701 /* [RW 3] The arbitration scheme of time_slot 5 */
702 #define CSEM_REG_TS_5_AS 0x20004c
703 /* [RW 3] The arbitration scheme of time_slot 6 */
704 #define CSEM_REG_TS_6_AS 0x200050
705 /* [RW 3] The arbitration scheme of time_slot 7 */
706 #define CSEM_REG_TS_7_AS 0x200054
707 /* [RW 3] The arbitration scheme of time_slot 8 */
708 #define CSEM_REG_TS_8_AS 0x200058
709 /* [RW 3] The arbitration scheme of time_slot 9 */
710 #define CSEM_REG_TS_9_AS 0x20005c
711 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
712 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
713 #define CSEM_REG_VFPF_ERR_NUM 0x200380
714 /* [RW 1] Parity mask register #0 read/write */
715 #define DBG_REG_DBG_PRTY_MASK 0xc0a8
716 /* [R 1] Parity register #0 read */
717 #define DBG_REG_DBG_PRTY_STS 0xc09c
718 /* [RC 1] Parity register #0 read clear */
719 #define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0
720 /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
721 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
722 * 4.Completion function=0; 5.Error handling=0 */
723 #define DMAE_REG_BACKWARD_COMP_EN 0x10207c
724 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
726 #define DMAE_REG_CMD_MEM 0x102400
727 #define DMAE_REG_CMD_MEM_SIZE 224
728 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
729 initial value is all ones. */
730 #define DMAE_REG_CRC16C_INIT 0x10201c
731 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
732 CRC-16 T10 initial value is all ones. */
733 #define DMAE_REG_CRC16T10_INIT 0x102020
734 /* [RW 2] Interrupt mask register #0 read/write */
735 #define DMAE_REG_DMAE_INT_MASK 0x102054
736 /* [RW 4] Parity mask register #0 read/write */
737 #define DMAE_REG_DMAE_PRTY_MASK 0x102064
738 /* [R 4] Parity register #0 read */
739 #define DMAE_REG_DMAE_PRTY_STS 0x102058
740 /* [RC 4] Parity register #0 read clear */
741 #define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c
742 /* [RW 1] Command 0 go. */
743 #define DMAE_REG_GO_C0 0x102080
744 /* [RW 1] Command 1 go. */
745 #define DMAE_REG_GO_C1 0x102084
746 /* [RW 1] Command 10 go. */
747 #define DMAE_REG_GO_C10 0x102088
748 /* [RW 1] Command 11 go. */
749 #define DMAE_REG_GO_C11 0x10208c
750 /* [RW 1] Command 12 go. */
751 #define DMAE_REG_GO_C12 0x102090
752 /* [RW 1] Command 13 go. */
753 #define DMAE_REG_GO_C13 0x102094
754 /* [RW 1] Command 14 go. */
755 #define DMAE_REG_GO_C14 0x102098
756 /* [RW 1] Command 15 go. */
757 #define DMAE_REG_GO_C15 0x10209c
758 /* [RW 1] Command 2 go. */
759 #define DMAE_REG_GO_C2 0x1020a0
760 /* [RW 1] Command 3 go. */
761 #define DMAE_REG_GO_C3 0x1020a4
762 /* [RW 1] Command 4 go. */
763 #define DMAE_REG_GO_C4 0x1020a8
764 /* [RW 1] Command 5 go. */
765 #define DMAE_REG_GO_C5 0x1020ac
766 /* [RW 1] Command 6 go. */
767 #define DMAE_REG_GO_C6 0x1020b0
768 /* [RW 1] Command 7 go. */
769 #define DMAE_REG_GO_C7 0x1020b4
770 /* [RW 1] Command 8 go. */
771 #define DMAE_REG_GO_C8 0x1020b8
772 /* [RW 1] Command 9 go. */
773 #define DMAE_REG_GO_C9 0x1020bc
774 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
775 input is disregarded; valid is deasserted; all other signals are treated
776 as usual; if 1 - normal activity. */
777 #define DMAE_REG_GRC_IFEN 0x102008
778 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
779 acknowledge input is disregarded; valid is deasserted; full is asserted;
780 all other signals are treated as usual; if 1 - normal activity. */
781 #define DMAE_REG_PCI_IFEN 0x102004
782 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
783 initial value to the credit counter; related to the address. Read returns
784 the current value of the counter. */
785 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
786 /* [RW 8] Aggregation command. */
787 #define DORQ_REG_AGG_CMD0 0x170060
788 /* [RW 8] Aggregation command. */
789 #define DORQ_REG_AGG_CMD1 0x170064
790 /* [RW 8] Aggregation command. */
791 #define DORQ_REG_AGG_CMD2 0x170068
792 /* [RW 8] Aggregation command. */
793 #define DORQ_REG_AGG_CMD3 0x17006c
794 /* [RW 28] UCM Header. */
795 #define DORQ_REG_CMHEAD_RX 0x170050
796 /* [RW 32] Doorbell address for RBC doorbells (function 0). */
797 #define DORQ_REG_DB_ADDR0 0x17008c
798 /* [RW 5] Interrupt mask register #0 read/write */
799 #define DORQ_REG_DORQ_INT_MASK 0x170180
800 /* [R 5] Interrupt register #0 read */
801 #define DORQ_REG_DORQ_INT_STS 0x170174
802 /* [RC 5] Interrupt register #0 read clear */
803 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178
804 /* [RW 2] Parity mask register #0 read/write */
805 #define DORQ_REG_DORQ_PRTY_MASK 0x170190
806 /* [R 2] Parity register #0 read */
807 #define DORQ_REG_DORQ_PRTY_STS 0x170184
808 /* [RC 2] Parity register #0 read clear */
809 #define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188
810 /* [RW 8] The address to write the DPM CID to STORM. */
811 #define DORQ_REG_DPM_CID_ADDR 0x170044
812 /* [RW 5] The DPM mode CID extraction offset. */
813 #define DORQ_REG_DPM_CID_OFST 0x170030
814 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
815 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
816 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
817 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
818 /* [R 13] Current value of the DQ FIFO fill level according to following
819 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
821 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4
822 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
823 equal to full threshold; reset on full clear. */
824 #define DORQ_REG_DQ_FULL_ST 0x1700c0
825 /* [RW 28] The value sent to CM header in the case of CFC load error. */
826 #define DORQ_REG_ERR_CMHEAD 0x170058
827 #define DORQ_REG_IF_EN 0x170004
828 #define DORQ_REG_MAX_RVFID_SIZE 0x1701ec
829 #define DORQ_REG_MODE_ACT 0x170008
830 /* [RW 5] The normal mode CID extraction offset. */
831 #define DORQ_REG_NORM_CID_OFST 0x17002c
832 /* [RW 28] TCM Header when only TCP context is loaded. */
833 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c
834 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
836 #define DORQ_REG_OUTST_REQ 0x17003c
837 #define DORQ_REG_PF_USAGE_CNT 0x1701d0
838 #define DORQ_REG_REGN 0x170038
839 /* [R 4] Current value of response A counter credit. Initial credit is
840 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
842 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac
843 /* [R 4] Current value of response B counter credit. Initial credit is
844 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
846 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
847 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
848 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
849 read reads this written value. */
850 #define DORQ_REG_RSP_INIT_CRD 0x170048
851 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
852 #define DORQ_REG_VF_NORM_CID_BASE 0x1701a0
853 #define DORQ_REG_VF_NORM_CID_OFST 0x1701f4
854 #define DORQ_REG_VF_NORM_CID_WND_SIZE 0x1701a4
855 #define DORQ_REG_VF_NORM_MAX_CID_COUNT 0x1701e4
856 #define DORQ_REG_VF_NORM_VF_BASE 0x1701a8
857 /* [RW 10] VF type validation mask value */
858 #define DORQ_REG_VF_TYPE_MASK_0 0x170218
859 /* [RW 17] VF type validation Min MCID value */
860 #define DORQ_REG_VF_TYPE_MAX_MCID_0 0x1702d8
861 /* [RW 17] VF type validation Max MCID value */
862 #define DORQ_REG_VF_TYPE_MIN_MCID_0 0x170298
863 /* [RW 10] VF type validation comp value */
864 #define DORQ_REG_VF_TYPE_VALUE_0 0x170258
865 #define DORQ_REG_VF_USAGE_CT_LIMIT 0x170340
867 /* [RW 4] Initial activity counter value on the load request; when the
869 #define DORQ_REG_SHRT_ACT_CNT 0x170070
870 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
871 #define DORQ_REG_SHRT_CMHEAD 0x170054
872 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
873 #define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
874 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
875 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
876 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
877 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
878 #define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)
879 #define DORQ_REG_VF_USAGE_CNT 0x170320
880 #define HC_REG_AGG_INT_0 0x108050
881 #define HC_REG_AGG_INT_1 0x108054
882 #define HC_REG_ATTN_BIT 0x108120
883 #define HC_REG_ATTN_IDX 0x108100
884 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018
885 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020
886 #define HC_REG_ATTN_NUM_P0 0x108038
887 #define HC_REG_ATTN_NUM_P1 0x10803c
888 #define HC_REG_COMMAND_REG 0x108180
889 #define HC_REG_CONFIG_0 0x108000
890 #define HC_REG_CONFIG_1 0x108004
891 #define HC_REG_FUNC_NUM_P0 0x1080ac
892 #define HC_REG_FUNC_NUM_P1 0x1080b0
893 /* [RW 3] Parity mask register #0 read/write */
894 #define HC_REG_HC_PRTY_MASK 0x1080a0
895 /* [R 3] Parity register #0 read */
896 #define HC_REG_HC_PRTY_STS 0x108094
897 /* [RC 3] Parity register #0 read clear */
898 #define HC_REG_HC_PRTY_STS_CLR 0x108098
899 #define HC_REG_INT_MASK 0x108108
900 #define HC_REG_LEADING_EDGE_0 0x108040
901 #define HC_REG_LEADING_EDGE_1 0x108048
902 #define HC_REG_MAIN_MEMORY 0x108800
903 #define HC_REG_MAIN_MEMORY_SIZE 152
904 #define HC_REG_P0_PROD_CONS 0x108200
905 #define HC_REG_P1_PROD_CONS 0x108400
906 #define HC_REG_PBA_COMMAND 0x108140
907 #define HC_REG_PCI_CONFIG_0 0x108010
908 #define HC_REG_PCI_CONFIG_1 0x108014
909 #define HC_REG_STATISTIC_COUNTERS 0x109000
910 #define HC_REG_TRAILING_EDGE_0 0x108044
911 #define HC_REG_TRAILING_EDGE_1 0x10804c
912 #define HC_REG_UC_RAM_ADDR_0 0x108028
913 #define HC_REG_UC_RAM_ADDR_1 0x108030
914 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
915 #define HC_REG_VQID_0 0x108008
916 #define HC_REG_VQID_1 0x10800c
917 #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
918 #define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)
919 #define IGU_REG_ATTENTION_ACK_BITS 0x130108
920 /* [R 4] Debug: attn_fsm */
921 #define IGU_REG_ATTN_FSM 0x130054
922 #define IGU_REG_ATTN_MSG_ADDR_H 0x13011c
923 #define IGU_REG_ATTN_MSG_ADDR_L 0x130120
924 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
925 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
926 * write done didn't receive. */
927 #define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030
928 #define IGU_REG_BLOCK_CONFIGURATION 0x130000
929 #define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124
930 #define IGU_REG_COMMAND_REG_CTRL 0x13012c
931 /* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
932 * is clear. The bits in this registers are set and clear via the producer
933 * command. Data valid only in addresses 0-4. all the rest are zero. */
934 #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200
935 /* [R 5] Debug: ctrl_fsm */
936 #define IGU_REG_CTRL_FSM 0x130064
937 /* [R 1] data available for error memory. If this bit is clear do not red
938 * from error_handling_memory. */
939 #define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
940 /* [RW 11] Parity mask register #0 read/write */
941 #define IGU_REG_IGU_PRTY_MASK 0x1300a8
942 /* [R 11] Parity register #0 read */
943 #define IGU_REG_IGU_PRTY_STS 0x13009c
944 /* [RC 11] Parity register #0 read clear */
945 #define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0
946 /* [R 4] Debug: int_handle_fsm */
947 #define IGU_REG_INT_HANDLE_FSM 0x130050
948 #define IGU_REG_LEADING_EDGE_LATCH 0x130134
949 /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
950 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
951 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
952 #define IGU_REG_MAPPING_MEMORY 0x131000
953 #define IGU_REG_MAPPING_MEMORY_SIZE 136
954 #define IGU_REG_PBA_STATUS_LSB 0x130138
955 #define IGU_REG_PBA_STATUS_MSB 0x13013c
956 #define IGU_REG_PCI_PF_MSI_EN 0x130140
957 #define IGU_REG_PCI_PF_MSIX_EN 0x130144
958 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148
959 /* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
960 * pending; 1 = pending. Pendings means interrupt was asserted; and write
961 * done was not received. Data valid only in addresses 0-4. all the rest are
963 #define IGU_REG_PENDING_BITS_STATUS 0x130300
964 #define IGU_REG_PF_CONFIGURATION 0x130154
965 /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
966 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
967 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
968 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
969 * - In backward compatible mode; for non default SB; each even line in the
970 * memory holds the U producer and each odd line hold the C producer. The
971 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
972 * last 20 producers are for the DSB for each PF. each PF has five segments
973 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
974 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
975 #define IGU_REG_PROD_CONS_MEMORY 0x132000
976 /* [R 3] Debug: pxp_arb_fsm */
977 #define IGU_REG_PXP_ARB_FSM 0x130068
978 /* [RW 6] Write one for each bit will reset the appropriate memory. When the
979 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
980 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
981 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
982 #define IGU_REG_RESET_MEMORIES 0x130158
983 /* [R 4] Debug: sb_ctrl_fsm */
984 #define IGU_REG_SB_CTRL_FSM 0x13004c
985 #define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c
986 #define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160
987 #define IGU_REG_SB_MASK_LSB 0x130164
988 #define IGU_REG_SB_MASK_MSB 0x130168
989 /* [RW 16] Number of command that were dropped without causing an interrupt
990 * due to: read access for WO BAR address; or write access for RO BAR
991 * address or any access for reserved address or PCI function error is set
992 * and address is not MSIX; PBA or cleanup */
993 #define IGU_REG_SILENT_DROP 0x13016c
994 /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
995 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
996 * PF; 68-71 number of ATTN messages per PF */
997 #define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800
998 /* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a
999 * timer mask command arrives. Value must be bigger than 100. */
1000 #define IGU_REG_TIMER_MASKING_VALUE 0x13003c
1001 #define IGU_REG_TRAILING_EDGE_LATCH 0x130104
1002 #define IGU_REG_VF_CONFIGURATION 0x130170
1003 /* [WB_R 32] Each bit represent write done pending bits status for that SB
1004 * (MSI/MSIX message was sent and write done was not received yet). 0 =
1005 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
1006 #define IGU_REG_WRITE_DONE_PENDING 0x130480
1007 #define MCP_A_REG_MCPR_SCRATCH 0x3a0000
1008 #define MCP_REG_MCPR_ACCESS_LOCK 0x8009c
1009 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
1010 #define MCP_REG_MCPR_GP_INPUTS 0x800c0
1011 #define MCP_REG_MCPR_GP_OENABLE 0x800c8
1012 #define MCP_REG_MCPR_GP_OUTPUTS 0x800c4
1013 #define MCP_REG_MCPR_IMC_COMMAND 0x85900
1014 #define MCP_REG_MCPR_IMC_DATAREG0 0x85920
1015 #define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904
1016 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
1017 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
1018 #define MCP_REG_MCPR_NVM_ADDR 0x8640c
1019 #define MCP_REG_MCPR_NVM_CFG4 0x8642c
1020 #define MCP_REG_MCPR_NVM_COMMAND 0x86400
1021 #define MCP_REG_MCPR_NVM_READ 0x86410
1022 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420
1023 #define MCP_REG_MCPR_NVM_WRITE 0x86408
1024 #define MCP_REG_MCPR_SCRATCH 0xa0000
1025 #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
1026 #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
1027 /* [R 32] read first 32 bit after inversion of function 0. mapped as
1028 follows: [0] NIG attention for function0; [1] NIG attention for
1029 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
1030 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
1031 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
1032 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
1033 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
1034 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
1035 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
1036 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
1037 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
1038 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
1039 Parity error; [31] PBF Hw interrupt; */
1040 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
1041 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
1042 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
1043 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1044 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1045 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1046 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1047 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1048 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1049 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1050 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1051 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1052 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1053 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1055 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
1056 /* [R 32] read second 32 bit after inversion of function 0. mapped as
1057 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1058 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1059 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1060 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1061 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1062 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1063 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1064 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1065 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1066 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1067 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1069 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
1070 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
1071 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
1072 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
1073 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
1074 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
1075 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1076 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1077 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1078 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1079 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1080 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1081 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1082 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1083 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
1084 /* [R 32] read third 32 bit after inversion of function 0. mapped as
1085 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
1086 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
1087 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1088 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1089 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1090 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1091 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1092 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1093 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1094 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1095 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1097 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
1098 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
1099 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
1100 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
1101 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
1102 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
1103 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
1104 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
1105 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
1106 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
1107 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
1108 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
1109 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
1110 timers attn_4 func1; [30] General attn0; [31] General attn1; */
1111 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
1112 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
1113 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1114 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1115 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1116 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1117 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1118 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1119 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1120 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1121 Latched timeout attention; [27] GRC Latched reserved access attention;
1122 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1123 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1124 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
1125 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
1126 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
1127 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
1128 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
1129 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
1130 General attn13; [12] General attn14; [13] General attn15; [14] General
1131 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
1132 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
1133 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
1134 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
1135 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
1136 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
1137 ump_tx_parity; [31] MCP Latched scpad_parity; */
1138 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
1139 /* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
1140 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1141 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1142 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
1143 #define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700
1144 /* [W 14] write to this register results with the clear of the latched
1145 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
1146 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
1147 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
1148 GRC Latched reserved access attention; one in d7 clears Latched
1149 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
1150 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
1151 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
1152 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
1153 from this register return zero */
1154 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
1155 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
1156 as follows: [0] NIG attention for function0; [1] NIG attention for
1157 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1158 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1159 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1160 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1161 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1162 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1163 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1164 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1165 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1166 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1167 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1168 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
1169 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
1170 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
1171 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
1172 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
1173 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
1174 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
1175 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
1176 as follows: [0] NIG attention for function0; [1] NIG attention for
1177 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
1178 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1179 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1180 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1181 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1182 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
1183 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1184 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1185 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1186 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1187 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1188 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
1189 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
1190 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
1191 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
1192 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
1193 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
1194 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
1195 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped
1196 as follows: [0] NIG attention for function0; [1] NIG attention for
1197 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1198 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1199 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1200 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1201 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1202 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1203 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1204 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1205 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1206 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1207 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1208 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
1209 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
1210 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
1211 as follows: [0] NIG attention for function0; [1] NIG attention for
1212 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1213 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1214 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1215 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1216 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1217 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1218 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1219 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1220 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1221 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1222 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1223 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
1224 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
1225 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
1226 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1227 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1228 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1229 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1230 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1231 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1232 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1233 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1234 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1235 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1236 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1238 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
1239 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1240 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1241 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1242 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1243 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1244 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1245 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1246 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1247 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1248 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1249 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1250 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1251 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1253 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1254 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
1255 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1256 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1257 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1258 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1259 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1260 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1261 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1262 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1263 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1264 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1265 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1266 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1268 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1269 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1270 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1271 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1272 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1273 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1274 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1275 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1276 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1277 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1278 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1279 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1280 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1281 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1283 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1284 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1285 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1286 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1287 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1288 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1289 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1290 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1291 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1292 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1293 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1294 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1295 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1296 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1298 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1299 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1300 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1301 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1302 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1303 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1304 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1305 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1306 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1307 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1308 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1309 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1310 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1311 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1313 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1314 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1315 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1316 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1317 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1318 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1319 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1320 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1321 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1322 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1323 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1324 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1325 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1326 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1328 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1329 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1330 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1331 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1332 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1333 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1334 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1335 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1336 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1337 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1338 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1339 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1340 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1341 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1343 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1344 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1345 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1346 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1347 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1348 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1349 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1350 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1351 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1352 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1353 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1354 Latched timeout attention; [27] GRC Latched reserved access attention;
1355 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1356 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1357 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1358 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1359 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1360 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1361 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1362 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
1363 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1364 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1365 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1366 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1367 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1368 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1369 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1370 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1371 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1372 Latched timeout attention; [27] GRC Latched reserved access attention;
1373 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1374 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1375 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1376 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1377 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1378 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1379 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1380 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1381 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1382 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1383 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1384 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1385 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1386 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1387 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1388 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1389 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1390 Latched timeout attention; [27] GRC Latched reserved access attention;
1391 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1392 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1393 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1394 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1395 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1396 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1397 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1398 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1399 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1400 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1401 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1402 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1403 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1404 Latched timeout attention; [27] GRC Latched reserved access attention;
1405 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1406 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1407 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1408 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1409 /* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped
1410 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1411 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1412 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
1413 * parity; [31-10] Reserved; */
1414 #define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688
1415 /* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped
1416 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1417 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1418 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
1419 * parity; [31-10] Reserved; */
1420 #define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0
1421 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1423 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1424 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1425 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1426 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1427 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1428 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1429 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1430 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1431 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1432 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1433 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1434 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1435 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1436 #define MISC_REG_AEU_GENERAL_MASK 0xa61c
1437 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1438 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1439 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1440 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1441 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1442 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1443 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1444 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1445 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1446 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1447 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1448 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1449 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1450 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1451 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1452 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1453 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1454 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1455 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1456 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1457 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1458 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1459 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1460 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1461 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1462 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1463 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1464 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1465 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1466 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1467 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1468 [9:8] = raserved. Zero = mask; one = unmask */
1469 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1470 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1471 /* [RW 1] If set a system kill occurred */
1472 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1473 /* [RW 32] Represent the status of the input vector to the AEU when a system
1474 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1475 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1476 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1477 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1478 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1479 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1480 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1481 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1482 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1483 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1484 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1485 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1487 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1488 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1489 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1490 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
1491 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1493 #define MISC_REG_BOND_ID 0xa400
1494 /* [R 16] These bits indicate the part number for the chip. */
1495 #define MISC_REG_CHIP_NUM 0xa408
1496 /* [R 4] These bits indicate the base revision of the chip. This value
1497 starts at 0x0 for the A0 tape-out and increments by one for each
1498 all-layer tape-out. */
1499 #define MISC_REG_CHIP_REV 0xa40c
1500 /* [R 14] otp_misc_do[100:0] spare bits collection: 13:11-
1501 * otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72];
1502 * 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1]. */
1503 #define MISC_REG_CHIP_TYPE 0xac60
1504 #define MISC_REG_CHIP_TYPE_57811_MASK (1<<1)
1505 #define MISC_REG_CPMU_LP_DR_ENABLE 0xa858
1506 /* [RW 1] FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled
1507 * by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk
1508 * 25MHz. Reset on hard reset. */
1509 #define MISC_REG_CPMU_LP_FW_ENABLE_P0 0xa84c
1510 /* [RW 32] EEE LPI Idle Threshold. The threshold value for the idle EEE LPI
1511 * counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset. */
1512 #define MISC_REG_CPMU_LP_IDLE_THR_P0 0xa8a0
1513 /* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that
1514 * the Vmain SM end state is disabled. When 0 indicates that the Vmain SM
1515 * end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that
1516 * the FW command that all Queues are empty is disabled. When 0 indicates
1517 * that the FW command that all Queues are empty is enabled. [2] - FW Early
1518 * Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early
1519 * Exit command is disabled. When 0 indicates that the FW Early Exit command
1520 * is enabled. This bit applicable only in the EXIT Events Mask registers.
1521 * [3] - PBF Request Mask. When 1 indicates that the PBF Request indication
1522 * is disabled. When 0 indicates that the PBF Request indication is enabled.
1523 * [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF
1524 * Request indication is disabled. When 0 indicates that the Tx Other Than
1525 * PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1
1526 * indicates that the RX EEE LPI Status indication is disabled. When 0
1527 * indicates that the RX EEE LPI Status indication is enabled. In the EXIT
1528 * Events Masks registers; this bit masks the falling edge detect of the LPI
1529 * Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that
1530 * the Tx Pause indication is disabled. When 0 indicates that the Tx Pause
1531 * indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the
1532 * BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY
1533 * indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM
1534 * IDLE indication is disabled. When 0 indicates that the QM IDLE indication
1535 * is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When
1536 * 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0
1537 * indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1
1538 * Status Mask. When 1 indicates that the L1 Status indication from the PCIE
1539 * CORE is disabled. When 0 indicates that the RX EEE LPI Status indication
1540 * from the PCIE CORE is enabled. In the EXIT Events Masks registers; this
1541 * bit masks the falling edge detect of the L1 status (L1 is on - off). [11]
1542 * - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE
1543 * LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI
1544 * REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1
1545 * indicates that the P0 EEE LPI REQ indication is disabled. When =0
1546 * indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE
1547 * LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is
1548 * disabled. When =0 indicates that the P0 EEE LPI REQ indication is
1549 * enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
1550 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
1551 * indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1
1552 * REQ indication is disabled. When =0 indicates that the L1 indication is
1553 * enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates
1554 * that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx
1555 * EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status
1556 * Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This
1557 * bit is applicable only in the EXIT Events Masks registers. [17] - L1
1558 * Status Edge Detect Mask. When =1 indicates that the L1 Status Falling
1559 * Edge Detect indication from the PCIE CORE is disabled (L1 is on - off).
1560 * When =0 indicates that the L1 Status Falling Edge Detect indication from
1561 * the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in
1562 * the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset. */
1563 #define MISC_REG_CPMU_LP_MASK_ENT_P0 0xa880
1564 /* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates
1565 * that the Vmain SM end state is disabled. When 0 indicates that the Vmain
1566 * SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates
1567 * that the FW command that all Queues are empty is disabled. When 0
1568 * indicates that the FW command that all Queues are empty is enabled. [2] -
1569 * FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW
1570 * Early Exit command is disabled. When 0 indicates that the FW Early Exit
1571 * command is enabled. This bit applicable only in the EXIT Events Mask
1572 * registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request
1573 * indication is disabled. When 0 indicates that the PBF Request indication
1574 * is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other
1575 * Than PBF Request indication is disabled. When 0 indicates that the Tx
1576 * Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status
1577 * Mask. When 1 indicates that the RX EEE LPI Status indication is disabled.
1578 * When 0 indicates that the RX LPI Status indication is enabled. In the
1579 * EXIT Events Masks registers; this bit masks the falling edge detect of
1580 * the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1
1581 * indicates that the Tx Pause indication is disabled. When 0 indicates that
1582 * the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1
1583 * indicates that the BRB1 EMPTY indication is disabled. When 0 indicates
1584 * that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1
1585 * indicates that the QM IDLE indication is disabled. When 0 indicates that
1586 * the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9]
1587 * - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for
1588 * LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for
1589 * LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1
1590 * Status indication from the PCIE CORE is disabled. When 0 indicates that
1591 * the RX EEE LPI Status indication from the PCIE CORE is enabled. In the
1592 * EXIT Events Masks registers; this bit masks the falling edge detect of
1593 * the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When
1594 * =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When
1595 * =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1
1596 * E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication
1597 * is disabled. When =0 indicates that the P0 EEE LPI REQ indication is
1598 * enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
1599 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
1600 * indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates
1601 * that the P0 EEE LPI REQ indication is disabled. When =0 indicates that
1602 * the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1
1603 * indicates that the L1 REQ indication is disabled. When =0 indicates that
1604 * the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask.
1605 * When =1 indicates that the RX EEE LPI Status Falling Edge Detect
1606 * indication is disabled (Rx EEE LPI is on - off). When =0 indicates that
1607 * the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE
1608 * LPI is on - off). This bit is applicable only in the EXIT Events Masks
1609 * registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the
1610 * L1 Status Falling Edge Detect indication from the PCIE CORE is disabled
1611 * (L1 is on - off). When =0 indicates that the L1 Status Falling Edge
1612 * Detect indication from the PCIE CORE is enabled (L1 is on - off). This
1613 * bit is applicable only in the EXIT Events Masks registers.Clock 25MHz.
1614 * Reset on hard reset. */
1615 #define MISC_REG_CPMU_LP_MASK_EXT_P0 0xa888
1616 /* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
1617 * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
1618 * register. Reset on hard reset. */
1619 #define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 0xa8b8
1620 /* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
1621 * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
1622 * register. Reset on hard reset. */
1623 #define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 0xa8bc
1624 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1625 32 clients. Each client can be controlled by one driver only. One in each
1626 bit represent that this driver control the appropriate client (Ex: bit 5
1627 is set means this driver control client number 5). addr1 = set; addr0 =
1628 clear; read from both addresses will give the same result = status. write
1629 to address 1 will set a request to control all the clients that their
1630 appropriate bit (in the write command) is set. if the client is free (the
1631 appropriate bit in all the other drivers is clear) one will be written to
1632 that driver register; if the client isn't free the bit will remain zero.
1633 if the appropriate bit is set (the driver request to gain control on a
1634 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1635 interrupt will be asserted). write to address 0 will set a request to
1636 free all the clients that their appropriate bit (in the write command) is
1637 set. if the appropriate bit is clear (the driver request to free a client
1638 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1640 #define MISC_REG_DRIVER_CONTROL_1 0xa510
1641 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1642 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1644 #define MISC_REG_E1HMF_MODE 0xa5f8
1645 /* [R 1] Status of four port mode path swap input pin. */
1646 #define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c
1647 /* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
1648 the path_swap output is equal to 4 port mode path swap input pin; if it
1649 is 1 - the path_swap output is equal to bit[1] of this register; [1] -
1650 Overwrite value. If bit[0] of this register is 1 this is the value that
1651 receives the path_swap output. Reset on Hard reset. */
1652 #define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738
1653 /* [R 1] Status of 4 port mode port swap input pin. */
1654 #define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754
1655 /* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
1656 the port_swap output is equal to 4 port mode port swap input pin; if it
1657 is 1 - the port_swap output is equal to bit[1] of this register; [1] -
1658 Overwrite value. If bit[0] of this register is 1 this is the value that
1659 receives the port_swap output. Reset on Hard reset. */
1660 #define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734
1661 /* [RW 32] Debug only: spare RW register reset by core reset */
1662 #define MISC_REG_GENERIC_CR_0 0xa460
1663 #define MISC_REG_GENERIC_CR_1 0xa464
1664 /* [RW 32] Debug only: spare RW register reset by por reset */
1665 #define MISC_REG_GENERIC_POR_1 0xa474
1666 /* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
1667 use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO
1668 can not be configured as an output. Each output has its output enable in
1669 the MCP register space; but this bit needs to be set to make use of that.
1670 Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When
1671 set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
1672 When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
1673 the i/o to an output and will drive the TimeSync output. Bit[31:7]:
1674 spare. Global register. Reset by hard reset. */
1675 #define MISC_REG_GEN_PURP_HWG 0xa9a0
1676 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1677 these bits is written as a '1'; the corresponding SPIO bit will turn off
1678 it's drivers and become an input. This is the reset state of all GPIO
1679 pins. The read value of these bits will be a '1' if that last command
1680 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1681 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1682 as a '1'; the corresponding GPIO bit will drive low. The read value of
1683 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1684 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1685 SET When any of these bits is written as a '1'; the corresponding GPIO
1686 bit will drive high (if it has that capability). The read value of these
1687 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1688 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1689 RO; These bits indicate the read value of each of the eight GPIO pins.
1690 This is the result value of the pin; not the drive value. Writing these
1691 bits will have not effect. */
1692 #define MISC_REG_GPIO 0xa490
1693 /* [RW 8] These bits enable the GPIO_INTs to signals event to the
1694 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1695 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1697 #define MISC_REG_GPIO_EVENT_EN 0xa2bc
1698 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1699 '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
1700 This will acknowledge an interrupt on the falling edge of corresponding
1701 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1702 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
1703 register. This will acknowledge an interrupt on the rising edge of
1704 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1705 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
1706 value. When the ~INT_STATE bit is set; this bit indicates the OLD value
1707 of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1708 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
1709 is '1'; then the interrupt is due to a high to low edge (reset value 0).
1710 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1711 current GPIO interrupt state for each GPIO pin. This bit is cleared when
1712 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
1713 set when the GPIO input does not match the current value in #OLD_VALUE
1715 #define MISC_REG_GPIO_INT 0xa494
1716 /* [R 28] this field hold the last information that caused reserved
1717 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1718 [27:24] the master that caused the attention - according to the following
1719 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1721 #define MISC_REG_GRC_RSV_ATTN 0xa3c0
1722 /* [R 28] this field hold the last information that caused timeout
1723 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1724 [27:24] the master that caused the attention - according to the following
1725 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1727 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
1728 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1729 access that does not finish within
1730 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1731 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1732 assert it attention output. */
1733 #define MISC_REG_GRC_TIMEOUT_EN 0xa280
1734 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1735 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1736 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1737 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1738 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1739 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1740 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1741 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1742 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1743 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1744 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1745 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1746 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1747 connected to RESET input directly. [15] capRetry_en (reset value 0)
1748 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1749 value 0) bit to continuously monitor vco freq (inverted). [17]
1750 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1751 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1752 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1753 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1754 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1755 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1756 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1757 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1758 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1759 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1760 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1762 #define MISC_REG_LCPLL_CTRL_1 0xa2a4
1763 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1764 /* [RW 1] LCPLL power down. Global register. Active High. Reset on POR
1766 #define MISC_REG_LCPLL_E40_PWRDWN 0xaa74
1767 /* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */
1768 #define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa78
1769 /* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR
1771 #define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7c
1772 /* [RW 4] Interrupt mask register #0 read/write */
1773 #define MISC_REG_MISC_INT_MASK 0xa388
1774 /* [RW 1] Parity mask register #0 read/write */
1775 #define MISC_REG_MISC_PRTY_MASK 0xa398
1776 /* [R 1] Parity register #0 read */
1777 #define MISC_REG_MISC_PRTY_STS 0xa38c
1778 /* [RC 1] Parity register #0 read clear */
1779 #define MISC_REG_MISC_PRTY_STS_CLR 0xa390
1780 #define MISC_REG_NIG_WOL_P0 0xa270
1781 #define MISC_REG_NIG_WOL_P1 0xa274
1782 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1784 #define MISC_REG_PCIE_HOT_RESET 0xa618
1785 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1786 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1787 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1788 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1789 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1790 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1791 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1792 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1793 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1794 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1795 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1796 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1797 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1798 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1799 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1800 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1801 testa_en (reset value 0); */
1802 #define MISC_REG_PLL_STORM_CTRL_1 0xa294
1803 #define MISC_REG_PLL_STORM_CTRL_2 0xa298
1804 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1805 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1806 /* [R 1] Status of 4 port mode enable input pin. */
1807 #define MISC_REG_PORT4MODE_EN 0xa750
1808 /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1809 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
1810 * the port4mode_en output is equal to bit[1] of this register; [1] -
1811 * Overwrite value. If bit[0] of this register is 1 this is the value that
1812 * receives the port4mode_en output . */
1813 #define MISC_REG_PORT4MODE_EN_OVWR 0xa720
1814 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1815 write/read zero = the specific block is in reset; addr 0-wr- the write
1816 value will be written to the register; addr 1-set - one will be written
1817 to all the bits that have the value of one in the data written (bits that
1818 have the value of zero will not be change) ; addr 2-clear - zero will be
1819 written to all the bits that have the value of one in the data written
1820 (bits that have the value of zero will not be change); addr 3-ignore;
1821 read ignore from all addr except addr 00; inside order of the bits is:
1822 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1823 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1824 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1825 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1826 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1827 rst_pxp_rq_rd_wr; 31:17] reserved */
1828 #define MISC_REG_RESET_REG_1 0xa580
1829 #define MISC_REG_RESET_REG_2 0xa590
1830 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1831 shared with the driver resides */
1832 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1833 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1834 the corresponding SPIO bit will turn off it's drivers and become an
1835 input. This is the reset state of all SPIO pins. The read value of these
1836 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1837 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1838 is written as a '1'; the corresponding SPIO bit will drive low. The read
1839 value of these bits will be a '1' if that last command (#SET; #CLR; or
1840 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1841 these bits is written as a '1'; the corresponding SPIO bit will drive
1842 high (if it has that capability). The read value of these bits will be a
1843 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1844 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1845 each of the eight SPIO pins. This is the result value of the pin; not the
1846 drive value. Writing these bits will have not effect. Each 8 bits field
1847 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1848 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1849 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1850 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1851 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1852 select VAUX supply. (This is an output pin only; it is not controlled by
1853 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1854 field is not applicable for this pin; only the VALUE fields is relevant -
1855 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1856 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1857 device ID select; read by UMP firmware. */
1858 #define MISC_REG_SPIO 0xa4fc
1859 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1860 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1862 #define MISC_REG_SPIO_EVENT_EN 0xa2b8
1863 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1864 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1865 interrupt on the falling edge of corresponding SPIO input (reset value
1866 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1867 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1868 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1869 RO; These bits indicate the old value of the SPIO input value. When the
1870 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1871 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1872 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1873 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1874 RO; These bits indicate the current SPIO interrupt state for each SPIO
1875 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1876 command bit is written. This bit is set when the SPIO input does not
1877 match the current value in #OLD_VALUE (reset value 0). */
1878 #define MISC_REG_SPIO_INT 0xa500
1879 /* [RW 32] reload value for counter 4 if reload; the value will be reload if
1880 the counter reached zero and the reload bit
1881 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1882 #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1883 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1884 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 -
1886 #define MISC_REG_SW_TIMER_VAL 0xa5c0
1887 /* [R 1] Status of two port mode path swap input pin. */
1888 #define MISC_REG_TWO_PORT_PATH_SWAP 0xa758
1889 /* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
1890 path_swap output is equal to 2 port mode path swap input pin; if it is 1
1891 - the path_swap output is equal to bit[1] of this register; [1] -
1892 Overwrite value. If bit[0] of this register is 1 this is the value that
1893 receives the path_swap output. Reset on Hard reset. */
1894 #define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c
1895 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1896 loaded; 0-prepare; -unprepare */
1897 #define MISC_REG_UNPREPARED 0xa424
1898 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1899 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1900 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1901 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1902 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1903 /* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
1904 * not it is the recipient of the message on the MDIO interface. The value
1905 * is compared to the value on ctrl_md_devad. Drives output
1906 * misc_xgxs0_phy_addr. Global register. */
1907 #define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc
1908 #define MISC_REG_WC0_RESET 0xac30
1909 /* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
1910 side. This should be less than or equal to phy_port_mode; if some of the
1911 ports are not used. This enables reduction of frequency on the core side.
1912 This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
1913 Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
1914 input for the XMAC_MP core; and should be changed only while reset is
1915 held low. Reset on Hard reset. */
1916 #define MISC_REG_XMAC_CORE_PORT_MODE 0xa964
1917 /* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
1918 Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
1919 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
1920 XMAC_MP core; and should be changed only while reset is held low. Reset
1922 #define MISC_REG_XMAC_PHY_PORT_MODE 0xa960
1923 /* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
1924 * Reads from this register will clear bits 31:0. */
1925 #define MSTAT_REG_RX_STAT_GR64_LO 0x200
1926 /* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
1927 * 31:0. Reads from this register will clear bits 31:0. */
1928 #define MSTAT_REG_TX_STAT_GTXPOK_LO 0
1929 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1930 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1931 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1932 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1933 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1934 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
1935 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
1936 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1937 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1938 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1939 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1940 /* [RW 1] Input enable for RX_BMAC0 IF */
1941 #define NIG_REG_BMAC0_IN_EN 0x100ac
1942 /* [RW 1] output enable for TX_BMAC0 IF */
1943 #define NIG_REG_BMAC0_OUT_EN 0x100e0
1944 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1945 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1946 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1947 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1948 /* [RW 1] output enable for RX BRB1 port0 IF */
1949 #define NIG_REG_BRB0_OUT_EN 0x100f8
1950 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1951 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1952 /* [RW 1] output enable for RX BRB1 port1 IF */
1953 #define NIG_REG_BRB1_OUT_EN 0x100fc
1954 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1955 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1956 /* [RW 1] output enable for RX BRB1 LP IF */
1957 #define NIG_REG_BRB_LB_OUT_EN 0x10100
1958 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1959 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1960 72:73]-vnic_num; 81:74]-sideband_info */
1961 #define NIG_REG_DEBUG_PACKET_LB 0x10800
1962 /* [RW 1] Input enable for TX Debug packet */
1963 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1964 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1965 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1966 First packet may be deleted from the middle. And last packet will be
1967 always deleted till the end. */
1968 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1969 /* [RW 1] Output enable to EMAC0 */
1970 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1971 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1972 to emac for port0; other way to bmac for port0 */
1973 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1974 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1975 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1976 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1977 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1978 /* [RW 1] Input enable for TX UMP management packet port0 IF */
1979 #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
1980 /* [RW 1] Input enable for RX_EMAC0 IF */
1981 #define NIG_REG_EMAC0_IN_EN 0x100a4
1982 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1983 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1984 /* [R 1] status from emac0. This bit is set when MDINT from either the
1985 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1986 be cleared in the attached PHY device that is driving the MINT pin. */
1987 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1988 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1989 are described in appendix A. In order to access the BMAC0 registers; the
1990 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1991 added to each BMAC register offset */
1992 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1993 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1994 are described in appendix A. In order to access the BMAC0 registers; the
1995 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1996 added to each BMAC register offset */
1997 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1998 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1999 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
2000 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
2001 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
2002 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
2003 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
2004 logic for interrupts must be used. Enable per bit of interrupt of
2005 ~latch_status.latch_status */
2006 #define NIG_REG_LATCH_BC_0 0x16210
2007 /* [RW 27] Latch for each interrupt from Unicore.b[0]
2008 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
2009 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
2010 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
2011 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
2012 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
2013 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
2014 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
2015 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
2016 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
2017 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
2018 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
2019 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
2020 #define NIG_REG_LATCH_STATUS_0 0x18000
2021 /* [RW 1] led 10g for port 0 */
2022 #define NIG_REG_LED_10G_P0 0x10320
2023 /* [RW 1] led 10g for port 1 */
2024 #define NIG_REG_LED_10G_P1 0x10324
2025 /* [RW 1] Port0: This bit is set to enable the use of the
2026 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
2027 defined below. If this bit is cleared; then the blink rate will be about
2029 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
2030 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
2031 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
2032 is reset to 0x080; giving a default blink period of approximately 8Hz. */
2033 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
2034 /* [RW 1] Port0: If set along with the
2035 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
2036 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
2037 bit; the Traffic LED will blink with the blink rate specified in
2038 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
2039 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
2041 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
2042 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
2043 Traffic LED will then be controlled via bit ~nig_registers_
2044 led_control_traffic_p0.led_control_traffic_p0 and bit
2045 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
2046 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
2047 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
2048 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
2049 set; the LED will blink with blink rate specified in
2050 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
2051 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
2053 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
2054 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
2055 9-11PHY7; 12 MAC4; 13-15 PHY10; */
2056 #define NIG_REG_LED_MODE_P0 0x102f0
2057 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
2058 tsdm enable; b2- usdm enable */
2059 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
2060 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
2061 /* [RW 1] SAFC enable for port0. This register may get 1 only when
2062 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
2064 #define NIG_REG_LLFC_ENABLE_0 0x16208
2065 #define NIG_REG_LLFC_ENABLE_1 0x1620c
2066 /* [RW 16] classes are high-priority for port0 */
2067 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
2068 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c
2069 /* [RW 16] classes are low-priority for port0 */
2070 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
2071 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064
2072 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
2073 #define NIG_REG_LLFC_OUT_EN_0 0x160c8
2074 #define NIG_REG_LLFC_OUT_EN_1 0x160cc
2075 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
2076 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
2077 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
2078 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
2079 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
2080 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
2081 /* [RW 2] Determine the classification participants. 0: no classification.1:
2082 classification upon VLAN id. 2: classification upon MAC address. 3:
2083 classification upon both VLAN id & MAC addr. */
2084 #define NIG_REG_LLH0_CLS_TYPE 0x16080
2085 /* [RW 32] cm header for llh0 */
2086 #define NIG_REG_LLH0_CM_HEADER 0x1007c
2087 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
2088 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
2089 /* [RW 16] destination TCP address 1. The LLH will look for this address in
2090 all incoming packets. */
2091 #define NIG_REG_LLH0_DEST_TCP_0 0x10220
2092 /* [RW 16] destination UDP address 1 The LLH will look for this address in
2093 all incoming packets. */
2094 #define NIG_REG_LLH0_DEST_UDP_0 0x10214
2095 #define NIG_REG_LLH0_ERROR_MASK 0x1008c
2096 /* [RW 8] event id for llh0 */
2097 #define NIG_REG_LLH0_EVENT_ID 0x10084
2098 #define NIG_REG_LLH0_FUNC_EN 0x160fc
2099 #define NIG_REG_LLH0_FUNC_MEM 0x16180
2100 #define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140
2101 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
2102 /* [RW 1] Determine the IP version to look for in
2103 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
2104 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
2105 /* [RW 1] t bit for llh0 */
2106 #define NIG_REG_LLH0_T_BIT 0x10074
2107 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
2108 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c
2109 /* [RW 8] init credit counter for port0 in LLH */
2110 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
2111 #define NIG_REG_LLH0_XCM_MASK 0x10130
2112 #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
2113 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
2114 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
2115 /* [RW 2] Determine the classification participants. 0: no classification.1:
2116 classification upon VLAN id. 2: classification upon MAC address. 3:
2117 classification upon both VLAN id & MAC addr. */
2118 #define NIG_REG_LLH1_CLS_TYPE 0x16084
2119 /* [RW 32] cm header for llh1 */
2120 #define NIG_REG_LLH1_CM_HEADER 0x10080
2121 #define NIG_REG_LLH1_ERROR_MASK 0x10090
2122 /* [RW 8] event id for llh1 */
2123 #define NIG_REG_LLH1_EVENT_ID 0x10088
2124 #define NIG_REG_LLH1_FUNC_EN 0x16104
2125 #define NIG_REG_LLH1_FUNC_MEM 0x161c0
2126 #define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
2127 #define NIG_REG_LLH1_FUNC_MEM_SIZE 16
2128 /* [RW 1] When this bit is set; the LLH will classify the packet before
2129 * sending it to the BRB or calculating WoL on it. This bit controls port 1
2130 * only. The legacy llh_multi_function_mode bit controls port 0. */
2131 #define NIG_REG_LLH1_MF_MODE 0x18614
2132 /* [RW 8] init credit counter for port1 in LLH */
2133 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
2134 #define NIG_REG_LLH1_XCM_MASK 0x10134
2135 /* [RW 1] When this bit is set; the LLH will expect all packets to be with
2137 #define NIG_REG_LLH_E1HOV_MODE 0x160d8
2138 /* [RW 1] When this bit is set; the LLH will classify the packet before
2139 sending it to the BRB or calculating WoL on it. */
2140 #define NIG_REG_LLH_MF_MODE 0x16024
2141 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
2142 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
2143 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
2144 #define NIG_REG_NIG_EMAC0_EN 0x1003c
2145 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
2146 #define NIG_REG_NIG_EMAC1_EN 0x10040
2147 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
2148 EMAC0 to strip the CRC from the ingress packets. */
2149 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
2150 /* [R 32] Interrupt register #0 read */
2151 #define NIG_REG_NIG_INT_STS_0 0x103b0
2152 #define NIG_REG_NIG_INT_STS_1 0x103c0
2153 /* [RC 32] Interrupt register #0 read clear */
2154 #define NIG_REG_NIG_INT_STS_CLR_0 0x103b4
2155 /* [R 32] Legacy E1 and E1H location for parity error mask register. */
2156 #define NIG_REG_NIG_PRTY_MASK 0x103dc
2157 /* [RW 32] Parity mask register #0 read/write */
2158 #define NIG_REG_NIG_PRTY_MASK_0 0x183c8
2159 #define NIG_REG_NIG_PRTY_MASK_1 0x183d8
2160 /* [R 32] Legacy E1 and E1H location for parity error status register. */
2161 #define NIG_REG_NIG_PRTY_STS 0x103d0
2162 /* [R 32] Parity register #0 read */
2163 #define NIG_REG_NIG_PRTY_STS_0 0x183bc
2164 #define NIG_REG_NIG_PRTY_STS_1 0x183cc
2165 /* [R 32] Legacy E1 and E1H location for parity error status clear register. */
2166 #define NIG_REG_NIG_PRTY_STS_CLR 0x103d4
2167 /* [RC 32] Parity register #0 read clear */
2168 #define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0
2169 #define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0
2170 #define MCPR_IMC_COMMAND_ENABLE (1L<<31)
2171 #define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
2172 #define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
2173 #define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
2174 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2175 * Ethernet header. */
2176 #define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
2177 /* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
2178 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
2179 * disabled when this bit is set. */
2180 #define NIG_REG_P0_HWPFC_ENABLE 0x18078
2181 #define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
2182 #define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440
2183 /* [RW 1] Input enable for RX MAC interface. */
2184 #define NIG_REG_P0_MAC_IN_EN 0x185ac
2185 /* [RW 1] Output enable for TX MAC interface */
2186 #define NIG_REG_P0_MAC_OUT_EN 0x185b0
2187 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2188 #define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4
2189 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2190 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2191 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2192 * priority field is extracted from the outer-most VLAN in receive packet.
2193 * Only COS 0 and COS 1 are supported in E2. */
2194 #define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
2195 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2196 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2197 * than one bit may be set; allowing multiple priorities to be mapped to one
2199 #define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058
2200 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2201 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2202 * than one bit may be set; allowing multiple priorities to be mapped to one
2204 #define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
2205 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2206 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2207 * than one bit may be set; allowing multiple priorities to be mapped to one
2209 #define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0
2210 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
2211 * priority is mapped to COS 3 when the corresponding mask bit is 1. More
2212 * than one bit may be set; allowing multiple priorities to be mapped to one
2214 #define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4
2215 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
2216 * priority is mapped to COS 4 when the corresponding mask bit is 1. More
2217 * than one bit may be set; allowing multiple priorities to be mapped to one
2219 #define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8
2220 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
2221 * priority is mapped to COS 5 when the corresponding mask bit is 1. More
2222 * than one bit may be set; allowing multiple priorities to be mapped to one
2224 #define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc
2225 /* [R 1] RX FIFO for receiving data from MAC is empty. */
2226 /* [RW 15] Specify which of the credit registers the client is to be mapped
2227 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
2228 * clients that are not subject to WFQ credit blocking - their
2229 * specifications here are not used. */
2230 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
2231 /* [RW 32] Specify which of the credit registers the client is to be mapped
2232 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2233 * for client 0; bits [35:32] are for client 8. For clients that are not
2234 * subject to WFQ credit blocking - their specifications here are not used.
2235 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2236 * input clients to ETS arbiter. The reset default is set for management and
2237 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2238 * use credit registers 0-5 respectively (0x543210876). Note that credit
2239 * registers can not be shared between clients. */
2240 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688
2241 /* [RW 4] Specify which of the credit registers the client is to be mapped
2242 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2243 * for client 0; bits [35:32] are for client 8. For clients that are not
2244 * subject to WFQ credit blocking - their specifications here are not used.
2245 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2246 * input clients to ETS arbiter. The reset default is set for management and
2247 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2248 * use credit registers 0-5 respectively (0x543210876). Note that credit
2249 * registers can not be shared between clients. */
2250 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c
2251 /* [RW 5] Specify whether the client competes directly in the strict
2252 * priority arbiter. The bits are mapped according to client ID (client IDs
2253 * are defined in tx_arb_priority_client). Default value is set to enable
2254 * strict priorities for clients 0-2 -- management and debug traffic. */
2255 #define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8
2256 /* [RW 5] Specify whether the client is subject to WFQ credit blocking. The
2257 * bits are mapped according to client ID (client IDs are defined in
2258 * tx_arb_priority_client). Default value is 0 for not using WFQ credit
2260 #define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec
2261 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
2263 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
2264 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
2265 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114
2266 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118
2267 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c
2268 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0
2269 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4
2270 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8
2271 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac
2272 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2273 * when it is time to increment. */
2274 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
2275 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
2276 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100
2277 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104
2278 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108
2279 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690
2280 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694
2281 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698
2282 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c
2283 /* [RW 12] Specify the number of strict priority arbitration slots between
2284 * two round-robin arbitration slots to avoid starvation. A value of 0 means
2285 * no strict priority cycles - the strict priority with anti-starvation
2286 * arbiter becomes a round-robin arbiter. */
2287 #define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4
2288 /* [RW 15] Specify the client number to be assigned to each priority of the
2289 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
2290 * are for priority 0 client; bits [14:12] are for priority 4 client. The
2291 * clients are assigned the following IDs: 0-management; 1-debug traffic
2292 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2293 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
2294 * for management at priority 0; debug traffic at priorities 1 and 2; COS0
2295 * traffic at priority 3; and COS1 traffic at priority 4. */
2296 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
2297 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2298 * Ethernet header. */
2299 #define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
2300 #define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
2301 #define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460
2302 /* [RW 32] Specify the client number to be assigned to each priority of the
2303 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2304 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2305 * client; bits [35-32] are for priority 8 client. The clients are assigned
2306 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2307 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2308 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2309 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2310 * accommodate the 9 input clients to ETS arbiter. */
2311 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680
2312 /* [RW 4] Specify the client number to be assigned to each priority of the
2313 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2314 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2315 * client; bits [35-32] are for priority 8 client. The clients are assigned
2316 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2317 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2318 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2319 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2320 * accommodate the 9 input clients to ETS arbiter. */
2321 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684
2322 /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
2323 * packets to BRB LB interface to forward the packet to the host. All
2324 * packets from MCP are forwarded to the network when this bit is cleared -
2325 * regardless of the configured destination in tx_mng_destination register.
2326 * When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter
2327 * for BRB LB interface is bypassed and PBF LB traffic is always selected to
2330 #define NIG_REG_P0_TX_MNG_HOST_ENABLE 0x182f4
2331 #define NIG_REG_P1_HWPFC_ENABLE 0x181d0
2332 #define NIG_REG_P1_MAC_IN_EN 0x185c0
2333 /* [RW 1] Output enable for TX MAC interface */
2334 #define NIG_REG_P1_MAC_OUT_EN 0x185c4
2335 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2336 #define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8
2337 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2338 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2339 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2340 * priority field is extracted from the outer-most VLAN in receive packet.
2341 * Only COS 0 and COS 1 are supported in E2. */
2342 #define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
2343 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2344 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2345 * than one bit may be set; allowing multiple priorities to be mapped to one
2347 #define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac
2348 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2349 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2350 * than one bit may be set; allowing multiple priorities to be mapped to one
2352 #define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
2353 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2354 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2355 * than one bit may be set; allowing multiple priorities to be mapped to one
2357 #define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8
2358 /* [R 1] RX FIFO for receiving data from MAC is empty. */
2359 #define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c
2360 /* [R 1] TLLH FIFO is empty. */
2361 #define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338
2362 /* [RW 32] Specify which of the credit registers the client is to be mapped
2363 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2364 * for client 0; bits [35:32] are for client 8. For clients that are not
2365 * subject to WFQ credit blocking - their specifications here are not used.
2366 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2367 * input clients to ETS arbiter. The reset default is set for management and
2368 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2369 * use credit registers 0-5 respectively (0x543210876). Note that credit
2370 * registers can not be shared between clients. Note also that there are
2371 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2372 * credit registers 0-5 are valid. This register should be configured
2373 * appropriately before enabling WFQ. */
2374 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8
2375 /* [RW 4] Specify which of the credit registers the client is to be mapped
2376 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2377 * for client 0; bits [35:32] are for client 8. For clients that are not
2378 * subject to WFQ credit blocking - their specifications here are not used.
2379 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2380 * input clients to ETS arbiter. The reset default is set for management and
2381 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2382 * use credit registers 0-5 respectively (0x543210876). Note that credit
2383 * registers can not be shared between clients. Note also that there are
2384 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2385 * credit registers 0-5 are valid. This register should be configured
2386 * appropriately before enabling WFQ. */
2387 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec
2388 /* [RW 9] Specify whether the client competes directly in the strict
2389 * priority arbiter. The bits are mapped according to client ID (client IDs
2390 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
2391 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2392 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
2393 * Default value is set to enable strict priorities for all clients. */
2394 #define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234
2395 /* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
2396 * bits are mapped according to client ID (client IDs are defined in
2397 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
2398 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
2399 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
2400 * 0 for not using WFQ credit blocking. */
2401 #define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238
2402 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258
2403 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c
2404 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260
2405 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264
2406 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268
2407 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4
2408 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2409 * when it is time to increment. */
2410 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244
2411 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248
2412 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c
2413 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250
2414 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254
2415 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0
2416 /* [RW 12] Specify the number of strict priority arbitration slots between
2417 two round-robin arbitration slots to avoid starvation. A value of 0 means
2418 no strict priority cycles - the strict priority with anti-starvation
2419 arbiter becomes a round-robin arbiter. */
2420 #define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240
2421 /* [RW 32] Specify the client number to be assigned to each priority of the
2422 strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2423 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2424 client; bits [35-32] are for priority 8 client. The clients are assigned
2425 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2426 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2427 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2428 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2429 accommodate the 9 input clients to ETS arbiter. Note that this register
2430 is the same as the one for port 0, except that port 1 only has COS 0-2
2431 traffic. There is no traffic for COS 3-5 of port 1. */
2432 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0
2433 /* [RW 4] Specify the client number to be assigned to each priority of the
2434 strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2435 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2436 client; bits [35-32] are for priority 8 client. The clients are assigned
2437 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2438 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2439 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2440 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2441 accommodate the 9 input clients to ETS arbiter. Note that this register
2442 is the same as the one for port 0, except that port 1 only has COS 0-2
2443 traffic. There is no traffic for COS 3-5 of port 1. */
2444 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4
2445 /* [R 1] TX FIFO for transmitting data to MAC is empty. */
2446 #define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594
2447 /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
2448 * packets to BRB LB interface to forward the packet to the host. All
2449 * packets from MCP are forwarded to the network when this bit is cleared -
2450 * regardless of the configured destination in tx_mng_destination register.
2452 #define NIG_REG_P1_TX_MNG_HOST_ENABLE 0x182f8
2453 /* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
2454 forwarded to the host. */
2455 #define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8
2456 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
2458 /* [RW 1] Pause enable for port0. This register may get 1 only when
2459 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
2461 #define NIG_REG_PAUSE_ENABLE_0 0x160c0
2462 #define NIG_REG_PAUSE_ENABLE_1 0x160c4
2463 /* [RW 1] Input enable for RX PBF LP IF */
2464 #define NIG_REG_PBF_LB_IN_EN 0x100b4
2465 /* [RW 1] Value of this register will be transmitted to port swap when
2466 ~nig_registers_strap_override.strap_override =1 */
2467 #define NIG_REG_PORT_SWAP 0x10394
2468 /* [RW 1] PPP enable for port0. This register may get 1 only when
2469 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
2471 #define NIG_REG_PPP_ENABLE_0 0x160b0
2472 #define NIG_REG_PPP_ENABLE_1 0x160b4
2473 /* [RW 1] output enable for RX parser descriptor IF */
2474 #define NIG_REG_PRS_EOP_OUT_EN 0x10104
2475 /* [RW 1] Input enable for RX parser request IF */
2476 #define NIG_REG_PRS_REQ_IN_EN 0x100b8
2477 /* [RW 5] control to serdes - CL45 DEVAD */
2478 #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
2479 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
2480 #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
2481 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
2482 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
2483 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
2484 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
2485 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2487 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0
2488 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
2490 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
2491 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2492 between 1024 and 1522 bytes for port0 */
2493 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
2494 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2495 between 1523 bytes and above for port0 */
2496 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
2497 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2499 #define NIG_REG_STAT1_BRB_DISCARD 0x10628
2500 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2501 between 1024 and 1522 bytes for port1 */
2502 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
2503 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2504 between 1523 bytes and above for port1 */
2505 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
2506 /* [WB_R 64] Rx statistics : User octets received for LP */
2507 #define NIG_REG_STAT2_BRB_OCTET 0x107e0
2508 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
2509 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
2510 /* [RW 1] port swap mux selection. If this register equal to 0 then port
2511 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
2512 ort swap is equal to ~nig_registers_port_swap.port_swap */
2513 #define NIG_REG_STRAP_OVERRIDE 0x10398
2514 /* [RW 1] output enable for RX_XCM0 IF */
2515 #define NIG_REG_XCM0_OUT_EN 0x100f0
2516 /* [RW 1] output enable for RX_XCM1 IF */
2517 #define NIG_REG_XCM1_OUT_EN 0x100f4
2518 /* [RW 1] control to xgxs - remote PHY in-band MDIO */
2519 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
2520 /* [RW 5] control to xgxs - CL45 DEVAD */
2521 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
2522 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
2523 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
2524 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
2525 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
2526 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
2527 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
2528 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
2529 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
2530 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
2531 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
2532 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
2533 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
2534 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
2535 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
2536 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
2537 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
2538 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
2539 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
2540 #define PBF_REG_COS0_UPPER_BOUND 0x15c05c
2541 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2543 #define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc
2544 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2546 #define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4
2547 /* [RW 31] The weight of COS0 in the ETS command arbiter. */
2548 #define PBF_REG_COS0_WEIGHT 0x15c054
2549 /* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */
2550 #define PBF_REG_COS0_WEIGHT_P0 0x15c2a8
2551 /* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */
2552 #define PBF_REG_COS0_WEIGHT_P1 0x15c2c0
2553 /* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
2554 #define PBF_REG_COS1_UPPER_BOUND 0x15c060
2555 /* [RW 31] The weight of COS1 in the ETS command arbiter. */
2556 #define PBF_REG_COS1_WEIGHT 0x15c058
2557 /* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */
2558 #define PBF_REG_COS1_WEIGHT_P0 0x15c2ac
2559 /* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */
2560 #define PBF_REG_COS1_WEIGHT_P1 0x15c2c4
2561 /* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */
2562 #define PBF_REG_COS2_WEIGHT_P0 0x15c2b0
2563 /* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */
2564 #define PBF_REG_COS2_WEIGHT_P1 0x15c2c8
2565 /* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */
2566 #define PBF_REG_COS3_WEIGHT_P0 0x15c2b4
2567 /* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */
2568 #define PBF_REG_COS4_WEIGHT_P0 0x15c2b8
2569 /* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */
2570 #define PBF_REG_COS5_WEIGHT_P0 0x15c2bc
2571 /* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte
2573 #define PBF_REG_CREDIT_LB_Q 0x140338
2574 /* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
2576 #define PBF_REG_CREDIT_Q0 0x14033c
2577 /* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte
2579 #define PBF_REG_CREDIT_Q1 0x140340
2580 /* [RW 1] Disable processing further tasks from port 0 (after ending the
2581 current task in process). */
2582 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
2583 /* [RW 1] Disable processing further tasks from port 1 (after ending the
2584 current task in process). */
2585 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
2586 /* [RW 1] Disable processing further tasks from port 4 (after ending the
2587 current task in process). */
2588 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
2589 #define PBF_REG_DISABLE_PF 0x1402e8
2590 #define PBF_REG_DISABLE_VF 0x1402ec
2591 /* [RW 18] For port 0: For each client that is subject to WFQ (the
2592 * corresponding bit is 1); indicates to which of the credit registers this
2593 * client is mapped. For clients which are not credit blocked; their mapping
2595 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288
2596 /* [RW 9] For port 1: For each client that is subject to WFQ (the
2597 * corresponding bit is 1); indicates to which of the credit registers this
2598 * client is mapped. For clients which are not credit blocked; their mapping
2600 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c
2601 /* [RW 6] For port 0: Bit per client to indicate if the client competes in
2602 * the strict priority arbiter directly (corresponding bit = 1); or first
2603 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2604 * lowest priority in the strict-priority arbiter. */
2605 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278
2606 /* [RW 3] For port 1: Bit per client to indicate if the client competes in
2607 * the strict priority arbiter directly (corresponding bit = 1); or first
2608 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2609 * lowest priority in the strict-priority arbiter. */
2610 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c
2611 /* [RW 6] For port 0: Bit per client to indicate if the client is subject to
2612 * WFQ credit blocking (corresponding bit = 1). */
2613 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280
2614 /* [RW 3] For port 0: Bit per client to indicate if the client is subject to
2615 * WFQ credit blocking (corresponding bit = 1). */
2616 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284
2617 /* [RW 16] For port 0: The number of strict priority arbitration slots
2618 * between 2 RR arbitration slots. A value of 0 means no strict priority
2619 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2621 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0
2622 /* [RW 16] For port 1: The number of strict priority arbitration slots
2623 * between 2 RR arbitration slots. A value of 0 means no strict priority
2624 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2626 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4
2627 /* [RW 18] For port 0: Indicates which client is connected to each priority
2628 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2629 * priority 5 is the lowest; to which the RR output is connected to (this is
2630 * not configurable). */
2631 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270
2632 /* [RW 9] For port 1: Indicates which client is connected to each priority
2633 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2634 * priority 5 is the lowest; to which the RR output is connected to (this is
2635 * not configurable). */
2636 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274
2637 /* [RW 1] Indicates that ETS is performed between the COSes in the command
2638 * arbiter. If reset strict priority w/ anti-starvation will be performed
2640 #define PBF_REG_ETS_ENABLED 0x15c050
2641 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2642 * Ethernet header. */
2643 #define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
2644 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2645 #define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8
2646 /* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
2647 * priority in the command arbiter. */
2648 #define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
2649 #define PBF_REG_IF_ENABLE_REG 0x140044
2650 /* [RW 1] Init bit. When set the initial credits are copied to the credit
2651 registers (except the port credits). Should be set and then reset after
2652 the configuration of the block has ended. */
2653 #define PBF_REG_INIT 0x140000
2654 /* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
2656 #define PBF_REG_INIT_CRD_LB_Q 0x15c248
2657 /* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
2659 #define PBF_REG_INIT_CRD_Q0 0x15c230
2660 /* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
2662 #define PBF_REG_INIT_CRD_Q1 0x15c234
2663 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
2664 copied to the credit register. Should be set and then reset after the
2665 configuration of the port has ended. */
2666 #define PBF_REG_INIT_P0 0x140004
2667 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
2668 copied to the credit register. Should be set and then reset after the
2669 configuration of the port has ended. */
2670 #define PBF_REG_INIT_P1 0x140008
2671 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
2672 copied to the credit register. Should be set and then reset after the
2673 configuration of the port has ended. */
2674 #define PBF_REG_INIT_P4 0x14000c
2675 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2676 * the LB queue. Reset upon init. */
2677 #define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354
2678 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2679 * queue 0. Reset upon init. */
2680 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358
2681 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2682 * queue 1. Reset upon init. */
2683 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c
2684 /* [RW 1] Enable for mac interface 0. */
2685 #define PBF_REG_MAC_IF0_ENABLE 0x140030
2686 /* [RW 1] Enable for mac interface 1. */
2687 #define PBF_REG_MAC_IF1_ENABLE 0x140034
2688 /* [RW 1] Enable for the loopback interface. */
2689 #define PBF_REG_MAC_LB_ENABLE 0x140040
2690 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2691 #define PBF_REG_MUST_HAVE_HDRS 0x15c0c4
2692 /* [RW 16] The number of strict priority arbitration slots between 2 RR
2693 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the
2694 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */
2695 #define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064
2696 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
2698 #define PBF_REG_P0_ARB_THRSH 0x1400e4
2699 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
2700 #define PBF_REG_P0_CREDIT 0x140200
2701 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
2703 #define PBF_REG_P0_INIT_CRD 0x1400d0
2704 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2705 * port 0. Reset upon init. */
2706 #define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308
2707 /* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
2708 #define PBF_REG_P0_PAUSE_ENABLE 0x140014
2709 /* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
2710 #define PBF_REG_P0_TASK_CNT 0x140204
2711 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2712 * freed from the task queue of port 0. Reset upon init. */
2713 #define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0
2714 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
2715 #define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc
2716 /* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
2717 * buffers in 16 byte lines. */
2718 #define PBF_REG_P1_CREDIT 0x140208
2719 /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
2720 * buffers in 16 byte lines. */
2721 #define PBF_REG_P1_INIT_CRD 0x1400d4
2722 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2723 * port 1. Reset upon init. */
2724 #define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c
2725 /* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
2726 #define PBF_REG_P1_TASK_CNT 0x14020c
2727 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2728 * freed from the task queue of port 1. Reset upon init. */
2729 #define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4
2730 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */
2731 #define PBF_REG_P1_TQ_OCCUPANCY 0x140300
2732 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
2733 #define PBF_REG_P4_CREDIT 0x140210
2734 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
2736 #define PBF_REG_P4_INIT_CRD 0x1400e0
2737 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2738 * port 4. Reset upon init. */
2739 #define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310
2740 /* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
2741 #define PBF_REG_P4_TASK_CNT 0x140214
2742 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2743 * freed from the task queue of port 4. Reset upon init. */
2744 #define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8
2745 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */
2746 #define PBF_REG_P4_TQ_OCCUPANCY 0x140304
2747 /* [RW 5] Interrupt mask register #0 read/write */
2748 #define PBF_REG_PBF_INT_MASK 0x1401d4
2749 /* [R 5] Interrupt register #0 read */
2750 #define PBF_REG_PBF_INT_STS 0x1401c8
2751 /* [RW 20] Parity mask register #0 read/write */
2752 #define PBF_REG_PBF_PRTY_MASK 0x1401e4
2753 /* [RC 20] Parity register #0 read clear */
2754 #define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
2755 /* [RW 16] The Ethernet type value for L2 tag 0 */
2756 #define PBF_REG_TAG_ETHERTYPE_0 0x15c090
2757 /* [RW 4] The length of the info field for L2 tag 0. The length is between
2758 * 2B and 14B; in 2B granularity */
2759 #define PBF_REG_TAG_LEN_0 0x15c09c
2760 /* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task
2761 * queue. Reset upon init. */
2762 #define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c
2763 /* [R 32] Cyclic counter for number of 8 byte lines freed from the task
2764 * queue 0. Reset upon init. */
2765 #define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390
2766 /* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.
2767 * Reset upon init. */
2768 #define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394
2769 /* [R 13] Number of 8 bytes lines occupied in the task queue of the LB
2771 #define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8
2772 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
2773 #define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
2774 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
2775 #define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
2776 #define PB_REG_CONTROL 0
2777 /* [RW 2] Interrupt mask register #0 read/write */
2778 #define PB_REG_PB_INT_MASK 0x28
2779 /* [R 2] Interrupt register #0 read */
2780 #define PB_REG_PB_INT_STS 0x1c
2781 /* [RW 4] Parity mask register #0 read/write */
2782 #define PB_REG_PB_PRTY_MASK 0x38
2783 /* [R 4] Parity register #0 read */
2784 #define PB_REG_PB_PRTY_STS 0x2c
2785 /* [RC 4] Parity register #0 read clear */
2786 #define PB_REG_PB_PRTY_STS_CLR 0x30
2787 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2788 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
2789 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
2790 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)
2791 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
2792 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
2793 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
2794 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
2795 #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)
2796 /* [R 8] Config space A attention dirty bits. Each bit indicates that the
2797 * corresponding PF generates config space A attention. Set by PXP. Reset by
2798 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
2799 * from both paths. */
2800 #define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010
2801 /* [R 8] Config space B attention dirty bits. Each bit indicates that the
2802 * corresponding PF generates config space B attention. Set by PXP. Reset by
2803 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
2804 * from both paths. */
2805 #define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014
2806 /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
2808 #define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194
2809 /* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
2810 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
2811 #define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c
2812 /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
2814 #define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c
2815 /* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */
2816 #define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100
2817 /* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */
2818 #define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108
2819 /* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */
2820 #define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110
2821 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2822 #define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac
2823 /* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
2824 * that the FLR register of the corresponding PF was set. Set by PXP. Reset
2825 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
2826 * from both paths. */
2827 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028
2828 /* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
2829 * to a bit in this register in order to clear the corresponding bit in
2830 * flr_request_pf_7_0 register. Note: register contains bits from both
2832 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418
2833 /* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
2834 * indicates that the FLR register of the corresponding VF was set. Set by
2835 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */
2836 #define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024
2837 /* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
2838 * indicates that the FLR register of the corresponding VF was set. Set by
2839 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */
2840 #define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018
2841 /* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
2842 * indicates that the FLR register of the corresponding VF was set. Set by
2843 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */
2844 #define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c
2845 /* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
2846 * indicates that the FLR register of the corresponding VF was set. Set by
2847 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */
2848 #define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020
2849 /* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
2850 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
2851 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
2852 * arrived with a correctable error. Bit 3 - Configuration RW arrived with
2853 * an uncorrectable error. Bit 4 - Completion with Configuration Request
2854 * Retry Status. Bit 5 - Expansion ROM access received with a write request.
2855 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
2856 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
2857 * and pcie_rx_last not asserted. */
2858 #define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068
2859 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c
2860 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430
2861 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434
2862 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438
2863 /* [R 9] Interrupt register #0 read */
2864 #define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
2865 /* [RC 9] Interrupt register #0 read clear */
2866 #define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
2867 /* [RW 2] Parity mask register #0 read/write */
2868 #define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4
2869 /* [R 2] Parity register #0 read */
2870 #define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
2871 /* [RC 2] Parity register #0 read clear */
2872 #define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac
2873 /* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
2874 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
2875 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
2876 * completer abort. 3 - Illegal value for this field. [12] valid - indicates
2877 * if there was a completion error since the last time this register was
2879 #define PGLUE_B_REG_RX_ERR_DETAILS 0x9080
2880 /* [R 18] Details of first ATS Translation Completion request received with
2881 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
2882 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
2883 * unsupported request. 2 - completer abort. 3 - Illegal value for this
2884 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
2885 * completion error since the last time this register was cleared. */
2886 #define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084
2887 /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
2888 * a bit in this register in order to clear the corresponding bit in
2889 * shadow_bme_pf_7_0 register. MCP should never use this unless a
2890 * work-around is needed. Note: register contains bits from both paths. */
2891 #define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458
2892 /* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
2893 * VF enable register of the corresponding PF is written to 0 and was
2894 * previously 1. Set by PXP. Reset by MCP writing 1 to
2895 * sr_iov_disabled_request_clr. Note: register contains bits from both
2897 #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030
2898 /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
2899 * completion did not return yet. 1 - tag is unused. Same functionality as
2900 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
2901 #define PGLUE_B_REG_TAGS_63_32 0x9244
2902 /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
2904 #define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170
2905 /* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */
2906 #define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4
2907 /* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */
2908 #define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc
2909 /* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */
2910 #define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4
2911 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2912 #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0
2913 /* [R 32] Address [31:0] of first read request not submitted due to error */
2914 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098
2915 /* [R 32] Address [63:32] of first read request not submitted due to error */
2916 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c
2917 /* [R 31] Details of first read request not submitted due to error. [4:0]
2918 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
2919 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
2921 #define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0
2922 /* [R 26] Details of first read request not submitted due to error. [15:0]
2923 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2924 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2925 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2926 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2927 * indicates if there was a request not submitted due to error since the
2928 * last time this register was cleared. */
2929 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4
2930 /* [R 32] Address [31:0] of first write request not submitted due to error */
2931 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088
2932 /* [R 32] Address [63:32] of first write request not submitted due to error */
2933 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c
2934 /* [R 31] Details of first write request not submitted due to error. [4:0]
2935 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
2937 #define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090
2938 /* [R 26] Details of first write request not submitted due to error. [15:0]
2939 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2940 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2941 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2942 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2943 * indicates if there was a request not submitted due to error since the
2944 * last time this register was cleared. */
2945 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094
2946 /* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
2947 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
2948 * value (Byte resolution address). */
2949 #define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128
2950 #define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c
2951 #define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130
2952 #define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134
2953 #define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138
2954 #define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c
2955 #define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140
2956 /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
2958 #define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c
2959 /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
2961 #define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180
2962 /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
2964 #define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184
2965 /* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */
2966 #define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8
2967 /* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */
2968 #define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0
2969 /* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */
2970 #define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8
2971 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2972 #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4
2973 /* [R 26] Details of first target VF request accessing VF GRC space that
2974 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
2975 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
2976 * request accessing VF GRC space that failed permission check since the
2977 * last time this register was cleared. Permission checks are: function
2978 * permission; R/W permission; address range permission. */
2979 #define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234
2980 /* [R 31] Details of first target VF request with length violation (too many
2981 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
2982 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
2983 * valid - indicates if there was a request with length violation since the
2984 * last time this register was cleared. Length violations: length of more
2985 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
2986 * length is more than 1 DW. */
2987 #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230
2988 /* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
2989 * that there was a completion with uncorrectable error for the
2990 * corresponding PF. Set by PXP. Reset by MCP writing 1 to
2991 * was_error_pf_7_0_clr. */
2992 #define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c
2993 /* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
2994 * to a bit in this register in order to clear the corresponding bit in
2995 * flr_request_pf_7_0 register. */
2996 #define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470
2997 /* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
2998 * indicates that there was a completion with uncorrectable error for the
2999 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
3000 * was_error_vf_127_96_clr. */
3001 #define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078
3002 /* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
3003 * writes 1 to a bit in this register in order to clear the corresponding
3004 * bit in was_error_vf_127_96 register. */
3005 #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474
3006 /* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
3007 * indicates that there was a completion with uncorrectable error for the
3008 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
3009 * was_error_vf_31_0_clr. */
3010 #define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c
3011 /* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
3012 * 1 to a bit in this register in order to clear the corresponding bit in
3013 * was_error_vf_31_0 register. */
3014 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478
3015 /* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
3016 * indicates that there was a completion with uncorrectable error for the
3017 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
3018 * was_error_vf_63_32_clr. */
3019 #define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070
3020 /* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
3021 * 1 to a bit in this register in order to clear the corresponding bit in
3022 * was_error_vf_63_32 register. */
3023 #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c
3024 /* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
3025 * indicates that there was a completion with uncorrectable error for the
3026 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
3027 * was_error_vf_95_64_clr. */
3028 #define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074
3029 /* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
3030 * 1 to a bit in this register in order to clear the corresponding bit in
3031 * was_error_vf_95_64 register. */
3032 #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480
3033 /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
3035 #define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188
3036 /* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */
3037 #define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec
3038 /* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */
3039 #define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4
3040 /* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */
3041 #define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc
3042 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3043 #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8
3044 #define PRS_REG_A_PRSU_20 0x40134
3045 /* [R 8] debug only: CFC load request current credit. Transaction based. */
3046 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
3047 /* [R 8] debug only: CFC search request current credit. Transaction based. */
3048 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
3049 /* [RW 6] The initial credit for the search message to the CFC interface.
3050 Credit is transaction based. */
3051 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
3052 /* [RW 24] CID for port 0 if no match */
3053 #define PRS_REG_CID_PORT_0 0x400fc
3054 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
3055 load response is reset and packet type is 0. Used in packet start message
3057 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
3058 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
3059 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
3060 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
3061 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
3062 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
3063 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
3064 load response is set and packet type is 0. Used in packet start message
3066 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
3067 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
3068 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
3069 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
3070 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
3071 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
3072 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
3073 Used in packet start message to TCM. */
3074 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
3075 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
3076 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
3077 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
3078 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
3080 #define PRS_REG_CM_HDR_TYPE_0 0x40078
3081 #define PRS_REG_CM_HDR_TYPE_1 0x4007c
3082 #define PRS_REG_CM_HDR_TYPE_2 0x40080
3083 #define PRS_REG_CM_HDR_TYPE_3 0x40084
3084 #define PRS_REG_CM_HDR_TYPE_4 0x40088
3085 /* [RW 32] The CM header in case there was not a match on the connection */
3086 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8
3087 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
3088 #define PRS_REG_E1HOV_MODE 0x401c8
3089 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
3090 start message to TCM. */
3091 #define PRS_REG_EVENT_ID_1 0x40054
3092 #define PRS_REG_EVENT_ID_2 0x40058
3093 #define PRS_REG_EVENT_ID_3 0x4005c
3094 /* [RW 16] The Ethernet type value for FCoE */
3095 #define PRS_REG_FCOE_TYPE 0x401d0
3096 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
3097 load request message. */
3098 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
3099 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
3100 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
3101 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
3102 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
3103 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
3104 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
3105 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
3106 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
3107 * Ethernet header. */
3108 #define PRS_REG_HDRS_AFTER_BASIC 0x40238
3109 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
3110 * Ethernet header for port 0 packets. */
3111 #define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270
3112 #define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290
3113 /* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
3114 #define PRS_REG_HDRS_AFTER_TAG_0 0x40248
3115 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
3117 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280
3118 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0
3119 /* [RW 4] The increment value to send in the CFC load request message */
3120 #define PRS_REG_INC_VALUE 0x40048
3121 /* [RW 6] Bit-map indicating which headers must appear in the packet */
3122 #define PRS_REG_MUST_HAVE_HDRS 0x40254
3123 /* [RW 6] Bit-map indicating which headers must appear in the packet for
3125 #define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c
3126 #define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac
3127 #define PRS_REG_NIC_MODE 0x40138
3128 /* [RW 8] The 8-bit event ID for cases where there is no match on the
3129 connection. Used in packet start message to TCM. */
3130 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070
3131 /* [ST 24] The number of input CFC flush packets */
3132 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
3133 /* [ST 32] The number of cycles the Parser halted its operation since it
3134 could not allocate the next serial number */
3135 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
3136 /* [ST 24] The number of input packets */
3137 #define PRS_REG_NUM_OF_PACKETS 0x40124
3138 /* [ST 24] The number of input transparent flush packets */
3139 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
3140 /* [RW 8] Context region for received Ethernet packet with a match and
3141 packet type 0. Used in CFC load request message */
3142 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
3143 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
3144 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
3145 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
3146 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
3147 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
3148 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
3149 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
3150 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
3151 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
3152 /* [R 2] debug only: Number of pending requests for header parsing. */
3153 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
3154 /* [R 1] Interrupt register #0 read */
3155 #define PRS_REG_PRS_INT_STS 0x40188
3156 /* [RW 8] Parity mask register #0 read/write */
3157 #define PRS_REG_PRS_PRTY_MASK 0x401a4
3158 /* [R 8] Parity register #0 read */
3159 #define PRS_REG_PRS_PRTY_STS 0x40198
3160 /* [RC 8] Parity register #0 read clear */
3161 #define PRS_REG_PRS_PRTY_STS_CLR 0x4019c
3162 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
3164 #define PRS_REG_PURE_REGIONS 0x40024
3165 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
3166 serail number was released by SDM but cannot be used because a previous
3167 serial number was not released. */
3168 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
3169 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
3170 serail number was released by SDM but cannot be used because a previous
3171 serial number was not released. */
3172 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
3173 /* [R 4] debug only: SRC current credit. Transaction based. */
3174 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
3175 /* [RW 16] The Ethernet type value for L2 tag 0 */
3176 #define PRS_REG_TAG_ETHERTYPE_0 0x401d4
3177 /* [RW 4] The length of the info field for L2 tag 0. The length is between
3178 * 2B and 14B; in 2B granularity */
3179 #define PRS_REG_TAG_LEN_0 0x4022c
3180 /* [R 8] debug only: TCM current credit. Cycle based. */
3181 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160
3182 /* [R 8] debug only: TSDM current credit. Transaction based. */
3183 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
3184 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
3185 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
3186 #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
3187 #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23)
3188 #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
3189 #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
3190 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
3191 /* [R 6] Debug only: Number of used entries in the data FIFO */
3192 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
3193 /* [R 7] Debug only: Number of used entries in the header FIFO */
3194 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
3195 #define PXP2_REG_PGL_ADDR_88_F0 0x120534
3196 /* [R 32] GRC address for configuration access to PCIE config address 0x88.
3197 * any write to this PCIE address will cause a GRC write access to the
3198 * address that's in t this register */
3199 #define PXP2_REG_PGL_ADDR_88_F1 0x120544
3200 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538
3201 /* [R 32] GRC address for configuration access to PCIE config address 0x8c.
3202 * any write to this PCIE address will cause a GRC write access to the
3203 * address that's in t this register */
3204 #define PXP2_REG_PGL_ADDR_8C_F1 0x120548
3205 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c
3206 /* [R 32] GRC address for configuration access to PCIE config address 0x90.
3207 * any write to this PCIE address will cause a GRC write access to the
3208 * address that's in t this register */
3209 #define PXP2_REG_PGL_ADDR_90_F1 0x12054c
3210 #define PXP2_REG_PGL_ADDR_94_F0 0x120540
3211 /* [R 32] GRC address for configuration access to PCIE config address 0x94.
3212 * any write to this PCIE address will cause a GRC write access to the
3213 * address that's in t this register */
3214 #define PXP2_REG_PGL_ADDR_94_F1 0x120550
3215 #define PXP2_REG_PGL_CONTROL0 0x120490
3216 #define PXP2_REG_PGL_CONTROL1 0x120514
3217 #define PXP2_REG_PGL_DEBUG 0x120520
3218 /* [RW 32] third dword data of expansion rom request. this register is
3219 special. reading from it provides a vector outstanding read requests. if
3220 a bit is zero it means that a read request on the corresponding tag did
3221 not finish yet (not all completions have arrived for it) */
3222 #define PXP2_REG_PGL_EXP_ROM2 0x120808
3223 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
3224 its[15:0]-address */
3225 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
3226 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
3227 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
3228 #define PXP2_REG_PGL_INT_CSDM_3 0x120500
3229 #define PXP2_REG_PGL_INT_CSDM_4 0x120504
3230 #define PXP2_REG_PGL_INT_CSDM_5 0x120508
3231 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c
3232 #define PXP2_REG_PGL_INT_CSDM_7 0x120510
3233 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
3234 its[15:0]-address */
3235 #define PXP2_REG_PGL_INT_TSDM_0 0x120494
3236 #define PXP2_REG_PGL_INT_TSDM_1 0x120498
3237 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c
3238 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
3239 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
3240 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
3241 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
3242 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
3243 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
3244 its[15:0]-address */
3245 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4
3246 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8
3247 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc
3248 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0
3249 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4
3250 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8
3251 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc
3252 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0
3253 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
3254 its[15:0]-address */
3255 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
3256 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
3257 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
3258 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
3259 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
3260 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
3261 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
3262 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
3263 /* [RW 3] this field allows one function to pretend being another function
3264 when accessing any BAR mapped resource within the device. the value of
3265 the field is the number of the function that will be accessed
3266 effectively. after software write to this bit it must read it in order to
3267 know that the new value is updated */
3268 #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
3269 #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
3270 #define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
3271 #define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
3272 #define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
3273 #define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
3274 #define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
3275 #define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
3276 /* [R 1] this bit indicates that a read request was blocked because of
3277 bus_master_en was deasserted */
3278 #define PXP2_REG_PGL_READ_BLOCKED 0x120568
3279 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
3280 /* [R 18] debug only */
3281 #define PXP2_REG_PGL_TXW_CDTS 0x12052c
3282 /* [R 1] this bit indicates that a write request was blocked because of
3283 bus_master_en was deasserted */
3284 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
3285 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
3286 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
3287 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
3288 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
3289 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
3290 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
3291 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
3292 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
3293 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
3294 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
3295 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
3296 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0
3297 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
3298 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
3299 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4
3300 #define PXP2_REG_PSWRQ_BW_L28 0x120318
3301 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8
3302 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4
3303 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8
3304 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc
3305 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0
3306 #define PXP2_REG_PSWRQ_BW_RD 0x120324
3307 #define PXP2_REG_PSWRQ_BW_UB1 0x120238
3308 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
3309 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
3310 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c
3311 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
3312 #define PXP2_REG_PSWRQ_BW_UB3 0x120240
3313 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c
3314 #define PXP2_REG_PSWRQ_BW_UB7 0x120250
3315 #define PXP2_REG_PSWRQ_BW_UB8 0x120254
3316 #define PXP2_REG_PSWRQ_BW_UB9 0x120258
3317 #define PXP2_REG_PSWRQ_BW_WR 0x120328
3318 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
3319 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038
3320 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
3321 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
3322 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
3323 /* [RW 32] Interrupt mask register #0 read/write */
3324 #define PXP2_REG_PXP2_INT_MASK_0 0x120578
3325 /* [R 32] Interrupt register #0 read */
3326 #define PXP2_REG_PXP2_INT_STS_0 0x12056c
3327 #define PXP2_REG_PXP2_INT_STS_1 0x120608
3328 /* [RC 32] Interrupt register #0 read clear */
3329 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
3330 /* [RW 32] Parity mask register #0 read/write */
3331 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
3332 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
3333 /* [R 32] Parity register #0 read */
3334 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
3335 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
3336 /* [RC 32] Parity register #0 read clear */
3337 #define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580
3338 #define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590
3339 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
3340 indication about backpressure) */
3341 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424
3342 /* [R 8] Debug only: The blocks counter - number of unused block ids */
3343 #define PXP2_REG_RD_BLK_CNT 0x120418
3344 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
3345 Must be bigger than 6. Normally should not be changed. */
3346 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
3347 /* [RW 2] CDU byte swapping mode configuration for master read requests */
3348 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
3349 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
3350 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374
3351 /* [R 1] PSWRD internal memories initialization is done */
3352 #define PXP2_REG_RD_INIT_DONE 0x120370
3353 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3354 allocated for vq10 */
3355 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
3356 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3357 allocated for vq11 */
3358 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
3359 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3360 allocated for vq17 */
3361 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
3362 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3363 allocated for vq18 */
3364 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
3365 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3366 allocated for vq19 */
3367 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
3368 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3369 allocated for vq22 */
3370 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
3371 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3372 allocated for vq25 */
3373 #define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc
3374 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3375 allocated for vq6 */
3376 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
3377 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3378 allocated for vq9 */
3379 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
3380 /* [RW 2] PBF byte swapping mode configuration for master read requests */
3381 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
3382 /* [R 1] Debug only: Indication if delivery ports are idle */
3383 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
3384 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
3385 /* [RW 2] QM byte swapping mode configuration for master read requests */
3386 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
3387 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
3388 #define PXP2_REG_RD_SR_CNT 0x120414
3389 /* [RW 2] SRC byte swapping mode configuration for master read requests */
3390 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
3391 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
3392 be bigger than 1. Normally should not be changed. */
3393 #define PXP2_REG_RD_SR_NUM_CFG 0x120408
3394 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
3395 #define PXP2_REG_RD_START_INIT 0x12036c
3396 /* [RW 2] TM byte swapping mode configuration for master read requests */
3397 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
3398 /* [RW 10] Bandwidth addition to VQ0 write requests */
3399 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
3400 /* [RW 10] Bandwidth addition to VQ12 read requests */
3401 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
3402 /* [RW 10] Bandwidth addition to VQ13 read requests */
3403 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
3404 /* [RW 10] Bandwidth addition to VQ14 read requests */
3405 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
3406 /* [RW 10] Bandwidth addition to VQ15 read requests */
3407 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
3408 /* [RW 10] Bandwidth addition to VQ16 read requests */
3409 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
3410 /* [RW 10] Bandwidth addition to VQ17 read requests */
3411 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200
3412 /* [RW 10] Bandwidth addition to VQ18 read requests */
3413 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204
3414 /* [RW 10] Bandwidth addition to VQ19 read requests */
3415 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208
3416 /* [RW 10] Bandwidth addition to VQ20 read requests */
3417 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
3418 /* [RW 10] Bandwidth addition to VQ22 read requests */
3419 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210
3420 /* [RW 10] Bandwidth addition to VQ23 read requests */
3421 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214
3422 /* [RW 10] Bandwidth addition to VQ24 read requests */
3423 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218
3424 /* [RW 10] Bandwidth addition to VQ25 read requests */
3425 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
3426 /* [RW 10] Bandwidth addition to VQ26 read requests */
3427 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220
3428 /* [RW 10] Bandwidth addition to VQ27 read requests */
3429 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224
3430 /* [RW 10] Bandwidth addition to VQ4 read requests */
3431 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
3432 /* [RW 10] Bandwidth addition to VQ5 read requests */
3433 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
3434 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
3435 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac
3436 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
3437 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc
3438 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
3439 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0
3440 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
3441 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4
3442 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
3443 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8
3444 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
3445 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec
3446 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
3447 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0
3448 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
3449 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4
3450 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
3451 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8
3452 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
3453 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc
3454 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
3455 #define PXP2_REG_RQ_BW_RD_L22 0x120300
3456 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
3457 #define PXP2_REG_RQ_BW_RD_L23 0x120304
3458 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
3459 #define PXP2_REG_RQ_BW_RD_L24 0x120308
3460 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
3461 #define PXP2_REG_RQ_BW_RD_L25 0x12030c
3462 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
3463 #define PXP2_REG_RQ_BW_RD_L26 0x120310
3464 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
3465 #define PXP2_REG_RQ_BW_RD_L27 0x120314
3466 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
3467 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc
3468 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
3469 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0
3470 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
3471 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
3472 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
3473 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
3474 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
3475 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
3476 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
3477 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
3478 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
3479 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
3480 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
3481 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
3482 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
3483 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
3484 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
3485 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
3486 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
3487 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
3488 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
3489 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
3490 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
3491 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
3492 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
3493 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
3494 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
3495 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
3496 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
3497 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
3498 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
3499 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
3500 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
3501 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
3502 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
3503 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
3504 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
3505 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
3506 /* [RW 10] Bandwidth addition to VQ29 write requests */
3507 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
3508 /* [RW 10] Bandwidth addition to VQ30 write requests */
3509 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230
3510 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
3511 #define PXP2_REG_RQ_BW_WR_L29 0x12031c
3512 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
3513 #define PXP2_REG_RQ_BW_WR_L30 0x120320
3514 /* [RW 7] Bandwidth upper bound for VQ29 */
3515 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
3516 /* [RW 7] Bandwidth upper bound for VQ30 */
3517 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
3518 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
3519 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
3520 /* [RW 2] Endian mode for cdu */
3521 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
3522 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
3523 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
3524 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
3526 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018
3527 /* [R 1] 1' indicates that the requester has finished its internal
3529 #define PXP2_REG_RQ_CFG_DONE 0x1201b4
3530 /* [RW 2] Endian mode for debug */
3531 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
3532 /* [RW 1] When '1'; requests will enter input buffers but wont get out
3534 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
3535 /* [RW 4] Determines alignment of write SRs when a request is split into
3536 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3537 * aligned. 4 - 512B aligned. */
3538 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
3539 /* [RW 4] Determines alignment of read SRs when a request is split into
3540 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3541 * aligned. 4 - 512B aligned. */
3542 #define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c
3543 /* [RW 1] when set the new alignment method (E2) will be applied; when reset
3544 * the original alignment method (E1 E1H) will be applied */
3545 #define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930
3546 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
3548 #define PXP2_REG_RQ_ELT_DISABLE 0x12066c
3549 /* [RW 2] Endian mode for hc */
3550 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
3551 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
3552 compatibility needs; Note that different registers are used per mode */
3553 #define PXP2_REG_RQ_ILT_MODE 0x1205b4
3554 /* [WB 53] Onchip address table */
3555 #define PXP2_REG_RQ_ONCHIP_AT 0x122000
3556 /* [WB 53] Onchip address table - B0 */
3557 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
3558 /* [RW 13] Pending read limiter threshold; in Dwords */
3559 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c
3560 /* [RW 2] Endian mode for qm */
3561 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
3562 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
3563 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638
3564 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
3566 #define PXP2_REG_RQ_QM_P_SIZE 0x120050
3567 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
3568 #define PXP2_REG_RQ_RBC_DONE 0x1201b0
3569 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
3570 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3571 #define PXP2_REG_RQ_RD_MBS0 0x120160
3572 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
3573 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3574 #define PXP2_REG_RQ_RD_MBS1 0x120168
3575 /* [RW 2] Endian mode for src */
3576 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
3577 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
3578 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
3579 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
3581 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
3582 /* [RW 2] Endian mode for tm */
3583 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
3584 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
3585 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648
3586 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
3588 #define PXP2_REG_RQ_TM_P_SIZE 0x120034
3589 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
3590 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
3591 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
3592 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
3593 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
3594 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
3595 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */
3596 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
3597 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */
3598 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
3599 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */
3600 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
3601 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */
3602 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
3603 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */
3604 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
3605 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */
3606 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
3607 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */
3608 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
3609 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */
3610 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
3611 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */
3612 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
3613 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */
3614 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
3615 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */
3616 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
3617 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */
3618 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
3619 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */
3620 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
3621 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */
3622 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
3623 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */
3624 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
3625 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */
3626 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
3627 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */
3628 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
3629 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */
3630 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
3631 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */
3632 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
3633 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */
3634 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
3635 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */
3636 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
3637 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */
3638 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
3639 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */
3640 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
3641 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */
3642 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
3643 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
3644 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
3645 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */
3646 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
3647 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */
3648 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
3649 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */
3650 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
3651 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */
3652 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
3653 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */
3654 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
3655 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */
3656 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
3657 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
3658 001:256B; 010: 512B; */
3659 #define PXP2_REG_RQ_WR_MBS0 0x12015c
3660 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
3661 001:256B; 010: 512B; */
3662 #define PXP2_REG_RQ_WR_MBS1 0x120164
3663 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3664 buffer reaches this number has_payload will be asserted */
3665 #define PXP2_REG_WR_CDU_MPS 0x1205f0
3666 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3667 buffer reaches this number has_payload will be asserted */
3668 #define PXP2_REG_WR_CSDM_MPS 0x1205d0
3669 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3670 buffer reaches this number has_payload will be asserted */
3671 #define PXP2_REG_WR_DBG_MPS 0x1205e8
3672 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3673 buffer reaches this number has_payload will be asserted */
3674 #define PXP2_REG_WR_DMAE_MPS 0x1205ec
3675 /* [RW 10] if Number of entries in dmae fifo will be higher than this
3676 threshold then has_payload indication will be asserted; the default value
3677 should be equal to > write MBS size! */
3678 #define PXP2_REG_WR_DMAE_TH 0x120368
3679 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3680 buffer reaches this number has_payload will be asserted */
3681 #define PXP2_REG_WR_HC_MPS 0x1205c8
3682 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3683 buffer reaches this number has_payload will be asserted */
3684 #define PXP2_REG_WR_QM_MPS 0x1205dc
3685 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */
3686 #define PXP2_REG_WR_REV_MODE 0x120670
3687 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3688 buffer reaches this number has_payload will be asserted */
3689 #define PXP2_REG_WR_SRC_MPS 0x1205e4
3690 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3691 buffer reaches this number has_payload will be asserted */
3692 #define PXP2_REG_WR_TM_MPS 0x1205e0
3693 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3694 buffer reaches this number has_payload will be asserted */
3695 #define PXP2_REG_WR_TSDM_MPS 0x1205d4
3696 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this
3697 threshold then has_payload indication will be asserted; the default value
3698 should be equal to > write MBS size! */
3699 #define PXP2_REG_WR_USDMDP_TH 0x120348
3700 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3701 buffer reaches this number has_payload will be asserted */
3702 #define PXP2_REG_WR_USDM_MPS 0x1205cc
3703 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3704 buffer reaches this number has_payload will be asserted */
3705 #define PXP2_REG_WR_XSDM_MPS 0x1205d8
3706 /* [R 1] debug only: Indication if PSWHST arbiter is idle */
3707 #define PXP_REG_HST_ARB_IS_IDLE 0x103004
3708 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
3709 this client is waiting for the arbiter. */
3710 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
3711 /* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
3712 block. Should be used for close the gates. */
3713 #define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4
3714 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
3715 should update according to 'hst_discard_doorbells' register when the state
3717 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
3718 /* [RW 1] When 1; new internal writes arriving to the block are discarded.
3719 Should be used for close the gates. */
3720 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8
3721 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
3722 means this PSWHST is discarding inputs from this client. Each bit should
3723 update according to 'hst_discard_internal_writes' register when the state
3725 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
3726 /* [WB 160] Used for initialization of the inbound interrupts memory */
3727 #define PXP_REG_HST_INBOUND_INT 0x103800
3728 /* [RW 7] Indirect access to the permission table. The fields are : {Valid;
3731 #define PXP_REG_HST_ZONE_PERMISSION_TABLE 0x103400
3732 /* [RW 32] Interrupt mask register #0 read/write */
3733 #define PXP_REG_PXP_INT_MASK_0 0x103074
3734 #define PXP_REG_PXP_INT_MASK_1 0x103084
3735 /* [R 32] Interrupt register #0 read */
3736 #define PXP_REG_PXP_INT_STS_0 0x103068
3737 #define PXP_REG_PXP_INT_STS_1 0x103078
3738 /* [RC 32] Interrupt register #0 read clear */
3739 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
3740 #define PXP_REG_PXP_INT_STS_CLR_1 0x10307c
3741 /* [RW 27] Parity mask register #0 read/write */
3742 #define PXP_REG_PXP_PRTY_MASK 0x103094
3743 /* [R 26] Parity register #0 read */
3744 #define PXP_REG_PXP_PRTY_STS 0x103088
3745 /* [RC 27] Parity register #0 read clear */
3746 #define PXP_REG_PXP_PRTY_STS_CLR 0x10308c
3747 /* [RW 4] The activity counter initial increment value sent in the load
3749 #define QM_REG_ACTCTRINITVAL_0 0x168040
3750 #define QM_REG_ACTCTRINITVAL_1 0x168044
3751 #define QM_REG_ACTCTRINITVAL_2 0x168048
3752 #define QM_REG_ACTCTRINITVAL_3 0x16804c
3753 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3754 index I represents the physical queue number. The 12 lsbs are ignore and
3755 considered zero so practically there are only 20 bits in this register;
3757 #define QM_REG_BASEADDR 0x168900
3758 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3759 index I represents the physical queue number. The 12 lsbs are ignore and
3760 considered zero so practically there are only 20 bits in this register;
3762 #define QM_REG_BASEADDR_EXT_A 0x16e100
3763 /* [RW 16] The byte credit cost for each task. This value is for both ports */
3764 #define QM_REG_BYTECRDCOST 0x168234
3765 /* [RW 16] The initial byte credit value for both ports. */
3766 #define QM_REG_BYTECRDINITVAL 0x168238
3767 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3768 queue uses port 0 else it uses port 1; queues 31-0 */
3769 #define QM_REG_BYTECRDPORT_LSB 0x168228
3770 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3771 queue uses port 0 else it uses port 1; queues 95-64 */
3772 #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
3773 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3774 queue uses port 0 else it uses port 1; queues 63-32 */
3775 #define QM_REG_BYTECRDPORT_MSB 0x168224
3776 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3777 queue uses port 0 else it uses port 1; queues 127-96 */
3778 #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
3779 /* [RW 16] The byte credit value that if above the QM is considered almost
3781 #define QM_REG_BYTECREDITAFULLTHR 0x168094
3782 /* [RW 4] The initial credit for interface */
3783 #define QM_REG_CMINITCRD_0 0x1680cc
3784 #define QM_REG_BYTECRDCMDQ_0 0x16e6e8
3785 #define QM_REG_CMINITCRD_1 0x1680d0
3786 #define QM_REG_CMINITCRD_2 0x1680d4
3787 #define QM_REG_CMINITCRD_3 0x1680d8
3788 #define QM_REG_CMINITCRD_4 0x1680dc
3789 #define QM_REG_CMINITCRD_5 0x1680e0
3790 #define QM_REG_CMINITCRD_6 0x1680e4
3791 #define QM_REG_CMINITCRD_7 0x1680e8
3792 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
3794 #define QM_REG_CMINTEN 0x1680ec
3795 /* [RW 12] A bit vector which indicates which one of the queues are tied to
3797 #define QM_REG_CMINTVOQMASK_0 0x1681f4
3798 #define QM_REG_CMINTVOQMASK_1 0x1681f8
3799 #define QM_REG_CMINTVOQMASK_2 0x1681fc
3800 #define QM_REG_CMINTVOQMASK_3 0x168200
3801 #define QM_REG_CMINTVOQMASK_4 0x168204
3802 #define QM_REG_CMINTVOQMASK_5 0x168208
3803 #define QM_REG_CMINTVOQMASK_6 0x16820c
3804 #define QM_REG_CMINTVOQMASK_7 0x168210
3805 /* [RW 20] The number of connections divided by 16 which dictates the size
3806 of each queue which belongs to even function number. */
3807 #define QM_REG_CONNNUM_0 0x168020
3808 /* [R 6] Keep the fill level of the fifo from write client 4 */
3809 #define QM_REG_CQM_WRC_FIFOLVL 0x168018
3810 /* [RW 8] The context regions sent in the CFC load request */
3811 #define QM_REG_CTXREG_0 0x168030
3812 #define QM_REG_CTXREG_1 0x168034
3813 #define QM_REG_CTXREG_2 0x168038
3814 #define QM_REG_CTXREG_3 0x16803c
3815 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
3817 #define QM_REG_ENBYPVOQMASK 0x16823c
3818 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3819 physical queue uses the byte credit; queues 31-0 */
3820 #define QM_REG_ENBYTECRD_LSB 0x168220
3821 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3822 physical queue uses the byte credit; queues 95-64 */
3823 #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
3824 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3825 physical queue uses the byte credit; queues 63-32 */
3826 #define QM_REG_ENBYTECRD_MSB 0x16821c
3827 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3828 physical queue uses the byte credit; queues 127-96 */
3829 #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
3830 /* [RW 4] If cleared then the secondary interface will not be served by the
3832 #define QM_REG_ENSEC 0x1680f0
3834 #define QM_REG_FUNCNUMSEL_LSB 0x168230
3836 #define QM_REG_FUNCNUMSEL_MSB 0x16822c
3837 /* [RW 32] A mask register to mask the Almost empty signals which will not
3838 be use for the almost empty indication to the HW block; queues 31:0 */
3839 #define QM_REG_HWAEMPTYMASK_LSB 0x168218
3840 /* [RW 32] A mask register to mask the Almost empty signals which will not
3841 be use for the almost empty indication to the HW block; queues 95-64 */
3842 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
3843 /* [RW 32] A mask register to mask the Almost empty signals which will not
3844 be use for the almost empty indication to the HW block; queues 63:32 */
3845 #define QM_REG_HWAEMPTYMASK_MSB 0x168214
3846 /* [RW 32] A mask register to mask the Almost empty signals which will not
3847 be use for the almost empty indication to the HW block; queues 127-96 */
3848 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
3849 /* [RW 4] The number of outstanding request to CFC */
3850 #define QM_REG_OUTLDREQ 0x168804
3851 /* [RC 1] A flag to indicate that overflow error occurred in one of the
3853 #define QM_REG_OVFERROR 0x16805c
3854 /* [RC 7] the Q where the overflow occurs */
3855 #define QM_REG_OVFQNUM 0x168058
3856 /* [R 16] Pause state for physical queues 15-0 */
3857 #define QM_REG_PAUSESTATE0 0x168410
3858 /* [R 16] Pause state for physical queues 31-16 */
3859 #define QM_REG_PAUSESTATE1 0x168414
3860 /* [R 16] Pause state for physical queues 47-32 */
3861 #define QM_REG_PAUSESTATE2 0x16e684
3862 /* [R 16] Pause state for physical queues 63-48 */
3863 #define QM_REG_PAUSESTATE3 0x16e688
3864 /* [R 16] Pause state for physical queues 79-64 */
3865 #define QM_REG_PAUSESTATE4 0x16e68c
3866 /* [R 16] Pause state for physical queues 95-80 */
3867 #define QM_REG_PAUSESTATE5 0x16e690
3868 /* [R 16] Pause state for physical queues 111-96 */
3869 #define QM_REG_PAUSESTATE6 0x16e694
3870 /* [R 16] Pause state for physical queues 127-112 */
3871 #define QM_REG_PAUSESTATE7 0x16e698
3872 /* [RW 2] The PCI attributes field used in the PCI request. */
3873 #define QM_REG_PCIREQAT 0x168054
3874 #define QM_REG_PF_EN 0x16e70c
3875 /* [R 24] The number of tasks stored in the QM for the PF. only even
3876 * functions are valid in E2 (odd I registers will be hard wired to 0) */
3877 #define QM_REG_PF_USG_CNT_0 0x16e040
3878 /* [R 16] NOT USED */
3879 #define QM_REG_PORT0BYTECRD 0x168300
3880 /* [R 16] The byte credit of port 1 */
3881 #define QM_REG_PORT1BYTECRD 0x168304
3882 /* [RW 3] pci function number of queues 15-0 */
3883 #define QM_REG_PQ2PCIFUNC_0 0x16e6bc
3884 #define QM_REG_PQ2PCIFUNC_1 0x16e6c0
3885 #define QM_REG_PQ2PCIFUNC_2 0x16e6c4
3886 #define QM_REG_PQ2PCIFUNC_3 0x16e6c8
3887 #define QM_REG_PQ2PCIFUNC_4 0x16e6cc
3888 #define QM_REG_PQ2PCIFUNC_5 0x16e6d0
3889 #define QM_REG_PQ2PCIFUNC_6 0x16e6d4
3890 #define QM_REG_PQ2PCIFUNC_7 0x16e6d8
3891 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
3892 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3893 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3894 #define QM_REG_PTRTBL 0x168a00
3895 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
3896 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3897 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3898 #define QM_REG_PTRTBL_EXT_A 0x16e200
3899 /* [RW 2] Interrupt mask register #0 read/write */
3900 #define QM_REG_QM_INT_MASK 0x168444
3901 /* [R 2] Interrupt register #0 read */
3902 #define QM_REG_QM_INT_STS 0x168438
3903 /* [RW 12] Parity mask register #0 read/write */
3904 #define QM_REG_QM_PRTY_MASK 0x168454
3905 /* [R 12] Parity register #0 read */
3906 #define QM_REG_QM_PRTY_STS 0x168448
3907 /* [RC 12] Parity register #0 read clear */
3908 #define QM_REG_QM_PRTY_STS_CLR 0x16844c
3909 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
3910 #define QM_REG_QSTATUS_HIGH 0x16802c
3911 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */
3912 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
3913 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
3914 #define QM_REG_QSTATUS_LOW 0x168028
3915 /* [R 32] Current queues in pipeline: Queues from 64 to 95 */
3916 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
3917 /* [R 24] The number of tasks queued for each queue; queues 63-0 */
3918 #define QM_REG_QTASKCTR_0 0x168308
3919 /* [R 24] The number of tasks queued for each queue; queues 127-64 */
3920 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584
3921 /* [RW 4] Queue tied to VOQ */
3922 #define QM_REG_QVOQIDX_0 0x1680f4
3923 #define QM_REG_QVOQIDX_10 0x16811c
3924 #define QM_REG_QVOQIDX_100 0x16e49c
3925 #define QM_REG_QVOQIDX_101 0x16e4a0
3926 #define QM_REG_QVOQIDX_102 0x16e4a4
3927 #define QM_REG_QVOQIDX_103 0x16e4a8
3928 #define QM_REG_QVOQIDX_104 0x16e4ac
3929 #define QM_REG_QVOQIDX_105 0x16e4b0
3930 #define QM_REG_QVOQIDX_106 0x16e4b4
3931 #define QM_REG_QVOQIDX_107 0x16e4b8
3932 #define QM_REG_QVOQIDX_108 0x16e4bc
3933 #define QM_REG_QVOQIDX_109 0x16e4c0
3934 #define QM_REG_QVOQIDX_11 0x168120
3935 #define QM_REG_QVOQIDX_110 0x16e4c4
3936 #define QM_REG_QVOQIDX_111 0x16e4c8
3937 #define QM_REG_QVOQIDX_112 0x16e4cc
3938 #define QM_REG_QVOQIDX_113 0x16e4d0
3939 #define QM_REG_QVOQIDX_114 0x16e4d4
3940 #define QM_REG_QVOQIDX_115 0x16e4d8
3941 #define QM_REG_QVOQIDX_116 0x16e4dc
3942 #define QM_REG_QVOQIDX_117 0x16e4e0
3943 #define QM_REG_QVOQIDX_118 0x16e4e4
3944 #define QM_REG_QVOQIDX_119 0x16e4e8
3945 #define QM_REG_QVOQIDX_12 0x168124
3946 #define QM_REG_QVOQIDX_120 0x16e4ec
3947 #define QM_REG_QVOQIDX_121 0x16e4f0
3948 #define QM_REG_QVOQIDX_122 0x16e4f4
3949 #define QM_REG_QVOQIDX_123 0x16e4f8
3950 #define QM_REG_QVOQIDX_124 0x16e4fc
3951 #define QM_REG_QVOQIDX_125 0x16e500
3952 #define QM_REG_QVOQIDX_126 0x16e504
3953 #define QM_REG_QVOQIDX_127 0x16e508
3954 #define QM_REG_QVOQIDX_13 0x168128
3955 #define QM_REG_QVOQIDX_14 0x16812c
3956 #define QM_REG_QVOQIDX_15 0x168130
3957 #define QM_REG_QVOQIDX_16 0x168134
3958 #define QM_REG_QVOQIDX_17 0x168138
3959 #define QM_REG_QVOQIDX_21 0x168148
3960 #define QM_REG_QVOQIDX_22 0x16814c
3961 #define QM_REG_QVOQIDX_23 0x168150
3962 #define QM_REG_QVOQIDX_24 0x168154
3963 #define QM_REG_QVOQIDX_25 0x168158
3964 #define QM_REG_QVOQIDX_26 0x16815c
3965 #define QM_REG_QVOQIDX_27 0x168160
3966 #define QM_REG_QVOQIDX_28 0x168164
3967 #define QM_REG_QVOQIDX_29 0x168168
3968 #define QM_REG_QVOQIDX_30 0x16816c
3969 #define QM_REG_QVOQIDX_31 0x168170
3970 #define QM_REG_QVOQIDX_32 0x168174
3971 #define QM_REG_QVOQIDX_33 0x168178
3972 #define QM_REG_QVOQIDX_34 0x16817c
3973 #define QM_REG_QVOQIDX_35 0x168180
3974 #define QM_REG_QVOQIDX_36 0x168184
3975 #define QM_REG_QVOQIDX_37 0x168188
3976 #define QM_REG_QVOQIDX_38 0x16818c
3977 #define QM_REG_QVOQIDX_39 0x168190
3978 #define QM_REG_QVOQIDX_40 0x168194
3979 #define QM_REG_QVOQIDX_41 0x168198
3980 #define QM_REG_QVOQIDX_42 0x16819c
3981 #define QM_REG_QVOQIDX_43 0x1681a0
3982 #define QM_REG_QVOQIDX_44 0x1681a4
3983 #define QM_REG_QVOQIDX_45 0x1681a8
3984 #define QM_REG_QVOQIDX_46 0x1681ac
3985 #define QM_REG_QVOQIDX_47 0x1681b0
3986 #define QM_REG_QVOQIDX_48 0x1681b4
3987 #define QM_REG_QVOQIDX_49 0x1681b8
3988 #define QM_REG_QVOQIDX_5 0x168108
3989 #define QM_REG_QVOQIDX_50 0x1681bc
3990 #define QM_REG_QVOQIDX_51 0x1681c0
3991 #define QM_REG_QVOQIDX_52 0x1681c4
3992 #define QM_REG_QVOQIDX_53 0x1681c8
3993 #define QM_REG_QVOQIDX_54 0x1681cc
3994 #define QM_REG_QVOQIDX_55 0x1681d0
3995 #define QM_REG_QVOQIDX_56 0x1681d4
3996 #define QM_REG_QVOQIDX_57 0x1681d8
3997 #define QM_REG_QVOQIDX_58 0x1681dc
3998 #define QM_REG_QVOQIDX_59 0x1681e0
3999 #define QM_REG_QVOQIDX_6 0x16810c
4000 #define QM_REG_QVOQIDX_60 0x1681e4
4001 #define QM_REG_QVOQIDX_61 0x1681e8
4002 #define QM_REG_QVOQIDX_62 0x1681ec
4003 #define QM_REG_QVOQIDX_63 0x1681f0
4004 #define QM_REG_QVOQIDX_64 0x16e40c
4005 #define QM_REG_QVOQIDX_65 0x16e410
4006 #define QM_REG_QVOQIDX_69 0x16e420
4007 #define QM_REG_QVOQIDX_7 0x168110
4008 #define QM_REG_QVOQIDX_70 0x16e424
4009 #define QM_REG_QVOQIDX_71 0x16e428
4010 #define QM_REG_QVOQIDX_72 0x16e42c
4011 #define QM_REG_QVOQIDX_73 0x16e430
4012 #define QM_REG_QVOQIDX_74 0x16e434
4013 #define QM_REG_QVOQIDX_75 0x16e438
4014 #define QM_REG_QVOQIDX_76 0x16e43c
4015 #define QM_REG_QVOQIDX_77 0x16e440
4016 #define QM_REG_QVOQIDX_78 0x16e444
4017 #define QM_REG_QVOQIDX_79 0x16e448
4018 #define QM_REG_QVOQIDX_8 0x168114
4019 #define QM_REG_QVOQIDX_80 0x16e44c
4020 #define QM_REG_QVOQIDX_81 0x16e450
4021 #define QM_REG_QVOQIDX_85 0x16e460
4022 #define QM_REG_QVOQIDX_86 0x16e464
4023 #define QM_REG_QVOQIDX_87 0x16e468
4024 #define QM_REG_QVOQIDX_88 0x16e46c
4025 #define QM_REG_QVOQIDX_89 0x16e470
4026 #define QM_REG_QVOQIDX_9 0x168118
4027 #define QM_REG_QVOQIDX_90 0x16e474
4028 #define QM_REG_QVOQIDX_91 0x16e478
4029 #define QM_REG_QVOQIDX_92 0x16e47c
4030 #define QM_REG_QVOQIDX_93 0x16e480
4031 #define QM_REG_QVOQIDX_94 0x16e484
4032 #define QM_REG_QVOQIDX_95 0x16e488
4033 #define QM_REG_QVOQIDX_96 0x16e48c
4034 #define QM_REG_QVOQIDX_97 0x16e490
4035 #define QM_REG_QVOQIDX_98 0x16e494
4036 #define QM_REG_QVOQIDX_99 0x16e498
4037 /* [RW 1] Initialization bit command */
4038 #define QM_REG_SOFT_RESET 0x168428
4039 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
4040 #define QM_REG_TASKCRDCOST_0 0x16809c
4041 #define QM_REG_TASKCRDCOST_1 0x1680a0
4042 #define QM_REG_TASKCRDCOST_2 0x1680a4
4043 #define QM_REG_TASKCRDCOST_4 0x1680ac
4044 #define QM_REG_TASKCRDCOST_5 0x1680b0
4045 /* [R 6] Keep the fill level of the fifo from write client 3 */
4046 #define QM_REG_TQM_WRC_FIFOLVL 0x168010
4047 /* [R 6] Keep the fill level of the fifo from write client 2 */
4048 #define QM_REG_UQM_WRC_FIFOLVL 0x168008
4049 /* [RC 32] Credit update error register */
4050 #define QM_REG_VOQCRDERRREG 0x168408
4051 /* [R 16] The credit value for each VOQ */
4052 #define QM_REG_VOQCREDIT_0 0x1682d0
4053 #define QM_REG_VOQCREDIT_1 0x1682d4
4054 #define QM_REG_VOQCREDIT_4 0x1682e0
4055 /* [RW 16] The credit value that if above the QM is considered almost full */
4056 #define QM_REG_VOQCREDITAFULLTHR 0x168090
4057 /* [RW 16] The init and maximum credit for each VoQ */
4058 #define QM_REG_VOQINITCREDIT_0 0x168060
4059 #define QM_REG_VOQINITCREDIT_1 0x168064
4060 #define QM_REG_VOQINITCREDIT_2 0x168068
4061 #define QM_REG_VOQINITCREDIT_4 0x168070
4062 #define QM_REG_VOQINITCREDIT_5 0x168074
4063 /* [RW 1] The port of which VOQ belongs */
4064 #define QM_REG_VOQPORT_0 0x1682a0
4065 #define QM_REG_VOQPORT_1 0x1682a4
4066 #define QM_REG_VOQPORT_2 0x1682a8
4067 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4068 #define QM_REG_VOQQMASK_0_LSB 0x168240
4069 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4070 #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
4071 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4072 #define QM_REG_VOQQMASK_0_MSB 0x168244
4073 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4074 #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
4075 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4076 #define QM_REG_VOQQMASK_10_LSB 0x168290
4077 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4078 #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
4079 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4080 #define QM_REG_VOQQMASK_10_MSB 0x168294
4081 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4082 #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
4083 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4084 #define QM_REG_VOQQMASK_11_LSB 0x168298
4085 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4086 #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
4087 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4088 #define QM_REG_VOQQMASK_11_MSB 0x16829c
4089 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4090 #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
4091 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4092 #define QM_REG_VOQQMASK_1_LSB 0x168248
4093 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4094 #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
4095 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4096 #define QM_REG_VOQQMASK_1_MSB 0x16824c
4097 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4098 #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
4099 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4100 #define QM_REG_VOQQMASK_2_LSB 0x168250
4101 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4102 #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
4103 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4104 #define QM_REG_VOQQMASK_2_MSB 0x168254
4105 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4106 #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
4107 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4108 #define QM_REG_VOQQMASK_3_LSB 0x168258
4109 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4110 #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
4111 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4112 #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
4113 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4114 #define QM_REG_VOQQMASK_4_LSB 0x168260
4115 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4116 #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
4117 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4118 #define QM_REG_VOQQMASK_4_MSB 0x168264
4119 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4120 #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
4121 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4122 #define QM_REG_VOQQMASK_5_LSB 0x168268
4123 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4124 #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
4125 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4126 #define QM_REG_VOQQMASK_5_MSB 0x16826c
4127 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4128 #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
4129 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4130 #define QM_REG_VOQQMASK_6_LSB 0x168270
4131 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4132 #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
4133 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4134 #define QM_REG_VOQQMASK_6_MSB 0x168274
4135 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4136 #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
4137 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4138 #define QM_REG_VOQQMASK_7_LSB 0x168278
4139 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4140 #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
4141 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4142 #define QM_REG_VOQQMASK_7_MSB 0x16827c
4143 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4144 #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
4145 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4146 #define QM_REG_VOQQMASK_8_LSB 0x168280
4147 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4148 #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
4149 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4150 #define QM_REG_VOQQMASK_8_MSB 0x168284
4151 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4152 #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
4153 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4154 #define QM_REG_VOQQMASK_9_LSB 0x168288
4155 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4156 #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
4157 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4158 #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
4159 /* [RW 32] Wrr weights */
4160 #define QM_REG_WRRWEIGHTS_0 0x16880c
4161 #define QM_REG_WRRWEIGHTS_1 0x168810
4162 #define QM_REG_WRRWEIGHTS_10 0x168814
4163 #define QM_REG_WRRWEIGHTS_11 0x168818
4164 #define QM_REG_WRRWEIGHTS_12 0x16881c
4165 #define QM_REG_WRRWEIGHTS_13 0x168820
4166 #define QM_REG_WRRWEIGHTS_14 0x168824
4167 #define QM_REG_WRRWEIGHTS_15 0x168828
4168 #define QM_REG_WRRWEIGHTS_16 0x16e000
4169 #define QM_REG_WRRWEIGHTS_17 0x16e004
4170 #define QM_REG_WRRWEIGHTS_18 0x16e008
4171 #define QM_REG_WRRWEIGHTS_19 0x16e00c
4172 #define QM_REG_WRRWEIGHTS_2 0x16882c
4173 #define QM_REG_WRRWEIGHTS_20 0x16e010
4174 #define QM_REG_WRRWEIGHTS_21 0x16e014
4175 #define QM_REG_WRRWEIGHTS_22 0x16e018
4176 #define QM_REG_WRRWEIGHTS_23 0x16e01c
4177 #define QM_REG_WRRWEIGHTS_24 0x16e020
4178 #define QM_REG_WRRWEIGHTS_25 0x16e024
4179 #define QM_REG_WRRWEIGHTS_26 0x16e028
4180 #define QM_REG_WRRWEIGHTS_27 0x16e02c
4181 #define QM_REG_WRRWEIGHTS_28 0x16e030
4182 #define QM_REG_WRRWEIGHTS_29 0x16e034
4183 #define QM_REG_WRRWEIGHTS_3 0x168830
4184 #define QM_REG_WRRWEIGHTS_30 0x16e038
4185 #define QM_REG_WRRWEIGHTS_31 0x16e03c
4186 #define QM_REG_WRRWEIGHTS_4 0x168834
4187 #define QM_REG_WRRWEIGHTS_5 0x168838
4188 #define QM_REG_WRRWEIGHTS_6 0x16883c
4189 #define QM_REG_WRRWEIGHTS_7 0x168840
4190 #define QM_REG_WRRWEIGHTS_8 0x168844
4191 #define QM_REG_WRRWEIGHTS_9 0x168848
4192 /* [R 6] Keep the fill level of the fifo from write client 1 */
4193 #define QM_REG_XQM_WRC_FIFOLVL 0x168000
4194 /* [W 1] reset to parity interrupt */
4195 #define SEM_FAST_REG_PARITY_RST 0x18840
4196 #define SRC_REG_COUNTFREE0 0x40500
4197 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
4198 ports. If set the searcher support 8 functions. */
4199 #define SRC_REG_E1HMF_ENABLE 0x404cc
4200 #define SRC_REG_FIRSTFREE0 0x40510
4201 #define SRC_REG_KEYRSS0_0 0x40408
4202 #define SRC_REG_KEYRSS0_7 0x40424
4203 #define SRC_REG_KEYRSS1_9 0x40454
4204 #define SRC_REG_KEYSEARCH_0 0x40458
4205 #define SRC_REG_KEYSEARCH_1 0x4045c
4206 #define SRC_REG_KEYSEARCH_2 0x40460
4207 #define SRC_REG_KEYSEARCH_3 0x40464
4208 #define SRC_REG_KEYSEARCH_4 0x40468
4209 #define SRC_REG_KEYSEARCH_5 0x4046c
4210 #define SRC_REG_KEYSEARCH_6 0x40470
4211 #define SRC_REG_KEYSEARCH_7 0x40474
4212 #define SRC_REG_KEYSEARCH_8 0x40478
4213 #define SRC_REG_KEYSEARCH_9 0x4047c
4214 #define SRC_REG_LASTFREE0 0x40530
4215 #define SRC_REG_NUMBER_HASH_BITS0 0x40400
4216 /* [RW 1] Reset internal state machines. */
4217 #define SRC_REG_SOFT_RST 0x4049c
4218 /* [R 3] Interrupt register #0 read */
4219 #define SRC_REG_SRC_INT_STS 0x404ac
4220 /* [RW 3] Parity mask register #0 read/write */
4221 #define SRC_REG_SRC_PRTY_MASK 0x404c8
4222 /* [R 3] Parity register #0 read */
4223 #define SRC_REG_SRC_PRTY_STS 0x404bc
4224 /* [RC 3] Parity register #0 read clear */
4225 #define SRC_REG_SRC_PRTY_STS_CLR 0x404c0
4226 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
4227 #define TCM_REG_CAM_OCCUP 0x5017c
4228 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4229 disregarded; valid output is deasserted; all other signals are treated as
4230 usual; if 1 - normal activity. */
4231 #define TCM_REG_CDU_AG_RD_IFEN 0x50034
4232 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4233 are disregarded; all other signals are treated as usual; if 1 - normal
4235 #define TCM_REG_CDU_AG_WR_IFEN 0x50030
4236 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4237 disregarded; valid output is deasserted; all other signals are treated as
4238 usual; if 1 - normal activity. */
4239 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c
4240 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4241 input is disregarded; all other signals are treated as usual; if 1 -
4243 #define TCM_REG_CDU_SM_WR_IFEN 0x50038
4244 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4245 the initial credit value; read returns the current value of the credit
4246 counter. Must be initialized to 1 at start-up. */
4247 #define TCM_REG_CFC_INIT_CRD 0x50204
4248 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4249 weight 8 (the most prioritised); 1 stands for weight 1(least
4250 prioritised); 2 stands for weight 2; tc. */
4251 #define TCM_REG_CP_WEIGHT 0x500c0
4252 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4253 disregarded; acknowledge output is deasserted; all other signals are
4254 treated as usual; if 1 - normal activity. */
4255 #define TCM_REG_CSEM_IFEN 0x5002c
4256 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
4258 #define TCM_REG_CSEM_LENGTH_MIS 0x50174
4259 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4260 weight 8 (the most prioritised); 1 stands for weight 1(least
4261 prioritised); 2 stands for weight 2; tc. */
4262 #define TCM_REG_CSEM_WEIGHT 0x500bc
4263 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
4264 #define TCM_REG_ERR_EVNT_ID 0x500a0
4265 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4266 #define TCM_REG_ERR_TCM_HDR 0x5009c
4267 /* [RW 8] The Event ID for Timers expiration. */
4268 #define TCM_REG_EXPR_EVNT_ID 0x500a4
4269 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4270 writes the initial credit value; read returns the current value of the
4271 credit counter. Must be initialized to 64 at start-up. */
4272 #define TCM_REG_FIC0_INIT_CRD 0x5020c
4273 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4274 writes the initial credit value; read returns the current value of the
4275 credit counter. Must be initialized to 64 at start-up. */
4276 #define TCM_REG_FIC1_INIT_CRD 0x50210
4277 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4278 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
4279 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
4280 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
4281 #define TCM_REG_GR_ARB_TYPE 0x50114
4282 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4283 highest priority is 3. It is supposed that the Store channel is the
4284 compliment of the other 3 groups. */
4285 #define TCM_REG_GR_LD0_PR 0x5011c
4286 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4287 highest priority is 3. It is supposed that the Store channel is the
4288 compliment of the other 3 groups. */
4289 #define TCM_REG_GR_LD1_PR 0x50120
4290 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
4291 sent to STORM; for a specific connection type. The double REG-pairs are
4292 used to align to STORM context row size of 128 bits. The offset of these
4293 data in the STORM context is always 0. Index _i stands for the connection
4294 type (one of 16). */
4295 #define TCM_REG_N_SM_CTX_LD_0 0x50050
4296 #define TCM_REG_N_SM_CTX_LD_1 0x50054
4297 #define TCM_REG_N_SM_CTX_LD_2 0x50058
4298 #define TCM_REG_N_SM_CTX_LD_3 0x5005c
4299 #define TCM_REG_N_SM_CTX_LD_4 0x50060
4300 #define TCM_REG_N_SM_CTX_LD_5 0x50064
4301 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4302 acknowledge output is deasserted; all other signals are treated as usual;
4303 if 1 - normal activity. */
4304 #define TCM_REG_PBF_IFEN 0x50024
4305 /* [RC 1] Message length mismatch (relative to last indication) at the In#7
4307 #define TCM_REG_PBF_LENGTH_MIS 0x5016c
4308 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4309 weight 8 (the most prioritised); 1 stands for weight 1(least
4310 prioritised); 2 stands for weight 2; tc. */
4311 #define TCM_REG_PBF_WEIGHT 0x500b4
4312 #define TCM_REG_PHYS_QNUM0_0 0x500e0
4313 #define TCM_REG_PHYS_QNUM0_1 0x500e4
4314 #define TCM_REG_PHYS_QNUM1_0 0x500e8
4315 #define TCM_REG_PHYS_QNUM1_1 0x500ec
4316 #define TCM_REG_PHYS_QNUM2_0 0x500f0
4317 #define TCM_REG_PHYS_QNUM2_1 0x500f4
4318 #define TCM_REG_PHYS_QNUM3_0 0x500f8
4319 #define TCM_REG_PHYS_QNUM3_1 0x500fc
4320 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
4321 acknowledge output is deasserted; all other signals are treated as usual;
4322 if 1 - normal activity. */
4323 #define TCM_REG_PRS_IFEN 0x50020
4324 /* [RC 1] Message length mismatch (relative to last indication) at the In#6
4326 #define TCM_REG_PRS_LENGTH_MIS 0x50168
4327 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
4328 weight 8 (the most prioritised); 1 stands for weight 1(least
4329 prioritised); 2 stands for weight 2; tc. */
4330 #define TCM_REG_PRS_WEIGHT 0x500b0
4331 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4332 #define TCM_REG_STOP_EVNT_ID 0x500a8
4333 /* [RC 1] Message length mismatch (relative to last indication) at the STORM
4335 #define TCM_REG_STORM_LENGTH_MIS 0x50160
4336 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4337 disregarded; acknowledge output is deasserted; all other signals are
4338 treated as usual; if 1 - normal activity. */
4339 #define TCM_REG_STORM_TCM_IFEN 0x50010
4340 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4341 weight 8 (the most prioritised); 1 stands for weight 1(least
4342 prioritised); 2 stands for weight 2; tc. */
4343 #define TCM_REG_STORM_WEIGHT 0x500ac
4344 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4345 acknowledge output is deasserted; all other signals are treated as usual;
4346 if 1 - normal activity. */
4347 #define TCM_REG_TCM_CFC_IFEN 0x50040
4348 /* [RW 11] Interrupt mask register #0 read/write */
4349 #define TCM_REG_TCM_INT_MASK 0x501dc
4350 /* [R 11] Interrupt register #0 read */
4351 #define TCM_REG_TCM_INT_STS 0x501d0
4352 /* [RW 27] Parity mask register #0 read/write */
4353 #define TCM_REG_TCM_PRTY_MASK 0x501ec
4354 /* [R 27] Parity register #0 read */
4355 #define TCM_REG_TCM_PRTY_STS 0x501e0
4356 /* [RC 27] Parity register #0 read clear */
4357 #define TCM_REG_TCM_PRTY_STS_CLR 0x501e4
4358 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
4359 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4360 Is used to determine the number of the AG context REG-pairs written back;
4361 when the input message Reg1WbFlg isn't set. */
4362 #define TCM_REG_TCM_REG0_SZ 0x500d8
4363 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4364 disregarded; valid is deasserted; all other signals are treated as usual;
4365 if 1 - normal activity. */
4366 #define TCM_REG_TCM_STORM0_IFEN 0x50004
4367 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4368 disregarded; valid is deasserted; all other signals are treated as usual;
4369 if 1 - normal activity. */
4370 #define TCM_REG_TCM_STORM1_IFEN 0x50008
4371 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4372 disregarded; valid is deasserted; all other signals are treated as usual;
4373 if 1 - normal activity. */
4374 #define TCM_REG_TCM_TQM_IFEN 0x5000c
4375 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4376 #define TCM_REG_TCM_TQM_USE_Q 0x500d4
4377 /* [RW 28] The CM header for Timers expiration command. */
4378 #define TCM_REG_TM_TCM_HDR 0x50098
4379 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4380 disregarded; acknowledge output is deasserted; all other signals are
4381 treated as usual; if 1 - normal activity. */
4382 #define TCM_REG_TM_TCM_IFEN 0x5001c
4383 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4384 weight 8 (the most prioritised); 1 stands for weight 1(least
4385 prioritised); 2 stands for weight 2; tc. */
4386 #define TCM_REG_TM_WEIGHT 0x500d0
4387 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4388 the initial credit value; read returns the current value of the credit
4389 counter. Must be initialized to 32 at start-up. */
4390 #define TCM_REG_TQM_INIT_CRD 0x5021c
4391 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4392 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4393 prioritised); 2 stands for weight 2; tc. */
4394 #define TCM_REG_TQM_P_WEIGHT 0x500c8
4395 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4396 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4397 prioritised); 2 stands for weight 2; tc. */
4398 #define TCM_REG_TQM_S_WEIGHT 0x500cc
4399 /* [RW 28] The CM header value for QM request (primary). */
4400 #define TCM_REG_TQM_TCM_HDR_P 0x50090
4401 /* [RW 28] The CM header value for QM request (secondary). */
4402 #define TCM_REG_TQM_TCM_HDR_S 0x50094
4403 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4404 acknowledge output is deasserted; all other signals are treated as usual;
4405 if 1 - normal activity. */
4406 #define TCM_REG_TQM_TCM_IFEN 0x50014
4407 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4408 acknowledge output is deasserted; all other signals are treated as usual;
4409 if 1 - normal activity. */
4410 #define TCM_REG_TSDM_IFEN 0x50018
4411 /* [RC 1] Message length mismatch (relative to last indication) at the SDM
4413 #define TCM_REG_TSDM_LENGTH_MIS 0x50164
4414 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4415 weight 8 (the most prioritised); 1 stands for weight 1(least
4416 prioritised); 2 stands for weight 2; tc. */
4417 #define TCM_REG_TSDM_WEIGHT 0x500c4
4418 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4419 disregarded; acknowledge output is deasserted; all other signals are
4420 treated as usual; if 1 - normal activity. */
4421 #define TCM_REG_USEM_IFEN 0x50028
4422 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
4424 #define TCM_REG_USEM_LENGTH_MIS 0x50170
4425 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4426 weight 8 (the most prioritised); 1 stands for weight 1(least
4427 prioritised); 2 stands for weight 2; tc. */
4428 #define TCM_REG_USEM_WEIGHT 0x500b8
4429 /* [RW 21] Indirect access to the descriptor table of the XX protection
4430 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
4431 pointer; 20:16] - next pointer. */
4432 #define TCM_REG_XX_DESCR_TABLE 0x50280
4433 #define TCM_REG_XX_DESCR_TABLE_SIZE 29
4434 /* [R 6] Use to read the value of XX protection Free counter. */
4435 #define TCM_REG_XX_FREE 0x50178
4436 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4437 of the Input Stage XX protection buffer by the XX protection pending
4438 messages. Max credit available - 127.Write writes the initial credit
4439 value; read returns the current value of the credit counter. Must be
4440 initialized to 19 at start-up. */
4441 #define TCM_REG_XX_INIT_CRD 0x50220
4442 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
4444 #define TCM_REG_XX_MAX_LL_SZ 0x50044
4445 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4446 protection. ~tcm_registers_xx_free.xx_free is read on read. */
4447 #define TCM_REG_XX_MSG_NUM 0x50224
4448 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4449 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048
4450 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4451 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
4453 #define TCM_REG_XX_TABLE 0x50240
4454 /* [RW 4] Load value for cfc ac credit cnt. */
4455 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
4456 /* [RW 4] Load value for cfc cld credit cnt. */
4457 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
4458 /* [RW 8] Client0 context region. */
4459 #define TM_REG_CL0_CONT_REGION 0x164030
4460 /* [RW 8] Client1 context region. */
4461 #define TM_REG_CL1_CONT_REGION 0x164034
4462 /* [RW 8] Client2 context region. */
4463 #define TM_REG_CL2_CONT_REGION 0x164038
4464 /* [RW 2] Client in High priority client number. */
4465 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
4466 /* [RW 4] Load value for clout0 cred cnt. */
4467 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
4468 /* [RW 4] Load value for clout1 cred cnt. */
4469 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
4470 /* [RW 4] Load value for clout2 cred cnt. */
4471 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
4472 /* [RW 1] Enable client0 input. */
4473 #define TM_REG_EN_CL0_INPUT 0x164008
4474 /* [RW 1] Enable client1 input. */
4475 #define TM_REG_EN_CL1_INPUT 0x16400c
4476 /* [RW 1] Enable client2 input. */
4477 #define TM_REG_EN_CL2_INPUT 0x164010
4478 #define TM_REG_EN_LINEAR0_TIMER 0x164014
4479 /* [RW 1] Enable real time counter. */
4480 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8
4481 /* [RW 1] Enable for Timers state machines. */
4482 #define TM_REG_EN_TIMERS 0x164000
4483 /* [RW 4] Load value for expiration credit cnt. CFC max number of
4484 outstanding load requests for timers (expiration) context loading. */
4485 #define TM_REG_EXP_CRDCNT_VAL 0x164238
4486 /* [RW 32] Linear0 logic address. */
4487 #define TM_REG_LIN0_LOGIC_ADDR 0x164240
4488 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
4489 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
4490 /* [ST 16] Linear0 Number of scans counter. */
4491 #define TM_REG_LIN0_NUM_SCANS 0x1640a0
4492 /* [WB 64] Linear0 phy address. */
4493 #define TM_REG_LIN0_PHY_ADDR 0x164270
4494 /* [RW 1] Linear0 physical address valid. */
4495 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
4496 #define TM_REG_LIN0_SCAN_ON 0x1640d0
4497 /* [RW 24] Linear0 array scan timeout. */
4498 #define TM_REG_LIN0_SCAN_TIME 0x16403c
4499 #define TM_REG_LIN0_VNIC_UC 0x164128
4500 /* [RW 32] Linear1 logic address. */
4501 #define TM_REG_LIN1_LOGIC_ADDR 0x164250
4502 /* [WB 64] Linear1 phy address. */
4503 #define TM_REG_LIN1_PHY_ADDR 0x164280
4504 /* [RW 1] Linear1 physical address valid. */
4505 #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
4506 /* [RW 6] Linear timer set_clear fifo threshold. */
4507 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
4508 /* [RW 2] Load value for pci arbiter credit cnt. */
4509 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260
4510 /* [RW 20] The amount of hardware cycles for each timer tick. */
4511 #define TM_REG_TIMER_TICK_SIZE 0x16401c
4512 /* [RW 8] Timers Context region. */
4513 #define TM_REG_TM_CONTEXT_REGION 0x164044
4514 /* [RW 1] Interrupt mask register #0 read/write */
4515 #define TM_REG_TM_INT_MASK 0x1640fc
4516 /* [R 1] Interrupt register #0 read */
4517 #define TM_REG_TM_INT_STS 0x1640f0
4518 /* [RW 7] Parity mask register #0 read/write */
4519 #define TM_REG_TM_PRTY_MASK 0x16410c
4520 /* [RC 7] Parity register #0 read clear */
4521 #define TM_REG_TM_PRTY_STS_CLR 0x164104
4522 /* [RW 8] The event id for aggregated interrupt 0 */
4523 #define TSDM_REG_AGG_INT_EVENT_0 0x42038
4524 #define TSDM_REG_AGG_INT_EVENT_1 0x4203c
4525 #define TSDM_REG_AGG_INT_EVENT_2 0x42040
4526 #define TSDM_REG_AGG_INT_EVENT_3 0x42044
4527 #define TSDM_REG_AGG_INT_EVENT_4 0x42048
4528 /* [RW 1] The T bit for aggregated interrupt 0 */
4529 #define TSDM_REG_AGG_INT_T_0 0x420b8
4530 #define TSDM_REG_AGG_INT_T_1 0x420bc
4531 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4532 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008
4533 /* [RW 16] The maximum value of the completion counter #0 */
4534 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
4535 /* [RW 16] The maximum value of the completion counter #1 */
4536 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020
4537 /* [RW 16] The maximum value of the completion counter #2 */
4538 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024
4539 /* [RW 16] The maximum value of the completion counter #3 */
4540 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028
4541 /* [RW 13] The start address in the internal RAM for the completion
4543 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
4544 #define TSDM_REG_ENABLE_IN1 0x42238
4545 #define TSDM_REG_ENABLE_IN2 0x4223c
4546 #define TSDM_REG_ENABLE_OUT1 0x42240
4547 #define TSDM_REG_ENABLE_OUT2 0x42244
4548 /* [RW 4] The initial number of messages that can be sent to the pxp control
4549 interface without receiving any ACK. */
4550 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
4551 /* [ST 32] The number of ACK after placement messages received */
4552 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
4553 /* [ST 32] The number of packet end messages received from the parser */
4554 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
4555 /* [ST 32] The number of requests received from the pxp async if */
4556 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
4557 /* [ST 32] The number of commands received in queue 0 */
4558 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248
4559 /* [ST 32] The number of commands received in queue 10 */
4560 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
4561 /* [ST 32] The number of commands received in queue 11 */
4562 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270
4563 /* [ST 32] The number of commands received in queue 1 */
4564 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
4565 /* [ST 32] The number of commands received in queue 3 */
4566 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250
4567 /* [ST 32] The number of commands received in queue 4 */
4568 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254
4569 /* [ST 32] The number of commands received in queue 5 */
4570 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258
4571 /* [ST 32] The number of commands received in queue 6 */
4572 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
4573 /* [ST 32] The number of commands received in queue 7 */
4574 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260
4575 /* [ST 32] The number of commands received in queue 8 */
4576 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264
4577 /* [ST 32] The number of commands received in queue 9 */
4578 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268
4579 /* [RW 13] The start address in the internal RAM for the packet end message */
4580 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
4581 /* [RW 13] The start address in the internal RAM for queue counters */
4582 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
4583 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4584 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
4585 /* [R 1] parser fifo empty in sdm_sync block */
4586 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
4587 /* [R 1] parser serial fifo empty in sdm_sync block */
4588 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
4589 /* [RW 32] Tick for timer counter. Applicable only when
4590 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4591 #define TSDM_REG_TIMER_TICK 0x42000
4592 /* [RW 32] Interrupt mask register #0 read/write */
4593 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c
4594 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac
4595 /* [R 32] Interrupt register #0 read */
4596 #define TSDM_REG_TSDM_INT_STS_0 0x42290
4597 #define TSDM_REG_TSDM_INT_STS_1 0x422a0
4598 /* [RW 11] Parity mask register #0 read/write */
4599 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc
4600 /* [R 11] Parity register #0 read */
4601 #define TSDM_REG_TSDM_PRTY_STS 0x422b0
4602 /* [RC 11] Parity register #0 read clear */
4603 #define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4
4604 /* [RW 5] The number of time_slots in the arbitration cycle */
4605 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034
4606 /* [RW 3] The source that is associated with arbitration element 0. Source
4607 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4608 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4609 #define TSEM_REG_ARB_ELEMENT0 0x180020
4610 /* [RW 3] The source that is associated with arbitration element 1. Source
4611 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4612 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4613 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
4614 #define TSEM_REG_ARB_ELEMENT1 0x180024
4615 /* [RW 3] The source that is associated with arbitration element 2. Source
4616 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4617 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4618 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4619 and ~tsem_registers_arb_element1.arb_element1 */
4620 #define TSEM_REG_ARB_ELEMENT2 0x180028
4621 /* [RW 3] The source that is associated with arbitration element 3. Source
4622 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4623 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4624 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
4625 ~tsem_registers_arb_element1.arb_element1 and
4626 ~tsem_registers_arb_element2.arb_element2 */
4627 #define TSEM_REG_ARB_ELEMENT3 0x18002c
4628 /* [RW 3] The source that is associated with arbitration element 4. Source
4629 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4630 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4631 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4632 and ~tsem_registers_arb_element1.arb_element1 and
4633 ~tsem_registers_arb_element2.arb_element2 and
4634 ~tsem_registers_arb_element3.arb_element3 */
4635 #define TSEM_REG_ARB_ELEMENT4 0x180030
4636 #define TSEM_REG_ENABLE_IN 0x1800a4
4637 #define TSEM_REG_ENABLE_OUT 0x1800a8
4638 /* [RW 32] This address space contains all registers and memories that are
4639 placed in SEM_FAST block. The SEM_FAST registers are described in
4640 appendix B. In order to access the sem_fast registers the base address
4641 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4642 #define TSEM_REG_FAST_MEMORY 0x1a0000
4643 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4645 #define TSEM_REG_FIC0_DISABLE 0x180224
4646 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4648 #define TSEM_REG_FIC1_DISABLE 0x180234
4649 /* [RW 15] Interrupt table Read and write access to it is not possible in
4650 the middle of the work */
4651 #define TSEM_REG_INT_TABLE 0x180400
4652 /* [ST 24] Statistics register. The number of messages that entered through
4654 #define TSEM_REG_MSG_NUM_FIC0 0x180000
4655 /* [ST 24] Statistics register. The number of messages that entered through
4657 #define TSEM_REG_MSG_NUM_FIC1 0x180004
4658 /* [ST 24] Statistics register. The number of messages that were sent to
4660 #define TSEM_REG_MSG_NUM_FOC0 0x180008
4661 /* [ST 24] Statistics register. The number of messages that were sent to
4663 #define TSEM_REG_MSG_NUM_FOC1 0x18000c
4664 /* [ST 24] Statistics register. The number of messages that were sent to
4666 #define TSEM_REG_MSG_NUM_FOC2 0x180010
4667 /* [ST 24] Statistics register. The number of messages that were sent to
4669 #define TSEM_REG_MSG_NUM_FOC3 0x180014
4670 /* [RW 1] Disables input messages from the passive buffer May be updated
4671 during run_time by the microcode */
4672 #define TSEM_REG_PAS_DISABLE 0x18024c
4673 /* [WB 128] Debug only. Passive buffer memory */
4674 #define TSEM_REG_PASSIVE_BUFFER 0x181000
4675 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4676 #define TSEM_REG_PRAM 0x1c0000
4677 /* [R 8] Valid sleeping threads indication have bit per thread */
4678 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
4679 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4680 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
4681 /* [RW 8] List of free threads . There is a bit per thread. */
4682 #define TSEM_REG_THREADS_LIST 0x1802e4
4683 /* [RC 32] Parity register #0 read clear */
4684 #define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118
4685 #define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128
4686 /* [RW 3] The arbitration scheme of time_slot 0 */
4687 #define TSEM_REG_TS_0_AS 0x180038
4688 /* [RW 3] The arbitration scheme of time_slot 10 */
4689 #define TSEM_REG_TS_10_AS 0x180060
4690 /* [RW 3] The arbitration scheme of time_slot 11 */
4691 #define TSEM_REG_TS_11_AS 0x180064
4692 /* [RW 3] The arbitration scheme of time_slot 12 */
4693 #define TSEM_REG_TS_12_AS 0x180068
4694 /* [RW 3] The arbitration scheme of time_slot 13 */
4695 #define TSEM_REG_TS_13_AS 0x18006c
4696 /* [RW 3] The arbitration scheme of time_slot 14 */
4697 #define TSEM_REG_TS_14_AS 0x180070
4698 /* [RW 3] The arbitration scheme of time_slot 15 */
4699 #define TSEM_REG_TS_15_AS 0x180074
4700 /* [RW 3] The arbitration scheme of time_slot 16 */
4701 #define TSEM_REG_TS_16_AS 0x180078
4702 /* [RW 3] The arbitration scheme of time_slot 17 */
4703 #define TSEM_REG_TS_17_AS 0x18007c
4704 /* [RW 3] The arbitration scheme of time_slot 18 */
4705 #define TSEM_REG_TS_18_AS 0x180080
4706 /* [RW 3] The arbitration scheme of time_slot 1 */
4707 #define TSEM_REG_TS_1_AS 0x18003c
4708 /* [RW 3] The arbitration scheme of time_slot 2 */
4709 #define TSEM_REG_TS_2_AS 0x180040
4710 /* [RW 3] The arbitration scheme of time_slot 3 */
4711 #define TSEM_REG_TS_3_AS 0x180044
4712 /* [RW 3] The arbitration scheme of time_slot 4 */
4713 #define TSEM_REG_TS_4_AS 0x180048
4714 /* [RW 3] The arbitration scheme of time_slot 5 */
4715 #define TSEM_REG_TS_5_AS 0x18004c
4716 /* [RW 3] The arbitration scheme of time_slot 6 */
4717 #define TSEM_REG_TS_6_AS 0x180050
4718 /* [RW 3] The arbitration scheme of time_slot 7 */
4719 #define TSEM_REG_TS_7_AS 0x180054
4720 /* [RW 3] The arbitration scheme of time_slot 8 */
4721 #define TSEM_REG_TS_8_AS 0x180058
4722 /* [RW 3] The arbitration scheme of time_slot 9 */
4723 #define TSEM_REG_TS_9_AS 0x18005c
4724 /* [RW 32] Interrupt mask register #0 read/write */
4725 #define TSEM_REG_TSEM_INT_MASK_0 0x180100
4726 #define TSEM_REG_TSEM_INT_MASK_1 0x180110
4727 /* [R 32] Interrupt register #0 read */
4728 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4
4729 #define TSEM_REG_TSEM_INT_STS_1 0x180104
4730 /* [RW 32] Parity mask register #0 read/write */
4731 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
4732 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
4733 /* [R 32] Parity register #0 read */
4734 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114
4735 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124
4736 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4737 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4738 #define TSEM_REG_VFPF_ERR_NUM 0x180380
4739 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4740 * [10:8] of the address should be the offset within the accessed LCID
4741 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
4742 * LCID100. The RBC address should be 12'ha64. */
4743 #define UCM_REG_AG_CTX 0xe2000
4744 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4745 #define UCM_REG_CAM_OCCUP 0xe0170
4746 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4747 disregarded; valid output is deasserted; all other signals are treated as
4748 usual; if 1 - normal activity. */
4749 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038
4750 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4751 are disregarded; all other signals are treated as usual; if 1 - normal
4753 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034
4754 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4755 disregarded; valid output is deasserted; all other signals are treated as
4756 usual; if 1 - normal activity. */
4757 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040
4758 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4759 input is disregarded; all other signals are treated as usual; if 1 -
4761 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c
4762 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4763 the initial credit value; read returns the current value of the credit
4764 counter. Must be initialized to 1 at start-up. */
4765 #define UCM_REG_CFC_INIT_CRD 0xe0204
4766 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4767 weight 8 (the most prioritised); 1 stands for weight 1(least
4768 prioritised); 2 stands for weight 2; tc. */
4769 #define UCM_REG_CP_WEIGHT 0xe00c4
4770 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4771 disregarded; acknowledge output is deasserted; all other signals are
4772 treated as usual; if 1 - normal activity. */
4773 #define UCM_REG_CSEM_IFEN 0xe0028
4774 /* [RC 1] Set when the message length mismatch (relative to last indication)
4775 at the csem interface is detected. */
4776 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160
4777 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4778 weight 8 (the most prioritised); 1 stands for weight 1(least
4779 prioritised); 2 stands for weight 2; tc. */
4780 #define UCM_REG_CSEM_WEIGHT 0xe00b8
4781 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4782 disregarded; acknowledge output is deasserted; all other signals are
4783 treated as usual; if 1 - normal activity. */
4784 #define UCM_REG_DORQ_IFEN 0xe0030
4785 /* [RC 1] Set when the message length mismatch (relative to last indication)
4786 at the dorq interface is detected. */
4787 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168
4788 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4789 weight 8 (the most prioritised); 1 stands for weight 1(least
4790 prioritised); 2 stands for weight 2; tc. */
4791 #define UCM_REG_DORQ_WEIGHT 0xe00c0
4792 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
4793 #define UCM_REG_ERR_EVNT_ID 0xe00a4
4794 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4795 #define UCM_REG_ERR_UCM_HDR 0xe00a0
4796 /* [RW 8] The Event ID for Timers expiration. */
4797 #define UCM_REG_EXPR_EVNT_ID 0xe00a8
4798 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4799 writes the initial credit value; read returns the current value of the
4800 credit counter. Must be initialized to 64 at start-up. */
4801 #define UCM_REG_FIC0_INIT_CRD 0xe020c
4802 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4803 writes the initial credit value; read returns the current value of the
4804 credit counter. Must be initialized to 64 at start-up. */
4805 #define UCM_REG_FIC1_INIT_CRD 0xe0210
4806 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4807 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
4808 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
4809 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
4810 #define UCM_REG_GR_ARB_TYPE 0xe0144
4811 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4812 highest priority is 3. It is supposed that the Store channel group is
4813 compliment to the others. */
4814 #define UCM_REG_GR_LD0_PR 0xe014c
4815 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4816 highest priority is 3. It is supposed that the Store channel group is
4817 compliment to the others. */
4818 #define UCM_REG_GR_LD1_PR 0xe0150
4819 /* [RW 2] The queue index for invalidate counter flag decision. */
4820 #define UCM_REG_INV_CFLG_Q 0xe00e4
4821 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4822 sent to STORM; for a specific connection type. the double REG-pairs are
4823 used in order to align to STORM context row size of 128 bits. The offset
4824 of these data in the STORM context is always 0. Index _i stands for the
4825 connection type (one of 16). */
4826 #define UCM_REG_N_SM_CTX_LD_0 0xe0054
4827 #define UCM_REG_N_SM_CTX_LD_1 0xe0058
4828 #define UCM_REG_N_SM_CTX_LD_2 0xe005c
4829 #define UCM_REG_N_SM_CTX_LD_3 0xe0060
4830 #define UCM_REG_N_SM_CTX_LD_4 0xe0064
4831 #define UCM_REG_N_SM_CTX_LD_5 0xe0068
4832 #define UCM_REG_PHYS_QNUM0_0 0xe0110
4833 #define UCM_REG_PHYS_QNUM0_1 0xe0114
4834 #define UCM_REG_PHYS_QNUM1_0 0xe0118
4835 #define UCM_REG_PHYS_QNUM1_1 0xe011c
4836 #define UCM_REG_PHYS_QNUM2_0 0xe0120
4837 #define UCM_REG_PHYS_QNUM2_1 0xe0124
4838 #define UCM_REG_PHYS_QNUM3_0 0xe0128
4839 #define UCM_REG_PHYS_QNUM3_1 0xe012c
4840 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4841 #define UCM_REG_STOP_EVNT_ID 0xe00ac
4842 /* [RC 1] Set when the message length mismatch (relative to last indication)
4843 at the STORM interface is detected. */
4844 #define UCM_REG_STORM_LENGTH_MIS 0xe0154
4845 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4846 disregarded; acknowledge output is deasserted; all other signals are
4847 treated as usual; if 1 - normal activity. */
4848 #define UCM_REG_STORM_UCM_IFEN 0xe0010
4849 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4850 weight 8 (the most prioritised); 1 stands for weight 1(least
4851 prioritised); 2 stands for weight 2; tc. */
4852 #define UCM_REG_STORM_WEIGHT 0xe00b0
4853 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4854 writes the initial credit value; read returns the current value of the
4855 credit counter. Must be initialized to 4 at start-up. */
4856 #define UCM_REG_TM_INIT_CRD 0xe021c
4857 /* [RW 28] The CM header for Timers expiration command. */
4858 #define UCM_REG_TM_UCM_HDR 0xe009c
4859 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4860 disregarded; acknowledge output is deasserted; all other signals are
4861 treated as usual; if 1 - normal activity. */
4862 #define UCM_REG_TM_UCM_IFEN 0xe001c
4863 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4864 weight 8 (the most prioritised); 1 stands for weight 1(least
4865 prioritised); 2 stands for weight 2; tc. */
4866 #define UCM_REG_TM_WEIGHT 0xe00d4
4867 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4868 disregarded; acknowledge output is deasserted; all other signals are
4869 treated as usual; if 1 - normal activity. */
4870 #define UCM_REG_TSEM_IFEN 0xe0024
4871 /* [RC 1] Set when the message length mismatch (relative to last indication)
4872 at the tsem interface is detected. */
4873 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c
4874 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4875 weight 8 (the most prioritised); 1 stands for weight 1(least
4876 prioritised); 2 stands for weight 2; tc. */
4877 #define UCM_REG_TSEM_WEIGHT 0xe00b4
4878 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4879 acknowledge output is deasserted; all other signals are treated as usual;
4880 if 1 - normal activity. */
4881 #define UCM_REG_UCM_CFC_IFEN 0xe0044
4882 /* [RW 11] Interrupt mask register #0 read/write */
4883 #define UCM_REG_UCM_INT_MASK 0xe01d4
4884 /* [R 11] Interrupt register #0 read */
4885 #define UCM_REG_UCM_INT_STS 0xe01c8
4886 /* [RW 27] Parity mask register #0 read/write */
4887 #define UCM_REG_UCM_PRTY_MASK 0xe01e4
4888 /* [R 27] Parity register #0 read */
4889 #define UCM_REG_UCM_PRTY_STS 0xe01d8
4890 /* [RC 27] Parity register #0 read clear */
4891 #define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc
4892 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
4893 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4894 Is used to determine the number of the AG context REG-pairs written back;
4895 when the Reg1WbFlg isn't set. */
4896 #define UCM_REG_UCM_REG0_SZ 0xe00dc
4897 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4898 disregarded; valid is deasserted; all other signals are treated as usual;
4899 if 1 - normal activity. */
4900 #define UCM_REG_UCM_STORM0_IFEN 0xe0004
4901 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4902 disregarded; valid is deasserted; all other signals are treated as usual;
4903 if 1 - normal activity. */
4904 #define UCM_REG_UCM_STORM1_IFEN 0xe0008
4905 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4906 disregarded; acknowledge output is deasserted; all other signals are
4907 treated as usual; if 1 - normal activity. */
4908 #define UCM_REG_UCM_TM_IFEN 0xe0020
4909 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4910 disregarded; valid is deasserted; all other signals are treated as usual;
4911 if 1 - normal activity. */
4912 #define UCM_REG_UCM_UQM_IFEN 0xe000c
4913 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4914 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8
4915 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4916 the initial credit value; read returns the current value of the credit
4917 counter. Must be initialized to 32 at start-up. */
4918 #define UCM_REG_UQM_INIT_CRD 0xe0220
4919 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4920 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4921 prioritised); 2 stands for weight 2; tc. */
4922 #define UCM_REG_UQM_P_WEIGHT 0xe00cc
4923 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4924 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4925 prioritised); 2 stands for weight 2; tc. */
4926 #define UCM_REG_UQM_S_WEIGHT 0xe00d0
4927 /* [RW 28] The CM header value for QM request (primary). */
4928 #define UCM_REG_UQM_UCM_HDR_P 0xe0094
4929 /* [RW 28] The CM header value for QM request (secondary). */
4930 #define UCM_REG_UQM_UCM_HDR_S 0xe0098
4931 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4932 acknowledge output is deasserted; all other signals are treated as usual;
4933 if 1 - normal activity. */
4934 #define UCM_REG_UQM_UCM_IFEN 0xe0014
4935 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4936 acknowledge output is deasserted; all other signals are treated as usual;
4937 if 1 - normal activity. */
4938 #define UCM_REG_USDM_IFEN 0xe0018
4939 /* [RC 1] Set when the message length mismatch (relative to last indication)
4940 at the SDM interface is detected. */
4941 #define UCM_REG_USDM_LENGTH_MIS 0xe0158
4942 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4943 weight 8 (the most prioritised); 1 stands for weight 1(least
4944 prioritised); 2 stands for weight 2; tc. */
4945 #define UCM_REG_USDM_WEIGHT 0xe00c8
4946 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
4947 disregarded; acknowledge output is deasserted; all other signals are
4948 treated as usual; if 1 - normal activity. */
4949 #define UCM_REG_XSEM_IFEN 0xe002c
4950 /* [RC 1] Set when the message length mismatch (relative to last indication)
4951 at the xsem interface isdetected. */
4952 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164
4953 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
4954 weight 8 (the most prioritised); 1 stands for weight 1(least
4955 prioritised); 2 stands for weight 2; tc. */
4956 #define UCM_REG_XSEM_WEIGHT 0xe00bc
4957 /* [RW 20] Indirect access to the descriptor table of the XX protection
4958 mechanism. The fields are:[5:0] - message length; 14:6] - message
4959 pointer; 19:15] - next pointer. */
4960 #define UCM_REG_XX_DESCR_TABLE 0xe0280
4961 #define UCM_REG_XX_DESCR_TABLE_SIZE 27
4962 /* [R 6] Use to read the XX protection Free counter. */
4963 #define UCM_REG_XX_FREE 0xe016c
4964 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4965 of the Input Stage XX protection buffer by the XX protection pending
4966 messages. Write writes the initial credit value; read returns the current
4967 value of the credit counter. Must be initialized to 12 at start-up. */
4968 #define UCM_REG_XX_INIT_CRD 0xe0224
4969 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4970 protection. ~ucm_registers_xx_free.xx_free read on read. */
4971 #define UCM_REG_XX_MSG_NUM 0xe0228
4972 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4973 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
4974 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4975 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4977 #define UCM_REG_XX_TABLE 0xe0300
4978 #define UMAC_COMMAND_CONFIG_REG_HD_ENA (0x1<<10)
4979 #define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1<<28)
4980 #define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15)
4981 #define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24)
4982 #define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5)
4983 #define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1<<8)
4984 #define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4)
4985 #define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1)
4986 #define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13)
4987 #define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0)
4988 #define UMAC_REG_COMMAND_CONFIG 0x8
4989 /* [RW 16] This is the duration for which MAC must wait to go back to ACTIVE
4990 * state from LPI state when it receives packet for transmission. The
4991 * decrement unit is 1 micro-second. */
4992 #define UMAC_REG_EEE_WAKE_TIMER 0x6c
4993 /* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers
4994 * to bit 17 of the MAC address etc. */
4995 #define UMAC_REG_MAC_ADDR0 0xc
4996 /* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1
4997 * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved. */
4998 #define UMAC_REG_MAC_ADDR1 0x10
4999 /* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive
5000 * logic to check frames. */
5001 #define UMAC_REG_MAXFR 0x14
5002 #define UMAC_REG_UMAC_EEE_CTRL 0x64
5003 #define UMAC_UMAC_EEE_CTRL_REG_EEE_EN (0x1<<3)
5004 /* [RW 8] The event id for aggregated interrupt 0 */
5005 #define USDM_REG_AGG_INT_EVENT_0 0xc4038
5006 #define USDM_REG_AGG_INT_EVENT_1 0xc403c
5007 #define USDM_REG_AGG_INT_EVENT_2 0xc4040
5008 #define USDM_REG_AGG_INT_EVENT_4 0xc4048
5009 #define USDM_REG_AGG_INT_EVENT_5 0xc404c
5010 #define USDM_REG_AGG_INT_EVENT_6 0xc4050
5011 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
5012 or auto-mask-mode (1) */
5013 #define USDM_REG_AGG_INT_MODE_0 0xc41b8
5014 #define USDM_REG_AGG_INT_MODE_1 0xc41bc
5015 #define USDM_REG_AGG_INT_MODE_4 0xc41c8
5016 #define USDM_REG_AGG_INT_MODE_5 0xc41cc
5017 #define USDM_REG_AGG_INT_MODE_6 0xc41d0
5018 /* [RW 1] The T bit for aggregated interrupt 5 */
5019 #define USDM_REG_AGG_INT_T_5 0xc40cc
5020 #define USDM_REG_AGG_INT_T_6 0xc40d0
5021 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
5022 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008
5023 /* [RW 16] The maximum value of the completion counter #0 */
5024 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c
5025 /* [RW 16] The maximum value of the completion counter #1 */
5026 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020
5027 /* [RW 16] The maximum value of the completion counter #2 */
5028 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024
5029 /* [RW 16] The maximum value of the completion counter #3 */
5030 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028
5031 /* [RW 13] The start address in the internal RAM for the completion
5033 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
5034 #define USDM_REG_ENABLE_IN1 0xc4238
5035 #define USDM_REG_ENABLE_IN2 0xc423c
5036 #define USDM_REG_ENABLE_OUT1 0xc4240
5037 #define USDM_REG_ENABLE_OUT2 0xc4244
5038 /* [RW 4] The initial number of messages that can be sent to the pxp control
5039 interface without receiving any ACK. */
5040 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
5041 /* [ST 32] The number of ACK after placement messages received */
5042 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
5043 /* [ST 32] The number of packet end messages received from the parser */
5044 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
5045 /* [ST 32] The number of requests received from the pxp async if */
5046 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
5047 /* [ST 32] The number of commands received in queue 0 */
5048 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248
5049 /* [ST 32] The number of commands received in queue 10 */
5050 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270
5051 /* [ST 32] The number of commands received in queue 11 */
5052 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274
5053 /* [ST 32] The number of commands received in queue 1 */
5054 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c
5055 /* [ST 32] The number of commands received in queue 2 */
5056 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250
5057 /* [ST 32] The number of commands received in queue 3 */
5058 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254
5059 /* [ST 32] The number of commands received in queue 4 */
5060 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258
5061 /* [ST 32] The number of commands received in queue 5 */
5062 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c
5063 /* [ST 32] The number of commands received in queue 6 */
5064 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260
5065 /* [ST 32] The number of commands received in queue 7 */
5066 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264
5067 /* [ST 32] The number of commands received in queue 8 */
5068 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268
5069 /* [ST 32] The number of commands received in queue 9 */
5070 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c
5071 /* [RW 13] The start address in the internal RAM for the packet end message */
5072 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
5073 /* [RW 13] The start address in the internal RAM for queue counters */
5074 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
5075 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
5076 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
5077 /* [R 1] parser fifo empty in sdm_sync block */
5078 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
5079 /* [R 1] parser serial fifo empty in sdm_sync block */
5080 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
5081 /* [RW 32] Tick for timer counter. Applicable only when
5082 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
5083 #define USDM_REG_TIMER_TICK 0xc4000
5084 /* [RW 32] Interrupt mask register #0 read/write */
5085 #define USDM_REG_USDM_INT_MASK_0 0xc42a0
5086 #define USDM_REG_USDM_INT_MASK_1 0xc42b0
5087 /* [R 32] Interrupt register #0 read */
5088 #define USDM_REG_USDM_INT_STS_0 0xc4294
5089 #define USDM_REG_USDM_INT_STS_1 0xc42a4
5090 /* [RW 11] Parity mask register #0 read/write */
5091 #define USDM_REG_USDM_PRTY_MASK 0xc42c0
5092 /* [R 11] Parity register #0 read */
5093 #define USDM_REG_USDM_PRTY_STS 0xc42b4
5094 /* [RC 11] Parity register #0 read clear */
5095 #define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8
5096 /* [RW 5] The number of time_slots in the arbitration cycle */
5097 #define USEM_REG_ARB_CYCLE_SIZE 0x300034
5098 /* [RW 3] The source that is associated with arbitration element 0. Source
5099 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5100 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
5101 #define USEM_REG_ARB_ELEMENT0 0x300020
5102 /* [RW 3] The source that is associated with arbitration element 1. Source
5103 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5104 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5105 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
5106 #define USEM_REG_ARB_ELEMENT1 0x300024
5107 /* [RW 3] The source that is associated with arbitration element 2. Source
5108 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5109 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5110 Could not be equal to register ~usem_registers_arb_element0.arb_element0
5111 and ~usem_registers_arb_element1.arb_element1 */
5112 #define USEM_REG_ARB_ELEMENT2 0x300028
5113 /* [RW 3] The source that is associated with arbitration element 3. Source
5114 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5115 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5116 not be equal to register ~usem_registers_arb_element0.arb_element0 and
5117 ~usem_registers_arb_element1.arb_element1 and
5118 ~usem_registers_arb_element2.arb_element2 */
5119 #define USEM_REG_ARB_ELEMENT3 0x30002c
5120 /* [RW 3] The source that is associated with arbitration element 4. Source
5121 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5122 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5123 Could not be equal to register ~usem_registers_arb_element0.arb_element0
5124 and ~usem_registers_arb_element1.arb_element1 and
5125 ~usem_registers_arb_element2.arb_element2 and
5126 ~usem_registers_arb_element3.arb_element3 */
5127 #define USEM_REG_ARB_ELEMENT4 0x300030
5128 #define USEM_REG_ENABLE_IN 0x3000a4
5129 #define USEM_REG_ENABLE_OUT 0x3000a8
5130 /* [RW 32] This address space contains all registers and memories that are
5131 placed in SEM_FAST block. The SEM_FAST registers are described in
5132 appendix B. In order to access the sem_fast registers the base address
5133 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
5134 #define USEM_REG_FAST_MEMORY 0x320000
5135 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
5137 #define USEM_REG_FIC0_DISABLE 0x300224
5138 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
5140 #define USEM_REG_FIC1_DISABLE 0x300234
5141 /* [RW 15] Interrupt table Read and write access to it is not possible in
5142 the middle of the work */
5143 #define USEM_REG_INT_TABLE 0x300400
5144 /* [ST 24] Statistics register. The number of messages that entered through
5146 #define USEM_REG_MSG_NUM_FIC0 0x300000
5147 /* [ST 24] Statistics register. The number of messages that entered through
5149 #define USEM_REG_MSG_NUM_FIC1 0x300004
5150 /* [ST 24] Statistics register. The number of messages that were sent to
5152 #define USEM_REG_MSG_NUM_FOC0 0x300008
5153 /* [ST 24] Statistics register. The number of messages that were sent to
5155 #define USEM_REG_MSG_NUM_FOC1 0x30000c
5156 /* [ST 24] Statistics register. The number of messages that were sent to
5158 #define USEM_REG_MSG_NUM_FOC2 0x300010
5159 /* [ST 24] Statistics register. The number of messages that were sent to
5161 #define USEM_REG_MSG_NUM_FOC3 0x300014
5162 /* [RW 1] Disables input messages from the passive buffer May be updated
5163 during run_time by the microcode */
5164 #define USEM_REG_PAS_DISABLE 0x30024c
5165 /* [WB 128] Debug only. Passive buffer memory */
5166 #define USEM_REG_PASSIVE_BUFFER 0x302000
5167 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5168 #define USEM_REG_PRAM 0x340000
5169 /* [R 16] Valid sleeping threads indication have bit per thread */
5170 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c
5171 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
5172 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
5173 /* [RW 16] List of free threads . There is a bit per thread. */
5174 #define USEM_REG_THREADS_LIST 0x3002e4
5175 /* [RW 3] The arbitration scheme of time_slot 0 */
5176 #define USEM_REG_TS_0_AS 0x300038
5177 /* [RW 3] The arbitration scheme of time_slot 10 */
5178 #define USEM_REG_TS_10_AS 0x300060
5179 /* [RW 3] The arbitration scheme of time_slot 11 */
5180 #define USEM_REG_TS_11_AS 0x300064
5181 /* [RW 3] The arbitration scheme of time_slot 12 */
5182 #define USEM_REG_TS_12_AS 0x300068
5183 /* [RW 3] The arbitration scheme of time_slot 13 */
5184 #define USEM_REG_TS_13_AS 0x30006c
5185 /* [RW 3] The arbitration scheme of time_slot 14 */
5186 #define USEM_REG_TS_14_AS 0x300070
5187 /* [RW 3] The arbitration scheme of time_slot 15 */
5188 #define USEM_REG_TS_15_AS 0x300074
5189 /* [RW 3] The arbitration scheme of time_slot 16 */
5190 #define USEM_REG_TS_16_AS 0x300078
5191 /* [RW 3] The arbitration scheme of time_slot 17 */
5192 #define USEM_REG_TS_17_AS 0x30007c
5193 /* [RW 3] The arbitration scheme of time_slot 18 */
5194 #define USEM_REG_TS_18_AS 0x300080
5195 /* [RW 3] The arbitration scheme of time_slot 1 */
5196 #define USEM_REG_TS_1_AS 0x30003c
5197 /* [RW 3] The arbitration scheme of time_slot 2 */
5198 #define USEM_REG_TS_2_AS 0x300040
5199 /* [RW 3] The arbitration scheme of time_slot 3 */
5200 #define USEM_REG_TS_3_AS 0x300044
5201 /* [RW 3] The arbitration scheme of time_slot 4 */
5202 #define USEM_REG_TS_4_AS 0x300048
5203 /* [RW 3] The arbitration scheme of time_slot 5 */
5204 #define USEM_REG_TS_5_AS 0x30004c
5205 /* [RW 3] The arbitration scheme of time_slot 6 */
5206 #define USEM_REG_TS_6_AS 0x300050
5207 /* [RW 3] The arbitration scheme of time_slot 7 */
5208 #define USEM_REG_TS_7_AS 0x300054
5209 /* [RW 3] The arbitration scheme of time_slot 8 */
5210 #define USEM_REG_TS_8_AS 0x300058
5211 /* [RW 3] The arbitration scheme of time_slot 9 */
5212 #define USEM_REG_TS_9_AS 0x30005c
5213 /* [RW 32] Interrupt mask register #0 read/write */
5214 #define USEM_REG_USEM_INT_MASK_0 0x300110
5215 #define USEM_REG_USEM_INT_MASK_1 0x300120
5216 /* [R 32] Interrupt register #0 read */
5217 #define USEM_REG_USEM_INT_STS_0 0x300104
5218 #define USEM_REG_USEM_INT_STS_1 0x300114
5219 /* [RW 32] Parity mask register #0 read/write */
5220 #define USEM_REG_USEM_PRTY_MASK_0 0x300130
5221 #define USEM_REG_USEM_PRTY_MASK_1 0x300140
5222 /* [R 32] Parity register #0 read */
5223 #define USEM_REG_USEM_PRTY_STS_0 0x300124
5224 #define USEM_REG_USEM_PRTY_STS_1 0x300134
5225 /* [RC 32] Parity register #0 read clear */
5226 #define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128
5227 #define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138
5228 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5229 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5230 #define USEM_REG_VFPF_ERR_NUM 0x300380
5231 #define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0)
5232 #define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1)
5233 #define VFC_REG_MEMORIES_RST 0x1943c
5234 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
5235 * [12:8] of the address should be the offset within the accessed LCID
5236 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
5237 * LCID100. The RBC address should be 13'ha64. */
5238 #define XCM_REG_AG_CTX 0x28000
5239 /* [RW 2] The queue index for registration on Aux1 counter flag. */
5240 #define XCM_REG_AUX1_Q 0x20134
5241 /* [RW 2] Per each decision rule the queue index to register to. */
5242 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
5243 /* [R 5] Used to read the XX protection CAM occupancy counter. */
5244 #define XCM_REG_CAM_OCCUP 0x20244
5245 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
5246 disregarded; valid output is deasserted; all other signals are treated as
5247 usual; if 1 - normal activity. */
5248 #define XCM_REG_CDU_AG_RD_IFEN 0x20044
5249 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
5250 are disregarded; all other signals are treated as usual; if 1 - normal
5252 #define XCM_REG_CDU_AG_WR_IFEN 0x20040
5253 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
5254 disregarded; valid output is deasserted; all other signals are treated as
5255 usual; if 1 - normal activity. */
5256 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c
5257 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
5258 input is disregarded; all other signals are treated as usual; if 1 -
5260 #define XCM_REG_CDU_SM_WR_IFEN 0x20048
5261 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
5262 the initial credit value; read returns the current value of the credit
5263 counter. Must be initialized to 1 at start-up. */
5264 #define XCM_REG_CFC_INIT_CRD 0x20404
5265 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
5266 weight 8 (the most prioritised); 1 stands for weight 1(least
5267 prioritised); 2 stands for weight 2; tc. */
5268 #define XCM_REG_CP_WEIGHT 0x200dc
5269 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
5270 disregarded; acknowledge output is deasserted; all other signals are
5271 treated as usual; if 1 - normal activity. */
5272 #define XCM_REG_CSEM_IFEN 0x20028
5273 /* [RC 1] Set at message length mismatch (relative to last indication) at
5274 the csem interface. */
5275 #define XCM_REG_CSEM_LENGTH_MIS 0x20228
5276 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
5277 weight 8 (the most prioritised); 1 stands for weight 1(least
5278 prioritised); 2 stands for weight 2; tc. */
5279 #define XCM_REG_CSEM_WEIGHT 0x200c4
5280 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
5281 disregarded; acknowledge output is deasserted; all other signals are
5282 treated as usual; if 1 - normal activity. */
5283 #define XCM_REG_DORQ_IFEN 0x20030
5284 /* [RC 1] Set at message length mismatch (relative to last indication) at
5285 the dorq interface. */
5286 #define XCM_REG_DORQ_LENGTH_MIS 0x20230
5287 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
5288 weight 8 (the most prioritised); 1 stands for weight 1(least
5289 prioritised); 2 stands for weight 2; tc. */
5290 #define XCM_REG_DORQ_WEIGHT 0x200cc
5291 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
5292 #define XCM_REG_ERR_EVNT_ID 0x200b0
5293 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
5294 #define XCM_REG_ERR_XCM_HDR 0x200ac
5295 /* [RW 8] The Event ID for Timers expiration. */
5296 #define XCM_REG_EXPR_EVNT_ID 0x200b4
5297 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
5298 writes the initial credit value; read returns the current value of the
5299 credit counter. Must be initialized to 64 at start-up. */
5300 #define XCM_REG_FIC0_INIT_CRD 0x2040c
5301 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
5302 writes the initial credit value; read returns the current value of the
5303 credit counter. Must be initialized to 64 at start-up. */
5304 #define XCM_REG_FIC1_INIT_CRD 0x20410
5305 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
5306 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
5307 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
5308 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
5309 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
5310 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
5311 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
5312 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
5313 #define XCM_REG_GR_ARB_TYPE 0x2020c
5314 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
5315 highest priority is 3. It is supposed that the Channel group is the
5316 compliment of the other 3 groups. */
5317 #define XCM_REG_GR_LD0_PR 0x20214
5318 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
5319 highest priority is 3. It is supposed that the Channel group is the
5320 compliment of the other 3 groups. */
5321 #define XCM_REG_GR_LD1_PR 0x20218
5322 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
5323 disregarded; acknowledge output is deasserted; all other signals are
5324 treated as usual; if 1 - normal activity. */
5325 #define XCM_REG_NIG0_IFEN 0x20038
5326 /* [RC 1] Set at message length mismatch (relative to last indication) at
5327 the nig0 interface. */
5328 #define XCM_REG_NIG0_LENGTH_MIS 0x20238
5329 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
5330 weight 8 (the most prioritised); 1 stands for weight 1(least
5331 prioritised); 2 stands for weight 2; tc. */
5332 #define XCM_REG_NIG0_WEIGHT 0x200d4
5333 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
5334 disregarded; acknowledge output is deasserted; all other signals are
5335 treated as usual; if 1 - normal activity. */
5336 #define XCM_REG_NIG1_IFEN 0x2003c
5337 /* [RC 1] Set at message length mismatch (relative to last indication) at
5338 the nig1 interface. */
5339 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c
5340 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
5341 sent to STORM; for a specific connection type. The double REG-pairs are
5342 used in order to align to STORM context row size of 128 bits. The offset
5343 of these data in the STORM context is always 0. Index _i stands for the
5344 connection type (one of 16). */
5345 #define XCM_REG_N_SM_CTX_LD_0 0x20060
5346 #define XCM_REG_N_SM_CTX_LD_1 0x20064
5347 #define XCM_REG_N_SM_CTX_LD_2 0x20068
5348 #define XCM_REG_N_SM_CTX_LD_3 0x2006c
5349 #define XCM_REG_N_SM_CTX_LD_4 0x20070
5350 #define XCM_REG_N_SM_CTX_LD_5 0x20074
5351 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
5352 acknowledge output is deasserted; all other signals are treated as usual;
5353 if 1 - normal activity. */
5354 #define XCM_REG_PBF_IFEN 0x20034
5355 /* [RC 1] Set at message length mismatch (relative to last indication) at
5356 the pbf interface. */
5357 #define XCM_REG_PBF_LENGTH_MIS 0x20234
5358 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
5359 weight 8 (the most prioritised); 1 stands for weight 1(least
5360 prioritised); 2 stands for weight 2; tc. */
5361 #define XCM_REG_PBF_WEIGHT 0x200d0
5362 #define XCM_REG_PHYS_QNUM3_0 0x20100
5363 #define XCM_REG_PHYS_QNUM3_1 0x20104
5364 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
5365 #define XCM_REG_STOP_EVNT_ID 0x200b8
5366 /* [RC 1] Set at message length mismatch (relative to last indication) at
5367 the STORM interface. */
5368 #define XCM_REG_STORM_LENGTH_MIS 0x2021c
5369 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
5370 weight 8 (the most prioritised); 1 stands for weight 1(least
5371 prioritised); 2 stands for weight 2; tc. */
5372 #define XCM_REG_STORM_WEIGHT 0x200bc
5373 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5374 disregarded; acknowledge output is deasserted; all other signals are
5375 treated as usual; if 1 - normal activity. */
5376 #define XCM_REG_STORM_XCM_IFEN 0x20010
5377 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
5378 writes the initial credit value; read returns the current value of the
5379 credit counter. Must be initialized to 4 at start-up. */
5380 #define XCM_REG_TM_INIT_CRD 0x2041c
5381 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
5382 weight 8 (the most prioritised); 1 stands for weight 1(least
5383 prioritised); 2 stands for weight 2; tc. */
5384 #define XCM_REG_TM_WEIGHT 0x200ec
5385 /* [RW 28] The CM header for Timers expiration command. */
5386 #define XCM_REG_TM_XCM_HDR 0x200a8
5387 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5388 disregarded; acknowledge output is deasserted; all other signals are
5389 treated as usual; if 1 - normal activity. */
5390 #define XCM_REG_TM_XCM_IFEN 0x2001c
5391 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5392 disregarded; acknowledge output is deasserted; all other signals are
5393 treated as usual; if 1 - normal activity. */
5394 #define XCM_REG_TSEM_IFEN 0x20024
5395 /* [RC 1] Set at message length mismatch (relative to last indication) at
5396 the tsem interface. */
5397 #define XCM_REG_TSEM_LENGTH_MIS 0x20224
5398 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
5399 weight 8 (the most prioritised); 1 stands for weight 1(least
5400 prioritised); 2 stands for weight 2; tc. */
5401 #define XCM_REG_TSEM_WEIGHT 0x200c0
5402 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
5403 #define XCM_REG_UNA_GT_NXT_Q 0x20120
5404 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
5405 disregarded; acknowledge output is deasserted; all other signals are
5406 treated as usual; if 1 - normal activity. */
5407 #define XCM_REG_USEM_IFEN 0x2002c
5408 /* [RC 1] Message length mismatch (relative to last indication) at the usem
5410 #define XCM_REG_USEM_LENGTH_MIS 0x2022c
5411 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
5412 weight 8 (the most prioritised); 1 stands for weight 1(least
5413 prioritised); 2 stands for weight 2; tc. */
5414 #define XCM_REG_USEM_WEIGHT 0x200c8
5415 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4
5416 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8
5417 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc
5418 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0
5419 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
5420 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
5421 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
5422 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
5423 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
5424 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
5425 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
5426 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
5427 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5428 acknowledge output is deasserted; all other signals are treated as usual;
5429 if 1 - normal activity. */
5430 #define XCM_REG_XCM_CFC_IFEN 0x20050
5431 /* [RW 14] Interrupt mask register #0 read/write */
5432 #define XCM_REG_XCM_INT_MASK 0x202b4
5433 /* [R 14] Interrupt register #0 read */
5434 #define XCM_REG_XCM_INT_STS 0x202a8
5435 /* [RW 30] Parity mask register #0 read/write */
5436 #define XCM_REG_XCM_PRTY_MASK 0x202c4
5437 /* [R 30] Parity register #0 read */
5438 #define XCM_REG_XCM_PRTY_STS 0x202b8
5439 /* [RC 30] Parity register #0 read clear */
5440 #define XCM_REG_XCM_PRTY_STS_CLR 0x202bc
5442 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
5443 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
5444 Is used to determine the number of the AG context REG-pairs written back;
5445 when the Reg1WbFlg isn't set. */
5446 #define XCM_REG_XCM_REG0_SZ 0x200f4
5447 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5448 disregarded; valid is deasserted; all other signals are treated as usual;
5449 if 1 - normal activity. */
5450 #define XCM_REG_XCM_STORM0_IFEN 0x20004
5451 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5452 disregarded; valid is deasserted; all other signals are treated as usual;
5453 if 1 - normal activity. */
5454 #define XCM_REG_XCM_STORM1_IFEN 0x20008
5455 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5456 disregarded; acknowledge output is deasserted; all other signals are
5457 treated as usual; if 1 - normal activity. */
5458 #define XCM_REG_XCM_TM_IFEN 0x20020
5459 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5460 disregarded; valid is deasserted; all other signals are treated as usual;
5461 if 1 - normal activity. */
5462 #define XCM_REG_XCM_XQM_IFEN 0x2000c
5463 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
5464 #define XCM_REG_XCM_XQM_USE_Q 0x200f0
5465 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
5466 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
5467 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
5468 the initial credit value; read returns the current value of the credit
5469 counter. Must be initialized to 32 at start-up. */
5470 #define XCM_REG_XQM_INIT_CRD 0x20420
5471 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
5472 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5473 prioritised); 2 stands for weight 2; tc. */
5474 #define XCM_REG_XQM_P_WEIGHT 0x200e4
5475 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
5476 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5477 prioritised); 2 stands for weight 2; tc. */
5478 #define XCM_REG_XQM_S_WEIGHT 0x200e8
5479 /* [RW 28] The CM header value for QM request (primary). */
5480 #define XCM_REG_XQM_XCM_HDR_P 0x200a0
5481 /* [RW 28] The CM header value for QM request (secondary). */
5482 #define XCM_REG_XQM_XCM_HDR_S 0x200a4
5483 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5484 acknowledge output is deasserted; all other signals are treated as usual;
5485 if 1 - normal activity. */
5486 #define XCM_REG_XQM_XCM_IFEN 0x20014
5487 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5488 acknowledge output is deasserted; all other signals are treated as usual;
5489 if 1 - normal activity. */
5490 #define XCM_REG_XSDM_IFEN 0x20018
5491 /* [RC 1] Set at message length mismatch (relative to last indication) at
5492 the SDM interface. */
5493 #define XCM_REG_XSDM_LENGTH_MIS 0x20220
5494 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
5495 weight 8 (the most prioritised); 1 stands for weight 1(least
5496 prioritised); 2 stands for weight 2; tc. */
5497 #define XCM_REG_XSDM_WEIGHT 0x200e0
5498 /* [RW 17] Indirect access to the descriptor table of the XX protection
5499 mechanism. The fields are: [5:0] - message length; 11:6] - message
5500 pointer; 16:12] - next pointer. */
5501 #define XCM_REG_XX_DESCR_TABLE 0x20480
5502 #define XCM_REG_XX_DESCR_TABLE_SIZE 32
5503 /* [R 6] Used to read the XX protection Free counter. */
5504 #define XCM_REG_XX_FREE 0x20240
5505 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
5506 of the Input Stage XX protection buffer by the XX protection pending
5507 messages. Max credit available - 3.Write writes the initial credit value;
5508 read returns the current value of the credit counter. Must be initialized
5509 to 2 at start-up. */
5510 #define XCM_REG_XX_INIT_CRD 0x20424
5511 /* [RW 6] The maximum number of pending messages; which may be stored in XX
5512 protection. ~xcm_registers_xx_free.xx_free read on read. */
5513 #define XCM_REG_XX_MSG_NUM 0x20428
5514 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
5515 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058
5516 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0)
5517 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1)
5518 #define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1<<2)
5519 #define XMAC_CTRL_REG_RX_EN (0x1<<1)
5520 #define XMAC_CTRL_REG_SOFT_RESET (0x1<<6)
5521 #define XMAC_CTRL_REG_TX_EN (0x1<<0)
5522 #define XMAC_CTRL_REG_XLGMII_ALIGN_ENB (0x1<<7)
5523 #define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18)
5524 #define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17)
5525 #define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON (0x1<<1)
5526 #define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0)
5527 #define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3)
5528 #define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4)
5529 #define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5)
5530 #define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60
5531 #define XMAC_REG_CTRL 0
5532 /* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
5533 * packets transmitted by the MAC */
5534 #define XMAC_REG_CTRL_SA_HI 0x2c
5535 /* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
5536 * packets transmitted by the MAC */
5537 #define XMAC_REG_CTRL_SA_LO 0x28
5538 #define XMAC_REG_EEE_CTRL 0xd8
5539 #define XMAC_REG_EEE_TIMERS_HI 0xe4
5540 #define XMAC_REG_PAUSE_CTRL 0x68
5541 #define XMAC_REG_PFC_CTRL 0x70
5542 #define XMAC_REG_PFC_CTRL_HI 0x74
5543 #define XMAC_REG_RX_LSS_CTRL 0x50
5544 #define XMAC_REG_RX_LSS_STATUS 0x58
5545 /* [RW 14] Maximum packet size in receive direction; exclusive of preamble &
5546 * CRC in strip mode */
5547 #define XMAC_REG_RX_MAX_SIZE 0x40
5548 #define XMAC_REG_TX_CTRL 0x20
5549 #define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE (0x1<<0)
5550 #define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE (0x1<<1)
5551 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
5552 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
5554 #define XCM_REG_XX_TABLE 0x20500
5555 /* [RW 8] The event id for aggregated interrupt 0 */
5556 #define XSDM_REG_AGG_INT_EVENT_0 0x166038
5557 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c
5558 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
5559 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
5560 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
5561 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
5562 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
5563 #define XSDM_REG_AGG_INT_EVENT_2 0x166040
5564 #define XSDM_REG_AGG_INT_EVENT_3 0x166044
5565 #define XSDM_REG_AGG_INT_EVENT_4 0x166048
5566 #define XSDM_REG_AGG_INT_EVENT_5 0x16604c
5567 #define XSDM_REG_AGG_INT_EVENT_6 0x166050
5568 #define XSDM_REG_AGG_INT_EVENT_7 0x166054
5569 #define XSDM_REG_AGG_INT_EVENT_8 0x166058
5570 #define XSDM_REG_AGG_INT_EVENT_9 0x16605c
5571 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
5572 or auto-mask-mode (1) */
5573 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8
5574 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc
5575 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
5576 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008
5577 /* [RW 16] The maximum value of the completion counter #0 */
5578 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
5579 /* [RW 16] The maximum value of the completion counter #1 */
5580 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020
5581 /* [RW 16] The maximum value of the completion counter #2 */
5582 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024
5583 /* [RW 16] The maximum value of the completion counter #3 */
5584 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028
5585 /* [RW 13] The start address in the internal RAM for the completion
5587 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
5588 #define XSDM_REG_ENABLE_IN1 0x166238
5589 #define XSDM_REG_ENABLE_IN2 0x16623c
5590 #define XSDM_REG_ENABLE_OUT1 0x166240
5591 #define XSDM_REG_ENABLE_OUT2 0x166244
5592 /* [RW 4] The initial number of messages that can be sent to the pxp control
5593 interface without receiving any ACK. */
5594 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
5595 /* [ST 32] The number of ACK after placement messages received */
5596 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
5597 /* [ST 32] The number of packet end messages received from the parser */
5598 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
5599 /* [ST 32] The number of requests received from the pxp async if */
5600 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
5601 /* [ST 32] The number of commands received in queue 0 */
5602 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248
5603 /* [ST 32] The number of commands received in queue 10 */
5604 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
5605 /* [ST 32] The number of commands received in queue 11 */
5606 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270
5607 /* [ST 32] The number of commands received in queue 1 */
5608 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
5609 /* [ST 32] The number of commands received in queue 3 */
5610 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250
5611 /* [ST 32] The number of commands received in queue 4 */
5612 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254
5613 /* [ST 32] The number of commands received in queue 5 */
5614 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258
5615 /* [ST 32] The number of commands received in queue 6 */
5616 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
5617 /* [ST 32] The number of commands received in queue 7 */
5618 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260
5619 /* [ST 32] The number of commands received in queue 8 */
5620 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264
5621 /* [ST 32] The number of commands received in queue 9 */
5622 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268
5623 /* [RW 13] The start address in the internal RAM for queue counters */
5624 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
5625 /* [W 17] Generate an operation after completion; bit-16 is
5626 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and
5627 * bits 4:0 are the T124Param[4:0] */
5628 #define XSDM_REG_OPERATION_GEN 0x1664c4
5629 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
5630 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
5631 /* [R 1] parser fifo empty in sdm_sync block */
5632 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
5633 /* [R 1] parser serial fifo empty in sdm_sync block */
5634 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
5635 /* [RW 32] Tick for timer counter. Applicable only when
5636 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
5637 #define XSDM_REG_TIMER_TICK 0x166000
5638 /* [RW 32] Interrupt mask register #0 read/write */
5639 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c
5640 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
5641 /* [R 32] Interrupt register #0 read */
5642 #define XSDM_REG_XSDM_INT_STS_0 0x166290
5643 #define XSDM_REG_XSDM_INT_STS_1 0x1662a0
5644 /* [RW 11] Parity mask register #0 read/write */
5645 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
5646 /* [R 11] Parity register #0 read */
5647 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0
5648 /* [RC 11] Parity register #0 read clear */
5649 #define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4
5650 /* [RW 5] The number of time_slots in the arbitration cycle */
5651 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034
5652 /* [RW 3] The source that is associated with arbitration element 0. Source
5653 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5654 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
5655 #define XSEM_REG_ARB_ELEMENT0 0x280020
5656 /* [RW 3] The source that is associated with arbitration element 1. Source
5657 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5658 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5659 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
5660 #define XSEM_REG_ARB_ELEMENT1 0x280024
5661 /* [RW 3] The source that is associated with arbitration element 2. Source
5662 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5663 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5664 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5665 and ~xsem_registers_arb_element1.arb_element1 */
5666 #define XSEM_REG_ARB_ELEMENT2 0x280028
5667 /* [RW 3] The source that is associated with arbitration element 3. Source
5668 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5669 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5670 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
5671 ~xsem_registers_arb_element1.arb_element1 and
5672 ~xsem_registers_arb_element2.arb_element2 */
5673 #define XSEM_REG_ARB_ELEMENT3 0x28002c
5674 /* [RW 3] The source that is associated with arbitration element 4. Source
5675 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5676 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5677 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5678 and ~xsem_registers_arb_element1.arb_element1 and
5679 ~xsem_registers_arb_element2.arb_element2 and
5680 ~xsem_registers_arb_element3.arb_element3 */
5681 #define XSEM_REG_ARB_ELEMENT4 0x280030
5682 #define XSEM_REG_ENABLE_IN 0x2800a4
5683 #define XSEM_REG_ENABLE_OUT 0x2800a8
5684 /* [RW 32] This address space contains all registers and memories that are
5685 placed in SEM_FAST block. The SEM_FAST registers are described in
5686 appendix B. In order to access the sem_fast registers the base address
5687 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
5688 #define XSEM_REG_FAST_MEMORY 0x2a0000
5689 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
5691 #define XSEM_REG_FIC0_DISABLE 0x280224
5692 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
5694 #define XSEM_REG_FIC1_DISABLE 0x280234
5695 /* [RW 15] Interrupt table Read and write access to it is not possible in
5696 the middle of the work */
5697 #define XSEM_REG_INT_TABLE 0x280400
5698 /* [ST 24] Statistics register. The number of messages that entered through
5700 #define XSEM_REG_MSG_NUM_FIC0 0x280000
5701 /* [ST 24] Statistics register. The number of messages that entered through
5703 #define XSEM_REG_MSG_NUM_FIC1 0x280004
5704 /* [ST 24] Statistics register. The number of messages that were sent to
5706 #define XSEM_REG_MSG_NUM_FOC0 0x280008
5707 /* [ST 24] Statistics register. The number of messages that were sent to
5709 #define XSEM_REG_MSG_NUM_FOC1 0x28000c
5710 /* [ST 24] Statistics register. The number of messages that were sent to
5712 #define XSEM_REG_MSG_NUM_FOC2 0x280010
5713 /* [ST 24] Statistics register. The number of messages that were sent to
5715 #define XSEM_REG_MSG_NUM_FOC3 0x280014
5716 /* [RW 1] Disables input messages from the passive buffer May be updated
5717 during run_time by the microcode */
5718 #define XSEM_REG_PAS_DISABLE 0x28024c
5719 /* [WB 128] Debug only. Passive buffer memory */
5720 #define XSEM_REG_PASSIVE_BUFFER 0x282000
5721 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5722 #define XSEM_REG_PRAM 0x2c0000
5723 /* [R 16] Valid sleeping threads indication have bit per thread */
5724 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
5725 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
5726 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
5727 /* [RW 16] List of free threads . There is a bit per thread. */
5728 #define XSEM_REG_THREADS_LIST 0x2802e4
5729 /* [RW 3] The arbitration scheme of time_slot 0 */
5730 #define XSEM_REG_TS_0_AS 0x280038
5731 /* [RW 3] The arbitration scheme of time_slot 10 */
5732 #define XSEM_REG_TS_10_AS 0x280060
5733 /* [RW 3] The arbitration scheme of time_slot 11 */
5734 #define XSEM_REG_TS_11_AS 0x280064
5735 /* [RW 3] The arbitration scheme of time_slot 12 */
5736 #define XSEM_REG_TS_12_AS 0x280068
5737 /* [RW 3] The arbitration scheme of time_slot 13 */
5738 #define XSEM_REG_TS_13_AS 0x28006c
5739 /* [RW 3] The arbitration scheme of time_slot 14 */
5740 #define XSEM_REG_TS_14_AS 0x280070
5741 /* [RW 3] The arbitration scheme of time_slot 15 */
5742 #define XSEM_REG_TS_15_AS 0x280074
5743 /* [RW 3] The arbitration scheme of time_slot 16 */
5744 #define XSEM_REG_TS_16_AS 0x280078
5745 /* [RW 3] The arbitration scheme of time_slot 17 */
5746 #define XSEM_REG_TS_17_AS 0x28007c
5747 /* [RW 3] The arbitration scheme of time_slot 18 */
5748 #define XSEM_REG_TS_18_AS 0x280080
5749 /* [RW 3] The arbitration scheme of time_slot 1 */
5750 #define XSEM_REG_TS_1_AS 0x28003c
5751 /* [RW 3] The arbitration scheme of time_slot 2 */
5752 #define XSEM_REG_TS_2_AS 0x280040
5753 /* [RW 3] The arbitration scheme of time_slot 3 */
5754 #define XSEM_REG_TS_3_AS 0x280044
5755 /* [RW 3] The arbitration scheme of time_slot 4 */
5756 #define XSEM_REG_TS_4_AS 0x280048
5757 /* [RW 3] The arbitration scheme of time_slot 5 */
5758 #define XSEM_REG_TS_5_AS 0x28004c
5759 /* [RW 3] The arbitration scheme of time_slot 6 */
5760 #define XSEM_REG_TS_6_AS 0x280050
5761 /* [RW 3] The arbitration scheme of time_slot 7 */
5762 #define XSEM_REG_TS_7_AS 0x280054
5763 /* [RW 3] The arbitration scheme of time_slot 8 */
5764 #define XSEM_REG_TS_8_AS 0x280058
5765 /* [RW 3] The arbitration scheme of time_slot 9 */
5766 #define XSEM_REG_TS_9_AS 0x28005c
5767 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5768 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5769 #define XSEM_REG_VFPF_ERR_NUM 0x280380
5770 /* [RW 32] Interrupt mask register #0 read/write */
5771 #define XSEM_REG_XSEM_INT_MASK_0 0x280110
5772 #define XSEM_REG_XSEM_INT_MASK_1 0x280120
5773 /* [R 32] Interrupt register #0 read */
5774 #define XSEM_REG_XSEM_INT_STS_0 0x280104
5775 #define XSEM_REG_XSEM_INT_STS_1 0x280114
5776 /* [RW 32] Parity mask register #0 read/write */
5777 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
5778 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
5779 /* [R 32] Parity register #0 read */
5780 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124
5781 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134
5782 /* [RC 32] Parity register #0 read clear */
5783 #define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128
5784 #define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138
5785 #define MCPR_ACCESS_LOCK_LOCK (1L<<31)
5786 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
5787 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
5788 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
5789 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
5790 #define MCPR_NVM_COMMAND_DOIT (1L<<4)
5791 #define MCPR_NVM_COMMAND_DONE (1L<<3)
5792 #define MCPR_NVM_COMMAND_FIRST (1L<<7)
5793 #define MCPR_NVM_COMMAND_LAST (1L<<8)
5794 #define MCPR_NVM_COMMAND_WR (1L<<5)
5795 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
5796 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
5797 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
5798 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
5799 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5800 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
5801 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
5802 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
5803 #define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
5804 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
5805 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
5806 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
5807 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
5808 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
5809 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
5810 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
5811 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
5812 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
5813 #define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
5814 #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5815 #define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
5816 #define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
5817 #define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
5818 #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
5819 #define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
5820 #define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
5821 #define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
5822 #define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
5823 #define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3)
5824 #define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
5825 #define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
5826 #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
5827 #define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
5828 #define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
5829 #define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
5830 #define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3)
5831 #define EMAC_LED_1000MB_OVERRIDE (1L<<1)
5832 #define EMAC_LED_100MB_OVERRIDE (1L<<2)
5833 #define EMAC_LED_10MB_OVERRIDE (1L<<3)
5834 #define EMAC_LED_2500MB_OVERRIDE (1L<<12)
5835 #define EMAC_LED_OVERRIDE (1L<<0)
5836 #define EMAC_LED_TRAFFIC (1L<<6)
5837 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
5838 #define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
5839 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
5840 #define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
5841 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
5842 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
5843 #define EMAC_MDIO_COMM_START_BUSY (1L<<29)
5844 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
5845 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
5846 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16)
5847 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
5848 #define EMAC_MDIO_STATUS_10MB (1L<<1)
5849 #define EMAC_MODE_25G_MODE (1L<<5)
5850 #define EMAC_MODE_HALF_DUPLEX (1L<<1)
5851 #define EMAC_MODE_PORT_GMII (2L<<2)
5852 #define EMAC_MODE_PORT_MII (1L<<2)
5853 #define EMAC_MODE_PORT_MII_10M (3L<<2)
5854 #define EMAC_MODE_RESET (1L<<0)
5855 #define EMAC_REG_EMAC_LED 0xc
5856 #define EMAC_REG_EMAC_MAC_MATCH 0x10
5857 #define EMAC_REG_EMAC_MDIO_COMM 0xac
5858 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
5859 #define EMAC_REG_EMAC_MDIO_STATUS 0xb0
5860 #define EMAC_REG_EMAC_MODE 0x0
5861 #define EMAC_REG_EMAC_RX_MODE 0xc8
5862 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
5863 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
5864 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
5865 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
5866 #define EMAC_REG_EMAC_TX_MODE 0xbc
5867 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
5868 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
5869 #define EMAC_REG_RX_PFC_MODE 0x320
5870 #define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)
5871 #define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)
5872 #define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
5873 #define EMAC_REG_RX_PFC_PARAM 0x324
5874 #define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
5875 #define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
5876 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
5877 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
5878 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
5879 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
5880 #define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
5881 #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
5882 #define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
5883 #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
5884 #define EMAC_RX_MODE_FLOW_EN (1L<<2)
5885 #define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
5886 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
5887 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
5888 #define EMAC_RX_MODE_RESET (1L<<0)
5889 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
5890 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
5891 #define EMAC_TX_MODE_FLOW_EN (1L<<4)
5892 #define EMAC_TX_MODE_RESET (1L<<0)
5893 #define MISC_REGISTERS_GPIO_0 0
5894 #define MISC_REGISTERS_GPIO_1 1
5895 #define MISC_REGISTERS_GPIO_2 2
5896 #define MISC_REGISTERS_GPIO_3 3
5897 #define MISC_REGISTERS_GPIO_CLR_POS 16
5898 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
5899 #define MISC_REGISTERS_GPIO_FLOAT_POS 24
5900 #define MISC_REGISTERS_GPIO_HIGH 1
5901 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
5902 #define MISC_REGISTERS_GPIO_INT_CLR_POS 24
5903 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
5904 #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
5905 #define MISC_REGISTERS_GPIO_INT_SET_POS 16
5906 #define MISC_REGISTERS_GPIO_LOW 0
5907 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
5908 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
5909 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4
5910 #define MISC_REGISTERS_GPIO_SET_POS 8
5911 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
5912 #define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
5913 #define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19)
5914 #define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
5915 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
5916 #define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
5917 #define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
5918 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
5919 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
5920 #define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24)
5921 #define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25)
5922 #define MISC_REGISTERS_RESET_REG_2_PGLC (0x1<<19)
5923 #define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1<<17)
5924 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
5925 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
5926 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
5927 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
5928 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
5929 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
5930 #define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
5931 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
5932 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
5933 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
5934 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
5935 #define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
5936 #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
5937 #define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13)
5938 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
5939 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
5940 #define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20)
5941 #define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1<<21)
5942 #define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22)
5943 #define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23)
5944 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
5945 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
5946 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
5947 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
5948 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
5949 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
5950 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
5951 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
5952 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
5953 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
5954 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
5955 #define MISC_REGISTERS_SPIO_4 4
5956 #define MISC_REGISTERS_SPIO_5 5
5957 #define MISC_REGISTERS_SPIO_7 7
5958 #define MISC_REGISTERS_SPIO_CLR_POS 16
5959 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
5960 #define MISC_REGISTERS_SPIO_FLOAT_POS 24
5961 #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
5962 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
5963 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
5964 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
5965 #define MISC_REGISTERS_SPIO_SET_POS 8
5966 #define MISC_SPIO_CLR_POS 16
5967 #define MISC_SPIO_FLOAT (0xffL<<24)
5968 #define MISC_SPIO_FLOAT_POS 24
5969 #define MISC_SPIO_INPUT_HI_Z 2
5970 #define MISC_SPIO_INT_OLD_SET_POS 16
5971 #define MISC_SPIO_OUTPUT_HIGH 1
5972 #define MISC_SPIO_OUTPUT_LOW 0
5973 #define MISC_SPIO_SET_POS 8
5974 #define MISC_SPIO_SPIO4 0x10
5975 #define MISC_SPIO_SPIO5 0x20
5976 #define HW_LOCK_MAX_RESOURCE_VALUE 31
5977 #define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB 13
5978 #define HW_LOCK_RESOURCE_DRV_FLAGS 10
5979 #define HW_LOCK_RESOURCE_GPIO 1
5980 #define HW_LOCK_RESOURCE_MDIO 0
5981 #define HW_LOCK_RESOURCE_NVRAM 12
5982 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
5983 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
5984 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
5985 #define HW_LOCK_RESOURCE_RECOVERY_REG 11
5986 #define HW_LOCK_RESOURCE_RESET 5
5987 #define HW_LOCK_RESOURCE_SPIO 2
5988 #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
5989 #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
5990 #define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19)
5991 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
5992 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)
5993 #define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
5994 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
5995 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
5996 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
5997 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
5998 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
5999 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
6000 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
6001 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
6002 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
6003 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
6004 #define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
6005 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
6006 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
6007 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
6008 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
6009 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
6010 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31)
6011 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
6012 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
6013 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
6014 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
6015 #define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
6016 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
6017 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31)
6018 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
6019 #define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
6020 #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
6021 #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
6022 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
6023 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
6024 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
6025 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
6026 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
6027 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
6028 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
6029 #define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
6030 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
6031 #define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
6032 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
6033 #define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
6034 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
6035 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
6036 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
6037 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
6038 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
6039 #define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
6040 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
6041 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
6042 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
6043 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
6044 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
6045 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
6046 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
6047 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
6048 #define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
6049 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
6050 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
6051 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
6052 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
6054 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5)
6055 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9)
6057 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
6059 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
6060 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
6062 #define RESERVED_GENERAL_ATTENTION_BIT_6 6
6063 #define RESERVED_GENERAL_ATTENTION_BIT_7 7
6064 #define RESERVED_GENERAL_ATTENTION_BIT_8 8
6065 #define RESERVED_GENERAL_ATTENTION_BIT_9 9
6066 #define RESERVED_GENERAL_ATTENTION_BIT_10 10
6067 #define RESERVED_GENERAL_ATTENTION_BIT_11 11
6068 #define RESERVED_GENERAL_ATTENTION_BIT_12 12
6069 #define RESERVED_GENERAL_ATTENTION_BIT_13 13
6070 #define RESERVED_GENERAL_ATTENTION_BIT_14 14
6071 #define RESERVED_GENERAL_ATTENTION_BIT_15 15
6072 #define RESERVED_GENERAL_ATTENTION_BIT_16 16
6073 #define RESERVED_GENERAL_ATTENTION_BIT_17 17
6074 #define RESERVED_GENERAL_ATTENTION_BIT_18 18
6075 #define RESERVED_GENERAL_ATTENTION_BIT_19 19
6076 #define RESERVED_GENERAL_ATTENTION_BIT_20 20
6077 #define RESERVED_GENERAL_ATTENTION_BIT_21 21
6079 /* storm asserts attention bits */
6080 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
6081 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
6082 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
6083 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
6085 /* mcp error attention bit */
6086 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
6088 /*E1H NIG status sync attention mapped to group 4-7*/
6089 #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
6090 #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
6091 #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
6092 #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
6093 #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
6094 #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
6095 #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
6096 #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
6099 #define LATCHED_ATTN_RBCR 23
6100 #define LATCHED_ATTN_RBCT 24
6101 #define LATCHED_ATTN_RBCN 25
6102 #define LATCHED_ATTN_RBCU 26
6103 #define LATCHED_ATTN_RBCP 27
6104 #define LATCHED_ATTN_TIMEOUT_GRC 28
6105 #define LATCHED_ATTN_RSVD_GRC 29
6106 #define LATCHED_ATTN_ROM_PARITY_MCP 30
6107 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31
6108 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32
6109 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33
6111 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
6112 #define GENERAL_ATTEN_OFFSET(atten_name)\
6113 (1UL << ((94 + atten_name) % 32))
6115 * This file defines GRC base address for every block.
6116 * This file is included by chipsim, asm microcode and cpp microcode.
6117 * These values are used in Design.xml on regBase attribute
6118 * Use the base with the generated offsets of specific registers.
6121 #define GRCBASE_PXPCS 0x000000
6122 #define GRCBASE_PCICONFIG 0x002000
6123 #define GRCBASE_PCIREG 0x002400
6124 #define GRCBASE_EMAC0 0x008000
6125 #define GRCBASE_EMAC1 0x008400
6126 #define GRCBASE_DBU 0x008800
6127 #define GRCBASE_MISC 0x00A000
6128 #define GRCBASE_DBG 0x00C000
6129 #define GRCBASE_NIG 0x010000
6130 #define GRCBASE_XCM 0x020000
6131 #define GRCBASE_PRS 0x040000
6132 #define GRCBASE_SRCH 0x040400
6133 #define GRCBASE_TSDM 0x042000
6134 #define GRCBASE_TCM 0x050000
6135 #define GRCBASE_BRB1 0x060000
6136 #define GRCBASE_MCP 0x080000
6137 #define GRCBASE_UPB 0x0C1000
6138 #define GRCBASE_CSDM 0x0C2000
6139 #define GRCBASE_USDM 0x0C4000
6140 #define GRCBASE_CCM 0x0D0000
6141 #define GRCBASE_UCM 0x0E0000
6142 #define GRCBASE_CDU 0x101000
6143 #define GRCBASE_DMAE 0x102000
6144 #define GRCBASE_PXP 0x103000
6145 #define GRCBASE_CFC 0x104000
6146 #define GRCBASE_HC 0x108000
6147 #define GRCBASE_PXP2 0x120000
6148 #define GRCBASE_PBF 0x140000
6149 #define GRCBASE_UMAC0 0x160000
6150 #define GRCBASE_UMAC1 0x160400
6151 #define GRCBASE_XPB 0x161000
6152 #define GRCBASE_MSTAT0 0x162000
6153 #define GRCBASE_MSTAT1 0x162800
6154 #define GRCBASE_XMAC0 0x163000
6155 #define GRCBASE_XMAC1 0x163800
6156 #define GRCBASE_TIMERS 0x164000
6157 #define GRCBASE_XSDM 0x166000
6158 #define GRCBASE_QM 0x168000
6159 #define GRCBASE_DQ 0x170000
6160 #define GRCBASE_TSEM 0x180000
6161 #define GRCBASE_CSEM 0x200000
6162 #define GRCBASE_XSEM 0x280000
6163 #define GRCBASE_USEM 0x300000
6164 #define GRCBASE_MISC_AEU GRCBASE_MISC
6167 /* offset of configuration space in the pci core register */
6168 #define PCICFG_OFFSET 0x2000
6169 #define PCICFG_VENDOR_ID_OFFSET 0x00
6170 #define PCICFG_DEVICE_ID_OFFSET 0x02
6171 #define PCICFG_COMMAND_OFFSET 0x04
6172 #define PCICFG_COMMAND_IO_SPACE (1<<0)
6173 #define PCICFG_COMMAND_MEM_SPACE (1<<1)
6174 #define PCICFG_COMMAND_BUS_MASTER (1<<2)
6175 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
6176 #define PCICFG_COMMAND_MWI_CYCLES (1<<4)
6177 #define PCICFG_COMMAND_VGA_SNOOP (1<<5)
6178 #define PCICFG_COMMAND_PERR_ENA (1<<6)
6179 #define PCICFG_COMMAND_STEPPING (1<<7)
6180 #define PCICFG_COMMAND_SERR_ENA (1<<8)
6181 #define PCICFG_COMMAND_FAST_B2B (1<<9)
6182 #define PCICFG_COMMAND_INT_DISABLE (1<<10)
6183 #define PCICFG_COMMAND_RESERVED (0x1f<<11)
6184 #define PCICFG_STATUS_OFFSET 0x06
6185 #define PCICFG_REVISION_ID_OFFSET 0x08
6186 #define PCICFG_REVESION_ID_MASK 0xff
6187 #define PCICFG_REVESION_ID_ERROR_VAL 0xff
6188 #define PCICFG_CACHE_LINE_SIZE 0x0c
6189 #define PCICFG_LATENCY_TIMER 0x0d
6190 #define PCICFG_BAR_1_LOW 0x10
6191 #define PCICFG_BAR_1_HIGH 0x14
6192 #define PCICFG_BAR_2_LOW 0x18
6193 #define PCICFG_BAR_2_HIGH 0x1c
6194 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
6195 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
6196 #define PCICFG_INT_LINE 0x3c
6197 #define PCICFG_INT_PIN 0x3d
6198 #define PCICFG_PM_CAPABILITY 0x48
6199 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
6200 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
6201 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
6202 #define PCICFG_PM_CAPABILITY_DSI (1<<21)
6203 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
6204 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
6205 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
6206 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
6207 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
6208 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
6209 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
6210 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
6211 #define PCICFG_PM_CSR_OFFSET 0x4c
6212 #define PCICFG_PM_CSR_STATE (0x3<<0)
6213 #define PCICFG_PM_CSR_PME_ENABLE (1<<8)
6214 #define PCICFG_PM_CSR_PME_STATUS (1<<15)
6215 #define PCICFG_MSI_CAP_ID_OFFSET 0x58
6216 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
6217 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
6218 #define PCICFG_MSI_CONTROL_MENA (0x7<<20)
6219 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
6220 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
6221 #define PCICFG_GRC_ADDRESS 0x78
6222 #define PCICFG_GRC_DATA 0x80
6223 #define PCICFG_ME_REGISTER 0x98
6224 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
6225 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
6226 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
6227 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
6228 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
6230 #define PCICFG_DEVICE_CONTROL 0xb4
6231 #define PCICFG_DEVICE_STATUS 0xb6
6232 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
6233 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
6234 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
6235 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
6236 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
6237 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
6238 #define PCICFG_LINK_CONTROL 0xbc
6241 #define BAR_USTRORM_INTMEM 0x400000
6242 #define BAR_CSTRORM_INTMEM 0x410000
6243 #define BAR_XSTRORM_INTMEM 0x420000
6244 #define BAR_TSTRORM_INTMEM 0x430000
6246 /* for accessing the IGU in case of status block ACK */
6247 #define BAR_IGU_INTMEM 0x440000
6249 #define BAR_DOORBELL_OFFSET 0x800000
6251 #define BAR_ME_REGISTER 0x450000
6253 /* config_2 offset */
6254 #define GRC_CONFIG_2_SIZE_REG 0x408
6255 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
6256 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
6257 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
6258 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
6259 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
6260 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
6261 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
6262 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
6263 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
6264 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
6265 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
6266 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
6267 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
6268 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
6269 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
6270 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
6271 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
6272 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
6273 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
6274 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
6275 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
6276 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
6277 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
6278 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
6279 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
6280 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
6281 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
6282 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
6283 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
6284 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
6285 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
6286 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
6287 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
6288 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
6289 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
6290 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
6291 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
6292 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
6293 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
6294 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
6296 /* config_3 offset */
6297 #define GRC_CONFIG_3_SIZE_REG 0x40c
6298 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
6299 #define PCI_CONFIG_3_FORCE_PME (1L<<24)
6300 #define PCI_CONFIG_3_PME_STATUS (1L<<25)
6301 #define PCI_CONFIG_3_PME_ENABLE (1L<<26)
6302 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
6303 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
6304 #define PCI_CONFIG_3_PCI_POWER (1L<<31)
6306 #define GRC_BAR2_CONFIG 0x4e0
6307 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
6308 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
6309 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
6310 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
6311 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
6312 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
6313 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
6314 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
6315 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
6316 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
6317 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
6318 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
6319 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
6320 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
6321 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
6322 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
6323 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
6324 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
6326 #define PCI_PM_DATA_A 0x410
6327 #define PCI_PM_DATA_B 0x414
6328 #define PCI_ID_VAL1 0x434
6329 #define PCI_ID_VAL2 0x438
6330 #define PCI_ID_VAL3 0x43c
6332 #define GRC_CONFIG_REG_PF_INIT_VF 0x624
6333 #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xf
6334 /* First VF_NUM for PF is encoded in this register.
6335 * The number of VFs assigned to a PF is assumed to be a multiple of 8.
6336 * Software should program these bits based on Total Number of VFs \
6337 * programmed for each PF.
6338 * Since registers from 0x000-0x7ff are split across functions, each PF will
6339 * have the same location for the same 4 bits
6342 #define PXPCS_TL_CONTROL_5 0x814
6343 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/
6344 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/
6345 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/
6346 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/
6347 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/
6348 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/
6349 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/
6350 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/
6351 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/
6352 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/
6353 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/
6354 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/
6355 #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/
6356 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/
6357 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/
6358 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/
6359 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/
6360 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/
6361 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/
6362 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/
6363 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/
6364 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/
6365 #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/
6366 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/
6367 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/
6368 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/
6369 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/
6370 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/
6371 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/
6372 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/
6375 #define PXPCS_TL_FUNC345_STAT 0x854
6376 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */
6377 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\
6378 (1 << 28) /* Unsupported Request Error Status in function4, if \
6379 set, generate pcie_err_attn output when this error is seen. WC */
6380 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\
6381 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \
6382 generate pcie_err_attn output when this error is seen.. WC */
6383 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\
6384 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \
6385 generate pcie_err_attn output when this error is seen.. WC */
6386 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\
6387 (1 << 25) /* Receiver Overflow Status Status in function 4, if \
6388 set, generate pcie_err_attn output when this error is seen.. WC \
6390 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\
6391 (1 << 24) /* Unexpected Completion Status Status in function 4, \
6392 if set, generate pcie_err_attn output when this error is seen. WC \
6394 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\
6395 (1 << 23) /* Receive UR Statusin function 4. If set, generate \
6396 pcie_err_attn output when this error is seen. WC */
6397 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\
6398 (1 << 22) /* Completer Timeout Status Status in function 4, if \
6399 set, generate pcie_err_attn output when this error is seen. WC */
6400 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\
6401 (1 << 21) /* Flow Control Protocol Error Status Status in \
6402 function 4, if set, generate pcie_err_attn output when this error \
6404 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\
6405 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \
6406 generate pcie_err_attn output when this error is seen.. WC */
6407 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */
6408 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\
6409 (1 << 18) /* Unsupported Request Error Status in function3, if \
6410 set, generate pcie_err_attn output when this error is seen. WC */
6411 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\
6412 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \
6413 generate pcie_err_attn output when this error is seen.. WC */
6414 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\
6415 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \
6416 generate pcie_err_attn output when this error is seen.. WC */
6417 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\
6418 (1 << 15) /* Receiver Overflow Status Status in function 3, if \
6419 set, generate pcie_err_attn output when this error is seen.. WC \
6421 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\
6422 (1 << 14) /* Unexpected Completion Status Status in function 3, \
6423 if set, generate pcie_err_attn output when this error is seen. WC \
6425 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\
6426 (1 << 13) /* Receive UR Statusin function 3. If set, generate \
6427 pcie_err_attn output when this error is seen. WC */
6428 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\
6429 (1 << 12) /* Completer Timeout Status Status in function 3, if \
6430 set, generate pcie_err_attn output when this error is seen. WC */
6431 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\
6432 (1 << 11) /* Flow Control Protocol Error Status Status in \
6433 function 3, if set, generate pcie_err_attn output when this error \
6435 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\
6436 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \
6437 generate pcie_err_attn output when this error is seen.. WC */
6438 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */
6439 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\
6440 (1 << 8) /* Unsupported Request Error Status for Function 2, if \
6441 set, generate pcie_err_attn output when this error is seen. WC */
6442 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\
6443 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \
6444 generate pcie_err_attn output when this error is seen.. WC */
6445 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\
6446 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \
6447 generate pcie_err_attn output when this error is seen.. WC */
6448 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\
6449 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \
6450 set, generate pcie_err_attn output when this error is seen.. WC \
6452 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\
6453 (1 << 4) /* Unexpected Completion Status Status for Function 2, \
6454 if set, generate pcie_err_attn output when this error is seen. WC \
6456 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\
6457 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \
6458 pcie_err_attn output when this error is seen. WC */
6459 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\
6460 (1 << 2) /* Completer Timeout Status Status for Function 2, if \
6461 set, generate pcie_err_attn output when this error is seen. WC */
6462 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\
6463 (1 << 1) /* Flow Control Protocol Error Status Status for \
6464 Function 2, if set, generate pcie_err_attn output when this error \
6466 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\
6467 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
6468 generate pcie_err_attn output when this error is seen.. WC */
6471 #define PXPCS_TL_FUNC678_STAT 0x85C
6472 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */
6473 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\
6474 (1 << 28) /* Unsupported Request Error Status in function7, if \
6475 set, generate pcie_err_attn output when this error is seen. WC */
6476 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\
6477 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \
6478 generate pcie_err_attn output when this error is seen.. WC */
6479 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\
6480 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \
6481 generate pcie_err_attn output when this error is seen.. WC */
6482 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\
6483 (1 << 25) /* Receiver Overflow Status Status in function 7, if \
6484 set, generate pcie_err_attn output when this error is seen.. WC \
6486 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\
6487 (1 << 24) /* Unexpected Completion Status Status in function 7, \
6488 if set, generate pcie_err_attn output when this error is seen. WC \
6490 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\
6491 (1 << 23) /* Receive UR Statusin function 7. If set, generate \
6492 pcie_err_attn output when this error is seen. WC */
6493 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\
6494 (1 << 22) /* Completer Timeout Status Status in function 7, if \
6495 set, generate pcie_err_attn output when this error is seen. WC */
6496 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\
6497 (1 << 21) /* Flow Control Protocol Error Status Status in \
6498 function 7, if set, generate pcie_err_attn output when this error \
6500 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\
6501 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \
6502 generate pcie_err_attn output when this error is seen.. WC */
6503 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */
6504 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\
6505 (1 << 18) /* Unsupported Request Error Status in function6, if \
6506 set, generate pcie_err_attn output when this error is seen. WC */
6507 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\
6508 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \
6509 generate pcie_err_attn output when this error is seen.. WC */
6510 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\
6511 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \
6512 generate pcie_err_attn output when this error is seen.. WC */
6513 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\
6514 (1 << 15) /* Receiver Overflow Status Status in function 6, if \
6515 set, generate pcie_err_attn output when this error is seen.. WC \
6517 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\
6518 (1 << 14) /* Unexpected Completion Status Status in function 6, \
6519 if set, generate pcie_err_attn output when this error is seen. WC \
6521 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\
6522 (1 << 13) /* Receive UR Statusin function 6. If set, generate \
6523 pcie_err_attn output when this error is seen. WC */
6524 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\
6525 (1 << 12) /* Completer Timeout Status Status in function 6, if \
6526 set, generate pcie_err_attn output when this error is seen. WC */
6527 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\
6528 (1 << 11) /* Flow Control Protocol Error Status Status in \
6529 function 6, if set, generate pcie_err_attn output when this error \
6531 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\
6532 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \
6533 generate pcie_err_attn output when this error is seen.. WC */
6534 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */
6535 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\
6536 (1 << 8) /* Unsupported Request Error Status for Function 5, if \
6537 set, generate pcie_err_attn output when this error is seen. WC */
6538 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\
6539 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \
6540 generate pcie_err_attn output when this error is seen.. WC */
6541 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\
6542 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \
6543 generate pcie_err_attn output when this error is seen.. WC */
6544 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\
6545 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \
6546 set, generate pcie_err_attn output when this error is seen.. WC \
6548 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\
6549 (1 << 4) /* Unexpected Completion Status Status for Function 5, \
6550 if set, generate pcie_err_attn output when this error is seen. WC \
6552 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\
6553 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \
6554 pcie_err_attn output when this error is seen. WC */
6555 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\
6556 (1 << 2) /* Completer Timeout Status Status for Function 5, if \
6557 set, generate pcie_err_attn output when this error is seen. WC */
6558 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\
6559 (1 << 1) /* Flow Control Protocol Error Status Status for \
6560 Function 5, if set, generate pcie_err_attn output when this error \
6562 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\
6563 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
6564 generate pcie_err_attn output when this error is seen.. WC */
6567 #define BAR_USTRORM_INTMEM 0x400000
6568 #define BAR_CSTRORM_INTMEM 0x410000
6569 #define BAR_XSTRORM_INTMEM 0x420000
6570 #define BAR_TSTRORM_INTMEM 0x430000
6572 /* for accessing the IGU in case of status block ACK */
6573 #define BAR_IGU_INTMEM 0x440000
6575 #define BAR_DOORBELL_OFFSET 0x800000
6577 #define BAR_ME_REGISTER 0x450000
6578 #define ME_REG_PF_NUM_SHIFT 0
6579 #define ME_REG_PF_NUM\
6580 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */
6581 #define ME_REG_VF_VALID (1<<8)
6582 #define ME_REG_VF_NUM_SHIFT 9
6583 #define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
6584 #define ME_REG_VF_ERR (0x1<<3)
6585 #define ME_REG_ABS_PF_NUM_SHIFT 16
6586 #define ME_REG_ABS_PF_NUM\
6587 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */
6590 #define PXP_VF_ADDR_IGU_START 0
6591 #define PXP_VF_ADDR_IGU_SIZE 0x3000
6592 #define PXP_VF_ADDR_IGU_END\
6593 ((PXP_VF_ADDR_IGU_START) + (PXP_VF_ADDR_IGU_SIZE) - 1)
6595 #define PXP_VF_ADDR_USDM_QUEUES_START 0x3000
6596 #define PXP_VF_ADDR_USDM_QUEUES_SIZE\
6597 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
6598 #define PXP_VF_ADDR_USDM_QUEUES_END\
6599 ((PXP_VF_ADDR_USDM_QUEUES_START) + (PXP_VF_ADDR_USDM_QUEUES_SIZE) - 1)
6601 #define PXP_VF_ADDR_CSDM_GLOBAL_START 0x7600
6602 #define PXP_VF_ADDR_CSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE)
6603 #define PXP_VF_ADDR_CSDM_GLOBAL_END\
6604 ((PXP_VF_ADDR_CSDM_GLOBAL_START) + (PXP_VF_ADDR_CSDM_GLOBAL_SIZE) - 1)
6606 #define PXP_VF_ADDR_DB_START 0x7c00
6607 #define PXP_VF_ADDR_DB_SIZE 0x200
6608 #define PXP_VF_ADDR_DB_END\
6609 ((PXP_VF_ADDR_DB_START) + (PXP_VF_ADDR_DB_SIZE) - 1)
6611 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
6612 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
6613 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
6614 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
6615 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
6617 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
6618 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
6619 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
6620 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
6621 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
6622 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
6623 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
6624 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
6625 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
6626 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
6627 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
6628 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
6629 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
6630 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
6631 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
6632 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
6633 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
6635 #define MDIO_REG_BANK_RX0 0x80b0
6636 #define MDIO_RX0_RX_STATUS 0x10
6637 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
6638 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
6639 #define MDIO_RX0_RX_EQ_BOOST 0x1c
6640 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6641 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
6643 #define MDIO_REG_BANK_RX1 0x80c0
6644 #define MDIO_RX1_RX_EQ_BOOST 0x1c
6645 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6646 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
6648 #define MDIO_REG_BANK_RX2 0x80d0
6649 #define MDIO_RX2_RX_EQ_BOOST 0x1c
6650 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6651 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
6653 #define MDIO_REG_BANK_RX3 0x80e0
6654 #define MDIO_RX3_RX_EQ_BOOST 0x1c
6655 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6656 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
6658 #define MDIO_REG_BANK_RX_ALL 0x80f0
6659 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
6660 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6661 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
6663 #define MDIO_REG_BANK_TX0 0x8060
6664 #define MDIO_TX0_TX_DRIVER 0x17
6665 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6666 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6667 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6668 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6669 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6670 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6671 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6672 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6673 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6675 #define MDIO_REG_BANK_TX1 0x8070
6676 #define MDIO_TX1_TX_DRIVER 0x17
6677 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6678 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6679 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6680 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6681 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6682 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6683 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6684 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6685 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6687 #define MDIO_REG_BANK_TX2 0x8080
6688 #define MDIO_TX2_TX_DRIVER 0x17
6689 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6690 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6691 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6692 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6693 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6694 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6695 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6696 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6697 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6699 #define MDIO_REG_BANK_TX3 0x8090
6700 #define MDIO_TX3_TX_DRIVER 0x17
6701 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6702 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6703 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6704 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6705 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6706 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6707 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6708 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6709 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6711 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
6712 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
6714 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
6715 #define MDIO_BLOCK1_LANE_CTRL0 0x15
6716 #define MDIO_BLOCK1_LANE_CTRL1 0x16
6717 #define MDIO_BLOCK1_LANE_CTRL2 0x17
6718 #define MDIO_BLOCK1_LANE_PRBS 0x19
6720 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
6721 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
6722 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
6723 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
6724 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
6725 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
6726 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
6727 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
6728 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
6729 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
6731 #define MDIO_REG_BANK_GP_STATUS 0x8120
6732 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
6733 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
6734 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
6735 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
6736 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
6737 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
6738 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
6739 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
6740 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
6741 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
6742 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
6743 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
6744 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
6745 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
6746 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
6747 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
6748 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
6749 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
6750 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
6751 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
6752 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
6753 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
6754 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
6755 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
6756 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
6757 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
6758 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
6759 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
6760 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
6761 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
6764 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
6765 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
6766 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
6767 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
6768 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
6769 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
6770 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
6772 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
6773 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
6774 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
6775 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
6776 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
6777 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
6778 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
6779 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
6780 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
6781 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
6782 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
6783 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
6784 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
6785 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
6786 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
6787 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
6788 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
6789 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
6790 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
6791 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
6792 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
6793 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
6794 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
6795 #define MDIO_SERDES_DIGITAL_MISC1 0x18
6796 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
6797 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
6798 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
6799 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
6800 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
6801 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
6802 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
6803 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
6804 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
6805 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
6806 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
6807 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
6808 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
6809 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
6810 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
6811 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
6812 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
6813 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
6815 #define MDIO_REG_BANK_OVER_1G 0x8320
6816 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
6817 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
6818 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
6819 #define MDIO_OVER_1G_UP1 0x19
6820 #define MDIO_OVER_1G_UP1_2_5G 0x0001
6821 #define MDIO_OVER_1G_UP1_5G 0x0002
6822 #define MDIO_OVER_1G_UP1_6G 0x0004
6823 #define MDIO_OVER_1G_UP1_10G 0x0010
6824 #define MDIO_OVER_1G_UP1_10GH 0x0008
6825 #define MDIO_OVER_1G_UP1_12G 0x0020
6826 #define MDIO_OVER_1G_UP1_12_5G 0x0040
6827 #define MDIO_OVER_1G_UP1_13G 0x0080
6828 #define MDIO_OVER_1G_UP1_15G 0x0100
6829 #define MDIO_OVER_1G_UP1_16G 0x0200
6830 #define MDIO_OVER_1G_UP2 0x1A
6831 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
6832 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
6833 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
6834 #define MDIO_OVER_1G_UP3 0x1B
6835 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
6836 #define MDIO_OVER_1G_LP_UP1 0x1C
6837 #define MDIO_OVER_1G_LP_UP2 0x1D
6838 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
6839 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
6840 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
6841 #define MDIO_OVER_1G_LP_UP3 0x1E
6843 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
6844 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
6845 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
6846 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
6848 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
6849 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
6850 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
6851 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
6853 #define MDIO_REG_BANK_CL73_USERB0 0x8370
6854 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
6855 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
6856 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
6857 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
6858 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
6859 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
6860 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
6861 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
6862 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
6863 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
6864 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
6866 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
6867 #define MDIO_AER_BLOCK_AER_REG 0x1E
6869 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
6870 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
6871 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
6872 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
6873 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
6874 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
6875 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
6876 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
6877 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
6878 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
6879 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
6880 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
6881 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
6882 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
6883 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
6884 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
6885 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
6886 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
6887 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
6888 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
6889 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
6890 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
6891 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
6892 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
6893 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
6894 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
6895 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
6896 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
6897 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
6898 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
6899 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
6900 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
6901 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
6902 Theotherbitsarereservedandshouldbezero*/
6903 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
6906 #define MDIO_PMA_DEVAD 0x1
6908 #define MDIO_PMA_REG_CTRL 0x0
6909 #define MDIO_PMA_REG_STATUS 0x1
6910 #define MDIO_PMA_REG_10G_CTRL2 0x7
6911 #define MDIO_PMA_REG_TX_DISABLE 0x0009
6912 #define MDIO_PMA_REG_RX_SD 0xa
6914 #define MDIO_PMA_REG_BCM_CTRL 0x0096
6915 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
6916 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
6917 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
6918 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
6919 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
6920 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
6921 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
6922 #define MDIO_PMA_REG_GEN_CTRL 0xca10
6923 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
6924 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
6925 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
6926 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
6927 #define MDIO_PMA_REG_ROM_VER1 0xca19
6928 #define MDIO_PMA_REG_ROM_VER2 0xca1a
6929 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
6930 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
6931 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
6932 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
6933 #define MDIO_PMA_REG_LRM_MODE 0xca3f
6934 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
6935 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
6937 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
6938 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
6939 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
6940 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
6941 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
6942 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
6943 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
6944 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
6945 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
6946 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
6947 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
6948 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
6950 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
6951 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
6952 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
6953 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
6954 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
6955 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
6956 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
6957 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
6958 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
6960 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
6962 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
6963 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
6964 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
6965 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
6967 #define MDIO_PMA_REG_7101_RESET 0xc000
6968 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
6969 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
6970 #define MDIO_PMA_REG_7101_VER1 0xc026
6971 #define MDIO_PMA_REG_7101_VER2 0xc027
6973 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
6974 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
6975 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
6976 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
6977 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
6978 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
6979 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
6980 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
6981 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
6982 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
6985 #define MDIO_WIS_DEVAD 0x2
6987 #define MDIO_WIS_REG_LASI_CNTL 0x9002
6988 #define MDIO_WIS_REG_LASI_STATUS 0x9005
6990 #define MDIO_PCS_DEVAD 0x3
6991 #define MDIO_PCS_REG_STATUS 0x0020
6992 #define MDIO_PCS_REG_LASI_STATUS 0x9005
6993 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
6994 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
6995 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
6996 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
6997 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
6998 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
6999 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
7000 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
7001 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
7004 #define MDIO_XS_DEVAD 0x4
7005 #define MDIO_XS_PLL_SEQUENCER 0x8000
7006 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
7008 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
7009 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
7010 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
7011 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
7012 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
7014 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
7016 #define MDIO_AN_DEVAD 0x7
7018 #define MDIO_AN_REG_CTRL 0x0000
7019 #define MDIO_AN_REG_STATUS 0x0001
7020 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
7021 #define MDIO_AN_REG_ADV_PAUSE 0x0010
7022 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
7023 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
7024 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
7025 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
7026 #define MDIO_AN_REG_ADV 0x0011
7027 #define MDIO_AN_REG_ADV2 0x0012
7028 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
7029 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
7030 #define MDIO_AN_REG_MASTER_STATUS 0x0021
7031 #define MDIO_AN_REG_EEE_ADV 0x003c
7032 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
7034 #define MDIO_AN_REG_LINK_STATUS 0x8304
7035 #define MDIO_AN_REG_CL37_CL73 0x8370
7036 #define MDIO_AN_REG_CL37_AN 0xffe0
7037 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
7038 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
7039 #define MDIO_AN_REG_1000T_STATUS 0xffea
7041 #define MDIO_AN_REG_8073_2_5G 0x8329
7042 #define MDIO_AN_REG_8073_BAM 0x8350
7044 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
7045 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
7046 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
7047 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
7048 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
7049 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
7050 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
7051 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
7052 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
7053 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
7054 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
7055 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
7056 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
7059 #define MDIO_CTL_DEVAD 0x1e
7060 #define MDIO_CTL_REG_84823_MEDIA 0x401a
7061 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
7062 /* These pins configure the BCM84823 interface to MAC after reset. */
7063 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
7064 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
7065 /* These pins configure the BCM84823 interface to Line after reset. */
7066 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
7067 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
7068 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
7069 /* When this pin is active high during reset, 10GBASE-T core is power
7070 * down, When it is active low the 10GBASE-T is power up
7072 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
7073 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
7074 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
7075 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
7076 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
7077 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
7078 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
7079 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
7080 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
7081 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
7082 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
7083 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
7086 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
7087 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
7088 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
7089 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
7090 #define MDIO_84833_SUPER_ISOLATE 0x8000
7091 /* These are mailbox register set used by 84833. */
7092 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
7093 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
7094 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
7095 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
7096 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
7097 #define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
7098 #define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
7099 #define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
7100 #define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
7101 #define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
7102 #define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
7103 #define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
7104 #define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
7105 #define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
7106 #define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
7107 #define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
7108 #define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
7109 #define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
7111 /* Mailbox command set used by 84833. */
7112 #define PHY84833_CMD_SET_PAIR_SWAP 0x8001
7113 #define PHY84833_CMD_GET_EEE_MODE 0x8008
7114 #define PHY84833_CMD_SET_EEE_MODE 0x8009
7115 /* Mailbox status set used by 84833. */
7116 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
7117 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
7118 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
7119 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
7120 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
7121 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
7122 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
7123 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
7124 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
7127 /* Warpcore clause 45 addressing */
7128 #define MDIO_WC_DEVAD 0x3
7129 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
7130 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
7131 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
7132 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
7133 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
7134 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
7135 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
7136 #define MDIO_WC_REG_PCS_STATUS2 0x0021
7137 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
7138 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
7139 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
7140 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
7141 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
7142 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
7143 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
7144 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
7145 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
7146 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
7147 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
7148 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
7149 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
7150 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
7151 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
7152 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
7153 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
7154 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
7155 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
7156 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
7157 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
7158 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
7159 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
7160 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
7161 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
7162 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
7163 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
7164 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
7165 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
7166 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
7167 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
7168 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
7169 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
7170 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
7171 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
7172 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
7173 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
7174 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
7175 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
7176 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
7177 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
7178 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
7179 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
7180 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
7181 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
7182 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
7183 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
7184 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
7185 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
7186 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
7187 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
7188 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
7189 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
7190 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
7191 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
7192 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
7193 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
7194 #define MDIO_WC_REG_DSC_SMC 0x8213
7195 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
7196 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
7197 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
7198 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
7199 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
7200 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
7201 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
7202 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
7203 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
7204 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
7205 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
7206 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
7207 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
7208 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
7209 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
7210 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
7211 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
7212 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
7213 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
7214 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
7215 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
7216 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
7217 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
7218 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
7219 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
7220 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
7221 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
7222 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
7223 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
7224 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
7225 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
7226 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
7227 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
7228 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
7229 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
7230 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
7231 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
7232 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
7233 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
7234 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
7235 #define MDIO_WC_REG_RX66_SCW0 0x83c2
7236 #define MDIO_WC_REG_RX66_SCW1 0x83c3
7237 #define MDIO_WC_REG_RX66_SCW2 0x83c4
7238 #define MDIO_WC_REG_RX66_SCW3 0x83c5
7239 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
7240 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
7241 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
7242 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
7243 #define MDIO_WC_REG_FX100_CTRL1 0x8400
7244 #define MDIO_WC_REG_FX100_CTRL3 0x8402
7245 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
7246 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
7247 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
7248 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
7249 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
7250 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
7251 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
7252 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
7253 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
7254 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
7255 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
7256 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
7257 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
7258 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
7260 #define MDIO_WC_REG_AERBLK_AER 0xffde
7261 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
7262 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
7264 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
7265 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
7266 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
7268 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
7270 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
7273 #define MDIO_REG_GPHY_PHYID_LSB 0x3
7274 #define MDIO_REG_GPHY_ID_54618SE 0x5cd5
7275 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
7276 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
7277 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
7278 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
7279 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
7280 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
7281 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
7282 #define MDIO_REG_GPHY_AUX_STATUS 0x19
7283 #define MDIO_REG_INTR_STATUS 0x1a
7284 #define MDIO_REG_INTR_MASK 0x1b
7285 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
7286 #define MDIO_REG_GPHY_SHADOW 0x1c
7287 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
7288 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
7289 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
7290 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
7291 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
7293 #define IGU_FUNC_BASE 0x0400
7295 #define IGU_ADDR_MSIX 0x0000
7296 #define IGU_ADDR_INT_ACK 0x0200
7297 #define IGU_ADDR_PROD_UPD 0x0201
7298 #define IGU_ADDR_ATTN_BITS_UPD 0x0202
7299 #define IGU_ADDR_ATTN_BITS_SET 0x0203
7300 #define IGU_ADDR_ATTN_BITS_CLR 0x0204
7301 #define IGU_ADDR_COALESCE_NOW 0x0205
7302 #define IGU_ADDR_SIMD_MASK 0x0206
7303 #define IGU_ADDR_SIMD_NOMASK 0x0207
7304 #define IGU_ADDR_MSI_CTL 0x0210
7305 #define IGU_ADDR_MSI_ADDR_LO 0x0211
7306 #define IGU_ADDR_MSI_ADDR_HI 0x0212
7307 #define IGU_ADDR_MSI_DATA 0x0213
7309 #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0
7310 #define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1
7311 #define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2
7312 #define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3
7314 #define COMMAND_REG_INT_ACK 0x0
7315 #define COMMAND_REG_PROD_UPD 0x4
7316 #define COMMAND_REG_ATTN_BITS_UPD 0x8
7317 #define COMMAND_REG_ATTN_BITS_SET 0xc
7318 #define COMMAND_REG_ATTN_BITS_CLR 0x10
7319 #define COMMAND_REG_COALESCE_NOW 0x14
7320 #define COMMAND_REG_SIMD_MASK 0x18
7321 #define COMMAND_REG_SIMD_NOMASK 0x1c
7324 #define IGU_MEM_BASE 0x0000
7326 #define IGU_MEM_MSIX_BASE 0x0000
7327 #define IGU_MEM_MSIX_UPPER 0x007f
7328 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
7330 #define IGU_MEM_PBA_MSIX_BASE 0x0200
7331 #define IGU_MEM_PBA_MSIX_UPPER 0x0200
7333 #define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
7334 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
7336 #define IGU_CMD_INT_ACK_BASE 0x0400
7337 #define IGU_CMD_INT_ACK_UPPER\
7338 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
7339 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
7341 #define IGU_CMD_E2_PROD_UPD_BASE 0x0500
7342 #define IGU_CMD_E2_PROD_UPD_UPPER\
7343 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
7344 #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
7346 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
7347 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
7348 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
7350 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
7351 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
7352 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
7353 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
7355 #define IGU_REG_RESERVED_UPPER 0x05ff
7356 /* Fields of IGU PF CONFIGRATION REGISTER */
7357 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
7358 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
7359 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
7360 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
7361 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
7362 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
7364 /* Fields of IGU VF CONFIGRATION REGISTER */
7365 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
7366 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
7367 #define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
7368 #define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */
7369 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
7372 #define IGU_BC_DSB_NUM_SEGS 5
7373 #define IGU_BC_NDSB_NUM_SEGS 2
7374 #define IGU_NORM_DSB_NUM_SEGS 2
7375 #define IGU_NORM_NDSB_NUM_SEGS 1
7376 #define IGU_BC_BASE_DSB_PROD 128
7377 #define IGU_NORM_BASE_DSB_PROD 136
7379 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
7380 [5:2] = 0; [1:0] = PF number) */
7381 #define IGU_FID_ENCODE_IS_PF (0x1<<6)
7382 #define IGU_FID_ENCODE_IS_PF_SHIFT 6
7383 #define IGU_FID_VF_NUM_MASK (0x3f)
7384 #define IGU_FID_PF_NUM_MASK (0x7)
7386 #define IGU_REG_MAPPING_MEMORY_VALID (1<<0)
7387 #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1)
7388 #define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1
7389 #define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)
7390 #define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7
7393 #define CDU_REGION_NUMBER_XCM_AG 2
7394 #define CDU_REGION_NUMBER_UCM_AG 4
7397 /* String-to-compress [31:8] = CID (all 24 bits)
7398 * String-to-compress [7:4] = Region
7399 * String-to-compress [3:0] = Type
7401 #define CDU_VALID_DATA(_cid, _region, _type)\
7402 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
7403 #define CDU_CRC8(_cid, _region, _type)\
7404 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
7405 #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\
7406 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
7407 #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\
7408 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
7409 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
7411 /******************************************************************************
7413 * Calculates crc 8 on a word value: polynomial 0-1-2-8
7414 * Code was translated from Verilog.
7416 *****************************************************************************/
7417 static inline u8
calc_crc8(u32 data
, u8 crc
)
7425 /* split the data into 31 bits */
7426 for (i
= 0; i
< 32; i
++) {
7427 D
[i
] = (u8
)(data
& 1);
7431 /* split the crc into 8 bits */
7432 for (i
= 0; i
< 8; i
++) {
7437 NewCRC
[0] = D
[31] ^ D
[30] ^ D
[28] ^ D
[23] ^ D
[21] ^ D
[19] ^ D
[18] ^
7438 D
[16] ^ D
[14] ^ D
[12] ^ D
[8] ^ D
[7] ^ D
[6] ^ D
[0] ^ C
[4] ^
7440 NewCRC
[1] = D
[30] ^ D
[29] ^ D
[28] ^ D
[24] ^ D
[23] ^ D
[22] ^ D
[21] ^
7441 D
[20] ^ D
[18] ^ D
[17] ^ D
[16] ^ D
[15] ^ D
[14] ^ D
[13] ^
7442 D
[12] ^ D
[9] ^ D
[6] ^ D
[1] ^ D
[0] ^ C
[0] ^ C
[4] ^ C
[5] ^
7444 NewCRC
[2] = D
[29] ^ D
[28] ^ D
[25] ^ D
[24] ^ D
[22] ^ D
[17] ^ D
[15] ^
7445 D
[13] ^ D
[12] ^ D
[10] ^ D
[8] ^ D
[6] ^ D
[2] ^ D
[1] ^ D
[0] ^
7446 C
[0] ^ C
[1] ^ C
[4] ^ C
[5];
7447 NewCRC
[3] = D
[30] ^ D
[29] ^ D
[26] ^ D
[25] ^ D
[23] ^ D
[18] ^ D
[16] ^
7448 D
[14] ^ D
[13] ^ D
[11] ^ D
[9] ^ D
[7] ^ D
[3] ^ D
[2] ^ D
[1] ^
7449 C
[1] ^ C
[2] ^ C
[5] ^ C
[6];
7450 NewCRC
[4] = D
[31] ^ D
[30] ^ D
[27] ^ D
[26] ^ D
[24] ^ D
[19] ^ D
[17] ^
7451 D
[15] ^ D
[14] ^ D
[12] ^ D
[10] ^ D
[8] ^ D
[4] ^ D
[3] ^ D
[2] ^
7452 C
[0] ^ C
[2] ^ C
[3] ^ C
[6] ^ C
[7];
7453 NewCRC
[5] = D
[31] ^ D
[28] ^ D
[27] ^ D
[25] ^ D
[20] ^ D
[18] ^ D
[16] ^
7454 D
[15] ^ D
[13] ^ D
[11] ^ D
[9] ^ D
[5] ^ D
[4] ^ D
[3] ^ C
[1] ^
7456 NewCRC
[6] = D
[29] ^ D
[28] ^ D
[26] ^ D
[21] ^ D
[19] ^ D
[17] ^ D
[16] ^
7457 D
[14] ^ D
[12] ^ D
[10] ^ D
[6] ^ D
[5] ^ D
[4] ^ C
[2] ^ C
[4] ^
7459 NewCRC
[7] = D
[30] ^ D
[29] ^ D
[27] ^ D
[22] ^ D
[20] ^ D
[18] ^ D
[17] ^
7460 D
[15] ^ D
[13] ^ D
[11] ^ D
[7] ^ D
[6] ^ D
[5] ^ C
[3] ^ C
[5] ^
7464 for (i
= 0; i
< 8; i
++)
7465 crc_res
|= (NewCRC
[i
] << i
);
7471 #endif /* BNX2X_REG_H */
projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob