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bnx2x: VF fastpath
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2012 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <net/ip.h>
44 #include <net/ipv6.h>
45 #include <net/tcp.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
53 #include <linux/io.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
57
58 #include "bnx2x.h"
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_vfpf.h"
63 #include "bnx2x_sriov.h"
64 #include "bnx2x_dcb.h"
65 #include "bnx2x_sp.h"
66
67 #include <linux/firmware.h>
68 #include "bnx2x_fw_file_hdr.h"
69 /* FW files */
70 #define FW_FILE_VERSION \
71 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
72 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
73 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
74 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
75 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
76 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
77 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
78
79 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
80
81 /* Time in jiffies before concluding the transmitter is hung */
82 #define TX_TIMEOUT (5*HZ)
83
84 static char version[] =
85 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
86 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
87
88 MODULE_AUTHOR("Eliezer Tamir");
89 MODULE_DESCRIPTION("Broadcom NetXtreme II "
90 "BCM57710/57711/57711E/"
91 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
92 "57840/57840_MF Driver");
93 MODULE_LICENSE("GPL");
94 MODULE_VERSION(DRV_MODULE_VERSION);
95 MODULE_FIRMWARE(FW_FILE_NAME_E1);
96 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
97 MODULE_FIRMWARE(FW_FILE_NAME_E2);
98
99
100 int num_queues;
101 module_param(num_queues, int, 0);
102 MODULE_PARM_DESC(num_queues,
103 " Set number of queues (default is as a number of CPUs)");
104
105 static int disable_tpa;
106 module_param(disable_tpa, int, 0);
107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
108
109 #define INT_MODE_INTx 1
110 #define INT_MODE_MSI 2
111 int int_mode;
112 module_param(int_mode, int, 0);
113 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
114 "(1 INT#x; 2 MSI)");
115
116 static int dropless_fc;
117 module_param(dropless_fc, int, 0);
118 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
119
120 static int mrrs = -1;
121 module_param(mrrs, int, 0);
122 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
123
124 static int debug;
125 module_param(debug, int, 0);
126 MODULE_PARM_DESC(debug, " Default debug msglevel");
127
128
129
130 struct workqueue_struct *bnx2x_wq;
131
132 enum bnx2x_board_type {
133 BCM57710 = 0,
134 BCM57711,
135 BCM57711E,
136 BCM57712,
137 BCM57712_MF,
138 BCM57712_VF,
139 BCM57800,
140 BCM57800_MF,
141 BCM57800_VF,
142 BCM57810,
143 BCM57810_MF,
144 BCM57810_VF,
145 BCM57840_4_10,
146 BCM57840_2_20,
147 BCM57840_MF,
148 BCM57840_VF,
149 BCM57811,
150 BCM57811_MF,
151 BCM57840_O,
152 BCM57840_MFO,
153 BCM57811_VF
154 };
155
156 /* indexed by board_type, above */
157 static struct {
158 char *name;
159 } board_info[] = {
160 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
161 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
162 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
163 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
164 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
165 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
166 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
167 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
168 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
169 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
170 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
171 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
172 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
173 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
174 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
175 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
176 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
177 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
178 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
179 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
180 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
181 };
182
183 #ifndef PCI_DEVICE_ID_NX2_57710
184 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
185 #endif
186 #ifndef PCI_DEVICE_ID_NX2_57711
187 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
188 #endif
189 #ifndef PCI_DEVICE_ID_NX2_57711E
190 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
191 #endif
192 #ifndef PCI_DEVICE_ID_NX2_57712
193 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
194 #endif
195 #ifndef PCI_DEVICE_ID_NX2_57712_MF
196 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
197 #endif
198 #ifndef PCI_DEVICE_ID_NX2_57800
199 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
200 #endif
201 #ifndef PCI_DEVICE_ID_NX2_57800_MF
202 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
203 #endif
204 #ifndef PCI_DEVICE_ID_NX2_57810
205 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
206 #endif
207 #ifndef PCI_DEVICE_ID_NX2_57810_MF
208 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
209 #endif
210 #ifndef PCI_DEVICE_ID_NX2_57840_O
211 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
212 #endif
213 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
214 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
215 #endif
216 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
217 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
218 #endif
219 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
220 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
221 #endif
222 #ifndef PCI_DEVICE_ID_NX2_57840_MF
223 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
224 #endif
225 #ifndef PCI_DEVICE_ID_NX2_57811
226 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
227 #endif
228 #ifndef PCI_DEVICE_ID_NX2_57811_MF
229 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
230 #endif
231 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
232 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
233 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
234 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
235 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
236 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
237 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
238 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
239 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
240 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
241 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
242 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
243 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
244 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
245 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
246 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
247 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
248 { 0 }
249 };
250
251 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
252
253 /* Global resources for unloading a previously loaded device */
254 #define BNX2X_PREV_WAIT_NEEDED 1
255 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
256 static LIST_HEAD(bnx2x_prev_list);
257 /****************************************************************************
258 * General service functions
259 ****************************************************************************/
260
261 static void __storm_memset_dma_mapping(struct bnx2x *bp,
262 u32 addr, dma_addr_t mapping)
263 {
264 REG_WR(bp, addr, U64_LO(mapping));
265 REG_WR(bp, addr + 4, U64_HI(mapping));
266 }
267
268 static void storm_memset_spq_addr(struct bnx2x *bp,
269 dma_addr_t mapping, u16 abs_fid)
270 {
271 u32 addr = XSEM_REG_FAST_MEMORY +
272 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
273
274 __storm_memset_dma_mapping(bp, addr, mapping);
275 }
276
277 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
278 u16 pf_id)
279 {
280 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
281 pf_id);
282 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
283 pf_id);
284 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
285 pf_id);
286 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
287 pf_id);
288 }
289
290 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
291 u8 enable)
292 {
293 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
294 enable);
295 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
296 enable);
297 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
298 enable);
299 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
300 enable);
301 }
302
303 static void storm_memset_eq_data(struct bnx2x *bp,
304 struct event_ring_data *eq_data,
305 u16 pfid)
306 {
307 size_t size = sizeof(struct event_ring_data);
308
309 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
310
311 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
312 }
313
314 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
315 u16 pfid)
316 {
317 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
318 REG_WR16(bp, addr, eq_prod);
319 }
320
321 /* used only at init
322 * locking is done by mcp
323 */
324 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
325 {
326 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
327 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
328 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
329 PCICFG_VENDOR_ID_OFFSET);
330 }
331
332 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
333 {
334 u32 val;
335
336 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
337 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
338 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
339 PCICFG_VENDOR_ID_OFFSET);
340
341 return val;
342 }
343
344 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
345 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
346 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
347 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
348 #define DMAE_DP_DST_NONE "dst_addr [none]"
349
350
351 /* copy command into DMAE command memory and set DMAE command go */
352 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
353 {
354 u32 cmd_offset;
355 int i;
356
357 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
358 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
359 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
360 }
361 REG_WR(bp, dmae_reg_go_c[idx], 1);
362 }
363
364 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
365 {
366 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
367 DMAE_CMD_C_ENABLE);
368 }
369
370 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
371 {
372 return opcode & ~DMAE_CMD_SRC_RESET;
373 }
374
375 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
376 bool with_comp, u8 comp_type)
377 {
378 u32 opcode = 0;
379
380 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
381 (dst_type << DMAE_COMMAND_DST_SHIFT));
382
383 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
384
385 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
386 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
387 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
388 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
389
390 #ifdef __BIG_ENDIAN
391 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
392 #else
393 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
394 #endif
395 if (with_comp)
396 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
397 return opcode;
398 }
399
400 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
401 struct dmae_command *dmae,
402 u8 src_type, u8 dst_type)
403 {
404 memset(dmae, 0, sizeof(struct dmae_command));
405
406 /* set the opcode */
407 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
408 true, DMAE_COMP_PCI);
409
410 /* fill in the completion parameters */
411 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
412 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
413 dmae->comp_val = DMAE_COMP_VAL;
414 }
415
416 /* issue a dmae command over the init-channel and wailt for completion */
417 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
418 struct dmae_command *dmae)
419 {
420 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
421 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
422 int rc = 0;
423
424 /*
425 * Lock the dmae channel. Disable BHs to prevent a dead-lock
426 * as long as this code is called both from syscall context and
427 * from ndo_set_rx_mode() flow that may be called from BH.
428 */
429 spin_lock_bh(&bp->dmae_lock);
430
431 /* reset completion */
432 *wb_comp = 0;
433
434 /* post the command on the channel used for initializations */
435 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
436
437 /* wait for completion */
438 udelay(5);
439 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
440
441 if (!cnt ||
442 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
443 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
444 BNX2X_ERR("DMAE timeout!\n");
445 rc = DMAE_TIMEOUT;
446 goto unlock;
447 }
448 cnt--;
449 udelay(50);
450 }
451 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
452 BNX2X_ERR("DMAE PCI error!\n");
453 rc = DMAE_PCI_ERROR;
454 }
455
456 unlock:
457 spin_unlock_bh(&bp->dmae_lock);
458 return rc;
459 }
460
461 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
462 u32 len32)
463 {
464 struct dmae_command dmae;
465
466 if (!bp->dmae_ready) {
467 u32 *data = bnx2x_sp(bp, wb_data[0]);
468
469 if (CHIP_IS_E1(bp))
470 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
471 else
472 bnx2x_init_str_wr(bp, dst_addr, data, len32);
473 return;
474 }
475
476 /* set opcode and fixed command fields */
477 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
478
479 /* fill in addresses and len */
480 dmae.src_addr_lo = U64_LO(dma_addr);
481 dmae.src_addr_hi = U64_HI(dma_addr);
482 dmae.dst_addr_lo = dst_addr >> 2;
483 dmae.dst_addr_hi = 0;
484 dmae.len = len32;
485
486 /* issue the command and wait for completion */
487 bnx2x_issue_dmae_with_comp(bp, &dmae);
488 }
489
490 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
491 {
492 struct dmae_command dmae;
493
494 if (!bp->dmae_ready) {
495 u32 *data = bnx2x_sp(bp, wb_data[0]);
496 int i;
497
498 if (CHIP_IS_E1(bp))
499 for (i = 0; i < len32; i++)
500 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
501 else
502 for (i = 0; i < len32; i++)
503 data[i] = REG_RD(bp, src_addr + i*4);
504
505 return;
506 }
507
508 /* set opcode and fixed command fields */
509 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
510
511 /* fill in addresses and len */
512 dmae.src_addr_lo = src_addr >> 2;
513 dmae.src_addr_hi = 0;
514 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
515 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
516 dmae.len = len32;
517
518 /* issue the command and wait for completion */
519 bnx2x_issue_dmae_with_comp(bp, &dmae);
520 }
521
522 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
523 u32 addr, u32 len)
524 {
525 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
526 int offset = 0;
527
528 while (len > dmae_wr_max) {
529 bnx2x_write_dmae(bp, phys_addr + offset,
530 addr + offset, dmae_wr_max);
531 offset += dmae_wr_max * 4;
532 len -= dmae_wr_max;
533 }
534
535 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
536 }
537
538 static int bnx2x_mc_assert(struct bnx2x *bp)
539 {
540 char last_idx;
541 int i, rc = 0;
542 u32 row0, row1, row2, row3;
543
544 /* XSTORM */
545 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
546 XSTORM_ASSERT_LIST_INDEX_OFFSET);
547 if (last_idx)
548 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
549
550 /* print the asserts */
551 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
552
553 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
554 XSTORM_ASSERT_LIST_OFFSET(i));
555 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
556 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
557 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
558 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
559 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
560 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
561
562 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
563 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
564 i, row3, row2, row1, row0);
565 rc++;
566 } else {
567 break;
568 }
569 }
570
571 /* TSTORM */
572 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
573 TSTORM_ASSERT_LIST_INDEX_OFFSET);
574 if (last_idx)
575 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
576
577 /* print the asserts */
578 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
579
580 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
581 TSTORM_ASSERT_LIST_OFFSET(i));
582 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
583 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
584 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
585 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
586 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
587 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
588
589 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
590 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
591 i, row3, row2, row1, row0);
592 rc++;
593 } else {
594 break;
595 }
596 }
597
598 /* CSTORM */
599 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
600 CSTORM_ASSERT_LIST_INDEX_OFFSET);
601 if (last_idx)
602 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
603
604 /* print the asserts */
605 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
606
607 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
608 CSTORM_ASSERT_LIST_OFFSET(i));
609 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
610 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
611 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
612 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
613 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
614 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
615
616 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
617 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
618 i, row3, row2, row1, row0);
619 rc++;
620 } else {
621 break;
622 }
623 }
624
625 /* USTORM */
626 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
627 USTORM_ASSERT_LIST_INDEX_OFFSET);
628 if (last_idx)
629 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
630
631 /* print the asserts */
632 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
633
634 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
635 USTORM_ASSERT_LIST_OFFSET(i));
636 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
637 USTORM_ASSERT_LIST_OFFSET(i) + 4);
638 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
639 USTORM_ASSERT_LIST_OFFSET(i) + 8);
640 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
641 USTORM_ASSERT_LIST_OFFSET(i) + 12);
642
643 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
644 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
645 i, row3, row2, row1, row0);
646 rc++;
647 } else {
648 break;
649 }
650 }
651
652 return rc;
653 }
654
655 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
656 {
657 u32 addr, val;
658 u32 mark, offset;
659 __be32 data[9];
660 int word;
661 u32 trace_shmem_base;
662 if (BP_NOMCP(bp)) {
663 BNX2X_ERR("NO MCP - can not dump\n");
664 return;
665 }
666 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
667 (bp->common.bc_ver & 0xff0000) >> 16,
668 (bp->common.bc_ver & 0xff00) >> 8,
669 (bp->common.bc_ver & 0xff));
670
671 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
672 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
673 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
674
675 if (BP_PATH(bp) == 0)
676 trace_shmem_base = bp->common.shmem_base;
677 else
678 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
679 addr = trace_shmem_base - 0x800;
680
681 /* validate TRCB signature */
682 mark = REG_RD(bp, addr);
683 if (mark != MFW_TRACE_SIGNATURE) {
684 BNX2X_ERR("Trace buffer signature is missing.");
685 return ;
686 }
687
688 /* read cyclic buffer pointer */
689 addr += 4;
690 mark = REG_RD(bp, addr);
691 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
692 + ((mark + 0x3) & ~0x3) - 0x08000000;
693 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
694
695 printk("%s", lvl);
696 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
697 for (word = 0; word < 8; word++)
698 data[word] = htonl(REG_RD(bp, offset + 4*word));
699 data[8] = 0x0;
700 pr_cont("%s", (char *)data);
701 }
702 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
703 for (word = 0; word < 8; word++)
704 data[word] = htonl(REG_RD(bp, offset + 4*word));
705 data[8] = 0x0;
706 pr_cont("%s", (char *)data);
707 }
708 printk("%s" "end of fw dump\n", lvl);
709 }
710
711 static void bnx2x_fw_dump(struct bnx2x *bp)
712 {
713 bnx2x_fw_dump_lvl(bp, KERN_ERR);
714 }
715
716 void bnx2x_panic_dump(struct bnx2x *bp)
717 {
718 int i;
719 u16 j;
720 struct hc_sp_status_block_data sp_sb_data;
721 int func = BP_FUNC(bp);
722 #ifdef BNX2X_STOP_ON_ERROR
723 u16 start = 0, end = 0;
724 u8 cos;
725 #endif
726
727 bp->stats_state = STATS_STATE_DISABLED;
728 bp->eth_stats.unrecoverable_error++;
729 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
730
731 BNX2X_ERR("begin crash dump -----------------\n");
732
733 /* Indices */
734 /* Common */
735 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
736 bp->def_idx, bp->def_att_idx, bp->attn_state,
737 bp->spq_prod_idx, bp->stats_counter);
738 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
739 bp->def_status_blk->atten_status_block.attn_bits,
740 bp->def_status_blk->atten_status_block.attn_bits_ack,
741 bp->def_status_blk->atten_status_block.status_block_id,
742 bp->def_status_blk->atten_status_block.attn_bits_index);
743 BNX2X_ERR(" def (");
744 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
745 pr_cont("0x%x%s",
746 bp->def_status_blk->sp_sb.index_values[i],
747 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
748
749 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
750 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
751 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
752 i*sizeof(u32));
753
754 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
755 sp_sb_data.igu_sb_id,
756 sp_sb_data.igu_seg_id,
757 sp_sb_data.p_func.pf_id,
758 sp_sb_data.p_func.vnic_id,
759 sp_sb_data.p_func.vf_id,
760 sp_sb_data.p_func.vf_valid,
761 sp_sb_data.state);
762
763
764 for_each_eth_queue(bp, i) {
765 struct bnx2x_fastpath *fp = &bp->fp[i];
766 int loop;
767 struct hc_status_block_data_e2 sb_data_e2;
768 struct hc_status_block_data_e1x sb_data_e1x;
769 struct hc_status_block_sm *hc_sm_p =
770 CHIP_IS_E1x(bp) ?
771 sb_data_e1x.common.state_machine :
772 sb_data_e2.common.state_machine;
773 struct hc_index_data *hc_index_p =
774 CHIP_IS_E1x(bp) ?
775 sb_data_e1x.index_data :
776 sb_data_e2.index_data;
777 u8 data_size, cos;
778 u32 *sb_data_p;
779 struct bnx2x_fp_txdata txdata;
780
781 /* Rx */
782 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
783 i, fp->rx_bd_prod, fp->rx_bd_cons,
784 fp->rx_comp_prod,
785 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
786 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
787 fp->rx_sge_prod, fp->last_max_sge,
788 le16_to_cpu(fp->fp_hc_idx));
789
790 /* Tx */
791 for_each_cos_in_tx_queue(fp, cos)
792 {
793 txdata = *fp->txdata_ptr[cos];
794 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
795 i, txdata.tx_pkt_prod,
796 txdata.tx_pkt_cons, txdata.tx_bd_prod,
797 txdata.tx_bd_cons,
798 le16_to_cpu(*txdata.tx_cons_sb));
799 }
800
801 loop = CHIP_IS_E1x(bp) ?
802 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
803
804 /* host sb data */
805
806 if (IS_FCOE_FP(fp))
807 continue;
808
809 BNX2X_ERR(" run indexes (");
810 for (j = 0; j < HC_SB_MAX_SM; j++)
811 pr_cont("0x%x%s",
812 fp->sb_running_index[j],
813 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
814
815 BNX2X_ERR(" indexes (");
816 for (j = 0; j < loop; j++)
817 pr_cont("0x%x%s",
818 fp->sb_index_values[j],
819 (j == loop - 1) ? ")" : " ");
820 /* fw sb data */
821 data_size = CHIP_IS_E1x(bp) ?
822 sizeof(struct hc_status_block_data_e1x) :
823 sizeof(struct hc_status_block_data_e2);
824 data_size /= sizeof(u32);
825 sb_data_p = CHIP_IS_E1x(bp) ?
826 (u32 *)&sb_data_e1x :
827 (u32 *)&sb_data_e2;
828 /* copy sb data in here */
829 for (j = 0; j < data_size; j++)
830 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
831 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
832 j * sizeof(u32));
833
834 if (!CHIP_IS_E1x(bp)) {
835 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
836 sb_data_e2.common.p_func.pf_id,
837 sb_data_e2.common.p_func.vf_id,
838 sb_data_e2.common.p_func.vf_valid,
839 sb_data_e2.common.p_func.vnic_id,
840 sb_data_e2.common.same_igu_sb_1b,
841 sb_data_e2.common.state);
842 } else {
843 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
844 sb_data_e1x.common.p_func.pf_id,
845 sb_data_e1x.common.p_func.vf_id,
846 sb_data_e1x.common.p_func.vf_valid,
847 sb_data_e1x.common.p_func.vnic_id,
848 sb_data_e1x.common.same_igu_sb_1b,
849 sb_data_e1x.common.state);
850 }
851
852 /* SB_SMs data */
853 for (j = 0; j < HC_SB_MAX_SM; j++) {
854 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
855 j, hc_sm_p[j].__flags,
856 hc_sm_p[j].igu_sb_id,
857 hc_sm_p[j].igu_seg_id,
858 hc_sm_p[j].time_to_expire,
859 hc_sm_p[j].timer_value);
860 }
861
862 /* Indecies data */
863 for (j = 0; j < loop; j++) {
864 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
865 hc_index_p[j].flags,
866 hc_index_p[j].timeout);
867 }
868 }
869
870 #ifdef BNX2X_STOP_ON_ERROR
871 /* Rings */
872 /* Rx */
873 for_each_valid_rx_queue(bp, i) {
874 struct bnx2x_fastpath *fp = &bp->fp[i];
875
876 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
877 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
878 for (j = start; j != end; j = RX_BD(j + 1)) {
879 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
880 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
881
882 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
883 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
884 }
885
886 start = RX_SGE(fp->rx_sge_prod);
887 end = RX_SGE(fp->last_max_sge);
888 for (j = start; j != end; j = RX_SGE(j + 1)) {
889 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
890 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
891
892 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
893 i, j, rx_sge[1], rx_sge[0], sw_page->page);
894 }
895
896 start = RCQ_BD(fp->rx_comp_cons - 10);
897 end = RCQ_BD(fp->rx_comp_cons + 503);
898 for (j = start; j != end; j = RCQ_BD(j + 1)) {
899 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
900
901 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
902 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
903 }
904 }
905
906 /* Tx */
907 for_each_valid_tx_queue(bp, i) {
908 struct bnx2x_fastpath *fp = &bp->fp[i];
909 for_each_cos_in_tx_queue(fp, cos) {
910 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
911
912 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
913 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
914 for (j = start; j != end; j = TX_BD(j + 1)) {
915 struct sw_tx_bd *sw_bd =
916 &txdata->tx_buf_ring[j];
917
918 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
919 i, cos, j, sw_bd->skb,
920 sw_bd->first_bd);
921 }
922
923 start = TX_BD(txdata->tx_bd_cons - 10);
924 end = TX_BD(txdata->tx_bd_cons + 254);
925 for (j = start; j != end; j = TX_BD(j + 1)) {
926 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
927
928 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
929 i, cos, j, tx_bd[0], tx_bd[1],
930 tx_bd[2], tx_bd[3]);
931 }
932 }
933 }
934 #endif
935 bnx2x_fw_dump(bp);
936 bnx2x_mc_assert(bp);
937 BNX2X_ERR("end crash dump -----------------\n");
938 }
939
940 /*
941 * FLR Support for E2
942 *
943 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
944 * initialization.
945 */
946 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
947 #define FLR_WAIT_INTERVAL 50 /* usec */
948 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
949
950 struct pbf_pN_buf_regs {
951 int pN;
952 u32 init_crd;
953 u32 crd;
954 u32 crd_freed;
955 };
956
957 struct pbf_pN_cmd_regs {
958 int pN;
959 u32 lines_occup;
960 u32 lines_freed;
961 };
962
963 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
964 struct pbf_pN_buf_regs *regs,
965 u32 poll_count)
966 {
967 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
968 u32 cur_cnt = poll_count;
969
970 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
971 crd = crd_start = REG_RD(bp, regs->crd);
972 init_crd = REG_RD(bp, regs->init_crd);
973
974 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
975 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
976 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
977
978 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
979 (init_crd - crd_start))) {
980 if (cur_cnt--) {
981 udelay(FLR_WAIT_INTERVAL);
982 crd = REG_RD(bp, regs->crd);
983 crd_freed = REG_RD(bp, regs->crd_freed);
984 } else {
985 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
986 regs->pN);
987 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
988 regs->pN, crd);
989 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
990 regs->pN, crd_freed);
991 break;
992 }
993 }
994 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
995 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
996 }
997
998 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
999 struct pbf_pN_cmd_regs *regs,
1000 u32 poll_count)
1001 {
1002 u32 occup, to_free, freed, freed_start;
1003 u32 cur_cnt = poll_count;
1004
1005 occup = to_free = REG_RD(bp, regs->lines_occup);
1006 freed = freed_start = REG_RD(bp, regs->lines_freed);
1007
1008 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1009 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1010
1011 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1012 if (cur_cnt--) {
1013 udelay(FLR_WAIT_INTERVAL);
1014 occup = REG_RD(bp, regs->lines_occup);
1015 freed = REG_RD(bp, regs->lines_freed);
1016 } else {
1017 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1018 regs->pN);
1019 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1020 regs->pN, occup);
1021 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1022 regs->pN, freed);
1023 break;
1024 }
1025 }
1026 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1027 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1028 }
1029
1030 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1031 u32 expected, u32 poll_count)
1032 {
1033 u32 cur_cnt = poll_count;
1034 u32 val;
1035
1036 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1037 udelay(FLR_WAIT_INTERVAL);
1038
1039 return val;
1040 }
1041
1042 static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1043 char *msg, u32 poll_cnt)
1044 {
1045 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1046 if (val != 0) {
1047 BNX2X_ERR("%s usage count=%d\n", msg, val);
1048 return 1;
1049 }
1050 return 0;
1051 }
1052
1053 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1054 {
1055 /* adjust polling timeout */
1056 if (CHIP_REV_IS_EMUL(bp))
1057 return FLR_POLL_CNT * 2000;
1058
1059 if (CHIP_REV_IS_FPGA(bp))
1060 return FLR_POLL_CNT * 120;
1061
1062 return FLR_POLL_CNT;
1063 }
1064
1065 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1066 {
1067 struct pbf_pN_cmd_regs cmd_regs[] = {
1068 {0, (CHIP_IS_E3B0(bp)) ?
1069 PBF_REG_TQ_OCCUPANCY_Q0 :
1070 PBF_REG_P0_TQ_OCCUPANCY,
1071 (CHIP_IS_E3B0(bp)) ?
1072 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1073 PBF_REG_P0_TQ_LINES_FREED_CNT},
1074 {1, (CHIP_IS_E3B0(bp)) ?
1075 PBF_REG_TQ_OCCUPANCY_Q1 :
1076 PBF_REG_P1_TQ_OCCUPANCY,
1077 (CHIP_IS_E3B0(bp)) ?
1078 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1079 PBF_REG_P1_TQ_LINES_FREED_CNT},
1080 {4, (CHIP_IS_E3B0(bp)) ?
1081 PBF_REG_TQ_OCCUPANCY_LB_Q :
1082 PBF_REG_P4_TQ_OCCUPANCY,
1083 (CHIP_IS_E3B0(bp)) ?
1084 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1085 PBF_REG_P4_TQ_LINES_FREED_CNT}
1086 };
1087
1088 struct pbf_pN_buf_regs buf_regs[] = {
1089 {0, (CHIP_IS_E3B0(bp)) ?
1090 PBF_REG_INIT_CRD_Q0 :
1091 PBF_REG_P0_INIT_CRD ,
1092 (CHIP_IS_E3B0(bp)) ?
1093 PBF_REG_CREDIT_Q0 :
1094 PBF_REG_P0_CREDIT,
1095 (CHIP_IS_E3B0(bp)) ?
1096 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1097 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1098 {1, (CHIP_IS_E3B0(bp)) ?
1099 PBF_REG_INIT_CRD_Q1 :
1100 PBF_REG_P1_INIT_CRD,
1101 (CHIP_IS_E3B0(bp)) ?
1102 PBF_REG_CREDIT_Q1 :
1103 PBF_REG_P1_CREDIT,
1104 (CHIP_IS_E3B0(bp)) ?
1105 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1106 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1107 {4, (CHIP_IS_E3B0(bp)) ?
1108 PBF_REG_INIT_CRD_LB_Q :
1109 PBF_REG_P4_INIT_CRD,
1110 (CHIP_IS_E3B0(bp)) ?
1111 PBF_REG_CREDIT_LB_Q :
1112 PBF_REG_P4_CREDIT,
1113 (CHIP_IS_E3B0(bp)) ?
1114 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1115 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1116 };
1117
1118 int i;
1119
1120 /* Verify the command queues are flushed P0, P1, P4 */
1121 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1122 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1123
1124
1125 /* Verify the transmission buffers are flushed P0, P1, P4 */
1126 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1127 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1128 }
1129
1130 #define OP_GEN_PARAM(param) \
1131 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1132
1133 #define OP_GEN_TYPE(type) \
1134 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1135
1136 #define OP_GEN_AGG_VECT(index) \
1137 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1138
1139
1140 static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1141 u32 poll_cnt)
1142 {
1143 struct sdm_op_gen op_gen = {0};
1144
1145 u32 comp_addr = BAR_CSTRORM_INTMEM +
1146 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1147 int ret = 0;
1148
1149 if (REG_RD(bp, comp_addr)) {
1150 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1151 return 1;
1152 }
1153
1154 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1155 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1156 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1157 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1158
1159 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1160 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1161
1162 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1163 BNX2X_ERR("FW final cleanup did not succeed\n");
1164 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1165 (REG_RD(bp, comp_addr)));
1166 ret = 1;
1167 }
1168 /* Zero completion for nxt FLR */
1169 REG_WR(bp, comp_addr, 0);
1170
1171 return ret;
1172 }
1173
1174 static u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1175 {
1176 u16 status;
1177
1178 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1179 return status & PCI_EXP_DEVSTA_TRPND;
1180 }
1181
1182 /* PF FLR specific routines
1183 */
1184 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1185 {
1186
1187 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1188 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1189 CFC_REG_NUM_LCIDS_INSIDE_PF,
1190 "CFC PF usage counter timed out",
1191 poll_cnt))
1192 return 1;
1193
1194
1195 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1196 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1197 DORQ_REG_PF_USAGE_CNT,
1198 "DQ PF usage counter timed out",
1199 poll_cnt))
1200 return 1;
1201
1202 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1203 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1204 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1205 "QM PF usage counter timed out",
1206 poll_cnt))
1207 return 1;
1208
1209 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1210 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1211 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1212 "Timers VNIC usage counter timed out",
1213 poll_cnt))
1214 return 1;
1215 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1216 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1217 "Timers NUM_SCANS usage counter timed out",
1218 poll_cnt))
1219 return 1;
1220
1221 /* Wait DMAE PF usage counter to zero */
1222 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1223 dmae_reg_go_c[INIT_DMAE_C(bp)],
1224 "DMAE dommand register timed out",
1225 poll_cnt))
1226 return 1;
1227
1228 return 0;
1229 }
1230
1231 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1232 {
1233 u32 val;
1234
1235 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1236 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1237
1238 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1239 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1240
1241 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1242 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1243
1244 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1245 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1246
1247 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1248 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1249
1250 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1251 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1252
1253 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1254 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1255
1256 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1257 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1258 val);
1259 }
1260
1261 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1262 {
1263 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1264
1265 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1266
1267 /* Re-enable PF target read access */
1268 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1269
1270 /* Poll HW usage counters */
1271 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1272 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1273 return -EBUSY;
1274
1275 /* Zero the igu 'trailing edge' and 'leading edge' */
1276
1277 /* Send the FW cleanup command */
1278 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1279 return -EBUSY;
1280
1281 /* ATC cleanup */
1282
1283 /* Verify TX hw is flushed */
1284 bnx2x_tx_hw_flushed(bp, poll_cnt);
1285
1286 /* Wait 100ms (not adjusted according to platform) */
1287 msleep(100);
1288
1289 /* Verify no pending pci transactions */
1290 if (bnx2x_is_pcie_pending(bp->pdev))
1291 BNX2X_ERR("PCIE Transactions still pending\n");
1292
1293 /* Debug */
1294 bnx2x_hw_enable_status(bp);
1295
1296 /*
1297 * Master enable - Due to WB DMAE writes performed before this
1298 * register is re-initialized as part of the regular function init
1299 */
1300 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1301
1302 return 0;
1303 }
1304
1305 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1306 {
1307 int port = BP_PORT(bp);
1308 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1309 u32 val = REG_RD(bp, addr);
1310 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1311 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1312 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1313
1314 if (msix) {
1315 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1316 HC_CONFIG_0_REG_INT_LINE_EN_0);
1317 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1318 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1319 if (single_msix)
1320 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1321 } else if (msi) {
1322 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1323 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1324 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1325 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1326 } else {
1327 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1328 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1329 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1330 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1331
1332 if (!CHIP_IS_E1(bp)) {
1333 DP(NETIF_MSG_IFUP,
1334 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1335
1336 REG_WR(bp, addr, val);
1337
1338 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1339 }
1340 }
1341
1342 if (CHIP_IS_E1(bp))
1343 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1344
1345 DP(NETIF_MSG_IFUP,
1346 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1347 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1348
1349 REG_WR(bp, addr, val);
1350 /*
1351 * Ensure that HC_CONFIG is written before leading/trailing edge config
1352 */
1353 mmiowb();
1354 barrier();
1355
1356 if (!CHIP_IS_E1(bp)) {
1357 /* init leading/trailing edge */
1358 if (IS_MF(bp)) {
1359 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1360 if (bp->port.pmf)
1361 /* enable nig and gpio3 attention */
1362 val |= 0x1100;
1363 } else
1364 val = 0xffff;
1365
1366 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1367 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1368 }
1369
1370 /* Make sure that interrupts are indeed enabled from here on */
1371 mmiowb();
1372 }
1373
1374 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1375 {
1376 u32 val;
1377 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1378 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1379 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1380
1381 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1382
1383 if (msix) {
1384 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1385 IGU_PF_CONF_SINGLE_ISR_EN);
1386 val |= (IGU_PF_CONF_FUNC_EN |
1387 IGU_PF_CONF_MSI_MSIX_EN |
1388 IGU_PF_CONF_ATTN_BIT_EN);
1389
1390 if (single_msix)
1391 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1392 } else if (msi) {
1393 val &= ~IGU_PF_CONF_INT_LINE_EN;
1394 val |= (IGU_PF_CONF_FUNC_EN |
1395 IGU_PF_CONF_MSI_MSIX_EN |
1396 IGU_PF_CONF_ATTN_BIT_EN |
1397 IGU_PF_CONF_SINGLE_ISR_EN);
1398 } else {
1399 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1400 val |= (IGU_PF_CONF_FUNC_EN |
1401 IGU_PF_CONF_INT_LINE_EN |
1402 IGU_PF_CONF_ATTN_BIT_EN |
1403 IGU_PF_CONF_SINGLE_ISR_EN);
1404 }
1405
1406 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1407 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1408
1409 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1410
1411 if (val & IGU_PF_CONF_INT_LINE_EN)
1412 pci_intx(bp->pdev, true);
1413
1414 barrier();
1415
1416 /* init leading/trailing edge */
1417 if (IS_MF(bp)) {
1418 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1419 if (bp->port.pmf)
1420 /* enable nig and gpio3 attention */
1421 val |= 0x1100;
1422 } else
1423 val = 0xffff;
1424
1425 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1426 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1427
1428 /* Make sure that interrupts are indeed enabled from here on */
1429 mmiowb();
1430 }
1431
1432 void bnx2x_int_enable(struct bnx2x *bp)
1433 {
1434 if (bp->common.int_block == INT_BLOCK_HC)
1435 bnx2x_hc_int_enable(bp);
1436 else
1437 bnx2x_igu_int_enable(bp);
1438 }
1439
1440 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1441 {
1442 int port = BP_PORT(bp);
1443 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1444 u32 val = REG_RD(bp, addr);
1445
1446 /*
1447 * in E1 we must use only PCI configuration space to disable
1448 * MSI/MSIX capablility
1449 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1450 */
1451 if (CHIP_IS_E1(bp)) {
1452 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1453 * Use mask register to prevent from HC sending interrupts
1454 * after we exit the function
1455 */
1456 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1457
1458 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1459 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1460 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1461 } else
1462 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1463 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1464 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1465 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1466
1467 DP(NETIF_MSG_IFDOWN,
1468 "write %x to HC %d (addr 0x%x)\n",
1469 val, port, addr);
1470
1471 /* flush all outstanding writes */
1472 mmiowb();
1473
1474 REG_WR(bp, addr, val);
1475 if (REG_RD(bp, addr) != val)
1476 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1477 }
1478
1479 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1480 {
1481 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1482
1483 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1484 IGU_PF_CONF_INT_LINE_EN |
1485 IGU_PF_CONF_ATTN_BIT_EN);
1486
1487 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
1488
1489 /* flush all outstanding writes */
1490 mmiowb();
1491
1492 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1493 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1494 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1495 }
1496
1497 static void bnx2x_int_disable(struct bnx2x *bp)
1498 {
1499 if (bp->common.int_block == INT_BLOCK_HC)
1500 bnx2x_hc_int_disable(bp);
1501 else
1502 bnx2x_igu_int_disable(bp);
1503 }
1504
1505 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1506 {
1507 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1508 int i, offset;
1509
1510 if (disable_hw)
1511 /* prevent the HW from sending interrupts */
1512 bnx2x_int_disable(bp);
1513
1514 /* make sure all ISRs are done */
1515 if (msix) {
1516 synchronize_irq(bp->msix_table[0].vector);
1517 offset = 1;
1518 if (CNIC_SUPPORT(bp))
1519 offset++;
1520 for_each_eth_queue(bp, i)
1521 synchronize_irq(bp->msix_table[offset++].vector);
1522 } else
1523 synchronize_irq(bp->pdev->irq);
1524
1525 /* make sure sp_task is not running */
1526 cancel_delayed_work(&bp->sp_task);
1527 cancel_delayed_work(&bp->period_task);
1528 flush_workqueue(bnx2x_wq);
1529 }
1530
1531 /* fast path */
1532
1533 /*
1534 * General service functions
1535 */
1536
1537 /* Return true if succeeded to acquire the lock */
1538 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1539 {
1540 u32 lock_status;
1541 u32 resource_bit = (1 << resource);
1542 int func = BP_FUNC(bp);
1543 u32 hw_lock_control_reg;
1544
1545 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1546 "Trying to take a lock on resource %d\n", resource);
1547
1548 /* Validating that the resource is within range */
1549 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1550 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1551 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1552 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1553 return false;
1554 }
1555
1556 if (func <= 5)
1557 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1558 else
1559 hw_lock_control_reg =
1560 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1561
1562 /* Try to acquire the lock */
1563 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1564 lock_status = REG_RD(bp, hw_lock_control_reg);
1565 if (lock_status & resource_bit)
1566 return true;
1567
1568 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1569 "Failed to get a lock on resource %d\n", resource);
1570 return false;
1571 }
1572
1573 /**
1574 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1575 *
1576 * @bp: driver handle
1577 *
1578 * Returns the recovery leader resource id according to the engine this function
1579 * belongs to. Currently only only 2 engines is supported.
1580 */
1581 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1582 {
1583 if (BP_PATH(bp))
1584 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1585 else
1586 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1587 }
1588
1589 /**
1590 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1591 *
1592 * @bp: driver handle
1593 *
1594 * Tries to aquire a leader lock for current engine.
1595 */
1596 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1597 {
1598 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1599 }
1600
1601 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1602
1603
1604 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1605 {
1606 struct bnx2x *bp = fp->bp;
1607 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1608 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1609 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1610 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1611
1612 DP(BNX2X_MSG_SP,
1613 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1614 fp->index, cid, command, bp->state,
1615 rr_cqe->ramrod_cqe.ramrod_type);
1616
1617 switch (command) {
1618 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1619 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1620 drv_cmd = BNX2X_Q_CMD_UPDATE;
1621 break;
1622
1623 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1624 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1625 drv_cmd = BNX2X_Q_CMD_SETUP;
1626 break;
1627
1628 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1629 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1630 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1631 break;
1632
1633 case (RAMROD_CMD_ID_ETH_HALT):
1634 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1635 drv_cmd = BNX2X_Q_CMD_HALT;
1636 break;
1637
1638 case (RAMROD_CMD_ID_ETH_TERMINATE):
1639 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1640 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1641 break;
1642
1643 case (RAMROD_CMD_ID_ETH_EMPTY):
1644 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1645 drv_cmd = BNX2X_Q_CMD_EMPTY;
1646 break;
1647
1648 default:
1649 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1650 command, fp->index);
1651 return;
1652 }
1653
1654 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1655 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1656 /* q_obj->complete_cmd() failure means that this was
1657 * an unexpected completion.
1658 *
1659 * In this case we don't want to increase the bp->spq_left
1660 * because apparently we haven't sent this command the first
1661 * place.
1662 */
1663 #ifdef BNX2X_STOP_ON_ERROR
1664 bnx2x_panic();
1665 #else
1666 return;
1667 #endif
1668
1669 smp_mb__before_atomic_inc();
1670 atomic_inc(&bp->cq_spq_left);
1671 /* push the change in bp->spq_left and towards the memory */
1672 smp_mb__after_atomic_inc();
1673
1674 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1675
1676 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1677 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1678 /* if Q update ramrod is completed for last Q in AFEX vif set
1679 * flow, then ACK MCP at the end
1680 *
1681 * mark pending ACK to MCP bit.
1682 * prevent case that both bits are cleared.
1683 * At the end of load/unload driver checks that
1684 * sp_state is cleaerd, and this order prevents
1685 * races
1686 */
1687 smp_mb__before_clear_bit();
1688 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1689 wmb();
1690 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1691 smp_mb__after_clear_bit();
1692
1693 /* schedule workqueue to send ack to MCP */
1694 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1695 }
1696
1697 return;
1698 }
1699
1700 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1701 {
1702 struct bnx2x *bp = netdev_priv(dev_instance);
1703 u16 status = bnx2x_ack_int(bp);
1704 u16 mask;
1705 int i;
1706 u8 cos;
1707
1708 /* Return here if interrupt is shared and it's not for us */
1709 if (unlikely(status == 0)) {
1710 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1711 return IRQ_NONE;
1712 }
1713 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1714
1715 #ifdef BNX2X_STOP_ON_ERROR
1716 if (unlikely(bp->panic))
1717 return IRQ_HANDLED;
1718 #endif
1719
1720 for_each_eth_queue(bp, i) {
1721 struct bnx2x_fastpath *fp = &bp->fp[i];
1722
1723 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1724 if (status & mask) {
1725 /* Handle Rx or Tx according to SB id */
1726 prefetch(fp->rx_cons_sb);
1727 for_each_cos_in_tx_queue(fp, cos)
1728 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1729 prefetch(&fp->sb_running_index[SM_RX_ID]);
1730 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1731 status &= ~mask;
1732 }
1733 }
1734
1735 if (CNIC_SUPPORT(bp)) {
1736 mask = 0x2;
1737 if (status & (mask | 0x1)) {
1738 struct cnic_ops *c_ops = NULL;
1739
1740 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1741 rcu_read_lock();
1742 c_ops = rcu_dereference(bp->cnic_ops);
1743 if (c_ops)
1744 c_ops->cnic_handler(bp->cnic_data,
1745 NULL);
1746 rcu_read_unlock();
1747 }
1748
1749 status &= ~mask;
1750 }
1751 }
1752
1753 if (unlikely(status & 0x1)) {
1754 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1755
1756 status &= ~0x1;
1757 if (!status)
1758 return IRQ_HANDLED;
1759 }
1760
1761 if (unlikely(status))
1762 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1763 status);
1764
1765 return IRQ_HANDLED;
1766 }
1767
1768 /* Link */
1769
1770 /*
1771 * General service functions
1772 */
1773
1774 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1775 {
1776 u32 lock_status;
1777 u32 resource_bit = (1 << resource);
1778 int func = BP_FUNC(bp);
1779 u32 hw_lock_control_reg;
1780 int cnt;
1781
1782 /* Validating that the resource is within range */
1783 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1784 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1785 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1786 return -EINVAL;
1787 }
1788
1789 if (func <= 5) {
1790 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1791 } else {
1792 hw_lock_control_reg =
1793 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1794 }
1795
1796 /* Validating that the resource is not already taken */
1797 lock_status = REG_RD(bp, hw_lock_control_reg);
1798 if (lock_status & resource_bit) {
1799 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1800 lock_status, resource_bit);
1801 return -EEXIST;
1802 }
1803
1804 /* Try for 5 second every 5ms */
1805 for (cnt = 0; cnt < 1000; cnt++) {
1806 /* Try to acquire the lock */
1807 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1808 lock_status = REG_RD(bp, hw_lock_control_reg);
1809 if (lock_status & resource_bit)
1810 return 0;
1811
1812 msleep(5);
1813 }
1814 BNX2X_ERR("Timeout\n");
1815 return -EAGAIN;
1816 }
1817
1818 int bnx2x_release_leader_lock(struct bnx2x *bp)
1819 {
1820 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1821 }
1822
1823 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1824 {
1825 u32 lock_status;
1826 u32 resource_bit = (1 << resource);
1827 int func = BP_FUNC(bp);
1828 u32 hw_lock_control_reg;
1829
1830 /* Validating that the resource is within range */
1831 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1832 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1833 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1834 return -EINVAL;
1835 }
1836
1837 if (func <= 5) {
1838 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1839 } else {
1840 hw_lock_control_reg =
1841 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1842 }
1843
1844 /* Validating that the resource is currently taken */
1845 lock_status = REG_RD(bp, hw_lock_control_reg);
1846 if (!(lock_status & resource_bit)) {
1847 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1848 lock_status, resource_bit);
1849 return -EFAULT;
1850 }
1851
1852 REG_WR(bp, hw_lock_control_reg, resource_bit);
1853 return 0;
1854 }
1855
1856
1857 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1858 {
1859 /* The GPIO should be swapped if swap register is set and active */
1860 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1861 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1862 int gpio_shift = gpio_num +
1863 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1864 u32 gpio_mask = (1 << gpio_shift);
1865 u32 gpio_reg;
1866 int value;
1867
1868 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1869 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1870 return -EINVAL;
1871 }
1872
1873 /* read GPIO value */
1874 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1875
1876 /* get the requested pin value */
1877 if ((gpio_reg & gpio_mask) == gpio_mask)
1878 value = 1;
1879 else
1880 value = 0;
1881
1882 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1883
1884 return value;
1885 }
1886
1887 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1888 {
1889 /* The GPIO should be swapped if swap register is set and active */
1890 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1891 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1892 int gpio_shift = gpio_num +
1893 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1894 u32 gpio_mask = (1 << gpio_shift);
1895 u32 gpio_reg;
1896
1897 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1898 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1899 return -EINVAL;
1900 }
1901
1902 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1903 /* read GPIO and mask except the float bits */
1904 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1905
1906 switch (mode) {
1907 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1908 DP(NETIF_MSG_LINK,
1909 "Set GPIO %d (shift %d) -> output low\n",
1910 gpio_num, gpio_shift);
1911 /* clear FLOAT and set CLR */
1912 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1913 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1914 break;
1915
1916 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1917 DP(NETIF_MSG_LINK,
1918 "Set GPIO %d (shift %d) -> output high\n",
1919 gpio_num, gpio_shift);
1920 /* clear FLOAT and set SET */
1921 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1922 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1923 break;
1924
1925 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1926 DP(NETIF_MSG_LINK,
1927 "Set GPIO %d (shift %d) -> input\n",
1928 gpio_num, gpio_shift);
1929 /* set FLOAT */
1930 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1931 break;
1932
1933 default:
1934 break;
1935 }
1936
1937 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1938 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1939
1940 return 0;
1941 }
1942
1943 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1944 {
1945 u32 gpio_reg = 0;
1946 int rc = 0;
1947
1948 /* Any port swapping should be handled by caller. */
1949
1950 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1951 /* read GPIO and mask except the float bits */
1952 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1953 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1954 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1955 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1956
1957 switch (mode) {
1958 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1959 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
1960 /* set CLR */
1961 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
1962 break;
1963
1964 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1965 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
1966 /* set SET */
1967 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
1968 break;
1969
1970 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1971 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
1972 /* set FLOAT */
1973 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1974 break;
1975
1976 default:
1977 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
1978 rc = -EINVAL;
1979 break;
1980 }
1981
1982 if (rc == 0)
1983 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1984
1985 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1986
1987 return rc;
1988 }
1989
1990 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1991 {
1992 /* The GPIO should be swapped if swap register is set and active */
1993 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1994 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1995 int gpio_shift = gpio_num +
1996 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1997 u32 gpio_mask = (1 << gpio_shift);
1998 u32 gpio_reg;
1999
2000 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2001 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2002 return -EINVAL;
2003 }
2004
2005 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2006 /* read GPIO int */
2007 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2008
2009 switch (mode) {
2010 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2011 DP(NETIF_MSG_LINK,
2012 "Clear GPIO INT %d (shift %d) -> output low\n",
2013 gpio_num, gpio_shift);
2014 /* clear SET and set CLR */
2015 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2016 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2017 break;
2018
2019 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2020 DP(NETIF_MSG_LINK,
2021 "Set GPIO INT %d (shift %d) -> output high\n",
2022 gpio_num, gpio_shift);
2023 /* clear CLR and set SET */
2024 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2025 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2026 break;
2027
2028 default:
2029 break;
2030 }
2031
2032 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2033 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2034
2035 return 0;
2036 }
2037
2038 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2039 {
2040 u32 spio_reg;
2041
2042 /* Only 2 SPIOs are configurable */
2043 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2044 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2045 return -EINVAL;
2046 }
2047
2048 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2049 /* read SPIO and mask except the float bits */
2050 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2051
2052 switch (mode) {
2053 case MISC_SPIO_OUTPUT_LOW:
2054 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2055 /* clear FLOAT and set CLR */
2056 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2057 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2058 break;
2059
2060 case MISC_SPIO_OUTPUT_HIGH:
2061 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2062 /* clear FLOAT and set SET */
2063 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2064 spio_reg |= (spio << MISC_SPIO_SET_POS);
2065 break;
2066
2067 case MISC_SPIO_INPUT_HI_Z:
2068 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2069 /* set FLOAT */
2070 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2071 break;
2072
2073 default:
2074 break;
2075 }
2076
2077 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2078 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2079
2080 return 0;
2081 }
2082
2083 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2084 {
2085 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2086 switch (bp->link_vars.ieee_fc &
2087 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2088 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2089 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2090 ADVERTISED_Pause);
2091 break;
2092
2093 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2094 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2095 ADVERTISED_Pause);
2096 break;
2097
2098 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2099 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2100 break;
2101
2102 default:
2103 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2104 ADVERTISED_Pause);
2105 break;
2106 }
2107 }
2108
2109 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2110 {
2111 /* Initialize link parameters structure variables
2112 * It is recommended to turn off RX FC for jumbo frames
2113 * for better performance
2114 */
2115 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2116 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2117 else
2118 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2119 }
2120
2121 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2122 {
2123 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2124 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2125
2126 if (!BP_NOMCP(bp)) {
2127 bnx2x_set_requested_fc(bp);
2128 bnx2x_acquire_phy_lock(bp);
2129
2130 if (load_mode == LOAD_DIAG) {
2131 struct link_params *lp = &bp->link_params;
2132 lp->loopback_mode = LOOPBACK_XGXS;
2133 /* do PHY loopback at 10G speed, if possible */
2134 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2135 if (lp->speed_cap_mask[cfx_idx] &
2136 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2137 lp->req_line_speed[cfx_idx] =
2138 SPEED_10000;
2139 else
2140 lp->req_line_speed[cfx_idx] =
2141 SPEED_1000;
2142 }
2143 }
2144
2145 if (load_mode == LOAD_LOOPBACK_EXT) {
2146 struct link_params *lp = &bp->link_params;
2147 lp->loopback_mode = LOOPBACK_EXT;
2148 }
2149
2150 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2151
2152 bnx2x_release_phy_lock(bp);
2153
2154 bnx2x_calc_fc_adv(bp);
2155
2156 if (bp->link_vars.link_up) {
2157 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2158 bnx2x_link_report(bp);
2159 }
2160 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2161 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2162 return rc;
2163 }
2164 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2165 return -EINVAL;
2166 }
2167
2168 void bnx2x_link_set(struct bnx2x *bp)
2169 {
2170 if (!BP_NOMCP(bp)) {
2171 bnx2x_acquire_phy_lock(bp);
2172 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2173 bnx2x_release_phy_lock(bp);
2174
2175 bnx2x_calc_fc_adv(bp);
2176 } else
2177 BNX2X_ERR("Bootcode is missing - can not set link\n");
2178 }
2179
2180 static void bnx2x__link_reset(struct bnx2x *bp)
2181 {
2182 if (!BP_NOMCP(bp)) {
2183 bnx2x_acquire_phy_lock(bp);
2184 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2185 bnx2x_release_phy_lock(bp);
2186 } else
2187 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2188 }
2189
2190 void bnx2x_force_link_reset(struct bnx2x *bp)
2191 {
2192 bnx2x_acquire_phy_lock(bp);
2193 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2194 bnx2x_release_phy_lock(bp);
2195 }
2196
2197 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2198 {
2199 u8 rc = 0;
2200
2201 if (!BP_NOMCP(bp)) {
2202 bnx2x_acquire_phy_lock(bp);
2203 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2204 is_serdes);
2205 bnx2x_release_phy_lock(bp);
2206 } else
2207 BNX2X_ERR("Bootcode is missing - can not test link\n");
2208
2209 return rc;
2210 }
2211
2212
2213 /* Calculates the sum of vn_min_rates.
2214 It's needed for further normalizing of the min_rates.
2215 Returns:
2216 sum of vn_min_rates.
2217 or
2218 0 - if all the min_rates are 0.
2219 In the later case fainess algorithm should be deactivated.
2220 If not all min_rates are zero then those that are zeroes will be set to 1.
2221 */
2222 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2223 struct cmng_init_input *input)
2224 {
2225 int all_zero = 1;
2226 int vn;
2227
2228 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2229 u32 vn_cfg = bp->mf_config[vn];
2230 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2231 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2232
2233 /* Skip hidden vns */
2234 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2235 vn_min_rate = 0;
2236 /* If min rate is zero - set it to 1 */
2237 else if (!vn_min_rate)
2238 vn_min_rate = DEF_MIN_RATE;
2239 else
2240 all_zero = 0;
2241
2242 input->vnic_min_rate[vn] = vn_min_rate;
2243 }
2244
2245 /* if ETS or all min rates are zeros - disable fairness */
2246 if (BNX2X_IS_ETS_ENABLED(bp)) {
2247 input->flags.cmng_enables &=
2248 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2249 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2250 } else if (all_zero) {
2251 input->flags.cmng_enables &=
2252 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2253 DP(NETIF_MSG_IFUP,
2254 "All MIN values are zeroes fairness will be disabled\n");
2255 } else
2256 input->flags.cmng_enables |=
2257 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2258 }
2259
2260 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2261 struct cmng_init_input *input)
2262 {
2263 u16 vn_max_rate;
2264 u32 vn_cfg = bp->mf_config[vn];
2265
2266 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2267 vn_max_rate = 0;
2268 else {
2269 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2270
2271 if (IS_MF_SI(bp)) {
2272 /* maxCfg in percents of linkspeed */
2273 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2274 } else /* SD modes */
2275 /* maxCfg is absolute in 100Mb units */
2276 vn_max_rate = maxCfg * 100;
2277 }
2278
2279 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2280
2281 input->vnic_max_rate[vn] = vn_max_rate;
2282 }
2283
2284
2285 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2286 {
2287 if (CHIP_REV_IS_SLOW(bp))
2288 return CMNG_FNS_NONE;
2289 if (IS_MF(bp))
2290 return CMNG_FNS_MINMAX;
2291
2292 return CMNG_FNS_NONE;
2293 }
2294
2295 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2296 {
2297 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2298
2299 if (BP_NOMCP(bp))
2300 return; /* what should be the default bvalue in this case */
2301
2302 /* For 2 port configuration the absolute function number formula
2303 * is:
2304 * abs_func = 2 * vn + BP_PORT + BP_PATH
2305 *
2306 * and there are 4 functions per port
2307 *
2308 * For 4 port configuration it is
2309 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2310 *
2311 * and there are 2 functions per port
2312 */
2313 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2314 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2315
2316 if (func >= E1H_FUNC_MAX)
2317 break;
2318
2319 bp->mf_config[vn] =
2320 MF_CFG_RD(bp, func_mf_config[func].config);
2321 }
2322 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2323 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2324 bp->flags |= MF_FUNC_DIS;
2325 } else {
2326 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2327 bp->flags &= ~MF_FUNC_DIS;
2328 }
2329 }
2330
2331 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2332 {
2333 struct cmng_init_input input;
2334 memset(&input, 0, sizeof(struct cmng_init_input));
2335
2336 input.port_rate = bp->link_vars.line_speed;
2337
2338 if (cmng_type == CMNG_FNS_MINMAX) {
2339 int vn;
2340
2341 /* read mf conf from shmem */
2342 if (read_cfg)
2343 bnx2x_read_mf_cfg(bp);
2344
2345 /* vn_weight_sum and enable fairness if not 0 */
2346 bnx2x_calc_vn_min(bp, &input);
2347
2348 /* calculate and set min-max rate for each vn */
2349 if (bp->port.pmf)
2350 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2351 bnx2x_calc_vn_max(bp, vn, &input);
2352
2353 /* always enable rate shaping and fairness */
2354 input.flags.cmng_enables |=
2355 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2356
2357 bnx2x_init_cmng(&input, &bp->cmng);
2358 return;
2359 }
2360
2361 /* rate shaping and fairness are disabled */
2362 DP(NETIF_MSG_IFUP,
2363 "rate shaping and fairness are disabled\n");
2364 }
2365
2366 static void storm_memset_cmng(struct bnx2x *bp,
2367 struct cmng_init *cmng,
2368 u8 port)
2369 {
2370 int vn;
2371 size_t size = sizeof(struct cmng_struct_per_port);
2372
2373 u32 addr = BAR_XSTRORM_INTMEM +
2374 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2375
2376 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2377
2378 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2379 int func = func_by_vn(bp, vn);
2380
2381 addr = BAR_XSTRORM_INTMEM +
2382 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2383 size = sizeof(struct rate_shaping_vars_per_vn);
2384 __storm_memset_struct(bp, addr, size,
2385 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2386
2387 addr = BAR_XSTRORM_INTMEM +
2388 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2389 size = sizeof(struct fairness_vars_per_vn);
2390 __storm_memset_struct(bp, addr, size,
2391 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2392 }
2393 }
2394
2395 /* This function is called upon link interrupt */
2396 static void bnx2x_link_attn(struct bnx2x *bp)
2397 {
2398 /* Make sure that we are synced with the current statistics */
2399 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2400
2401 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2402
2403 if (bp->link_vars.link_up) {
2404
2405 /* dropless flow control */
2406 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2407 int port = BP_PORT(bp);
2408 u32 pause_enabled = 0;
2409
2410 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2411 pause_enabled = 1;
2412
2413 REG_WR(bp, BAR_USTRORM_INTMEM +
2414 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2415 pause_enabled);
2416 }
2417
2418 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2419 struct host_port_stats *pstats;
2420
2421 pstats = bnx2x_sp(bp, port_stats);
2422 /* reset old mac stats */
2423 memset(&(pstats->mac_stx[0]), 0,
2424 sizeof(struct mac_stx));
2425 }
2426 if (bp->state == BNX2X_STATE_OPEN)
2427 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2428 }
2429
2430 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2431 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2432
2433 if (cmng_fns != CMNG_FNS_NONE) {
2434 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2435 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2436 } else
2437 /* rate shaping and fairness are disabled */
2438 DP(NETIF_MSG_IFUP,
2439 "single function mode without fairness\n");
2440 }
2441
2442 __bnx2x_link_report(bp);
2443
2444 if (IS_MF(bp))
2445 bnx2x_link_sync_notify(bp);
2446 }
2447
2448 void bnx2x__link_status_update(struct bnx2x *bp)
2449 {
2450 if (bp->state != BNX2X_STATE_OPEN)
2451 return;
2452
2453 /* read updated dcb configuration */
2454 if (IS_PF(bp)) {
2455 bnx2x_dcbx_pmf_update(bp);
2456 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2457 if (bp->link_vars.link_up)
2458 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2459 else
2460 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2461 /* indicate link status */
2462 bnx2x_link_report(bp);
2463
2464 } else { /* VF */
2465 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2466 SUPPORTED_10baseT_Full |
2467 SUPPORTED_100baseT_Half |
2468 SUPPORTED_100baseT_Full |
2469 SUPPORTED_1000baseT_Full |
2470 SUPPORTED_2500baseX_Full |
2471 SUPPORTED_10000baseT_Full |
2472 SUPPORTED_TP |
2473 SUPPORTED_FIBRE |
2474 SUPPORTED_Autoneg |
2475 SUPPORTED_Pause |
2476 SUPPORTED_Asym_Pause);
2477 bp->port.advertising[0] = bp->port.supported[0];
2478
2479 bp->link_params.bp = bp;
2480 bp->link_params.port = BP_PORT(bp);
2481 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2482 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2483 bp->link_params.req_line_speed[0] = SPEED_10000;
2484 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2485 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2486 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2487 bp->link_vars.line_speed = SPEED_10000;
2488 bp->link_vars.link_status =
2489 (LINK_STATUS_LINK_UP |
2490 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2491 bp->link_vars.link_up = 1;
2492 bp->link_vars.duplex = DUPLEX_FULL;
2493 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2494 __bnx2x_link_report(bp);
2495 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2496 }
2497 }
2498
2499 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2500 u16 vlan_val, u8 allowed_prio)
2501 {
2502 struct bnx2x_func_state_params func_params = {0};
2503 struct bnx2x_func_afex_update_params *f_update_params =
2504 &func_params.params.afex_update;
2505
2506 func_params.f_obj = &bp->func_obj;
2507 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2508
2509 /* no need to wait for RAMROD completion, so don't
2510 * set RAMROD_COMP_WAIT flag
2511 */
2512
2513 f_update_params->vif_id = vifid;
2514 f_update_params->afex_default_vlan = vlan_val;
2515 f_update_params->allowed_priorities = allowed_prio;
2516
2517 /* if ramrod can not be sent, response to MCP immediately */
2518 if (bnx2x_func_state_change(bp, &func_params) < 0)
2519 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2520
2521 return 0;
2522 }
2523
2524 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2525 u16 vif_index, u8 func_bit_map)
2526 {
2527 struct bnx2x_func_state_params func_params = {0};
2528 struct bnx2x_func_afex_viflists_params *update_params =
2529 &func_params.params.afex_viflists;
2530 int rc;
2531 u32 drv_msg_code;
2532
2533 /* validate only LIST_SET and LIST_GET are received from switch */
2534 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2535 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2536 cmd_type);
2537
2538 func_params.f_obj = &bp->func_obj;
2539 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2540
2541 /* set parameters according to cmd_type */
2542 update_params->afex_vif_list_command = cmd_type;
2543 update_params->vif_list_index = cpu_to_le16(vif_index);
2544 update_params->func_bit_map =
2545 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2546 update_params->func_to_clear = 0;
2547 drv_msg_code =
2548 (cmd_type == VIF_LIST_RULE_GET) ?
2549 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2550 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2551
2552 /* if ramrod can not be sent, respond to MCP immediately for
2553 * SET and GET requests (other are not triggered from MCP)
2554 */
2555 rc = bnx2x_func_state_change(bp, &func_params);
2556 if (rc < 0)
2557 bnx2x_fw_command(bp, drv_msg_code, 0);
2558
2559 return 0;
2560 }
2561
2562 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2563 {
2564 struct afex_stats afex_stats;
2565 u32 func = BP_ABS_FUNC(bp);
2566 u32 mf_config;
2567 u16 vlan_val;
2568 u32 vlan_prio;
2569 u16 vif_id;
2570 u8 allowed_prio;
2571 u8 vlan_mode;
2572 u32 addr_to_write, vifid, addrs, stats_type, i;
2573
2574 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2575 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2576 DP(BNX2X_MSG_MCP,
2577 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2578 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2579 }
2580
2581 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2582 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2583 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2584 DP(BNX2X_MSG_MCP,
2585 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2586 vifid, addrs);
2587 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2588 addrs);
2589 }
2590
2591 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2592 addr_to_write = SHMEM2_RD(bp,
2593 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2594 stats_type = SHMEM2_RD(bp,
2595 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2596
2597 DP(BNX2X_MSG_MCP,
2598 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2599 addr_to_write);
2600
2601 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2602
2603 /* write response to scratchpad, for MCP */
2604 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2605 REG_WR(bp, addr_to_write + i*sizeof(u32),
2606 *(((u32 *)(&afex_stats))+i));
2607
2608 /* send ack message to MCP */
2609 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2610 }
2611
2612 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2613 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2614 bp->mf_config[BP_VN(bp)] = mf_config;
2615 DP(BNX2X_MSG_MCP,
2616 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2617 mf_config);
2618
2619 /* if VIF_SET is "enabled" */
2620 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2621 /* set rate limit directly to internal RAM */
2622 struct cmng_init_input cmng_input;
2623 struct rate_shaping_vars_per_vn m_rs_vn;
2624 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2625 u32 addr = BAR_XSTRORM_INTMEM +
2626 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2627
2628 bp->mf_config[BP_VN(bp)] = mf_config;
2629
2630 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2631 m_rs_vn.vn_counter.rate =
2632 cmng_input.vnic_max_rate[BP_VN(bp)];
2633 m_rs_vn.vn_counter.quota =
2634 (m_rs_vn.vn_counter.rate *
2635 RS_PERIODIC_TIMEOUT_USEC) / 8;
2636
2637 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2638
2639 /* read relevant values from mf_cfg struct in shmem */
2640 vif_id =
2641 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2642 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2643 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2644 vlan_val =
2645 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2646 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2647 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2648 vlan_prio = (mf_config &
2649 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2650 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2651 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2652 vlan_mode =
2653 (MF_CFG_RD(bp,
2654 func_mf_config[func].afex_config) &
2655 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2656 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2657 allowed_prio =
2658 (MF_CFG_RD(bp,
2659 func_mf_config[func].afex_config) &
2660 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2661 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2662
2663 /* send ramrod to FW, return in case of failure */
2664 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2665 allowed_prio))
2666 return;
2667
2668 bp->afex_def_vlan_tag = vlan_val;
2669 bp->afex_vlan_mode = vlan_mode;
2670 } else {
2671 /* notify link down because BP->flags is disabled */
2672 bnx2x_link_report(bp);
2673
2674 /* send INVALID VIF ramrod to FW */
2675 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2676
2677 /* Reset the default afex VLAN */
2678 bp->afex_def_vlan_tag = -1;
2679 }
2680 }
2681 }
2682
2683 static void bnx2x_pmf_update(struct bnx2x *bp)
2684 {
2685 int port = BP_PORT(bp);
2686 u32 val;
2687
2688 bp->port.pmf = 1;
2689 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2690
2691 /*
2692 * We need the mb() to ensure the ordering between the writing to
2693 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2694 */
2695 smp_mb();
2696
2697 /* queue a periodic task */
2698 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2699
2700 bnx2x_dcbx_pmf_update(bp);
2701
2702 /* enable nig attention */
2703 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2704 if (bp->common.int_block == INT_BLOCK_HC) {
2705 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2706 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2707 } else if (!CHIP_IS_E1x(bp)) {
2708 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2709 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2710 }
2711
2712 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2713 }
2714
2715 /* end of Link */
2716
2717 /* slow path */
2718
2719 /*
2720 * General service functions
2721 */
2722
2723 /* send the MCP a request, block until there is a reply */
2724 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2725 {
2726 int mb_idx = BP_FW_MB_IDX(bp);
2727 u32 seq;
2728 u32 rc = 0;
2729 u32 cnt = 1;
2730 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2731
2732 mutex_lock(&bp->fw_mb_mutex);
2733 seq = ++bp->fw_seq;
2734 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2735 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2736
2737 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2738 (command | seq), param);
2739
2740 do {
2741 /* let the FW do it's magic ... */
2742 msleep(delay);
2743
2744 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2745
2746 /* Give the FW up to 5 second (500*10ms) */
2747 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2748
2749 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2750 cnt*delay, rc, seq);
2751
2752 /* is this a reply to our command? */
2753 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2754 rc &= FW_MSG_CODE_MASK;
2755 else {
2756 /* FW BUG! */
2757 BNX2X_ERR("FW failed to respond!\n");
2758 bnx2x_fw_dump(bp);
2759 rc = 0;
2760 }
2761 mutex_unlock(&bp->fw_mb_mutex);
2762
2763 return rc;
2764 }
2765
2766
2767 static void storm_memset_func_cfg(struct bnx2x *bp,
2768 struct tstorm_eth_function_common_config *tcfg,
2769 u16 abs_fid)
2770 {
2771 size_t size = sizeof(struct tstorm_eth_function_common_config);
2772
2773 u32 addr = BAR_TSTRORM_INTMEM +
2774 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2775
2776 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2777 }
2778
2779 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2780 {
2781 if (CHIP_IS_E1x(bp)) {
2782 struct tstorm_eth_function_common_config tcfg = {0};
2783
2784 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2785 }
2786
2787 /* Enable the function in the FW */
2788 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2789 storm_memset_func_en(bp, p->func_id, 1);
2790
2791 /* spq */
2792 if (p->func_flgs & FUNC_FLG_SPQ) {
2793 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2794 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2795 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2796 }
2797 }
2798
2799 /**
2800 * bnx2x_get_tx_only_flags - Return common flags
2801 *
2802 * @bp device handle
2803 * @fp queue handle
2804 * @zero_stats TRUE if statistics zeroing is needed
2805 *
2806 * Return the flags that are common for the Tx-only and not normal connections.
2807 */
2808 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2809 struct bnx2x_fastpath *fp,
2810 bool zero_stats)
2811 {
2812 unsigned long flags = 0;
2813
2814 /* PF driver will always initialize the Queue to an ACTIVE state */
2815 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2816
2817 /* tx only connections collect statistics (on the same index as the
2818 * parent connection). The statistics are zeroed when the parent
2819 * connection is initialized.
2820 */
2821
2822 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2823 if (zero_stats)
2824 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2825
2826
2827 return flags;
2828 }
2829
2830 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2831 struct bnx2x_fastpath *fp,
2832 bool leading)
2833 {
2834 unsigned long flags = 0;
2835
2836 /* calculate other queue flags */
2837 if (IS_MF_SD(bp))
2838 __set_bit(BNX2X_Q_FLG_OV, &flags);
2839
2840 if (IS_FCOE_FP(fp)) {
2841 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2842 /* For FCoE - force usage of default priority (for afex) */
2843 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2844 }
2845
2846 if (!fp->disable_tpa) {
2847 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2848 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2849 if (fp->mode == TPA_MODE_GRO)
2850 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2851 }
2852
2853 if (leading) {
2854 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2855 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2856 }
2857
2858 /* Always set HW VLAN stripping */
2859 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2860
2861 /* configure silent vlan removal */
2862 if (IS_MF_AFEX(bp))
2863 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
2864
2865
2866 return flags | bnx2x_get_common_flags(bp, fp, true);
2867 }
2868
2869 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2870 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2871 u8 cos)
2872 {
2873 gen_init->stat_id = bnx2x_stats_id(fp);
2874 gen_init->spcl_id = fp->cl_id;
2875
2876 /* Always use mini-jumbo MTU for FCoE L2 ring */
2877 if (IS_FCOE_FP(fp))
2878 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2879 else
2880 gen_init->mtu = bp->dev->mtu;
2881
2882 gen_init->cos = cos;
2883 }
2884
2885 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2886 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2887 struct bnx2x_rxq_setup_params *rxq_init)
2888 {
2889 u8 max_sge = 0;
2890 u16 sge_sz = 0;
2891 u16 tpa_agg_size = 0;
2892
2893 if (!fp->disable_tpa) {
2894 pause->sge_th_lo = SGE_TH_LO(bp);
2895 pause->sge_th_hi = SGE_TH_HI(bp);
2896
2897 /* validate SGE ring has enough to cross high threshold */
2898 WARN_ON(bp->dropless_fc &&
2899 pause->sge_th_hi + FW_PREFETCH_CNT >
2900 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2901
2902 tpa_agg_size = min_t(u32,
2903 (min_t(u32, 8, MAX_SKB_FRAGS) *
2904 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2905 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2906 SGE_PAGE_SHIFT;
2907 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2908 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2909 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2910 0xffff);
2911 }
2912
2913 /* pause - not for e1 */
2914 if (!CHIP_IS_E1(bp)) {
2915 pause->bd_th_lo = BD_TH_LO(bp);
2916 pause->bd_th_hi = BD_TH_HI(bp);
2917
2918 pause->rcq_th_lo = RCQ_TH_LO(bp);
2919 pause->rcq_th_hi = RCQ_TH_HI(bp);
2920 /*
2921 * validate that rings have enough entries to cross
2922 * high thresholds
2923 */
2924 WARN_ON(bp->dropless_fc &&
2925 pause->bd_th_hi + FW_PREFETCH_CNT >
2926 bp->rx_ring_size);
2927 WARN_ON(bp->dropless_fc &&
2928 pause->rcq_th_hi + FW_PREFETCH_CNT >
2929 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2930
2931 pause->pri_map = 1;
2932 }
2933
2934 /* rxq setup */
2935 rxq_init->dscr_map = fp->rx_desc_mapping;
2936 rxq_init->sge_map = fp->rx_sge_mapping;
2937 rxq_init->rcq_map = fp->rx_comp_mapping;
2938 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2939
2940 /* This should be a maximum number of data bytes that may be
2941 * placed on the BD (not including paddings).
2942 */
2943 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2944 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
2945
2946 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2947 rxq_init->tpa_agg_sz = tpa_agg_size;
2948 rxq_init->sge_buf_sz = sge_sz;
2949 rxq_init->max_sges_pkt = max_sge;
2950 rxq_init->rss_engine_id = BP_FUNC(bp);
2951 rxq_init->mcast_engine_id = BP_FUNC(bp);
2952
2953 /* Maximum number or simultaneous TPA aggregation for this Queue.
2954 *
2955 * For PF Clients it should be the maximum avaliable number.
2956 * VF driver(s) may want to define it to a smaller value.
2957 */
2958 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2959
2960 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2961 rxq_init->fw_sb_id = fp->fw_sb_id;
2962
2963 if (IS_FCOE_FP(fp))
2964 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2965 else
2966 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2967 /* configure silent vlan removal
2968 * if multi function mode is afex, then mask default vlan
2969 */
2970 if (IS_MF_AFEX(bp)) {
2971 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
2972 rxq_init->silent_removal_mask = VLAN_VID_MASK;
2973 }
2974 }
2975
2976 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2977 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2978 u8 cos)
2979 {
2980 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
2981 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2982 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2983 txq_init->fw_sb_id = fp->fw_sb_id;
2984
2985 /*
2986 * set the tss leading client id for TX classfication ==
2987 * leading RSS client id
2988 */
2989 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2990
2991 if (IS_FCOE_FP(fp)) {
2992 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2993 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2994 }
2995 }
2996
2997 static void bnx2x_pf_init(struct bnx2x *bp)
2998 {
2999 struct bnx2x_func_init_params func_init = {0};
3000 struct event_ring_data eq_data = { {0} };
3001 u16 flags;
3002
3003 if (!CHIP_IS_E1x(bp)) {
3004 /* reset IGU PF statistics: MSIX + ATTN */
3005 /* PF */
3006 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3007 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3008 (CHIP_MODE_IS_4_PORT(bp) ?
3009 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3010 /* ATTN */
3011 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3012 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3013 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3014 (CHIP_MODE_IS_4_PORT(bp) ?
3015 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3016 }
3017
3018 /* function setup flags */
3019 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3020
3021 /* This flag is relevant for E1x only.
3022 * E2 doesn't have a TPA configuration in a function level.
3023 */
3024 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3025
3026 func_init.func_flgs = flags;
3027 func_init.pf_id = BP_FUNC(bp);
3028 func_init.func_id = BP_FUNC(bp);
3029 func_init.spq_map = bp->spq_mapping;
3030 func_init.spq_prod = bp->spq_prod_idx;
3031
3032 bnx2x_func_init(bp, &func_init);
3033
3034 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3035
3036 /*
3037 * Congestion management values depend on the link rate
3038 * There is no active link so initial link rate is set to 10 Gbps.
3039 * When the link comes up The congestion management values are
3040 * re-calculated according to the actual link rate.
3041 */
3042 bp->link_vars.line_speed = SPEED_10000;
3043 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3044
3045 /* Only the PMF sets the HW */
3046 if (bp->port.pmf)
3047 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3048
3049 /* init Event Queue */
3050 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3051 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3052 eq_data.producer = bp->eq_prod;
3053 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3054 eq_data.sb_id = DEF_SB_ID;
3055 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3056 }
3057
3058
3059 static void bnx2x_e1h_disable(struct bnx2x *bp)
3060 {
3061 int port = BP_PORT(bp);
3062
3063 bnx2x_tx_disable(bp);
3064
3065 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3066 }
3067
3068 static void bnx2x_e1h_enable(struct bnx2x *bp)
3069 {
3070 int port = BP_PORT(bp);
3071
3072 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3073
3074 /* Tx queue should be only reenabled */
3075 netif_tx_wake_all_queues(bp->dev);
3076
3077 /*
3078 * Should not call netif_carrier_on since it will be called if the link
3079 * is up when checking for link state
3080 */
3081 }
3082
3083 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3084
3085 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3086 {
3087 struct eth_stats_info *ether_stat =
3088 &bp->slowpath->drv_info_to_mcp.ether_stat;
3089
3090 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3091 ETH_STAT_INFO_VERSION_LEN);
3092
3093 bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3094 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3095 ether_stat->mac_local);
3096
3097 ether_stat->mtu_size = bp->dev->mtu;
3098
3099 if (bp->dev->features & NETIF_F_RXCSUM)
3100 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3101 if (bp->dev->features & NETIF_F_TSO)
3102 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3103 ether_stat->feature_flags |= bp->common.boot_mode;
3104
3105 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3106
3107 ether_stat->txq_size = bp->tx_ring_size;
3108 ether_stat->rxq_size = bp->rx_ring_size;
3109 }
3110
3111 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3112 {
3113 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3114 struct fcoe_stats_info *fcoe_stat =
3115 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3116
3117 if (!CNIC_LOADED(bp))
3118 return;
3119
3120 memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
3121 bp->fip_mac, ETH_ALEN);
3122
3123 fcoe_stat->qos_priority =
3124 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3125
3126 /* insert FCoE stats from ramrod response */
3127 if (!NO_FCOE(bp)) {
3128 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3129 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3130 tstorm_queue_statistics;
3131
3132 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3133 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3134 xstorm_queue_statistics;
3135
3136 struct fcoe_statistics_params *fw_fcoe_stat =
3137 &bp->fw_stats_data->fcoe;
3138
3139 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
3140 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3141
3142 ADD_64(fcoe_stat->rx_bytes_hi,
3143 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3144 fcoe_stat->rx_bytes_lo,
3145 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3146
3147 ADD_64(fcoe_stat->rx_bytes_hi,
3148 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3149 fcoe_stat->rx_bytes_lo,
3150 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3151
3152 ADD_64(fcoe_stat->rx_bytes_hi,
3153 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3154 fcoe_stat->rx_bytes_lo,
3155 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3156
3157 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3158 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3159
3160 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3161 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3162
3163 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3164 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3165
3166 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3167 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3168
3169 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3170 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3171
3172 ADD_64(fcoe_stat->tx_bytes_hi,
3173 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3174 fcoe_stat->tx_bytes_lo,
3175 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3176
3177 ADD_64(fcoe_stat->tx_bytes_hi,
3178 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3179 fcoe_stat->tx_bytes_lo,
3180 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3181
3182 ADD_64(fcoe_stat->tx_bytes_hi,
3183 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3184 fcoe_stat->tx_bytes_lo,
3185 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3186
3187 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3188 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3189
3190 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3191 fcoe_q_xstorm_stats->ucast_pkts_sent);
3192
3193 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3194 fcoe_q_xstorm_stats->bcast_pkts_sent);
3195
3196 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3197 fcoe_q_xstorm_stats->mcast_pkts_sent);
3198 }
3199
3200 /* ask L5 driver to add data to the struct */
3201 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3202 }
3203
3204 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3205 {
3206 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3207 struct iscsi_stats_info *iscsi_stat =
3208 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3209
3210 if (!CNIC_LOADED(bp))
3211 return;
3212
3213 memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
3214 bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3215
3216 iscsi_stat->qos_priority =
3217 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3218
3219 /* ask L5 driver to add data to the struct */
3220 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3221 }
3222
3223 /* called due to MCP event (on pmf):
3224 * reread new bandwidth configuration
3225 * configure FW
3226 * notify others function about the change
3227 */
3228 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3229 {
3230 if (bp->link_vars.link_up) {
3231 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3232 bnx2x_link_sync_notify(bp);
3233 }
3234 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3235 }
3236
3237 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3238 {
3239 bnx2x_config_mf_bw(bp);
3240 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3241 }
3242
3243 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3244 {
3245 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3246 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3247 }
3248
3249 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3250 {
3251 enum drv_info_opcode op_code;
3252 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3253
3254 /* if drv_info version supported by MFW doesn't match - send NACK */
3255 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3256 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3257 return;
3258 }
3259
3260 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3261 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3262
3263 memset(&bp->slowpath->drv_info_to_mcp, 0,
3264 sizeof(union drv_info_to_mcp));
3265
3266 switch (op_code) {
3267 case ETH_STATS_OPCODE:
3268 bnx2x_drv_info_ether_stat(bp);
3269 break;
3270 case FCOE_STATS_OPCODE:
3271 bnx2x_drv_info_fcoe_stat(bp);
3272 break;
3273 case ISCSI_STATS_OPCODE:
3274 bnx2x_drv_info_iscsi_stat(bp);
3275 break;
3276 default:
3277 /* if op code isn't supported - send NACK */
3278 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3279 return;
3280 }
3281
3282 /* if we got drv_info attn from MFW then these fields are defined in
3283 * shmem2 for sure
3284 */
3285 SHMEM2_WR(bp, drv_info_host_addr_lo,
3286 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3287 SHMEM2_WR(bp, drv_info_host_addr_hi,
3288 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3289
3290 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3291 }
3292
3293 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3294 {
3295 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3296
3297 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3298
3299 /*
3300 * This is the only place besides the function initialization
3301 * where the bp->flags can change so it is done without any
3302 * locks
3303 */
3304 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3305 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3306 bp->flags |= MF_FUNC_DIS;
3307
3308 bnx2x_e1h_disable(bp);
3309 } else {
3310 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3311 bp->flags &= ~MF_FUNC_DIS;
3312
3313 bnx2x_e1h_enable(bp);
3314 }
3315 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3316 }
3317 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3318 bnx2x_config_mf_bw(bp);
3319 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3320 }
3321
3322 /* Report results to MCP */
3323 if (dcc_event)
3324 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3325 else
3326 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3327 }
3328
3329 /* must be called under the spq lock */
3330 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3331 {
3332 struct eth_spe *next_spe = bp->spq_prod_bd;
3333
3334 if (bp->spq_prod_bd == bp->spq_last_bd) {
3335 bp->spq_prod_bd = bp->spq;
3336 bp->spq_prod_idx = 0;
3337 DP(BNX2X_MSG_SP, "end of spq\n");
3338 } else {
3339 bp->spq_prod_bd++;
3340 bp->spq_prod_idx++;
3341 }
3342 return next_spe;
3343 }
3344
3345 /* must be called under the spq lock */
3346 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3347 {
3348 int func = BP_FUNC(bp);
3349
3350 /*
3351 * Make sure that BD data is updated before writing the producer:
3352 * BD data is written to the memory, the producer is read from the
3353 * memory, thus we need a full memory barrier to ensure the ordering.
3354 */
3355 mb();
3356
3357 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3358 bp->spq_prod_idx);
3359 mmiowb();
3360 }
3361
3362 /**
3363 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3364 *
3365 * @cmd: command to check
3366 * @cmd_type: command type
3367 */
3368 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3369 {
3370 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3371 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3372 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3373 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3374 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3375 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3376 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3377 return true;
3378 else
3379 return false;
3380
3381 }
3382
3383
3384 /**
3385 * bnx2x_sp_post - place a single command on an SP ring
3386 *
3387 * @bp: driver handle
3388 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3389 * @cid: SW CID the command is related to
3390 * @data_hi: command private data address (high 32 bits)
3391 * @data_lo: command private data address (low 32 bits)
3392 * @cmd_type: command type (e.g. NONE, ETH)
3393 *
3394 * SP data is handled as if it's always an address pair, thus data fields are
3395 * not swapped to little endian in upper functions. Instead this function swaps
3396 * data as if it's two u32 fields.
3397 */
3398 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3399 u32 data_hi, u32 data_lo, int cmd_type)
3400 {
3401 struct eth_spe *spe;
3402 u16 type;
3403 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3404
3405 #ifdef BNX2X_STOP_ON_ERROR
3406 if (unlikely(bp->panic)) {
3407 BNX2X_ERR("Can't post SP when there is panic\n");
3408 return -EIO;
3409 }
3410 #endif
3411
3412 spin_lock_bh(&bp->spq_lock);
3413
3414 if (common) {
3415 if (!atomic_read(&bp->eq_spq_left)) {
3416 BNX2X_ERR("BUG! EQ ring full!\n");
3417 spin_unlock_bh(&bp->spq_lock);
3418 bnx2x_panic();
3419 return -EBUSY;
3420 }
3421 } else if (!atomic_read(&bp->cq_spq_left)) {
3422 BNX2X_ERR("BUG! SPQ ring full!\n");
3423 spin_unlock_bh(&bp->spq_lock);
3424 bnx2x_panic();
3425 return -EBUSY;
3426 }
3427
3428 spe = bnx2x_sp_get_next(bp);
3429
3430 /* CID needs port number to be encoded int it */
3431 spe->hdr.conn_and_cmd_data =
3432 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3433 HW_CID(bp, cid));
3434
3435 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3436
3437 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3438 SPE_HDR_FUNCTION_ID);
3439
3440 spe->hdr.type = cpu_to_le16(type);
3441
3442 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3443 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3444
3445 /*
3446 * It's ok if the actual decrement is issued towards the memory
3447 * somewhere between the spin_lock and spin_unlock. Thus no
3448 * more explict memory barrier is needed.
3449 */
3450 if (common)
3451 atomic_dec(&bp->eq_spq_left);
3452 else
3453 atomic_dec(&bp->cq_spq_left);
3454
3455
3456 DP(BNX2X_MSG_SP,
3457 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3458 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3459 (u32)(U64_LO(bp->spq_mapping) +
3460 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3461 HW_CID(bp, cid), data_hi, data_lo, type,
3462 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3463
3464 bnx2x_sp_prod_update(bp);
3465 spin_unlock_bh(&bp->spq_lock);
3466 return 0;
3467 }
3468
3469 /* acquire split MCP access lock register */
3470 static int bnx2x_acquire_alr(struct bnx2x *bp)
3471 {
3472 u32 j, val;
3473 int rc = 0;
3474
3475 might_sleep();
3476 for (j = 0; j < 1000; j++) {
3477 val = (1UL << 31);
3478 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3479 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3480 if (val & (1L << 31))
3481 break;
3482
3483 msleep(5);
3484 }
3485 if (!(val & (1L << 31))) {
3486 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3487 rc = -EBUSY;
3488 }
3489
3490 return rc;
3491 }
3492
3493 /* release split MCP access lock register */
3494 static void bnx2x_release_alr(struct bnx2x *bp)
3495 {
3496 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3497 }
3498
3499 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3500 #define BNX2X_DEF_SB_IDX 0x0002
3501
3502 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3503 {
3504 struct host_sp_status_block *def_sb = bp->def_status_blk;
3505 u16 rc = 0;
3506
3507 barrier(); /* status block is written to by the chip */
3508 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3509 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3510 rc |= BNX2X_DEF_SB_ATT_IDX;
3511 }
3512
3513 if (bp->def_idx != def_sb->sp_sb.running_index) {
3514 bp->def_idx = def_sb->sp_sb.running_index;
3515 rc |= BNX2X_DEF_SB_IDX;
3516 }
3517
3518 /* Do not reorder: indecies reading should complete before handling */
3519 barrier();
3520 return rc;
3521 }
3522
3523 /*
3524 * slow path service functions
3525 */
3526
3527 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3528 {
3529 int port = BP_PORT(bp);
3530 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3531 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3532 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3533 NIG_REG_MASK_INTERRUPT_PORT0;
3534 u32 aeu_mask;
3535 u32 nig_mask = 0;
3536 u32 reg_addr;
3537
3538 if (bp->attn_state & asserted)
3539 BNX2X_ERR("IGU ERROR\n");
3540
3541 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3542 aeu_mask = REG_RD(bp, aeu_addr);
3543
3544 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3545 aeu_mask, asserted);
3546 aeu_mask &= ~(asserted & 0x3ff);
3547 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3548
3549 REG_WR(bp, aeu_addr, aeu_mask);
3550 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3551
3552 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3553 bp->attn_state |= asserted;
3554 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3555
3556 if (asserted & ATTN_HARD_WIRED_MASK) {
3557 if (asserted & ATTN_NIG_FOR_FUNC) {
3558
3559 bnx2x_acquire_phy_lock(bp);
3560
3561 /* save nig interrupt mask */
3562 nig_mask = REG_RD(bp, nig_int_mask_addr);
3563
3564 /* If nig_mask is not set, no need to call the update
3565 * function.
3566 */
3567 if (nig_mask) {
3568 REG_WR(bp, nig_int_mask_addr, 0);
3569
3570 bnx2x_link_attn(bp);
3571 }
3572
3573 /* handle unicore attn? */
3574 }
3575 if (asserted & ATTN_SW_TIMER_4_FUNC)
3576 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3577
3578 if (asserted & GPIO_2_FUNC)
3579 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3580
3581 if (asserted & GPIO_3_FUNC)
3582 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3583
3584 if (asserted & GPIO_4_FUNC)
3585 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3586
3587 if (port == 0) {
3588 if (asserted & ATTN_GENERAL_ATTN_1) {
3589 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3590 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3591 }
3592 if (asserted & ATTN_GENERAL_ATTN_2) {
3593 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3594 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3595 }
3596 if (asserted & ATTN_GENERAL_ATTN_3) {
3597 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3598 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3599 }
3600 } else {
3601 if (asserted & ATTN_GENERAL_ATTN_4) {
3602 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3603 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3604 }
3605 if (asserted & ATTN_GENERAL_ATTN_5) {
3606 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3607 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3608 }
3609 if (asserted & ATTN_GENERAL_ATTN_6) {
3610 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3611 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3612 }
3613 }
3614
3615 } /* if hardwired */
3616
3617 if (bp->common.int_block == INT_BLOCK_HC)
3618 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3619 COMMAND_REG_ATTN_BITS_SET);
3620 else
3621 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3622
3623 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3624 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3625 REG_WR(bp, reg_addr, asserted);
3626
3627 /* now set back the mask */
3628 if (asserted & ATTN_NIG_FOR_FUNC) {
3629 /* Verify that IGU ack through BAR was written before restoring
3630 * NIG mask. This loop should exit after 2-3 iterations max.
3631 */
3632 if (bp->common.int_block != INT_BLOCK_HC) {
3633 u32 cnt = 0, igu_acked;
3634 do {
3635 igu_acked = REG_RD(bp,
3636 IGU_REG_ATTENTION_ACK_BITS);
3637 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3638 (++cnt < MAX_IGU_ATTN_ACK_TO));
3639 if (!igu_acked)
3640 DP(NETIF_MSG_HW,
3641 "Failed to verify IGU ack on time\n");
3642 barrier();
3643 }
3644 REG_WR(bp, nig_int_mask_addr, nig_mask);
3645 bnx2x_release_phy_lock(bp);
3646 }
3647 }
3648
3649 static void bnx2x_fan_failure(struct bnx2x *bp)
3650 {
3651 int port = BP_PORT(bp);
3652 u32 ext_phy_config;
3653 /* mark the failure */
3654 ext_phy_config =
3655 SHMEM_RD(bp,
3656 dev_info.port_hw_config[port].external_phy_config);
3657
3658 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3659 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3660 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3661 ext_phy_config);
3662
3663 /* log the failure */
3664 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3665 "Please contact OEM Support for assistance\n");
3666
3667 /*
3668 * Scheudle device reset (unload)
3669 * This is due to some boards consuming sufficient power when driver is
3670 * up to overheat if fan fails.
3671 */
3672 smp_mb__before_clear_bit();
3673 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3674 smp_mb__after_clear_bit();
3675 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3676
3677 }
3678
3679 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3680 {
3681 int port = BP_PORT(bp);
3682 int reg_offset;
3683 u32 val;
3684
3685 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3686 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3687
3688 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3689
3690 val = REG_RD(bp, reg_offset);
3691 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3692 REG_WR(bp, reg_offset, val);
3693
3694 BNX2X_ERR("SPIO5 hw attention\n");
3695
3696 /* Fan failure attention */
3697 bnx2x_hw_reset_phy(&bp->link_params);
3698 bnx2x_fan_failure(bp);
3699 }
3700
3701 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3702 bnx2x_acquire_phy_lock(bp);
3703 bnx2x_handle_module_detect_int(&bp->link_params);
3704 bnx2x_release_phy_lock(bp);
3705 }
3706
3707 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3708
3709 val = REG_RD(bp, reg_offset);
3710 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3711 REG_WR(bp, reg_offset, val);
3712
3713 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3714 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3715 bnx2x_panic();
3716 }
3717 }
3718
3719 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3720 {
3721 u32 val;
3722
3723 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3724
3725 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3726 BNX2X_ERR("DB hw attention 0x%x\n", val);
3727 /* DORQ discard attention */
3728 if (val & 0x2)
3729 BNX2X_ERR("FATAL error from DORQ\n");
3730 }
3731
3732 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3733
3734 int port = BP_PORT(bp);
3735 int reg_offset;
3736
3737 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3738 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3739
3740 val = REG_RD(bp, reg_offset);
3741 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3742 REG_WR(bp, reg_offset, val);
3743
3744 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3745 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3746 bnx2x_panic();
3747 }
3748 }
3749
3750 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3751 {
3752 u32 val;
3753
3754 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3755
3756 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3757 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3758 /* CFC error attention */
3759 if (val & 0x2)
3760 BNX2X_ERR("FATAL error from CFC\n");
3761 }
3762
3763 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3764 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3765 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3766 /* RQ_USDMDP_FIFO_OVERFLOW */
3767 if (val & 0x18000)
3768 BNX2X_ERR("FATAL error from PXP\n");
3769
3770 if (!CHIP_IS_E1x(bp)) {
3771 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3772 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3773 }
3774 }
3775
3776 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3777
3778 int port = BP_PORT(bp);
3779 int reg_offset;
3780
3781 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3782 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3783
3784 val = REG_RD(bp, reg_offset);
3785 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3786 REG_WR(bp, reg_offset, val);
3787
3788 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3789 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3790 bnx2x_panic();
3791 }
3792 }
3793
3794 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3795 {
3796 u32 val;
3797
3798 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3799
3800 if (attn & BNX2X_PMF_LINK_ASSERT) {
3801 int func = BP_FUNC(bp);
3802
3803 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3804 bnx2x_read_mf_cfg(bp);
3805 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3806 func_mf_config[BP_ABS_FUNC(bp)].config);
3807 val = SHMEM_RD(bp,
3808 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3809 if (val & DRV_STATUS_DCC_EVENT_MASK)
3810 bnx2x_dcc_event(bp,
3811 (val & DRV_STATUS_DCC_EVENT_MASK));
3812
3813 if (val & DRV_STATUS_SET_MF_BW)
3814 bnx2x_set_mf_bw(bp);
3815
3816 if (val & DRV_STATUS_DRV_INFO_REQ)
3817 bnx2x_handle_drv_info_req(bp);
3818 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3819 bnx2x_pmf_update(bp);
3820
3821 if (bp->port.pmf &&
3822 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3823 bp->dcbx_enabled > 0)
3824 /* start dcbx state machine */
3825 bnx2x_dcbx_set_params(bp,
3826 BNX2X_DCBX_STATE_NEG_RECEIVED);
3827 if (val & DRV_STATUS_AFEX_EVENT_MASK)
3828 bnx2x_handle_afex_cmd(bp,
3829 val & DRV_STATUS_AFEX_EVENT_MASK);
3830 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3831 bnx2x_handle_eee_event(bp);
3832 if (bp->link_vars.periodic_flags &
3833 PERIODIC_FLAGS_LINK_EVENT) {
3834 /* sync with link */
3835 bnx2x_acquire_phy_lock(bp);
3836 bp->link_vars.periodic_flags &=
3837 ~PERIODIC_FLAGS_LINK_EVENT;
3838 bnx2x_release_phy_lock(bp);
3839 if (IS_MF(bp))
3840 bnx2x_link_sync_notify(bp);
3841 bnx2x_link_report(bp);
3842 }
3843 /* Always call it here: bnx2x_link_report() will
3844 * prevent the link indication duplication.
3845 */
3846 bnx2x__link_status_update(bp);
3847 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3848
3849 BNX2X_ERR("MC assert!\n");
3850 bnx2x_mc_assert(bp);
3851 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3852 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3853 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3854 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3855 bnx2x_panic();
3856
3857 } else if (attn & BNX2X_MCP_ASSERT) {
3858
3859 BNX2X_ERR("MCP assert!\n");
3860 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3861 bnx2x_fw_dump(bp);
3862
3863 } else
3864 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3865 }
3866
3867 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3868 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3869 if (attn & BNX2X_GRC_TIMEOUT) {
3870 val = CHIP_IS_E1(bp) ? 0 :
3871 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3872 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3873 }
3874 if (attn & BNX2X_GRC_RSV) {
3875 val = CHIP_IS_E1(bp) ? 0 :
3876 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3877 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3878 }
3879 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3880 }
3881 }
3882
3883 /*
3884 * Bits map:
3885 * 0-7 - Engine0 load counter.
3886 * 8-15 - Engine1 load counter.
3887 * 16 - Engine0 RESET_IN_PROGRESS bit.
3888 * 17 - Engine1 RESET_IN_PROGRESS bit.
3889 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3890 * on the engine
3891 * 19 - Engine1 ONE_IS_LOADED.
3892 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3893 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3894 * just the one belonging to its engine).
3895 *
3896 */
3897 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3898
3899 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3900 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3901 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3902 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3903 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3904 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3905 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3906
3907 /*
3908 * Set the GLOBAL_RESET bit.
3909 *
3910 * Should be run under rtnl lock
3911 */
3912 void bnx2x_set_reset_global(struct bnx2x *bp)
3913 {
3914 u32 val;
3915 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3916 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3917 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3918 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3919 }
3920
3921 /*
3922 * Clear the GLOBAL_RESET bit.
3923 *
3924 * Should be run under rtnl lock
3925 */
3926 static void bnx2x_clear_reset_global(struct bnx2x *bp)
3927 {
3928 u32 val;
3929 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3930 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3931 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3932 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3933 }
3934
3935 /*
3936 * Checks the GLOBAL_RESET bit.
3937 *
3938 * should be run under rtnl lock
3939 */
3940 static bool bnx2x_reset_is_global(struct bnx2x *bp)
3941 {
3942 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3943
3944 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3945 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3946 }
3947
3948 /*
3949 * Clear RESET_IN_PROGRESS bit for the current engine.
3950 *
3951 * Should be run under rtnl lock
3952 */
3953 static void bnx2x_set_reset_done(struct bnx2x *bp)
3954 {
3955 u32 val;
3956 u32 bit = BP_PATH(bp) ?
3957 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3958 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3959 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3960
3961 /* Clear the bit */
3962 val &= ~bit;
3963 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3964
3965 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3966 }
3967
3968 /*
3969 * Set RESET_IN_PROGRESS for the current engine.
3970 *
3971 * should be run under rtnl lock
3972 */
3973 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3974 {
3975 u32 val;
3976 u32 bit = BP_PATH(bp) ?
3977 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3978 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3979 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3980
3981 /* Set the bit */
3982 val |= bit;
3983 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3984 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3985 }
3986
3987 /*
3988 * Checks the RESET_IN_PROGRESS bit for the given engine.
3989 * should be run under rtnl lock
3990 */
3991 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3992 {
3993 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3994 u32 bit = engine ?
3995 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3996
3997 /* return false if bit is set */
3998 return (val & bit) ? false : true;
3999 }
4000
4001 /*
4002 * set pf load for the current pf.
4003 *
4004 * should be run under rtnl lock
4005 */
4006 void bnx2x_set_pf_load(struct bnx2x *bp)
4007 {
4008 u32 val1, val;
4009 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4010 BNX2X_PATH0_LOAD_CNT_MASK;
4011 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4012 BNX2X_PATH0_LOAD_CNT_SHIFT;
4013
4014 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4015 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4016
4017 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4018
4019 /* get the current counter value */
4020 val1 = (val & mask) >> shift;
4021
4022 /* set bit of that PF */
4023 val1 |= (1 << bp->pf_num);
4024
4025 /* clear the old value */
4026 val &= ~mask;
4027
4028 /* set the new one */
4029 val |= ((val1 << shift) & mask);
4030
4031 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4032 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4033 }
4034
4035 /**
4036 * bnx2x_clear_pf_load - clear pf load mark
4037 *
4038 * @bp: driver handle
4039 *
4040 * Should be run under rtnl lock.
4041 * Decrements the load counter for the current engine. Returns
4042 * whether other functions are still loaded
4043 */
4044 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4045 {
4046 u32 val1, val;
4047 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4048 BNX2X_PATH0_LOAD_CNT_MASK;
4049 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4050 BNX2X_PATH0_LOAD_CNT_SHIFT;
4051
4052 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4053 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4054 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4055
4056 /* get the current counter value */
4057 val1 = (val & mask) >> shift;
4058
4059 /* clear bit of that PF */
4060 val1 &= ~(1 << bp->pf_num);
4061
4062 /* clear the old value */
4063 val &= ~mask;
4064
4065 /* set the new one */
4066 val |= ((val1 << shift) & mask);
4067
4068 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4069 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4070 return val1 != 0;
4071 }
4072
4073 /*
4074 * Read the load status for the current engine.
4075 *
4076 * should be run under rtnl lock
4077 */
4078 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4079 {
4080 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4081 BNX2X_PATH0_LOAD_CNT_MASK);
4082 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4083 BNX2X_PATH0_LOAD_CNT_SHIFT);
4084 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4085
4086 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4087
4088 val = (val & mask) >> shift;
4089
4090 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4091 engine, val);
4092
4093 return val != 0;
4094 }
4095
4096 static void _print_next_block(int idx, const char *blk)
4097 {
4098 pr_cont("%s%s", idx ? ", " : "", blk);
4099 }
4100
4101 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4102 bool print)
4103 {
4104 int i = 0;
4105 u32 cur_bit = 0;
4106 for (i = 0; sig; i++) {
4107 cur_bit = ((u32)0x1 << i);
4108 if (sig & cur_bit) {
4109 switch (cur_bit) {
4110 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4111 if (print)
4112 _print_next_block(par_num++, "BRB");
4113 break;
4114 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4115 if (print)
4116 _print_next_block(par_num++, "PARSER");
4117 break;
4118 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4119 if (print)
4120 _print_next_block(par_num++, "TSDM");
4121 break;
4122 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4123 if (print)
4124 _print_next_block(par_num++,
4125 "SEARCHER");
4126 break;
4127 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4128 if (print)
4129 _print_next_block(par_num++, "TCM");
4130 break;
4131 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4132 if (print)
4133 _print_next_block(par_num++, "TSEMI");
4134 break;
4135 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4136 if (print)
4137 _print_next_block(par_num++, "XPB");
4138 break;
4139 }
4140
4141 /* Clear the bit */
4142 sig &= ~cur_bit;
4143 }
4144 }
4145
4146 return par_num;
4147 }
4148
4149 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4150 bool *global, bool print)
4151 {
4152 int i = 0;
4153 u32 cur_bit = 0;
4154 for (i = 0; sig; i++) {
4155 cur_bit = ((u32)0x1 << i);
4156 if (sig & cur_bit) {
4157 switch (cur_bit) {
4158 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4159 if (print)
4160 _print_next_block(par_num++, "PBF");
4161 break;
4162 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4163 if (print)
4164 _print_next_block(par_num++, "QM");
4165 break;
4166 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4167 if (print)
4168 _print_next_block(par_num++, "TM");
4169 break;
4170 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4171 if (print)
4172 _print_next_block(par_num++, "XSDM");
4173 break;
4174 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4175 if (print)
4176 _print_next_block(par_num++, "XCM");
4177 break;
4178 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4179 if (print)
4180 _print_next_block(par_num++, "XSEMI");
4181 break;
4182 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4183 if (print)
4184 _print_next_block(par_num++,
4185 "DOORBELLQ");
4186 break;
4187 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4188 if (print)
4189 _print_next_block(par_num++, "NIG");
4190 break;
4191 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4192 if (print)
4193 _print_next_block(par_num++,
4194 "VAUX PCI CORE");
4195 *global = true;
4196 break;
4197 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4198 if (print)
4199 _print_next_block(par_num++, "DEBUG");
4200 break;
4201 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4202 if (print)
4203 _print_next_block(par_num++, "USDM");
4204 break;
4205 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4206 if (print)
4207 _print_next_block(par_num++, "UCM");
4208 break;
4209 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4210 if (print)
4211 _print_next_block(par_num++, "USEMI");
4212 break;
4213 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4214 if (print)
4215 _print_next_block(par_num++, "UPB");
4216 break;
4217 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4218 if (print)
4219 _print_next_block(par_num++, "CSDM");
4220 break;
4221 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4222 if (print)
4223 _print_next_block(par_num++, "CCM");
4224 break;
4225 }
4226
4227 /* Clear the bit */
4228 sig &= ~cur_bit;
4229 }
4230 }
4231
4232 return par_num;
4233 }
4234
4235 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4236 bool print)
4237 {
4238 int i = 0;
4239 u32 cur_bit = 0;
4240 for (i = 0; sig; i++) {
4241 cur_bit = ((u32)0x1 << i);
4242 if (sig & cur_bit) {
4243 switch (cur_bit) {
4244 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4245 if (print)
4246 _print_next_block(par_num++, "CSEMI");
4247 break;
4248 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4249 if (print)
4250 _print_next_block(par_num++, "PXP");
4251 break;
4252 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4253 if (print)
4254 _print_next_block(par_num++,
4255 "PXPPCICLOCKCLIENT");
4256 break;
4257 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4258 if (print)
4259 _print_next_block(par_num++, "CFC");
4260 break;
4261 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4262 if (print)
4263 _print_next_block(par_num++, "CDU");
4264 break;
4265 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4266 if (print)
4267 _print_next_block(par_num++, "DMAE");
4268 break;
4269 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4270 if (print)
4271 _print_next_block(par_num++, "IGU");
4272 break;
4273 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4274 if (print)
4275 _print_next_block(par_num++, "MISC");
4276 break;
4277 }
4278
4279 /* Clear the bit */
4280 sig &= ~cur_bit;
4281 }
4282 }
4283
4284 return par_num;
4285 }
4286
4287 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4288 bool *global, bool print)
4289 {
4290 int i = 0;
4291 u32 cur_bit = 0;
4292 for (i = 0; sig; i++) {
4293 cur_bit = ((u32)0x1 << i);
4294 if (sig & cur_bit) {
4295 switch (cur_bit) {
4296 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4297 if (print)
4298 _print_next_block(par_num++, "MCP ROM");
4299 *global = true;
4300 break;
4301 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4302 if (print)
4303 _print_next_block(par_num++,
4304 "MCP UMP RX");
4305 *global = true;
4306 break;
4307 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4308 if (print)
4309 _print_next_block(par_num++,
4310 "MCP UMP TX");
4311 *global = true;
4312 break;
4313 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4314 if (print)
4315 _print_next_block(par_num++,
4316 "MCP SCPAD");
4317 *global = true;
4318 break;
4319 }
4320
4321 /* Clear the bit */
4322 sig &= ~cur_bit;
4323 }
4324 }
4325
4326 return par_num;
4327 }
4328
4329 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4330 bool print)
4331 {
4332 int i = 0;
4333 u32 cur_bit = 0;
4334 for (i = 0; sig; i++) {
4335 cur_bit = ((u32)0x1 << i);
4336 if (sig & cur_bit) {
4337 switch (cur_bit) {
4338 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4339 if (print)
4340 _print_next_block(par_num++, "PGLUE_B");
4341 break;
4342 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4343 if (print)
4344 _print_next_block(par_num++, "ATC");
4345 break;
4346 }
4347
4348 /* Clear the bit */
4349 sig &= ~cur_bit;
4350 }
4351 }
4352
4353 return par_num;
4354 }
4355
4356 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4357 u32 *sig)
4358 {
4359 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4360 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4361 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4362 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4363 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4364 int par_num = 0;
4365 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4366 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4367 sig[0] & HW_PRTY_ASSERT_SET_0,
4368 sig[1] & HW_PRTY_ASSERT_SET_1,
4369 sig[2] & HW_PRTY_ASSERT_SET_2,
4370 sig[3] & HW_PRTY_ASSERT_SET_3,
4371 sig[4] & HW_PRTY_ASSERT_SET_4);
4372 if (print)
4373 netdev_err(bp->dev,
4374 "Parity errors detected in blocks: ");
4375 par_num = bnx2x_check_blocks_with_parity0(
4376 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4377 par_num = bnx2x_check_blocks_with_parity1(
4378 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4379 par_num = bnx2x_check_blocks_with_parity2(
4380 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4381 par_num = bnx2x_check_blocks_with_parity3(
4382 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4383 par_num = bnx2x_check_blocks_with_parity4(
4384 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4385
4386 if (print)
4387 pr_cont("\n");
4388
4389 return true;
4390 } else
4391 return false;
4392 }
4393
4394 /**
4395 * bnx2x_chk_parity_attn - checks for parity attentions.
4396 *
4397 * @bp: driver handle
4398 * @global: true if there was a global attention
4399 * @print: show parity attention in syslog
4400 */
4401 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4402 {
4403 struct attn_route attn = { {0} };
4404 int port = BP_PORT(bp);
4405
4406 attn.sig[0] = REG_RD(bp,
4407 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4408 port*4);
4409 attn.sig[1] = REG_RD(bp,
4410 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4411 port*4);
4412 attn.sig[2] = REG_RD(bp,
4413 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4414 port*4);
4415 attn.sig[3] = REG_RD(bp,
4416 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4417 port*4);
4418
4419 if (!CHIP_IS_E1x(bp))
4420 attn.sig[4] = REG_RD(bp,
4421 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4422 port*4);
4423
4424 return bnx2x_parity_attn(bp, global, print, attn.sig);
4425 }
4426
4427
4428 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4429 {
4430 u32 val;
4431 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4432
4433 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4434 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4435 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4436 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4437 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4438 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4439 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4440 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4441 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4442 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4443 if (val &
4444 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4445 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4446 if (val &
4447 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4448 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4449 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4450 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4451 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4452 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4453 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4454 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4455 }
4456 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4457 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4458 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4459 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4460 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4461 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4462 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4463 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4464 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4465 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4466 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4467 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4468 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4469 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4470 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4471 }
4472
4473 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4474 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4475 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4476 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4477 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4478 }
4479
4480 }
4481
4482 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4483 {
4484 struct attn_route attn, *group_mask;
4485 int port = BP_PORT(bp);
4486 int index;
4487 u32 reg_addr;
4488 u32 val;
4489 u32 aeu_mask;
4490 bool global = false;
4491
4492 /* need to take HW lock because MCP or other port might also
4493 try to handle this event */
4494 bnx2x_acquire_alr(bp);
4495
4496 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4497 #ifndef BNX2X_STOP_ON_ERROR
4498 bp->recovery_state = BNX2X_RECOVERY_INIT;
4499 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4500 /* Disable HW interrupts */
4501 bnx2x_int_disable(bp);
4502 /* In case of parity errors don't handle attentions so that
4503 * other function would "see" parity errors.
4504 */
4505 #else
4506 bnx2x_panic();
4507 #endif
4508 bnx2x_release_alr(bp);
4509 return;
4510 }
4511
4512 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4513 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4514 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4515 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4516 if (!CHIP_IS_E1x(bp))
4517 attn.sig[4] =
4518 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4519 else
4520 attn.sig[4] = 0;
4521
4522 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4523 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4524
4525 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4526 if (deasserted & (1 << index)) {
4527 group_mask = &bp->attn_group[index];
4528
4529 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4530 index,
4531 group_mask->sig[0], group_mask->sig[1],
4532 group_mask->sig[2], group_mask->sig[3],
4533 group_mask->sig[4]);
4534
4535 bnx2x_attn_int_deasserted4(bp,
4536 attn.sig[4] & group_mask->sig[4]);
4537 bnx2x_attn_int_deasserted3(bp,
4538 attn.sig[3] & group_mask->sig[3]);
4539 bnx2x_attn_int_deasserted1(bp,
4540 attn.sig[1] & group_mask->sig[1]);
4541 bnx2x_attn_int_deasserted2(bp,
4542 attn.sig[2] & group_mask->sig[2]);
4543 bnx2x_attn_int_deasserted0(bp,
4544 attn.sig[0] & group_mask->sig[0]);
4545 }
4546 }
4547
4548 bnx2x_release_alr(bp);
4549
4550 if (bp->common.int_block == INT_BLOCK_HC)
4551 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4552 COMMAND_REG_ATTN_BITS_CLR);
4553 else
4554 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4555
4556 val = ~deasserted;
4557 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4558 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4559 REG_WR(bp, reg_addr, val);
4560
4561 if (~bp->attn_state & deasserted)
4562 BNX2X_ERR("IGU ERROR\n");
4563
4564 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4565 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4566
4567 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4568 aeu_mask = REG_RD(bp, reg_addr);
4569
4570 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4571 aeu_mask, deasserted);
4572 aeu_mask |= (deasserted & 0x3ff);
4573 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4574
4575 REG_WR(bp, reg_addr, aeu_mask);
4576 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4577
4578 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4579 bp->attn_state &= ~deasserted;
4580 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4581 }
4582
4583 static void bnx2x_attn_int(struct bnx2x *bp)
4584 {
4585 /* read local copy of bits */
4586 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4587 attn_bits);
4588 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4589 attn_bits_ack);
4590 u32 attn_state = bp->attn_state;
4591
4592 /* look for changed bits */
4593 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4594 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4595
4596 DP(NETIF_MSG_HW,
4597 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4598 attn_bits, attn_ack, asserted, deasserted);
4599
4600 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4601 BNX2X_ERR("BAD attention state\n");
4602
4603 /* handle bits that were raised */
4604 if (asserted)
4605 bnx2x_attn_int_asserted(bp, asserted);
4606
4607 if (deasserted)
4608 bnx2x_attn_int_deasserted(bp, deasserted);
4609 }
4610
4611 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4612 u16 index, u8 op, u8 update)
4613 {
4614 u32 igu_addr = bp->igu_base_addr;
4615 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4616 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4617 igu_addr);
4618 }
4619
4620 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4621 {
4622 /* No memory barriers */
4623 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4624 mmiowb(); /* keep prod updates ordered */
4625 }
4626
4627 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4628 union event_ring_elem *elem)
4629 {
4630 u8 err = elem->message.error;
4631
4632 if (!bp->cnic_eth_dev.starting_cid ||
4633 (cid < bp->cnic_eth_dev.starting_cid &&
4634 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4635 return 1;
4636
4637 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4638
4639 if (unlikely(err)) {
4640
4641 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4642 cid);
4643 bnx2x_panic_dump(bp);
4644 }
4645 bnx2x_cnic_cfc_comp(bp, cid, err);
4646 return 0;
4647 }
4648
4649 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4650 {
4651 struct bnx2x_mcast_ramrod_params rparam;
4652 int rc;
4653
4654 memset(&rparam, 0, sizeof(rparam));
4655
4656 rparam.mcast_obj = &bp->mcast_obj;
4657
4658 netif_addr_lock_bh(bp->dev);
4659
4660 /* Clear pending state for the last command */
4661 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4662
4663 /* If there are pending mcast commands - send them */
4664 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4665 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4666 if (rc < 0)
4667 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4668 rc);
4669 }
4670
4671 netif_addr_unlock_bh(bp->dev);
4672 }
4673
4674 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4675 union event_ring_elem *elem)
4676 {
4677 unsigned long ramrod_flags = 0;
4678 int rc = 0;
4679 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4680 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4681
4682 /* Always push next commands out, don't wait here */
4683 __set_bit(RAMROD_CONT, &ramrod_flags);
4684
4685 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4686 case BNX2X_FILTER_MAC_PENDING:
4687 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4688 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4689 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4690 else
4691 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4692
4693 break;
4694 case BNX2X_FILTER_MCAST_PENDING:
4695 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4696 /* This is only relevant for 57710 where multicast MACs are
4697 * configured as unicast MACs using the same ramrod.
4698 */
4699 bnx2x_handle_mcast_eqe(bp);
4700 return;
4701 default:
4702 BNX2X_ERR("Unsupported classification command: %d\n",
4703 elem->message.data.eth_event.echo);
4704 return;
4705 }
4706
4707 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4708
4709 if (rc < 0)
4710 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4711 else if (rc > 0)
4712 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4713
4714 }
4715
4716 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4717
4718 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4719 {
4720 netif_addr_lock_bh(bp->dev);
4721
4722 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4723
4724 /* Send rx_mode command again if was requested */
4725 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4726 bnx2x_set_storm_rx_mode(bp);
4727 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4728 &bp->sp_state))
4729 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4730 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4731 &bp->sp_state))
4732 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4733
4734 netif_addr_unlock_bh(bp->dev);
4735 }
4736
4737 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4738 union event_ring_elem *elem)
4739 {
4740 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4741 DP(BNX2X_MSG_SP,
4742 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4743 elem->message.data.vif_list_event.func_bit_map);
4744 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4745 elem->message.data.vif_list_event.func_bit_map);
4746 } else if (elem->message.data.vif_list_event.echo ==
4747 VIF_LIST_RULE_SET) {
4748 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4749 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4750 }
4751 }
4752
4753 /* called with rtnl_lock */
4754 static void bnx2x_after_function_update(struct bnx2x *bp)
4755 {
4756 int q, rc;
4757 struct bnx2x_fastpath *fp;
4758 struct bnx2x_queue_state_params queue_params = {NULL};
4759 struct bnx2x_queue_update_params *q_update_params =
4760 &queue_params.params.update;
4761
4762 /* Send Q update command with afex vlan removal values for all Qs */
4763 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4764
4765 /* set silent vlan removal values according to vlan mode */
4766 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4767 &q_update_params->update_flags);
4768 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4769 &q_update_params->update_flags);
4770 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4771
4772 /* in access mode mark mask and value are 0 to strip all vlans */
4773 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4774 q_update_params->silent_removal_value = 0;
4775 q_update_params->silent_removal_mask = 0;
4776 } else {
4777 q_update_params->silent_removal_value =
4778 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4779 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4780 }
4781
4782 for_each_eth_queue(bp, q) {
4783 /* Set the appropriate Queue object */
4784 fp = &bp->fp[q];
4785 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4786
4787 /* send the ramrod */
4788 rc = bnx2x_queue_state_change(bp, &queue_params);
4789 if (rc < 0)
4790 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4791 q);
4792 }
4793
4794 if (!NO_FCOE(bp)) {
4795 fp = &bp->fp[FCOE_IDX(bp)];
4796 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4797
4798 /* clear pending completion bit */
4799 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4800
4801 /* mark latest Q bit */
4802 smp_mb__before_clear_bit();
4803 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4804 smp_mb__after_clear_bit();
4805
4806 /* send Q update ramrod for FCoE Q */
4807 rc = bnx2x_queue_state_change(bp, &queue_params);
4808 if (rc < 0)
4809 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4810 q);
4811 } else {
4812 /* If no FCoE ring - ACK MCP now */
4813 bnx2x_link_report(bp);
4814 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4815 }
4816 }
4817
4818 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4819 struct bnx2x *bp, u32 cid)
4820 {
4821 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4822
4823 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
4824 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4825 else
4826 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4827 }
4828
4829 static void bnx2x_eq_int(struct bnx2x *bp)
4830 {
4831 u16 hw_cons, sw_cons, sw_prod;
4832 union event_ring_elem *elem;
4833 u8 echo;
4834 u32 cid;
4835 u8 opcode;
4836 int spqe_cnt = 0;
4837 struct bnx2x_queue_sp_obj *q_obj;
4838 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4839 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4840
4841 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4842
4843 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4844 * when we get the the next-page we nned to adjust so the loop
4845 * condition below will be met. The next element is the size of a
4846 * regular element and hence incrementing by 1
4847 */
4848 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4849 hw_cons++;
4850
4851 /* This function may never run in parallel with itself for a
4852 * specific bp, thus there is no need in "paired" read memory
4853 * barrier here.
4854 */
4855 sw_cons = bp->eq_cons;
4856 sw_prod = bp->eq_prod;
4857
4858 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4859 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4860
4861 for (; sw_cons != hw_cons;
4862 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4863
4864
4865 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4866
4867 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4868 opcode = elem->message.opcode;
4869
4870
4871 /* handle eq element */
4872 switch (opcode) {
4873 case EVENT_RING_OPCODE_STAT_QUERY:
4874 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
4875 "got statistics comp event %d\n",
4876 bp->stats_comp++);
4877 /* nothing to do with stats comp */
4878 goto next_spqe;
4879
4880 case EVENT_RING_OPCODE_CFC_DEL:
4881 /* handle according to cid range */
4882 /*
4883 * we may want to verify here that the bp state is
4884 * HALTING
4885 */
4886 DP(BNX2X_MSG_SP,
4887 "got delete ramrod for MULTI[%d]\n", cid);
4888
4889 if (CNIC_LOADED(bp) &&
4890 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4891 goto next_spqe;
4892
4893 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4894
4895 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4896 break;
4897
4898
4899
4900 goto next_spqe;
4901
4902 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4903 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
4904 if (f_obj->complete_cmd(bp, f_obj,
4905 BNX2X_F_CMD_TX_STOP))
4906 break;
4907 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4908 goto next_spqe;
4909
4910 case EVENT_RING_OPCODE_START_TRAFFIC:
4911 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
4912 if (f_obj->complete_cmd(bp, f_obj,
4913 BNX2X_F_CMD_TX_START))
4914 break;
4915 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4916 goto next_spqe;
4917
4918 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4919 echo = elem->message.data.function_update_event.echo;
4920 if (echo == SWITCH_UPDATE) {
4921 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4922 "got FUNC_SWITCH_UPDATE ramrod\n");
4923 if (f_obj->complete_cmd(
4924 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
4925 break;
4926
4927 } else {
4928 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
4929 "AFEX: ramrod completed FUNCTION_UPDATE\n");
4930 f_obj->complete_cmd(bp, f_obj,
4931 BNX2X_F_CMD_AFEX_UPDATE);
4932
4933 /* We will perform the Queues update from
4934 * sp_rtnl task as all Queue SP operations
4935 * should run under rtnl_lock.
4936 */
4937 smp_mb__before_clear_bit();
4938 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
4939 &bp->sp_rtnl_state);
4940 smp_mb__after_clear_bit();
4941
4942 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4943 }
4944
4945 goto next_spqe;
4946
4947 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
4948 f_obj->complete_cmd(bp, f_obj,
4949 BNX2X_F_CMD_AFEX_VIFLISTS);
4950 bnx2x_after_afex_vif_lists(bp, elem);
4951 goto next_spqe;
4952 case EVENT_RING_OPCODE_FUNCTION_START:
4953 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4954 "got FUNC_START ramrod\n");
4955 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4956 break;
4957
4958 goto next_spqe;
4959
4960 case EVENT_RING_OPCODE_FUNCTION_STOP:
4961 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4962 "got FUNC_STOP ramrod\n");
4963 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4964 break;
4965
4966 goto next_spqe;
4967 }
4968
4969 switch (opcode | bp->state) {
4970 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4971 BNX2X_STATE_OPEN):
4972 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4973 BNX2X_STATE_OPENING_WAIT4_PORT):
4974 cid = elem->message.data.eth_event.echo &
4975 BNX2X_SWCID_MASK;
4976 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4977 cid);
4978 rss_raw->clear_pending(rss_raw);
4979 break;
4980
4981 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4982 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4983 case (EVENT_RING_OPCODE_SET_MAC |
4984 BNX2X_STATE_CLOSING_WAIT4_HALT):
4985 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4986 BNX2X_STATE_OPEN):
4987 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4988 BNX2X_STATE_DIAG):
4989 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4990 BNX2X_STATE_CLOSING_WAIT4_HALT):
4991 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4992 bnx2x_handle_classification_eqe(bp, elem);
4993 break;
4994
4995 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4996 BNX2X_STATE_OPEN):
4997 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4998 BNX2X_STATE_DIAG):
4999 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5000 BNX2X_STATE_CLOSING_WAIT4_HALT):
5001 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5002 bnx2x_handle_mcast_eqe(bp);
5003 break;
5004
5005 case (EVENT_RING_OPCODE_FILTERS_RULES |
5006 BNX2X_STATE_OPEN):
5007 case (EVENT_RING_OPCODE_FILTERS_RULES |
5008 BNX2X_STATE_DIAG):
5009 case (EVENT_RING_OPCODE_FILTERS_RULES |
5010 BNX2X_STATE_CLOSING_WAIT4_HALT):
5011 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5012 bnx2x_handle_rx_mode_eqe(bp);
5013 break;
5014 default:
5015 /* unknown event log error and continue */
5016 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5017 elem->message.opcode, bp->state);
5018 }
5019 next_spqe:
5020 spqe_cnt++;
5021 } /* for */
5022
5023 smp_mb__before_atomic_inc();
5024 atomic_add(spqe_cnt, &bp->eq_spq_left);
5025
5026 bp->eq_cons = sw_cons;
5027 bp->eq_prod = sw_prod;
5028 /* Make sure that above mem writes were issued towards the memory */
5029 smp_wmb();
5030
5031 /* update producer */
5032 bnx2x_update_eq_prod(bp, bp->eq_prod);
5033 }
5034
5035 static void bnx2x_sp_task(struct work_struct *work)
5036 {
5037 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5038 u16 status;
5039
5040 status = bnx2x_update_dsb_idx(bp);
5041 /* if (status == 0) */
5042 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
5043
5044 DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status);
5045
5046 /* HW attentions */
5047 if (status & BNX2X_DEF_SB_ATT_IDX) {
5048 bnx2x_attn_int(bp);
5049 status &= ~BNX2X_DEF_SB_ATT_IDX;
5050 }
5051
5052 /* SP events: STAT_QUERY and others */
5053 if (status & BNX2X_DEF_SB_IDX) {
5054 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5055
5056 if (FCOE_INIT(bp) &&
5057 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5058 /*
5059 * Prevent local bottom-halves from running as
5060 * we are going to change the local NAPI list.
5061 */
5062 local_bh_disable();
5063 napi_schedule(&bnx2x_fcoe(bp, napi));
5064 local_bh_enable();
5065 }
5066
5067 /* Handle EQ completions */
5068 bnx2x_eq_int(bp);
5069
5070 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5071 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5072
5073 status &= ~BNX2X_DEF_SB_IDX;
5074 }
5075
5076 if (unlikely(status))
5077 DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n",
5078 status);
5079
5080 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5081 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5082
5083 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5084 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5085 &bp->sp_state)) {
5086 bnx2x_link_report(bp);
5087 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5088 }
5089 }
5090
5091 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5092 {
5093 struct net_device *dev = dev_instance;
5094 struct bnx2x *bp = netdev_priv(dev);
5095
5096 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5097 IGU_INT_DISABLE, 0);
5098
5099 #ifdef BNX2X_STOP_ON_ERROR
5100 if (unlikely(bp->panic))
5101 return IRQ_HANDLED;
5102 #endif
5103
5104 if (CNIC_LOADED(bp)) {
5105 struct cnic_ops *c_ops;
5106
5107 rcu_read_lock();
5108 c_ops = rcu_dereference(bp->cnic_ops);
5109 if (c_ops)
5110 c_ops->cnic_handler(bp->cnic_data, NULL);
5111 rcu_read_unlock();
5112 }
5113
5114 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
5115
5116 return IRQ_HANDLED;
5117 }
5118
5119 /* end of slow path */
5120
5121
5122 void bnx2x_drv_pulse(struct bnx2x *bp)
5123 {
5124 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5125 bp->fw_drv_pulse_wr_seq);
5126 }
5127
5128
5129 static void bnx2x_timer(unsigned long data)
5130 {
5131 struct bnx2x *bp = (struct bnx2x *) data;
5132
5133 if (!netif_running(bp->dev))
5134 return;
5135
5136 if (!BP_NOMCP(bp)) {
5137 int mb_idx = BP_FW_MB_IDX(bp);
5138 u32 drv_pulse;
5139 u32 mcp_pulse;
5140
5141 ++bp->fw_drv_pulse_wr_seq;
5142 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5143 /* TBD - add SYSTEM_TIME */
5144 drv_pulse = bp->fw_drv_pulse_wr_seq;
5145 bnx2x_drv_pulse(bp);
5146
5147 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5148 MCP_PULSE_SEQ_MASK);
5149 /* The delta between driver pulse and mcp response
5150 * should be 1 (before mcp response) or 0 (after mcp response)
5151 */
5152 if ((drv_pulse != mcp_pulse) &&
5153 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5154 /* someone lost a heartbeat... */
5155 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5156 drv_pulse, mcp_pulse);
5157 }
5158 }
5159
5160 if (bp->state == BNX2X_STATE_OPEN)
5161 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5162
5163 mod_timer(&bp->timer, jiffies + bp->current_interval);
5164 }
5165
5166 /* end of Statistics */
5167
5168 /* nic init */
5169
5170 /*
5171 * nic init service functions
5172 */
5173
5174 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5175 {
5176 u32 i;
5177 if (!(len%4) && !(addr%4))
5178 for (i = 0; i < len; i += 4)
5179 REG_WR(bp, addr + i, fill);
5180 else
5181 for (i = 0; i < len; i++)
5182 REG_WR8(bp, addr + i, fill);
5183
5184 }
5185
5186 /* helper: writes FP SP data to FW - data_size in dwords */
5187 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5188 int fw_sb_id,
5189 u32 *sb_data_p,
5190 u32 data_size)
5191 {
5192 int index;
5193 for (index = 0; index < data_size; index++)
5194 REG_WR(bp, BAR_CSTRORM_INTMEM +
5195 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5196 sizeof(u32)*index,
5197 *(sb_data_p + index));
5198 }
5199
5200 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5201 {
5202 u32 *sb_data_p;
5203 u32 data_size = 0;
5204 struct hc_status_block_data_e2 sb_data_e2;
5205 struct hc_status_block_data_e1x sb_data_e1x;
5206
5207 /* disable the function first */
5208 if (!CHIP_IS_E1x(bp)) {
5209 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5210 sb_data_e2.common.state = SB_DISABLED;
5211 sb_data_e2.common.p_func.vf_valid = false;
5212 sb_data_p = (u32 *)&sb_data_e2;
5213 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5214 } else {
5215 memset(&sb_data_e1x, 0,
5216 sizeof(struct hc_status_block_data_e1x));
5217 sb_data_e1x.common.state = SB_DISABLED;
5218 sb_data_e1x.common.p_func.vf_valid = false;
5219 sb_data_p = (u32 *)&sb_data_e1x;
5220 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5221 }
5222 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5223
5224 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5225 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5226 CSTORM_STATUS_BLOCK_SIZE);
5227 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5228 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5229 CSTORM_SYNC_BLOCK_SIZE);
5230 }
5231
5232 /* helper: writes SP SB data to FW */
5233 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5234 struct hc_sp_status_block_data *sp_sb_data)
5235 {
5236 int func = BP_FUNC(bp);
5237 int i;
5238 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5239 REG_WR(bp, BAR_CSTRORM_INTMEM +
5240 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5241 i*sizeof(u32),
5242 *((u32 *)sp_sb_data + i));
5243 }
5244
5245 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5246 {
5247 int func = BP_FUNC(bp);
5248 struct hc_sp_status_block_data sp_sb_data;
5249 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5250
5251 sp_sb_data.state = SB_DISABLED;
5252 sp_sb_data.p_func.vf_valid = false;
5253
5254 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5255
5256 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5257 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5258 CSTORM_SP_STATUS_BLOCK_SIZE);
5259 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5260 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5261 CSTORM_SP_SYNC_BLOCK_SIZE);
5262
5263 }
5264
5265
5266 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5267 int igu_sb_id, int igu_seg_id)
5268 {
5269 hc_sm->igu_sb_id = igu_sb_id;
5270 hc_sm->igu_seg_id = igu_seg_id;
5271 hc_sm->timer_value = 0xFF;
5272 hc_sm->time_to_expire = 0xFFFFFFFF;
5273 }
5274
5275
5276 /* allocates state machine ids. */
5277 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5278 {
5279 /* zero out state machine indices */
5280 /* rx indices */
5281 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5282
5283 /* tx indices */
5284 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5285 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5286 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5287 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5288
5289 /* map indices */
5290 /* rx indices */
5291 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5292 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5293
5294 /* tx indices */
5295 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5296 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5297 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5298 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5299 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5300 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5301 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5302 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5303 }
5304
5305 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5306 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5307 {
5308 int igu_seg_id;
5309
5310 struct hc_status_block_data_e2 sb_data_e2;
5311 struct hc_status_block_data_e1x sb_data_e1x;
5312 struct hc_status_block_sm *hc_sm_p;
5313 int data_size;
5314 u32 *sb_data_p;
5315
5316 if (CHIP_INT_MODE_IS_BC(bp))
5317 igu_seg_id = HC_SEG_ACCESS_NORM;
5318 else
5319 igu_seg_id = IGU_SEG_ACCESS_NORM;
5320
5321 bnx2x_zero_fp_sb(bp, fw_sb_id);
5322
5323 if (!CHIP_IS_E1x(bp)) {
5324 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5325 sb_data_e2.common.state = SB_ENABLED;
5326 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5327 sb_data_e2.common.p_func.vf_id = vfid;
5328 sb_data_e2.common.p_func.vf_valid = vf_valid;
5329 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5330 sb_data_e2.common.same_igu_sb_1b = true;
5331 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5332 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5333 hc_sm_p = sb_data_e2.common.state_machine;
5334 sb_data_p = (u32 *)&sb_data_e2;
5335 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5336 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5337 } else {
5338 memset(&sb_data_e1x, 0,
5339 sizeof(struct hc_status_block_data_e1x));
5340 sb_data_e1x.common.state = SB_ENABLED;
5341 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5342 sb_data_e1x.common.p_func.vf_id = 0xff;
5343 sb_data_e1x.common.p_func.vf_valid = false;
5344 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5345 sb_data_e1x.common.same_igu_sb_1b = true;
5346 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5347 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5348 hc_sm_p = sb_data_e1x.common.state_machine;
5349 sb_data_p = (u32 *)&sb_data_e1x;
5350 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5351 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5352 }
5353
5354 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5355 igu_sb_id, igu_seg_id);
5356 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5357 igu_sb_id, igu_seg_id);
5358
5359 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5360
5361 /* write indecies to HW */
5362 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5363 }
5364
5365 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5366 u16 tx_usec, u16 rx_usec)
5367 {
5368 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5369 false, rx_usec);
5370 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5371 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5372 tx_usec);
5373 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5374 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5375 tx_usec);
5376 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5377 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5378 tx_usec);
5379 }
5380
5381 static void bnx2x_init_def_sb(struct bnx2x *bp)
5382 {
5383 struct host_sp_status_block *def_sb = bp->def_status_blk;
5384 dma_addr_t mapping = bp->def_status_blk_mapping;
5385 int igu_sp_sb_index;
5386 int igu_seg_id;
5387 int port = BP_PORT(bp);
5388 int func = BP_FUNC(bp);
5389 int reg_offset, reg_offset_en5;
5390 u64 section;
5391 int index;
5392 struct hc_sp_status_block_data sp_sb_data;
5393 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5394
5395 if (CHIP_INT_MODE_IS_BC(bp)) {
5396 igu_sp_sb_index = DEF_SB_IGU_ID;
5397 igu_seg_id = HC_SEG_ACCESS_DEF;
5398 } else {
5399 igu_sp_sb_index = bp->igu_dsb_id;
5400 igu_seg_id = IGU_SEG_ACCESS_DEF;
5401 }
5402
5403 /* ATTN */
5404 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5405 atten_status_block);
5406 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5407
5408 bp->attn_state = 0;
5409
5410 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5411 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5412 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5413 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5414 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5415 int sindex;
5416 /* take care of sig[0]..sig[4] */
5417 for (sindex = 0; sindex < 4; sindex++)
5418 bp->attn_group[index].sig[sindex] =
5419 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5420
5421 if (!CHIP_IS_E1x(bp))
5422 /*
5423 * enable5 is separate from the rest of the registers,
5424 * and therefore the address skip is 4
5425 * and not 16 between the different groups
5426 */
5427 bp->attn_group[index].sig[4] = REG_RD(bp,
5428 reg_offset_en5 + 0x4*index);
5429 else
5430 bp->attn_group[index].sig[4] = 0;
5431 }
5432
5433 if (bp->common.int_block == INT_BLOCK_HC) {
5434 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5435 HC_REG_ATTN_MSG0_ADDR_L);
5436
5437 REG_WR(bp, reg_offset, U64_LO(section));
5438 REG_WR(bp, reg_offset + 4, U64_HI(section));
5439 } else if (!CHIP_IS_E1x(bp)) {
5440 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5441 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5442 }
5443
5444 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5445 sp_sb);
5446
5447 bnx2x_zero_sp_sb(bp);
5448
5449 sp_sb_data.state = SB_ENABLED;
5450 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5451 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5452 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5453 sp_sb_data.igu_seg_id = igu_seg_id;
5454 sp_sb_data.p_func.pf_id = func;
5455 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5456 sp_sb_data.p_func.vf_id = 0xff;
5457
5458 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5459
5460 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5461 }
5462
5463 void bnx2x_update_coalesce(struct bnx2x *bp)
5464 {
5465 int i;
5466
5467 for_each_eth_queue(bp, i)
5468 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5469 bp->tx_ticks, bp->rx_ticks);
5470 }
5471
5472 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5473 {
5474 spin_lock_init(&bp->spq_lock);
5475 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5476
5477 bp->spq_prod_idx = 0;
5478 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5479 bp->spq_prod_bd = bp->spq;
5480 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5481 }
5482
5483 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5484 {
5485 int i;
5486 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5487 union event_ring_elem *elem =
5488 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5489
5490 elem->next_page.addr.hi =
5491 cpu_to_le32(U64_HI(bp->eq_mapping +
5492 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5493 elem->next_page.addr.lo =
5494 cpu_to_le32(U64_LO(bp->eq_mapping +
5495 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5496 }
5497 bp->eq_cons = 0;
5498 bp->eq_prod = NUM_EQ_DESC;
5499 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5500 /* we want a warning message before it gets rought... */
5501 atomic_set(&bp->eq_spq_left,
5502 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5503 }
5504
5505
5506 /* called with netif_addr_lock_bh() */
5507 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5508 unsigned long rx_mode_flags,
5509 unsigned long rx_accept_flags,
5510 unsigned long tx_accept_flags,
5511 unsigned long ramrod_flags)
5512 {
5513 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5514 int rc;
5515
5516 memset(&ramrod_param, 0, sizeof(ramrod_param));
5517
5518 /* Prepare ramrod parameters */
5519 ramrod_param.cid = 0;
5520 ramrod_param.cl_id = cl_id;
5521 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5522 ramrod_param.func_id = BP_FUNC(bp);
5523
5524 ramrod_param.pstate = &bp->sp_state;
5525 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5526
5527 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5528 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5529
5530 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5531
5532 ramrod_param.ramrod_flags = ramrod_flags;
5533 ramrod_param.rx_mode_flags = rx_mode_flags;
5534
5535 ramrod_param.rx_accept_flags = rx_accept_flags;
5536 ramrod_param.tx_accept_flags = tx_accept_flags;
5537
5538 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5539 if (rc < 0) {
5540 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5541 return;
5542 }
5543 }
5544
5545 /* called with netif_addr_lock_bh() */
5546 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5547 {
5548 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5549 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5550
5551 if (!NO_FCOE(bp))
5552
5553 /* Configure rx_mode of FCoE Queue */
5554 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5555
5556 switch (bp->rx_mode) {
5557 case BNX2X_RX_MODE_NONE:
5558 /*
5559 * 'drop all' supersedes any accept flags that may have been
5560 * passed to the function.
5561 */
5562 break;
5563 case BNX2X_RX_MODE_NORMAL:
5564 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5565 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5566 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5567
5568 /* internal switching mode */
5569 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5570 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5571 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5572
5573 break;
5574 case BNX2X_RX_MODE_ALLMULTI:
5575 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5576 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5577 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5578
5579 /* internal switching mode */
5580 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5581 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5582 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5583
5584 break;
5585 case BNX2X_RX_MODE_PROMISC:
5586 /* According to deffinition of SI mode, iface in promisc mode
5587 * should receive matched and unmatched (in resolution of port)
5588 * unicast packets.
5589 */
5590 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5591 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5592 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5593 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5594
5595 /* internal switching mode */
5596 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5597 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5598
5599 if (IS_MF_SI(bp))
5600 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5601 else
5602 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5603
5604 break;
5605 default:
5606 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5607 return;
5608 }
5609
5610 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5611 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5612 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5613 }
5614
5615 __set_bit(RAMROD_RX, &ramrod_flags);
5616 __set_bit(RAMROD_TX, &ramrod_flags);
5617
5618 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5619 tx_accept_flags, ramrod_flags);
5620 }
5621
5622 static void bnx2x_init_internal_common(struct bnx2x *bp)
5623 {
5624 int i;
5625
5626 if (IS_MF_SI(bp))
5627 /*
5628 * In switch independent mode, the TSTORM needs to accept
5629 * packets that failed classification, since approximate match
5630 * mac addresses aren't written to NIG LLH
5631 */
5632 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5633 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5634 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5635 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5636 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5637
5638 /* Zero this manually as its initialization is
5639 currently missing in the initTool */
5640 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5641 REG_WR(bp, BAR_USTRORM_INTMEM +
5642 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5643 if (!CHIP_IS_E1x(bp)) {
5644 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5645 CHIP_INT_MODE_IS_BC(bp) ?
5646 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5647 }
5648 }
5649
5650 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5651 {
5652 switch (load_code) {
5653 case FW_MSG_CODE_DRV_LOAD_COMMON:
5654 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5655 bnx2x_init_internal_common(bp);
5656 /* no break */
5657
5658 case FW_MSG_CODE_DRV_LOAD_PORT:
5659 /* nothing to do */
5660 /* no break */
5661
5662 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5663 /* internal memory per function is
5664 initialized inside bnx2x_pf_init */
5665 break;
5666
5667 default:
5668 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5669 break;
5670 }
5671 }
5672
5673 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5674 {
5675 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
5676 }
5677
5678 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5679 {
5680 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
5681 }
5682
5683 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5684 {
5685 if (CHIP_IS_E1x(fp->bp))
5686 return BP_L_ID(fp->bp) + fp->index;
5687 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5688 return bnx2x_fp_igu_sb_id(fp);
5689 }
5690
5691 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5692 {
5693 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5694 u8 cos;
5695 unsigned long q_type = 0;
5696 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5697 fp->rx_queue = fp_idx;
5698 fp->cid = fp_idx;
5699 fp->cl_id = bnx2x_fp_cl_id(fp);
5700 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5701 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5702 /* qZone id equals to FW (per path) client id */
5703 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5704
5705 /* init shortcut */
5706 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5707
5708 /* Setup SB indicies */
5709 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5710
5711 /* Configure Queue State object */
5712 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5713 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5714
5715 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5716
5717 /* init tx data */
5718 for_each_cos_in_tx_queue(fp, cos) {
5719 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5720 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5721 FP_COS_TO_TXQ(fp, cos, bp),
5722 BNX2X_TX_SB_INDEX_BASE + cos, fp);
5723 cids[cos] = fp->txdata_ptr[cos]->cid;
5724 }
5725
5726 /* nothing more for vf to do here */
5727 if (IS_VF(bp))
5728 return;
5729
5730 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5731 fp->fw_sb_id, fp->igu_sb_id);
5732 bnx2x_update_fpsb_idx(fp);
5733 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5734 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5735 bnx2x_sp_mapping(bp, q_rdata), q_type);
5736
5737 /**
5738 * Configure classification DBs: Always enable Tx switching
5739 */
5740 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5741
5742 DP(NETIF_MSG_IFUP,
5743 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5744 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5745 fp->igu_sb_id);
5746 }
5747
5748 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5749 {
5750 int i;
5751
5752 for (i = 1; i <= NUM_TX_RINGS; i++) {
5753 struct eth_tx_next_bd *tx_next_bd =
5754 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5755
5756 tx_next_bd->addr_hi =
5757 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5758 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5759 tx_next_bd->addr_lo =
5760 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5761 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5762 }
5763
5764 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5765 txdata->tx_db.data.zero_fill1 = 0;
5766 txdata->tx_db.data.prod = 0;
5767
5768 txdata->tx_pkt_prod = 0;
5769 txdata->tx_pkt_cons = 0;
5770 txdata->tx_bd_prod = 0;
5771 txdata->tx_bd_cons = 0;
5772 txdata->tx_pkt = 0;
5773 }
5774
5775 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
5776 {
5777 int i;
5778
5779 for_each_tx_queue_cnic(bp, i)
5780 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
5781 }
5782 static void bnx2x_init_tx_rings(struct bnx2x *bp)
5783 {
5784 int i;
5785 u8 cos;
5786
5787 for_each_eth_queue(bp, i)
5788 for_each_cos_in_tx_queue(&bp->fp[i], cos)
5789 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
5790 }
5791
5792 void bnx2x_nic_init_cnic(struct bnx2x *bp)
5793 {
5794 if (!NO_FCOE(bp))
5795 bnx2x_init_fcoe_fp(bp);
5796
5797 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5798 BNX2X_VF_ID_INVALID, false,
5799 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5800
5801 /* ensure status block indices were read */
5802 rmb();
5803 bnx2x_init_rx_rings_cnic(bp);
5804 bnx2x_init_tx_rings_cnic(bp);
5805
5806 /* flush all */
5807 mb();
5808 mmiowb();
5809 }
5810
5811 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5812 {
5813 int i;
5814
5815 for_each_eth_queue(bp, i)
5816 bnx2x_init_eth_fp(bp, i);
5817
5818 /* ensure status block indices were read */
5819 rmb();
5820 bnx2x_init_rx_rings(bp);
5821 bnx2x_init_tx_rings(bp);
5822
5823 if (IS_VF(bp))
5824 return;
5825
5826 /* Initialize MOD_ABS interrupts */
5827 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5828 bp->common.shmem_base, bp->common.shmem2_base,
5829 BP_PORT(bp));
5830
5831 bnx2x_init_def_sb(bp);
5832 bnx2x_update_dsb_idx(bp);
5833 bnx2x_init_sp_ring(bp);
5834 bnx2x_init_eq_ring(bp);
5835 bnx2x_init_internal(bp, load_code);
5836 bnx2x_pf_init(bp);
5837 bnx2x_stats_init(bp);
5838
5839 /* flush all before enabling interrupts */
5840 mb();
5841 mmiowb();
5842
5843 bnx2x_int_enable(bp);
5844
5845 /* Check for SPIO5 */
5846 bnx2x_attn_int_deasserted0(bp,
5847 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5848 AEU_INPUTS_ATTN_BITS_SPIO5);
5849 }
5850
5851 /* end of nic init */
5852
5853 /*
5854 * gzip service functions
5855 */
5856
5857 static int bnx2x_gunzip_init(struct bnx2x *bp)
5858 {
5859 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5860 &bp->gunzip_mapping, GFP_KERNEL);
5861 if (bp->gunzip_buf == NULL)
5862 goto gunzip_nomem1;
5863
5864 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5865 if (bp->strm == NULL)
5866 goto gunzip_nomem2;
5867
5868 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5869 if (bp->strm->workspace == NULL)
5870 goto gunzip_nomem3;
5871
5872 return 0;
5873
5874 gunzip_nomem3:
5875 kfree(bp->strm);
5876 bp->strm = NULL;
5877
5878 gunzip_nomem2:
5879 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5880 bp->gunzip_mapping);
5881 bp->gunzip_buf = NULL;
5882
5883 gunzip_nomem1:
5884 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
5885 return -ENOMEM;
5886 }
5887
5888 static void bnx2x_gunzip_end(struct bnx2x *bp)
5889 {
5890 if (bp->strm) {
5891 vfree(bp->strm->workspace);
5892 kfree(bp->strm);
5893 bp->strm = NULL;
5894 }
5895
5896 if (bp->gunzip_buf) {
5897 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5898 bp->gunzip_mapping);
5899 bp->gunzip_buf = NULL;
5900 }
5901 }
5902
5903 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5904 {
5905 int n, rc;
5906
5907 /* check gzip header */
5908 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5909 BNX2X_ERR("Bad gzip header\n");
5910 return -EINVAL;
5911 }
5912
5913 n = 10;
5914
5915 #define FNAME 0x8
5916
5917 if (zbuf[3] & FNAME)
5918 while ((zbuf[n++] != 0) && (n < len));
5919
5920 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5921 bp->strm->avail_in = len - n;
5922 bp->strm->next_out = bp->gunzip_buf;
5923 bp->strm->avail_out = FW_BUF_SIZE;
5924
5925 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5926 if (rc != Z_OK)
5927 return rc;
5928
5929 rc = zlib_inflate(bp->strm, Z_FINISH);
5930 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5931 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5932 bp->strm->msg);
5933
5934 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5935 if (bp->gunzip_outlen & 0x3)
5936 netdev_err(bp->dev,
5937 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
5938 bp->gunzip_outlen);
5939 bp->gunzip_outlen >>= 2;
5940
5941 zlib_inflateEnd(bp->strm);
5942
5943 if (rc == Z_STREAM_END)
5944 return 0;
5945
5946 return rc;
5947 }
5948
5949 /* nic load/unload */
5950
5951 /*
5952 * General service functions
5953 */
5954
5955 /* send a NIG loopback debug packet */
5956 static void bnx2x_lb_pckt(struct bnx2x *bp)
5957 {
5958 u32 wb_write[3];
5959
5960 /* Ethernet source and destination addresses */
5961 wb_write[0] = 0x55555555;
5962 wb_write[1] = 0x55555555;
5963 wb_write[2] = 0x20; /* SOP */
5964 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5965
5966 /* NON-IP protocol */
5967 wb_write[0] = 0x09000000;
5968 wb_write[1] = 0x55555555;
5969 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5970 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5971 }
5972
5973 /* some of the internal memories
5974 * are not directly readable from the driver
5975 * to test them we send debug packets
5976 */
5977 static int bnx2x_int_mem_test(struct bnx2x *bp)
5978 {
5979 int factor;
5980 int count, i;
5981 u32 val = 0;
5982
5983 if (CHIP_REV_IS_FPGA(bp))
5984 factor = 120;
5985 else if (CHIP_REV_IS_EMUL(bp))
5986 factor = 200;
5987 else
5988 factor = 1;
5989
5990 /* Disable inputs of parser neighbor blocks */
5991 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5992 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5993 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5994 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5995
5996 /* Write 0 to parser credits for CFC search request */
5997 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5998
5999 /* send Ethernet packet */
6000 bnx2x_lb_pckt(bp);
6001
6002 /* TODO do i reset NIG statistic? */
6003 /* Wait until NIG register shows 1 packet of size 0x10 */
6004 count = 1000 * factor;
6005 while (count) {
6006
6007 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6008 val = *bnx2x_sp(bp, wb_data[0]);
6009 if (val == 0x10)
6010 break;
6011
6012 msleep(10);
6013 count--;
6014 }
6015 if (val != 0x10) {
6016 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6017 return -1;
6018 }
6019
6020 /* Wait until PRS register shows 1 packet */
6021 count = 1000 * factor;
6022 while (count) {
6023 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6024 if (val == 1)
6025 break;
6026
6027 msleep(10);
6028 count--;
6029 }
6030 if (val != 0x1) {
6031 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6032 return -2;
6033 }
6034
6035 /* Reset and init BRB, PRS */
6036 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6037 msleep(50);
6038 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6039 msleep(50);
6040 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6041 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6042
6043 DP(NETIF_MSG_HW, "part2\n");
6044
6045 /* Disable inputs of parser neighbor blocks */
6046 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6047 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6048 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6049 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6050
6051 /* Write 0 to parser credits for CFC search request */
6052 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6053
6054 /* send 10 Ethernet packets */
6055 for (i = 0; i < 10; i++)
6056 bnx2x_lb_pckt(bp);
6057
6058 /* Wait until NIG register shows 10 + 1
6059 packets of size 11*0x10 = 0xb0 */
6060 count = 1000 * factor;
6061 while (count) {
6062
6063 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6064 val = *bnx2x_sp(bp, wb_data[0]);
6065 if (val == 0xb0)
6066 break;
6067
6068 msleep(10);
6069 count--;
6070 }
6071 if (val != 0xb0) {
6072 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6073 return -3;
6074 }
6075
6076 /* Wait until PRS register shows 2 packets */
6077 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6078 if (val != 2)
6079 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6080
6081 /* Write 1 to parser credits for CFC search request */
6082 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6083
6084 /* Wait until PRS register shows 3 packets */
6085 msleep(10 * factor);
6086 /* Wait until NIG register shows 1 packet of size 0x10 */
6087 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6088 if (val != 3)
6089 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6090
6091 /* clear NIG EOP FIFO */
6092 for (i = 0; i < 11; i++)
6093 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6094 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6095 if (val != 1) {
6096 BNX2X_ERR("clear of NIG failed\n");
6097 return -4;
6098 }
6099
6100 /* Reset and init BRB, PRS, NIG */
6101 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6102 msleep(50);
6103 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6104 msleep(50);
6105 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6106 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6107 if (!CNIC_SUPPORT(bp))
6108 /* set NIC mode */
6109 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6110
6111 /* Enable inputs of parser neighbor blocks */
6112 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6113 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6114 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6115 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6116
6117 DP(NETIF_MSG_HW, "done\n");
6118
6119 return 0; /* OK */
6120 }
6121
6122 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6123 {
6124 u32 val;
6125
6126 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6127 if (!CHIP_IS_E1x(bp))
6128 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6129 else
6130 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6131 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6132 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6133 /*
6134 * mask read length error interrupts in brb for parser
6135 * (parsing unit and 'checksum and crc' unit)
6136 * these errors are legal (PU reads fixed length and CAC can cause
6137 * read length error on truncated packets)
6138 */
6139 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6140 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6141 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6142 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6143 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6144 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6145 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6146 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6147 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6148 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6149 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6150 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6151 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6152 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6153 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6154 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6155 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6156 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6157 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6158
6159 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6160 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6161 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6162 if (!CHIP_IS_E1x(bp))
6163 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6164 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6165 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6166
6167 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6168 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6169 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6170 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6171
6172 if (!CHIP_IS_E1x(bp))
6173 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6174 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6175
6176 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6177 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6178 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6179 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6180 }
6181
6182 static void bnx2x_reset_common(struct bnx2x *bp)
6183 {
6184 u32 val = 0x1400;
6185
6186 /* reset_common */
6187 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6188 0xd3ffff7f);
6189
6190 if (CHIP_IS_E3(bp)) {
6191 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6192 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6193 }
6194
6195 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6196 }
6197
6198 static void bnx2x_setup_dmae(struct bnx2x *bp)
6199 {
6200 bp->dmae_ready = 0;
6201 spin_lock_init(&bp->dmae_lock);
6202 }
6203
6204 static void bnx2x_init_pxp(struct bnx2x *bp)
6205 {
6206 u16 devctl;
6207 int r_order, w_order;
6208
6209 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6210 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6211 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6212 if (bp->mrrs == -1)
6213 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6214 else {
6215 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6216 r_order = bp->mrrs;
6217 }
6218
6219 bnx2x_init_pxp_arb(bp, r_order, w_order);
6220 }
6221
6222 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6223 {
6224 int is_required;
6225 u32 val;
6226 int port;
6227
6228 if (BP_NOMCP(bp))
6229 return;
6230
6231 is_required = 0;
6232 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6233 SHARED_HW_CFG_FAN_FAILURE_MASK;
6234
6235 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6236 is_required = 1;
6237
6238 /*
6239 * The fan failure mechanism is usually related to the PHY type since
6240 * the power consumption of the board is affected by the PHY. Currently,
6241 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6242 */
6243 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6244 for (port = PORT_0; port < PORT_MAX; port++) {
6245 is_required |=
6246 bnx2x_fan_failure_det_req(
6247 bp,
6248 bp->common.shmem_base,
6249 bp->common.shmem2_base,
6250 port);
6251 }
6252
6253 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6254
6255 if (is_required == 0)
6256 return;
6257
6258 /* Fan failure is indicated by SPIO 5 */
6259 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6260
6261 /* set to active low mode */
6262 val = REG_RD(bp, MISC_REG_SPIO_INT);
6263 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6264 REG_WR(bp, MISC_REG_SPIO_INT, val);
6265
6266 /* enable interrupt to signal the IGU */
6267 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6268 val |= MISC_SPIO_SPIO5;
6269 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6270 }
6271
6272 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
6273 {
6274 u32 offset = 0;
6275
6276 if (CHIP_IS_E1(bp))
6277 return;
6278 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
6279 return;
6280
6281 switch (BP_ABS_FUNC(bp)) {
6282 case 0:
6283 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
6284 break;
6285 case 1:
6286 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
6287 break;
6288 case 2:
6289 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
6290 break;
6291 case 3:
6292 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
6293 break;
6294 case 4:
6295 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
6296 break;
6297 case 5:
6298 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
6299 break;
6300 case 6:
6301 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
6302 break;
6303 case 7:
6304 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
6305 break;
6306 default:
6307 return;
6308 }
6309
6310 REG_WR(bp, offset, pretend_func_num);
6311 REG_RD(bp, offset);
6312 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
6313 }
6314
6315 void bnx2x_pf_disable(struct bnx2x *bp)
6316 {
6317 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6318 val &= ~IGU_PF_CONF_FUNC_EN;
6319
6320 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6321 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6322 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6323 }
6324
6325 static void bnx2x__common_init_phy(struct bnx2x *bp)
6326 {
6327 u32 shmem_base[2], shmem2_base[2];
6328 /* Avoid common init in case MFW supports LFA */
6329 if (SHMEM2_RD(bp, size) >
6330 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6331 return;
6332 shmem_base[0] = bp->common.shmem_base;
6333 shmem2_base[0] = bp->common.shmem2_base;
6334 if (!CHIP_IS_E1x(bp)) {
6335 shmem_base[1] =
6336 SHMEM2_RD(bp, other_shmem_base_addr);
6337 shmem2_base[1] =
6338 SHMEM2_RD(bp, other_shmem2_base_addr);
6339 }
6340 bnx2x_acquire_phy_lock(bp);
6341 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6342 bp->common.chip_id);
6343 bnx2x_release_phy_lock(bp);
6344 }
6345
6346 /**
6347 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6348 *
6349 * @bp: driver handle
6350 */
6351 static int bnx2x_init_hw_common(struct bnx2x *bp)
6352 {
6353 u32 val;
6354
6355 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6356
6357 /*
6358 * take the UNDI lock to protect undi_unload flow from accessing
6359 * registers while we're resetting the chip
6360 */
6361 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6362
6363 bnx2x_reset_common(bp);
6364 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6365
6366 val = 0xfffc;
6367 if (CHIP_IS_E3(bp)) {
6368 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6369 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6370 }
6371 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6372
6373 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6374
6375 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6376
6377 if (!CHIP_IS_E1x(bp)) {
6378 u8 abs_func_id;
6379
6380 /**
6381 * 4-port mode or 2-port mode we need to turn of master-enable
6382 * for everyone, after that, turn it back on for self.
6383 * so, we disregard multi-function or not, and always disable
6384 * for all functions on the given path, this means 0,2,4,6 for
6385 * path 0 and 1,3,5,7 for path 1
6386 */
6387 for (abs_func_id = BP_PATH(bp);
6388 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6389 if (abs_func_id == BP_ABS_FUNC(bp)) {
6390 REG_WR(bp,
6391 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6392 1);
6393 continue;
6394 }
6395
6396 bnx2x_pretend_func(bp, abs_func_id);
6397 /* clear pf enable */
6398 bnx2x_pf_disable(bp);
6399 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6400 }
6401 }
6402
6403 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6404 if (CHIP_IS_E1(bp)) {
6405 /* enable HW interrupt from PXP on USDM overflow
6406 bit 16 on INT_MASK_0 */
6407 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6408 }
6409
6410 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6411 bnx2x_init_pxp(bp);
6412
6413 #ifdef __BIG_ENDIAN
6414 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6415 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6416 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6417 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6418 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6419 /* make sure this value is 0 */
6420 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6421
6422 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6423 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6424 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6425 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6426 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6427 #endif
6428
6429 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6430
6431 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6432 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6433
6434 /* let the HW do it's magic ... */
6435 msleep(100);
6436 /* finish PXP init */
6437 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6438 if (val != 1) {
6439 BNX2X_ERR("PXP2 CFG failed\n");
6440 return -EBUSY;
6441 }
6442 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6443 if (val != 1) {
6444 BNX2X_ERR("PXP2 RD_INIT failed\n");
6445 return -EBUSY;
6446 }
6447
6448 /* Timers bug workaround E2 only. We need to set the entire ILT to
6449 * have entries with value "0" and valid bit on.
6450 * This needs to be done by the first PF that is loaded in a path
6451 * (i.e. common phase)
6452 */
6453 if (!CHIP_IS_E1x(bp)) {
6454 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6455 * (i.e. vnic3) to start even if it is marked as "scan-off".
6456 * This occurs when a different function (func2,3) is being marked
6457 * as "scan-off". Real-life scenario for example: if a driver is being
6458 * load-unloaded while func6,7 are down. This will cause the timer to access
6459 * the ilt, translate to a logical address and send a request to read/write.
6460 * Since the ilt for the function that is down is not valid, this will cause
6461 * a translation error which is unrecoverable.
6462 * The Workaround is intended to make sure that when this happens nothing fatal
6463 * will occur. The workaround:
6464 * 1. First PF driver which loads on a path will:
6465 * a. After taking the chip out of reset, by using pretend,
6466 * it will write "0" to the following registers of
6467 * the other vnics.
6468 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6469 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6470 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6471 * And for itself it will write '1' to
6472 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6473 * dmae-operations (writing to pram for example.)
6474 * note: can be done for only function 6,7 but cleaner this
6475 * way.
6476 * b. Write zero+valid to the entire ILT.
6477 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6478 * VNIC3 (of that port). The range allocated will be the
6479 * entire ILT. This is needed to prevent ILT range error.
6480 * 2. Any PF driver load flow:
6481 * a. ILT update with the physical addresses of the allocated
6482 * logical pages.
6483 * b. Wait 20msec. - note that this timeout is needed to make
6484 * sure there are no requests in one of the PXP internal
6485 * queues with "old" ILT addresses.
6486 * c. PF enable in the PGLC.
6487 * d. Clear the was_error of the PF in the PGLC. (could have
6488 * occured while driver was down)
6489 * e. PF enable in the CFC (WEAK + STRONG)
6490 * f. Timers scan enable
6491 * 3. PF driver unload flow:
6492 * a. Clear the Timers scan_en.
6493 * b. Polling for scan_on=0 for that PF.
6494 * c. Clear the PF enable bit in the PXP.
6495 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6496 * e. Write zero+valid to all ILT entries (The valid bit must
6497 * stay set)
6498 * f. If this is VNIC 3 of a port then also init
6499 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6500 * to the last enrty in the ILT.
6501 *
6502 * Notes:
6503 * Currently the PF error in the PGLC is non recoverable.
6504 * In the future the there will be a recovery routine for this error.
6505 * Currently attention is masked.
6506 * Having an MCP lock on the load/unload process does not guarantee that
6507 * there is no Timer disable during Func6/7 enable. This is because the
6508 * Timers scan is currently being cleared by the MCP on FLR.
6509 * Step 2.d can be done only for PF6/7 and the driver can also check if
6510 * there is error before clearing it. But the flow above is simpler and
6511 * more general.
6512 * All ILT entries are written by zero+valid and not just PF6/7
6513 * ILT entries since in the future the ILT entries allocation for
6514 * PF-s might be dynamic.
6515 */
6516 struct ilt_client_info ilt_cli;
6517 struct bnx2x_ilt ilt;
6518 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6519 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6520
6521 /* initialize dummy TM client */
6522 ilt_cli.start = 0;
6523 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6524 ilt_cli.client_num = ILT_CLIENT_TM;
6525
6526 /* Step 1: set zeroes to all ilt page entries with valid bit on
6527 * Step 2: set the timers first/last ilt entry to point
6528 * to the entire range to prevent ILT range error for 3rd/4th
6529 * vnic (this code assumes existance of the vnic)
6530 *
6531 * both steps performed by call to bnx2x_ilt_client_init_op()
6532 * with dummy TM client
6533 *
6534 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6535 * and his brother are split registers
6536 */
6537 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6538 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6539 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6540
6541 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6542 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6543 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6544 }
6545
6546
6547 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6548 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6549
6550 if (!CHIP_IS_E1x(bp)) {
6551 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6552 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6553 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6554
6555 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6556
6557 /* let the HW do it's magic ... */
6558 do {
6559 msleep(200);
6560 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6561 } while (factor-- && (val != 1));
6562
6563 if (val != 1) {
6564 BNX2X_ERR("ATC_INIT failed\n");
6565 return -EBUSY;
6566 }
6567 }
6568
6569 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6570
6571 /* clean the DMAE memory */
6572 bp->dmae_ready = 1;
6573 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6574
6575 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6576
6577 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6578
6579 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6580
6581 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6582
6583 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6584 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6585 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6586 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6587
6588 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6589
6590
6591 /* QM queues pointers table */
6592 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6593
6594 /* soft reset pulse */
6595 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6596 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6597
6598 if (CNIC_SUPPORT(bp))
6599 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6600
6601 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6602 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6603 if (!CHIP_REV_IS_SLOW(bp))
6604 /* enable hw interrupt from doorbell Q */
6605 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6606
6607 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6608
6609 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6610 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6611
6612 if (!CHIP_IS_E1(bp))
6613 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6614
6615 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6616 if (IS_MF_AFEX(bp)) {
6617 /* configure that VNTag and VLAN headers must be
6618 * received in afex mode
6619 */
6620 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6621 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6622 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6623 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6624 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6625 } else {
6626 /* Bit-map indicating which L2 hdrs may appear
6627 * after the basic Ethernet header
6628 */
6629 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6630 bp->path_has_ovlan ? 7 : 6);
6631 }
6632 }
6633
6634 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6635 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6636 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6637 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6638
6639 if (!CHIP_IS_E1x(bp)) {
6640 /* reset VFC memories */
6641 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6642 VFC_MEMORIES_RST_REG_CAM_RST |
6643 VFC_MEMORIES_RST_REG_RAM_RST);
6644 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6645 VFC_MEMORIES_RST_REG_CAM_RST |
6646 VFC_MEMORIES_RST_REG_RAM_RST);
6647
6648 msleep(20);
6649 }
6650
6651 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6652 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6653 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6654 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6655
6656 /* sync semi rtc */
6657 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6658 0x80000000);
6659 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6660 0x80000000);
6661
6662 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6663 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6664 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6665
6666 if (!CHIP_IS_E1x(bp)) {
6667 if (IS_MF_AFEX(bp)) {
6668 /* configure that VNTag and VLAN headers must be
6669 * sent in afex mode
6670 */
6671 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6672 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6673 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6674 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6675 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6676 } else {
6677 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6678 bp->path_has_ovlan ? 7 : 6);
6679 }
6680 }
6681
6682 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6683
6684 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6685
6686 if (CNIC_SUPPORT(bp)) {
6687 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6688 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6689 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6690 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6691 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6692 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6693 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6694 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6695 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6696 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6697 }
6698 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6699
6700 if (sizeof(union cdu_context) != 1024)
6701 /* we currently assume that a context is 1024 bytes */
6702 dev_alert(&bp->pdev->dev,
6703 "please adjust the size of cdu_context(%ld)\n",
6704 (long)sizeof(union cdu_context));
6705
6706 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6707 val = (4 << 24) + (0 << 12) + 1024;
6708 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6709
6710 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6711 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6712 /* enable context validation interrupt from CFC */
6713 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6714
6715 /* set the thresholds to prevent CFC/CDU race */
6716 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6717
6718 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6719
6720 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6721 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6722
6723 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6724 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6725
6726 /* Reset PCIE errors for debug */
6727 REG_WR(bp, 0x2814, 0xffffffff);
6728 REG_WR(bp, 0x3820, 0xffffffff);
6729
6730 if (!CHIP_IS_E1x(bp)) {
6731 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6732 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6733 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6734 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6735 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6736 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6737 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6738 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6739 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6740 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6741 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6742 }
6743
6744 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6745 if (!CHIP_IS_E1(bp)) {
6746 /* in E3 this done in per-port section */
6747 if (!CHIP_IS_E3(bp))
6748 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6749 }
6750 if (CHIP_IS_E1H(bp))
6751 /* not applicable for E2 (and above ...) */
6752 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6753
6754 if (CHIP_REV_IS_SLOW(bp))
6755 msleep(200);
6756
6757 /* finish CFC init */
6758 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6759 if (val != 1) {
6760 BNX2X_ERR("CFC LL_INIT failed\n");
6761 return -EBUSY;
6762 }
6763 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6764 if (val != 1) {
6765 BNX2X_ERR("CFC AC_INIT failed\n");
6766 return -EBUSY;
6767 }
6768 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6769 if (val != 1) {
6770 BNX2X_ERR("CFC CAM_INIT failed\n");
6771 return -EBUSY;
6772 }
6773 REG_WR(bp, CFC_REG_DEBUG0, 0);
6774
6775 if (CHIP_IS_E1(bp)) {
6776 /* read NIG statistic
6777 to see if this is our first up since powerup */
6778 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6779 val = *bnx2x_sp(bp, wb_data[0]);
6780
6781 /* do internal memory self test */
6782 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6783 BNX2X_ERR("internal mem self test failed\n");
6784 return -EBUSY;
6785 }
6786 }
6787
6788 bnx2x_setup_fan_failure_detection(bp);
6789
6790 /* clear PXP2 attentions */
6791 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6792
6793 bnx2x_enable_blocks_attention(bp);
6794 bnx2x_enable_blocks_parity(bp);
6795
6796 if (!BP_NOMCP(bp)) {
6797 if (CHIP_IS_E1x(bp))
6798 bnx2x__common_init_phy(bp);
6799 } else
6800 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6801
6802 return 0;
6803 }
6804
6805 /**
6806 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6807 *
6808 * @bp: driver handle
6809 */
6810 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6811 {
6812 int rc = bnx2x_init_hw_common(bp);
6813
6814 if (rc)
6815 return rc;
6816
6817 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6818 if (!BP_NOMCP(bp))
6819 bnx2x__common_init_phy(bp);
6820
6821 return 0;
6822 }
6823
6824 static int bnx2x_init_hw_port(struct bnx2x *bp)
6825 {
6826 int port = BP_PORT(bp);
6827 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6828 u32 low, high;
6829 u32 val;
6830
6831
6832 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
6833
6834 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6835
6836 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6837 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6838 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6839
6840 /* Timers bug workaround: disables the pf_master bit in pglue at
6841 * common phase, we need to enable it here before any dmae access are
6842 * attempted. Therefore we manually added the enable-master to the
6843 * port phase (it also happens in the function phase)
6844 */
6845 if (!CHIP_IS_E1x(bp))
6846 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6847
6848 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6849 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6850 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6851 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6852
6853 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6854 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6855 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6856 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6857
6858 /* QM cid (connection) count */
6859 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6860
6861 if (CNIC_SUPPORT(bp)) {
6862 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6863 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6864 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6865 }
6866
6867 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6868
6869 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6870
6871 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6872
6873 if (IS_MF(bp))
6874 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6875 else if (bp->dev->mtu > 4096) {
6876 if (bp->flags & ONE_PORT_FLAG)
6877 low = 160;
6878 else {
6879 val = bp->dev->mtu;
6880 /* (24*1024 + val*4)/256 */
6881 low = 96 + (val/64) +
6882 ((val % 64) ? 1 : 0);
6883 }
6884 } else
6885 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6886 high = low + 56; /* 14*1024/256 */
6887 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6888 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6889 }
6890
6891 if (CHIP_MODE_IS_4_PORT(bp))
6892 REG_WR(bp, (BP_PORT(bp) ?
6893 BRB1_REG_MAC_GUARANTIED_1 :
6894 BRB1_REG_MAC_GUARANTIED_0), 40);
6895
6896
6897 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6898 if (CHIP_IS_E3B0(bp)) {
6899 if (IS_MF_AFEX(bp)) {
6900 /* configure headers for AFEX mode */
6901 REG_WR(bp, BP_PORT(bp) ?
6902 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6903 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
6904 REG_WR(bp, BP_PORT(bp) ?
6905 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
6906 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
6907 REG_WR(bp, BP_PORT(bp) ?
6908 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
6909 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
6910 } else {
6911 /* Ovlan exists only if we are in multi-function +
6912 * switch-dependent mode, in switch-independent there
6913 * is no ovlan headers
6914 */
6915 REG_WR(bp, BP_PORT(bp) ?
6916 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6917 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6918 (bp->path_has_ovlan ? 7 : 6));
6919 }
6920 }
6921
6922 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6923 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6924 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6925 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6926
6927 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6928 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6929 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6930 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6931
6932 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6933 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6934
6935 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6936
6937 if (CHIP_IS_E1x(bp)) {
6938 /* configure PBF to work without PAUSE mtu 9000 */
6939 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6940
6941 /* update threshold */
6942 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6943 /* update init credit */
6944 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6945
6946 /* probe changes */
6947 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6948 udelay(50);
6949 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6950 }
6951
6952 if (CNIC_SUPPORT(bp))
6953 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6954
6955 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6956 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6957
6958 if (CHIP_IS_E1(bp)) {
6959 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6960 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6961 }
6962 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6963
6964 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6965
6966 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6967 /* init aeu_mask_attn_func_0/1:
6968 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6969 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6970 * bits 4-7 are used for "per vn group attention" */
6971 val = IS_MF(bp) ? 0xF7 : 0x7;
6972 /* Enable DCBX attention for all but E1 */
6973 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6974 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6975
6976 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6977
6978 if (!CHIP_IS_E1x(bp)) {
6979 /* Bit-map indicating which L2 hdrs may appear after the
6980 * basic Ethernet header
6981 */
6982 if (IS_MF_AFEX(bp))
6983 REG_WR(bp, BP_PORT(bp) ?
6984 NIG_REG_P1_HDRS_AFTER_BASIC :
6985 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
6986 else
6987 REG_WR(bp, BP_PORT(bp) ?
6988 NIG_REG_P1_HDRS_AFTER_BASIC :
6989 NIG_REG_P0_HDRS_AFTER_BASIC,
6990 IS_MF_SD(bp) ? 7 : 6);
6991
6992 if (CHIP_IS_E3(bp))
6993 REG_WR(bp, BP_PORT(bp) ?
6994 NIG_REG_LLH1_MF_MODE :
6995 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6996 }
6997 if (!CHIP_IS_E3(bp))
6998 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6999
7000 if (!CHIP_IS_E1(bp)) {
7001 /* 0x2 disable mf_ov, 0x1 enable */
7002 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7003 (IS_MF_SD(bp) ? 0x1 : 0x2));
7004
7005 if (!CHIP_IS_E1x(bp)) {
7006 val = 0;
7007 switch (bp->mf_mode) {
7008 case MULTI_FUNCTION_SD:
7009 val = 1;
7010 break;
7011 case MULTI_FUNCTION_SI:
7012 case MULTI_FUNCTION_AFEX:
7013 val = 2;
7014 break;
7015 }
7016
7017 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7018 NIG_REG_LLH0_CLS_TYPE), val);
7019 }
7020 {
7021 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7022 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7023 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7024 }
7025 }
7026
7027
7028 /* If SPIO5 is set to generate interrupts, enable it for this port */
7029 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7030 if (val & MISC_SPIO_SPIO5) {
7031 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7032 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7033 val = REG_RD(bp, reg_addr);
7034 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7035 REG_WR(bp, reg_addr, val);
7036 }
7037
7038 return 0;
7039 }
7040
7041 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7042 {
7043 int reg;
7044 u32 wb_write[2];
7045
7046 if (CHIP_IS_E1(bp))
7047 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7048 else
7049 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7050
7051 wb_write[0] = ONCHIP_ADDR1(addr);
7052 wb_write[1] = ONCHIP_ADDR2(addr);
7053 REG_WR_DMAE(bp, reg, wb_write, 2);
7054 }
7055
7056 static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,
7057 u8 idu_sb_id, bool is_Pf)
7058 {
7059 u32 data, ctl, cnt = 100;
7060 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7061 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7062 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7063 u32 sb_bit = 1 << (idu_sb_id%32);
7064 u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7065 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7066
7067 /* Not supported in BC mode */
7068 if (CHIP_INT_MODE_IS_BC(bp))
7069 return;
7070
7071 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7072 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7073 IGU_REGULAR_CLEANUP_SET |
7074 IGU_REGULAR_BCLEANUP;
7075
7076 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7077 func_encode << IGU_CTRL_REG_FID_SHIFT |
7078 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7079
7080 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7081 data, igu_addr_data);
7082 REG_WR(bp, igu_addr_data, data);
7083 mmiowb();
7084 barrier();
7085 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7086 ctl, igu_addr_ctl);
7087 REG_WR(bp, igu_addr_ctl, ctl);
7088 mmiowb();
7089 barrier();
7090
7091 /* wait for clean up to finish */
7092 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7093 msleep(20);
7094
7095
7096 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7097 DP(NETIF_MSG_HW,
7098 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7099 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7100 }
7101 }
7102
7103 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7104 {
7105 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7106 }
7107
7108 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7109 {
7110 u32 i, base = FUNC_ILT_BASE(func);
7111 for (i = base; i < base + ILT_PER_FUNC; i++)
7112 bnx2x_ilt_wr(bp, i, 0);
7113 }
7114
7115
7116 static void bnx2x_init_searcher(struct bnx2x *bp)
7117 {
7118 int port = BP_PORT(bp);
7119 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7120 /* T1 hash bits value determines the T1 number of entries */
7121 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7122 }
7123
7124 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7125 {
7126 int rc;
7127 struct bnx2x_func_state_params func_params = {NULL};
7128 struct bnx2x_func_switch_update_params *switch_update_params =
7129 &func_params.params.switch_update;
7130
7131 /* Prepare parameters for function state transitions */
7132 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7133 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7134
7135 func_params.f_obj = &bp->func_obj;
7136 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7137
7138 /* Function parameters */
7139 switch_update_params->suspend = suspend;
7140
7141 rc = bnx2x_func_state_change(bp, &func_params);
7142
7143 return rc;
7144 }
7145
7146 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7147 {
7148 int rc, i, port = BP_PORT(bp);
7149 int vlan_en = 0, mac_en[NUM_MACS];
7150
7151
7152 /* Close input from network */
7153 if (bp->mf_mode == SINGLE_FUNCTION) {
7154 bnx2x_set_rx_filter(&bp->link_params, 0);
7155 } else {
7156 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7157 NIG_REG_LLH0_FUNC_EN);
7158 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7159 NIG_REG_LLH0_FUNC_EN, 0);
7160 for (i = 0; i < NUM_MACS; i++) {
7161 mac_en[i] = REG_RD(bp, port ?
7162 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7163 4 * i) :
7164 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7165 4 * i));
7166 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7167 4 * i) :
7168 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7169 }
7170 }
7171
7172 /* Close BMC to host */
7173 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7174 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7175
7176 /* Suspend Tx switching to the PF. Completion of this ramrod
7177 * further guarantees that all the packets of that PF / child
7178 * VFs in BRB were processed by the Parser, so it is safe to
7179 * change the NIC_MODE register.
7180 */
7181 rc = bnx2x_func_switch_update(bp, 1);
7182 if (rc) {
7183 BNX2X_ERR("Can't suspend tx-switching!\n");
7184 return rc;
7185 }
7186
7187 /* Change NIC_MODE register */
7188 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7189
7190 /* Open input from network */
7191 if (bp->mf_mode == SINGLE_FUNCTION) {
7192 bnx2x_set_rx_filter(&bp->link_params, 1);
7193 } else {
7194 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7195 NIG_REG_LLH0_FUNC_EN, vlan_en);
7196 for (i = 0; i < NUM_MACS; i++) {
7197 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7198 4 * i) :
7199 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7200 mac_en[i]);
7201 }
7202 }
7203
7204 /* Enable BMC to host */
7205 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7206 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7207
7208 /* Resume Tx switching to the PF */
7209 rc = bnx2x_func_switch_update(bp, 0);
7210 if (rc) {
7211 BNX2X_ERR("Can't resume tx-switching!\n");
7212 return rc;
7213 }
7214
7215 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7216 return 0;
7217 }
7218
7219 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7220 {
7221 int rc;
7222
7223 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7224
7225 if (CONFIGURE_NIC_MODE(bp)) {
7226 /* Configrue searcher as part of function hw init */
7227 bnx2x_init_searcher(bp);
7228
7229 /* Reset NIC mode */
7230 rc = bnx2x_reset_nic_mode(bp);
7231 if (rc)
7232 BNX2X_ERR("Can't change NIC mode!\n");
7233 return rc;
7234 }
7235
7236 return 0;
7237 }
7238
7239 static int bnx2x_init_hw_func(struct bnx2x *bp)
7240 {
7241 int port = BP_PORT(bp);
7242 int func = BP_FUNC(bp);
7243 int init_phase = PHASE_PF0 + func;
7244 struct bnx2x_ilt *ilt = BP_ILT(bp);
7245 u16 cdu_ilt_start;
7246 u32 addr, val;
7247 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7248 int i, main_mem_width, rc;
7249
7250 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7251
7252 /* FLR cleanup - hmmm */
7253 if (!CHIP_IS_E1x(bp)) {
7254 rc = bnx2x_pf_flr_clnup(bp);
7255 if (rc)
7256 return rc;
7257 }
7258
7259 /* set MSI reconfigure capability */
7260 if (bp->common.int_block == INT_BLOCK_HC) {
7261 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7262 val = REG_RD(bp, addr);
7263 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7264 REG_WR(bp, addr, val);
7265 }
7266
7267 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7268 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7269
7270 ilt = BP_ILT(bp);
7271 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7272
7273 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7274 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7275 ilt->lines[cdu_ilt_start + i].page_mapping =
7276 bp->context[i].cxt_mapping;
7277 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7278 }
7279 bnx2x_ilt_init_op(bp, INITOP_SET);
7280
7281 if (!CONFIGURE_NIC_MODE(bp)) {
7282 bnx2x_init_searcher(bp);
7283 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7284 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7285 } else {
7286 /* Set NIC mode */
7287 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7288 DP(NETIF_MSG_IFUP, "NIC MODE configrued\n");
7289
7290 }
7291
7292 if (!CHIP_IS_E1x(bp)) {
7293 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7294
7295 /* Turn on a single ISR mode in IGU if driver is going to use
7296 * INT#x or MSI
7297 */
7298 if (!(bp->flags & USING_MSIX_FLAG))
7299 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7300 /*
7301 * Timers workaround bug: function init part.
7302 * Need to wait 20msec after initializing ILT,
7303 * needed to make sure there are no requests in
7304 * one of the PXP internal queues with "old" ILT addresses
7305 */
7306 msleep(20);
7307 /*
7308 * Master enable - Due to WB DMAE writes performed before this
7309 * register is re-initialized as part of the regular function
7310 * init
7311 */
7312 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7313 /* Enable the function in IGU */
7314 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7315 }
7316
7317 bp->dmae_ready = 1;
7318
7319 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7320
7321 if (!CHIP_IS_E1x(bp))
7322 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7323
7324 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7325 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7326 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7327 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7328 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7329 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7330 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7331 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7332 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7333 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7334 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7335 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7336 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7337
7338 if (!CHIP_IS_E1x(bp))
7339 REG_WR(bp, QM_REG_PF_EN, 1);
7340
7341 if (!CHIP_IS_E1x(bp)) {
7342 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7343 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7344 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7345 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7346 }
7347 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7348
7349 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7350 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7351 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7352 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7353 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7354 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7355 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7356 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7357 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7358 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7359 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7360 if (!CHIP_IS_E1x(bp))
7361 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7362
7363 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7364
7365 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7366
7367 if (!CHIP_IS_E1x(bp))
7368 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7369
7370 if (IS_MF(bp)) {
7371 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7372 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7373 }
7374
7375 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7376
7377 /* HC init per function */
7378 if (bp->common.int_block == INT_BLOCK_HC) {
7379 if (CHIP_IS_E1H(bp)) {
7380 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7381
7382 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7383 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7384 }
7385 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7386
7387 } else {
7388 int num_segs, sb_idx, prod_offset;
7389
7390 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7391
7392 if (!CHIP_IS_E1x(bp)) {
7393 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7394 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7395 }
7396
7397 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7398
7399 if (!CHIP_IS_E1x(bp)) {
7400 int dsb_idx = 0;
7401 /**
7402 * Producer memory:
7403 * E2 mode: address 0-135 match to the mapping memory;
7404 * 136 - PF0 default prod; 137 - PF1 default prod;
7405 * 138 - PF2 default prod; 139 - PF3 default prod;
7406 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7407 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7408 * 144-147 reserved.
7409 *
7410 * E1.5 mode - In backward compatible mode;
7411 * for non default SB; each even line in the memory
7412 * holds the U producer and each odd line hold
7413 * the C producer. The first 128 producers are for
7414 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7415 * producers are for the DSB for each PF.
7416 * Each PF has five segments: (the order inside each
7417 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7418 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7419 * 144-147 attn prods;
7420 */
7421 /* non-default-status-blocks */
7422 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7423 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7424 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7425 prod_offset = (bp->igu_base_sb + sb_idx) *
7426 num_segs;
7427
7428 for (i = 0; i < num_segs; i++) {
7429 addr = IGU_REG_PROD_CONS_MEMORY +
7430 (prod_offset + i) * 4;
7431 REG_WR(bp, addr, 0);
7432 }
7433 /* send consumer update with value 0 */
7434 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7435 USTORM_ID, 0, IGU_INT_NOP, 1);
7436 bnx2x_igu_clear_sb(bp,
7437 bp->igu_base_sb + sb_idx);
7438 }
7439
7440 /* default-status-blocks */
7441 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7442 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7443
7444 if (CHIP_MODE_IS_4_PORT(bp))
7445 dsb_idx = BP_FUNC(bp);
7446 else
7447 dsb_idx = BP_VN(bp);
7448
7449 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7450 IGU_BC_BASE_DSB_PROD + dsb_idx :
7451 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7452
7453 /*
7454 * igu prods come in chunks of E1HVN_MAX (4) -
7455 * does not matters what is the current chip mode
7456 */
7457 for (i = 0; i < (num_segs * E1HVN_MAX);
7458 i += E1HVN_MAX) {
7459 addr = IGU_REG_PROD_CONS_MEMORY +
7460 (prod_offset + i)*4;
7461 REG_WR(bp, addr, 0);
7462 }
7463 /* send consumer update with 0 */
7464 if (CHIP_INT_MODE_IS_BC(bp)) {
7465 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7466 USTORM_ID, 0, IGU_INT_NOP, 1);
7467 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7468 CSTORM_ID, 0, IGU_INT_NOP, 1);
7469 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7470 XSTORM_ID, 0, IGU_INT_NOP, 1);
7471 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7472 TSTORM_ID, 0, IGU_INT_NOP, 1);
7473 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7474 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7475 } else {
7476 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7477 USTORM_ID, 0, IGU_INT_NOP, 1);
7478 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7479 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7480 }
7481 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7482
7483 /* !!! these should become driver const once
7484 rf-tool supports split-68 const */
7485 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7486 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7487 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7488 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7489 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7490 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7491 }
7492 }
7493
7494 /* Reset PCIE errors for debug */
7495 REG_WR(bp, 0x2114, 0xffffffff);
7496 REG_WR(bp, 0x2120, 0xffffffff);
7497
7498 if (CHIP_IS_E1x(bp)) {
7499 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7500 main_mem_base = HC_REG_MAIN_MEMORY +
7501 BP_PORT(bp) * (main_mem_size * 4);
7502 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7503 main_mem_width = 8;
7504
7505 val = REG_RD(bp, main_mem_prty_clr);
7506 if (val)
7507 DP(NETIF_MSG_HW,
7508 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7509 val);
7510
7511 /* Clear "false" parity errors in MSI-X table */
7512 for (i = main_mem_base;
7513 i < main_mem_base + main_mem_size * 4;
7514 i += main_mem_width) {
7515 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7516 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7517 i, main_mem_width / 4);
7518 }
7519 /* Clear HC parity attention */
7520 REG_RD(bp, main_mem_prty_clr);
7521 }
7522
7523 #ifdef BNX2X_STOP_ON_ERROR
7524 /* Enable STORMs SP logging */
7525 REG_WR8(bp, BAR_USTRORM_INTMEM +
7526 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7527 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7528 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7529 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7530 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7531 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7532 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7533 #endif
7534
7535 bnx2x_phy_probe(&bp->link_params);
7536
7537 return 0;
7538 }
7539
7540
7541 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7542 {
7543 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7544
7545 if (!CHIP_IS_E1x(bp))
7546 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7547 sizeof(struct host_hc_status_block_e2));
7548 else
7549 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7550 sizeof(struct host_hc_status_block_e1x));
7551
7552 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7553 }
7554
7555 void bnx2x_free_mem(struct bnx2x *bp)
7556 {
7557 int i;
7558
7559 /* fastpath */
7560 bnx2x_free_fp_mem(bp);
7561 /* end of fastpath */
7562
7563 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7564 sizeof(struct host_sp_status_block));
7565
7566 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7567 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7568
7569 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7570 sizeof(struct bnx2x_slowpath));
7571
7572 for (i = 0; i < L2_ILT_LINES(bp); i++)
7573 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7574 bp->context[i].size);
7575 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7576
7577 BNX2X_FREE(bp->ilt->lines);
7578
7579 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7580
7581 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7582 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7583 }
7584
7585 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
7586 {
7587 int num_groups;
7588 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
7589
7590 /* number of queues for statistics is number of eth queues + FCoE */
7591 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
7592
7593 /* Total number of FW statistics requests =
7594 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7595 * num of queues
7596 */
7597 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
7598
7599
7600 /* Request is built from stats_query_header and an array of
7601 * stats_query_cmd_group each of which contains
7602 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7603 * configured in the stats_query_header.
7604 */
7605 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
7606 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
7607
7608 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
7609 num_groups * sizeof(struct stats_query_cmd_group);
7610
7611 /* Data for statistics requests + stats_conter
7612 *
7613 * stats_counter holds per-STORM counters that are incremented
7614 * when STORM has finished with the current request.
7615 *
7616 * memory for FCoE offloaded statistics are counted anyway,
7617 * even if they will not be sent.
7618 */
7619 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
7620 sizeof(struct per_pf_stats) +
7621 sizeof(struct fcoe_statistics_params) +
7622 sizeof(struct per_queue_stats) * num_queue_stats +
7623 sizeof(struct stats_counter);
7624
7625 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
7626 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7627
7628 /* Set shortcuts */
7629 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
7630 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
7631
7632 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
7633 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
7634
7635 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
7636 bp->fw_stats_req_sz;
7637 return 0;
7638
7639 alloc_mem_err:
7640 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7641 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7642 BNX2X_ERR("Can't allocate memory\n");
7643 return -ENOMEM;
7644 }
7645
7646 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7647 {
7648 if (!CHIP_IS_E1x(bp))
7649 /* size = the status block + ramrod buffers */
7650 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7651 sizeof(struct host_hc_status_block_e2));
7652 else
7653 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7654 &bp->cnic_sb_mapping,
7655 sizeof(struct
7656 host_hc_status_block_e1x));
7657
7658 if (CONFIGURE_NIC_MODE(bp))
7659 /* allocate searcher T2 table, as it wan't allocated before */
7660 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7661
7662 /* write address to which L5 should insert its values */
7663 bp->cnic_eth_dev.addr_drv_info_to_mcp =
7664 &bp->slowpath->drv_info_to_mcp;
7665
7666 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7667 goto alloc_mem_err;
7668
7669 return 0;
7670
7671 alloc_mem_err:
7672 bnx2x_free_mem_cnic(bp);
7673 BNX2X_ERR("Can't allocate memory\n");
7674 return -ENOMEM;
7675 }
7676
7677 int bnx2x_alloc_mem(struct bnx2x *bp)
7678 {
7679 int i, allocated, context_size;
7680
7681 if (!CONFIGURE_NIC_MODE(bp))
7682 /* allocate searcher T2 table */
7683 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7684
7685 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7686 sizeof(struct host_sp_status_block));
7687
7688 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7689 sizeof(struct bnx2x_slowpath));
7690
7691 /* Allocated memory for FW statistics */
7692 if (bnx2x_alloc_fw_stats_mem(bp))
7693 goto alloc_mem_err;
7694
7695 /* Allocate memory for CDU context:
7696 * This memory is allocated separately and not in the generic ILT
7697 * functions because CDU differs in few aspects:
7698 * 1. There are multiple entities allocating memory for context -
7699 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7700 * its own ILT lines.
7701 * 2. Since CDU page-size is not a single 4KB page (which is the case
7702 * for the other ILT clients), to be efficient we want to support
7703 * allocation of sub-page-size in the last entry.
7704 * 3. Context pointers are used by the driver to pass to FW / update
7705 * the context (for the other ILT clients the pointers are used just to
7706 * free the memory during unload).
7707 */
7708 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7709
7710 for (i = 0, allocated = 0; allocated < context_size; i++) {
7711 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7712 (context_size - allocated));
7713 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7714 &bp->context[i].cxt_mapping,
7715 bp->context[i].size);
7716 allocated += bp->context[i].size;
7717 }
7718 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7719
7720 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7721 goto alloc_mem_err;
7722
7723 /* Slow path ring */
7724 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7725
7726 /* EQ */
7727 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7728 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7729
7730
7731 /* fastpath */
7732 /* need to be done at the end, since it's self adjusting to amount
7733 * of memory available for RSS queues
7734 */
7735 if (bnx2x_alloc_fp_mem(bp))
7736 goto alloc_mem_err;
7737 return 0;
7738
7739 alloc_mem_err:
7740 bnx2x_free_mem(bp);
7741 BNX2X_ERR("Can't allocate memory\n");
7742 return -ENOMEM;
7743 }
7744
7745 /*
7746 * Init service functions
7747 */
7748
7749 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7750 struct bnx2x_vlan_mac_obj *obj, bool set,
7751 int mac_type, unsigned long *ramrod_flags)
7752 {
7753 int rc;
7754 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7755
7756 memset(&ramrod_param, 0, sizeof(ramrod_param));
7757
7758 /* Fill general parameters */
7759 ramrod_param.vlan_mac_obj = obj;
7760 ramrod_param.ramrod_flags = *ramrod_flags;
7761
7762 /* Fill a user request section if needed */
7763 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7764 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7765
7766 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7767
7768 /* Set the command: ADD or DEL */
7769 if (set)
7770 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7771 else
7772 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7773 }
7774
7775 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7776
7777 if (rc == -EEXIST) {
7778 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7779 /* do not treat adding same MAC as error */
7780 rc = 0;
7781 } else if (rc < 0)
7782 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7783
7784 return rc;
7785 }
7786
7787 int bnx2x_del_all_macs(struct bnx2x *bp,
7788 struct bnx2x_vlan_mac_obj *mac_obj,
7789 int mac_type, bool wait_for_comp)
7790 {
7791 int rc;
7792 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7793
7794 /* Wait for completion of requested */
7795 if (wait_for_comp)
7796 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7797
7798 /* Set the mac type of addresses we want to clear */
7799 __set_bit(mac_type, &vlan_mac_flags);
7800
7801 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7802 if (rc < 0)
7803 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7804
7805 return rc;
7806 }
7807
7808 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7809 {
7810 unsigned long ramrod_flags = 0;
7811
7812 if (is_zero_ether_addr(bp->dev->dev_addr) &&
7813 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7814 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7815 "Ignoring Zero MAC for STORAGE SD mode\n");
7816 return 0;
7817 }
7818
7819 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7820
7821 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7822 /* Eth MAC is set on RSS leading client (fp[0]) */
7823 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7824 set, BNX2X_ETH_MAC, &ramrod_flags);
7825 }
7826
7827 int bnx2x_setup_leading(struct bnx2x *bp)
7828 {
7829 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7830 }
7831
7832 /**
7833 * bnx2x_set_int_mode - configure interrupt mode
7834 *
7835 * @bp: driver handle
7836 *
7837 * In case of MSI-X it will also try to enable MSI-X.
7838 */
7839 int bnx2x_set_int_mode(struct bnx2x *bp)
7840 {
7841 int rc = 0;
7842
7843 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX)
7844 return -EINVAL;
7845
7846 switch (int_mode) {
7847 case BNX2X_INT_MODE_MSIX:
7848 /* attempt to enable msix */
7849 rc = bnx2x_enable_msix(bp);
7850
7851 /* msix attained */
7852 if (!rc)
7853 return 0;
7854
7855 /* vfs use only msix */
7856 if (rc && IS_VF(bp))
7857 return rc;
7858
7859 /* failed to enable multiple MSI-X */
7860 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7861 bp->num_queues,
7862 1 + bp->num_cnic_queues);
7863
7864 /* falling through... */
7865 case BNX2X_INT_MODE_MSI:
7866 bnx2x_enable_msi(bp);
7867
7868 /* falling through... */
7869 case BNX2X_INT_MODE_INTX:
7870 bp->num_ethernet_queues = 1;
7871 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
7872 BNX2X_DEV_INFO("set number of queues to 1\n");
7873 break;
7874 default:
7875 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
7876 return -EINVAL;
7877 }
7878 return 0;
7879 }
7880
7881 /* must be called prior to any HW initializations */
7882 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7883 {
7884 return L2_ILT_LINES(bp);
7885 }
7886
7887 void bnx2x_ilt_set_info(struct bnx2x *bp)
7888 {
7889 struct ilt_client_info *ilt_client;
7890 struct bnx2x_ilt *ilt = BP_ILT(bp);
7891 u16 line = 0;
7892
7893 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7894 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7895
7896 /* CDU */
7897 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7898 ilt_client->client_num = ILT_CLIENT_CDU;
7899 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7900 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7901 ilt_client->start = line;
7902 line += bnx2x_cid_ilt_lines(bp);
7903
7904 if (CNIC_SUPPORT(bp))
7905 line += CNIC_ILT_LINES;
7906 ilt_client->end = line - 1;
7907
7908 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7909 ilt_client->start,
7910 ilt_client->end,
7911 ilt_client->page_size,
7912 ilt_client->flags,
7913 ilog2(ilt_client->page_size >> 12));
7914
7915 /* QM */
7916 if (QM_INIT(bp->qm_cid_count)) {
7917 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7918 ilt_client->client_num = ILT_CLIENT_QM;
7919 ilt_client->page_size = QM_ILT_PAGE_SZ;
7920 ilt_client->flags = 0;
7921 ilt_client->start = line;
7922
7923 /* 4 bytes for each cid */
7924 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7925 QM_ILT_PAGE_SZ);
7926
7927 ilt_client->end = line - 1;
7928
7929 DP(NETIF_MSG_IFUP,
7930 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7931 ilt_client->start,
7932 ilt_client->end,
7933 ilt_client->page_size,
7934 ilt_client->flags,
7935 ilog2(ilt_client->page_size >> 12));
7936
7937 }
7938
7939 if (CNIC_SUPPORT(bp)) {
7940 /* SRC */
7941 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7942 ilt_client->client_num = ILT_CLIENT_SRC;
7943 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7944 ilt_client->flags = 0;
7945 ilt_client->start = line;
7946 line += SRC_ILT_LINES;
7947 ilt_client->end = line - 1;
7948
7949 DP(NETIF_MSG_IFUP,
7950 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7951 ilt_client->start,
7952 ilt_client->end,
7953 ilt_client->page_size,
7954 ilt_client->flags,
7955 ilog2(ilt_client->page_size >> 12));
7956
7957 /* TM */
7958 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7959 ilt_client->client_num = ILT_CLIENT_TM;
7960 ilt_client->page_size = TM_ILT_PAGE_SZ;
7961 ilt_client->flags = 0;
7962 ilt_client->start = line;
7963 line += TM_ILT_LINES;
7964 ilt_client->end = line - 1;
7965
7966 DP(NETIF_MSG_IFUP,
7967 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7968 ilt_client->start,
7969 ilt_client->end,
7970 ilt_client->page_size,
7971 ilt_client->flags,
7972 ilog2(ilt_client->page_size >> 12));
7973 }
7974
7975 BUG_ON(line > ILT_MAX_LINES);
7976 }
7977
7978 /**
7979 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7980 *
7981 * @bp: driver handle
7982 * @fp: pointer to fastpath
7983 * @init_params: pointer to parameters structure
7984 *
7985 * parameters configured:
7986 * - HC configuration
7987 * - Queue's CDU context
7988 */
7989 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7990 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7991 {
7992
7993 u8 cos;
7994 int cxt_index, cxt_offset;
7995
7996 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7997 if (!IS_FCOE_FP(fp)) {
7998 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7999 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8000
8001 /* If HC is supporterd, enable host coalescing in the transition
8002 * to INIT state.
8003 */
8004 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8005 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8006
8007 /* HC rate */
8008 init_params->rx.hc_rate = bp->rx_ticks ?
8009 (1000000 / bp->rx_ticks) : 0;
8010 init_params->tx.hc_rate = bp->tx_ticks ?
8011 (1000000 / bp->tx_ticks) : 0;
8012
8013 /* FW SB ID */
8014 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8015 fp->fw_sb_id;
8016
8017 /*
8018 * CQ index among the SB indices: FCoE clients uses the default
8019 * SB, therefore it's different.
8020 */
8021 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8022 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8023 }
8024
8025 /* set maximum number of COSs supported by this queue */
8026 init_params->max_cos = fp->max_cos;
8027
8028 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8029 fp->index, init_params->max_cos);
8030
8031 /* set the context pointers queue object */
8032 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8033 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8034 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8035 ILT_PAGE_CIDS);
8036 init_params->cxts[cos] =
8037 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8038 }
8039 }
8040
8041 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8042 struct bnx2x_queue_state_params *q_params,
8043 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8044 int tx_index, bool leading)
8045 {
8046 memset(tx_only_params, 0, sizeof(*tx_only_params));
8047
8048 /* Set the command */
8049 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8050
8051 /* Set tx-only QUEUE flags: don't zero statistics */
8052 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8053
8054 /* choose the index of the cid to send the slow path on */
8055 tx_only_params->cid_index = tx_index;
8056
8057 /* Set general TX_ONLY_SETUP parameters */
8058 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8059
8060 /* Set Tx TX_ONLY_SETUP parameters */
8061 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8062
8063 DP(NETIF_MSG_IFUP,
8064 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8065 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8066 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8067 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8068
8069 /* send the ramrod */
8070 return bnx2x_queue_state_change(bp, q_params);
8071 }
8072
8073
8074 /**
8075 * bnx2x_setup_queue - setup queue
8076 *
8077 * @bp: driver handle
8078 * @fp: pointer to fastpath
8079 * @leading: is leading
8080 *
8081 * This function performs 2 steps in a Queue state machine
8082 * actually: 1) RESET->INIT 2) INIT->SETUP
8083 */
8084
8085 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8086 bool leading)
8087 {
8088 struct bnx2x_queue_state_params q_params = {NULL};
8089 struct bnx2x_queue_setup_params *setup_params =
8090 &q_params.params.setup;
8091 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8092 &q_params.params.tx_only;
8093 int rc;
8094 u8 tx_index;
8095
8096 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8097
8098 /* reset IGU state skip FCoE L2 queue */
8099 if (!IS_FCOE_FP(fp))
8100 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8101 IGU_INT_ENABLE, 0);
8102
8103 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8104 /* We want to wait for completion in this context */
8105 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8106
8107 /* Prepare the INIT parameters */
8108 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8109
8110 /* Set the command */
8111 q_params.cmd = BNX2X_Q_CMD_INIT;
8112
8113 /* Change the state to INIT */
8114 rc = bnx2x_queue_state_change(bp, &q_params);
8115 if (rc) {
8116 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8117 return rc;
8118 }
8119
8120 DP(NETIF_MSG_IFUP, "init complete\n");
8121
8122
8123 /* Now move the Queue to the SETUP state... */
8124 memset(setup_params, 0, sizeof(*setup_params));
8125
8126 /* Set QUEUE flags */
8127 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8128
8129 /* Set general SETUP parameters */
8130 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8131 FIRST_TX_COS_INDEX);
8132
8133 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8134 &setup_params->rxq_params);
8135
8136 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8137 FIRST_TX_COS_INDEX);
8138
8139 /* Set the command */
8140 q_params.cmd = BNX2X_Q_CMD_SETUP;
8141
8142 if (IS_FCOE_FP(fp))
8143 bp->fcoe_init = true;
8144
8145 /* Change the state to SETUP */
8146 rc = bnx2x_queue_state_change(bp, &q_params);
8147 if (rc) {
8148 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8149 return rc;
8150 }
8151
8152 /* loop through the relevant tx-only indices */
8153 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8154 tx_index < fp->max_cos;
8155 tx_index++) {
8156
8157 /* prepare and send tx-only ramrod*/
8158 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8159 tx_only_params, tx_index, leading);
8160 if (rc) {
8161 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8162 fp->index, tx_index);
8163 return rc;
8164 }
8165 }
8166
8167 return rc;
8168 }
8169
8170 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8171 {
8172 struct bnx2x_fastpath *fp = &bp->fp[index];
8173 struct bnx2x_fp_txdata *txdata;
8174 struct bnx2x_queue_state_params q_params = {NULL};
8175 int rc, tx_index;
8176
8177 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8178
8179 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8180 /* We want to wait for completion in this context */
8181 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8182
8183
8184 /* close tx-only connections */
8185 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8186 tx_index < fp->max_cos;
8187 tx_index++){
8188
8189 /* ascertain this is a normal queue*/
8190 txdata = fp->txdata_ptr[tx_index];
8191
8192 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8193 txdata->txq_index);
8194
8195 /* send halt terminate on tx-only connection */
8196 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8197 memset(&q_params.params.terminate, 0,
8198 sizeof(q_params.params.terminate));
8199 q_params.params.terminate.cid_index = tx_index;
8200
8201 rc = bnx2x_queue_state_change(bp, &q_params);
8202 if (rc)
8203 return rc;
8204
8205 /* send halt terminate on tx-only connection */
8206 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8207 memset(&q_params.params.cfc_del, 0,
8208 sizeof(q_params.params.cfc_del));
8209 q_params.params.cfc_del.cid_index = tx_index;
8210 rc = bnx2x_queue_state_change(bp, &q_params);
8211 if (rc)
8212 return rc;
8213 }
8214 /* Stop the primary connection: */
8215 /* ...halt the connection */
8216 q_params.cmd = BNX2X_Q_CMD_HALT;
8217 rc = bnx2x_queue_state_change(bp, &q_params);
8218 if (rc)
8219 return rc;
8220
8221 /* ...terminate the connection */
8222 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8223 memset(&q_params.params.terminate, 0,
8224 sizeof(q_params.params.terminate));
8225 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8226 rc = bnx2x_queue_state_change(bp, &q_params);
8227 if (rc)
8228 return rc;
8229 /* ...delete cfc entry */
8230 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8231 memset(&q_params.params.cfc_del, 0,
8232 sizeof(q_params.params.cfc_del));
8233 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8234 return bnx2x_queue_state_change(bp, &q_params);
8235 }
8236
8237
8238 static void bnx2x_reset_func(struct bnx2x *bp)
8239 {
8240 int port = BP_PORT(bp);
8241 int func = BP_FUNC(bp);
8242 int i;
8243
8244 /* Disable the function in the FW */
8245 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8246 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8247 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8248 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8249
8250 /* FP SBs */
8251 for_each_eth_queue(bp, i) {
8252 struct bnx2x_fastpath *fp = &bp->fp[i];
8253 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8254 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8255 SB_DISABLED);
8256 }
8257
8258 if (CNIC_LOADED(bp))
8259 /* CNIC SB */
8260 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8261 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8262 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8263
8264 /* SP SB */
8265 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8266 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8267 SB_DISABLED);
8268
8269 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8270 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8271 0);
8272
8273 /* Configure IGU */
8274 if (bp->common.int_block == INT_BLOCK_HC) {
8275 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8276 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8277 } else {
8278 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8279 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8280 }
8281
8282 if (CNIC_LOADED(bp)) {
8283 /* Disable Timer scan */
8284 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8285 /*
8286 * Wait for at least 10ms and up to 2 second for the timers
8287 * scan to complete
8288 */
8289 for (i = 0; i < 200; i++) {
8290 msleep(10);
8291 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8292 break;
8293 }
8294 }
8295 /* Clear ILT */
8296 bnx2x_clear_func_ilt(bp, func);
8297
8298 /* Timers workaround bug for E2: if this is vnic-3,
8299 * we need to set the entire ilt range for this timers.
8300 */
8301 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8302 struct ilt_client_info ilt_cli;
8303 /* use dummy TM client */
8304 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8305 ilt_cli.start = 0;
8306 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8307 ilt_cli.client_num = ILT_CLIENT_TM;
8308
8309 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8310 }
8311
8312 /* this assumes that reset_port() called before reset_func()*/
8313 if (!CHIP_IS_E1x(bp))
8314 bnx2x_pf_disable(bp);
8315
8316 bp->dmae_ready = 0;
8317 }
8318
8319 static void bnx2x_reset_port(struct bnx2x *bp)
8320 {
8321 int port = BP_PORT(bp);
8322 u32 val;
8323
8324 /* Reset physical Link */
8325 bnx2x__link_reset(bp);
8326
8327 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8328
8329 /* Do not rcv packets to BRB */
8330 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8331 /* Do not direct rcv packets that are not for MCP to the BRB */
8332 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8333 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8334
8335 /* Configure AEU */
8336 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8337
8338 msleep(100);
8339 /* Check for BRB port occupancy */
8340 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8341 if (val)
8342 DP(NETIF_MSG_IFDOWN,
8343 "BRB1 is not empty %d blocks are occupied\n", val);
8344
8345 /* TODO: Close Doorbell port? */
8346 }
8347
8348 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8349 {
8350 struct bnx2x_func_state_params func_params = {NULL};
8351
8352 /* Prepare parameters for function state transitions */
8353 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8354
8355 func_params.f_obj = &bp->func_obj;
8356 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8357
8358 func_params.params.hw_init.load_phase = load_code;
8359
8360 return bnx2x_func_state_change(bp, &func_params);
8361 }
8362
8363 static int bnx2x_func_stop(struct bnx2x *bp)
8364 {
8365 struct bnx2x_func_state_params func_params = {NULL};
8366 int rc;
8367
8368 /* Prepare parameters for function state transitions */
8369 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8370 func_params.f_obj = &bp->func_obj;
8371 func_params.cmd = BNX2X_F_CMD_STOP;
8372
8373 /*
8374 * Try to stop the function the 'good way'. If fails (in case
8375 * of a parity error during bnx2x_chip_cleanup()) and we are
8376 * not in a debug mode, perform a state transaction in order to
8377 * enable further HW_RESET transaction.
8378 */
8379 rc = bnx2x_func_state_change(bp, &func_params);
8380 if (rc) {
8381 #ifdef BNX2X_STOP_ON_ERROR
8382 return rc;
8383 #else
8384 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8385 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8386 return bnx2x_func_state_change(bp, &func_params);
8387 #endif
8388 }
8389
8390 return 0;
8391 }
8392
8393 /**
8394 * bnx2x_send_unload_req - request unload mode from the MCP.
8395 *
8396 * @bp: driver handle
8397 * @unload_mode: requested function's unload mode
8398 *
8399 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8400 */
8401 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8402 {
8403 u32 reset_code = 0;
8404 int port = BP_PORT(bp);
8405
8406 /* Select the UNLOAD request mode */
8407 if (unload_mode == UNLOAD_NORMAL)
8408 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8409
8410 else if (bp->flags & NO_WOL_FLAG)
8411 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8412
8413 else if (bp->wol) {
8414 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8415 u8 *mac_addr = bp->dev->dev_addr;
8416 u32 val;
8417 u16 pmc;
8418
8419 /* The mac address is written to entries 1-4 to
8420 * preserve entry 0 which is used by the PMF
8421 */
8422 u8 entry = (BP_VN(bp) + 1)*8;
8423
8424 val = (mac_addr[0] << 8) | mac_addr[1];
8425 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8426
8427 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8428 (mac_addr[4] << 8) | mac_addr[5];
8429 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8430
8431 /* Enable the PME and clear the status */
8432 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8433 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8434 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8435
8436 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8437
8438 } else
8439 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8440
8441 /* Send the request to the MCP */
8442 if (!BP_NOMCP(bp))
8443 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8444 else {
8445 int path = BP_PATH(bp);
8446
8447 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
8448 path, load_count[path][0], load_count[path][1],
8449 load_count[path][2]);
8450 load_count[path][0]--;
8451 load_count[path][1 + port]--;
8452 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
8453 path, load_count[path][0], load_count[path][1],
8454 load_count[path][2]);
8455 if (load_count[path][0] == 0)
8456 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8457 else if (load_count[path][1 + port] == 0)
8458 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8459 else
8460 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8461 }
8462
8463 return reset_code;
8464 }
8465
8466 /**
8467 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8468 *
8469 * @bp: driver handle
8470 * @keep_link: true iff link should be kept up
8471 */
8472 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8473 {
8474 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8475
8476 /* Report UNLOAD_DONE to MCP */
8477 if (!BP_NOMCP(bp))
8478 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8479 }
8480
8481 static int bnx2x_func_wait_started(struct bnx2x *bp)
8482 {
8483 int tout = 50;
8484 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8485
8486 if (!bp->port.pmf)
8487 return 0;
8488
8489 /*
8490 * (assumption: No Attention from MCP at this stage)
8491 * PMF probably in the middle of TXdisable/enable transaction
8492 * 1. Sync IRS for default SB
8493 * 2. Sync SP queue - this guarantes us that attention handling started
8494 * 3. Wait, that TXdisable/enable transaction completes
8495 *
8496 * 1+2 guranty that if DCBx attention was scheduled it already changed
8497 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8498 * received complettion for the transaction the state is TX_STOPPED.
8499 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8500 * transaction.
8501 */
8502
8503 /* make sure default SB ISR is done */
8504 if (msix)
8505 synchronize_irq(bp->msix_table[0].vector);
8506 else
8507 synchronize_irq(bp->pdev->irq);
8508
8509 flush_workqueue(bnx2x_wq);
8510
8511 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8512 BNX2X_F_STATE_STARTED && tout--)
8513 msleep(20);
8514
8515 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8516 BNX2X_F_STATE_STARTED) {
8517 #ifdef BNX2X_STOP_ON_ERROR
8518 BNX2X_ERR("Wrong function state\n");
8519 return -EBUSY;
8520 #else
8521 /*
8522 * Failed to complete the transaction in a "good way"
8523 * Force both transactions with CLR bit
8524 */
8525 struct bnx2x_func_state_params func_params = {NULL};
8526
8527 DP(NETIF_MSG_IFDOWN,
8528 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8529
8530 func_params.f_obj = &bp->func_obj;
8531 __set_bit(RAMROD_DRV_CLR_ONLY,
8532 &func_params.ramrod_flags);
8533
8534 /* STARTED-->TX_ST0PPED */
8535 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8536 bnx2x_func_state_change(bp, &func_params);
8537
8538 /* TX_ST0PPED-->STARTED */
8539 func_params.cmd = BNX2X_F_CMD_TX_START;
8540 return bnx2x_func_state_change(bp, &func_params);
8541 #endif
8542 }
8543
8544 return 0;
8545 }
8546
8547 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8548 {
8549 int port = BP_PORT(bp);
8550 int i, rc = 0;
8551 u8 cos;
8552 struct bnx2x_mcast_ramrod_params rparam = {NULL};
8553 u32 reset_code;
8554
8555 /* Wait until tx fastpath tasks complete */
8556 for_each_tx_queue(bp, i) {
8557 struct bnx2x_fastpath *fp = &bp->fp[i];
8558
8559 for_each_cos_in_tx_queue(fp, cos)
8560 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8561 #ifdef BNX2X_STOP_ON_ERROR
8562 if (rc)
8563 return;
8564 #endif
8565 }
8566
8567 /* Give HW time to discard old tx messages */
8568 usleep_range(1000, 1000);
8569
8570 /* Clean all ETH MACs */
8571 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8572 false);
8573 if (rc < 0)
8574 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8575
8576 /* Clean up UC list */
8577 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8578 true);
8579 if (rc < 0)
8580 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8581 rc);
8582
8583 /* Disable LLH */
8584 if (!CHIP_IS_E1(bp))
8585 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8586
8587 /* Set "drop all" (stop Rx).
8588 * We need to take a netif_addr_lock() here in order to prevent
8589 * a race between the completion code and this code.
8590 */
8591 netif_addr_lock_bh(bp->dev);
8592 /* Schedule the rx_mode command */
8593 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8594 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8595 else
8596 bnx2x_set_storm_rx_mode(bp);
8597
8598 /* Cleanup multicast configuration */
8599 rparam.mcast_obj = &bp->mcast_obj;
8600 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8601 if (rc < 0)
8602 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8603
8604 netif_addr_unlock_bh(bp->dev);
8605
8606
8607
8608 /*
8609 * Send the UNLOAD_REQUEST to the MCP. This will return if
8610 * this function should perform FUNC, PORT or COMMON HW
8611 * reset.
8612 */
8613 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8614
8615 /*
8616 * (assumption: No Attention from MCP at this stage)
8617 * PMF probably in the middle of TXdisable/enable transaction
8618 */
8619 rc = bnx2x_func_wait_started(bp);
8620 if (rc) {
8621 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8622 #ifdef BNX2X_STOP_ON_ERROR
8623 return;
8624 #endif
8625 }
8626
8627 /* Close multi and leading connections
8628 * Completions for ramrods are collected in a synchronous way
8629 */
8630 for_each_eth_queue(bp, i)
8631 if (bnx2x_stop_queue(bp, i))
8632 #ifdef BNX2X_STOP_ON_ERROR
8633 return;
8634 #else
8635 goto unload_error;
8636 #endif
8637
8638 if (CNIC_LOADED(bp)) {
8639 for_each_cnic_queue(bp, i)
8640 if (bnx2x_stop_queue(bp, i))
8641 #ifdef BNX2X_STOP_ON_ERROR
8642 return;
8643 #else
8644 goto unload_error;
8645 #endif
8646 }
8647
8648 /* If SP settings didn't get completed so far - something
8649 * very wrong has happen.
8650 */
8651 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8652 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8653
8654 #ifndef BNX2X_STOP_ON_ERROR
8655 unload_error:
8656 #endif
8657 rc = bnx2x_func_stop(bp);
8658 if (rc) {
8659 BNX2X_ERR("Function stop failed!\n");
8660 #ifdef BNX2X_STOP_ON_ERROR
8661 return;
8662 #endif
8663 }
8664
8665 /* Disable HW interrupts, NAPI */
8666 bnx2x_netif_stop(bp, 1);
8667 /* Delete all NAPI objects */
8668 bnx2x_del_all_napi(bp);
8669 if (CNIC_LOADED(bp))
8670 bnx2x_del_all_napi_cnic(bp);
8671
8672 /* Release IRQs */
8673 bnx2x_free_irq(bp);
8674
8675 /* Reset the chip */
8676 rc = bnx2x_reset_hw(bp, reset_code);
8677 if (rc)
8678 BNX2X_ERR("HW_RESET failed\n");
8679
8680
8681 /* Report UNLOAD_DONE to MCP */
8682 bnx2x_send_unload_done(bp, keep_link);
8683 }
8684
8685 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8686 {
8687 u32 val;
8688
8689 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8690
8691 if (CHIP_IS_E1(bp)) {
8692 int port = BP_PORT(bp);
8693 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8694 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8695
8696 val = REG_RD(bp, addr);
8697 val &= ~(0x300);
8698 REG_WR(bp, addr, val);
8699 } else {
8700 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8701 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8702 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8703 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8704 }
8705 }
8706
8707 /* Close gates #2, #3 and #4: */
8708 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8709 {
8710 u32 val;
8711
8712 /* Gates #2 and #4a are closed/opened for "not E1" only */
8713 if (!CHIP_IS_E1(bp)) {
8714 /* #4 */
8715 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8716 /* #2 */
8717 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8718 }
8719
8720 /* #3 */
8721 if (CHIP_IS_E1x(bp)) {
8722 /* Prevent interrupts from HC on both ports */
8723 val = REG_RD(bp, HC_REG_CONFIG_1);
8724 REG_WR(bp, HC_REG_CONFIG_1,
8725 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8726 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8727
8728 val = REG_RD(bp, HC_REG_CONFIG_0);
8729 REG_WR(bp, HC_REG_CONFIG_0,
8730 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8731 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8732 } else {
8733 /* Prevent incomming interrupts in IGU */
8734 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8735
8736 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8737 (!close) ?
8738 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8739 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8740 }
8741
8742 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8743 close ? "closing" : "opening");
8744 mmiowb();
8745 }
8746
8747 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8748
8749 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8750 {
8751 /* Do some magic... */
8752 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8753 *magic_val = val & SHARED_MF_CLP_MAGIC;
8754 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8755 }
8756
8757 /**
8758 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8759 *
8760 * @bp: driver handle
8761 * @magic_val: old value of the `magic' bit.
8762 */
8763 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8764 {
8765 /* Restore the `magic' bit value... */
8766 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8767 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8768 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8769 }
8770
8771 /**
8772 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8773 *
8774 * @bp: driver handle
8775 * @magic_val: old value of 'magic' bit.
8776 *
8777 * Takes care of CLP configurations.
8778 */
8779 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8780 {
8781 u32 shmem;
8782 u32 validity_offset;
8783
8784 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8785
8786 /* Set `magic' bit in order to save MF config */
8787 if (!CHIP_IS_E1(bp))
8788 bnx2x_clp_reset_prep(bp, magic_val);
8789
8790 /* Get shmem offset */
8791 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8792 validity_offset =
8793 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
8794
8795 /* Clear validity map flags */
8796 if (shmem > 0)
8797 REG_WR(bp, shmem + validity_offset, 0);
8798 }
8799
8800 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8801 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8802
8803 /**
8804 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8805 *
8806 * @bp: driver handle
8807 */
8808 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8809 {
8810 /* special handling for emulation and FPGA,
8811 wait 10 times longer */
8812 if (CHIP_REV_IS_SLOW(bp))
8813 msleep(MCP_ONE_TIMEOUT*10);
8814 else
8815 msleep(MCP_ONE_TIMEOUT);
8816 }
8817
8818 /*
8819 * initializes bp->common.shmem_base and waits for validity signature to appear
8820 */
8821 static int bnx2x_init_shmem(struct bnx2x *bp)
8822 {
8823 int cnt = 0;
8824 u32 val = 0;
8825
8826 do {
8827 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8828 if (bp->common.shmem_base) {
8829 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8830 if (val & SHR_MEM_VALIDITY_MB)
8831 return 0;
8832 }
8833
8834 bnx2x_mcp_wait_one(bp);
8835
8836 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8837
8838 BNX2X_ERR("BAD MCP validity signature\n");
8839
8840 return -ENODEV;
8841 }
8842
8843 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8844 {
8845 int rc = bnx2x_init_shmem(bp);
8846
8847 /* Restore the `magic' bit value */
8848 if (!CHIP_IS_E1(bp))
8849 bnx2x_clp_reset_done(bp, magic_val);
8850
8851 return rc;
8852 }
8853
8854 static void bnx2x_pxp_prep(struct bnx2x *bp)
8855 {
8856 if (!CHIP_IS_E1(bp)) {
8857 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8858 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8859 mmiowb();
8860 }
8861 }
8862
8863 /*
8864 * Reset the whole chip except for:
8865 * - PCIE core
8866 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8867 * one reset bit)
8868 * - IGU
8869 * - MISC (including AEU)
8870 * - GRC
8871 * - RBCN, RBCP
8872 */
8873 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8874 {
8875 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8876 u32 global_bits2, stay_reset2;
8877
8878 /*
8879 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8880 * (per chip) blocks.
8881 */
8882 global_bits2 =
8883 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8884 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8885
8886 /* Don't reset the following blocks.
8887 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
8888 * reset, as in 4 port device they might still be owned
8889 * by the MCP (there is only one leader per path).
8890 */
8891 not_reset_mask1 =
8892 MISC_REGISTERS_RESET_REG_1_RST_HC |
8893 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8894 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8895
8896 not_reset_mask2 =
8897 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8898 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8899 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8900 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8901 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8902 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8903 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8904 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8905 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8906 MISC_REGISTERS_RESET_REG_2_PGLC |
8907 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8908 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8909 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8910 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8911 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8912 MISC_REGISTERS_RESET_REG_2_UMAC1;
8913
8914 /*
8915 * Keep the following blocks in reset:
8916 * - all xxMACs are handled by the bnx2x_link code.
8917 */
8918 stay_reset2 =
8919 MISC_REGISTERS_RESET_REG_2_XMAC |
8920 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8921
8922 /* Full reset masks according to the chip */
8923 reset_mask1 = 0xffffffff;
8924
8925 if (CHIP_IS_E1(bp))
8926 reset_mask2 = 0xffff;
8927 else if (CHIP_IS_E1H(bp))
8928 reset_mask2 = 0x1ffff;
8929 else if (CHIP_IS_E2(bp))
8930 reset_mask2 = 0xfffff;
8931 else /* CHIP_IS_E3 */
8932 reset_mask2 = 0x3ffffff;
8933
8934 /* Don't reset global blocks unless we need to */
8935 if (!global)
8936 reset_mask2 &= ~global_bits2;
8937
8938 /*
8939 * In case of attention in the QM, we need to reset PXP
8940 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8941 * because otherwise QM reset would release 'close the gates' shortly
8942 * before resetting the PXP, then the PSWRQ would send a write
8943 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8944 * read the payload data from PSWWR, but PSWWR would not
8945 * respond. The write queue in PGLUE would stuck, dmae commands
8946 * would not return. Therefore it's important to reset the second
8947 * reset register (containing the
8948 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8949 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8950 * bit).
8951 */
8952 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8953 reset_mask2 & (~not_reset_mask2));
8954
8955 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8956 reset_mask1 & (~not_reset_mask1));
8957
8958 barrier();
8959 mmiowb();
8960
8961 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8962 reset_mask2 & (~stay_reset2));
8963
8964 barrier();
8965 mmiowb();
8966
8967 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8968 mmiowb();
8969 }
8970
8971 /**
8972 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8973 * It should get cleared in no more than 1s.
8974 *
8975 * @bp: driver handle
8976 *
8977 * It should get cleared in no more than 1s. Returns 0 if
8978 * pending writes bit gets cleared.
8979 */
8980 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8981 {
8982 u32 cnt = 1000;
8983 u32 pend_bits = 0;
8984
8985 do {
8986 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8987
8988 if (pend_bits == 0)
8989 break;
8990
8991 usleep_range(1000, 1000);
8992 } while (cnt-- > 0);
8993
8994 if (cnt <= 0) {
8995 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8996 pend_bits);
8997 return -EBUSY;
8998 }
8999
9000 return 0;
9001 }
9002
9003 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9004 {
9005 int cnt = 1000;
9006 u32 val = 0;
9007 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9008 u32 tags_63_32 = 0;
9009
9010
9011 /* Empty the Tetris buffer, wait for 1s */
9012 do {
9013 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9014 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9015 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9016 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9017 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9018 if (CHIP_IS_E3(bp))
9019 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9020
9021 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9022 ((port_is_idle_0 & 0x1) == 0x1) &&
9023 ((port_is_idle_1 & 0x1) == 0x1) &&
9024 (pgl_exp_rom2 == 0xffffffff) &&
9025 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9026 break;
9027 usleep_range(1000, 1000);
9028 } while (cnt-- > 0);
9029
9030 if (cnt <= 0) {
9031 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9032 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9033 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9034 pgl_exp_rom2);
9035 return -EAGAIN;
9036 }
9037
9038 barrier();
9039
9040 /* Close gates #2, #3 and #4 */
9041 bnx2x_set_234_gates(bp, true);
9042
9043 /* Poll for IGU VQs for 57712 and newer chips */
9044 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9045 return -EAGAIN;
9046
9047
9048 /* TBD: Indicate that "process kill" is in progress to MCP */
9049
9050 /* Clear "unprepared" bit */
9051 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9052 barrier();
9053
9054 /* Make sure all is written to the chip before the reset */
9055 mmiowb();
9056
9057 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9058 * PSWHST, GRC and PSWRD Tetris buffer.
9059 */
9060 usleep_range(1000, 1000);
9061
9062 /* Prepare to chip reset: */
9063 /* MCP */
9064 if (global)
9065 bnx2x_reset_mcp_prep(bp, &val);
9066
9067 /* PXP */
9068 bnx2x_pxp_prep(bp);
9069 barrier();
9070
9071 /* reset the chip */
9072 bnx2x_process_kill_chip_reset(bp, global);
9073 barrier();
9074
9075 /* Recover after reset: */
9076 /* MCP */
9077 if (global && bnx2x_reset_mcp_comp(bp, val))
9078 return -EAGAIN;
9079
9080 /* TBD: Add resetting the NO_MCP mode DB here */
9081
9082 /* Open the gates #2, #3 and #4 */
9083 bnx2x_set_234_gates(bp, false);
9084
9085 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9086 * reset state, re-enable attentions. */
9087
9088 return 0;
9089 }
9090
9091 static int bnx2x_leader_reset(struct bnx2x *bp)
9092 {
9093 int rc = 0;
9094 bool global = bnx2x_reset_is_global(bp);
9095 u32 load_code;
9096
9097 /* if not going to reset MCP - load "fake" driver to reset HW while
9098 * driver is owner of the HW
9099 */
9100 if (!global && !BP_NOMCP(bp)) {
9101 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9102 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9103 if (!load_code) {
9104 BNX2X_ERR("MCP response failure, aborting\n");
9105 rc = -EAGAIN;
9106 goto exit_leader_reset;
9107 }
9108 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9109 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9110 BNX2X_ERR("MCP unexpected resp, aborting\n");
9111 rc = -EAGAIN;
9112 goto exit_leader_reset2;
9113 }
9114 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9115 if (!load_code) {
9116 BNX2X_ERR("MCP response failure, aborting\n");
9117 rc = -EAGAIN;
9118 goto exit_leader_reset2;
9119 }
9120 }
9121
9122 /* Try to recover after the failure */
9123 if (bnx2x_process_kill(bp, global)) {
9124 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9125 BP_PATH(bp));
9126 rc = -EAGAIN;
9127 goto exit_leader_reset2;
9128 }
9129
9130 /*
9131 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9132 * state.
9133 */
9134 bnx2x_set_reset_done(bp);
9135 if (global)
9136 bnx2x_clear_reset_global(bp);
9137
9138 exit_leader_reset2:
9139 /* unload "fake driver" if it was loaded */
9140 if (!global && !BP_NOMCP(bp)) {
9141 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9142 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9143 }
9144 exit_leader_reset:
9145 bp->is_leader = 0;
9146 bnx2x_release_leader_lock(bp);
9147 smp_mb();
9148 return rc;
9149 }
9150
9151 static void bnx2x_recovery_failed(struct bnx2x *bp)
9152 {
9153 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9154
9155 /* Disconnect this device */
9156 netif_device_detach(bp->dev);
9157
9158 /*
9159 * Block ifup for all function on this engine until "process kill"
9160 * or power cycle.
9161 */
9162 bnx2x_set_reset_in_progress(bp);
9163
9164 /* Shut down the power */
9165 bnx2x_set_power_state(bp, PCI_D3hot);
9166
9167 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9168
9169 smp_mb();
9170 }
9171
9172 /*
9173 * Assumption: runs under rtnl lock. This together with the fact
9174 * that it's called only from bnx2x_sp_rtnl() ensure that it
9175 * will never be called when netif_running(bp->dev) is false.
9176 */
9177 static void bnx2x_parity_recover(struct bnx2x *bp)
9178 {
9179 bool global = false;
9180 u32 error_recovered, error_unrecovered;
9181 bool is_parity;
9182
9183 DP(NETIF_MSG_HW, "Handling parity\n");
9184 while (1) {
9185 switch (bp->recovery_state) {
9186 case BNX2X_RECOVERY_INIT:
9187 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9188 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9189 WARN_ON(!is_parity);
9190
9191 /* Try to get a LEADER_LOCK HW lock */
9192 if (bnx2x_trylock_leader_lock(bp)) {
9193 bnx2x_set_reset_in_progress(bp);
9194 /*
9195 * Check if there is a global attention and if
9196 * there was a global attention, set the global
9197 * reset bit.
9198 */
9199
9200 if (global)
9201 bnx2x_set_reset_global(bp);
9202
9203 bp->is_leader = 1;
9204 }
9205
9206 /* Stop the driver */
9207 /* If interface has been removed - break */
9208 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9209 return;
9210
9211 bp->recovery_state = BNX2X_RECOVERY_WAIT;
9212
9213 /* Ensure "is_leader", MCP command sequence and
9214 * "recovery_state" update values are seen on other
9215 * CPUs.
9216 */
9217 smp_mb();
9218 break;
9219
9220 case BNX2X_RECOVERY_WAIT:
9221 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9222 if (bp->is_leader) {
9223 int other_engine = BP_PATH(bp) ? 0 : 1;
9224 bool other_load_status =
9225 bnx2x_get_load_status(bp, other_engine);
9226 bool load_status =
9227 bnx2x_get_load_status(bp, BP_PATH(bp));
9228 global = bnx2x_reset_is_global(bp);
9229
9230 /*
9231 * In case of a parity in a global block, let
9232 * the first leader that performs a
9233 * leader_reset() reset the global blocks in
9234 * order to clear global attentions. Otherwise
9235 * the the gates will remain closed for that
9236 * engine.
9237 */
9238 if (load_status ||
9239 (global && other_load_status)) {
9240 /* Wait until all other functions get
9241 * down.
9242 */
9243 schedule_delayed_work(&bp->sp_rtnl_task,
9244 HZ/10);
9245 return;
9246 } else {
9247 /* If all other functions got down -
9248 * try to bring the chip back to
9249 * normal. In any case it's an exit
9250 * point for a leader.
9251 */
9252 if (bnx2x_leader_reset(bp)) {
9253 bnx2x_recovery_failed(bp);
9254 return;
9255 }
9256
9257 /* If we are here, means that the
9258 * leader has succeeded and doesn't
9259 * want to be a leader any more. Try
9260 * to continue as a none-leader.
9261 */
9262 break;
9263 }
9264 } else { /* non-leader */
9265 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9266 /* Try to get a LEADER_LOCK HW lock as
9267 * long as a former leader may have
9268 * been unloaded by the user or
9269 * released a leadership by another
9270 * reason.
9271 */
9272 if (bnx2x_trylock_leader_lock(bp)) {
9273 /* I'm a leader now! Restart a
9274 * switch case.
9275 */
9276 bp->is_leader = 1;
9277 break;
9278 }
9279
9280 schedule_delayed_work(&bp->sp_rtnl_task,
9281 HZ/10);
9282 return;
9283
9284 } else {
9285 /*
9286 * If there was a global attention, wait
9287 * for it to be cleared.
9288 */
9289 if (bnx2x_reset_is_global(bp)) {
9290 schedule_delayed_work(
9291 &bp->sp_rtnl_task,
9292 HZ/10);
9293 return;
9294 }
9295
9296 error_recovered =
9297 bp->eth_stats.recoverable_error;
9298 error_unrecovered =
9299 bp->eth_stats.unrecoverable_error;
9300 bp->recovery_state =
9301 BNX2X_RECOVERY_NIC_LOADING;
9302 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9303 error_unrecovered++;
9304 netdev_err(bp->dev,
9305 "Recovery failed. Power cycle needed\n");
9306 /* Disconnect this device */
9307 netif_device_detach(bp->dev);
9308 /* Shut down the power */
9309 bnx2x_set_power_state(
9310 bp, PCI_D3hot);
9311 smp_mb();
9312 } else {
9313 bp->recovery_state =
9314 BNX2X_RECOVERY_DONE;
9315 error_recovered++;
9316 smp_mb();
9317 }
9318 bp->eth_stats.recoverable_error =
9319 error_recovered;
9320 bp->eth_stats.unrecoverable_error =
9321 error_unrecovered;
9322
9323 return;
9324 }
9325 }
9326 default:
9327 return;
9328 }
9329 }
9330 }
9331
9332 static int bnx2x_close(struct net_device *dev);
9333
9334 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9335 * scheduled on a general queue in order to prevent a dead lock.
9336 */
9337 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9338 {
9339 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9340
9341 rtnl_lock();
9342
9343 if (!netif_running(bp->dev))
9344 goto sp_rtnl_exit;
9345
9346 /* if stop on error is defined no recovery flows should be executed */
9347 #ifdef BNX2X_STOP_ON_ERROR
9348 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9349 "you will need to reboot when done\n");
9350 goto sp_rtnl_not_reset;
9351 #endif
9352
9353 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9354 /*
9355 * Clear all pending SP commands as we are going to reset the
9356 * function anyway.
9357 */
9358 bp->sp_rtnl_state = 0;
9359 smp_mb();
9360
9361 bnx2x_parity_recover(bp);
9362
9363 goto sp_rtnl_exit;
9364 }
9365
9366 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9367 /*
9368 * Clear all pending SP commands as we are going to reset the
9369 * function anyway.
9370 */
9371 bp->sp_rtnl_state = 0;
9372 smp_mb();
9373
9374 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9375 bnx2x_nic_load(bp, LOAD_NORMAL);
9376
9377 goto sp_rtnl_exit;
9378 }
9379 #ifdef BNX2X_STOP_ON_ERROR
9380 sp_rtnl_not_reset:
9381 #endif
9382 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9383 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9384 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9385 bnx2x_after_function_update(bp);
9386 /*
9387 * in case of fan failure we need to reset id if the "stop on error"
9388 * debug flag is set, since we trying to prevent permanent overheating
9389 * damage
9390 */
9391 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9392 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9393 netif_device_detach(bp->dev);
9394 bnx2x_close(bp->dev);
9395 }
9396
9397 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9398 DP(BNX2X_MSG_SP,
9399 "sending set mcast vf pf channel message from rtnl sp-task\n");
9400 bnx2x_vfpf_set_mcast(bp->dev);
9401 }
9402
9403 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
9404 &bp->sp_rtnl_state)) {
9405 DP(BNX2X_MSG_SP,
9406 "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9407 bnx2x_vfpf_storm_rx_mode(bp);
9408 }
9409
9410 sp_rtnl_exit:
9411 rtnl_unlock();
9412 }
9413
9414 /* end of nic load/unload */
9415
9416 static void bnx2x_period_task(struct work_struct *work)
9417 {
9418 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9419
9420 if (!netif_running(bp->dev))
9421 goto period_task_exit;
9422
9423 if (CHIP_REV_IS_SLOW(bp)) {
9424 BNX2X_ERR("period task called on emulation, ignoring\n");
9425 goto period_task_exit;
9426 }
9427
9428 bnx2x_acquire_phy_lock(bp);
9429 /*
9430 * The barrier is needed to ensure the ordering between the writing to
9431 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9432 * the reading here.
9433 */
9434 smp_mb();
9435 if (bp->port.pmf) {
9436 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9437
9438 /* Re-queue task in 1 sec */
9439 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9440 }
9441
9442 bnx2x_release_phy_lock(bp);
9443 period_task_exit:
9444 return;
9445 }
9446
9447 /*
9448 * Init service functions
9449 */
9450
9451 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9452 {
9453 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9454 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9455 return base + (BP_ABS_FUNC(bp)) * stride;
9456 }
9457
9458 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
9459 {
9460 u32 reg = bnx2x_get_pretend_reg(bp);
9461
9462 /* Flush all outstanding writes */
9463 mmiowb();
9464
9465 /* Pretend to be function 0 */
9466 REG_WR(bp, reg, 0);
9467 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
9468
9469 /* From now we are in the "like-E1" mode */
9470 bnx2x_int_disable(bp);
9471
9472 /* Flush all outstanding writes */
9473 mmiowb();
9474
9475 /* Restore the original function */
9476 REG_WR(bp, reg, BP_ABS_FUNC(bp));
9477 REG_RD(bp, reg);
9478 }
9479
9480 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
9481 {
9482 if (CHIP_IS_E1(bp))
9483 bnx2x_int_disable(bp);
9484 else
9485 bnx2x_undi_int_disable_e1h(bp);
9486 }
9487
9488 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp)
9489 {
9490 u32 val, base_addr, offset, mask, reset_reg;
9491 bool mac_stopped = false;
9492 u8 port = BP_PORT(bp);
9493
9494 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9495
9496 if (!CHIP_IS_E3(bp)) {
9497 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9498 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9499 if ((mask & reset_reg) && val) {
9500 u32 wb_data[2];
9501 BNX2X_DEV_INFO("Disable bmac Rx\n");
9502 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9503 : NIG_REG_INGRESS_BMAC0_MEM;
9504 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9505 : BIGMAC_REGISTER_BMAC_CONTROL;
9506
9507 /*
9508 * use rd/wr since we cannot use dmae. This is safe
9509 * since MCP won't access the bus due to the request
9510 * to unload, and no function on the path can be
9511 * loaded at this time.
9512 */
9513 wb_data[0] = REG_RD(bp, base_addr + offset);
9514 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9515 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9516 REG_WR(bp, base_addr + offset, wb_data[0]);
9517 REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
9518
9519 }
9520 BNX2X_DEV_INFO("Disable emac Rx\n");
9521 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
9522
9523 mac_stopped = true;
9524 } else {
9525 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9526 BNX2X_DEV_INFO("Disable xmac Rx\n");
9527 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9528 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9529 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9530 val & ~(1 << 1));
9531 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9532 val | (1 << 1));
9533 REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
9534 mac_stopped = true;
9535 }
9536 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9537 if (mask & reset_reg) {
9538 BNX2X_DEV_INFO("Disable umac Rx\n");
9539 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9540 REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
9541 mac_stopped = true;
9542 }
9543 }
9544
9545 if (mac_stopped)
9546 msleep(20);
9547
9548 }
9549
9550 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9551 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9552 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9553 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9554
9555 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9556 {
9557 u16 rcq, bd;
9558 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9559
9560 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9561 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9562
9563 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9564 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9565
9566 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9567 port, bd, rcq);
9568 }
9569
9570 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9571 {
9572 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9573 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9574 if (!rc) {
9575 BNX2X_ERR("MCP response failure, aborting\n");
9576 return -EBUSY;
9577 }
9578
9579 return 0;
9580 }
9581
9582 static struct bnx2x_prev_path_list *
9583 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9584 {
9585 struct bnx2x_prev_path_list *tmp_list;
9586
9587 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9588 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9589 bp->pdev->bus->number == tmp_list->bus &&
9590 BP_PATH(bp) == tmp_list->path)
9591 return tmp_list;
9592
9593 return NULL;
9594 }
9595
9596 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9597 {
9598 struct bnx2x_prev_path_list *tmp_list;
9599 int rc = false;
9600
9601 if (down_trylock(&bnx2x_prev_sem))
9602 return false;
9603
9604 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9605 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9606 bp->pdev->bus->number == tmp_list->bus &&
9607 BP_PATH(bp) == tmp_list->path) {
9608 rc = true;
9609 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9610 BP_PATH(bp));
9611 break;
9612 }
9613 }
9614
9615 up(&bnx2x_prev_sem);
9616
9617 return rc;
9618 }
9619
9620 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9621 {
9622 struct bnx2x_prev_path_list *tmp_list;
9623 int rc;
9624
9625 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9626 if (!tmp_list) {
9627 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9628 return -ENOMEM;
9629 }
9630
9631 tmp_list->bus = bp->pdev->bus->number;
9632 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9633 tmp_list->path = BP_PATH(bp);
9634 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9635
9636 rc = down_interruptible(&bnx2x_prev_sem);
9637 if (rc) {
9638 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9639 kfree(tmp_list);
9640 } else {
9641 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9642 BP_PATH(bp));
9643 list_add(&tmp_list->list, &bnx2x_prev_list);
9644 up(&bnx2x_prev_sem);
9645 }
9646
9647 return rc;
9648 }
9649
9650 static int bnx2x_do_flr(struct bnx2x *bp)
9651 {
9652 int i;
9653 u16 status;
9654 struct pci_dev *dev = bp->pdev;
9655
9656
9657 if (CHIP_IS_E1x(bp)) {
9658 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9659 return -EINVAL;
9660 }
9661
9662 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9663 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9664 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9665 bp->common.bc_ver);
9666 return -EINVAL;
9667 }
9668
9669 /* Wait for Transaction Pending bit clean */
9670 for (i = 0; i < 4; i++) {
9671 if (i)
9672 msleep((1 << (i - 1)) * 100);
9673
9674 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9675 if (!(status & PCI_EXP_DEVSTA_TRPND))
9676 goto clear;
9677 }
9678
9679 dev_err(&dev->dev,
9680 "transaction is not cleared; proceeding with reset anyway\n");
9681
9682 clear:
9683
9684 BNX2X_DEV_INFO("Initiating FLR\n");
9685 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9686
9687 return 0;
9688 }
9689
9690 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9691 {
9692 int rc;
9693
9694 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9695
9696 /* Test if previous unload process was already finished for this path */
9697 if (bnx2x_prev_is_path_marked(bp))
9698 return bnx2x_prev_mcp_done(bp);
9699
9700 /* If function has FLR capabilities, and existing FW version matches
9701 * the one required, then FLR will be sufficient to clean any residue
9702 * left by previous driver
9703 */
9704 rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9705
9706 if (!rc) {
9707 /* fw version is good */
9708 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9709 rc = bnx2x_do_flr(bp);
9710 }
9711
9712 if (!rc) {
9713 /* FLR was performed */
9714 BNX2X_DEV_INFO("FLR successful\n");
9715 return 0;
9716 }
9717
9718 BNX2X_DEV_INFO("Could not FLR\n");
9719
9720 /* Close the MCP request, return failure*/
9721 rc = bnx2x_prev_mcp_done(bp);
9722 if (!rc)
9723 rc = BNX2X_PREV_WAIT_NEEDED;
9724
9725 return rc;
9726 }
9727
9728 static int bnx2x_prev_unload_common(struct bnx2x *bp)
9729 {
9730 u32 reset_reg, tmp_reg = 0, rc;
9731 bool prev_undi = false;
9732 /* It is possible a previous function received 'common' answer,
9733 * but hasn't loaded yet, therefore creating a scenario of
9734 * multiple functions receiving 'common' on the same path.
9735 */
9736 BNX2X_DEV_INFO("Common unload Flow\n");
9737
9738 if (bnx2x_prev_is_path_marked(bp))
9739 return bnx2x_prev_mcp_done(bp);
9740
9741 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9742
9743 /* Reset should be performed after BRB is emptied */
9744 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9745 u32 timer_count = 1000;
9746
9747 /* Close the MAC Rx to prevent BRB from filling up */
9748 bnx2x_prev_unload_close_mac(bp);
9749
9750 /* Check if the UNDI driver was previously loaded
9751 * UNDI driver initializes CID offset for normal bell to 0x7
9752 */
9753 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9754 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9755 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9756 if (tmp_reg == 0x7) {
9757 BNX2X_DEV_INFO("UNDI previously loaded\n");
9758 prev_undi = true;
9759 /* clear the UNDI indication */
9760 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9761 }
9762 }
9763 /* wait until BRB is empty */
9764 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9765 while (timer_count) {
9766 u32 prev_brb = tmp_reg;
9767
9768 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9769 if (!tmp_reg)
9770 break;
9771
9772 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9773
9774 /* reset timer as long as BRB actually gets emptied */
9775 if (prev_brb > tmp_reg)
9776 timer_count = 1000;
9777 else
9778 timer_count--;
9779
9780 /* If UNDI resides in memory, manually increment it */
9781 if (prev_undi)
9782 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9783
9784 udelay(10);
9785 }
9786
9787 if (!timer_count)
9788 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9789
9790 }
9791
9792 /* No packets are in the pipeline, path is ready for reset */
9793 bnx2x_reset_common(bp);
9794
9795 rc = bnx2x_prev_mark_path(bp, prev_undi);
9796 if (rc) {
9797 bnx2x_prev_mcp_done(bp);
9798 return rc;
9799 }
9800
9801 return bnx2x_prev_mcp_done(bp);
9802 }
9803
9804 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9805 * and boot began, or when kdump kernel was loaded. Either case would invalidate
9806 * the addresses of the transaction, resulting in was-error bit set in the pci
9807 * causing all hw-to-host pcie transactions to timeout. If this happened we want
9808 * to clear the interrupt which detected this from the pglueb and the was done
9809 * bit
9810 */
9811 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
9812 {
9813 if (!CHIP_IS_E1x(bp)) {
9814 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9815 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9816 BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9817 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9818 1 << BP_FUNC(bp));
9819 }
9820 }
9821 }
9822
9823 static int bnx2x_prev_unload(struct bnx2x *bp)
9824 {
9825 int time_counter = 10;
9826 u32 rc, fw, hw_lock_reg, hw_lock_val;
9827 struct bnx2x_prev_path_list *prev_list;
9828 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9829
9830 /* clear hw from errors which may have resulted from an interrupted
9831 * dmae transaction.
9832 */
9833 bnx2x_prev_interrupted_dmae(bp);
9834
9835 /* Release previously held locks */
9836 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9837 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9838 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9839
9840 hw_lock_val = (REG_RD(bp, hw_lock_reg));
9841 if (hw_lock_val) {
9842 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9843 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9844 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9845 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9846 }
9847
9848 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9849 REG_WR(bp, hw_lock_reg, 0xffffffff);
9850 } else
9851 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9852
9853 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9854 BNX2X_DEV_INFO("Release previously held alr\n");
9855 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9856 }
9857
9858
9859 do {
9860 /* Lock MCP using an unload request */
9861 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9862 if (!fw) {
9863 BNX2X_ERR("MCP response failure, aborting\n");
9864 rc = -EBUSY;
9865 break;
9866 }
9867
9868 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9869 rc = bnx2x_prev_unload_common(bp);
9870 break;
9871 }
9872
9873 /* non-common reply from MCP night require looping */
9874 rc = bnx2x_prev_unload_uncommon(bp);
9875 if (rc != BNX2X_PREV_WAIT_NEEDED)
9876 break;
9877
9878 msleep(20);
9879 } while (--time_counter);
9880
9881 if (!time_counter || rc) {
9882 BNX2X_ERR("Failed unloading previous driver, aborting\n");
9883 rc = -EBUSY;
9884 }
9885
9886 /* Mark function if its port was used to boot from SAN */
9887 prev_list = bnx2x_prev_path_get_entry(bp);
9888 if (prev_list && (prev_list->undi & (1 << BP_PORT(bp))))
9889 bp->link_params.feature_config_flags |=
9890 FEATURE_CONFIG_BOOT_FROM_SAN;
9891
9892 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
9893
9894 return rc;
9895 }
9896
9897 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
9898 {
9899 u32 val, val2, val3, val4, id, boot_mode;
9900 u16 pmc;
9901
9902 /* Get the chip revision id and number. */
9903 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
9904 val = REG_RD(bp, MISC_REG_CHIP_NUM);
9905 id = ((val & 0xffff) << 16);
9906 val = REG_RD(bp, MISC_REG_CHIP_REV);
9907 id |= ((val & 0xf) << 12);
9908 val = REG_RD(bp, MISC_REG_CHIP_METAL);
9909 id |= ((val & 0xff) << 4);
9910 val = REG_RD(bp, MISC_REG_BOND_ID);
9911 id |= (val & 0xf);
9912 bp->common.chip_id = id;
9913
9914 /* force 57811 according to MISC register */
9915 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
9916 if (CHIP_IS_57810(bp))
9917 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
9918 (bp->common.chip_id & 0x0000FFFF);
9919 else if (CHIP_IS_57810_MF(bp))
9920 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
9921 (bp->common.chip_id & 0x0000FFFF);
9922 bp->common.chip_id |= 0x1;
9923 }
9924
9925 /* Set doorbell size */
9926 bp->db_size = (1 << BNX2X_DB_SHIFT);
9927
9928 if (!CHIP_IS_E1x(bp)) {
9929 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
9930 if ((val & 1) == 0)
9931 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
9932 else
9933 val = (val >> 1) & 1;
9934 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
9935 "2_PORT_MODE");
9936 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
9937 CHIP_2_PORT_MODE;
9938
9939 if (CHIP_MODE_IS_4_PORT(bp))
9940 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
9941 else
9942 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
9943 } else {
9944 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
9945 bp->pfid = bp->pf_num; /* 0..7 */
9946 }
9947
9948 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
9949
9950 bp->link_params.chip_id = bp->common.chip_id;
9951 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
9952
9953 val = (REG_RD(bp, 0x2874) & 0x55);
9954 if ((bp->common.chip_id & 0x1) ||
9955 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
9956 bp->flags |= ONE_PORT_FLAG;
9957 BNX2X_DEV_INFO("single port device\n");
9958 }
9959
9960 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
9961 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
9962 (val & MCPR_NVM_CFG4_FLASH_SIZE));
9963 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
9964 bp->common.flash_size, bp->common.flash_size);
9965
9966 bnx2x_init_shmem(bp);
9967
9968
9969
9970 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
9971 MISC_REG_GENERIC_CR_1 :
9972 MISC_REG_GENERIC_CR_0));
9973
9974 bp->link_params.shmem_base = bp->common.shmem_base;
9975 bp->link_params.shmem2_base = bp->common.shmem2_base;
9976 if (SHMEM2_RD(bp, size) >
9977 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
9978 bp->link_params.lfa_base =
9979 REG_RD(bp, bp->common.shmem2_base +
9980 (u32)offsetof(struct shmem2_region,
9981 lfa_host_addr[BP_PORT(bp)]));
9982 else
9983 bp->link_params.lfa_base = 0;
9984 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
9985 bp->common.shmem_base, bp->common.shmem2_base);
9986
9987 if (!bp->common.shmem_base) {
9988 BNX2X_DEV_INFO("MCP not active\n");
9989 bp->flags |= NO_MCP_FLAG;
9990 return;
9991 }
9992
9993 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
9994 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
9995
9996 bp->link_params.hw_led_mode = ((bp->common.hw_config &
9997 SHARED_HW_CFG_LED_MODE_MASK) >>
9998 SHARED_HW_CFG_LED_MODE_SHIFT);
9999
10000 bp->link_params.feature_config_flags = 0;
10001 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10002 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10003 bp->link_params.feature_config_flags |=
10004 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10005 else
10006 bp->link_params.feature_config_flags &=
10007 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10008
10009 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10010 bp->common.bc_ver = val;
10011 BNX2X_DEV_INFO("bc_ver %X\n", val);
10012 if (val < BNX2X_BC_VER) {
10013 /* for now only warn
10014 * later we might need to enforce this */
10015 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10016 BNX2X_BC_VER, val);
10017 }
10018 bp->link_params.feature_config_flags |=
10019 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10020 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10021
10022 bp->link_params.feature_config_flags |=
10023 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10024 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10025 bp->link_params.feature_config_flags |=
10026 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10027 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10028 bp->link_params.feature_config_flags |=
10029 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10030 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10031
10032 bp->link_params.feature_config_flags |=
10033 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10034 FEATURE_CONFIG_MT_SUPPORT : 0;
10035
10036 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10037 BC_SUPPORTS_PFC_STATS : 0;
10038
10039 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10040 BC_SUPPORTS_FCOE_FEATURES : 0;
10041
10042 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10043 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10044 boot_mode = SHMEM_RD(bp,
10045 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10046 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10047 switch (boot_mode) {
10048 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10049 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10050 break;
10051 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10052 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10053 break;
10054 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10055 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10056 break;
10057 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10058 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10059 break;
10060 }
10061
10062 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10063 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10064
10065 BNX2X_DEV_INFO("%sWoL capable\n",
10066 (bp->flags & NO_WOL_FLAG) ? "not " : "");
10067
10068 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10069 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10070 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10071 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10072
10073 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10074 val, val2, val3, val4);
10075 }
10076
10077 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10078 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10079
10080 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10081 {
10082 int pfid = BP_FUNC(bp);
10083 int igu_sb_id;
10084 u32 val;
10085 u8 fid, igu_sb_cnt = 0;
10086
10087 bp->igu_base_sb = 0xff;
10088 if (CHIP_INT_MODE_IS_BC(bp)) {
10089 int vn = BP_VN(bp);
10090 igu_sb_cnt = bp->igu_sb_cnt;
10091 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10092 FP_SB_MAX_E1x;
10093
10094 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10095 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10096
10097 return 0;
10098 }
10099
10100 /* IGU in normal mode - read CAM */
10101 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10102 igu_sb_id++) {
10103 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10104 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10105 continue;
10106 fid = IGU_FID(val);
10107 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10108 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10109 continue;
10110 if (IGU_VEC(val) == 0)
10111 /* default status block */
10112 bp->igu_dsb_id = igu_sb_id;
10113 else {
10114 if (bp->igu_base_sb == 0xff)
10115 bp->igu_base_sb = igu_sb_id;
10116 igu_sb_cnt++;
10117 }
10118 }
10119 }
10120
10121 #ifdef CONFIG_PCI_MSI
10122 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10123 * optional that number of CAM entries will not be equal to the value
10124 * advertised in PCI.
10125 * Driver should use the minimal value of both as the actual status
10126 * block count
10127 */
10128 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10129 #endif
10130
10131 if (igu_sb_cnt == 0) {
10132 BNX2X_ERR("CAM configuration error\n");
10133 return -EINVAL;
10134 }
10135
10136 return 0;
10137 }
10138
10139 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10140 {
10141 int cfg_size = 0, idx, port = BP_PORT(bp);
10142
10143 /* Aggregation of supported attributes of all external phys */
10144 bp->port.supported[0] = 0;
10145 bp->port.supported[1] = 0;
10146 switch (bp->link_params.num_phys) {
10147 case 1:
10148 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10149 cfg_size = 1;
10150 break;
10151 case 2:
10152 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10153 cfg_size = 1;
10154 break;
10155 case 3:
10156 if (bp->link_params.multi_phy_config &
10157 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10158 bp->port.supported[1] =
10159 bp->link_params.phy[EXT_PHY1].supported;
10160 bp->port.supported[0] =
10161 bp->link_params.phy[EXT_PHY2].supported;
10162 } else {
10163 bp->port.supported[0] =
10164 bp->link_params.phy[EXT_PHY1].supported;
10165 bp->port.supported[1] =
10166 bp->link_params.phy[EXT_PHY2].supported;
10167 }
10168 cfg_size = 2;
10169 break;
10170 }
10171
10172 if (!(bp->port.supported[0] || bp->port.supported[1])) {
10173 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10174 SHMEM_RD(bp,
10175 dev_info.port_hw_config[port].external_phy_config),
10176 SHMEM_RD(bp,
10177 dev_info.port_hw_config[port].external_phy_config2));
10178 return;
10179 }
10180
10181 if (CHIP_IS_E3(bp))
10182 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10183 else {
10184 switch (switch_cfg) {
10185 case SWITCH_CFG_1G:
10186 bp->port.phy_addr = REG_RD(
10187 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10188 break;
10189 case SWITCH_CFG_10G:
10190 bp->port.phy_addr = REG_RD(
10191 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10192 break;
10193 default:
10194 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10195 bp->port.link_config[0]);
10196 return;
10197 }
10198 }
10199 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10200 /* mask what we support according to speed_cap_mask per configuration */
10201 for (idx = 0; idx < cfg_size; idx++) {
10202 if (!(bp->link_params.speed_cap_mask[idx] &
10203 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10204 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10205
10206 if (!(bp->link_params.speed_cap_mask[idx] &
10207 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10208 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10209
10210 if (!(bp->link_params.speed_cap_mask[idx] &
10211 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10212 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10213
10214 if (!(bp->link_params.speed_cap_mask[idx] &
10215 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10216 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10217
10218 if (!(bp->link_params.speed_cap_mask[idx] &
10219 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10220 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10221 SUPPORTED_1000baseT_Full);
10222
10223 if (!(bp->link_params.speed_cap_mask[idx] &
10224 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10225 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10226
10227 if (!(bp->link_params.speed_cap_mask[idx] &
10228 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10229 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10230
10231 }
10232
10233 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10234 bp->port.supported[1]);
10235 }
10236
10237 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10238 {
10239 u32 link_config, idx, cfg_size = 0;
10240 bp->port.advertising[0] = 0;
10241 bp->port.advertising[1] = 0;
10242 switch (bp->link_params.num_phys) {
10243 case 1:
10244 case 2:
10245 cfg_size = 1;
10246 break;
10247 case 3:
10248 cfg_size = 2;
10249 break;
10250 }
10251 for (idx = 0; idx < cfg_size; idx++) {
10252 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10253 link_config = bp->port.link_config[idx];
10254 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10255 case PORT_FEATURE_LINK_SPEED_AUTO:
10256 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10257 bp->link_params.req_line_speed[idx] =
10258 SPEED_AUTO_NEG;
10259 bp->port.advertising[idx] |=
10260 bp->port.supported[idx];
10261 if (bp->link_params.phy[EXT_PHY1].type ==
10262 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10263 bp->port.advertising[idx] |=
10264 (SUPPORTED_100baseT_Half |
10265 SUPPORTED_100baseT_Full);
10266 } else {
10267 /* force 10G, no AN */
10268 bp->link_params.req_line_speed[idx] =
10269 SPEED_10000;
10270 bp->port.advertising[idx] |=
10271 (ADVERTISED_10000baseT_Full |
10272 ADVERTISED_FIBRE);
10273 continue;
10274 }
10275 break;
10276
10277 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10278 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10279 bp->link_params.req_line_speed[idx] =
10280 SPEED_10;
10281 bp->port.advertising[idx] |=
10282 (ADVERTISED_10baseT_Full |
10283 ADVERTISED_TP);
10284 } else {
10285 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10286 link_config,
10287 bp->link_params.speed_cap_mask[idx]);
10288 return;
10289 }
10290 break;
10291
10292 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10293 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10294 bp->link_params.req_line_speed[idx] =
10295 SPEED_10;
10296 bp->link_params.req_duplex[idx] =
10297 DUPLEX_HALF;
10298 bp->port.advertising[idx] |=
10299 (ADVERTISED_10baseT_Half |
10300 ADVERTISED_TP);
10301 } else {
10302 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10303 link_config,
10304 bp->link_params.speed_cap_mask[idx]);
10305 return;
10306 }
10307 break;
10308
10309 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10310 if (bp->port.supported[idx] &
10311 SUPPORTED_100baseT_Full) {
10312 bp->link_params.req_line_speed[idx] =
10313 SPEED_100;
10314 bp->port.advertising[idx] |=
10315 (ADVERTISED_100baseT_Full |
10316 ADVERTISED_TP);
10317 } else {
10318 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10319 link_config,
10320 bp->link_params.speed_cap_mask[idx]);
10321 return;
10322 }
10323 break;
10324
10325 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10326 if (bp->port.supported[idx] &
10327 SUPPORTED_100baseT_Half) {
10328 bp->link_params.req_line_speed[idx] =
10329 SPEED_100;
10330 bp->link_params.req_duplex[idx] =
10331 DUPLEX_HALF;
10332 bp->port.advertising[idx] |=
10333 (ADVERTISED_100baseT_Half |
10334 ADVERTISED_TP);
10335 } else {
10336 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10337 link_config,
10338 bp->link_params.speed_cap_mask[idx]);
10339 return;
10340 }
10341 break;
10342
10343 case PORT_FEATURE_LINK_SPEED_1G:
10344 if (bp->port.supported[idx] &
10345 SUPPORTED_1000baseT_Full) {
10346 bp->link_params.req_line_speed[idx] =
10347 SPEED_1000;
10348 bp->port.advertising[idx] |=
10349 (ADVERTISED_1000baseT_Full |
10350 ADVERTISED_TP);
10351 } else {
10352 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10353 link_config,
10354 bp->link_params.speed_cap_mask[idx]);
10355 return;
10356 }
10357 break;
10358
10359 case PORT_FEATURE_LINK_SPEED_2_5G:
10360 if (bp->port.supported[idx] &
10361 SUPPORTED_2500baseX_Full) {
10362 bp->link_params.req_line_speed[idx] =
10363 SPEED_2500;
10364 bp->port.advertising[idx] |=
10365 (ADVERTISED_2500baseX_Full |
10366 ADVERTISED_TP);
10367 } else {
10368 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10369 link_config,
10370 bp->link_params.speed_cap_mask[idx]);
10371 return;
10372 }
10373 break;
10374
10375 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10376 if (bp->port.supported[idx] &
10377 SUPPORTED_10000baseT_Full) {
10378 bp->link_params.req_line_speed[idx] =
10379 SPEED_10000;
10380 bp->port.advertising[idx] |=
10381 (ADVERTISED_10000baseT_Full |
10382 ADVERTISED_FIBRE);
10383 } else {
10384 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10385 link_config,
10386 bp->link_params.speed_cap_mask[idx]);
10387 return;
10388 }
10389 break;
10390 case PORT_FEATURE_LINK_SPEED_20G:
10391 bp->link_params.req_line_speed[idx] = SPEED_20000;
10392
10393 break;
10394 default:
10395 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10396 link_config);
10397 bp->link_params.req_line_speed[idx] =
10398 SPEED_AUTO_NEG;
10399 bp->port.advertising[idx] =
10400 bp->port.supported[idx];
10401 break;
10402 }
10403
10404 bp->link_params.req_flow_ctrl[idx] = (link_config &
10405 PORT_FEATURE_FLOW_CONTROL_MASK);
10406 if (bp->link_params.req_flow_ctrl[idx] ==
10407 BNX2X_FLOW_CTRL_AUTO) {
10408 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10409 bp->link_params.req_flow_ctrl[idx] =
10410 BNX2X_FLOW_CTRL_NONE;
10411 else
10412 bnx2x_set_requested_fc(bp);
10413 }
10414
10415 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10416 bp->link_params.req_line_speed[idx],
10417 bp->link_params.req_duplex[idx],
10418 bp->link_params.req_flow_ctrl[idx],
10419 bp->port.advertising[idx]);
10420 }
10421 }
10422
10423 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10424 {
10425 mac_hi = cpu_to_be16(mac_hi);
10426 mac_lo = cpu_to_be32(mac_lo);
10427 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
10428 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
10429 }
10430
10431 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10432 {
10433 int port = BP_PORT(bp);
10434 u32 config;
10435 u32 ext_phy_type, ext_phy_config, eee_mode;
10436
10437 bp->link_params.bp = bp;
10438 bp->link_params.port = port;
10439
10440 bp->link_params.lane_config =
10441 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10442
10443 bp->link_params.speed_cap_mask[0] =
10444 SHMEM_RD(bp,
10445 dev_info.port_hw_config[port].speed_capability_mask);
10446 bp->link_params.speed_cap_mask[1] =
10447 SHMEM_RD(bp,
10448 dev_info.port_hw_config[port].speed_capability_mask2);
10449 bp->port.link_config[0] =
10450 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10451
10452 bp->port.link_config[1] =
10453 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10454
10455 bp->link_params.multi_phy_config =
10456 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10457 /* If the device is capable of WoL, set the default state according
10458 * to the HW
10459 */
10460 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10461 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10462 (config & PORT_FEATURE_WOL_ENABLED));
10463
10464 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10465 bp->link_params.lane_config,
10466 bp->link_params.speed_cap_mask[0],
10467 bp->port.link_config[0]);
10468
10469 bp->link_params.switch_cfg = (bp->port.link_config[0] &
10470 PORT_FEATURE_CONNECTED_SWITCH_MASK);
10471 bnx2x_phy_probe(&bp->link_params);
10472 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10473
10474 bnx2x_link_settings_requested(bp);
10475
10476 /*
10477 * If connected directly, work with the internal PHY, otherwise, work
10478 * with the external PHY
10479 */
10480 ext_phy_config =
10481 SHMEM_RD(bp,
10482 dev_info.port_hw_config[port].external_phy_config);
10483 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10484 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10485 bp->mdio.prtad = bp->port.phy_addr;
10486
10487 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10488 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10489 bp->mdio.prtad =
10490 XGXS_EXT_PHY_ADDR(ext_phy_config);
10491
10492 /* Configure link feature according to nvram value */
10493 eee_mode = (((SHMEM_RD(bp, dev_info.
10494 port_feature_config[port].eee_power_mode)) &
10495 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10496 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10497 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10498 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10499 EEE_MODE_ENABLE_LPI |
10500 EEE_MODE_OUTPUT_TIME;
10501 } else {
10502 bp->link_params.eee_mode = 0;
10503 }
10504 }
10505
10506 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10507 {
10508 u32 no_flags = NO_ISCSI_FLAG;
10509 int port = BP_PORT(bp);
10510 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10511 drv_lic_key[port].max_iscsi_conn);
10512
10513 if (!CNIC_SUPPORT(bp)) {
10514 bp->flags |= no_flags;
10515 return;
10516 }
10517
10518 /* Get the number of maximum allowed iSCSI connections */
10519 bp->cnic_eth_dev.max_iscsi_conn =
10520 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10521 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10522
10523 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10524 bp->cnic_eth_dev.max_iscsi_conn);
10525
10526 /*
10527 * If maximum allowed number of connections is zero -
10528 * disable the feature.
10529 */
10530 if (!bp->cnic_eth_dev.max_iscsi_conn)
10531 bp->flags |= no_flags;
10532
10533 }
10534
10535 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10536 {
10537 /* Port info */
10538 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10539 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10540 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10541 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10542
10543 /* Node info */
10544 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10545 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10546 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10547 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10548 }
10549 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10550 {
10551 int port = BP_PORT(bp);
10552 int func = BP_ABS_FUNC(bp);
10553 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10554 drv_lic_key[port].max_fcoe_conn);
10555
10556 if (!CNIC_SUPPORT(bp)) {
10557 bp->flags |= NO_FCOE_FLAG;
10558 return;
10559 }
10560
10561 /* Get the number of maximum allowed FCoE connections */
10562 bp->cnic_eth_dev.max_fcoe_conn =
10563 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10564 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10565
10566 /* Read the WWN: */
10567 if (!IS_MF(bp)) {
10568 /* Port info */
10569 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10570 SHMEM_RD(bp,
10571 dev_info.port_hw_config[port].
10572 fcoe_wwn_port_name_upper);
10573 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10574 SHMEM_RD(bp,
10575 dev_info.port_hw_config[port].
10576 fcoe_wwn_port_name_lower);
10577
10578 /* Node info */
10579 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10580 SHMEM_RD(bp,
10581 dev_info.port_hw_config[port].
10582 fcoe_wwn_node_name_upper);
10583 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10584 SHMEM_RD(bp,
10585 dev_info.port_hw_config[port].
10586 fcoe_wwn_node_name_lower);
10587 } else if (!IS_MF_SD(bp)) {
10588 /*
10589 * Read the WWN info only if the FCoE feature is enabled for
10590 * this function.
10591 */
10592 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10593 bnx2x_get_ext_wwn_info(bp, func);
10594
10595 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
10596 bnx2x_get_ext_wwn_info(bp, func);
10597 }
10598
10599 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10600
10601 /*
10602 * If maximum allowed number of connections is zero -
10603 * disable the feature.
10604 */
10605 if (!bp->cnic_eth_dev.max_fcoe_conn)
10606 bp->flags |= NO_FCOE_FLAG;
10607 }
10608
10609 static void bnx2x_get_cnic_info(struct bnx2x *bp)
10610 {
10611 /*
10612 * iSCSI may be dynamically disabled but reading
10613 * info here we will decrease memory usage by driver
10614 * if the feature is disabled for good
10615 */
10616 bnx2x_get_iscsi_info(bp);
10617 bnx2x_get_fcoe_info(bp);
10618 }
10619
10620 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
10621 {
10622 u32 val, val2;
10623 int func = BP_ABS_FUNC(bp);
10624 int port = BP_PORT(bp);
10625 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10626 u8 *fip_mac = bp->fip_mac;
10627
10628 if (IS_MF(bp)) {
10629 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10630 * FCoE MAC then the appropriate feature should be disabled.
10631 * In non SD mode features configuration comes from struct
10632 * func_ext_config.
10633 */
10634 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
10635 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10636 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10637 val2 = MF_CFG_RD(bp, func_ext_config[func].
10638 iscsi_mac_addr_upper);
10639 val = MF_CFG_RD(bp, func_ext_config[func].
10640 iscsi_mac_addr_lower);
10641 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10642 BNX2X_DEV_INFO
10643 ("Read iSCSI MAC: %pM\n", iscsi_mac);
10644 } else {
10645 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10646 }
10647
10648 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10649 val2 = MF_CFG_RD(bp, func_ext_config[func].
10650 fcoe_mac_addr_upper);
10651 val = MF_CFG_RD(bp, func_ext_config[func].
10652 fcoe_mac_addr_lower);
10653 bnx2x_set_mac_buf(fip_mac, val, val2);
10654 BNX2X_DEV_INFO
10655 ("Read FCoE L2 MAC: %pM\n", fip_mac);
10656 } else {
10657 bp->flags |= NO_FCOE_FLAG;
10658 }
10659
10660 bp->mf_ext_config = cfg;
10661
10662 } else { /* SD MODE */
10663 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10664 /* use primary mac as iscsi mac */
10665 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
10666
10667 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10668 BNX2X_DEV_INFO
10669 ("Read iSCSI MAC: %pM\n", iscsi_mac);
10670 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
10671 /* use primary mac as fip mac */
10672 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
10673 BNX2X_DEV_INFO("SD FCoE MODE\n");
10674 BNX2X_DEV_INFO
10675 ("Read FIP MAC: %pM\n", fip_mac);
10676 }
10677 }
10678
10679 if (IS_MF_STORAGE_SD(bp))
10680 /* Zero primary MAC configuration */
10681 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10682
10683 if (IS_MF_FCOE_AFEX(bp))
10684 /* use FIP MAC as primary MAC */
10685 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10686
10687 } else {
10688 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10689 iscsi_mac_upper);
10690 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10691 iscsi_mac_lower);
10692 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10693
10694 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10695 fcoe_fip_mac_upper);
10696 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10697 fcoe_fip_mac_lower);
10698 bnx2x_set_mac_buf(fip_mac, val, val2);
10699 }
10700
10701 /* Disable iSCSI OOO if MAC configuration is invalid. */
10702 if (!is_valid_ether_addr(iscsi_mac)) {
10703 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10704 memset(iscsi_mac, 0, ETH_ALEN);
10705 }
10706
10707 /* Disable FCoE if MAC configuration is invalid. */
10708 if (!is_valid_ether_addr(fip_mac)) {
10709 bp->flags |= NO_FCOE_FLAG;
10710 memset(bp->fip_mac, 0, ETH_ALEN);
10711 }
10712 }
10713
10714 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10715 {
10716 u32 val, val2;
10717 int func = BP_ABS_FUNC(bp);
10718 int port = BP_PORT(bp);
10719
10720 /* Zero primary MAC configuration */
10721 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10722
10723 if (BP_NOMCP(bp)) {
10724 BNX2X_ERROR("warning: random MAC workaround active\n");
10725 eth_hw_addr_random(bp->dev);
10726 } else if (IS_MF(bp)) {
10727 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10728 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10729 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10730 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10731 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10732
10733 if (CNIC_SUPPORT(bp))
10734 bnx2x_get_cnic_mac_hwinfo(bp);
10735 } else {
10736 /* in SF read MACs from port configuration */
10737 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10738 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10739 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10740
10741 if (CNIC_SUPPORT(bp))
10742 bnx2x_get_cnic_mac_hwinfo(bp);
10743 }
10744
10745 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10746 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
10747
10748 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10749 dev_err(&bp->pdev->dev,
10750 "bad Ethernet MAC address configuration: %pM\n"
10751 "change it manually before bringing up the appropriate network interface\n",
10752 bp->dev->dev_addr);
10753 }
10754
10755 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
10756 {
10757 int tmp;
10758 u32 cfg;
10759
10760 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
10761 /* Take function: tmp = func */
10762 tmp = BP_ABS_FUNC(bp);
10763 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
10764 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
10765 } else {
10766 /* Take port: tmp = port */
10767 tmp = BP_PORT(bp);
10768 cfg = SHMEM_RD(bp,
10769 dev_info.port_hw_config[tmp].generic_features);
10770 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
10771 }
10772 return cfg;
10773 }
10774
10775 static int bnx2x_get_hwinfo(struct bnx2x *bp)
10776 {
10777 int /*abs*/func = BP_ABS_FUNC(bp);
10778 int vn;
10779 u32 val = 0;
10780 int rc = 0;
10781
10782 bnx2x_get_common_hwinfo(bp);
10783
10784 /*
10785 * initialize IGU parameters
10786 */
10787 if (CHIP_IS_E1x(bp)) {
10788 bp->common.int_block = INT_BLOCK_HC;
10789
10790 bp->igu_dsb_id = DEF_SB_IGU_ID;
10791 bp->igu_base_sb = 0;
10792 } else {
10793 bp->common.int_block = INT_BLOCK_IGU;
10794
10795 /* do not allow device reset during IGU info preocessing */
10796 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10797
10798 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
10799
10800 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10801 int tout = 5000;
10802
10803 BNX2X_DEV_INFO("FORCING Normal Mode\n");
10804
10805 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10806 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10807 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10808
10809 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10810 tout--;
10811 usleep_range(1000, 1000);
10812 }
10813
10814 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10815 dev_err(&bp->pdev->dev,
10816 "FORCING Normal Mode failed!!!\n");
10817 bnx2x_release_hw_lock(bp,
10818 HW_LOCK_RESOURCE_RESET);
10819 return -EPERM;
10820 }
10821 }
10822
10823 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10824 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10825 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10826 } else
10827 BNX2X_DEV_INFO("IGU Normal Mode\n");
10828
10829 rc = bnx2x_get_igu_cam_info(bp);
10830 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10831 if (rc)
10832 return rc;
10833 }
10834
10835 /*
10836 * set base FW non-default (fast path) status block id, this value is
10837 * used to initialize the fw_sb_id saved on the fp/queue structure to
10838 * determine the id used by the FW.
10839 */
10840 if (CHIP_IS_E1x(bp))
10841 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10842 else /*
10843 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10844 * the same queue are indicated on the same IGU SB). So we prefer
10845 * FW and IGU SBs to be the same value.
10846 */
10847 bp->base_fw_ndsb = bp->igu_base_sb;
10848
10849 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
10850 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10851 bp->igu_sb_cnt, bp->base_fw_ndsb);
10852
10853 /*
10854 * Initialize MF configuration
10855 */
10856
10857 bp->mf_ov = 0;
10858 bp->mf_mode = 0;
10859 vn = BP_VN(bp);
10860
10861 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
10862 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10863 bp->common.shmem2_base, SHMEM2_RD(bp, size),
10864 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
10865
10866 if (SHMEM2_HAS(bp, mf_cfg_addr))
10867 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
10868 else
10869 bp->common.mf_cfg_base = bp->common.shmem_base +
10870 offsetof(struct shmem_region, func_mb) +
10871 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
10872 /*
10873 * get mf configuration:
10874 * 1. existence of MF configuration
10875 * 2. MAC address must be legal (check only upper bytes)
10876 * for Switch-Independent mode;
10877 * OVLAN must be legal for Switch-Dependent mode
10878 * 3. SF_MODE configures specific MF mode
10879 */
10880 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10881 /* get mf configuration */
10882 val = SHMEM_RD(bp,
10883 dev_info.shared_feature_config.config);
10884 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
10885
10886 switch (val) {
10887 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
10888 val = MF_CFG_RD(bp, func_mf_config[func].
10889 mac_upper);
10890 /* check for legal mac (upper bytes)*/
10891 if (val != 0xffff) {
10892 bp->mf_mode = MULTI_FUNCTION_SI;
10893 bp->mf_config[vn] = MF_CFG_RD(bp,
10894 func_mf_config[func].config);
10895 } else
10896 BNX2X_DEV_INFO("illegal MAC address for SI\n");
10897 break;
10898 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
10899 if ((!CHIP_IS_E1x(bp)) &&
10900 (MF_CFG_RD(bp, func_mf_config[func].
10901 mac_upper) != 0xffff) &&
10902 (SHMEM2_HAS(bp,
10903 afex_driver_support))) {
10904 bp->mf_mode = MULTI_FUNCTION_AFEX;
10905 bp->mf_config[vn] = MF_CFG_RD(bp,
10906 func_mf_config[func].config);
10907 } else {
10908 BNX2X_DEV_INFO("can not configure afex mode\n");
10909 }
10910 break;
10911 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
10912 /* get OV configuration */
10913 val = MF_CFG_RD(bp,
10914 func_mf_config[FUNC_0].e1hov_tag);
10915 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
10916
10917 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10918 bp->mf_mode = MULTI_FUNCTION_SD;
10919 bp->mf_config[vn] = MF_CFG_RD(bp,
10920 func_mf_config[func].config);
10921 } else
10922 BNX2X_DEV_INFO("illegal OV for SD\n");
10923 break;
10924 default:
10925 /* Unknown configuration: reset mf_config */
10926 bp->mf_config[vn] = 0;
10927 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
10928 }
10929 }
10930
10931 BNX2X_DEV_INFO("%s function mode\n",
10932 IS_MF(bp) ? "multi" : "single");
10933
10934 switch (bp->mf_mode) {
10935 case MULTI_FUNCTION_SD:
10936 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
10937 FUNC_MF_CFG_E1HOV_TAG_MASK;
10938 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10939 bp->mf_ov = val;
10940 bp->path_has_ovlan = true;
10941
10942 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
10943 func, bp->mf_ov, bp->mf_ov);
10944 } else {
10945 dev_err(&bp->pdev->dev,
10946 "No valid MF OV for func %d, aborting\n",
10947 func);
10948 return -EPERM;
10949 }
10950 break;
10951 case MULTI_FUNCTION_AFEX:
10952 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
10953 break;
10954 case MULTI_FUNCTION_SI:
10955 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
10956 func);
10957 break;
10958 default:
10959 if (vn) {
10960 dev_err(&bp->pdev->dev,
10961 "VN %d is in a single function mode, aborting\n",
10962 vn);
10963 return -EPERM;
10964 }
10965 break;
10966 }
10967
10968 /* check if other port on the path needs ovlan:
10969 * Since MF configuration is shared between ports
10970 * Possible mixed modes are only
10971 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
10972 */
10973 if (CHIP_MODE_IS_4_PORT(bp) &&
10974 !bp->path_has_ovlan &&
10975 !IS_MF(bp) &&
10976 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10977 u8 other_port = !BP_PORT(bp);
10978 u8 other_func = BP_PATH(bp) + 2*other_port;
10979 val = MF_CFG_RD(bp,
10980 func_mf_config[other_func].e1hov_tag);
10981 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
10982 bp->path_has_ovlan = true;
10983 }
10984 }
10985
10986 /* adjust igu_sb_cnt to MF for E1x */
10987 if (CHIP_IS_E1x(bp) && IS_MF(bp))
10988 bp->igu_sb_cnt /= E1HVN_MAX;
10989
10990 /* port info */
10991 bnx2x_get_port_hwinfo(bp);
10992
10993 /* Get MAC addresses */
10994 bnx2x_get_mac_hwinfo(bp);
10995
10996 bnx2x_get_cnic_info(bp);
10997
10998 return rc;
10999 }
11000
11001 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11002 {
11003 int cnt, i, block_end, rodi;
11004 char vpd_start[BNX2X_VPD_LEN+1];
11005 char str_id_reg[VENDOR_ID_LEN+1];
11006 char str_id_cap[VENDOR_ID_LEN+1];
11007 char *vpd_data;
11008 char *vpd_extended_data = NULL;
11009 u8 len;
11010
11011 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11012 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11013
11014 if (cnt < BNX2X_VPD_LEN)
11015 goto out_not_found;
11016
11017 /* VPD RO tag should be first tag after identifier string, hence
11018 * we should be able to find it in first BNX2X_VPD_LEN chars
11019 */
11020 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11021 PCI_VPD_LRDT_RO_DATA);
11022 if (i < 0)
11023 goto out_not_found;
11024
11025 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11026 pci_vpd_lrdt_size(&vpd_start[i]);
11027
11028 i += PCI_VPD_LRDT_TAG_SIZE;
11029
11030 if (block_end > BNX2X_VPD_LEN) {
11031 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11032 if (vpd_extended_data == NULL)
11033 goto out_not_found;
11034
11035 /* read rest of vpd image into vpd_extended_data */
11036 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11037 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11038 block_end - BNX2X_VPD_LEN,
11039 vpd_extended_data + BNX2X_VPD_LEN);
11040 if (cnt < (block_end - BNX2X_VPD_LEN))
11041 goto out_not_found;
11042 vpd_data = vpd_extended_data;
11043 } else
11044 vpd_data = vpd_start;
11045
11046 /* now vpd_data holds full vpd content in both cases */
11047
11048 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11049 PCI_VPD_RO_KEYWORD_MFR_ID);
11050 if (rodi < 0)
11051 goto out_not_found;
11052
11053 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11054
11055 if (len != VENDOR_ID_LEN)
11056 goto out_not_found;
11057
11058 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11059
11060 /* vendor specific info */
11061 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11062 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11063 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11064 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11065
11066 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11067 PCI_VPD_RO_KEYWORD_VENDOR0);
11068 if (rodi >= 0) {
11069 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11070
11071 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11072
11073 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11074 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11075 bp->fw_ver[len] = ' ';
11076 }
11077 }
11078 kfree(vpd_extended_data);
11079 return;
11080 }
11081 out_not_found:
11082 kfree(vpd_extended_data);
11083 return;
11084 }
11085
11086 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11087 {
11088 u32 flags = 0;
11089
11090 if (CHIP_REV_IS_FPGA(bp))
11091 SET_FLAGS(flags, MODE_FPGA);
11092 else if (CHIP_REV_IS_EMUL(bp))
11093 SET_FLAGS(flags, MODE_EMUL);
11094 else
11095 SET_FLAGS(flags, MODE_ASIC);
11096
11097 if (CHIP_MODE_IS_4_PORT(bp))
11098 SET_FLAGS(flags, MODE_PORT4);
11099 else
11100 SET_FLAGS(flags, MODE_PORT2);
11101
11102 if (CHIP_IS_E2(bp))
11103 SET_FLAGS(flags, MODE_E2);
11104 else if (CHIP_IS_E3(bp)) {
11105 SET_FLAGS(flags, MODE_E3);
11106 if (CHIP_REV(bp) == CHIP_REV_Ax)
11107 SET_FLAGS(flags, MODE_E3_A0);
11108 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11109 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11110 }
11111
11112 if (IS_MF(bp)) {
11113 SET_FLAGS(flags, MODE_MF);
11114 switch (bp->mf_mode) {
11115 case MULTI_FUNCTION_SD:
11116 SET_FLAGS(flags, MODE_MF_SD);
11117 break;
11118 case MULTI_FUNCTION_SI:
11119 SET_FLAGS(flags, MODE_MF_SI);
11120 break;
11121 case MULTI_FUNCTION_AFEX:
11122 SET_FLAGS(flags, MODE_MF_AFEX);
11123 break;
11124 }
11125 } else
11126 SET_FLAGS(flags, MODE_SF);
11127
11128 #if defined(__LITTLE_ENDIAN)
11129 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11130 #else /*(__BIG_ENDIAN)*/
11131 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11132 #endif
11133 INIT_MODE_FLAGS(bp) = flags;
11134 }
11135
11136 static int bnx2x_init_bp(struct bnx2x *bp)
11137 {
11138 int func;
11139 int rc;
11140
11141 mutex_init(&bp->port.phy_mutex);
11142 mutex_init(&bp->fw_mb_mutex);
11143 spin_lock_init(&bp->stats_lock);
11144
11145
11146 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11147 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11148 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11149 if (IS_PF(bp)) {
11150 rc = bnx2x_get_hwinfo(bp);
11151 if (rc)
11152 return rc;
11153 } else {
11154 random_ether_addr(bp->dev->dev_addr);
11155 }
11156
11157 bnx2x_set_modes_bitmap(bp);
11158
11159 rc = bnx2x_alloc_mem_bp(bp);
11160 if (rc)
11161 return rc;
11162
11163 bnx2x_read_fwinfo(bp);
11164
11165 func = BP_FUNC(bp);
11166
11167 /* need to reset chip if undi was active */
11168 if (IS_PF(bp) && !BP_NOMCP(bp)) {
11169 /* init fw_seq */
11170 bp->fw_seq =
11171 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11172 DRV_MSG_SEQ_NUMBER_MASK;
11173 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11174
11175 bnx2x_prev_unload(bp);
11176 }
11177
11178
11179 if (CHIP_REV_IS_FPGA(bp))
11180 dev_err(&bp->pdev->dev, "FPGA detected\n");
11181
11182 if (BP_NOMCP(bp) && (func == 0))
11183 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11184
11185 bp->disable_tpa = disable_tpa;
11186 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11187
11188 /* Set TPA flags */
11189 if (bp->disable_tpa) {
11190 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11191 bp->dev->features &= ~NETIF_F_LRO;
11192 } else {
11193 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11194 bp->dev->features |= NETIF_F_LRO;
11195 }
11196
11197 if (CHIP_IS_E1(bp))
11198 bp->dropless_fc = 0;
11199 else
11200 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11201
11202 bp->mrrs = mrrs;
11203
11204 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11205 if (IS_VF(bp))
11206 bp->rx_ring_size = MAX_RX_AVAIL;
11207
11208 /* make sure that the numbers are in the right granularity */
11209 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11210 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11211
11212 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11213
11214 init_timer(&bp->timer);
11215 bp->timer.expires = jiffies + bp->current_interval;
11216 bp->timer.data = (unsigned long) bp;
11217 bp->timer.function = bnx2x_timer;
11218
11219 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11220 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11221 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11222 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11223 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11224 bnx2x_dcbx_init_params(bp);
11225 } else {
11226 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11227 }
11228
11229 if (CHIP_IS_E1x(bp))
11230 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11231 else
11232 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11233
11234 /* multiple tx priority */
11235 if (IS_VF(bp))
11236 bp->max_cos = 1;
11237 else if (CHIP_IS_E1x(bp))
11238 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11239 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11240 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11241 else if (CHIP_IS_E3B0(bp))
11242 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11243 else
11244 BNX2X_ERR("unknown chip %x revision %x\n",
11245 CHIP_NUM(bp), CHIP_REV(bp));
11246 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11247
11248 /* We need at least one default status block for slow-path events,
11249 * second status block for the L2 queue, and a third status block for
11250 * CNIC if supproted.
11251 */
11252 if (CNIC_SUPPORT(bp))
11253 bp->min_msix_vec_cnt = 3;
11254 else
11255 bp->min_msix_vec_cnt = 2;
11256 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11257
11258 return rc;
11259 }
11260
11261
11262 /****************************************************************************
11263 * General service functions
11264 ****************************************************************************/
11265
11266 /*
11267 * net_device service functions
11268 */
11269
11270 /* called with rtnl_lock */
11271 static int bnx2x_open(struct net_device *dev)
11272 {
11273 struct bnx2x *bp = netdev_priv(dev);
11274 bool global = false;
11275 int other_engine = BP_PATH(bp) ? 0 : 1;
11276 bool other_load_status, load_status;
11277
11278 bp->stats_init = true;
11279
11280 netif_carrier_off(dev);
11281
11282 bnx2x_set_power_state(bp, PCI_D0);
11283
11284 /* If parity had happen during the unload, then attentions
11285 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11286 * want the first function loaded on the current engine to
11287 * complete the recovery.
11288 * Parity recovery is only relevant for PF driver.
11289 */
11290 if (IS_PF(bp)) {
11291 other_load_status = bnx2x_get_load_status(bp, other_engine);
11292 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11293 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11294 bnx2x_chk_parity_attn(bp, &global, true)) {
11295 do {
11296 /* If there are attentions and they are in a
11297 * global blocks, set the GLOBAL_RESET bit
11298 * regardless whether it will be this function
11299 * that will complete the recovery or not.
11300 */
11301 if (global)
11302 bnx2x_set_reset_global(bp);
11303
11304 /* Only the first function on the current
11305 * engine should try to recover in open. In case
11306 * of attentions in global blocks only the first
11307 * in the chip should try to recover.
11308 */
11309 if ((!load_status &&
11310 (!global || !other_load_status)) &&
11311 bnx2x_trylock_leader_lock(bp) &&
11312 !bnx2x_leader_reset(bp)) {
11313 netdev_info(bp->dev,
11314 "Recovered in open\n");
11315 break;
11316 }
11317
11318 /* recovery has failed... */
11319 bnx2x_set_power_state(bp, PCI_D3hot);
11320 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11321
11322 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11323 "If you still see this message after a few retries then power cycle is required.\n");
11324
11325 return -EAGAIN;
11326 } while (0);
11327 }
11328 }
11329
11330 bp->recovery_state = BNX2X_RECOVERY_DONE;
11331 return bnx2x_nic_load(bp, LOAD_OPEN);
11332 }
11333
11334 /* called with rtnl_lock */
11335 static int bnx2x_close(struct net_device *dev)
11336 {
11337 struct bnx2x *bp = netdev_priv(dev);
11338
11339 /* Unload the driver, release IRQs */
11340 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11341
11342 /* Power off */
11343 bnx2x_set_power_state(bp, PCI_D3hot);
11344
11345 return 0;
11346 }
11347
11348 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11349 struct bnx2x_mcast_ramrod_params *p)
11350 {
11351 int mc_count = netdev_mc_count(bp->dev);
11352 struct bnx2x_mcast_list_elem *mc_mac =
11353 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11354 struct netdev_hw_addr *ha;
11355
11356 if (!mc_mac)
11357 return -ENOMEM;
11358
11359 INIT_LIST_HEAD(&p->mcast_list);
11360
11361 netdev_for_each_mc_addr(ha, bp->dev) {
11362 mc_mac->mac = bnx2x_mc_addr(ha);
11363 list_add_tail(&mc_mac->link, &p->mcast_list);
11364 mc_mac++;
11365 }
11366
11367 p->mcast_list_len = mc_count;
11368
11369 return 0;
11370 }
11371
11372 static void bnx2x_free_mcast_macs_list(
11373 struct bnx2x_mcast_ramrod_params *p)
11374 {
11375 struct bnx2x_mcast_list_elem *mc_mac =
11376 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11377 link);
11378
11379 WARN_ON(!mc_mac);
11380 kfree(mc_mac);
11381 }
11382
11383 /**
11384 * bnx2x_set_uc_list - configure a new unicast MACs list.
11385 *
11386 * @bp: driver handle
11387 *
11388 * We will use zero (0) as a MAC type for these MACs.
11389 */
11390 static int bnx2x_set_uc_list(struct bnx2x *bp)
11391 {
11392 int rc;
11393 struct net_device *dev = bp->dev;
11394 struct netdev_hw_addr *ha;
11395 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11396 unsigned long ramrod_flags = 0;
11397
11398 /* First schedule a cleanup up of old configuration */
11399 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11400 if (rc < 0) {
11401 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11402 return rc;
11403 }
11404
11405 netdev_for_each_uc_addr(ha, dev) {
11406 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11407 BNX2X_UC_LIST_MAC, &ramrod_flags);
11408 if (rc == -EEXIST) {
11409 DP(BNX2X_MSG_SP,
11410 "Failed to schedule ADD operations: %d\n", rc);
11411 /* do not treat adding same MAC as error */
11412 rc = 0;
11413
11414 } else if (rc < 0) {
11415
11416 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11417 rc);
11418 return rc;
11419 }
11420 }
11421
11422 /* Execute the pending commands */
11423 __set_bit(RAMROD_CONT, &ramrod_flags);
11424 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11425 BNX2X_UC_LIST_MAC, &ramrod_flags);
11426 }
11427
11428 static int bnx2x_set_mc_list(struct bnx2x *bp)
11429 {
11430 struct net_device *dev = bp->dev;
11431 struct bnx2x_mcast_ramrod_params rparam = {NULL};
11432 int rc = 0;
11433
11434 rparam.mcast_obj = &bp->mcast_obj;
11435
11436 /* first, clear all configured multicast MACs */
11437 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11438 if (rc < 0) {
11439 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11440 return rc;
11441 }
11442
11443 /* then, configure a new MACs list */
11444 if (netdev_mc_count(dev)) {
11445 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11446 if (rc) {
11447 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11448 rc);
11449 return rc;
11450 }
11451
11452 /* Now add the new MACs */
11453 rc = bnx2x_config_mcast(bp, &rparam,
11454 BNX2X_MCAST_CMD_ADD);
11455 if (rc < 0)
11456 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11457 rc);
11458
11459 bnx2x_free_mcast_macs_list(&rparam);
11460 }
11461
11462 return rc;
11463 }
11464
11465
11466 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11467 void bnx2x_set_rx_mode(struct net_device *dev)
11468 {
11469 struct bnx2x *bp = netdev_priv(dev);
11470 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11471
11472 if (bp->state != BNX2X_STATE_OPEN) {
11473 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11474 return;
11475 }
11476
11477 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11478
11479 if (dev->flags & IFF_PROMISC)
11480 rx_mode = BNX2X_RX_MODE_PROMISC;
11481 else if ((dev->flags & IFF_ALLMULTI) ||
11482 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11483 CHIP_IS_E1(bp)))
11484 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11485 else {
11486 if (IS_PF(bp)) {
11487 /* some multicasts */
11488 if (bnx2x_set_mc_list(bp) < 0)
11489 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11490
11491 if (bnx2x_set_uc_list(bp) < 0)
11492 rx_mode = BNX2X_RX_MODE_PROMISC;
11493 } else {
11494 /* configuring mcast to a vf involves sleeping (when we
11495 * wait for the pf's response). Since this function is
11496 * called from non sleepable context we must schedule
11497 * a work item for this purpose
11498 */
11499 smp_mb__before_clear_bit();
11500 set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11501 &bp->sp_rtnl_state);
11502 smp_mb__after_clear_bit();
11503 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11504 }
11505 }
11506
11507 bp->rx_mode = rx_mode;
11508 /* handle ISCSI SD mode */
11509 if (IS_MF_ISCSI_SD(bp))
11510 bp->rx_mode = BNX2X_RX_MODE_NONE;
11511
11512 /* Schedule the rx_mode command */
11513 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11514 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11515 return;
11516 }
11517
11518 if (IS_PF(bp)) {
11519 bnx2x_set_storm_rx_mode(bp);
11520 } else {
11521 /* configuring rx mode to storms in a vf involves sleeping (when
11522 * we wait for the pf's response). Since this function is
11523 * called from non sleepable context we must schedule
11524 * a work item for this purpose
11525 */
11526 smp_mb__before_clear_bit();
11527 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
11528 &bp->sp_rtnl_state);
11529 smp_mb__after_clear_bit();
11530 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11531 }
11532 }
11533
11534 /* called with rtnl_lock */
11535 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11536 int devad, u16 addr)
11537 {
11538 struct bnx2x *bp = netdev_priv(netdev);
11539 u16 value;
11540 int rc;
11541
11542 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11543 prtad, devad, addr);
11544
11545 /* The HW expects different devad if CL22 is used */
11546 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11547
11548 bnx2x_acquire_phy_lock(bp);
11549 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11550 bnx2x_release_phy_lock(bp);
11551 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11552
11553 if (!rc)
11554 rc = value;
11555 return rc;
11556 }
11557
11558 /* called with rtnl_lock */
11559 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11560 u16 addr, u16 value)
11561 {
11562 struct bnx2x *bp = netdev_priv(netdev);
11563 int rc;
11564
11565 DP(NETIF_MSG_LINK,
11566 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11567 prtad, devad, addr, value);
11568
11569 /* The HW expects different devad if CL22 is used */
11570 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11571
11572 bnx2x_acquire_phy_lock(bp);
11573 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11574 bnx2x_release_phy_lock(bp);
11575 return rc;
11576 }
11577
11578 /* called with rtnl_lock */
11579 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11580 {
11581 struct bnx2x *bp = netdev_priv(dev);
11582 struct mii_ioctl_data *mdio = if_mii(ifr);
11583
11584 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11585 mdio->phy_id, mdio->reg_num, mdio->val_in);
11586
11587 if (!netif_running(dev))
11588 return -EAGAIN;
11589
11590 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11591 }
11592
11593 #ifdef CONFIG_NET_POLL_CONTROLLER
11594 static void poll_bnx2x(struct net_device *dev)
11595 {
11596 struct bnx2x *bp = netdev_priv(dev);
11597 int i;
11598
11599 for_each_eth_queue(bp, i) {
11600 struct bnx2x_fastpath *fp = &bp->fp[i];
11601 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11602 }
11603 }
11604 #endif
11605
11606 static int bnx2x_validate_addr(struct net_device *dev)
11607 {
11608 struct bnx2x *bp = netdev_priv(dev);
11609
11610 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11611 BNX2X_ERR("Non-valid Ethernet address\n");
11612 return -EADDRNOTAVAIL;
11613 }
11614 return 0;
11615 }
11616
11617 static const struct net_device_ops bnx2x_netdev_ops = {
11618 .ndo_open = bnx2x_open,
11619 .ndo_stop = bnx2x_close,
11620 .ndo_start_xmit = bnx2x_start_xmit,
11621 .ndo_select_queue = bnx2x_select_queue,
11622 .ndo_set_rx_mode = bnx2x_set_rx_mode,
11623 .ndo_set_mac_address = bnx2x_change_mac_addr,
11624 .ndo_validate_addr = bnx2x_validate_addr,
11625 .ndo_do_ioctl = bnx2x_ioctl,
11626 .ndo_change_mtu = bnx2x_change_mtu,
11627 .ndo_fix_features = bnx2x_fix_features,
11628 .ndo_set_features = bnx2x_set_features,
11629 .ndo_tx_timeout = bnx2x_tx_timeout,
11630 #ifdef CONFIG_NET_POLL_CONTROLLER
11631 .ndo_poll_controller = poll_bnx2x,
11632 #endif
11633 .ndo_setup_tc = bnx2x_setup_tc,
11634
11635 #ifdef NETDEV_FCOE_WWNN
11636 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
11637 #endif
11638 };
11639
11640 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11641 {
11642 struct device *dev = &bp->pdev->dev;
11643
11644 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11645 bp->flags |= USING_DAC_FLAG;
11646 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11647 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11648 return -EIO;
11649 }
11650 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11651 dev_err(dev, "System does not support DMA, aborting\n");
11652 return -EIO;
11653 }
11654
11655 return 0;
11656 }
11657
11658 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
11659 struct net_device *dev, unsigned long board_type)
11660 {
11661 int rc;
11662 u32 pci_cfg_dword;
11663 bool chip_is_e1x = (board_type == BCM57710 ||
11664 board_type == BCM57711 ||
11665 board_type == BCM57711E);
11666
11667 SET_NETDEV_DEV(dev, &pdev->dev);
11668
11669 bp->dev = dev;
11670 bp->pdev = pdev;
11671
11672 rc = pci_enable_device(pdev);
11673 if (rc) {
11674 dev_err(&bp->pdev->dev,
11675 "Cannot enable PCI device, aborting\n");
11676 goto err_out;
11677 }
11678
11679 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11680 dev_err(&bp->pdev->dev,
11681 "Cannot find PCI device base address, aborting\n");
11682 rc = -ENODEV;
11683 goto err_out_disable;
11684 }
11685
11686 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11687 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
11688 rc = -ENODEV;
11689 goto err_out_disable;
11690 }
11691
11692 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
11693 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
11694 PCICFG_REVESION_ID_ERROR_VAL) {
11695 pr_err("PCI device error, probably due to fan failure, aborting\n");
11696 rc = -ENODEV;
11697 goto err_out_disable;
11698 }
11699
11700 if (atomic_read(&pdev->enable_cnt) == 1) {
11701 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11702 if (rc) {
11703 dev_err(&bp->pdev->dev,
11704 "Cannot obtain PCI resources, aborting\n");
11705 goto err_out_disable;
11706 }
11707
11708 pci_set_master(pdev);
11709 pci_save_state(pdev);
11710 }
11711
11712 if (IS_PF(bp)) {
11713 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11714 if (bp->pm_cap == 0) {
11715 dev_err(&bp->pdev->dev,
11716 "Cannot find power management capability, aborting\n");
11717 rc = -EIO;
11718 goto err_out_release;
11719 }
11720 }
11721
11722 if (!pci_is_pcie(pdev)) {
11723 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11724 rc = -EIO;
11725 goto err_out_release;
11726 }
11727
11728 rc = bnx2x_set_coherency_mask(bp);
11729 if (rc)
11730 goto err_out_release;
11731
11732 dev->mem_start = pci_resource_start(pdev, 0);
11733 dev->base_addr = dev->mem_start;
11734 dev->mem_end = pci_resource_end(pdev, 0);
11735
11736 dev->irq = pdev->irq;
11737
11738 bp->regview = pci_ioremap_bar(pdev, 0);
11739 if (!bp->regview) {
11740 dev_err(&bp->pdev->dev,
11741 "Cannot map register space, aborting\n");
11742 rc = -ENOMEM;
11743 goto err_out_release;
11744 }
11745
11746 /* In E1/E1H use pci device function given by kernel.
11747 * In E2/E3 read physical function from ME register since these chips
11748 * support Physical Device Assignment where kernel BDF maybe arbitrary
11749 * (depending on hypervisor).
11750 */
11751 if (chip_is_e1x)
11752 bp->pf_num = PCI_FUNC(pdev->devfn);
11753 else {/* chip is E2/3*/
11754 pci_read_config_dword(bp->pdev,
11755 PCICFG_ME_REGISTER, &pci_cfg_dword);
11756 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11757 ME_REG_ABS_PF_NUM_SHIFT);
11758 }
11759 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11760
11761 bnx2x_set_power_state(bp, PCI_D0);
11762
11763 /* clean indirect addresses */
11764 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11765 PCICFG_VENDOR_ID_OFFSET);
11766 /*
11767 * Clean the following indirect addresses for all functions since it
11768 * is not used by the driver.
11769 */
11770 if (IS_PF(bp)) {
11771 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11772 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11773 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11774 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11775
11776 if (chip_is_e1x) {
11777 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11778 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11779 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11780 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11781 }
11782
11783 /* Enable internal target-read (in case we are probed after PF
11784 * FLR). Must be done prior to any BAR read access. Only for
11785 * 57712 and up
11786 */
11787 if (!chip_is_e1x)
11788 REG_WR(bp,
11789 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11790 }
11791
11792 dev->watchdog_timeo = TX_TIMEOUT;
11793
11794 dev->netdev_ops = &bnx2x_netdev_ops;
11795 bnx2x_set_ethtool_ops(dev);
11796
11797 dev->priv_flags |= IFF_UNICAST_FLT;
11798
11799 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11800 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11801 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11802 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
11803
11804 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11805 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11806
11807 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
11808 if (bp->flags & USING_DAC_FLAG)
11809 dev->features |= NETIF_F_HIGHDMA;
11810
11811 /* Add Loopback capability to the device */
11812 dev->hw_features |= NETIF_F_LOOPBACK;
11813
11814 #ifdef BCM_DCBNL
11815 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11816 #endif
11817
11818 /* get_port_hwinfo() will set prtad and mmds properly */
11819 bp->mdio.prtad = MDIO_PRTAD_NONE;
11820 bp->mdio.mmds = 0;
11821 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11822 bp->mdio.dev = dev;
11823 bp->mdio.mdio_read = bnx2x_mdio_read;
11824 bp->mdio.mdio_write = bnx2x_mdio_write;
11825
11826 return 0;
11827
11828 err_out_release:
11829 if (atomic_read(&pdev->enable_cnt) == 1)
11830 pci_release_regions(pdev);
11831
11832 err_out_disable:
11833 pci_disable_device(pdev);
11834 pci_set_drvdata(pdev, NULL);
11835
11836 err_out:
11837 return rc;
11838 }
11839
11840 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed)
11841 {
11842 u32 val = 0;
11843
11844 pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
11845 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
11846
11847 /* return value of 1=2.5GHz 2=5GHz */
11848 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
11849 }
11850
11851 static int bnx2x_check_firmware(struct bnx2x *bp)
11852 {
11853 const struct firmware *firmware = bp->firmware;
11854 struct bnx2x_fw_file_hdr *fw_hdr;
11855 struct bnx2x_fw_file_section *sections;
11856 u32 offset, len, num_ops;
11857 u16 *ops_offsets;
11858 int i;
11859 const u8 *fw_ver;
11860
11861 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
11862 BNX2X_ERR("Wrong FW size\n");
11863 return -EINVAL;
11864 }
11865
11866 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
11867 sections = (struct bnx2x_fw_file_section *)fw_hdr;
11868
11869 /* Make sure none of the offsets and sizes make us read beyond
11870 * the end of the firmware data */
11871 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
11872 offset = be32_to_cpu(sections[i].offset);
11873 len = be32_to_cpu(sections[i].len);
11874 if (offset + len > firmware->size) {
11875 BNX2X_ERR("Section %d length is out of bounds\n", i);
11876 return -EINVAL;
11877 }
11878 }
11879
11880 /* Likewise for the init_ops offsets */
11881 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
11882 ops_offsets = (u16 *)(firmware->data + offset);
11883 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
11884
11885 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
11886 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
11887 BNX2X_ERR("Section offset %d is out of bounds\n", i);
11888 return -EINVAL;
11889 }
11890 }
11891
11892 /* Check FW version */
11893 offset = be32_to_cpu(fw_hdr->fw_version.offset);
11894 fw_ver = firmware->data + offset;
11895 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
11896 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
11897 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
11898 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
11899 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
11900 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
11901 BCM_5710_FW_MAJOR_VERSION,
11902 BCM_5710_FW_MINOR_VERSION,
11903 BCM_5710_FW_REVISION_VERSION,
11904 BCM_5710_FW_ENGINEERING_VERSION);
11905 return -EINVAL;
11906 }
11907
11908 return 0;
11909 }
11910
11911 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11912 {
11913 const __be32 *source = (const __be32 *)_source;
11914 u32 *target = (u32 *)_target;
11915 u32 i;
11916
11917 for (i = 0; i < n/4; i++)
11918 target[i] = be32_to_cpu(source[i]);
11919 }
11920
11921 /*
11922 Ops array is stored in the following format:
11923 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
11924 */
11925 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
11926 {
11927 const __be32 *source = (const __be32 *)_source;
11928 struct raw_op *target = (struct raw_op *)_target;
11929 u32 i, j, tmp;
11930
11931 for (i = 0, j = 0; i < n/8; i++, j += 2) {
11932 tmp = be32_to_cpu(source[j]);
11933 target[i].op = (tmp >> 24) & 0xff;
11934 target[i].offset = tmp & 0xffffff;
11935 target[i].raw_data = be32_to_cpu(source[j + 1]);
11936 }
11937 }
11938
11939 /* IRO array is stored in the following format:
11940 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
11941 */
11942 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
11943 {
11944 const __be32 *source = (const __be32 *)_source;
11945 struct iro *target = (struct iro *)_target;
11946 u32 i, j, tmp;
11947
11948 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
11949 target[i].base = be32_to_cpu(source[j]);
11950 j++;
11951 tmp = be32_to_cpu(source[j]);
11952 target[i].m1 = (tmp >> 16) & 0xffff;
11953 target[i].m2 = tmp & 0xffff;
11954 j++;
11955 tmp = be32_to_cpu(source[j]);
11956 target[i].m3 = (tmp >> 16) & 0xffff;
11957 target[i].size = tmp & 0xffff;
11958 j++;
11959 }
11960 }
11961
11962 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11963 {
11964 const __be16 *source = (const __be16 *)_source;
11965 u16 *target = (u16 *)_target;
11966 u32 i;
11967
11968 for (i = 0; i < n/2; i++)
11969 target[i] = be16_to_cpu(source[i]);
11970 }
11971
11972 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
11973 do { \
11974 u32 len = be32_to_cpu(fw_hdr->arr.len); \
11975 bp->arr = kmalloc(len, GFP_KERNEL); \
11976 if (!bp->arr) \
11977 goto lbl; \
11978 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
11979 (u8 *)bp->arr, len); \
11980 } while (0)
11981
11982 static int bnx2x_init_firmware(struct bnx2x *bp)
11983 {
11984 const char *fw_file_name;
11985 struct bnx2x_fw_file_hdr *fw_hdr;
11986 int rc;
11987
11988 if (bp->firmware)
11989 return 0;
11990
11991 if (CHIP_IS_E1(bp))
11992 fw_file_name = FW_FILE_NAME_E1;
11993 else if (CHIP_IS_E1H(bp))
11994 fw_file_name = FW_FILE_NAME_E1H;
11995 else if (!CHIP_IS_E1x(bp))
11996 fw_file_name = FW_FILE_NAME_E2;
11997 else {
11998 BNX2X_ERR("Unsupported chip revision\n");
11999 return -EINVAL;
12000 }
12001 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12002
12003 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12004 if (rc) {
12005 BNX2X_ERR("Can't load firmware file %s\n",
12006 fw_file_name);
12007 goto request_firmware_exit;
12008 }
12009
12010 rc = bnx2x_check_firmware(bp);
12011 if (rc) {
12012 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12013 goto request_firmware_exit;
12014 }
12015
12016 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12017
12018 /* Initialize the pointers to the init arrays */
12019 /* Blob */
12020 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12021
12022 /* Opcodes */
12023 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12024
12025 /* Offsets */
12026 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12027 be16_to_cpu_n);
12028
12029 /* STORMs firmware */
12030 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12031 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12032 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12033 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12034 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12035 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12036 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12037 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12038 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12039 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12040 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12041 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12042 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12043 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12044 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12045 be32_to_cpu(fw_hdr->csem_pram_data.offset);
12046 /* IRO */
12047 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12048
12049 return 0;
12050
12051 iro_alloc_err:
12052 kfree(bp->init_ops_offsets);
12053 init_offsets_alloc_err:
12054 kfree(bp->init_ops);
12055 init_ops_alloc_err:
12056 kfree(bp->init_data);
12057 request_firmware_exit:
12058 release_firmware(bp->firmware);
12059 bp->firmware = NULL;
12060
12061 return rc;
12062 }
12063
12064 static void bnx2x_release_firmware(struct bnx2x *bp)
12065 {
12066 kfree(bp->init_ops_offsets);
12067 kfree(bp->init_ops);
12068 kfree(bp->init_data);
12069 release_firmware(bp->firmware);
12070 bp->firmware = NULL;
12071 }
12072
12073
12074 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12075 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12076 .init_hw_cmn = bnx2x_init_hw_common,
12077 .init_hw_port = bnx2x_init_hw_port,
12078 .init_hw_func = bnx2x_init_hw_func,
12079
12080 .reset_hw_cmn = bnx2x_reset_common,
12081 .reset_hw_port = bnx2x_reset_port,
12082 .reset_hw_func = bnx2x_reset_func,
12083
12084 .gunzip_init = bnx2x_gunzip_init,
12085 .gunzip_end = bnx2x_gunzip_end,
12086
12087 .init_fw = bnx2x_init_firmware,
12088 .release_fw = bnx2x_release_firmware,
12089 };
12090
12091 void bnx2x__init_func_obj(struct bnx2x *bp)
12092 {
12093 /* Prepare DMAE related driver resources */
12094 bnx2x_setup_dmae(bp);
12095
12096 bnx2x_init_func_obj(bp, &bp->func_obj,
12097 bnx2x_sp(bp, func_rdata),
12098 bnx2x_sp_mapping(bp, func_rdata),
12099 bnx2x_sp(bp, func_afex_rdata),
12100 bnx2x_sp_mapping(bp, func_afex_rdata),
12101 &bnx2x_func_sp_drv);
12102 }
12103
12104 /* must be called after sriov-enable */
12105 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12106 {
12107 int cid_count = BNX2X_L2_MAX_CID(bp);
12108
12109 if (CNIC_SUPPORT(bp))
12110 cid_count += CNIC_CID_MAX;
12111 return roundup(cid_count, QM_CID_ROUND);
12112 }
12113
12114 /**
12115 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12116 *
12117 * @dev: pci device
12118 *
12119 */
12120 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
12121 int cnic_cnt, bool is_vf)
12122 {
12123 int pos, index;
12124 u16 control = 0;
12125
12126 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
12127
12128 /*
12129 * If MSI-X is not supported - return number of SBs needed to support
12130 * one fast path queue: one FP queue + SB for CNIC
12131 */
12132 if (!pos) {
12133 dev_info(&pdev->dev, "no msix capability found\n");
12134 return 1 + cnic_cnt;
12135 }
12136 dev_info(&pdev->dev, "msix capability found\n");
12137
12138 /*
12139 * The value in the PCI configuration space is the index of the last
12140 * entry, namely one less than the actual size of the table, which is
12141 * exactly what we want to return from this function: number of all SBs
12142 * without the default SB.
12143 * For VFs there is no default SB, then we return (index+1).
12144 */
12145 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
12146
12147 index = control & PCI_MSIX_FLAGS_QSIZE;
12148
12149 return is_vf ? index + 1 : index;
12150 }
12151
12152 static int set_max_cos_est(int chip_id)
12153 {
12154 switch (chip_id) {
12155 case BCM57710:
12156 case BCM57711:
12157 case BCM57711E:
12158 return BNX2X_MULTI_TX_COS_E1X;
12159 case BCM57712:
12160 case BCM57712_MF:
12161 case BCM57712_VF:
12162 return BNX2X_MULTI_TX_COS_E2_E3A0;
12163 case BCM57800:
12164 case BCM57800_MF:
12165 case BCM57800_VF:
12166 case BCM57810:
12167 case BCM57810_MF:
12168 case BCM57840_4_10:
12169 case BCM57840_2_20:
12170 case BCM57840_O:
12171 case BCM57840_MFO:
12172 case BCM57810_VF:
12173 case BCM57840_MF:
12174 case BCM57840_VF:
12175 case BCM57811:
12176 case BCM57811_MF:
12177 case BCM57811_VF:
12178 return BNX2X_MULTI_TX_COS_E3B0;
12179 return 1;
12180 default:
12181 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12182 return -ENODEV;
12183 }
12184 }
12185
12186 static int set_is_vf(int chip_id)
12187 {
12188 switch (chip_id) {
12189 case BCM57712_VF:
12190 case BCM57800_VF:
12191 case BCM57810_VF:
12192 case BCM57840_VF:
12193 case BCM57811_VF:
12194 return true;
12195 default:
12196 return false;
12197 }
12198 }
12199
12200 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12201
12202 static int bnx2x_init_one(struct pci_dev *pdev,
12203 const struct pci_device_id *ent)
12204 {
12205 struct net_device *dev = NULL;
12206 struct bnx2x *bp;
12207 int pcie_width, pcie_speed;
12208 int rc, max_non_def_sbs;
12209 int rx_count, tx_count, rss_count, doorbell_size;
12210 int max_cos_est;
12211 bool is_vf;
12212 int cnic_cnt;
12213
12214 /* An estimated maximum supported CoS number according to the chip
12215 * version.
12216 * We will try to roughly estimate the maximum number of CoSes this chip
12217 * may support in order to minimize the memory allocated for Tx
12218 * netdev_queue's. This number will be accurately calculated during the
12219 * initialization of bp->max_cos based on the chip versions AND chip
12220 * revision in the bnx2x_init_bp().
12221 */
12222 max_cos_est = set_max_cos_est(ent->driver_data);
12223 if (max_cos_est < 0)
12224 return max_cos_est;
12225 is_vf = set_is_vf(ent->driver_data);
12226 cnic_cnt = is_vf ? 0 : 1;
12227
12228 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf);
12229
12230 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12231 rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt;
12232
12233 if (rss_count < 1)
12234 return -EINVAL;
12235
12236 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12237 rx_count = rss_count + cnic_cnt;
12238
12239 /* Maximum number of netdev Tx queues:
12240 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
12241 */
12242 tx_count = rss_count * max_cos_est + cnic_cnt;
12243
12244 /* dev zeroed in init_etherdev */
12245 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12246 if (!dev)
12247 return -ENOMEM;
12248
12249 bp = netdev_priv(dev);
12250
12251 bp->flags = 0;
12252 if (is_vf)
12253 bp->flags |= IS_VF_FLAG;
12254
12255 bp->igu_sb_cnt = max_non_def_sbs;
12256 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12257 bp->msg_enable = debug;
12258 bp->cnic_support = cnic_cnt;
12259 bp->cnic_probe = bnx2x_cnic_probe;
12260
12261 pci_set_drvdata(pdev, dev);
12262
12263 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12264 if (rc < 0) {
12265 free_netdev(dev);
12266 return rc;
12267 }
12268
12269 BNX2X_DEV_INFO("This is a %s function\n",
12270 IS_PF(bp) ? "physical" : "virtual");
12271 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12272 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12273 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12274 tx_count, rx_count);
12275
12276 rc = bnx2x_init_bp(bp);
12277 if (rc)
12278 goto init_one_exit;
12279
12280 /* Map doorbells here as we need the real value of bp->max_cos which
12281 * is initialized in bnx2x_init_bp() to determine the number of
12282 * l2 connections.
12283 */
12284 if (IS_VF(bp)) {
12285 /* vf doorbells are embedded within the regview */
12286 bp->doorbells = bp->regview + PXP_VF_ADDR_DB_START;
12287
12288 /* allocate vf2pf mailbox for vf to pf channel */
12289 BNX2X_PCI_ALLOC(bp->vf2pf_mbox, &bp->vf2pf_mbox_mapping,
12290 sizeof(struct bnx2x_vf_mbx_msg));
12291 } else {
12292 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12293 if (doorbell_size > pci_resource_len(pdev, 2)) {
12294 dev_err(&bp->pdev->dev,
12295 "Cannot map doorbells, bar size too small, aborting\n");
12296 rc = -ENOMEM;
12297 goto init_one_exit;
12298 }
12299 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12300 doorbell_size);
12301 }
12302 if (!bp->doorbells) {
12303 dev_err(&bp->pdev->dev,
12304 "Cannot map doorbell space, aborting\n");
12305 rc = -ENOMEM;
12306 goto init_one_exit;
12307 }
12308
12309 if (IS_VF(bp)) {
12310 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12311 if (rc)
12312 goto init_one_exit;
12313 }
12314
12315 /* calc qm_cid_count */
12316 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12317 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12318
12319 /* disable FCOE L2 queue for E1x*/
12320 if (CHIP_IS_E1x(bp))
12321 bp->flags |= NO_FCOE_FLAG;
12322
12323 /* disable FCOE for 57840 device, until FW supports it */
12324 switch (ent->driver_data) {
12325 case BCM57840_O:
12326 case BCM57840_4_10:
12327 case BCM57840_2_20:
12328 case BCM57840_MFO:
12329 case BCM57840_MF:
12330 bp->flags |= NO_FCOE_FLAG;
12331 }
12332
12333 /* Set bp->num_queues for MSI-X mode*/
12334 bnx2x_set_num_queues(bp);
12335
12336 /* Configure interrupt mode: try to enable MSI-X/MSI if
12337 * needed.
12338 */
12339 rc = bnx2x_set_int_mode(bp);
12340 if (rc) {
12341 dev_err(&pdev->dev, "Cannot set interrupts\n");
12342 goto init_one_exit;
12343 }
12344
12345 /* register the net device */
12346 rc = register_netdev(dev);
12347 if (rc) {
12348 dev_err(&pdev->dev, "Cannot register net device\n");
12349 goto init_one_exit;
12350 }
12351 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12352
12353
12354 if (!NO_FCOE(bp)) {
12355 /* Add storage MAC address */
12356 rtnl_lock();
12357 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12358 rtnl_unlock();
12359 }
12360
12361 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12362 BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12363 pcie_width, pcie_speed);
12364
12365 BNX2X_DEV_INFO(
12366 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12367 board_info[ent->driver_data].name,
12368 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12369 pcie_width,
12370 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
12371 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
12372 "5GHz (Gen2)" : "2.5GHz",
12373 dev->base_addr, bp->pdev->irq, dev->dev_addr);
12374
12375 return 0;
12376
12377 alloc_mem_err:
12378 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping,
12379 sizeof(struct bnx2x_vf_mbx_msg));
12380 rc = -ENOMEM;
12381
12382 init_one_exit:
12383 if (bp->regview)
12384 iounmap(bp->regview);
12385
12386 if (IS_PF(bp) && bp->doorbells)
12387 iounmap(bp->doorbells);
12388
12389 free_netdev(dev);
12390
12391 if (atomic_read(&pdev->enable_cnt) == 1)
12392 pci_release_regions(pdev);
12393
12394 pci_disable_device(pdev);
12395 pci_set_drvdata(pdev, NULL);
12396
12397 return rc;
12398 }
12399
12400 static void bnx2x_remove_one(struct pci_dev *pdev)
12401 {
12402 struct net_device *dev = pci_get_drvdata(pdev);
12403 struct bnx2x *bp;
12404
12405 if (!dev) {
12406 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12407 return;
12408 }
12409 bp = netdev_priv(dev);
12410
12411 /* Delete storage MAC address */
12412 if (!NO_FCOE(bp)) {
12413 rtnl_lock();
12414 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12415 rtnl_unlock();
12416 }
12417
12418 #ifdef BCM_DCBNL
12419 /* Delete app tlvs from dcbnl */
12420 bnx2x_dcbnl_update_applist(bp, true);
12421 #endif
12422
12423 unregister_netdev(dev);
12424
12425 /* Power on: we can't let PCI layer write to us while we are in D3 */
12426 if (IS_PF(bp))
12427 bnx2x_set_power_state(bp, PCI_D0);
12428
12429 /* Disable MSI/MSI-X */
12430 bnx2x_disable_msi(bp);
12431
12432 /* Power off */
12433 if (IS_PF(bp))
12434 bnx2x_set_power_state(bp, PCI_D3hot);
12435
12436 /* Make sure RESET task is not scheduled before continuing */
12437 cancel_delayed_work_sync(&bp->sp_rtnl_task);
12438 /* send message via vfpf channel to release the resources of this vf */
12439 if (IS_VF(bp))
12440 bnx2x_vfpf_release(bp);
12441
12442 if (bp->regview)
12443 iounmap(bp->regview);
12444
12445 /* for vf doorbells are part of the regview and were unmapped along with
12446 * it. FW is only loaded by PF.
12447 */
12448 if (IS_PF(bp)) {
12449 if (bp->doorbells)
12450 iounmap(bp->doorbells);
12451
12452 bnx2x_release_firmware(bp);
12453 }
12454 bnx2x_free_mem_bp(bp);
12455
12456 free_netdev(dev);
12457
12458 if (atomic_read(&pdev->enable_cnt) == 1)
12459 pci_release_regions(pdev);
12460
12461 pci_disable_device(pdev);
12462 pci_set_drvdata(pdev, NULL);
12463 }
12464
12465 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12466 {
12467 int i;
12468
12469 bp->state = BNX2X_STATE_ERROR;
12470
12471 bp->rx_mode = BNX2X_RX_MODE_NONE;
12472
12473 if (CNIC_LOADED(bp))
12474 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12475
12476 /* Stop Tx */
12477 bnx2x_tx_disable(bp);
12478
12479 bnx2x_netif_stop(bp, 0);
12480 /* Delete all NAPI objects */
12481 bnx2x_del_all_napi(bp);
12482 if (CNIC_LOADED(bp))
12483 bnx2x_del_all_napi_cnic(bp);
12484
12485 del_timer_sync(&bp->timer);
12486
12487 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
12488
12489 /* Release IRQs */
12490 bnx2x_free_irq(bp);
12491
12492 /* Free SKBs, SGEs, TPA pool and driver internals */
12493 bnx2x_free_skbs(bp);
12494
12495 for_each_rx_queue(bp, i)
12496 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12497
12498 bnx2x_free_mem(bp);
12499
12500 bp->state = BNX2X_STATE_CLOSED;
12501
12502 netif_carrier_off(bp->dev);
12503
12504 return 0;
12505 }
12506
12507 static void bnx2x_eeh_recover(struct bnx2x *bp)
12508 {
12509 u32 val;
12510
12511 mutex_init(&bp->port.phy_mutex);
12512
12513
12514 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12515 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12516 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12517 BNX2X_ERR("BAD MCP validity signature\n");
12518 }
12519
12520 /**
12521 * bnx2x_io_error_detected - called when PCI error is detected
12522 * @pdev: Pointer to PCI device
12523 * @state: The current pci connection state
12524 *
12525 * This function is called after a PCI bus error affecting
12526 * this device has been detected.
12527 */
12528 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12529 pci_channel_state_t state)
12530 {
12531 struct net_device *dev = pci_get_drvdata(pdev);
12532 struct bnx2x *bp = netdev_priv(dev);
12533
12534 rtnl_lock();
12535
12536 netif_device_detach(dev);
12537
12538 if (state == pci_channel_io_perm_failure) {
12539 rtnl_unlock();
12540 return PCI_ERS_RESULT_DISCONNECT;
12541 }
12542
12543 if (netif_running(dev))
12544 bnx2x_eeh_nic_unload(bp);
12545
12546 pci_disable_device(pdev);
12547
12548 rtnl_unlock();
12549
12550 /* Request a slot reset */
12551 return PCI_ERS_RESULT_NEED_RESET;
12552 }
12553
12554 /**
12555 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12556 * @pdev: Pointer to PCI device
12557 *
12558 * Restart the card from scratch, as if from a cold-boot.
12559 */
12560 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12561 {
12562 struct net_device *dev = pci_get_drvdata(pdev);
12563 struct bnx2x *bp = netdev_priv(dev);
12564
12565 rtnl_lock();
12566
12567 if (pci_enable_device(pdev)) {
12568 dev_err(&pdev->dev,
12569 "Cannot re-enable PCI device after reset\n");
12570 rtnl_unlock();
12571 return PCI_ERS_RESULT_DISCONNECT;
12572 }
12573
12574 pci_set_master(pdev);
12575 pci_restore_state(pdev);
12576
12577 if (netif_running(dev))
12578 bnx2x_set_power_state(bp, PCI_D0);
12579
12580 rtnl_unlock();
12581
12582 return PCI_ERS_RESULT_RECOVERED;
12583 }
12584
12585 /**
12586 * bnx2x_io_resume - called when traffic can start flowing again
12587 * @pdev: Pointer to PCI device
12588 *
12589 * This callback is called when the error recovery driver tells us that
12590 * its OK to resume normal operation.
12591 */
12592 static void bnx2x_io_resume(struct pci_dev *pdev)
12593 {
12594 struct net_device *dev = pci_get_drvdata(pdev);
12595 struct bnx2x *bp = netdev_priv(dev);
12596
12597 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12598 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12599 return;
12600 }
12601
12602 rtnl_lock();
12603
12604 bnx2x_eeh_recover(bp);
12605
12606 if (netif_running(dev))
12607 bnx2x_nic_load(bp, LOAD_NORMAL);
12608
12609 netif_device_attach(dev);
12610
12611 rtnl_unlock();
12612 }
12613
12614 static const struct pci_error_handlers bnx2x_err_handler = {
12615 .error_detected = bnx2x_io_error_detected,
12616 .slot_reset = bnx2x_io_slot_reset,
12617 .resume = bnx2x_io_resume,
12618 };
12619
12620 static struct pci_driver bnx2x_pci_driver = {
12621 .name = DRV_MODULE_NAME,
12622 .id_table = bnx2x_pci_tbl,
12623 .probe = bnx2x_init_one,
12624 .remove = bnx2x_remove_one,
12625 .suspend = bnx2x_suspend,
12626 .resume = bnx2x_resume,
12627 .err_handler = &bnx2x_err_handler,
12628 };
12629
12630 static int __init bnx2x_init(void)
12631 {
12632 int ret;
12633
12634 pr_info("%s", version);
12635
12636 bnx2x_wq = create_singlethread_workqueue("bnx2x");
12637 if (bnx2x_wq == NULL) {
12638 pr_err("Cannot create workqueue\n");
12639 return -ENOMEM;
12640 }
12641
12642 ret = pci_register_driver(&bnx2x_pci_driver);
12643 if (ret) {
12644 pr_err("Cannot register driver\n");
12645 destroy_workqueue(bnx2x_wq);
12646 }
12647 return ret;
12648 }
12649
12650 static void __exit bnx2x_cleanup(void)
12651 {
12652 struct list_head *pos, *q;
12653 pci_unregister_driver(&bnx2x_pci_driver);
12654
12655 destroy_workqueue(bnx2x_wq);
12656
12657 /* Free globablly allocated resources */
12658 list_for_each_safe(pos, q, &bnx2x_prev_list) {
12659 struct bnx2x_prev_path_list *tmp =
12660 list_entry(pos, struct bnx2x_prev_path_list, list);
12661 list_del(pos);
12662 kfree(tmp);
12663 }
12664 }
12665
12666 void bnx2x_notify_link_changed(struct bnx2x *bp)
12667 {
12668 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12669 }
12670
12671 module_init(bnx2x_init);
12672 module_exit(bnx2x_cleanup);
12673
12674 /**
12675 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12676 *
12677 * @bp: driver handle
12678 * @set: set or clear the CAM entry
12679 *
12680 * This function will wait until the ramdord completion returns.
12681 * Return 0 if success, -ENODEV if ramrod doesn't return.
12682 */
12683 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12684 {
12685 unsigned long ramrod_flags = 0;
12686
12687 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12688 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12689 &bp->iscsi_l2_mac_obj, true,
12690 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12691 }
12692
12693 /* count denotes the number of new completions we have seen */
12694 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12695 {
12696 struct eth_spe *spe;
12697 int cxt_index, cxt_offset;
12698
12699 #ifdef BNX2X_STOP_ON_ERROR
12700 if (unlikely(bp->panic))
12701 return;
12702 #endif
12703
12704 spin_lock_bh(&bp->spq_lock);
12705 BUG_ON(bp->cnic_spq_pending < count);
12706 bp->cnic_spq_pending -= count;
12707
12708
12709 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12710 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12711 & SPE_HDR_CONN_TYPE) >>
12712 SPE_HDR_CONN_TYPE_SHIFT;
12713 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12714 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12715
12716 /* Set validation for iSCSI L2 client before sending SETUP
12717 * ramrod
12718 */
12719 if (type == ETH_CONNECTION_TYPE) {
12720 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12721 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12722 ILT_PAGE_CIDS;
12723 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12724 (cxt_index * ILT_PAGE_CIDS);
12725 bnx2x_set_ctx_validation(bp,
12726 &bp->context[cxt_index].
12727 vcxt[cxt_offset].eth,
12728 BNX2X_ISCSI_ETH_CID(bp));
12729 }
12730 }
12731
12732 /*
12733 * There may be not more than 8 L2, not more than 8 L5 SPEs
12734 * and in the air. We also check that number of outstanding
12735 * COMMON ramrods is not more than the EQ and SPQ can
12736 * accommodate.
12737 */
12738 if (type == ETH_CONNECTION_TYPE) {
12739 if (!atomic_read(&bp->cq_spq_left))
12740 break;
12741 else
12742 atomic_dec(&bp->cq_spq_left);
12743 } else if (type == NONE_CONNECTION_TYPE) {
12744 if (!atomic_read(&bp->eq_spq_left))
12745 break;
12746 else
12747 atomic_dec(&bp->eq_spq_left);
12748 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12749 (type == FCOE_CONNECTION_TYPE)) {
12750 if (bp->cnic_spq_pending >=
12751 bp->cnic_eth_dev.max_kwqe_pending)
12752 break;
12753 else
12754 bp->cnic_spq_pending++;
12755 } else {
12756 BNX2X_ERR("Unknown SPE type: %d\n", type);
12757 bnx2x_panic();
12758 break;
12759 }
12760
12761 spe = bnx2x_sp_get_next(bp);
12762 *spe = *bp->cnic_kwq_cons;
12763
12764 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
12765 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12766
12767 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12768 bp->cnic_kwq_cons = bp->cnic_kwq;
12769 else
12770 bp->cnic_kwq_cons++;
12771 }
12772 bnx2x_sp_prod_update(bp);
12773 spin_unlock_bh(&bp->spq_lock);
12774 }
12775
12776 static int bnx2x_cnic_sp_queue(struct net_device *dev,
12777 struct kwqe_16 *kwqes[], u32 count)
12778 {
12779 struct bnx2x *bp = netdev_priv(dev);
12780 int i;
12781
12782 #ifdef BNX2X_STOP_ON_ERROR
12783 if (unlikely(bp->panic)) {
12784 BNX2X_ERR("Can't post to SP queue while panic\n");
12785 return -EIO;
12786 }
12787 #endif
12788
12789 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12790 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
12791 BNX2X_ERR("Handling parity error recovery. Try again later\n");
12792 return -EAGAIN;
12793 }
12794
12795 spin_lock_bh(&bp->spq_lock);
12796
12797 for (i = 0; i < count; i++) {
12798 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12799
12800 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12801 break;
12802
12803 *bp->cnic_kwq_prod = *spe;
12804
12805 bp->cnic_kwq_pending++;
12806
12807 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
12808 spe->hdr.conn_and_cmd_data, spe->hdr.type,
12809 spe->data.update_data_addr.hi,
12810 spe->data.update_data_addr.lo,
12811 bp->cnic_kwq_pending);
12812
12813 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12814 bp->cnic_kwq_prod = bp->cnic_kwq;
12815 else
12816 bp->cnic_kwq_prod++;
12817 }
12818
12819 spin_unlock_bh(&bp->spq_lock);
12820
12821 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
12822 bnx2x_cnic_sp_post(bp, 0);
12823
12824 return i;
12825 }
12826
12827 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12828 {
12829 struct cnic_ops *c_ops;
12830 int rc = 0;
12831
12832 mutex_lock(&bp->cnic_mutex);
12833 c_ops = rcu_dereference_protected(bp->cnic_ops,
12834 lockdep_is_held(&bp->cnic_mutex));
12835 if (c_ops)
12836 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12837 mutex_unlock(&bp->cnic_mutex);
12838
12839 return rc;
12840 }
12841
12842 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12843 {
12844 struct cnic_ops *c_ops;
12845 int rc = 0;
12846
12847 rcu_read_lock();
12848 c_ops = rcu_dereference(bp->cnic_ops);
12849 if (c_ops)
12850 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12851 rcu_read_unlock();
12852
12853 return rc;
12854 }
12855
12856 /*
12857 * for commands that have no data
12858 */
12859 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
12860 {
12861 struct cnic_ctl_info ctl = {0};
12862
12863 ctl.cmd = cmd;
12864
12865 return bnx2x_cnic_ctl_send(bp, &ctl);
12866 }
12867
12868 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
12869 {
12870 struct cnic_ctl_info ctl = {0};
12871
12872 /* first we tell CNIC and only then we count this as a completion */
12873 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
12874 ctl.data.comp.cid = cid;
12875 ctl.data.comp.error = err;
12876
12877 bnx2x_cnic_ctl_send_bh(bp, &ctl);
12878 bnx2x_cnic_sp_post(bp, 0);
12879 }
12880
12881
12882 /* Called with netif_addr_lock_bh() taken.
12883 * Sets an rx_mode config for an iSCSI ETH client.
12884 * Doesn't block.
12885 * Completion should be checked outside.
12886 */
12887 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
12888 {
12889 unsigned long accept_flags = 0, ramrod_flags = 0;
12890 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12891 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
12892
12893 if (start) {
12894 /* Start accepting on iSCSI L2 ring. Accept all multicasts
12895 * because it's the only way for UIO Queue to accept
12896 * multicasts (in non-promiscuous mode only one Queue per
12897 * function will receive multicast packets (leading in our
12898 * case).
12899 */
12900 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
12901 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
12902 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
12903 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
12904
12905 /* Clear STOP_PENDING bit if START is requested */
12906 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
12907
12908 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
12909 } else
12910 /* Clear START_PENDING bit if STOP is requested */
12911 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
12912
12913 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
12914 set_bit(sched_state, &bp->sp_state);
12915 else {
12916 __set_bit(RAMROD_RX, &ramrod_flags);
12917 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
12918 ramrod_flags);
12919 }
12920 }
12921
12922
12923 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
12924 {
12925 struct bnx2x *bp = netdev_priv(dev);
12926 int rc = 0;
12927
12928 switch (ctl->cmd) {
12929 case DRV_CTL_CTXTBL_WR_CMD: {
12930 u32 index = ctl->data.io.offset;
12931 dma_addr_t addr = ctl->data.io.dma_addr;
12932
12933 bnx2x_ilt_wr(bp, index, addr);
12934 break;
12935 }
12936
12937 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
12938 int count = ctl->data.credit.credit_count;
12939
12940 bnx2x_cnic_sp_post(bp, count);
12941 break;
12942 }
12943
12944 /* rtnl_lock is held. */
12945 case DRV_CTL_START_L2_CMD: {
12946 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12947 unsigned long sp_bits = 0;
12948
12949 /* Configure the iSCSI classification object */
12950 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
12951 cp->iscsi_l2_client_id,
12952 cp->iscsi_l2_cid, BP_FUNC(bp),
12953 bnx2x_sp(bp, mac_rdata),
12954 bnx2x_sp_mapping(bp, mac_rdata),
12955 BNX2X_FILTER_MAC_PENDING,
12956 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
12957 &bp->macs_pool);
12958
12959 /* Set iSCSI MAC address */
12960 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
12961 if (rc)
12962 break;
12963
12964 mmiowb();
12965 barrier();
12966
12967 /* Start accepting on iSCSI L2 ring */
12968
12969 netif_addr_lock_bh(dev);
12970 bnx2x_set_iscsi_eth_rx_mode(bp, true);
12971 netif_addr_unlock_bh(dev);
12972
12973 /* bits to wait on */
12974 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12975 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
12976
12977 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12978 BNX2X_ERR("rx_mode completion timed out!\n");
12979
12980 break;
12981 }
12982
12983 /* rtnl_lock is held. */
12984 case DRV_CTL_STOP_L2_CMD: {
12985 unsigned long sp_bits = 0;
12986
12987 /* Stop accepting on iSCSI L2 ring */
12988 netif_addr_lock_bh(dev);
12989 bnx2x_set_iscsi_eth_rx_mode(bp, false);
12990 netif_addr_unlock_bh(dev);
12991
12992 /* bits to wait on */
12993 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12994 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
12995
12996 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12997 BNX2X_ERR("rx_mode completion timed out!\n");
12998
12999 mmiowb();
13000 barrier();
13001
13002 /* Unset iSCSI L2 MAC */
13003 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13004 BNX2X_ISCSI_ETH_MAC, true);
13005 break;
13006 }
13007 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13008 int count = ctl->data.credit.credit_count;
13009
13010 smp_mb__before_atomic_inc();
13011 atomic_add(count, &bp->cq_spq_left);
13012 smp_mb__after_atomic_inc();
13013 break;
13014 }
13015 case DRV_CTL_ULP_REGISTER_CMD: {
13016 int ulp_type = ctl->data.register_data.ulp_type;
13017
13018 if (CHIP_IS_E3(bp)) {
13019 int idx = BP_FW_MB_IDX(bp);
13020 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13021 int path = BP_PATH(bp);
13022 int port = BP_PORT(bp);
13023 int i;
13024 u32 scratch_offset;
13025 u32 *host_addr;
13026
13027 /* first write capability to shmem2 */
13028 if (ulp_type == CNIC_ULP_ISCSI)
13029 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13030 else if (ulp_type == CNIC_ULP_FCOE)
13031 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13032 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13033
13034 if ((ulp_type != CNIC_ULP_FCOE) ||
13035 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13036 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
13037 break;
13038
13039 /* if reached here - should write fcoe capabilities */
13040 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13041 if (!scratch_offset)
13042 break;
13043 scratch_offset += offsetof(struct glob_ncsi_oem_data,
13044 fcoe_features[path][port]);
13045 host_addr = (u32 *) &(ctl->data.register_data.
13046 fcoe_features);
13047 for (i = 0; i < sizeof(struct fcoe_capabilities);
13048 i += 4)
13049 REG_WR(bp, scratch_offset + i,
13050 *(host_addr + i/4));
13051 }
13052 break;
13053 }
13054
13055 case DRV_CTL_ULP_UNREGISTER_CMD: {
13056 int ulp_type = ctl->data.ulp_type;
13057
13058 if (CHIP_IS_E3(bp)) {
13059 int idx = BP_FW_MB_IDX(bp);
13060 u32 cap;
13061
13062 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13063 if (ulp_type == CNIC_ULP_ISCSI)
13064 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13065 else if (ulp_type == CNIC_ULP_FCOE)
13066 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13067 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13068 }
13069 break;
13070 }
13071
13072 default:
13073 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13074 rc = -EINVAL;
13075 }
13076
13077 return rc;
13078 }
13079
13080 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13081 {
13082 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13083
13084 if (bp->flags & USING_MSIX_FLAG) {
13085 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13086 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13087 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13088 } else {
13089 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13090 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13091 }
13092 if (!CHIP_IS_E1x(bp))
13093 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13094 else
13095 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13096
13097 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
13098 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13099 cp->irq_arr[1].status_blk = bp->def_status_blk;
13100 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13101 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13102
13103 cp->num_irq = 2;
13104 }
13105
13106 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13107 {
13108 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13109
13110
13111 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13112 bnx2x_cid_ilt_lines(bp);
13113 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13114 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13115 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13116
13117 if (NO_ISCSI_OOO(bp))
13118 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13119 }
13120
13121 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13122 void *data)
13123 {
13124 struct bnx2x *bp = netdev_priv(dev);
13125 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13126 int rc;
13127
13128 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13129
13130 if (ops == NULL) {
13131 BNX2X_ERR("NULL ops received\n");
13132 return -EINVAL;
13133 }
13134
13135 if (!CNIC_SUPPORT(bp)) {
13136 BNX2X_ERR("Can't register CNIC when not supported\n");
13137 return -EOPNOTSUPP;
13138 }
13139
13140 if (!CNIC_LOADED(bp)) {
13141 rc = bnx2x_load_cnic(bp);
13142 if (rc) {
13143 BNX2X_ERR("CNIC-related load failed\n");
13144 return rc;
13145 }
13146
13147 }
13148
13149 bp->cnic_enabled = true;
13150
13151 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13152 if (!bp->cnic_kwq)
13153 return -ENOMEM;
13154
13155 bp->cnic_kwq_cons = bp->cnic_kwq;
13156 bp->cnic_kwq_prod = bp->cnic_kwq;
13157 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13158
13159 bp->cnic_spq_pending = 0;
13160 bp->cnic_kwq_pending = 0;
13161
13162 bp->cnic_data = data;
13163
13164 cp->num_irq = 0;
13165 cp->drv_state |= CNIC_DRV_STATE_REGD;
13166 cp->iro_arr = bp->iro_arr;
13167
13168 bnx2x_setup_cnic_irq_info(bp);
13169
13170 rcu_assign_pointer(bp->cnic_ops, ops);
13171
13172 return 0;
13173 }
13174
13175 static int bnx2x_unregister_cnic(struct net_device *dev)
13176 {
13177 struct bnx2x *bp = netdev_priv(dev);
13178 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13179
13180 mutex_lock(&bp->cnic_mutex);
13181 cp->drv_state = 0;
13182 RCU_INIT_POINTER(bp->cnic_ops, NULL);
13183 mutex_unlock(&bp->cnic_mutex);
13184 synchronize_rcu();
13185 kfree(bp->cnic_kwq);
13186 bp->cnic_kwq = NULL;
13187
13188 return 0;
13189 }
13190
13191 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13192 {
13193 struct bnx2x *bp = netdev_priv(dev);
13194 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13195
13196 /* If both iSCSI and FCoE are disabled - return NULL in
13197 * order to indicate CNIC that it should not try to work
13198 * with this device.
13199 */
13200 if (NO_ISCSI(bp) && NO_FCOE(bp))
13201 return NULL;
13202
13203 cp->drv_owner = THIS_MODULE;
13204 cp->chip_id = CHIP_ID(bp);
13205 cp->pdev = bp->pdev;
13206 cp->io_base = bp->regview;
13207 cp->io_base2 = bp->doorbells;
13208 cp->max_kwqe_pending = 8;
13209 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13210 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13211 bnx2x_cid_ilt_lines(bp);
13212 cp->ctx_tbl_len = CNIC_ILT_LINES;
13213 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13214 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13215 cp->drv_ctl = bnx2x_drv_ctl;
13216 cp->drv_register_cnic = bnx2x_register_cnic;
13217 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13218 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13219 cp->iscsi_l2_client_id =
13220 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13221 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13222
13223 if (NO_ISCSI_OOO(bp))
13224 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13225
13226 if (NO_ISCSI(bp))
13227 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13228
13229 if (NO_FCOE(bp))
13230 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13231
13232 BNX2X_DEV_INFO(
13233 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13234 cp->ctx_blk_size,
13235 cp->ctx_tbl_offset,
13236 cp->ctx_tbl_len,
13237 cp->starting_cid);
13238 return cp;
13239 }
13240
13241 int bnx2x_send_msg2pf(struct bnx2x *bp, u8 *done, dma_addr_t msg_mapping)
13242 {
13243 struct cstorm_vf_zone_data __iomem *zone_data =
13244 REG_ADDR(bp, PXP_VF_ADDR_CSDM_GLOBAL_START);
13245 int tout = 600, interval = 100; /* wait for 60 seconds */
13246
13247 if (*done) {
13248 BNX2X_ERR("done was non zero before message to pf was sent\n");
13249 WARN_ON(true);
13250 return -EINVAL;
13251 }
13252
13253 /* Write message address */
13254 writel(U64_LO(msg_mapping),
13255 &zone_data->non_trigger.vf_pf_channel.msg_addr_lo);
13256 writel(U64_HI(msg_mapping),
13257 &zone_data->non_trigger.vf_pf_channel.msg_addr_hi);
13258
13259 /* make sure the address is written before FW accesses it */
13260 wmb();
13261
13262 /* Trigger the PF FW */
13263 writeb(1, &zone_data->trigger.vf_pf_channel.addr_valid);
13264
13265 /* Wait for PF to complete */
13266 while ((tout >= 0) && (!*done)) {
13267 msleep(interval);
13268 tout -= 1;
13269
13270 /* progress indicator - HV can take its own sweet time in
13271 * answering VFs...
13272 */
13273 DP_CONT(BNX2X_MSG_IOV, ".");
13274 }
13275
13276 if (!*done) {
13277 BNX2X_ERR("PF response has timed out\n");
13278 return -EAGAIN;
13279 }
13280 DP(BNX2X_MSG_SP, "Got a response from PF\n");
13281 return 0;
13282 }
13283
13284 int bnx2x_get_vf_id(struct bnx2x *bp, u32 *vf_id)
13285 {
13286 u32 me_reg;
13287 int tout = 10, interval = 100; /* Wait for 1 sec */
13288
13289 do {
13290 /* pxp traps vf read of doorbells and returns me reg value */
13291 me_reg = readl(bp->doorbells);
13292 if (GOOD_ME_REG(me_reg))
13293 break;
13294
13295 msleep(interval);
13296
13297 BNX2X_ERR("Invalid ME register value: 0x%08x\n. Is pf driver up?",
13298 me_reg);
13299 } while (tout-- > 0);
13300
13301 if (!GOOD_ME_REG(me_reg)) {
13302 BNX2X_ERR("Invalid ME register value: 0x%08x\n", me_reg);
13303 return -EINVAL;
13304 }
13305
13306 BNX2X_ERR("valid ME register value: 0x%08x\n", me_reg);
13307
13308 *vf_id = (me_reg & ME_REG_VF_NUM_MASK) >> ME_REG_VF_NUM_SHIFT;
13309
13310 return 0;
13311 }
13312
13313 int bnx2x_vfpf_acquire(struct bnx2x *bp, u8 tx_count, u8 rx_count)
13314 {
13315 int rc = 0, attempts = 0;
13316 struct vfpf_acquire_tlv *req = &bp->vf2pf_mbox->req.acquire;
13317 struct pfvf_acquire_resp_tlv *resp = &bp->vf2pf_mbox->resp.acquire_resp;
13318 u32 vf_id;
13319 bool resources_acquired = false;
13320
13321 /* clear mailbox and prep first tlv */
13322 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_ACQUIRE, sizeof(*req));
13323
13324 if (bnx2x_get_vf_id(bp, &vf_id))
13325 return -EAGAIN;
13326
13327 req->vfdev_info.vf_id = vf_id;
13328 req->vfdev_info.vf_os = 0;
13329
13330 req->resc_request.num_rxqs = rx_count;
13331 req->resc_request.num_txqs = tx_count;
13332 req->resc_request.num_sbs = bp->igu_sb_cnt;
13333 req->resc_request.num_mac_filters = VF_ACQUIRE_MAC_FILTERS;
13334 req->resc_request.num_mc_filters = VF_ACQUIRE_MC_FILTERS;
13335
13336 /* add list termination tlv */
13337 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13338 sizeof(struct channel_list_end_tlv));
13339
13340 /* output tlvs list */
13341 bnx2x_dp_tlv_list(bp, req);
13342
13343 while (!resources_acquired) {
13344 DP(BNX2X_MSG_SP, "attempting to acquire resources\n");
13345
13346 /* send acquire request */
13347 rc = bnx2x_send_msg2pf(bp,
13348 &resp->hdr.status,
13349 bp->vf2pf_mbox_mapping);
13350
13351 /* PF timeout */
13352 if (rc)
13353 return rc;
13354
13355 /* copy acquire response from buffer to bp */
13356 memcpy(&bp->acquire_resp, resp, sizeof(bp->acquire_resp));
13357
13358 attempts++;
13359
13360 /* test whether the PF accepted our request. If not, humble the
13361 * the request and try again.
13362 */
13363 if (bp->acquire_resp.hdr.status == PFVF_STATUS_SUCCESS) {
13364 DP(BNX2X_MSG_SP, "resources acquired\n");
13365 resources_acquired = true;
13366 } else if (bp->acquire_resp.hdr.status ==
13367 PFVF_STATUS_NO_RESOURCE &&
13368 attempts < VF_ACQUIRE_THRESH) {
13369 DP(BNX2X_MSG_SP,
13370 "PF unwilling to fulfill resource request. Try PF recommended amount\n");
13371
13372 /* humble our request */
13373 req->resc_request.num_txqs =
13374 bp->acquire_resp.resc.num_txqs;
13375 req->resc_request.num_rxqs =
13376 bp->acquire_resp.resc.num_rxqs;
13377 req->resc_request.num_sbs =
13378 bp->acquire_resp.resc.num_sbs;
13379 req->resc_request.num_mac_filters =
13380 bp->acquire_resp.resc.num_mac_filters;
13381 req->resc_request.num_vlan_filters =
13382 bp->acquire_resp.resc.num_vlan_filters;
13383 req->resc_request.num_mc_filters =
13384 bp->acquire_resp.resc.num_mc_filters;
13385
13386 /* Clear response buffer */
13387 memset(&bp->vf2pf_mbox->resp, 0,
13388 sizeof(union pfvf_tlvs));
13389 } else {
13390 /* PF reports error */
13391 BNX2X_ERR("Failed to get the requested amount of resources: %d. Breaking...\n",
13392 bp->acquire_resp.hdr.status);
13393 return -EAGAIN;
13394 }
13395 }
13396
13397 /* get HW info */
13398 bp->common.chip_id |= (bp->acquire_resp.pfdev_info.chip_num & 0xffff);
13399 bp->link_params.chip_id = bp->common.chip_id;
13400 bp->db_size = bp->acquire_resp.pfdev_info.db_size;
13401 bp->common.int_block = INT_BLOCK_IGU;
13402 bp->common.chip_port_mode = CHIP_2_PORT_MODE;
13403 bp->igu_dsb_id = -1;
13404 bp->mf_ov = 0;
13405 bp->mf_mode = 0;
13406 bp->common.flash_size = 0;
13407 bp->flags |=
13408 NO_WOL_FLAG | NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG | NO_FCOE_FLAG;
13409 bp->igu_sb_cnt = 1;
13410 bp->igu_base_sb = bp->acquire_resp.resc.hw_sbs[0].hw_sb_id;
13411 strlcpy(bp->fw_ver, bp->acquire_resp.pfdev_info.fw_ver,
13412 sizeof(bp->fw_ver));
13413
13414 if (is_valid_ether_addr(bp->acquire_resp.resc.current_mac_addr))
13415 memcpy(bp->dev->dev_addr,
13416 bp->acquire_resp.resc.current_mac_addr,
13417 ETH_ALEN);
13418
13419 return 0;
13420 }
13421
13422 int bnx2x_vfpf_release(struct bnx2x *bp)
13423 {
13424 struct vfpf_release_tlv *req = &bp->vf2pf_mbox->req.release;
13425 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13426 u32 rc = 0, vf_id;
13427
13428 /* clear mailbox and prep first tlv */
13429 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_RELEASE, sizeof(*req));
13430
13431 if (bnx2x_get_vf_id(bp, &vf_id))
13432 return -EAGAIN;
13433
13434 req->vf_id = vf_id;
13435
13436 /* add list termination tlv */
13437 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13438 sizeof(struct channel_list_end_tlv));
13439
13440 /* output tlvs list */
13441 bnx2x_dp_tlv_list(bp, req);
13442
13443 /* send release request */
13444 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13445
13446 if (rc)
13447 /* PF timeout */
13448 return rc;
13449 if (resp->hdr.status == PFVF_STATUS_SUCCESS) {
13450 /* PF released us */
13451 DP(BNX2X_MSG_SP, "vf released\n");
13452 } else {
13453 /* PF reports error */
13454 BNX2X_ERR("PF failed our release request - are we out of sync? response status: %d\n",
13455 resp->hdr.status);
13456 return -EAGAIN;
13457 }
13458
13459 return 0;
13460 }
13461
13462 /* Tell PF about SB addresses */
13463 int bnx2x_vfpf_init(struct bnx2x *bp)
13464 {
13465 struct vfpf_init_tlv *req = &bp->vf2pf_mbox->req.init;
13466 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13467 int rc, i;
13468
13469 /* clear mailbox and prep first tlv */
13470 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_INIT, sizeof(*req));
13471
13472 /* status blocks */
13473 for_each_eth_queue(bp, i)
13474 req->sb_addr[i] = (dma_addr_t)bnx2x_fp(bp, i,
13475 status_blk_mapping);
13476
13477 /* statistics - requests only supports single queue for now */
13478 req->stats_addr = bp->fw_stats_data_mapping +
13479 offsetof(struct bnx2x_fw_stats_data, queue_stats);
13480
13481 /* add list termination tlv */
13482 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13483 sizeof(struct channel_list_end_tlv));
13484
13485 /* output tlvs list */
13486 bnx2x_dp_tlv_list(bp, req);
13487
13488 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13489 if (rc)
13490 return rc;
13491
13492 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13493 BNX2X_ERR("INIT VF failed: %d. Breaking...\n",
13494 resp->hdr.status);
13495 return -EAGAIN;
13496 }
13497
13498 DP(BNX2X_MSG_SP, "INIT VF Succeeded\n");
13499 return 0;
13500 }
13501
13502 /* CLOSE VF - opposite to INIT_VF */
13503 void bnx2x_vfpf_close_vf(struct bnx2x *bp)
13504 {
13505 struct vfpf_close_tlv *req = &bp->vf2pf_mbox->req.close;
13506 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13507 int i, rc;
13508 u32 vf_id;
13509
13510 /* If we haven't got a valid VF id, there is no sense to
13511 * continue with sending messages
13512 */
13513 if (bnx2x_get_vf_id(bp, &vf_id))
13514 goto free_irq;
13515
13516 /* Close the queues */
13517 for_each_queue(bp, i)
13518 bnx2x_vfpf_teardown_queue(bp, i);
13519
13520 /* clear mailbox and prep first tlv */
13521 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_CLOSE, sizeof(*req));
13522
13523 req->vf_id = vf_id;
13524
13525 /* add list termination tlv */
13526 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13527 sizeof(struct channel_list_end_tlv));
13528
13529 /* output tlvs list */
13530 bnx2x_dp_tlv_list(bp, req);
13531
13532 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13533
13534 if (rc)
13535 BNX2X_ERR("Sending CLOSE failed. rc was: %d\n", rc);
13536
13537 else if (resp->hdr.status != PFVF_STATUS_SUCCESS)
13538 BNX2X_ERR("Sending CLOSE failed: pf response was %d\n",
13539 resp->hdr.status);
13540
13541 free_irq:
13542 /* Disable HW interrupts, NAPI */
13543 bnx2x_netif_stop(bp, 0);
13544 /* Delete all NAPI objects */
13545 bnx2x_del_all_napi(bp);
13546
13547 /* Release IRQs */
13548 bnx2x_free_irq(bp);
13549 }
13550
13551 /* ask the pf to open a queue for the vf */
13552 int bnx2x_vfpf_setup_q(struct bnx2x *bp, int fp_idx)
13553 {
13554 struct vfpf_setup_q_tlv *req = &bp->vf2pf_mbox->req.setup_q;
13555 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13556 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
13557 u16 tpa_agg_size = 0, flags = 0;
13558 int rc;
13559
13560 /* clear mailbox and prep first tlv */
13561 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SETUP_Q, sizeof(*req));
13562
13563 /* select tpa mode to request */
13564 if (!fp->disable_tpa) {
13565 flags |= VFPF_QUEUE_FLG_TPA;
13566 flags |= VFPF_QUEUE_FLG_TPA_IPV6;
13567 if (fp->mode == TPA_MODE_GRO)
13568 flags |= VFPF_QUEUE_FLG_TPA_GRO;
13569 tpa_agg_size = TPA_AGG_SIZE;
13570 }
13571
13572 /* calculate queue flags */
13573 flags |= VFPF_QUEUE_FLG_STATS;
13574 flags |= VFPF_QUEUE_FLG_CACHE_ALIGN;
13575 flags |= IS_MF_SD(bp) ? VFPF_QUEUE_FLG_OV : 0;
13576 flags |= VFPF_QUEUE_FLG_VLAN;
13577 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
13578
13579 /* Common */
13580 req->vf_qid = fp_idx;
13581 req->param_valid = VFPF_RXQ_VALID | VFPF_TXQ_VALID;
13582
13583 /* Rx */
13584 req->rxq.rcq_addr = fp->rx_comp_mapping;
13585 req->rxq.rcq_np_addr = fp->rx_comp_mapping + BCM_PAGE_SIZE;
13586 req->rxq.rxq_addr = fp->rx_desc_mapping;
13587 req->rxq.sge_addr = fp->rx_sge_mapping;
13588 req->rxq.vf_sb = fp_idx;
13589 req->rxq.sb_index = HC_INDEX_ETH_RX_CQ_CONS;
13590 req->rxq.hc_rate = bp->rx_ticks ? 1000000/bp->rx_ticks : 0;
13591 req->rxq.mtu = bp->dev->mtu;
13592 req->rxq.buf_sz = fp->rx_buf_size;
13593 req->rxq.sge_buf_sz = BCM_PAGE_SIZE * PAGES_PER_SGE;
13594 req->rxq.tpa_agg_sz = tpa_agg_size;
13595 req->rxq.max_sge_pkt = SGE_PAGE_ALIGN(bp->dev->mtu) >> SGE_PAGE_SHIFT;
13596 req->rxq.max_sge_pkt = ((req->rxq.max_sge_pkt + PAGES_PER_SGE - 1) &
13597 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
13598 req->rxq.flags = flags;
13599 req->rxq.drop_flags = 0;
13600 req->rxq.cache_line_log = BNX2X_RX_ALIGN_SHIFT;
13601 req->rxq.stat_id = -1; /* No stats at the moment */
13602
13603 /* Tx */
13604 req->txq.txq_addr = fp->txdata_ptr[FIRST_TX_COS_INDEX]->tx_desc_mapping;
13605 req->txq.vf_sb = fp_idx;
13606 req->txq.sb_index = HC_INDEX_ETH_TX_CQ_CONS_COS0;
13607 req->txq.hc_rate = bp->tx_ticks ? 1000000/bp->tx_ticks : 0;
13608 req->txq.flags = flags;
13609 req->txq.traffic_type = LLFC_TRAFFIC_TYPE_NW;
13610
13611 /* add list termination tlv */
13612 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13613 sizeof(struct channel_list_end_tlv));
13614
13615 /* output tlvs list */
13616 bnx2x_dp_tlv_list(bp, req);
13617
13618 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13619 if (rc)
13620 BNX2X_ERR("Sending SETUP_Q message for queue[%d] failed!\n",
13621 fp_idx);
13622
13623 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13624 BNX2X_ERR("Status of SETUP_Q for queue[%d] is %d\n",
13625 fp_idx, resp->hdr.status);
13626 return -EINVAL;
13627 }
13628 return rc;
13629 }
13630
13631 int bnx2x_vfpf_teardown_queue(struct bnx2x *bp, int qidx)
13632 {
13633 struct vfpf_q_op_tlv *req = &bp->vf2pf_mbox->req.q_op;
13634 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13635 int rc;
13636
13637 /* clear mailbox and prep first tlv */
13638 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_TEARDOWN_Q,
13639 sizeof(*req));
13640
13641 req->vf_qid = qidx;
13642
13643 /* add list termination tlv */
13644 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13645 sizeof(struct channel_list_end_tlv));
13646
13647 /* output tlvs list */
13648 bnx2x_dp_tlv_list(bp, req);
13649
13650 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13651
13652 if (rc) {
13653 BNX2X_ERR("Sending TEARDOWN for queue %d failed: %d\n", qidx,
13654 rc);
13655 return rc;
13656 }
13657
13658 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13659 BNX2X_ERR("TEARDOWN for queue %d failed: %d\n", qidx,
13660 resp->hdr.status);
13661 return -EINVAL;
13662 }
13663
13664 return 0;
13665 }
13666
13667 /* request pf to add a mac for the vf */
13668 int bnx2x_vfpf_set_mac(struct bnx2x *bp)
13669 {
13670 struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters;
13671 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13672 int rc;
13673
13674 /* clear mailbox and prep first tlv */
13675 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS,
13676 sizeof(*req));
13677
13678 req->flags = VFPF_SET_Q_FILTERS_MAC_VLAN_CHANGED;
13679 req->vf_qid = 0;
13680 req->n_mac_vlan_filters = 1;
13681 req->filters[0].flags =
13682 VFPF_Q_FILTER_DEST_MAC_VALID | VFPF_Q_FILTER_SET_MAC;
13683
13684 /* copy mac from device to request */
13685 memcpy(req->filters[0].mac, bp->dev->dev_addr, ETH_ALEN);
13686
13687 /* add list termination tlv */
13688 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13689 sizeof(struct channel_list_end_tlv));
13690
13691 /* output tlvs list */
13692 bnx2x_dp_tlv_list(bp, req);
13693
13694 /* send message to pf */
13695 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13696 if (rc) {
13697 BNX2X_ERR("failed to send message to pf. rc was %d\n", rc);
13698 return rc;
13699 }
13700
13701 /* PF failed the transaction */
13702 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13703 BNX2X_ERR("vfpf SET MAC failed: %d\n", resp->hdr.status);
13704 return -EINVAL;
13705 }
13706
13707 return 0;
13708 }
13709
13710 int bnx2x_vfpf_set_mcast(struct net_device *dev)
13711 {
13712 struct bnx2x *bp = netdev_priv(dev);
13713 struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters;
13714 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13715 int rc, i = 0;
13716 struct netdev_hw_addr *ha;
13717
13718 if (bp->state != BNX2X_STATE_OPEN) {
13719 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
13720 return -EINVAL;
13721 }
13722
13723 /* clear mailbox and prep first tlv */
13724 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS,
13725 sizeof(*req));
13726
13727 /* Get Rx mode requested */
13728 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
13729
13730 netdev_for_each_mc_addr(ha, dev) {
13731 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
13732 bnx2x_mc_addr(ha));
13733 memcpy(req->multicast[i], bnx2x_mc_addr(ha), ETH_ALEN);
13734 i++;
13735 }
13736
13737 /* We support four PFVF_MAX_MULTICAST_PER_VF mcast
13738 * addresses tops
13739 */
13740 if (i >= PFVF_MAX_MULTICAST_PER_VF) {
13741 DP(NETIF_MSG_IFUP,
13742 "VF supports not more than %d multicast MAC addresses\n",
13743 PFVF_MAX_MULTICAST_PER_VF);
13744 return -EINVAL;
13745 }
13746
13747 req->n_multicast = i;
13748 req->flags |= VFPF_SET_Q_FILTERS_MULTICAST_CHANGED;
13749 req->vf_qid = 0;
13750
13751 /* add list termination tlv */
13752 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13753 sizeof(struct channel_list_end_tlv));
13754
13755 /* output tlvs list */
13756 bnx2x_dp_tlv_list(bp, req);
13757
13758 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13759 if (rc) {
13760 BNX2X_ERR("Sending a message failed: %d\n", rc);
13761 return rc;
13762 }
13763
13764 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13765 BNX2X_ERR("Set Rx mode/multicast failed: %d\n",
13766 resp->hdr.status);
13767 return -EINVAL;
13768 }
13769
13770 return 0;
13771 }
13772
13773 int bnx2x_vfpf_storm_rx_mode(struct bnx2x *bp)
13774 {
13775 int mode = bp->rx_mode;
13776 struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters;
13777 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13778 int rc;
13779
13780 /* clear mailbox and prep first tlv */
13781 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS,
13782 sizeof(*req));
13783
13784 DP(NETIF_MSG_IFUP, "Rx mode is %d\n", mode);
13785
13786 switch (mode) {
13787 case BNX2X_RX_MODE_NONE: /* no Rx */
13788 req->rx_mask = VFPF_RX_MASK_ACCEPT_NONE;
13789 break;
13790 case BNX2X_RX_MODE_NORMAL:
13791 req->rx_mask = VFPF_RX_MASK_ACCEPT_MATCHED_MULTICAST;
13792 req->rx_mask |= VFPF_RX_MASK_ACCEPT_MATCHED_UNICAST;
13793 req->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST;
13794 break;
13795 case BNX2X_RX_MODE_ALLMULTI:
13796 req->rx_mask = VFPF_RX_MASK_ACCEPT_ALL_MULTICAST;
13797 req->rx_mask |= VFPF_RX_MASK_ACCEPT_MATCHED_UNICAST;
13798 req->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST;
13799 break;
13800 case BNX2X_RX_MODE_PROMISC:
13801 req->rx_mask = VFPF_RX_MASK_ACCEPT_ALL_UNICAST;
13802 req->rx_mask |= VFPF_RX_MASK_ACCEPT_ALL_MULTICAST;
13803 req->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST;
13804 break;
13805 default:
13806 BNX2X_ERR("BAD rx mode (%d)\n", mode);
13807 return -EINVAL;
13808 }
13809
13810 req->flags |= VFPF_SET_Q_FILTERS_RX_MASK_CHANGED;
13811 req->vf_qid = 0;
13812
13813 /* add list termination tlv */
13814 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13815 sizeof(struct channel_list_end_tlv));
13816
13817 /* output tlvs list */
13818 bnx2x_dp_tlv_list(bp, req);
13819
13820 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13821 if (rc)
13822 BNX2X_ERR("Sending a message failed: %d\n", rc);
13823
13824 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13825 BNX2X_ERR("Set Rx mode failed: %d\n", resp->hdr.status);
13826 return -EINVAL;
13827 }
13828
13829 return rc;
13830 }
kernel source for telekom puls (alcatel/mediatek)