projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
bnx2x: Support loading cnic resources at run-time
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2012 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <net/ip.h>
44 #include <net/ipv6.h>
45 #include <net/tcp.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
53 #include <linux/io.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
57
58 #include "bnx2x.h"
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_dcb.h"
63 #include "bnx2x_sp.h"
64
65 #include <linux/firmware.h>
66 #include "bnx2x_fw_file_hdr.h"
67 /* FW files */
68 #define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
76
77 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
78
79 /* Time in jiffies before concluding the transmitter is hung */
80 #define TX_TIMEOUT (5*HZ)
81
82 static char version[] __devinitdata =
83 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
84 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
85
86 MODULE_AUTHOR("Eliezer Tamir");
87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
88 "BCM57710/57711/57711E/"
89 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
90 "57840/57840_MF Driver");
91 MODULE_LICENSE("GPL");
92 MODULE_VERSION(DRV_MODULE_VERSION);
93 MODULE_FIRMWARE(FW_FILE_NAME_E1);
94 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
95 MODULE_FIRMWARE(FW_FILE_NAME_E2);
96
97
98 int num_queues;
99 module_param(num_queues, int, 0);
100 MODULE_PARM_DESC(num_queues,
101 " Set number of queues (default is as a number of CPUs)");
102
103 static int disable_tpa;
104 module_param(disable_tpa, int, 0);
105 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
106
107 #define INT_MODE_INTx 1
108 #define INT_MODE_MSI 2
109 int int_mode;
110 module_param(int_mode, int, 0);
111 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
112 "(1 INT#x; 2 MSI)");
113
114 static int dropless_fc;
115 module_param(dropless_fc, int, 0);
116 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
117
118 static int mrrs = -1;
119 module_param(mrrs, int, 0);
120 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
121
122 static int debug;
123 module_param(debug, int, 0);
124 MODULE_PARM_DESC(debug, " Default debug msglevel");
125
126
127
128 struct workqueue_struct *bnx2x_wq;
129
130 enum bnx2x_board_type {
131 BCM57710 = 0,
132 BCM57711,
133 BCM57711E,
134 BCM57712,
135 BCM57712_MF,
136 BCM57800,
137 BCM57800_MF,
138 BCM57810,
139 BCM57810_MF,
140 BCM57840_O,
141 BCM57840_4_10,
142 BCM57840_2_20,
143 BCM57840_MFO,
144 BCM57840_MF,
145 BCM57811,
146 BCM57811_MF
147 };
148
149 /* indexed by board_type, above */
150 static struct {
151 char *name;
152 } board_info[] __devinitdata = {
153 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
154 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
155 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
156 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
158 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
160 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
162 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
163 { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
164 { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
165 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
166 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
167 { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet"},
168 { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function"},
169 };
170
171 #ifndef PCI_DEVICE_ID_NX2_57710
172 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
173 #endif
174 #ifndef PCI_DEVICE_ID_NX2_57711
175 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
176 #endif
177 #ifndef PCI_DEVICE_ID_NX2_57711E
178 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
179 #endif
180 #ifndef PCI_DEVICE_ID_NX2_57712
181 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
182 #endif
183 #ifndef PCI_DEVICE_ID_NX2_57712_MF
184 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
185 #endif
186 #ifndef PCI_DEVICE_ID_NX2_57800
187 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
188 #endif
189 #ifndef PCI_DEVICE_ID_NX2_57800_MF
190 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
191 #endif
192 #ifndef PCI_DEVICE_ID_NX2_57810
193 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
194 #endif
195 #ifndef PCI_DEVICE_ID_NX2_57810_MF
196 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
197 #endif
198 #ifndef PCI_DEVICE_ID_NX2_57840_O
199 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
200 #endif
201 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
202 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
203 #endif
204 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
205 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
206 #endif
207 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
208 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
209 #endif
210 #ifndef PCI_DEVICE_ID_NX2_57840_MF
211 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
212 #endif
213 #ifndef PCI_DEVICE_ID_NX2_57811
214 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
215 #endif
216 #ifndef PCI_DEVICE_ID_NX2_57811_MF
217 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
218 #endif
219 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
220 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
221 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
222 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
223 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
224 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
225 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
226 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
227 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
228 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
229 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
230 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
231 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
232 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
233 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
234 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
235 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
236 { 0 }
237 };
238
239 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
240
241 /* Global resources for unloading a previously loaded device */
242 #define BNX2X_PREV_WAIT_NEEDED 1
243 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
244 static LIST_HEAD(bnx2x_prev_list);
245 /****************************************************************************
246 * General service functions
247 ****************************************************************************/
248
249 static void __storm_memset_dma_mapping(struct bnx2x *bp,
250 u32 addr, dma_addr_t mapping)
251 {
252 REG_WR(bp, addr, U64_LO(mapping));
253 REG_WR(bp, addr + 4, U64_HI(mapping));
254 }
255
256 static void storm_memset_spq_addr(struct bnx2x *bp,
257 dma_addr_t mapping, u16 abs_fid)
258 {
259 u32 addr = XSEM_REG_FAST_MEMORY +
260 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
261
262 __storm_memset_dma_mapping(bp, addr, mapping);
263 }
264
265 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
266 u16 pf_id)
267 {
268 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
269 pf_id);
270 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
271 pf_id);
272 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
273 pf_id);
274 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
275 pf_id);
276 }
277
278 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
279 u8 enable)
280 {
281 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
282 enable);
283 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
284 enable);
285 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
286 enable);
287 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
288 enable);
289 }
290
291 static void storm_memset_eq_data(struct bnx2x *bp,
292 struct event_ring_data *eq_data,
293 u16 pfid)
294 {
295 size_t size = sizeof(struct event_ring_data);
296
297 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
298
299 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
300 }
301
302 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
303 u16 pfid)
304 {
305 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
306 REG_WR16(bp, addr, eq_prod);
307 }
308
309 /* used only at init
310 * locking is done by mcp
311 */
312 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
313 {
314 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
315 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
316 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
317 PCICFG_VENDOR_ID_OFFSET);
318 }
319
320 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
321 {
322 u32 val;
323
324 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
325 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
326 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
327 PCICFG_VENDOR_ID_OFFSET);
328
329 return val;
330 }
331
332 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
333 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
334 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
335 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
336 #define DMAE_DP_DST_NONE "dst_addr [none]"
337
338
339 /* copy command into DMAE command memory and set DMAE command go */
340 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
341 {
342 u32 cmd_offset;
343 int i;
344
345 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
346 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
347 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
348 }
349 REG_WR(bp, dmae_reg_go_c[idx], 1);
350 }
351
352 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
353 {
354 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
355 DMAE_CMD_C_ENABLE);
356 }
357
358 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
359 {
360 return opcode & ~DMAE_CMD_SRC_RESET;
361 }
362
363 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
364 bool with_comp, u8 comp_type)
365 {
366 u32 opcode = 0;
367
368 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
369 (dst_type << DMAE_COMMAND_DST_SHIFT));
370
371 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
372
373 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
374 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
375 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
376 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
377
378 #ifdef __BIG_ENDIAN
379 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
380 #else
381 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
382 #endif
383 if (with_comp)
384 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
385 return opcode;
386 }
387
388 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
389 struct dmae_command *dmae,
390 u8 src_type, u8 dst_type)
391 {
392 memset(dmae, 0, sizeof(struct dmae_command));
393
394 /* set the opcode */
395 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
396 true, DMAE_COMP_PCI);
397
398 /* fill in the completion parameters */
399 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
400 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
401 dmae->comp_val = DMAE_COMP_VAL;
402 }
403
404 /* issue a dmae command over the init-channel and wailt for completion */
405 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
406 struct dmae_command *dmae)
407 {
408 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
409 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
410 int rc = 0;
411
412 /*
413 * Lock the dmae channel. Disable BHs to prevent a dead-lock
414 * as long as this code is called both from syscall context and
415 * from ndo_set_rx_mode() flow that may be called from BH.
416 */
417 spin_lock_bh(&bp->dmae_lock);
418
419 /* reset completion */
420 *wb_comp = 0;
421
422 /* post the command on the channel used for initializations */
423 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
424
425 /* wait for completion */
426 udelay(5);
427 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
428
429 if (!cnt ||
430 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
431 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
432 BNX2X_ERR("DMAE timeout!\n");
433 rc = DMAE_TIMEOUT;
434 goto unlock;
435 }
436 cnt--;
437 udelay(50);
438 }
439 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
440 BNX2X_ERR("DMAE PCI error!\n");
441 rc = DMAE_PCI_ERROR;
442 }
443
444 unlock:
445 spin_unlock_bh(&bp->dmae_lock);
446 return rc;
447 }
448
449 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
450 u32 len32)
451 {
452 struct dmae_command dmae;
453
454 if (!bp->dmae_ready) {
455 u32 *data = bnx2x_sp(bp, wb_data[0]);
456
457 if (CHIP_IS_E1(bp))
458 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
459 else
460 bnx2x_init_str_wr(bp, dst_addr, data, len32);
461 return;
462 }
463
464 /* set opcode and fixed command fields */
465 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
466
467 /* fill in addresses and len */
468 dmae.src_addr_lo = U64_LO(dma_addr);
469 dmae.src_addr_hi = U64_HI(dma_addr);
470 dmae.dst_addr_lo = dst_addr >> 2;
471 dmae.dst_addr_hi = 0;
472 dmae.len = len32;
473
474 /* issue the command and wait for completion */
475 bnx2x_issue_dmae_with_comp(bp, &dmae);
476 }
477
478 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
479 {
480 struct dmae_command dmae;
481
482 if (!bp->dmae_ready) {
483 u32 *data = bnx2x_sp(bp, wb_data[0]);
484 int i;
485
486 if (CHIP_IS_E1(bp))
487 for (i = 0; i < len32; i++)
488 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
489 else
490 for (i = 0; i < len32; i++)
491 data[i] = REG_RD(bp, src_addr + i*4);
492
493 return;
494 }
495
496 /* set opcode and fixed command fields */
497 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
498
499 /* fill in addresses and len */
500 dmae.src_addr_lo = src_addr >> 2;
501 dmae.src_addr_hi = 0;
502 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
503 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
504 dmae.len = len32;
505
506 /* issue the command and wait for completion */
507 bnx2x_issue_dmae_with_comp(bp, &dmae);
508 }
509
510 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
511 u32 addr, u32 len)
512 {
513 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
514 int offset = 0;
515
516 while (len > dmae_wr_max) {
517 bnx2x_write_dmae(bp, phys_addr + offset,
518 addr + offset, dmae_wr_max);
519 offset += dmae_wr_max * 4;
520 len -= dmae_wr_max;
521 }
522
523 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
524 }
525
526 static int bnx2x_mc_assert(struct bnx2x *bp)
527 {
528 char last_idx;
529 int i, rc = 0;
530 u32 row0, row1, row2, row3;
531
532 /* XSTORM */
533 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
534 XSTORM_ASSERT_LIST_INDEX_OFFSET);
535 if (last_idx)
536 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
537
538 /* print the asserts */
539 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
540
541 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
542 XSTORM_ASSERT_LIST_OFFSET(i));
543 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
544 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
545 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
546 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
547 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
548 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
549
550 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
551 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
552 i, row3, row2, row1, row0);
553 rc++;
554 } else {
555 break;
556 }
557 }
558
559 /* TSTORM */
560 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
561 TSTORM_ASSERT_LIST_INDEX_OFFSET);
562 if (last_idx)
563 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
564
565 /* print the asserts */
566 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
567
568 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
569 TSTORM_ASSERT_LIST_OFFSET(i));
570 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
571 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
572 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
573 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
574 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
575 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
576
577 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
578 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
579 i, row3, row2, row1, row0);
580 rc++;
581 } else {
582 break;
583 }
584 }
585
586 /* CSTORM */
587 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
588 CSTORM_ASSERT_LIST_INDEX_OFFSET);
589 if (last_idx)
590 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
591
592 /* print the asserts */
593 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
594
595 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
596 CSTORM_ASSERT_LIST_OFFSET(i));
597 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
598 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
599 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
600 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
601 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
602 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
603
604 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
605 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
606 i, row3, row2, row1, row0);
607 rc++;
608 } else {
609 break;
610 }
611 }
612
613 /* USTORM */
614 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
615 USTORM_ASSERT_LIST_INDEX_OFFSET);
616 if (last_idx)
617 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
618
619 /* print the asserts */
620 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
621
622 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
623 USTORM_ASSERT_LIST_OFFSET(i));
624 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
625 USTORM_ASSERT_LIST_OFFSET(i) + 4);
626 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
627 USTORM_ASSERT_LIST_OFFSET(i) + 8);
628 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
629 USTORM_ASSERT_LIST_OFFSET(i) + 12);
630
631 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
632 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
633 i, row3, row2, row1, row0);
634 rc++;
635 } else {
636 break;
637 }
638 }
639
640 return rc;
641 }
642
643 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
644 {
645 u32 addr, val;
646 u32 mark, offset;
647 __be32 data[9];
648 int word;
649 u32 trace_shmem_base;
650 if (BP_NOMCP(bp)) {
651 BNX2X_ERR("NO MCP - can not dump\n");
652 return;
653 }
654 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
655 (bp->common.bc_ver & 0xff0000) >> 16,
656 (bp->common.bc_ver & 0xff00) >> 8,
657 (bp->common.bc_ver & 0xff));
658
659 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
660 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
661 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
662
663 if (BP_PATH(bp) == 0)
664 trace_shmem_base = bp->common.shmem_base;
665 else
666 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
667 addr = trace_shmem_base - 0x800;
668
669 /* validate TRCB signature */
670 mark = REG_RD(bp, addr);
671 if (mark != MFW_TRACE_SIGNATURE) {
672 BNX2X_ERR("Trace buffer signature is missing.");
673 return ;
674 }
675
676 /* read cyclic buffer pointer */
677 addr += 4;
678 mark = REG_RD(bp, addr);
679 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
680 + ((mark + 0x3) & ~0x3) - 0x08000000;
681 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
682
683 printk("%s", lvl);
684 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
685 for (word = 0; word < 8; word++)
686 data[word] = htonl(REG_RD(bp, offset + 4*word));
687 data[8] = 0x0;
688 pr_cont("%s", (char *)data);
689 }
690 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
691 for (word = 0; word < 8; word++)
692 data[word] = htonl(REG_RD(bp, offset + 4*word));
693 data[8] = 0x0;
694 pr_cont("%s", (char *)data);
695 }
696 printk("%s" "end of fw dump\n", lvl);
697 }
698
699 static void bnx2x_fw_dump(struct bnx2x *bp)
700 {
701 bnx2x_fw_dump_lvl(bp, KERN_ERR);
702 }
703
704 void bnx2x_panic_dump(struct bnx2x *bp)
705 {
706 int i;
707 u16 j;
708 struct hc_sp_status_block_data sp_sb_data;
709 int func = BP_FUNC(bp);
710 #ifdef BNX2X_STOP_ON_ERROR
711 u16 start = 0, end = 0;
712 u8 cos;
713 #endif
714
715 bp->stats_state = STATS_STATE_DISABLED;
716 bp->eth_stats.unrecoverable_error++;
717 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
718
719 BNX2X_ERR("begin crash dump -----------------\n");
720
721 /* Indices */
722 /* Common */
723 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
724 bp->def_idx, bp->def_att_idx, bp->attn_state,
725 bp->spq_prod_idx, bp->stats_counter);
726 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
727 bp->def_status_blk->atten_status_block.attn_bits,
728 bp->def_status_blk->atten_status_block.attn_bits_ack,
729 bp->def_status_blk->atten_status_block.status_block_id,
730 bp->def_status_blk->atten_status_block.attn_bits_index);
731 BNX2X_ERR(" def (");
732 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
733 pr_cont("0x%x%s",
734 bp->def_status_blk->sp_sb.index_values[i],
735 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
736
737 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
738 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
739 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
740 i*sizeof(u32));
741
742 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
743 sp_sb_data.igu_sb_id,
744 sp_sb_data.igu_seg_id,
745 sp_sb_data.p_func.pf_id,
746 sp_sb_data.p_func.vnic_id,
747 sp_sb_data.p_func.vf_id,
748 sp_sb_data.p_func.vf_valid,
749 sp_sb_data.state);
750
751
752 for_each_eth_queue(bp, i) {
753 struct bnx2x_fastpath *fp = &bp->fp[i];
754 int loop;
755 struct hc_status_block_data_e2 sb_data_e2;
756 struct hc_status_block_data_e1x sb_data_e1x;
757 struct hc_status_block_sm *hc_sm_p =
758 CHIP_IS_E1x(bp) ?
759 sb_data_e1x.common.state_machine :
760 sb_data_e2.common.state_machine;
761 struct hc_index_data *hc_index_p =
762 CHIP_IS_E1x(bp) ?
763 sb_data_e1x.index_data :
764 sb_data_e2.index_data;
765 u8 data_size, cos;
766 u32 *sb_data_p;
767 struct bnx2x_fp_txdata txdata;
768
769 /* Rx */
770 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
771 i, fp->rx_bd_prod, fp->rx_bd_cons,
772 fp->rx_comp_prod,
773 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
774 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
775 fp->rx_sge_prod, fp->last_max_sge,
776 le16_to_cpu(fp->fp_hc_idx));
777
778 /* Tx */
779 for_each_cos_in_tx_queue(fp, cos)
780 {
781 txdata = *fp->txdata_ptr[cos];
782 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
783 i, txdata.tx_pkt_prod,
784 txdata.tx_pkt_cons, txdata.tx_bd_prod,
785 txdata.tx_bd_cons,
786 le16_to_cpu(*txdata.tx_cons_sb));
787 }
788
789 loop = CHIP_IS_E1x(bp) ?
790 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
791
792 /* host sb data */
793
794 if (IS_FCOE_FP(fp))
795 continue;
796
797 BNX2X_ERR(" run indexes (");
798 for (j = 0; j < HC_SB_MAX_SM; j++)
799 pr_cont("0x%x%s",
800 fp->sb_running_index[j],
801 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
802
803 BNX2X_ERR(" indexes (");
804 for (j = 0; j < loop; j++)
805 pr_cont("0x%x%s",
806 fp->sb_index_values[j],
807 (j == loop - 1) ? ")" : " ");
808 /* fw sb data */
809 data_size = CHIP_IS_E1x(bp) ?
810 sizeof(struct hc_status_block_data_e1x) :
811 sizeof(struct hc_status_block_data_e2);
812 data_size /= sizeof(u32);
813 sb_data_p = CHIP_IS_E1x(bp) ?
814 (u32 *)&sb_data_e1x :
815 (u32 *)&sb_data_e2;
816 /* copy sb data in here */
817 for (j = 0; j < data_size; j++)
818 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
819 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
820 j * sizeof(u32));
821
822 if (!CHIP_IS_E1x(bp)) {
823 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
824 sb_data_e2.common.p_func.pf_id,
825 sb_data_e2.common.p_func.vf_id,
826 sb_data_e2.common.p_func.vf_valid,
827 sb_data_e2.common.p_func.vnic_id,
828 sb_data_e2.common.same_igu_sb_1b,
829 sb_data_e2.common.state);
830 } else {
831 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
832 sb_data_e1x.common.p_func.pf_id,
833 sb_data_e1x.common.p_func.vf_id,
834 sb_data_e1x.common.p_func.vf_valid,
835 sb_data_e1x.common.p_func.vnic_id,
836 sb_data_e1x.common.same_igu_sb_1b,
837 sb_data_e1x.common.state);
838 }
839
840 /* SB_SMs data */
841 for (j = 0; j < HC_SB_MAX_SM; j++) {
842 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
843 j, hc_sm_p[j].__flags,
844 hc_sm_p[j].igu_sb_id,
845 hc_sm_p[j].igu_seg_id,
846 hc_sm_p[j].time_to_expire,
847 hc_sm_p[j].timer_value);
848 }
849
850 /* Indecies data */
851 for (j = 0; j < loop; j++) {
852 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
853 hc_index_p[j].flags,
854 hc_index_p[j].timeout);
855 }
856 }
857
858 #ifdef BNX2X_STOP_ON_ERROR
859 /* Rings */
860 /* Rx */
861 for_each_valid_rx_queue(bp, i) {
862 struct bnx2x_fastpath *fp = &bp->fp[i];
863
864 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
865 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
866 for (j = start; j != end; j = RX_BD(j + 1)) {
867 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
868 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
869
870 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
871 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
872 }
873
874 start = RX_SGE(fp->rx_sge_prod);
875 end = RX_SGE(fp->last_max_sge);
876 for (j = start; j != end; j = RX_SGE(j + 1)) {
877 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
878 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
879
880 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
881 i, j, rx_sge[1], rx_sge[0], sw_page->page);
882 }
883
884 start = RCQ_BD(fp->rx_comp_cons - 10);
885 end = RCQ_BD(fp->rx_comp_cons + 503);
886 for (j = start; j != end; j = RCQ_BD(j + 1)) {
887 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
888
889 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
890 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
891 }
892 }
893
894 /* Tx */
895 for_each_valid_tx_queue(bp, i) {
896 struct bnx2x_fastpath *fp = &bp->fp[i];
897 for_each_cos_in_tx_queue(fp, cos) {
898 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
899
900 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
901 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
902 for (j = start; j != end; j = TX_BD(j + 1)) {
903 struct sw_tx_bd *sw_bd =
904 &txdata->tx_buf_ring[j];
905
906 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
907 i, cos, j, sw_bd->skb,
908 sw_bd->first_bd);
909 }
910
911 start = TX_BD(txdata->tx_bd_cons - 10);
912 end = TX_BD(txdata->tx_bd_cons + 254);
913 for (j = start; j != end; j = TX_BD(j + 1)) {
914 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
915
916 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
917 i, cos, j, tx_bd[0], tx_bd[1],
918 tx_bd[2], tx_bd[3]);
919 }
920 }
921 }
922 #endif
923 bnx2x_fw_dump(bp);
924 bnx2x_mc_assert(bp);
925 BNX2X_ERR("end crash dump -----------------\n");
926 }
927
928 /*
929 * FLR Support for E2
930 *
931 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
932 * initialization.
933 */
934 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
935 #define FLR_WAIT_INTERVAL 50 /* usec */
936 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
937
938 struct pbf_pN_buf_regs {
939 int pN;
940 u32 init_crd;
941 u32 crd;
942 u32 crd_freed;
943 };
944
945 struct pbf_pN_cmd_regs {
946 int pN;
947 u32 lines_occup;
948 u32 lines_freed;
949 };
950
951 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
952 struct pbf_pN_buf_regs *regs,
953 u32 poll_count)
954 {
955 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
956 u32 cur_cnt = poll_count;
957
958 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
959 crd = crd_start = REG_RD(bp, regs->crd);
960 init_crd = REG_RD(bp, regs->init_crd);
961
962 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
963 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
964 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
965
966 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
967 (init_crd - crd_start))) {
968 if (cur_cnt--) {
969 udelay(FLR_WAIT_INTERVAL);
970 crd = REG_RD(bp, regs->crd);
971 crd_freed = REG_RD(bp, regs->crd_freed);
972 } else {
973 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
974 regs->pN);
975 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
976 regs->pN, crd);
977 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
978 regs->pN, crd_freed);
979 break;
980 }
981 }
982 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
983 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
984 }
985
986 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
987 struct pbf_pN_cmd_regs *regs,
988 u32 poll_count)
989 {
990 u32 occup, to_free, freed, freed_start;
991 u32 cur_cnt = poll_count;
992
993 occup = to_free = REG_RD(bp, regs->lines_occup);
994 freed = freed_start = REG_RD(bp, regs->lines_freed);
995
996 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
997 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
998
999 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1000 if (cur_cnt--) {
1001 udelay(FLR_WAIT_INTERVAL);
1002 occup = REG_RD(bp, regs->lines_occup);
1003 freed = REG_RD(bp, regs->lines_freed);
1004 } else {
1005 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1006 regs->pN);
1007 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1008 regs->pN, occup);
1009 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1010 regs->pN, freed);
1011 break;
1012 }
1013 }
1014 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1015 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1016 }
1017
1018 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1019 u32 expected, u32 poll_count)
1020 {
1021 u32 cur_cnt = poll_count;
1022 u32 val;
1023
1024 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1025 udelay(FLR_WAIT_INTERVAL);
1026
1027 return val;
1028 }
1029
1030 static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1031 char *msg, u32 poll_cnt)
1032 {
1033 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1034 if (val != 0) {
1035 BNX2X_ERR("%s usage count=%d\n", msg, val);
1036 return 1;
1037 }
1038 return 0;
1039 }
1040
1041 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1042 {
1043 /* adjust polling timeout */
1044 if (CHIP_REV_IS_EMUL(bp))
1045 return FLR_POLL_CNT * 2000;
1046
1047 if (CHIP_REV_IS_FPGA(bp))
1048 return FLR_POLL_CNT * 120;
1049
1050 return FLR_POLL_CNT;
1051 }
1052
1053 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1054 {
1055 struct pbf_pN_cmd_regs cmd_regs[] = {
1056 {0, (CHIP_IS_E3B0(bp)) ?
1057 PBF_REG_TQ_OCCUPANCY_Q0 :
1058 PBF_REG_P0_TQ_OCCUPANCY,
1059 (CHIP_IS_E3B0(bp)) ?
1060 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1061 PBF_REG_P0_TQ_LINES_FREED_CNT},
1062 {1, (CHIP_IS_E3B0(bp)) ?
1063 PBF_REG_TQ_OCCUPANCY_Q1 :
1064 PBF_REG_P1_TQ_OCCUPANCY,
1065 (CHIP_IS_E3B0(bp)) ?
1066 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1067 PBF_REG_P1_TQ_LINES_FREED_CNT},
1068 {4, (CHIP_IS_E3B0(bp)) ?
1069 PBF_REG_TQ_OCCUPANCY_LB_Q :
1070 PBF_REG_P4_TQ_OCCUPANCY,
1071 (CHIP_IS_E3B0(bp)) ?
1072 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1073 PBF_REG_P4_TQ_LINES_FREED_CNT}
1074 };
1075
1076 struct pbf_pN_buf_regs buf_regs[] = {
1077 {0, (CHIP_IS_E3B0(bp)) ?
1078 PBF_REG_INIT_CRD_Q0 :
1079 PBF_REG_P0_INIT_CRD ,
1080 (CHIP_IS_E3B0(bp)) ?
1081 PBF_REG_CREDIT_Q0 :
1082 PBF_REG_P0_CREDIT,
1083 (CHIP_IS_E3B0(bp)) ?
1084 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1085 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1086 {1, (CHIP_IS_E3B0(bp)) ?
1087 PBF_REG_INIT_CRD_Q1 :
1088 PBF_REG_P1_INIT_CRD,
1089 (CHIP_IS_E3B0(bp)) ?
1090 PBF_REG_CREDIT_Q1 :
1091 PBF_REG_P1_CREDIT,
1092 (CHIP_IS_E3B0(bp)) ?
1093 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1094 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1095 {4, (CHIP_IS_E3B0(bp)) ?
1096 PBF_REG_INIT_CRD_LB_Q :
1097 PBF_REG_P4_INIT_CRD,
1098 (CHIP_IS_E3B0(bp)) ?
1099 PBF_REG_CREDIT_LB_Q :
1100 PBF_REG_P4_CREDIT,
1101 (CHIP_IS_E3B0(bp)) ?
1102 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1103 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1104 };
1105
1106 int i;
1107
1108 /* Verify the command queues are flushed P0, P1, P4 */
1109 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1110 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1111
1112
1113 /* Verify the transmission buffers are flushed P0, P1, P4 */
1114 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1115 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1116 }
1117
1118 #define OP_GEN_PARAM(param) \
1119 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1120
1121 #define OP_GEN_TYPE(type) \
1122 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1123
1124 #define OP_GEN_AGG_VECT(index) \
1125 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1126
1127
1128 static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1129 u32 poll_cnt)
1130 {
1131 struct sdm_op_gen op_gen = {0};
1132
1133 u32 comp_addr = BAR_CSTRORM_INTMEM +
1134 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1135 int ret = 0;
1136
1137 if (REG_RD(bp, comp_addr)) {
1138 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1139 return 1;
1140 }
1141
1142 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1143 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1144 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1145 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1146
1147 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1148 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1149
1150 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1151 BNX2X_ERR("FW final cleanup did not succeed\n");
1152 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1153 (REG_RD(bp, comp_addr)));
1154 ret = 1;
1155 }
1156 /* Zero completion for nxt FLR */
1157 REG_WR(bp, comp_addr, 0);
1158
1159 return ret;
1160 }
1161
1162 static u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1163 {
1164 u16 status;
1165
1166 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1167 return status & PCI_EXP_DEVSTA_TRPND;
1168 }
1169
1170 /* PF FLR specific routines
1171 */
1172 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1173 {
1174
1175 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1176 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1177 CFC_REG_NUM_LCIDS_INSIDE_PF,
1178 "CFC PF usage counter timed out",
1179 poll_cnt))
1180 return 1;
1181
1182
1183 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1184 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1185 DORQ_REG_PF_USAGE_CNT,
1186 "DQ PF usage counter timed out",
1187 poll_cnt))
1188 return 1;
1189
1190 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1191 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1192 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1193 "QM PF usage counter timed out",
1194 poll_cnt))
1195 return 1;
1196
1197 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1198 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1199 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1200 "Timers VNIC usage counter timed out",
1201 poll_cnt))
1202 return 1;
1203 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1204 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1205 "Timers NUM_SCANS usage counter timed out",
1206 poll_cnt))
1207 return 1;
1208
1209 /* Wait DMAE PF usage counter to zero */
1210 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1211 dmae_reg_go_c[INIT_DMAE_C(bp)],
1212 "DMAE dommand register timed out",
1213 poll_cnt))
1214 return 1;
1215
1216 return 0;
1217 }
1218
1219 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1220 {
1221 u32 val;
1222
1223 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1224 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1225
1226 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1227 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1228
1229 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1230 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1231
1232 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1233 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1234
1235 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1236 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1237
1238 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1239 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1240
1241 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1242 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1243
1244 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1245 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1246 val);
1247 }
1248
1249 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1250 {
1251 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1252
1253 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1254
1255 /* Re-enable PF target read access */
1256 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1257
1258 /* Poll HW usage counters */
1259 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1260 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1261 return -EBUSY;
1262
1263 /* Zero the igu 'trailing edge' and 'leading edge' */
1264
1265 /* Send the FW cleanup command */
1266 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1267 return -EBUSY;
1268
1269 /* ATC cleanup */
1270
1271 /* Verify TX hw is flushed */
1272 bnx2x_tx_hw_flushed(bp, poll_cnt);
1273
1274 /* Wait 100ms (not adjusted according to platform) */
1275 msleep(100);
1276
1277 /* Verify no pending pci transactions */
1278 if (bnx2x_is_pcie_pending(bp->pdev))
1279 BNX2X_ERR("PCIE Transactions still pending\n");
1280
1281 /* Debug */
1282 bnx2x_hw_enable_status(bp);
1283
1284 /*
1285 * Master enable - Due to WB DMAE writes performed before this
1286 * register is re-initialized as part of the regular function init
1287 */
1288 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1289
1290 return 0;
1291 }
1292
1293 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1294 {
1295 int port = BP_PORT(bp);
1296 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1297 u32 val = REG_RD(bp, addr);
1298 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1299 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1300 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1301
1302 if (msix) {
1303 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1304 HC_CONFIG_0_REG_INT_LINE_EN_0);
1305 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1306 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1307 if (single_msix)
1308 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1309 } else if (msi) {
1310 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1311 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1312 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1313 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1314 } else {
1315 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1316 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1317 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1318 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1319
1320 if (!CHIP_IS_E1(bp)) {
1321 DP(NETIF_MSG_IFUP,
1322 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1323
1324 REG_WR(bp, addr, val);
1325
1326 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1327 }
1328 }
1329
1330 if (CHIP_IS_E1(bp))
1331 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1332
1333 DP(NETIF_MSG_IFUP,
1334 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1335 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1336
1337 REG_WR(bp, addr, val);
1338 /*
1339 * Ensure that HC_CONFIG is written before leading/trailing edge config
1340 */
1341 mmiowb();
1342 barrier();
1343
1344 if (!CHIP_IS_E1(bp)) {
1345 /* init leading/trailing edge */
1346 if (IS_MF(bp)) {
1347 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1348 if (bp->port.pmf)
1349 /* enable nig and gpio3 attention */
1350 val |= 0x1100;
1351 } else
1352 val = 0xffff;
1353
1354 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1355 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1356 }
1357
1358 /* Make sure that interrupts are indeed enabled from here on */
1359 mmiowb();
1360 }
1361
1362 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1363 {
1364 u32 val;
1365 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1366 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1367 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1368
1369 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1370
1371 if (msix) {
1372 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1373 IGU_PF_CONF_SINGLE_ISR_EN);
1374 val |= (IGU_PF_CONF_FUNC_EN |
1375 IGU_PF_CONF_MSI_MSIX_EN |
1376 IGU_PF_CONF_ATTN_BIT_EN);
1377
1378 if (single_msix)
1379 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1380 } else if (msi) {
1381 val &= ~IGU_PF_CONF_INT_LINE_EN;
1382 val |= (IGU_PF_CONF_FUNC_EN |
1383 IGU_PF_CONF_MSI_MSIX_EN |
1384 IGU_PF_CONF_ATTN_BIT_EN |
1385 IGU_PF_CONF_SINGLE_ISR_EN);
1386 } else {
1387 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1388 val |= (IGU_PF_CONF_FUNC_EN |
1389 IGU_PF_CONF_INT_LINE_EN |
1390 IGU_PF_CONF_ATTN_BIT_EN |
1391 IGU_PF_CONF_SINGLE_ISR_EN);
1392 }
1393
1394 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1395 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1396
1397 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1398
1399 if (val & IGU_PF_CONF_INT_LINE_EN)
1400 pci_intx(bp->pdev, true);
1401
1402 barrier();
1403
1404 /* init leading/trailing edge */
1405 if (IS_MF(bp)) {
1406 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1407 if (bp->port.pmf)
1408 /* enable nig and gpio3 attention */
1409 val |= 0x1100;
1410 } else
1411 val = 0xffff;
1412
1413 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1414 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1415
1416 /* Make sure that interrupts are indeed enabled from here on */
1417 mmiowb();
1418 }
1419
1420 void bnx2x_int_enable(struct bnx2x *bp)
1421 {
1422 if (bp->common.int_block == INT_BLOCK_HC)
1423 bnx2x_hc_int_enable(bp);
1424 else
1425 bnx2x_igu_int_enable(bp);
1426 }
1427
1428 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1429 {
1430 int port = BP_PORT(bp);
1431 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1432 u32 val = REG_RD(bp, addr);
1433
1434 /*
1435 * in E1 we must use only PCI configuration space to disable
1436 * MSI/MSIX capablility
1437 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1438 */
1439 if (CHIP_IS_E1(bp)) {
1440 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1441 * Use mask register to prevent from HC sending interrupts
1442 * after we exit the function
1443 */
1444 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1445
1446 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1447 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1448 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1449 } else
1450 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1451 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1452 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1453 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1454
1455 DP(NETIF_MSG_IFDOWN,
1456 "write %x to HC %d (addr 0x%x)\n",
1457 val, port, addr);
1458
1459 /* flush all outstanding writes */
1460 mmiowb();
1461
1462 REG_WR(bp, addr, val);
1463 if (REG_RD(bp, addr) != val)
1464 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1465 }
1466
1467 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1468 {
1469 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1470
1471 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1472 IGU_PF_CONF_INT_LINE_EN |
1473 IGU_PF_CONF_ATTN_BIT_EN);
1474
1475 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
1476
1477 /* flush all outstanding writes */
1478 mmiowb();
1479
1480 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1481 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1482 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1483 }
1484
1485 void bnx2x_int_disable(struct bnx2x *bp)
1486 {
1487 if (bp->common.int_block == INT_BLOCK_HC)
1488 bnx2x_hc_int_disable(bp);
1489 else
1490 bnx2x_igu_int_disable(bp);
1491 }
1492
1493 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1494 {
1495 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1496 int i, offset;
1497
1498 if (disable_hw)
1499 /* prevent the HW from sending interrupts */
1500 bnx2x_int_disable(bp);
1501
1502 /* make sure all ISRs are done */
1503 if (msix) {
1504 synchronize_irq(bp->msix_table[0].vector);
1505 offset = 1;
1506 if (CNIC_SUPPORT(bp))
1507 offset++;
1508 for_each_eth_queue(bp, i)
1509 synchronize_irq(bp->msix_table[offset++].vector);
1510 } else
1511 synchronize_irq(bp->pdev->irq);
1512
1513 /* make sure sp_task is not running */
1514 cancel_delayed_work(&bp->sp_task);
1515 cancel_delayed_work(&bp->period_task);
1516 flush_workqueue(bnx2x_wq);
1517 }
1518
1519 /* fast path */
1520
1521 /*
1522 * General service functions
1523 */
1524
1525 /* Return true if succeeded to acquire the lock */
1526 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1527 {
1528 u32 lock_status;
1529 u32 resource_bit = (1 << resource);
1530 int func = BP_FUNC(bp);
1531 u32 hw_lock_control_reg;
1532
1533 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1534 "Trying to take a lock on resource %d\n", resource);
1535
1536 /* Validating that the resource is within range */
1537 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1538 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1539 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1540 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1541 return false;
1542 }
1543
1544 if (func <= 5)
1545 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1546 else
1547 hw_lock_control_reg =
1548 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1549
1550 /* Try to acquire the lock */
1551 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1552 lock_status = REG_RD(bp, hw_lock_control_reg);
1553 if (lock_status & resource_bit)
1554 return true;
1555
1556 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1557 "Failed to get a lock on resource %d\n", resource);
1558 return false;
1559 }
1560
1561 /**
1562 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1563 *
1564 * @bp: driver handle
1565 *
1566 * Returns the recovery leader resource id according to the engine this function
1567 * belongs to. Currently only only 2 engines is supported.
1568 */
1569 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1570 {
1571 if (BP_PATH(bp))
1572 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1573 else
1574 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1575 }
1576
1577 /**
1578 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1579 *
1580 * @bp: driver handle
1581 *
1582 * Tries to aquire a leader lock for current engine.
1583 */
1584 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1585 {
1586 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1587 }
1588
1589 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1590
1591
1592 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1593 {
1594 struct bnx2x *bp = fp->bp;
1595 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1596 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1597 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1598 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1599
1600 DP(BNX2X_MSG_SP,
1601 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1602 fp->index, cid, command, bp->state,
1603 rr_cqe->ramrod_cqe.ramrod_type);
1604
1605 switch (command) {
1606 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1607 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1608 drv_cmd = BNX2X_Q_CMD_UPDATE;
1609 break;
1610
1611 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1612 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1613 drv_cmd = BNX2X_Q_CMD_SETUP;
1614 break;
1615
1616 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1617 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1618 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1619 break;
1620
1621 case (RAMROD_CMD_ID_ETH_HALT):
1622 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1623 drv_cmd = BNX2X_Q_CMD_HALT;
1624 break;
1625
1626 case (RAMROD_CMD_ID_ETH_TERMINATE):
1627 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1628 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1629 break;
1630
1631 case (RAMROD_CMD_ID_ETH_EMPTY):
1632 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1633 drv_cmd = BNX2X_Q_CMD_EMPTY;
1634 break;
1635
1636 default:
1637 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1638 command, fp->index);
1639 return;
1640 }
1641
1642 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1643 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1644 /* q_obj->complete_cmd() failure means that this was
1645 * an unexpected completion.
1646 *
1647 * In this case we don't want to increase the bp->spq_left
1648 * because apparently we haven't sent this command the first
1649 * place.
1650 */
1651 #ifdef BNX2X_STOP_ON_ERROR
1652 bnx2x_panic();
1653 #else
1654 return;
1655 #endif
1656
1657 smp_mb__before_atomic_inc();
1658 atomic_inc(&bp->cq_spq_left);
1659 /* push the change in bp->spq_left and towards the memory */
1660 smp_mb__after_atomic_inc();
1661
1662 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1663
1664 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1665 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1666 /* if Q update ramrod is completed for last Q in AFEX vif set
1667 * flow, then ACK MCP at the end
1668 *
1669 * mark pending ACK to MCP bit.
1670 * prevent case that both bits are cleared.
1671 * At the end of load/unload driver checks that
1672 * sp_state is cleaerd, and this order prevents
1673 * races
1674 */
1675 smp_mb__before_clear_bit();
1676 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1677 wmb();
1678 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1679 smp_mb__after_clear_bit();
1680
1681 /* schedule workqueue to send ack to MCP */
1682 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1683 }
1684
1685 return;
1686 }
1687
1688 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1689 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1690 {
1691 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1692
1693 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1694 start);
1695 }
1696
1697 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1698 {
1699 struct bnx2x *bp = netdev_priv(dev_instance);
1700 u16 status = bnx2x_ack_int(bp);
1701 u16 mask;
1702 int i;
1703 u8 cos;
1704
1705 /* Return here if interrupt is shared and it's not for us */
1706 if (unlikely(status == 0)) {
1707 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1708 return IRQ_NONE;
1709 }
1710 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1711
1712 #ifdef BNX2X_STOP_ON_ERROR
1713 if (unlikely(bp->panic))
1714 return IRQ_HANDLED;
1715 #endif
1716
1717 for_each_eth_queue(bp, i) {
1718 struct bnx2x_fastpath *fp = &bp->fp[i];
1719
1720 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1721 if (status & mask) {
1722 /* Handle Rx or Tx according to SB id */
1723 prefetch(fp->rx_cons_sb);
1724 for_each_cos_in_tx_queue(fp, cos)
1725 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1726 prefetch(&fp->sb_running_index[SM_RX_ID]);
1727 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1728 status &= ~mask;
1729 }
1730 }
1731
1732 if (CNIC_SUPPORT(bp)) {
1733 mask = 0x2;
1734 if (status & (mask | 0x1)) {
1735 struct cnic_ops *c_ops = NULL;
1736
1737 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1738 rcu_read_lock();
1739 c_ops = rcu_dereference(bp->cnic_ops);
1740 if (c_ops)
1741 c_ops->cnic_handler(bp->cnic_data,
1742 NULL);
1743 rcu_read_unlock();
1744 }
1745
1746 status &= ~mask;
1747 }
1748 }
1749
1750 if (unlikely(status & 0x1)) {
1751 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1752
1753 status &= ~0x1;
1754 if (!status)
1755 return IRQ_HANDLED;
1756 }
1757
1758 if (unlikely(status))
1759 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1760 status);
1761
1762 return IRQ_HANDLED;
1763 }
1764
1765 /* Link */
1766
1767 /*
1768 * General service functions
1769 */
1770
1771 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1772 {
1773 u32 lock_status;
1774 u32 resource_bit = (1 << resource);
1775 int func = BP_FUNC(bp);
1776 u32 hw_lock_control_reg;
1777 int cnt;
1778
1779 /* Validating that the resource is within range */
1780 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1781 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1782 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1783 return -EINVAL;
1784 }
1785
1786 if (func <= 5) {
1787 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1788 } else {
1789 hw_lock_control_reg =
1790 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1791 }
1792
1793 /* Validating that the resource is not already taken */
1794 lock_status = REG_RD(bp, hw_lock_control_reg);
1795 if (lock_status & resource_bit) {
1796 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1797 lock_status, resource_bit);
1798 return -EEXIST;
1799 }
1800
1801 /* Try for 5 second every 5ms */
1802 for (cnt = 0; cnt < 1000; cnt++) {
1803 /* Try to acquire the lock */
1804 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1805 lock_status = REG_RD(bp, hw_lock_control_reg);
1806 if (lock_status & resource_bit)
1807 return 0;
1808
1809 msleep(5);
1810 }
1811 BNX2X_ERR("Timeout\n");
1812 return -EAGAIN;
1813 }
1814
1815 int bnx2x_release_leader_lock(struct bnx2x *bp)
1816 {
1817 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1818 }
1819
1820 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1821 {
1822 u32 lock_status;
1823 u32 resource_bit = (1 << resource);
1824 int func = BP_FUNC(bp);
1825 u32 hw_lock_control_reg;
1826
1827 /* Validating that the resource is within range */
1828 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1829 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1830 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1831 return -EINVAL;
1832 }
1833
1834 if (func <= 5) {
1835 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1836 } else {
1837 hw_lock_control_reg =
1838 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1839 }
1840
1841 /* Validating that the resource is currently taken */
1842 lock_status = REG_RD(bp, hw_lock_control_reg);
1843 if (!(lock_status & resource_bit)) {
1844 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1845 lock_status, resource_bit);
1846 return -EFAULT;
1847 }
1848
1849 REG_WR(bp, hw_lock_control_reg, resource_bit);
1850 return 0;
1851 }
1852
1853
1854 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1855 {
1856 /* The GPIO should be swapped if swap register is set and active */
1857 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1858 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1859 int gpio_shift = gpio_num +
1860 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1861 u32 gpio_mask = (1 << gpio_shift);
1862 u32 gpio_reg;
1863 int value;
1864
1865 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1866 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1867 return -EINVAL;
1868 }
1869
1870 /* read GPIO value */
1871 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1872
1873 /* get the requested pin value */
1874 if ((gpio_reg & gpio_mask) == gpio_mask)
1875 value = 1;
1876 else
1877 value = 0;
1878
1879 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1880
1881 return value;
1882 }
1883
1884 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1885 {
1886 /* The GPIO should be swapped if swap register is set and active */
1887 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1888 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1889 int gpio_shift = gpio_num +
1890 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1891 u32 gpio_mask = (1 << gpio_shift);
1892 u32 gpio_reg;
1893
1894 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1895 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1896 return -EINVAL;
1897 }
1898
1899 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1900 /* read GPIO and mask except the float bits */
1901 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1902
1903 switch (mode) {
1904 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1905 DP(NETIF_MSG_LINK,
1906 "Set GPIO %d (shift %d) -> output low\n",
1907 gpio_num, gpio_shift);
1908 /* clear FLOAT and set CLR */
1909 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1910 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1911 break;
1912
1913 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1914 DP(NETIF_MSG_LINK,
1915 "Set GPIO %d (shift %d) -> output high\n",
1916 gpio_num, gpio_shift);
1917 /* clear FLOAT and set SET */
1918 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1919 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1920 break;
1921
1922 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1923 DP(NETIF_MSG_LINK,
1924 "Set GPIO %d (shift %d) -> input\n",
1925 gpio_num, gpio_shift);
1926 /* set FLOAT */
1927 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1928 break;
1929
1930 default:
1931 break;
1932 }
1933
1934 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1935 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1936
1937 return 0;
1938 }
1939
1940 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1941 {
1942 u32 gpio_reg = 0;
1943 int rc = 0;
1944
1945 /* Any port swapping should be handled by caller. */
1946
1947 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1948 /* read GPIO and mask except the float bits */
1949 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1950 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1951 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1952 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1953
1954 switch (mode) {
1955 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1956 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
1957 /* set CLR */
1958 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
1959 break;
1960
1961 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1962 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
1963 /* set SET */
1964 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
1965 break;
1966
1967 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1968 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
1969 /* set FLOAT */
1970 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1971 break;
1972
1973 default:
1974 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
1975 rc = -EINVAL;
1976 break;
1977 }
1978
1979 if (rc == 0)
1980 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1981
1982 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1983
1984 return rc;
1985 }
1986
1987 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1988 {
1989 /* The GPIO should be swapped if swap register is set and active */
1990 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1991 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1992 int gpio_shift = gpio_num +
1993 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1994 u32 gpio_mask = (1 << gpio_shift);
1995 u32 gpio_reg;
1996
1997 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1998 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1999 return -EINVAL;
2000 }
2001
2002 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2003 /* read GPIO int */
2004 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2005
2006 switch (mode) {
2007 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2008 DP(NETIF_MSG_LINK,
2009 "Clear GPIO INT %d (shift %d) -> output low\n",
2010 gpio_num, gpio_shift);
2011 /* clear SET and set CLR */
2012 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2013 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2014 break;
2015
2016 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2017 DP(NETIF_MSG_LINK,
2018 "Set GPIO INT %d (shift %d) -> output high\n",
2019 gpio_num, gpio_shift);
2020 /* clear CLR and set SET */
2021 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2022 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2023 break;
2024
2025 default:
2026 break;
2027 }
2028
2029 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2030 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2031
2032 return 0;
2033 }
2034
2035 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2036 {
2037 u32 spio_mask = (1 << spio_num);
2038 u32 spio_reg;
2039
2040 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2041 (spio_num > MISC_REGISTERS_SPIO_7)) {
2042 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2043 return -EINVAL;
2044 }
2045
2046 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2047 /* read SPIO and mask except the float bits */
2048 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2049
2050 switch (mode) {
2051 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2052 DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num);
2053 /* clear FLOAT and set CLR */
2054 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2055 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2056 break;
2057
2058 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2059 DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num);
2060 /* clear FLOAT and set SET */
2061 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2062 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2063 break;
2064
2065 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2066 DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num);
2067 /* set FLOAT */
2068 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2069 break;
2070
2071 default:
2072 break;
2073 }
2074
2075 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2076 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2077
2078 return 0;
2079 }
2080
2081 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2082 {
2083 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2084 switch (bp->link_vars.ieee_fc &
2085 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2086 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2087 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2088 ADVERTISED_Pause);
2089 break;
2090
2091 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2092 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2093 ADVERTISED_Pause);
2094 break;
2095
2096 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2097 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2098 break;
2099
2100 default:
2101 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2102 ADVERTISED_Pause);
2103 break;
2104 }
2105 }
2106
2107 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2108 {
2109 if (!BP_NOMCP(bp)) {
2110 u8 rc;
2111 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2112 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2113 /*
2114 * Initialize link parameters structure variables
2115 * It is recommended to turn off RX FC for jumbo frames
2116 * for better performance
2117 */
2118 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2119 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2120 else
2121 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2122
2123 bnx2x_acquire_phy_lock(bp);
2124
2125 if (load_mode == LOAD_DIAG) {
2126 struct link_params *lp = &bp->link_params;
2127 lp->loopback_mode = LOOPBACK_XGXS;
2128 /* do PHY loopback at 10G speed, if possible */
2129 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2130 if (lp->speed_cap_mask[cfx_idx] &
2131 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2132 lp->req_line_speed[cfx_idx] =
2133 SPEED_10000;
2134 else
2135 lp->req_line_speed[cfx_idx] =
2136 SPEED_1000;
2137 }
2138 }
2139
2140 if (load_mode == LOAD_LOOPBACK_EXT) {
2141 struct link_params *lp = &bp->link_params;
2142 lp->loopback_mode = LOOPBACK_EXT;
2143 }
2144
2145 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2146
2147 bnx2x_release_phy_lock(bp);
2148
2149 bnx2x_calc_fc_adv(bp);
2150
2151 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2152 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2153 bnx2x_link_report(bp);
2154 } else
2155 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2156 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2157 return rc;
2158 }
2159 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2160 return -EINVAL;
2161 }
2162
2163 void bnx2x_link_set(struct bnx2x *bp)
2164 {
2165 if (!BP_NOMCP(bp)) {
2166 bnx2x_acquire_phy_lock(bp);
2167 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2168 bnx2x_release_phy_lock(bp);
2169
2170 bnx2x_calc_fc_adv(bp);
2171 } else
2172 BNX2X_ERR("Bootcode is missing - can not set link\n");
2173 }
2174
2175 static void bnx2x__link_reset(struct bnx2x *bp)
2176 {
2177 if (!BP_NOMCP(bp)) {
2178 bnx2x_acquire_phy_lock(bp);
2179 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2180 bnx2x_release_phy_lock(bp);
2181 } else
2182 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2183 }
2184
2185 void bnx2x_force_link_reset(struct bnx2x *bp)
2186 {
2187 bnx2x_acquire_phy_lock(bp);
2188 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2189 bnx2x_release_phy_lock(bp);
2190 }
2191
2192 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2193 {
2194 u8 rc = 0;
2195
2196 if (!BP_NOMCP(bp)) {
2197 bnx2x_acquire_phy_lock(bp);
2198 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2199 is_serdes);
2200 bnx2x_release_phy_lock(bp);
2201 } else
2202 BNX2X_ERR("Bootcode is missing - can not test link\n");
2203
2204 return rc;
2205 }
2206
2207
2208 /* Calculates the sum of vn_min_rates.
2209 It's needed for further normalizing of the min_rates.
2210 Returns:
2211 sum of vn_min_rates.
2212 or
2213 0 - if all the min_rates are 0.
2214 In the later case fainess algorithm should be deactivated.
2215 If not all min_rates are zero then those that are zeroes will be set to 1.
2216 */
2217 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2218 struct cmng_init_input *input)
2219 {
2220 int all_zero = 1;
2221 int vn;
2222
2223 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2224 u32 vn_cfg = bp->mf_config[vn];
2225 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2226 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2227
2228 /* Skip hidden vns */
2229 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2230 vn_min_rate = 0;
2231 /* If min rate is zero - set it to 1 */
2232 else if (!vn_min_rate)
2233 vn_min_rate = DEF_MIN_RATE;
2234 else
2235 all_zero = 0;
2236
2237 input->vnic_min_rate[vn] = vn_min_rate;
2238 }
2239
2240 /* if ETS or all min rates are zeros - disable fairness */
2241 if (BNX2X_IS_ETS_ENABLED(bp)) {
2242 input->flags.cmng_enables &=
2243 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2244 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2245 } else if (all_zero) {
2246 input->flags.cmng_enables &=
2247 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2248 DP(NETIF_MSG_IFUP,
2249 "All MIN values are zeroes fairness will be disabled\n");
2250 } else
2251 input->flags.cmng_enables |=
2252 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2253 }
2254
2255 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2256 struct cmng_init_input *input)
2257 {
2258 u16 vn_max_rate;
2259 u32 vn_cfg = bp->mf_config[vn];
2260
2261 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2262 vn_max_rate = 0;
2263 else {
2264 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2265
2266 if (IS_MF_SI(bp)) {
2267 /* maxCfg in percents of linkspeed */
2268 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2269 } else /* SD modes */
2270 /* maxCfg is absolute in 100Mb units */
2271 vn_max_rate = maxCfg * 100;
2272 }
2273
2274 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2275
2276 input->vnic_max_rate[vn] = vn_max_rate;
2277 }
2278
2279
2280 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2281 {
2282 if (CHIP_REV_IS_SLOW(bp))
2283 return CMNG_FNS_NONE;
2284 if (IS_MF(bp))
2285 return CMNG_FNS_MINMAX;
2286
2287 return CMNG_FNS_NONE;
2288 }
2289
2290 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2291 {
2292 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2293
2294 if (BP_NOMCP(bp))
2295 return; /* what should be the default bvalue in this case */
2296
2297 /* For 2 port configuration the absolute function number formula
2298 * is:
2299 * abs_func = 2 * vn + BP_PORT + BP_PATH
2300 *
2301 * and there are 4 functions per port
2302 *
2303 * For 4 port configuration it is
2304 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2305 *
2306 * and there are 2 functions per port
2307 */
2308 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2309 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2310
2311 if (func >= E1H_FUNC_MAX)
2312 break;
2313
2314 bp->mf_config[vn] =
2315 MF_CFG_RD(bp, func_mf_config[func].config);
2316 }
2317 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2318 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2319 bp->flags |= MF_FUNC_DIS;
2320 } else {
2321 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2322 bp->flags &= ~MF_FUNC_DIS;
2323 }
2324 }
2325
2326 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2327 {
2328 struct cmng_init_input input;
2329 memset(&input, 0, sizeof(struct cmng_init_input));
2330
2331 input.port_rate = bp->link_vars.line_speed;
2332
2333 if (cmng_type == CMNG_FNS_MINMAX) {
2334 int vn;
2335
2336 /* read mf conf from shmem */
2337 if (read_cfg)
2338 bnx2x_read_mf_cfg(bp);
2339
2340 /* vn_weight_sum and enable fairness if not 0 */
2341 bnx2x_calc_vn_min(bp, &input);
2342
2343 /* calculate and set min-max rate for each vn */
2344 if (bp->port.pmf)
2345 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2346 bnx2x_calc_vn_max(bp, vn, &input);
2347
2348 /* always enable rate shaping and fairness */
2349 input.flags.cmng_enables |=
2350 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2351
2352 bnx2x_init_cmng(&input, &bp->cmng);
2353 return;
2354 }
2355
2356 /* rate shaping and fairness are disabled */
2357 DP(NETIF_MSG_IFUP,
2358 "rate shaping and fairness are disabled\n");
2359 }
2360
2361 static void storm_memset_cmng(struct bnx2x *bp,
2362 struct cmng_init *cmng,
2363 u8 port)
2364 {
2365 int vn;
2366 size_t size = sizeof(struct cmng_struct_per_port);
2367
2368 u32 addr = BAR_XSTRORM_INTMEM +
2369 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2370
2371 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2372
2373 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2374 int func = func_by_vn(bp, vn);
2375
2376 addr = BAR_XSTRORM_INTMEM +
2377 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2378 size = sizeof(struct rate_shaping_vars_per_vn);
2379 __storm_memset_struct(bp, addr, size,
2380 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2381
2382 addr = BAR_XSTRORM_INTMEM +
2383 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2384 size = sizeof(struct fairness_vars_per_vn);
2385 __storm_memset_struct(bp, addr, size,
2386 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2387 }
2388 }
2389
2390 /* This function is called upon link interrupt */
2391 static void bnx2x_link_attn(struct bnx2x *bp)
2392 {
2393 /* Make sure that we are synced with the current statistics */
2394 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2395
2396 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2397
2398 if (bp->link_vars.link_up) {
2399
2400 /* dropless flow control */
2401 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2402 int port = BP_PORT(bp);
2403 u32 pause_enabled = 0;
2404
2405 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2406 pause_enabled = 1;
2407
2408 REG_WR(bp, BAR_USTRORM_INTMEM +
2409 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2410 pause_enabled);
2411 }
2412
2413 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2414 struct host_port_stats *pstats;
2415
2416 pstats = bnx2x_sp(bp, port_stats);
2417 /* reset old mac stats */
2418 memset(&(pstats->mac_stx[0]), 0,
2419 sizeof(struct mac_stx));
2420 }
2421 if (bp->state == BNX2X_STATE_OPEN)
2422 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2423 }
2424
2425 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2426 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2427
2428 if (cmng_fns != CMNG_FNS_NONE) {
2429 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2430 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2431 } else
2432 /* rate shaping and fairness are disabled */
2433 DP(NETIF_MSG_IFUP,
2434 "single function mode without fairness\n");
2435 }
2436
2437 __bnx2x_link_report(bp);
2438
2439 if (IS_MF(bp))
2440 bnx2x_link_sync_notify(bp);
2441 }
2442
2443 void bnx2x__link_status_update(struct bnx2x *bp)
2444 {
2445 if (bp->state != BNX2X_STATE_OPEN)
2446 return;
2447
2448 /* read updated dcb configuration */
2449 bnx2x_dcbx_pmf_update(bp);
2450
2451 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2452
2453 if (bp->link_vars.link_up)
2454 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2455 else
2456 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2457
2458 /* indicate link status */
2459 bnx2x_link_report(bp);
2460 }
2461
2462 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2463 u16 vlan_val, u8 allowed_prio)
2464 {
2465 struct bnx2x_func_state_params func_params = {0};
2466 struct bnx2x_func_afex_update_params *f_update_params =
2467 &func_params.params.afex_update;
2468
2469 func_params.f_obj = &bp->func_obj;
2470 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2471
2472 /* no need to wait for RAMROD completion, so don't
2473 * set RAMROD_COMP_WAIT flag
2474 */
2475
2476 f_update_params->vif_id = vifid;
2477 f_update_params->afex_default_vlan = vlan_val;
2478 f_update_params->allowed_priorities = allowed_prio;
2479
2480 /* if ramrod can not be sent, response to MCP immediately */
2481 if (bnx2x_func_state_change(bp, &func_params) < 0)
2482 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2483
2484 return 0;
2485 }
2486
2487 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2488 u16 vif_index, u8 func_bit_map)
2489 {
2490 struct bnx2x_func_state_params func_params = {0};
2491 struct bnx2x_func_afex_viflists_params *update_params =
2492 &func_params.params.afex_viflists;
2493 int rc;
2494 u32 drv_msg_code;
2495
2496 /* validate only LIST_SET and LIST_GET are received from switch */
2497 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2498 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2499 cmd_type);
2500
2501 func_params.f_obj = &bp->func_obj;
2502 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2503
2504 /* set parameters according to cmd_type */
2505 update_params->afex_vif_list_command = cmd_type;
2506 update_params->vif_list_index = cpu_to_le16(vif_index);
2507 update_params->func_bit_map =
2508 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2509 update_params->func_to_clear = 0;
2510 drv_msg_code =
2511 (cmd_type == VIF_LIST_RULE_GET) ?
2512 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2513 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2514
2515 /* if ramrod can not be sent, respond to MCP immediately for
2516 * SET and GET requests (other are not triggered from MCP)
2517 */
2518 rc = bnx2x_func_state_change(bp, &func_params);
2519 if (rc < 0)
2520 bnx2x_fw_command(bp, drv_msg_code, 0);
2521
2522 return 0;
2523 }
2524
2525 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2526 {
2527 struct afex_stats afex_stats;
2528 u32 func = BP_ABS_FUNC(bp);
2529 u32 mf_config;
2530 u16 vlan_val;
2531 u32 vlan_prio;
2532 u16 vif_id;
2533 u8 allowed_prio;
2534 u8 vlan_mode;
2535 u32 addr_to_write, vifid, addrs, stats_type, i;
2536
2537 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2538 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2539 DP(BNX2X_MSG_MCP,
2540 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2541 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2542 }
2543
2544 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2545 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2546 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2547 DP(BNX2X_MSG_MCP,
2548 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2549 vifid, addrs);
2550 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2551 addrs);
2552 }
2553
2554 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2555 addr_to_write = SHMEM2_RD(bp,
2556 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2557 stats_type = SHMEM2_RD(bp,
2558 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2559
2560 DP(BNX2X_MSG_MCP,
2561 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2562 addr_to_write);
2563
2564 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2565
2566 /* write response to scratchpad, for MCP */
2567 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2568 REG_WR(bp, addr_to_write + i*sizeof(u32),
2569 *(((u32 *)(&afex_stats))+i));
2570
2571 /* send ack message to MCP */
2572 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2573 }
2574
2575 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2576 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2577 bp->mf_config[BP_VN(bp)] = mf_config;
2578 DP(BNX2X_MSG_MCP,
2579 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2580 mf_config);
2581
2582 /* if VIF_SET is "enabled" */
2583 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2584 /* set rate limit directly to internal RAM */
2585 struct cmng_init_input cmng_input;
2586 struct rate_shaping_vars_per_vn m_rs_vn;
2587 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2588 u32 addr = BAR_XSTRORM_INTMEM +
2589 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2590
2591 bp->mf_config[BP_VN(bp)] = mf_config;
2592
2593 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2594 m_rs_vn.vn_counter.rate =
2595 cmng_input.vnic_max_rate[BP_VN(bp)];
2596 m_rs_vn.vn_counter.quota =
2597 (m_rs_vn.vn_counter.rate *
2598 RS_PERIODIC_TIMEOUT_USEC) / 8;
2599
2600 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2601
2602 /* read relevant values from mf_cfg struct in shmem */
2603 vif_id =
2604 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2605 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2606 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2607 vlan_val =
2608 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2609 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2610 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2611 vlan_prio = (mf_config &
2612 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2613 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2614 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2615 vlan_mode =
2616 (MF_CFG_RD(bp,
2617 func_mf_config[func].afex_config) &
2618 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2619 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2620 allowed_prio =
2621 (MF_CFG_RD(bp,
2622 func_mf_config[func].afex_config) &
2623 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2624 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2625
2626 /* send ramrod to FW, return in case of failure */
2627 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2628 allowed_prio))
2629 return;
2630
2631 bp->afex_def_vlan_tag = vlan_val;
2632 bp->afex_vlan_mode = vlan_mode;
2633 } else {
2634 /* notify link down because BP->flags is disabled */
2635 bnx2x_link_report(bp);
2636
2637 /* send INVALID VIF ramrod to FW */
2638 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2639
2640 /* Reset the default afex VLAN */
2641 bp->afex_def_vlan_tag = -1;
2642 }
2643 }
2644 }
2645
2646 static void bnx2x_pmf_update(struct bnx2x *bp)
2647 {
2648 int port = BP_PORT(bp);
2649 u32 val;
2650
2651 bp->port.pmf = 1;
2652 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2653
2654 /*
2655 * We need the mb() to ensure the ordering between the writing to
2656 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2657 */
2658 smp_mb();
2659
2660 /* queue a periodic task */
2661 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2662
2663 bnx2x_dcbx_pmf_update(bp);
2664
2665 /* enable nig attention */
2666 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2667 if (bp->common.int_block == INT_BLOCK_HC) {
2668 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2669 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2670 } else if (!CHIP_IS_E1x(bp)) {
2671 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2672 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2673 }
2674
2675 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2676 }
2677
2678 /* end of Link */
2679
2680 /* slow path */
2681
2682 /*
2683 * General service functions
2684 */
2685
2686 /* send the MCP a request, block until there is a reply */
2687 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2688 {
2689 int mb_idx = BP_FW_MB_IDX(bp);
2690 u32 seq;
2691 u32 rc = 0;
2692 u32 cnt = 1;
2693 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2694
2695 mutex_lock(&bp->fw_mb_mutex);
2696 seq = ++bp->fw_seq;
2697 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2698 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2699
2700 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2701 (command | seq), param);
2702
2703 do {
2704 /* let the FW do it's magic ... */
2705 msleep(delay);
2706
2707 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2708
2709 /* Give the FW up to 5 second (500*10ms) */
2710 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2711
2712 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2713 cnt*delay, rc, seq);
2714
2715 /* is this a reply to our command? */
2716 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2717 rc &= FW_MSG_CODE_MASK;
2718 else {
2719 /* FW BUG! */
2720 BNX2X_ERR("FW failed to respond!\n");
2721 bnx2x_fw_dump(bp);
2722 rc = 0;
2723 }
2724 mutex_unlock(&bp->fw_mb_mutex);
2725
2726 return rc;
2727 }
2728
2729
2730 static void storm_memset_func_cfg(struct bnx2x *bp,
2731 struct tstorm_eth_function_common_config *tcfg,
2732 u16 abs_fid)
2733 {
2734 size_t size = sizeof(struct tstorm_eth_function_common_config);
2735
2736 u32 addr = BAR_TSTRORM_INTMEM +
2737 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2738
2739 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2740 }
2741
2742 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2743 {
2744 if (CHIP_IS_E1x(bp)) {
2745 struct tstorm_eth_function_common_config tcfg = {0};
2746
2747 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2748 }
2749
2750 /* Enable the function in the FW */
2751 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2752 storm_memset_func_en(bp, p->func_id, 1);
2753
2754 /* spq */
2755 if (p->func_flgs & FUNC_FLG_SPQ) {
2756 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2757 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2758 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2759 }
2760 }
2761
2762 /**
2763 * bnx2x_get_tx_only_flags - Return common flags
2764 *
2765 * @bp device handle
2766 * @fp queue handle
2767 * @zero_stats TRUE if statistics zeroing is needed
2768 *
2769 * Return the flags that are common for the Tx-only and not normal connections.
2770 */
2771 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2772 struct bnx2x_fastpath *fp,
2773 bool zero_stats)
2774 {
2775 unsigned long flags = 0;
2776
2777 /* PF driver will always initialize the Queue to an ACTIVE state */
2778 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2779
2780 /* tx only connections collect statistics (on the same index as the
2781 * parent connection). The statistics are zeroed when the parent
2782 * connection is initialized.
2783 */
2784
2785 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2786 if (zero_stats)
2787 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2788
2789
2790 return flags;
2791 }
2792
2793 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2794 struct bnx2x_fastpath *fp,
2795 bool leading)
2796 {
2797 unsigned long flags = 0;
2798
2799 /* calculate other queue flags */
2800 if (IS_MF_SD(bp))
2801 __set_bit(BNX2X_Q_FLG_OV, &flags);
2802
2803 if (IS_FCOE_FP(fp)) {
2804 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2805 /* For FCoE - force usage of default priority (for afex) */
2806 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2807 }
2808
2809 if (!fp->disable_tpa) {
2810 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2811 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2812 if (fp->mode == TPA_MODE_GRO)
2813 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2814 }
2815
2816 if (leading) {
2817 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2818 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2819 }
2820
2821 /* Always set HW VLAN stripping */
2822 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2823
2824 /* configure silent vlan removal */
2825 if (IS_MF_AFEX(bp))
2826 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
2827
2828
2829 return flags | bnx2x_get_common_flags(bp, fp, true);
2830 }
2831
2832 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2833 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2834 u8 cos)
2835 {
2836 gen_init->stat_id = bnx2x_stats_id(fp);
2837 gen_init->spcl_id = fp->cl_id;
2838
2839 /* Always use mini-jumbo MTU for FCoE L2 ring */
2840 if (IS_FCOE_FP(fp))
2841 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2842 else
2843 gen_init->mtu = bp->dev->mtu;
2844
2845 gen_init->cos = cos;
2846 }
2847
2848 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2849 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2850 struct bnx2x_rxq_setup_params *rxq_init)
2851 {
2852 u8 max_sge = 0;
2853 u16 sge_sz = 0;
2854 u16 tpa_agg_size = 0;
2855
2856 if (!fp->disable_tpa) {
2857 pause->sge_th_lo = SGE_TH_LO(bp);
2858 pause->sge_th_hi = SGE_TH_HI(bp);
2859
2860 /* validate SGE ring has enough to cross high threshold */
2861 WARN_ON(bp->dropless_fc &&
2862 pause->sge_th_hi + FW_PREFETCH_CNT >
2863 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2864
2865 tpa_agg_size = min_t(u32,
2866 (min_t(u32, 8, MAX_SKB_FRAGS) *
2867 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2868 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2869 SGE_PAGE_SHIFT;
2870 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2871 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2872 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2873 0xffff);
2874 }
2875
2876 /* pause - not for e1 */
2877 if (!CHIP_IS_E1(bp)) {
2878 pause->bd_th_lo = BD_TH_LO(bp);
2879 pause->bd_th_hi = BD_TH_HI(bp);
2880
2881 pause->rcq_th_lo = RCQ_TH_LO(bp);
2882 pause->rcq_th_hi = RCQ_TH_HI(bp);
2883 /*
2884 * validate that rings have enough entries to cross
2885 * high thresholds
2886 */
2887 WARN_ON(bp->dropless_fc &&
2888 pause->bd_th_hi + FW_PREFETCH_CNT >
2889 bp->rx_ring_size);
2890 WARN_ON(bp->dropless_fc &&
2891 pause->rcq_th_hi + FW_PREFETCH_CNT >
2892 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2893
2894 pause->pri_map = 1;
2895 }
2896
2897 /* rxq setup */
2898 rxq_init->dscr_map = fp->rx_desc_mapping;
2899 rxq_init->sge_map = fp->rx_sge_mapping;
2900 rxq_init->rcq_map = fp->rx_comp_mapping;
2901 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2902
2903 /* This should be a maximum number of data bytes that may be
2904 * placed on the BD (not including paddings).
2905 */
2906 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2907 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
2908
2909 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2910 rxq_init->tpa_agg_sz = tpa_agg_size;
2911 rxq_init->sge_buf_sz = sge_sz;
2912 rxq_init->max_sges_pkt = max_sge;
2913 rxq_init->rss_engine_id = BP_FUNC(bp);
2914 rxq_init->mcast_engine_id = BP_FUNC(bp);
2915
2916 /* Maximum number or simultaneous TPA aggregation for this Queue.
2917 *
2918 * For PF Clients it should be the maximum avaliable number.
2919 * VF driver(s) may want to define it to a smaller value.
2920 */
2921 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2922
2923 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2924 rxq_init->fw_sb_id = fp->fw_sb_id;
2925
2926 if (IS_FCOE_FP(fp))
2927 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2928 else
2929 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2930 /* configure silent vlan removal
2931 * if multi function mode is afex, then mask default vlan
2932 */
2933 if (IS_MF_AFEX(bp)) {
2934 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
2935 rxq_init->silent_removal_mask = VLAN_VID_MASK;
2936 }
2937 }
2938
2939 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2940 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2941 u8 cos)
2942 {
2943 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
2944 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2945 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2946 txq_init->fw_sb_id = fp->fw_sb_id;
2947
2948 /*
2949 * set the tss leading client id for TX classfication ==
2950 * leading RSS client id
2951 */
2952 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2953
2954 if (IS_FCOE_FP(fp)) {
2955 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2956 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2957 }
2958 }
2959
2960 static void bnx2x_pf_init(struct bnx2x *bp)
2961 {
2962 struct bnx2x_func_init_params func_init = {0};
2963 struct event_ring_data eq_data = { {0} };
2964 u16 flags;
2965
2966 if (!CHIP_IS_E1x(bp)) {
2967 /* reset IGU PF statistics: MSIX + ATTN */
2968 /* PF */
2969 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2970 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2971 (CHIP_MODE_IS_4_PORT(bp) ?
2972 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2973 /* ATTN */
2974 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2975 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2976 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2977 (CHIP_MODE_IS_4_PORT(bp) ?
2978 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2979 }
2980
2981 /* function setup flags */
2982 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2983
2984 /* This flag is relevant for E1x only.
2985 * E2 doesn't have a TPA configuration in a function level.
2986 */
2987 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2988
2989 func_init.func_flgs = flags;
2990 func_init.pf_id = BP_FUNC(bp);
2991 func_init.func_id = BP_FUNC(bp);
2992 func_init.spq_map = bp->spq_mapping;
2993 func_init.spq_prod = bp->spq_prod_idx;
2994
2995 bnx2x_func_init(bp, &func_init);
2996
2997 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2998
2999 /*
3000 * Congestion management values depend on the link rate
3001 * There is no active link so initial link rate is set to 10 Gbps.
3002 * When the link comes up The congestion management values are
3003 * re-calculated according to the actual link rate.
3004 */
3005 bp->link_vars.line_speed = SPEED_10000;
3006 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3007
3008 /* Only the PMF sets the HW */
3009 if (bp->port.pmf)
3010 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3011
3012 /* init Event Queue */
3013 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3014 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3015 eq_data.producer = bp->eq_prod;
3016 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3017 eq_data.sb_id = DEF_SB_ID;
3018 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3019 }
3020
3021
3022 static void bnx2x_e1h_disable(struct bnx2x *bp)
3023 {
3024 int port = BP_PORT(bp);
3025
3026 bnx2x_tx_disable(bp);
3027
3028 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3029 }
3030
3031 static void bnx2x_e1h_enable(struct bnx2x *bp)
3032 {
3033 int port = BP_PORT(bp);
3034
3035 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3036
3037 /* Tx queue should be only reenabled */
3038 netif_tx_wake_all_queues(bp->dev);
3039
3040 /*
3041 * Should not call netif_carrier_on since it will be called if the link
3042 * is up when checking for link state
3043 */
3044 }
3045
3046 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3047
3048 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3049 {
3050 struct eth_stats_info *ether_stat =
3051 &bp->slowpath->drv_info_to_mcp.ether_stat;
3052
3053 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3054 ETH_STAT_INFO_VERSION_LEN);
3055
3056 bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3057 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3058 ether_stat->mac_local);
3059
3060 ether_stat->mtu_size = bp->dev->mtu;
3061
3062 if (bp->dev->features & NETIF_F_RXCSUM)
3063 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3064 if (bp->dev->features & NETIF_F_TSO)
3065 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3066 ether_stat->feature_flags |= bp->common.boot_mode;
3067
3068 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3069
3070 ether_stat->txq_size = bp->tx_ring_size;
3071 ether_stat->rxq_size = bp->rx_ring_size;
3072 }
3073
3074 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3075 {
3076 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3077 struct fcoe_stats_info *fcoe_stat =
3078 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3079
3080 if (!CNIC_LOADED(bp))
3081 return;
3082
3083 memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
3084 bp->fip_mac, ETH_ALEN);
3085
3086 fcoe_stat->qos_priority =
3087 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3088
3089 /* insert FCoE stats from ramrod response */
3090 if (!NO_FCOE(bp)) {
3091 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3092 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3093 tstorm_queue_statistics;
3094
3095 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3096 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3097 xstorm_queue_statistics;
3098
3099 struct fcoe_statistics_params *fw_fcoe_stat =
3100 &bp->fw_stats_data->fcoe;
3101
3102 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
3103 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3104
3105 ADD_64(fcoe_stat->rx_bytes_hi,
3106 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3107 fcoe_stat->rx_bytes_lo,
3108 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3109
3110 ADD_64(fcoe_stat->rx_bytes_hi,
3111 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3112 fcoe_stat->rx_bytes_lo,
3113 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3114
3115 ADD_64(fcoe_stat->rx_bytes_hi,
3116 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3117 fcoe_stat->rx_bytes_lo,
3118 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3119
3120 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3121 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3122
3123 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3124 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3125
3126 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3127 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3128
3129 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3130 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3131
3132 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3133 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3134
3135 ADD_64(fcoe_stat->tx_bytes_hi,
3136 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3137 fcoe_stat->tx_bytes_lo,
3138 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3139
3140 ADD_64(fcoe_stat->tx_bytes_hi,
3141 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3142 fcoe_stat->tx_bytes_lo,
3143 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3144
3145 ADD_64(fcoe_stat->tx_bytes_hi,
3146 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3147 fcoe_stat->tx_bytes_lo,
3148 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3149
3150 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3151 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3152
3153 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3154 fcoe_q_xstorm_stats->ucast_pkts_sent);
3155
3156 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3157 fcoe_q_xstorm_stats->bcast_pkts_sent);
3158
3159 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3160 fcoe_q_xstorm_stats->mcast_pkts_sent);
3161 }
3162
3163 /* ask L5 driver to add data to the struct */
3164 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3165 }
3166
3167 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3168 {
3169 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3170 struct iscsi_stats_info *iscsi_stat =
3171 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3172
3173 if (!CNIC_LOADED(bp))
3174 return;
3175
3176 memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
3177 bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3178
3179 iscsi_stat->qos_priority =
3180 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3181
3182 /* ask L5 driver to add data to the struct */
3183 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3184 }
3185
3186 /* called due to MCP event (on pmf):
3187 * reread new bandwidth configuration
3188 * configure FW
3189 * notify others function about the change
3190 */
3191 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3192 {
3193 if (bp->link_vars.link_up) {
3194 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3195 bnx2x_link_sync_notify(bp);
3196 }
3197 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3198 }
3199
3200 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3201 {
3202 bnx2x_config_mf_bw(bp);
3203 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3204 }
3205
3206 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3207 {
3208 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3209 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3210 }
3211
3212 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3213 {
3214 enum drv_info_opcode op_code;
3215 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3216
3217 /* if drv_info version supported by MFW doesn't match - send NACK */
3218 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3219 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3220 return;
3221 }
3222
3223 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3224 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3225
3226 memset(&bp->slowpath->drv_info_to_mcp, 0,
3227 sizeof(union drv_info_to_mcp));
3228
3229 switch (op_code) {
3230 case ETH_STATS_OPCODE:
3231 bnx2x_drv_info_ether_stat(bp);
3232 break;
3233 case FCOE_STATS_OPCODE:
3234 bnx2x_drv_info_fcoe_stat(bp);
3235 break;
3236 case ISCSI_STATS_OPCODE:
3237 bnx2x_drv_info_iscsi_stat(bp);
3238 break;
3239 default:
3240 /* if op code isn't supported - send NACK */
3241 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3242 return;
3243 }
3244
3245 /* if we got drv_info attn from MFW then these fields are defined in
3246 * shmem2 for sure
3247 */
3248 SHMEM2_WR(bp, drv_info_host_addr_lo,
3249 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3250 SHMEM2_WR(bp, drv_info_host_addr_hi,
3251 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3252
3253 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3254 }
3255
3256 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3257 {
3258 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3259
3260 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3261
3262 /*
3263 * This is the only place besides the function initialization
3264 * where the bp->flags can change so it is done without any
3265 * locks
3266 */
3267 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3268 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3269 bp->flags |= MF_FUNC_DIS;
3270
3271 bnx2x_e1h_disable(bp);
3272 } else {
3273 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3274 bp->flags &= ~MF_FUNC_DIS;
3275
3276 bnx2x_e1h_enable(bp);
3277 }
3278 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3279 }
3280 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3281 bnx2x_config_mf_bw(bp);
3282 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3283 }
3284
3285 /* Report results to MCP */
3286 if (dcc_event)
3287 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3288 else
3289 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3290 }
3291
3292 /* must be called under the spq lock */
3293 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3294 {
3295 struct eth_spe *next_spe = bp->spq_prod_bd;
3296
3297 if (bp->spq_prod_bd == bp->spq_last_bd) {
3298 bp->spq_prod_bd = bp->spq;
3299 bp->spq_prod_idx = 0;
3300 DP(BNX2X_MSG_SP, "end of spq\n");
3301 } else {
3302 bp->spq_prod_bd++;
3303 bp->spq_prod_idx++;
3304 }
3305 return next_spe;
3306 }
3307
3308 /* must be called under the spq lock */
3309 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3310 {
3311 int func = BP_FUNC(bp);
3312
3313 /*
3314 * Make sure that BD data is updated before writing the producer:
3315 * BD data is written to the memory, the producer is read from the
3316 * memory, thus we need a full memory barrier to ensure the ordering.
3317 */
3318 mb();
3319
3320 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3321 bp->spq_prod_idx);
3322 mmiowb();
3323 }
3324
3325 /**
3326 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3327 *
3328 * @cmd: command to check
3329 * @cmd_type: command type
3330 */
3331 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3332 {
3333 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3334 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3335 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3336 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3337 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3338 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3339 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3340 return true;
3341 else
3342 return false;
3343
3344 }
3345
3346
3347 /**
3348 * bnx2x_sp_post - place a single command on an SP ring
3349 *
3350 * @bp: driver handle
3351 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3352 * @cid: SW CID the command is related to
3353 * @data_hi: command private data address (high 32 bits)
3354 * @data_lo: command private data address (low 32 bits)
3355 * @cmd_type: command type (e.g. NONE, ETH)
3356 *
3357 * SP data is handled as if it's always an address pair, thus data fields are
3358 * not swapped to little endian in upper functions. Instead this function swaps
3359 * data as if it's two u32 fields.
3360 */
3361 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3362 u32 data_hi, u32 data_lo, int cmd_type)
3363 {
3364 struct eth_spe *spe;
3365 u16 type;
3366 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3367
3368 #ifdef BNX2X_STOP_ON_ERROR
3369 if (unlikely(bp->panic)) {
3370 BNX2X_ERR("Can't post SP when there is panic\n");
3371 return -EIO;
3372 }
3373 #endif
3374
3375 spin_lock_bh(&bp->spq_lock);
3376
3377 if (common) {
3378 if (!atomic_read(&bp->eq_spq_left)) {
3379 BNX2X_ERR("BUG! EQ ring full!\n");
3380 spin_unlock_bh(&bp->spq_lock);
3381 bnx2x_panic();
3382 return -EBUSY;
3383 }
3384 } else if (!atomic_read(&bp->cq_spq_left)) {
3385 BNX2X_ERR("BUG! SPQ ring full!\n");
3386 spin_unlock_bh(&bp->spq_lock);
3387 bnx2x_panic();
3388 return -EBUSY;
3389 }
3390
3391 spe = bnx2x_sp_get_next(bp);
3392
3393 /* CID needs port number to be encoded int it */
3394 spe->hdr.conn_and_cmd_data =
3395 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3396 HW_CID(bp, cid));
3397
3398 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3399
3400 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3401 SPE_HDR_FUNCTION_ID);
3402
3403 spe->hdr.type = cpu_to_le16(type);
3404
3405 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3406 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3407
3408 /*
3409 * It's ok if the actual decrement is issued towards the memory
3410 * somewhere between the spin_lock and spin_unlock. Thus no
3411 * more explict memory barrier is needed.
3412 */
3413 if (common)
3414 atomic_dec(&bp->eq_spq_left);
3415 else
3416 atomic_dec(&bp->cq_spq_left);
3417
3418
3419 DP(BNX2X_MSG_SP,
3420 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3421 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3422 (u32)(U64_LO(bp->spq_mapping) +
3423 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3424 HW_CID(bp, cid), data_hi, data_lo, type,
3425 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3426
3427 bnx2x_sp_prod_update(bp);
3428 spin_unlock_bh(&bp->spq_lock);
3429 return 0;
3430 }
3431
3432 /* acquire split MCP access lock register */
3433 static int bnx2x_acquire_alr(struct bnx2x *bp)
3434 {
3435 u32 j, val;
3436 int rc = 0;
3437
3438 might_sleep();
3439 for (j = 0; j < 1000; j++) {
3440 val = (1UL << 31);
3441 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3442 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3443 if (val & (1L << 31))
3444 break;
3445
3446 msleep(5);
3447 }
3448 if (!(val & (1L << 31))) {
3449 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3450 rc = -EBUSY;
3451 }
3452
3453 return rc;
3454 }
3455
3456 /* release split MCP access lock register */
3457 static void bnx2x_release_alr(struct bnx2x *bp)
3458 {
3459 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3460 }
3461
3462 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3463 #define BNX2X_DEF_SB_IDX 0x0002
3464
3465 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3466 {
3467 struct host_sp_status_block *def_sb = bp->def_status_blk;
3468 u16 rc = 0;
3469
3470 barrier(); /* status block is written to by the chip */
3471 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3472 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3473 rc |= BNX2X_DEF_SB_ATT_IDX;
3474 }
3475
3476 if (bp->def_idx != def_sb->sp_sb.running_index) {
3477 bp->def_idx = def_sb->sp_sb.running_index;
3478 rc |= BNX2X_DEF_SB_IDX;
3479 }
3480
3481 /* Do not reorder: indecies reading should complete before handling */
3482 barrier();
3483 return rc;
3484 }
3485
3486 /*
3487 * slow path service functions
3488 */
3489
3490 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3491 {
3492 int port = BP_PORT(bp);
3493 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3494 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3495 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3496 NIG_REG_MASK_INTERRUPT_PORT0;
3497 u32 aeu_mask;
3498 u32 nig_mask = 0;
3499 u32 reg_addr;
3500
3501 if (bp->attn_state & asserted)
3502 BNX2X_ERR("IGU ERROR\n");
3503
3504 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3505 aeu_mask = REG_RD(bp, aeu_addr);
3506
3507 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3508 aeu_mask, asserted);
3509 aeu_mask &= ~(asserted & 0x3ff);
3510 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3511
3512 REG_WR(bp, aeu_addr, aeu_mask);
3513 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3514
3515 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3516 bp->attn_state |= asserted;
3517 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3518
3519 if (asserted & ATTN_HARD_WIRED_MASK) {
3520 if (asserted & ATTN_NIG_FOR_FUNC) {
3521
3522 bnx2x_acquire_phy_lock(bp);
3523
3524 /* save nig interrupt mask */
3525 nig_mask = REG_RD(bp, nig_int_mask_addr);
3526
3527 /* If nig_mask is not set, no need to call the update
3528 * function.
3529 */
3530 if (nig_mask) {
3531 REG_WR(bp, nig_int_mask_addr, 0);
3532
3533 bnx2x_link_attn(bp);
3534 }
3535
3536 /* handle unicore attn? */
3537 }
3538 if (asserted & ATTN_SW_TIMER_4_FUNC)
3539 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3540
3541 if (asserted & GPIO_2_FUNC)
3542 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3543
3544 if (asserted & GPIO_3_FUNC)
3545 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3546
3547 if (asserted & GPIO_4_FUNC)
3548 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3549
3550 if (port == 0) {
3551 if (asserted & ATTN_GENERAL_ATTN_1) {
3552 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3553 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3554 }
3555 if (asserted & ATTN_GENERAL_ATTN_2) {
3556 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3557 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3558 }
3559 if (asserted & ATTN_GENERAL_ATTN_3) {
3560 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3561 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3562 }
3563 } else {
3564 if (asserted & ATTN_GENERAL_ATTN_4) {
3565 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3566 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3567 }
3568 if (asserted & ATTN_GENERAL_ATTN_5) {
3569 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3570 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3571 }
3572 if (asserted & ATTN_GENERAL_ATTN_6) {
3573 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3574 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3575 }
3576 }
3577
3578 } /* if hardwired */
3579
3580 if (bp->common.int_block == INT_BLOCK_HC)
3581 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3582 COMMAND_REG_ATTN_BITS_SET);
3583 else
3584 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3585
3586 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3587 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3588 REG_WR(bp, reg_addr, asserted);
3589
3590 /* now set back the mask */
3591 if (asserted & ATTN_NIG_FOR_FUNC) {
3592 REG_WR(bp, nig_int_mask_addr, nig_mask);
3593 bnx2x_release_phy_lock(bp);
3594 }
3595 }
3596
3597 static void bnx2x_fan_failure(struct bnx2x *bp)
3598 {
3599 int port = BP_PORT(bp);
3600 u32 ext_phy_config;
3601 /* mark the failure */
3602 ext_phy_config =
3603 SHMEM_RD(bp,
3604 dev_info.port_hw_config[port].external_phy_config);
3605
3606 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3607 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3608 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3609 ext_phy_config);
3610
3611 /* log the failure */
3612 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3613 "Please contact OEM Support for assistance\n");
3614
3615 /*
3616 * Scheudle device reset (unload)
3617 * This is due to some boards consuming sufficient power when driver is
3618 * up to overheat if fan fails.
3619 */
3620 smp_mb__before_clear_bit();
3621 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3622 smp_mb__after_clear_bit();
3623 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3624
3625 }
3626
3627 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3628 {
3629 int port = BP_PORT(bp);
3630 int reg_offset;
3631 u32 val;
3632
3633 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3634 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3635
3636 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3637
3638 val = REG_RD(bp, reg_offset);
3639 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3640 REG_WR(bp, reg_offset, val);
3641
3642 BNX2X_ERR("SPIO5 hw attention\n");
3643
3644 /* Fan failure attention */
3645 bnx2x_hw_reset_phy(&bp->link_params);
3646 bnx2x_fan_failure(bp);
3647 }
3648
3649 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3650 bnx2x_acquire_phy_lock(bp);
3651 bnx2x_handle_module_detect_int(&bp->link_params);
3652 bnx2x_release_phy_lock(bp);
3653 }
3654
3655 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3656
3657 val = REG_RD(bp, reg_offset);
3658 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3659 REG_WR(bp, reg_offset, val);
3660
3661 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3662 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3663 bnx2x_panic();
3664 }
3665 }
3666
3667 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3668 {
3669 u32 val;
3670
3671 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3672
3673 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3674 BNX2X_ERR("DB hw attention 0x%x\n", val);
3675 /* DORQ discard attention */
3676 if (val & 0x2)
3677 BNX2X_ERR("FATAL error from DORQ\n");
3678 }
3679
3680 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3681
3682 int port = BP_PORT(bp);
3683 int reg_offset;
3684
3685 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3686 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3687
3688 val = REG_RD(bp, reg_offset);
3689 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3690 REG_WR(bp, reg_offset, val);
3691
3692 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3693 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3694 bnx2x_panic();
3695 }
3696 }
3697
3698 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3699 {
3700 u32 val;
3701
3702 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3703
3704 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3705 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3706 /* CFC error attention */
3707 if (val & 0x2)
3708 BNX2X_ERR("FATAL error from CFC\n");
3709 }
3710
3711 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3712 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3713 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3714 /* RQ_USDMDP_FIFO_OVERFLOW */
3715 if (val & 0x18000)
3716 BNX2X_ERR("FATAL error from PXP\n");
3717
3718 if (!CHIP_IS_E1x(bp)) {
3719 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3720 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3721 }
3722 }
3723
3724 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3725
3726 int port = BP_PORT(bp);
3727 int reg_offset;
3728
3729 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3730 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3731
3732 val = REG_RD(bp, reg_offset);
3733 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3734 REG_WR(bp, reg_offset, val);
3735
3736 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3737 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3738 bnx2x_panic();
3739 }
3740 }
3741
3742 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3743 {
3744 u32 val;
3745
3746 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3747
3748 if (attn & BNX2X_PMF_LINK_ASSERT) {
3749 int func = BP_FUNC(bp);
3750
3751 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3752 bnx2x_read_mf_cfg(bp);
3753 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3754 func_mf_config[BP_ABS_FUNC(bp)].config);
3755 val = SHMEM_RD(bp,
3756 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3757 if (val & DRV_STATUS_DCC_EVENT_MASK)
3758 bnx2x_dcc_event(bp,
3759 (val & DRV_STATUS_DCC_EVENT_MASK));
3760
3761 if (val & DRV_STATUS_SET_MF_BW)
3762 bnx2x_set_mf_bw(bp);
3763
3764 if (val & DRV_STATUS_DRV_INFO_REQ)
3765 bnx2x_handle_drv_info_req(bp);
3766 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3767 bnx2x_pmf_update(bp);
3768
3769 if (bp->port.pmf &&
3770 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3771 bp->dcbx_enabled > 0)
3772 /* start dcbx state machine */
3773 bnx2x_dcbx_set_params(bp,
3774 BNX2X_DCBX_STATE_NEG_RECEIVED);
3775 if (val & DRV_STATUS_AFEX_EVENT_MASK)
3776 bnx2x_handle_afex_cmd(bp,
3777 val & DRV_STATUS_AFEX_EVENT_MASK);
3778 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3779 bnx2x_handle_eee_event(bp);
3780 if (bp->link_vars.periodic_flags &
3781 PERIODIC_FLAGS_LINK_EVENT) {
3782 /* sync with link */
3783 bnx2x_acquire_phy_lock(bp);
3784 bp->link_vars.periodic_flags &=
3785 ~PERIODIC_FLAGS_LINK_EVENT;
3786 bnx2x_release_phy_lock(bp);
3787 if (IS_MF(bp))
3788 bnx2x_link_sync_notify(bp);
3789 bnx2x_link_report(bp);
3790 }
3791 /* Always call it here: bnx2x_link_report() will
3792 * prevent the link indication duplication.
3793 */
3794 bnx2x__link_status_update(bp);
3795 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3796
3797 BNX2X_ERR("MC assert!\n");
3798 bnx2x_mc_assert(bp);
3799 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3800 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3801 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3802 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3803 bnx2x_panic();
3804
3805 } else if (attn & BNX2X_MCP_ASSERT) {
3806
3807 BNX2X_ERR("MCP assert!\n");
3808 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3809 bnx2x_fw_dump(bp);
3810
3811 } else
3812 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3813 }
3814
3815 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3816 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3817 if (attn & BNX2X_GRC_TIMEOUT) {
3818 val = CHIP_IS_E1(bp) ? 0 :
3819 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3820 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3821 }
3822 if (attn & BNX2X_GRC_RSV) {
3823 val = CHIP_IS_E1(bp) ? 0 :
3824 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3825 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3826 }
3827 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3828 }
3829 }
3830
3831 /*
3832 * Bits map:
3833 * 0-7 - Engine0 load counter.
3834 * 8-15 - Engine1 load counter.
3835 * 16 - Engine0 RESET_IN_PROGRESS bit.
3836 * 17 - Engine1 RESET_IN_PROGRESS bit.
3837 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3838 * on the engine
3839 * 19 - Engine1 ONE_IS_LOADED.
3840 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3841 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3842 * just the one belonging to its engine).
3843 *
3844 */
3845 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3846
3847 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3848 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3849 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3850 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3851 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3852 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3853 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3854
3855 /*
3856 * Set the GLOBAL_RESET bit.
3857 *
3858 * Should be run under rtnl lock
3859 */
3860 void bnx2x_set_reset_global(struct bnx2x *bp)
3861 {
3862 u32 val;
3863 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3864 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3865 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3866 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3867 }
3868
3869 /*
3870 * Clear the GLOBAL_RESET bit.
3871 *
3872 * Should be run under rtnl lock
3873 */
3874 static void bnx2x_clear_reset_global(struct bnx2x *bp)
3875 {
3876 u32 val;
3877 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3878 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3879 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3880 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3881 }
3882
3883 /*
3884 * Checks the GLOBAL_RESET bit.
3885 *
3886 * should be run under rtnl lock
3887 */
3888 static bool bnx2x_reset_is_global(struct bnx2x *bp)
3889 {
3890 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3891
3892 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3893 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3894 }
3895
3896 /*
3897 * Clear RESET_IN_PROGRESS bit for the current engine.
3898 *
3899 * Should be run under rtnl lock
3900 */
3901 static void bnx2x_set_reset_done(struct bnx2x *bp)
3902 {
3903 u32 val;
3904 u32 bit = BP_PATH(bp) ?
3905 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3906 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3907 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3908
3909 /* Clear the bit */
3910 val &= ~bit;
3911 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3912
3913 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3914 }
3915
3916 /*
3917 * Set RESET_IN_PROGRESS for the current engine.
3918 *
3919 * should be run under rtnl lock
3920 */
3921 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3922 {
3923 u32 val;
3924 u32 bit = BP_PATH(bp) ?
3925 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3926 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3927 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3928
3929 /* Set the bit */
3930 val |= bit;
3931 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3932 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3933 }
3934
3935 /*
3936 * Checks the RESET_IN_PROGRESS bit for the given engine.
3937 * should be run under rtnl lock
3938 */
3939 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3940 {
3941 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3942 u32 bit = engine ?
3943 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3944
3945 /* return false if bit is set */
3946 return (val & bit) ? false : true;
3947 }
3948
3949 /*
3950 * set pf load for the current pf.
3951 *
3952 * should be run under rtnl lock
3953 */
3954 void bnx2x_set_pf_load(struct bnx2x *bp)
3955 {
3956 u32 val1, val;
3957 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3958 BNX2X_PATH0_LOAD_CNT_MASK;
3959 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3960 BNX2X_PATH0_LOAD_CNT_SHIFT;
3961
3962 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3963 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3964
3965 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
3966
3967 /* get the current counter value */
3968 val1 = (val & mask) >> shift;
3969
3970 /* set bit of that PF */
3971 val1 |= (1 << bp->pf_num);
3972
3973 /* clear the old value */
3974 val &= ~mask;
3975
3976 /* set the new one */
3977 val |= ((val1 << shift) & mask);
3978
3979 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3980 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3981 }
3982
3983 /**
3984 * bnx2x_clear_pf_load - clear pf load mark
3985 *
3986 * @bp: driver handle
3987 *
3988 * Should be run under rtnl lock.
3989 * Decrements the load counter for the current engine. Returns
3990 * whether other functions are still loaded
3991 */
3992 bool bnx2x_clear_pf_load(struct bnx2x *bp)
3993 {
3994 u32 val1, val;
3995 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3996 BNX2X_PATH0_LOAD_CNT_MASK;
3997 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3998 BNX2X_PATH0_LOAD_CNT_SHIFT;
3999
4000 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4001 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4002 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4003
4004 /* get the current counter value */
4005 val1 = (val & mask) >> shift;
4006
4007 /* clear bit of that PF */
4008 val1 &= ~(1 << bp->pf_num);
4009
4010 /* clear the old value */
4011 val &= ~mask;
4012
4013 /* set the new one */
4014 val |= ((val1 << shift) & mask);
4015
4016 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4017 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4018 return val1 != 0;
4019 }
4020
4021 /*
4022 * Read the load status for the current engine.
4023 *
4024 * should be run under rtnl lock
4025 */
4026 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4027 {
4028 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4029 BNX2X_PATH0_LOAD_CNT_MASK);
4030 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4031 BNX2X_PATH0_LOAD_CNT_SHIFT);
4032 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4033
4034 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4035
4036 val = (val & mask) >> shift;
4037
4038 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4039 engine, val);
4040
4041 return val != 0;
4042 }
4043
4044 static void _print_next_block(int idx, const char *blk)
4045 {
4046 pr_cont("%s%s", idx ? ", " : "", blk);
4047 }
4048
4049 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4050 bool print)
4051 {
4052 int i = 0;
4053 u32 cur_bit = 0;
4054 for (i = 0; sig; i++) {
4055 cur_bit = ((u32)0x1 << i);
4056 if (sig & cur_bit) {
4057 switch (cur_bit) {
4058 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4059 if (print)
4060 _print_next_block(par_num++, "BRB");
4061 break;
4062 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4063 if (print)
4064 _print_next_block(par_num++, "PARSER");
4065 break;
4066 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4067 if (print)
4068 _print_next_block(par_num++, "TSDM");
4069 break;
4070 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4071 if (print)
4072 _print_next_block(par_num++,
4073 "SEARCHER");
4074 break;
4075 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4076 if (print)
4077 _print_next_block(par_num++, "TCM");
4078 break;
4079 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4080 if (print)
4081 _print_next_block(par_num++, "TSEMI");
4082 break;
4083 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4084 if (print)
4085 _print_next_block(par_num++, "XPB");
4086 break;
4087 }
4088
4089 /* Clear the bit */
4090 sig &= ~cur_bit;
4091 }
4092 }
4093
4094 return par_num;
4095 }
4096
4097 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4098 bool *global, bool print)
4099 {
4100 int i = 0;
4101 u32 cur_bit = 0;
4102 for (i = 0; sig; i++) {
4103 cur_bit = ((u32)0x1 << i);
4104 if (sig & cur_bit) {
4105 switch (cur_bit) {
4106 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4107 if (print)
4108 _print_next_block(par_num++, "PBF");
4109 break;
4110 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4111 if (print)
4112 _print_next_block(par_num++, "QM");
4113 break;
4114 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4115 if (print)
4116 _print_next_block(par_num++, "TM");
4117 break;
4118 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4119 if (print)
4120 _print_next_block(par_num++, "XSDM");
4121 break;
4122 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4123 if (print)
4124 _print_next_block(par_num++, "XCM");
4125 break;
4126 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4127 if (print)
4128 _print_next_block(par_num++, "XSEMI");
4129 break;
4130 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4131 if (print)
4132 _print_next_block(par_num++,
4133 "DOORBELLQ");
4134 break;
4135 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4136 if (print)
4137 _print_next_block(par_num++, "NIG");
4138 break;
4139 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4140 if (print)
4141 _print_next_block(par_num++,
4142 "VAUX PCI CORE");
4143 *global = true;
4144 break;
4145 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4146 if (print)
4147 _print_next_block(par_num++, "DEBUG");
4148 break;
4149 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4150 if (print)
4151 _print_next_block(par_num++, "USDM");
4152 break;
4153 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4154 if (print)
4155 _print_next_block(par_num++, "UCM");
4156 break;
4157 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4158 if (print)
4159 _print_next_block(par_num++, "USEMI");
4160 break;
4161 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4162 if (print)
4163 _print_next_block(par_num++, "UPB");
4164 break;
4165 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4166 if (print)
4167 _print_next_block(par_num++, "CSDM");
4168 break;
4169 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4170 if (print)
4171 _print_next_block(par_num++, "CCM");
4172 break;
4173 }
4174
4175 /* Clear the bit */
4176 sig &= ~cur_bit;
4177 }
4178 }
4179
4180 return par_num;
4181 }
4182
4183 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4184 bool print)
4185 {
4186 int i = 0;
4187 u32 cur_bit = 0;
4188 for (i = 0; sig; i++) {
4189 cur_bit = ((u32)0x1 << i);
4190 if (sig & cur_bit) {
4191 switch (cur_bit) {
4192 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4193 if (print)
4194 _print_next_block(par_num++, "CSEMI");
4195 break;
4196 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4197 if (print)
4198 _print_next_block(par_num++, "PXP");
4199 break;
4200 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4201 if (print)
4202 _print_next_block(par_num++,
4203 "PXPPCICLOCKCLIENT");
4204 break;
4205 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4206 if (print)
4207 _print_next_block(par_num++, "CFC");
4208 break;
4209 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4210 if (print)
4211 _print_next_block(par_num++, "CDU");
4212 break;
4213 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4214 if (print)
4215 _print_next_block(par_num++, "DMAE");
4216 break;
4217 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4218 if (print)
4219 _print_next_block(par_num++, "IGU");
4220 break;
4221 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4222 if (print)
4223 _print_next_block(par_num++, "MISC");
4224 break;
4225 }
4226
4227 /* Clear the bit */
4228 sig &= ~cur_bit;
4229 }
4230 }
4231
4232 return par_num;
4233 }
4234
4235 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4236 bool *global, bool print)
4237 {
4238 int i = 0;
4239 u32 cur_bit = 0;
4240 for (i = 0; sig; i++) {
4241 cur_bit = ((u32)0x1 << i);
4242 if (sig & cur_bit) {
4243 switch (cur_bit) {
4244 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4245 if (print)
4246 _print_next_block(par_num++, "MCP ROM");
4247 *global = true;
4248 break;
4249 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4250 if (print)
4251 _print_next_block(par_num++,
4252 "MCP UMP RX");
4253 *global = true;
4254 break;
4255 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4256 if (print)
4257 _print_next_block(par_num++,
4258 "MCP UMP TX");
4259 *global = true;
4260 break;
4261 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4262 if (print)
4263 _print_next_block(par_num++,
4264 "MCP SCPAD");
4265 *global = true;
4266 break;
4267 }
4268
4269 /* Clear the bit */
4270 sig &= ~cur_bit;
4271 }
4272 }
4273
4274 return par_num;
4275 }
4276
4277 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4278 bool print)
4279 {
4280 int i = 0;
4281 u32 cur_bit = 0;
4282 for (i = 0; sig; i++) {
4283 cur_bit = ((u32)0x1 << i);
4284 if (sig & cur_bit) {
4285 switch (cur_bit) {
4286 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4287 if (print)
4288 _print_next_block(par_num++, "PGLUE_B");
4289 break;
4290 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4291 if (print)
4292 _print_next_block(par_num++, "ATC");
4293 break;
4294 }
4295
4296 /* Clear the bit */
4297 sig &= ~cur_bit;
4298 }
4299 }
4300
4301 return par_num;
4302 }
4303
4304 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4305 u32 *sig)
4306 {
4307 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4308 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4309 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4310 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4311 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4312 int par_num = 0;
4313 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4314 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4315 sig[0] & HW_PRTY_ASSERT_SET_0,
4316 sig[1] & HW_PRTY_ASSERT_SET_1,
4317 sig[2] & HW_PRTY_ASSERT_SET_2,
4318 sig[3] & HW_PRTY_ASSERT_SET_3,
4319 sig[4] & HW_PRTY_ASSERT_SET_4);
4320 if (print)
4321 netdev_err(bp->dev,
4322 "Parity errors detected in blocks: ");
4323 par_num = bnx2x_check_blocks_with_parity0(
4324 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4325 par_num = bnx2x_check_blocks_with_parity1(
4326 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4327 par_num = bnx2x_check_blocks_with_parity2(
4328 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4329 par_num = bnx2x_check_blocks_with_parity3(
4330 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4331 par_num = bnx2x_check_blocks_with_parity4(
4332 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4333
4334 if (print)
4335 pr_cont("\n");
4336
4337 return true;
4338 } else
4339 return false;
4340 }
4341
4342 /**
4343 * bnx2x_chk_parity_attn - checks for parity attentions.
4344 *
4345 * @bp: driver handle
4346 * @global: true if there was a global attention
4347 * @print: show parity attention in syslog
4348 */
4349 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4350 {
4351 struct attn_route attn = { {0} };
4352 int port = BP_PORT(bp);
4353
4354 attn.sig[0] = REG_RD(bp,
4355 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4356 port*4);
4357 attn.sig[1] = REG_RD(bp,
4358 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4359 port*4);
4360 attn.sig[2] = REG_RD(bp,
4361 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4362 port*4);
4363 attn.sig[3] = REG_RD(bp,
4364 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4365 port*4);
4366
4367 if (!CHIP_IS_E1x(bp))
4368 attn.sig[4] = REG_RD(bp,
4369 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4370 port*4);
4371
4372 return bnx2x_parity_attn(bp, global, print, attn.sig);
4373 }
4374
4375
4376 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4377 {
4378 u32 val;
4379 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4380
4381 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4382 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4383 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4384 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4385 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4386 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4387 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4388 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4389 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4390 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4391 if (val &
4392 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4393 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4394 if (val &
4395 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4396 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4397 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4398 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4399 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4400 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4401 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4402 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4403 }
4404 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4405 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4406 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4407 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4408 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4409 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4410 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4411 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4412 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4413 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4414 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4415 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4416 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4417 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4418 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4419 }
4420
4421 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4422 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4423 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4424 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4425 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4426 }
4427
4428 }
4429
4430 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4431 {
4432 struct attn_route attn, *group_mask;
4433 int port = BP_PORT(bp);
4434 int index;
4435 u32 reg_addr;
4436 u32 val;
4437 u32 aeu_mask;
4438 bool global = false;
4439
4440 /* need to take HW lock because MCP or other port might also
4441 try to handle this event */
4442 bnx2x_acquire_alr(bp);
4443
4444 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4445 #ifndef BNX2X_STOP_ON_ERROR
4446 bp->recovery_state = BNX2X_RECOVERY_INIT;
4447 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4448 /* Disable HW interrupts */
4449 bnx2x_int_disable(bp);
4450 /* In case of parity errors don't handle attentions so that
4451 * other function would "see" parity errors.
4452 */
4453 #else
4454 bnx2x_panic();
4455 #endif
4456 bnx2x_release_alr(bp);
4457 return;
4458 }
4459
4460 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4461 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4462 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4463 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4464 if (!CHIP_IS_E1x(bp))
4465 attn.sig[4] =
4466 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4467 else
4468 attn.sig[4] = 0;
4469
4470 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4471 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4472
4473 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4474 if (deasserted & (1 << index)) {
4475 group_mask = &bp->attn_group[index];
4476
4477 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4478 index,
4479 group_mask->sig[0], group_mask->sig[1],
4480 group_mask->sig[2], group_mask->sig[3],
4481 group_mask->sig[4]);
4482
4483 bnx2x_attn_int_deasserted4(bp,
4484 attn.sig[4] & group_mask->sig[4]);
4485 bnx2x_attn_int_deasserted3(bp,
4486 attn.sig[3] & group_mask->sig[3]);
4487 bnx2x_attn_int_deasserted1(bp,
4488 attn.sig[1] & group_mask->sig[1]);
4489 bnx2x_attn_int_deasserted2(bp,
4490 attn.sig[2] & group_mask->sig[2]);
4491 bnx2x_attn_int_deasserted0(bp,
4492 attn.sig[0] & group_mask->sig[0]);
4493 }
4494 }
4495
4496 bnx2x_release_alr(bp);
4497
4498 if (bp->common.int_block == INT_BLOCK_HC)
4499 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4500 COMMAND_REG_ATTN_BITS_CLR);
4501 else
4502 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4503
4504 val = ~deasserted;
4505 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4506 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4507 REG_WR(bp, reg_addr, val);
4508
4509 if (~bp->attn_state & deasserted)
4510 BNX2X_ERR("IGU ERROR\n");
4511
4512 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4513 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4514
4515 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4516 aeu_mask = REG_RD(bp, reg_addr);
4517
4518 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4519 aeu_mask, deasserted);
4520 aeu_mask |= (deasserted & 0x3ff);
4521 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4522
4523 REG_WR(bp, reg_addr, aeu_mask);
4524 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4525
4526 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4527 bp->attn_state &= ~deasserted;
4528 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4529 }
4530
4531 static void bnx2x_attn_int(struct bnx2x *bp)
4532 {
4533 /* read local copy of bits */
4534 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4535 attn_bits);
4536 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4537 attn_bits_ack);
4538 u32 attn_state = bp->attn_state;
4539
4540 /* look for changed bits */
4541 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4542 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4543
4544 DP(NETIF_MSG_HW,
4545 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4546 attn_bits, attn_ack, asserted, deasserted);
4547
4548 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4549 BNX2X_ERR("BAD attention state\n");
4550
4551 /* handle bits that were raised */
4552 if (asserted)
4553 bnx2x_attn_int_asserted(bp, asserted);
4554
4555 if (deasserted)
4556 bnx2x_attn_int_deasserted(bp, deasserted);
4557 }
4558
4559 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4560 u16 index, u8 op, u8 update)
4561 {
4562 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4563
4564 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4565 igu_addr);
4566 }
4567
4568 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4569 {
4570 /* No memory barriers */
4571 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4572 mmiowb(); /* keep prod updates ordered */
4573 }
4574
4575 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4576 union event_ring_elem *elem)
4577 {
4578 u8 err = elem->message.error;
4579
4580 if (!bp->cnic_eth_dev.starting_cid ||
4581 (cid < bp->cnic_eth_dev.starting_cid &&
4582 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4583 return 1;
4584
4585 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4586
4587 if (unlikely(err)) {
4588
4589 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4590 cid);
4591 bnx2x_panic_dump(bp);
4592 }
4593 bnx2x_cnic_cfc_comp(bp, cid, err);
4594 return 0;
4595 }
4596
4597 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4598 {
4599 struct bnx2x_mcast_ramrod_params rparam;
4600 int rc;
4601
4602 memset(&rparam, 0, sizeof(rparam));
4603
4604 rparam.mcast_obj = &bp->mcast_obj;
4605
4606 netif_addr_lock_bh(bp->dev);
4607
4608 /* Clear pending state for the last command */
4609 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4610
4611 /* If there are pending mcast commands - send them */
4612 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4613 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4614 if (rc < 0)
4615 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4616 rc);
4617 }
4618
4619 netif_addr_unlock_bh(bp->dev);
4620 }
4621
4622 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4623 union event_ring_elem *elem)
4624 {
4625 unsigned long ramrod_flags = 0;
4626 int rc = 0;
4627 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4628 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4629
4630 /* Always push next commands out, don't wait here */
4631 __set_bit(RAMROD_CONT, &ramrod_flags);
4632
4633 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4634 case BNX2X_FILTER_MAC_PENDING:
4635 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4636 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4637 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4638 else
4639 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4640
4641 break;
4642 case BNX2X_FILTER_MCAST_PENDING:
4643 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4644 /* This is only relevant for 57710 where multicast MACs are
4645 * configured as unicast MACs using the same ramrod.
4646 */
4647 bnx2x_handle_mcast_eqe(bp);
4648 return;
4649 default:
4650 BNX2X_ERR("Unsupported classification command: %d\n",
4651 elem->message.data.eth_event.echo);
4652 return;
4653 }
4654
4655 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4656
4657 if (rc < 0)
4658 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4659 else if (rc > 0)
4660 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4661
4662 }
4663
4664 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4665
4666 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4667 {
4668 netif_addr_lock_bh(bp->dev);
4669
4670 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4671
4672 /* Send rx_mode command again if was requested */
4673 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4674 bnx2x_set_storm_rx_mode(bp);
4675 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4676 &bp->sp_state))
4677 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4678 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4679 &bp->sp_state))
4680 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4681
4682 netif_addr_unlock_bh(bp->dev);
4683 }
4684
4685 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4686 union event_ring_elem *elem)
4687 {
4688 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4689 DP(BNX2X_MSG_SP,
4690 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4691 elem->message.data.vif_list_event.func_bit_map);
4692 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4693 elem->message.data.vif_list_event.func_bit_map);
4694 } else if (elem->message.data.vif_list_event.echo ==
4695 VIF_LIST_RULE_SET) {
4696 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4697 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4698 }
4699 }
4700
4701 /* called with rtnl_lock */
4702 static void bnx2x_after_function_update(struct bnx2x *bp)
4703 {
4704 int q, rc;
4705 struct bnx2x_fastpath *fp;
4706 struct bnx2x_queue_state_params queue_params = {NULL};
4707 struct bnx2x_queue_update_params *q_update_params =
4708 &queue_params.params.update;
4709
4710 /* Send Q update command with afex vlan removal values for all Qs */
4711 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4712
4713 /* set silent vlan removal values according to vlan mode */
4714 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4715 &q_update_params->update_flags);
4716 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4717 &q_update_params->update_flags);
4718 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4719
4720 /* in access mode mark mask and value are 0 to strip all vlans */
4721 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4722 q_update_params->silent_removal_value = 0;
4723 q_update_params->silent_removal_mask = 0;
4724 } else {
4725 q_update_params->silent_removal_value =
4726 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4727 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4728 }
4729
4730 for_each_eth_queue(bp, q) {
4731 /* Set the appropriate Queue object */
4732 fp = &bp->fp[q];
4733 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4734
4735 /* send the ramrod */
4736 rc = bnx2x_queue_state_change(bp, &queue_params);
4737 if (rc < 0)
4738 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4739 q);
4740 }
4741
4742 if (!NO_FCOE(bp)) {
4743 fp = &bp->fp[FCOE_IDX(bp)];
4744 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4745
4746 /* clear pending completion bit */
4747 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4748
4749 /* mark latest Q bit */
4750 smp_mb__before_clear_bit();
4751 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4752 smp_mb__after_clear_bit();
4753
4754 /* send Q update ramrod for FCoE Q */
4755 rc = bnx2x_queue_state_change(bp, &queue_params);
4756 if (rc < 0)
4757 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4758 q);
4759 } else {
4760 /* If no FCoE ring - ACK MCP now */
4761 bnx2x_link_report(bp);
4762 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4763 }
4764 }
4765
4766 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4767 struct bnx2x *bp, u32 cid)
4768 {
4769 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4770
4771 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
4772 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4773 else
4774 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4775 }
4776
4777 static void bnx2x_eq_int(struct bnx2x *bp)
4778 {
4779 u16 hw_cons, sw_cons, sw_prod;
4780 union event_ring_elem *elem;
4781 u8 echo;
4782 u32 cid;
4783 u8 opcode;
4784 int spqe_cnt = 0;
4785 struct bnx2x_queue_sp_obj *q_obj;
4786 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4787 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4788
4789 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4790
4791 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4792 * when we get the the next-page we nned to adjust so the loop
4793 * condition below will be met. The next element is the size of a
4794 * regular element and hence incrementing by 1
4795 */
4796 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4797 hw_cons++;
4798
4799 /* This function may never run in parallel with itself for a
4800 * specific bp, thus there is no need in "paired" read memory
4801 * barrier here.
4802 */
4803 sw_cons = bp->eq_cons;
4804 sw_prod = bp->eq_prod;
4805
4806 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4807 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4808
4809 for (; sw_cons != hw_cons;
4810 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4811
4812
4813 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4814
4815 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4816 opcode = elem->message.opcode;
4817
4818
4819 /* handle eq element */
4820 switch (opcode) {
4821 case EVENT_RING_OPCODE_STAT_QUERY:
4822 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
4823 "got statistics comp event %d\n",
4824 bp->stats_comp++);
4825 /* nothing to do with stats comp */
4826 goto next_spqe;
4827
4828 case EVENT_RING_OPCODE_CFC_DEL:
4829 /* handle according to cid range */
4830 /*
4831 * we may want to verify here that the bp state is
4832 * HALTING
4833 */
4834 DP(BNX2X_MSG_SP,
4835 "got delete ramrod for MULTI[%d]\n", cid);
4836
4837 if (CNIC_LOADED(bp) &&
4838 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4839 goto next_spqe;
4840
4841 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4842
4843 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4844 break;
4845
4846
4847
4848 goto next_spqe;
4849
4850 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4851 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
4852 if (f_obj->complete_cmd(bp, f_obj,
4853 BNX2X_F_CMD_TX_STOP))
4854 break;
4855 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4856 goto next_spqe;
4857
4858 case EVENT_RING_OPCODE_START_TRAFFIC:
4859 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
4860 if (f_obj->complete_cmd(bp, f_obj,
4861 BNX2X_F_CMD_TX_START))
4862 break;
4863 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4864 goto next_spqe;
4865
4866 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4867 echo = elem->message.data.function_update_event.echo;
4868 if (echo == SWITCH_UPDATE) {
4869 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4870 "got FUNC_SWITCH_UPDATE ramrod\n");
4871 if (f_obj->complete_cmd(
4872 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
4873 break;
4874
4875 } else {
4876 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
4877 "AFEX: ramrod completed FUNCTION_UPDATE\n");
4878 f_obj->complete_cmd(bp, f_obj,
4879 BNX2X_F_CMD_AFEX_UPDATE);
4880
4881 /* We will perform the Queues update from
4882 * sp_rtnl task as all Queue SP operations
4883 * should run under rtnl_lock.
4884 */
4885 smp_mb__before_clear_bit();
4886 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
4887 &bp->sp_rtnl_state);
4888 smp_mb__after_clear_bit();
4889
4890 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4891 }
4892
4893 goto next_spqe;
4894
4895 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
4896 f_obj->complete_cmd(bp, f_obj,
4897 BNX2X_F_CMD_AFEX_VIFLISTS);
4898 bnx2x_after_afex_vif_lists(bp, elem);
4899 goto next_spqe;
4900 case EVENT_RING_OPCODE_FUNCTION_START:
4901 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4902 "got FUNC_START ramrod\n");
4903 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4904 break;
4905
4906 goto next_spqe;
4907
4908 case EVENT_RING_OPCODE_FUNCTION_STOP:
4909 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4910 "got FUNC_STOP ramrod\n");
4911 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4912 break;
4913
4914 goto next_spqe;
4915 }
4916
4917 switch (opcode | bp->state) {
4918 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4919 BNX2X_STATE_OPEN):
4920 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4921 BNX2X_STATE_OPENING_WAIT4_PORT):
4922 cid = elem->message.data.eth_event.echo &
4923 BNX2X_SWCID_MASK;
4924 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4925 cid);
4926 rss_raw->clear_pending(rss_raw);
4927 break;
4928
4929 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4930 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4931 case (EVENT_RING_OPCODE_SET_MAC |
4932 BNX2X_STATE_CLOSING_WAIT4_HALT):
4933 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4934 BNX2X_STATE_OPEN):
4935 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4936 BNX2X_STATE_DIAG):
4937 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4938 BNX2X_STATE_CLOSING_WAIT4_HALT):
4939 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4940 bnx2x_handle_classification_eqe(bp, elem);
4941 break;
4942
4943 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4944 BNX2X_STATE_OPEN):
4945 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4946 BNX2X_STATE_DIAG):
4947 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4948 BNX2X_STATE_CLOSING_WAIT4_HALT):
4949 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4950 bnx2x_handle_mcast_eqe(bp);
4951 break;
4952
4953 case (EVENT_RING_OPCODE_FILTERS_RULES |
4954 BNX2X_STATE_OPEN):
4955 case (EVENT_RING_OPCODE_FILTERS_RULES |
4956 BNX2X_STATE_DIAG):
4957 case (EVENT_RING_OPCODE_FILTERS_RULES |
4958 BNX2X_STATE_CLOSING_WAIT4_HALT):
4959 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4960 bnx2x_handle_rx_mode_eqe(bp);
4961 break;
4962 default:
4963 /* unknown event log error and continue */
4964 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4965 elem->message.opcode, bp->state);
4966 }
4967 next_spqe:
4968 spqe_cnt++;
4969 } /* for */
4970
4971 smp_mb__before_atomic_inc();
4972 atomic_add(spqe_cnt, &bp->eq_spq_left);
4973
4974 bp->eq_cons = sw_cons;
4975 bp->eq_prod = sw_prod;
4976 /* Make sure that above mem writes were issued towards the memory */
4977 smp_wmb();
4978
4979 /* update producer */
4980 bnx2x_update_eq_prod(bp, bp->eq_prod);
4981 }
4982
4983 static void bnx2x_sp_task(struct work_struct *work)
4984 {
4985 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4986 u16 status;
4987
4988 status = bnx2x_update_dsb_idx(bp);
4989 /* if (status == 0) */
4990 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4991
4992 DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status);
4993
4994 /* HW attentions */
4995 if (status & BNX2X_DEF_SB_ATT_IDX) {
4996 bnx2x_attn_int(bp);
4997 status &= ~BNX2X_DEF_SB_ATT_IDX;
4998 }
4999
5000 /* SP events: STAT_QUERY and others */
5001 if (status & BNX2X_DEF_SB_IDX) {
5002 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5003
5004 if (FCOE_INIT(bp) &&
5005 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5006 /*
5007 * Prevent local bottom-halves from running as
5008 * we are going to change the local NAPI list.
5009 */
5010 local_bh_disable();
5011 napi_schedule(&bnx2x_fcoe(bp, napi));
5012 local_bh_enable();
5013 }
5014
5015 /* Handle EQ completions */
5016 bnx2x_eq_int(bp);
5017
5018 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5019 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5020
5021 status &= ~BNX2X_DEF_SB_IDX;
5022 }
5023
5024 if (unlikely(status))
5025 DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n",
5026 status);
5027
5028 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5029 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5030
5031 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5032 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5033 &bp->sp_state)) {
5034 bnx2x_link_report(bp);
5035 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5036 }
5037 }
5038
5039 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5040 {
5041 struct net_device *dev = dev_instance;
5042 struct bnx2x *bp = netdev_priv(dev);
5043
5044 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5045 IGU_INT_DISABLE, 0);
5046
5047 #ifdef BNX2X_STOP_ON_ERROR
5048 if (unlikely(bp->panic))
5049 return IRQ_HANDLED;
5050 #endif
5051
5052 if (CNIC_LOADED(bp)) {
5053 struct cnic_ops *c_ops;
5054
5055 rcu_read_lock();
5056 c_ops = rcu_dereference(bp->cnic_ops);
5057 if (c_ops)
5058 c_ops->cnic_handler(bp->cnic_data, NULL);
5059 rcu_read_unlock();
5060 }
5061
5062 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
5063
5064 return IRQ_HANDLED;
5065 }
5066
5067 /* end of slow path */
5068
5069
5070 void bnx2x_drv_pulse(struct bnx2x *bp)
5071 {
5072 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5073 bp->fw_drv_pulse_wr_seq);
5074 }
5075
5076
5077 static void bnx2x_timer(unsigned long data)
5078 {
5079 struct bnx2x *bp = (struct bnx2x *) data;
5080
5081 if (!netif_running(bp->dev))
5082 return;
5083
5084 if (!BP_NOMCP(bp)) {
5085 int mb_idx = BP_FW_MB_IDX(bp);
5086 u32 drv_pulse;
5087 u32 mcp_pulse;
5088
5089 ++bp->fw_drv_pulse_wr_seq;
5090 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5091 /* TBD - add SYSTEM_TIME */
5092 drv_pulse = bp->fw_drv_pulse_wr_seq;
5093 bnx2x_drv_pulse(bp);
5094
5095 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5096 MCP_PULSE_SEQ_MASK);
5097 /* The delta between driver pulse and mcp response
5098 * should be 1 (before mcp response) or 0 (after mcp response)
5099 */
5100 if ((drv_pulse != mcp_pulse) &&
5101 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5102 /* someone lost a heartbeat... */
5103 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5104 drv_pulse, mcp_pulse);
5105 }
5106 }
5107
5108 if (bp->state == BNX2X_STATE_OPEN)
5109 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5110
5111 mod_timer(&bp->timer, jiffies + bp->current_interval);
5112 }
5113
5114 /* end of Statistics */
5115
5116 /* nic init */
5117
5118 /*
5119 * nic init service functions
5120 */
5121
5122 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5123 {
5124 u32 i;
5125 if (!(len%4) && !(addr%4))
5126 for (i = 0; i < len; i += 4)
5127 REG_WR(bp, addr + i, fill);
5128 else
5129 for (i = 0; i < len; i++)
5130 REG_WR8(bp, addr + i, fill);
5131
5132 }
5133
5134 /* helper: writes FP SP data to FW - data_size in dwords */
5135 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5136 int fw_sb_id,
5137 u32 *sb_data_p,
5138 u32 data_size)
5139 {
5140 int index;
5141 for (index = 0; index < data_size; index++)
5142 REG_WR(bp, BAR_CSTRORM_INTMEM +
5143 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5144 sizeof(u32)*index,
5145 *(sb_data_p + index));
5146 }
5147
5148 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5149 {
5150 u32 *sb_data_p;
5151 u32 data_size = 0;
5152 struct hc_status_block_data_e2 sb_data_e2;
5153 struct hc_status_block_data_e1x sb_data_e1x;
5154
5155 /* disable the function first */
5156 if (!CHIP_IS_E1x(bp)) {
5157 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5158 sb_data_e2.common.state = SB_DISABLED;
5159 sb_data_e2.common.p_func.vf_valid = false;
5160 sb_data_p = (u32 *)&sb_data_e2;
5161 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5162 } else {
5163 memset(&sb_data_e1x, 0,
5164 sizeof(struct hc_status_block_data_e1x));
5165 sb_data_e1x.common.state = SB_DISABLED;
5166 sb_data_e1x.common.p_func.vf_valid = false;
5167 sb_data_p = (u32 *)&sb_data_e1x;
5168 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5169 }
5170 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5171
5172 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5173 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5174 CSTORM_STATUS_BLOCK_SIZE);
5175 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5176 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5177 CSTORM_SYNC_BLOCK_SIZE);
5178 }
5179
5180 /* helper: writes SP SB data to FW */
5181 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5182 struct hc_sp_status_block_data *sp_sb_data)
5183 {
5184 int func = BP_FUNC(bp);
5185 int i;
5186 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5187 REG_WR(bp, BAR_CSTRORM_INTMEM +
5188 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5189 i*sizeof(u32),
5190 *((u32 *)sp_sb_data + i));
5191 }
5192
5193 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5194 {
5195 int func = BP_FUNC(bp);
5196 struct hc_sp_status_block_data sp_sb_data;
5197 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5198
5199 sp_sb_data.state = SB_DISABLED;
5200 sp_sb_data.p_func.vf_valid = false;
5201
5202 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5203
5204 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5205 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5206 CSTORM_SP_STATUS_BLOCK_SIZE);
5207 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5208 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5209 CSTORM_SP_SYNC_BLOCK_SIZE);
5210
5211 }
5212
5213
5214 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5215 int igu_sb_id, int igu_seg_id)
5216 {
5217 hc_sm->igu_sb_id = igu_sb_id;
5218 hc_sm->igu_seg_id = igu_seg_id;
5219 hc_sm->timer_value = 0xFF;
5220 hc_sm->time_to_expire = 0xFFFFFFFF;
5221 }
5222
5223
5224 /* allocates state machine ids. */
5225 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5226 {
5227 /* zero out state machine indices */
5228 /* rx indices */
5229 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5230
5231 /* tx indices */
5232 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5233 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5234 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5235 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5236
5237 /* map indices */
5238 /* rx indices */
5239 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5240 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5241
5242 /* tx indices */
5243 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5244 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5245 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5246 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5247 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5248 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5249 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5250 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5251 }
5252
5253 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5254 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5255 {
5256 int igu_seg_id;
5257
5258 struct hc_status_block_data_e2 sb_data_e2;
5259 struct hc_status_block_data_e1x sb_data_e1x;
5260 struct hc_status_block_sm *hc_sm_p;
5261 int data_size;
5262 u32 *sb_data_p;
5263
5264 if (CHIP_INT_MODE_IS_BC(bp))
5265 igu_seg_id = HC_SEG_ACCESS_NORM;
5266 else
5267 igu_seg_id = IGU_SEG_ACCESS_NORM;
5268
5269 bnx2x_zero_fp_sb(bp, fw_sb_id);
5270
5271 if (!CHIP_IS_E1x(bp)) {
5272 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5273 sb_data_e2.common.state = SB_ENABLED;
5274 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5275 sb_data_e2.common.p_func.vf_id = vfid;
5276 sb_data_e2.common.p_func.vf_valid = vf_valid;
5277 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5278 sb_data_e2.common.same_igu_sb_1b = true;
5279 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5280 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5281 hc_sm_p = sb_data_e2.common.state_machine;
5282 sb_data_p = (u32 *)&sb_data_e2;
5283 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5284 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5285 } else {
5286 memset(&sb_data_e1x, 0,
5287 sizeof(struct hc_status_block_data_e1x));
5288 sb_data_e1x.common.state = SB_ENABLED;
5289 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5290 sb_data_e1x.common.p_func.vf_id = 0xff;
5291 sb_data_e1x.common.p_func.vf_valid = false;
5292 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5293 sb_data_e1x.common.same_igu_sb_1b = true;
5294 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5295 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5296 hc_sm_p = sb_data_e1x.common.state_machine;
5297 sb_data_p = (u32 *)&sb_data_e1x;
5298 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5299 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5300 }
5301
5302 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5303 igu_sb_id, igu_seg_id);
5304 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5305 igu_sb_id, igu_seg_id);
5306
5307 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5308
5309 /* write indecies to HW */
5310 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5311 }
5312
5313 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5314 u16 tx_usec, u16 rx_usec)
5315 {
5316 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5317 false, rx_usec);
5318 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5319 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5320 tx_usec);
5321 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5322 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5323 tx_usec);
5324 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5325 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5326 tx_usec);
5327 }
5328
5329 static void bnx2x_init_def_sb(struct bnx2x *bp)
5330 {
5331 struct host_sp_status_block *def_sb = bp->def_status_blk;
5332 dma_addr_t mapping = bp->def_status_blk_mapping;
5333 int igu_sp_sb_index;
5334 int igu_seg_id;
5335 int port = BP_PORT(bp);
5336 int func = BP_FUNC(bp);
5337 int reg_offset, reg_offset_en5;
5338 u64 section;
5339 int index;
5340 struct hc_sp_status_block_data sp_sb_data;
5341 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5342
5343 if (CHIP_INT_MODE_IS_BC(bp)) {
5344 igu_sp_sb_index = DEF_SB_IGU_ID;
5345 igu_seg_id = HC_SEG_ACCESS_DEF;
5346 } else {
5347 igu_sp_sb_index = bp->igu_dsb_id;
5348 igu_seg_id = IGU_SEG_ACCESS_DEF;
5349 }
5350
5351 /* ATTN */
5352 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5353 atten_status_block);
5354 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5355
5356 bp->attn_state = 0;
5357
5358 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5359 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5360 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5361 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5362 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5363 int sindex;
5364 /* take care of sig[0]..sig[4] */
5365 for (sindex = 0; sindex < 4; sindex++)
5366 bp->attn_group[index].sig[sindex] =
5367 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5368
5369 if (!CHIP_IS_E1x(bp))
5370 /*
5371 * enable5 is separate from the rest of the registers,
5372 * and therefore the address skip is 4
5373 * and not 16 between the different groups
5374 */
5375 bp->attn_group[index].sig[4] = REG_RD(bp,
5376 reg_offset_en5 + 0x4*index);
5377 else
5378 bp->attn_group[index].sig[4] = 0;
5379 }
5380
5381 if (bp->common.int_block == INT_BLOCK_HC) {
5382 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5383 HC_REG_ATTN_MSG0_ADDR_L);
5384
5385 REG_WR(bp, reg_offset, U64_LO(section));
5386 REG_WR(bp, reg_offset + 4, U64_HI(section));
5387 } else if (!CHIP_IS_E1x(bp)) {
5388 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5389 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5390 }
5391
5392 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5393 sp_sb);
5394
5395 bnx2x_zero_sp_sb(bp);
5396
5397 sp_sb_data.state = SB_ENABLED;
5398 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5399 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5400 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5401 sp_sb_data.igu_seg_id = igu_seg_id;
5402 sp_sb_data.p_func.pf_id = func;
5403 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5404 sp_sb_data.p_func.vf_id = 0xff;
5405
5406 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5407
5408 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5409 }
5410
5411 void bnx2x_update_coalesce(struct bnx2x *bp)
5412 {
5413 int i;
5414
5415 for_each_eth_queue(bp, i)
5416 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5417 bp->tx_ticks, bp->rx_ticks);
5418 }
5419
5420 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5421 {
5422 spin_lock_init(&bp->spq_lock);
5423 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5424
5425 bp->spq_prod_idx = 0;
5426 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5427 bp->spq_prod_bd = bp->spq;
5428 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5429 }
5430
5431 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5432 {
5433 int i;
5434 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5435 union event_ring_elem *elem =
5436 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5437
5438 elem->next_page.addr.hi =
5439 cpu_to_le32(U64_HI(bp->eq_mapping +
5440 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5441 elem->next_page.addr.lo =
5442 cpu_to_le32(U64_LO(bp->eq_mapping +
5443 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5444 }
5445 bp->eq_cons = 0;
5446 bp->eq_prod = NUM_EQ_DESC;
5447 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5448 /* we want a warning message before it gets rought... */
5449 atomic_set(&bp->eq_spq_left,
5450 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5451 }
5452
5453
5454 /* called with netif_addr_lock_bh() */
5455 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5456 unsigned long rx_mode_flags,
5457 unsigned long rx_accept_flags,
5458 unsigned long tx_accept_flags,
5459 unsigned long ramrod_flags)
5460 {
5461 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5462 int rc;
5463
5464 memset(&ramrod_param, 0, sizeof(ramrod_param));
5465
5466 /* Prepare ramrod parameters */
5467 ramrod_param.cid = 0;
5468 ramrod_param.cl_id = cl_id;
5469 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5470 ramrod_param.func_id = BP_FUNC(bp);
5471
5472 ramrod_param.pstate = &bp->sp_state;
5473 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5474
5475 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5476 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5477
5478 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5479
5480 ramrod_param.ramrod_flags = ramrod_flags;
5481 ramrod_param.rx_mode_flags = rx_mode_flags;
5482
5483 ramrod_param.rx_accept_flags = rx_accept_flags;
5484 ramrod_param.tx_accept_flags = tx_accept_flags;
5485
5486 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5487 if (rc < 0) {
5488 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5489 return;
5490 }
5491 }
5492
5493 /* called with netif_addr_lock_bh() */
5494 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5495 {
5496 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5497 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5498
5499 if (!NO_FCOE(bp))
5500
5501 /* Configure rx_mode of FCoE Queue */
5502 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5503
5504 switch (bp->rx_mode) {
5505 case BNX2X_RX_MODE_NONE:
5506 /*
5507 * 'drop all' supersedes any accept flags that may have been
5508 * passed to the function.
5509 */
5510 break;
5511 case BNX2X_RX_MODE_NORMAL:
5512 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5513 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5514 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5515
5516 /* internal switching mode */
5517 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5518 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5519 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5520
5521 break;
5522 case BNX2X_RX_MODE_ALLMULTI:
5523 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5524 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5525 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5526
5527 /* internal switching mode */
5528 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5529 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5530 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5531
5532 break;
5533 case BNX2X_RX_MODE_PROMISC:
5534 /* According to deffinition of SI mode, iface in promisc mode
5535 * should receive matched and unmatched (in resolution of port)
5536 * unicast packets.
5537 */
5538 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5539 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5540 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5541 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5542
5543 /* internal switching mode */
5544 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5545 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5546
5547 if (IS_MF_SI(bp))
5548 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5549 else
5550 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5551
5552 break;
5553 default:
5554 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5555 return;
5556 }
5557
5558 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5559 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5560 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5561 }
5562
5563 __set_bit(RAMROD_RX, &ramrod_flags);
5564 __set_bit(RAMROD_TX, &ramrod_flags);
5565
5566 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5567 tx_accept_flags, ramrod_flags);
5568 }
5569
5570 static void bnx2x_init_internal_common(struct bnx2x *bp)
5571 {
5572 int i;
5573
5574 if (IS_MF_SI(bp))
5575 /*
5576 * In switch independent mode, the TSTORM needs to accept
5577 * packets that failed classification, since approximate match
5578 * mac addresses aren't written to NIG LLH
5579 */
5580 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5581 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5582 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5583 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5584 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5585
5586 /* Zero this manually as its initialization is
5587 currently missing in the initTool */
5588 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5589 REG_WR(bp, BAR_USTRORM_INTMEM +
5590 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5591 if (!CHIP_IS_E1x(bp)) {
5592 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5593 CHIP_INT_MODE_IS_BC(bp) ?
5594 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5595 }
5596 }
5597
5598 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5599 {
5600 switch (load_code) {
5601 case FW_MSG_CODE_DRV_LOAD_COMMON:
5602 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5603 bnx2x_init_internal_common(bp);
5604 /* no break */
5605
5606 case FW_MSG_CODE_DRV_LOAD_PORT:
5607 /* nothing to do */
5608 /* no break */
5609
5610 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5611 /* internal memory per function is
5612 initialized inside bnx2x_pf_init */
5613 break;
5614
5615 default:
5616 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5617 break;
5618 }
5619 }
5620
5621 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5622 {
5623 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
5624 }
5625
5626 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5627 {
5628 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
5629 }
5630
5631 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5632 {
5633 if (CHIP_IS_E1x(fp->bp))
5634 return BP_L_ID(fp->bp) + fp->index;
5635 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5636 return bnx2x_fp_igu_sb_id(fp);
5637 }
5638
5639 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5640 {
5641 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5642 u8 cos;
5643 unsigned long q_type = 0;
5644 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5645 fp->rx_queue = fp_idx;
5646 fp->cid = fp_idx;
5647 fp->cl_id = bnx2x_fp_cl_id(fp);
5648 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5649 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5650 /* qZone id equals to FW (per path) client id */
5651 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5652
5653 /* init shortcut */
5654 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5655
5656 /* Setup SB indicies */
5657 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5658
5659 /* Configure Queue State object */
5660 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5661 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5662
5663 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5664
5665 /* init tx data */
5666 for_each_cos_in_tx_queue(fp, cos) {
5667 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5668 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5669 FP_COS_TO_TXQ(fp, cos, bp),
5670 BNX2X_TX_SB_INDEX_BASE + cos, fp);
5671 cids[cos] = fp->txdata_ptr[cos]->cid;
5672 }
5673
5674 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5675 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5676 bnx2x_sp_mapping(bp, q_rdata), q_type);
5677
5678 /**
5679 * Configure classification DBs: Always enable Tx switching
5680 */
5681 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5682
5683 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5684 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5685 fp->igu_sb_id);
5686 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5687 fp->fw_sb_id, fp->igu_sb_id);
5688
5689 bnx2x_update_fpsb_idx(fp);
5690 }
5691
5692 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5693 {
5694 int i;
5695
5696 for (i = 1; i <= NUM_TX_RINGS; i++) {
5697 struct eth_tx_next_bd *tx_next_bd =
5698 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5699
5700 tx_next_bd->addr_hi =
5701 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5702 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5703 tx_next_bd->addr_lo =
5704 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5705 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5706 }
5707
5708 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5709 txdata->tx_db.data.zero_fill1 = 0;
5710 txdata->tx_db.data.prod = 0;
5711
5712 txdata->tx_pkt_prod = 0;
5713 txdata->tx_pkt_cons = 0;
5714 txdata->tx_bd_prod = 0;
5715 txdata->tx_bd_cons = 0;
5716 txdata->tx_pkt = 0;
5717 }
5718
5719 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
5720 {
5721 int i;
5722
5723 for_each_tx_queue_cnic(bp, i)
5724 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
5725 }
5726 static void bnx2x_init_tx_rings(struct bnx2x *bp)
5727 {
5728 int i;
5729 u8 cos;
5730
5731 for_each_eth_queue(bp, i)
5732 for_each_cos_in_tx_queue(&bp->fp[i], cos)
5733 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
5734 }
5735
5736 void bnx2x_nic_init_cnic(struct bnx2x *bp)
5737 {
5738 if (!NO_FCOE(bp))
5739 bnx2x_init_fcoe_fp(bp);
5740
5741 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5742 BNX2X_VF_ID_INVALID, false,
5743 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5744
5745 /* ensure status block indices were read */
5746 rmb();
5747 bnx2x_init_rx_rings_cnic(bp);
5748 bnx2x_init_tx_rings_cnic(bp);
5749
5750 /* flush all */
5751 mb();
5752 mmiowb();
5753 }
5754
5755 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5756 {
5757 int i;
5758
5759 for_each_eth_queue(bp, i)
5760 bnx2x_init_eth_fp(bp, i);
5761 /* Initialize MOD_ABS interrupts */
5762 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5763 bp->common.shmem_base, bp->common.shmem2_base,
5764 BP_PORT(bp));
5765 /* ensure status block indices were read */
5766 rmb();
5767
5768 bnx2x_init_def_sb(bp);
5769 bnx2x_update_dsb_idx(bp);
5770 bnx2x_init_rx_rings(bp);
5771 bnx2x_init_tx_rings(bp);
5772 bnx2x_init_sp_ring(bp);
5773 bnx2x_init_eq_ring(bp);
5774 bnx2x_init_internal(bp, load_code);
5775 bnx2x_pf_init(bp);
5776 bnx2x_stats_init(bp);
5777
5778 /* flush all before enabling interrupts */
5779 mb();
5780 mmiowb();
5781
5782 bnx2x_int_enable(bp);
5783
5784 /* Check for SPIO5 */
5785 bnx2x_attn_int_deasserted0(bp,
5786 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5787 AEU_INPUTS_ATTN_BITS_SPIO5);
5788 }
5789
5790 /* end of nic init */
5791
5792 /*
5793 * gzip service functions
5794 */
5795
5796 static int bnx2x_gunzip_init(struct bnx2x *bp)
5797 {
5798 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5799 &bp->gunzip_mapping, GFP_KERNEL);
5800 if (bp->gunzip_buf == NULL)
5801 goto gunzip_nomem1;
5802
5803 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5804 if (bp->strm == NULL)
5805 goto gunzip_nomem2;
5806
5807 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5808 if (bp->strm->workspace == NULL)
5809 goto gunzip_nomem3;
5810
5811 return 0;
5812
5813 gunzip_nomem3:
5814 kfree(bp->strm);
5815 bp->strm = NULL;
5816
5817 gunzip_nomem2:
5818 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5819 bp->gunzip_mapping);
5820 bp->gunzip_buf = NULL;
5821
5822 gunzip_nomem1:
5823 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
5824 return -ENOMEM;
5825 }
5826
5827 static void bnx2x_gunzip_end(struct bnx2x *bp)
5828 {
5829 if (bp->strm) {
5830 vfree(bp->strm->workspace);
5831 kfree(bp->strm);
5832 bp->strm = NULL;
5833 }
5834
5835 if (bp->gunzip_buf) {
5836 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5837 bp->gunzip_mapping);
5838 bp->gunzip_buf = NULL;
5839 }
5840 }
5841
5842 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5843 {
5844 int n, rc;
5845
5846 /* check gzip header */
5847 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5848 BNX2X_ERR("Bad gzip header\n");
5849 return -EINVAL;
5850 }
5851
5852 n = 10;
5853
5854 #define FNAME 0x8
5855
5856 if (zbuf[3] & FNAME)
5857 while ((zbuf[n++] != 0) && (n < len));
5858
5859 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5860 bp->strm->avail_in = len - n;
5861 bp->strm->next_out = bp->gunzip_buf;
5862 bp->strm->avail_out = FW_BUF_SIZE;
5863
5864 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5865 if (rc != Z_OK)
5866 return rc;
5867
5868 rc = zlib_inflate(bp->strm, Z_FINISH);
5869 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5870 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5871 bp->strm->msg);
5872
5873 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5874 if (bp->gunzip_outlen & 0x3)
5875 netdev_err(bp->dev,
5876 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
5877 bp->gunzip_outlen);
5878 bp->gunzip_outlen >>= 2;
5879
5880 zlib_inflateEnd(bp->strm);
5881
5882 if (rc == Z_STREAM_END)
5883 return 0;
5884
5885 return rc;
5886 }
5887
5888 /* nic load/unload */
5889
5890 /*
5891 * General service functions
5892 */
5893
5894 /* send a NIG loopback debug packet */
5895 static void bnx2x_lb_pckt(struct bnx2x *bp)
5896 {
5897 u32 wb_write[3];
5898
5899 /* Ethernet source and destination addresses */
5900 wb_write[0] = 0x55555555;
5901 wb_write[1] = 0x55555555;
5902 wb_write[2] = 0x20; /* SOP */
5903 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5904
5905 /* NON-IP protocol */
5906 wb_write[0] = 0x09000000;
5907 wb_write[1] = 0x55555555;
5908 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5909 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5910 }
5911
5912 /* some of the internal memories
5913 * are not directly readable from the driver
5914 * to test them we send debug packets
5915 */
5916 static int bnx2x_int_mem_test(struct bnx2x *bp)
5917 {
5918 int factor;
5919 int count, i;
5920 u32 val = 0;
5921
5922 if (CHIP_REV_IS_FPGA(bp))
5923 factor = 120;
5924 else if (CHIP_REV_IS_EMUL(bp))
5925 factor = 200;
5926 else
5927 factor = 1;
5928
5929 /* Disable inputs of parser neighbor blocks */
5930 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5931 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5932 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5933 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5934
5935 /* Write 0 to parser credits for CFC search request */
5936 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5937
5938 /* send Ethernet packet */
5939 bnx2x_lb_pckt(bp);
5940
5941 /* TODO do i reset NIG statistic? */
5942 /* Wait until NIG register shows 1 packet of size 0x10 */
5943 count = 1000 * factor;
5944 while (count) {
5945
5946 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5947 val = *bnx2x_sp(bp, wb_data[0]);
5948 if (val == 0x10)
5949 break;
5950
5951 msleep(10);
5952 count--;
5953 }
5954 if (val != 0x10) {
5955 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5956 return -1;
5957 }
5958
5959 /* Wait until PRS register shows 1 packet */
5960 count = 1000 * factor;
5961 while (count) {
5962 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5963 if (val == 1)
5964 break;
5965
5966 msleep(10);
5967 count--;
5968 }
5969 if (val != 0x1) {
5970 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5971 return -2;
5972 }
5973
5974 /* Reset and init BRB, PRS */
5975 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5976 msleep(50);
5977 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5978 msleep(50);
5979 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5980 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5981
5982 DP(NETIF_MSG_HW, "part2\n");
5983
5984 /* Disable inputs of parser neighbor blocks */
5985 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5986 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5987 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5988 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5989
5990 /* Write 0 to parser credits for CFC search request */
5991 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5992
5993 /* send 10 Ethernet packets */
5994 for (i = 0; i < 10; i++)
5995 bnx2x_lb_pckt(bp);
5996
5997 /* Wait until NIG register shows 10 + 1
5998 packets of size 11*0x10 = 0xb0 */
5999 count = 1000 * factor;
6000 while (count) {
6001
6002 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6003 val = *bnx2x_sp(bp, wb_data[0]);
6004 if (val == 0xb0)
6005 break;
6006
6007 msleep(10);
6008 count--;
6009 }
6010 if (val != 0xb0) {
6011 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6012 return -3;
6013 }
6014
6015 /* Wait until PRS register shows 2 packets */
6016 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6017 if (val != 2)
6018 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6019
6020 /* Write 1 to parser credits for CFC search request */
6021 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6022
6023 /* Wait until PRS register shows 3 packets */
6024 msleep(10 * factor);
6025 /* Wait until NIG register shows 1 packet of size 0x10 */
6026 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6027 if (val != 3)
6028 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6029
6030 /* clear NIG EOP FIFO */
6031 for (i = 0; i < 11; i++)
6032 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6033 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6034 if (val != 1) {
6035 BNX2X_ERR("clear of NIG failed\n");
6036 return -4;
6037 }
6038
6039 /* Reset and init BRB, PRS, NIG */
6040 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6041 msleep(50);
6042 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6043 msleep(50);
6044 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6045 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6046 if (!CNIC_SUPPORT(bp))
6047 /* set NIC mode */
6048 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6049
6050 /* Enable inputs of parser neighbor blocks */
6051 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6052 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6053 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6054 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6055
6056 DP(NETIF_MSG_HW, "done\n");
6057
6058 return 0; /* OK */
6059 }
6060
6061 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6062 {
6063 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6064 if (!CHIP_IS_E1x(bp))
6065 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6066 else
6067 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6068 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6069 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6070 /*
6071 * mask read length error interrupts in brb for parser
6072 * (parsing unit and 'checksum and crc' unit)
6073 * these errors are legal (PU reads fixed length and CAC can cause
6074 * read length error on truncated packets)
6075 */
6076 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6077 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6078 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6079 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6080 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6081 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6082 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6083 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6084 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6085 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6086 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6087 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6088 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6089 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6090 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6091 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6092 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6093 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6094 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6095
6096 if (CHIP_REV_IS_FPGA(bp))
6097 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
6098 else if (!CHIP_IS_E1x(bp))
6099 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
6100 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
6101 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
6102 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
6103 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
6104 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
6105 else
6106 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
6107 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6108 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6109 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6110 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6111
6112 if (!CHIP_IS_E1x(bp))
6113 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6114 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6115
6116 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6117 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6118 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6119 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6120 }
6121
6122 static void bnx2x_reset_common(struct bnx2x *bp)
6123 {
6124 u32 val = 0x1400;
6125
6126 /* reset_common */
6127 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6128 0xd3ffff7f);
6129
6130 if (CHIP_IS_E3(bp)) {
6131 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6132 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6133 }
6134
6135 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6136 }
6137
6138 static void bnx2x_setup_dmae(struct bnx2x *bp)
6139 {
6140 bp->dmae_ready = 0;
6141 spin_lock_init(&bp->dmae_lock);
6142 }
6143
6144 static void bnx2x_init_pxp(struct bnx2x *bp)
6145 {
6146 u16 devctl;
6147 int r_order, w_order;
6148
6149 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6150 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6151 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6152 if (bp->mrrs == -1)
6153 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6154 else {
6155 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6156 r_order = bp->mrrs;
6157 }
6158
6159 bnx2x_init_pxp_arb(bp, r_order, w_order);
6160 }
6161
6162 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6163 {
6164 int is_required;
6165 u32 val;
6166 int port;
6167
6168 if (BP_NOMCP(bp))
6169 return;
6170
6171 is_required = 0;
6172 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6173 SHARED_HW_CFG_FAN_FAILURE_MASK;
6174
6175 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6176 is_required = 1;
6177
6178 /*
6179 * The fan failure mechanism is usually related to the PHY type since
6180 * the power consumption of the board is affected by the PHY. Currently,
6181 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6182 */
6183 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6184 for (port = PORT_0; port < PORT_MAX; port++) {
6185 is_required |=
6186 bnx2x_fan_failure_det_req(
6187 bp,
6188 bp->common.shmem_base,
6189 bp->common.shmem2_base,
6190 port);
6191 }
6192
6193 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6194
6195 if (is_required == 0)
6196 return;
6197
6198 /* Fan failure is indicated by SPIO 5 */
6199 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
6200 MISC_REGISTERS_SPIO_INPUT_HI_Z);
6201
6202 /* set to active low mode */
6203 val = REG_RD(bp, MISC_REG_SPIO_INT);
6204 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
6205 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
6206 REG_WR(bp, MISC_REG_SPIO_INT, val);
6207
6208 /* enable interrupt to signal the IGU */
6209 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6210 val |= (1 << MISC_REGISTERS_SPIO_5);
6211 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6212 }
6213
6214 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
6215 {
6216 u32 offset = 0;
6217
6218 if (CHIP_IS_E1(bp))
6219 return;
6220 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
6221 return;
6222
6223 switch (BP_ABS_FUNC(bp)) {
6224 case 0:
6225 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
6226 break;
6227 case 1:
6228 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
6229 break;
6230 case 2:
6231 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
6232 break;
6233 case 3:
6234 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
6235 break;
6236 case 4:
6237 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
6238 break;
6239 case 5:
6240 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
6241 break;
6242 case 6:
6243 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
6244 break;
6245 case 7:
6246 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
6247 break;
6248 default:
6249 return;
6250 }
6251
6252 REG_WR(bp, offset, pretend_func_num);
6253 REG_RD(bp, offset);
6254 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
6255 }
6256
6257 void bnx2x_pf_disable(struct bnx2x *bp)
6258 {
6259 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6260 val &= ~IGU_PF_CONF_FUNC_EN;
6261
6262 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6263 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6264 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6265 }
6266
6267 static void bnx2x__common_init_phy(struct bnx2x *bp)
6268 {
6269 u32 shmem_base[2], shmem2_base[2];
6270 shmem_base[0] = bp->common.shmem_base;
6271 shmem2_base[0] = bp->common.shmem2_base;
6272 if (!CHIP_IS_E1x(bp)) {
6273 shmem_base[1] =
6274 SHMEM2_RD(bp, other_shmem_base_addr);
6275 shmem2_base[1] =
6276 SHMEM2_RD(bp, other_shmem2_base_addr);
6277 }
6278 bnx2x_acquire_phy_lock(bp);
6279 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6280 bp->common.chip_id);
6281 bnx2x_release_phy_lock(bp);
6282 }
6283
6284 /**
6285 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6286 *
6287 * @bp: driver handle
6288 */
6289 static int bnx2x_init_hw_common(struct bnx2x *bp)
6290 {
6291 u32 val;
6292
6293 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6294
6295 /*
6296 * take the UNDI lock to protect undi_unload flow from accessing
6297 * registers while we're resetting the chip
6298 */
6299 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6300
6301 bnx2x_reset_common(bp);
6302 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6303
6304 val = 0xfffc;
6305 if (CHIP_IS_E3(bp)) {
6306 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6307 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6308 }
6309 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6310
6311 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6312
6313 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6314
6315 if (!CHIP_IS_E1x(bp)) {
6316 u8 abs_func_id;
6317
6318 /**
6319 * 4-port mode or 2-port mode we need to turn of master-enable
6320 * for everyone, after that, turn it back on for self.
6321 * so, we disregard multi-function or not, and always disable
6322 * for all functions on the given path, this means 0,2,4,6 for
6323 * path 0 and 1,3,5,7 for path 1
6324 */
6325 for (abs_func_id = BP_PATH(bp);
6326 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6327 if (abs_func_id == BP_ABS_FUNC(bp)) {
6328 REG_WR(bp,
6329 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6330 1);
6331 continue;
6332 }
6333
6334 bnx2x_pretend_func(bp, abs_func_id);
6335 /* clear pf enable */
6336 bnx2x_pf_disable(bp);
6337 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6338 }
6339 }
6340
6341 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6342 if (CHIP_IS_E1(bp)) {
6343 /* enable HW interrupt from PXP on USDM overflow
6344 bit 16 on INT_MASK_0 */
6345 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6346 }
6347
6348 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6349 bnx2x_init_pxp(bp);
6350
6351 #ifdef __BIG_ENDIAN
6352 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6353 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6354 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6355 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6356 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6357 /* make sure this value is 0 */
6358 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6359
6360 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6361 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6362 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6363 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6364 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6365 #endif
6366
6367 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6368
6369 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6370 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6371
6372 /* let the HW do it's magic ... */
6373 msleep(100);
6374 /* finish PXP init */
6375 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6376 if (val != 1) {
6377 BNX2X_ERR("PXP2 CFG failed\n");
6378 return -EBUSY;
6379 }
6380 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6381 if (val != 1) {
6382 BNX2X_ERR("PXP2 RD_INIT failed\n");
6383 return -EBUSY;
6384 }
6385
6386 /* Timers bug workaround E2 only. We need to set the entire ILT to
6387 * have entries with value "0" and valid bit on.
6388 * This needs to be done by the first PF that is loaded in a path
6389 * (i.e. common phase)
6390 */
6391 if (!CHIP_IS_E1x(bp)) {
6392 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6393 * (i.e. vnic3) to start even if it is marked as "scan-off".
6394 * This occurs when a different function (func2,3) is being marked
6395 * as "scan-off". Real-life scenario for example: if a driver is being
6396 * load-unloaded while func6,7 are down. This will cause the timer to access
6397 * the ilt, translate to a logical address and send a request to read/write.
6398 * Since the ilt for the function that is down is not valid, this will cause
6399 * a translation error which is unrecoverable.
6400 * The Workaround is intended to make sure that when this happens nothing fatal
6401 * will occur. The workaround:
6402 * 1. First PF driver which loads on a path will:
6403 * a. After taking the chip out of reset, by using pretend,
6404 * it will write "0" to the following registers of
6405 * the other vnics.
6406 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6407 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6408 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6409 * And for itself it will write '1' to
6410 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6411 * dmae-operations (writing to pram for example.)
6412 * note: can be done for only function 6,7 but cleaner this
6413 * way.
6414 * b. Write zero+valid to the entire ILT.
6415 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6416 * VNIC3 (of that port). The range allocated will be the
6417 * entire ILT. This is needed to prevent ILT range error.
6418 * 2. Any PF driver load flow:
6419 * a. ILT update with the physical addresses of the allocated
6420 * logical pages.
6421 * b. Wait 20msec. - note that this timeout is needed to make
6422 * sure there are no requests in one of the PXP internal
6423 * queues with "old" ILT addresses.
6424 * c. PF enable in the PGLC.
6425 * d. Clear the was_error of the PF in the PGLC. (could have
6426 * occured while driver was down)
6427 * e. PF enable in the CFC (WEAK + STRONG)
6428 * f. Timers scan enable
6429 * 3. PF driver unload flow:
6430 * a. Clear the Timers scan_en.
6431 * b. Polling for scan_on=0 for that PF.
6432 * c. Clear the PF enable bit in the PXP.
6433 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6434 * e. Write zero+valid to all ILT entries (The valid bit must
6435 * stay set)
6436 * f. If this is VNIC 3 of a port then also init
6437 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6438 * to the last enrty in the ILT.
6439 *
6440 * Notes:
6441 * Currently the PF error in the PGLC is non recoverable.
6442 * In the future the there will be a recovery routine for this error.
6443 * Currently attention is masked.
6444 * Having an MCP lock on the load/unload process does not guarantee that
6445 * there is no Timer disable during Func6/7 enable. This is because the
6446 * Timers scan is currently being cleared by the MCP on FLR.
6447 * Step 2.d can be done only for PF6/7 and the driver can also check if
6448 * there is error before clearing it. But the flow above is simpler and
6449 * more general.
6450 * All ILT entries are written by zero+valid and not just PF6/7
6451 * ILT entries since in the future the ILT entries allocation for
6452 * PF-s might be dynamic.
6453 */
6454 struct ilt_client_info ilt_cli;
6455 struct bnx2x_ilt ilt;
6456 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6457 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6458
6459 /* initialize dummy TM client */
6460 ilt_cli.start = 0;
6461 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6462 ilt_cli.client_num = ILT_CLIENT_TM;
6463
6464 /* Step 1: set zeroes to all ilt page entries with valid bit on
6465 * Step 2: set the timers first/last ilt entry to point
6466 * to the entire range to prevent ILT range error for 3rd/4th
6467 * vnic (this code assumes existance of the vnic)
6468 *
6469 * both steps performed by call to bnx2x_ilt_client_init_op()
6470 * with dummy TM client
6471 *
6472 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6473 * and his brother are split registers
6474 */
6475 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6476 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6477 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6478
6479 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6480 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6481 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6482 }
6483
6484
6485 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6486 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6487
6488 if (!CHIP_IS_E1x(bp)) {
6489 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6490 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6491 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6492
6493 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6494
6495 /* let the HW do it's magic ... */
6496 do {
6497 msleep(200);
6498 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6499 } while (factor-- && (val != 1));
6500
6501 if (val != 1) {
6502 BNX2X_ERR("ATC_INIT failed\n");
6503 return -EBUSY;
6504 }
6505 }
6506
6507 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6508
6509 /* clean the DMAE memory */
6510 bp->dmae_ready = 1;
6511 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6512
6513 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6514
6515 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6516
6517 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6518
6519 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6520
6521 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6522 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6523 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6524 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6525
6526 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6527
6528
6529 /* QM queues pointers table */
6530 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6531
6532 /* soft reset pulse */
6533 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6534 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6535
6536 if (CNIC_SUPPORT(bp))
6537 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6538
6539 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6540 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6541 if (!CHIP_REV_IS_SLOW(bp))
6542 /* enable hw interrupt from doorbell Q */
6543 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6544
6545 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6546
6547 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6548 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6549
6550 if (!CHIP_IS_E1(bp))
6551 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6552
6553 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6554 if (IS_MF_AFEX(bp)) {
6555 /* configure that VNTag and VLAN headers must be
6556 * received in afex mode
6557 */
6558 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6559 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6560 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6561 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6562 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6563 } else {
6564 /* Bit-map indicating which L2 hdrs may appear
6565 * after the basic Ethernet header
6566 */
6567 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6568 bp->path_has_ovlan ? 7 : 6);
6569 }
6570 }
6571
6572 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6573 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6574 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6575 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6576
6577 if (!CHIP_IS_E1x(bp)) {
6578 /* reset VFC memories */
6579 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6580 VFC_MEMORIES_RST_REG_CAM_RST |
6581 VFC_MEMORIES_RST_REG_RAM_RST);
6582 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6583 VFC_MEMORIES_RST_REG_CAM_RST |
6584 VFC_MEMORIES_RST_REG_RAM_RST);
6585
6586 msleep(20);
6587 }
6588
6589 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6590 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6591 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6592 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6593
6594 /* sync semi rtc */
6595 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6596 0x80000000);
6597 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6598 0x80000000);
6599
6600 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6601 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6602 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6603
6604 if (!CHIP_IS_E1x(bp)) {
6605 if (IS_MF_AFEX(bp)) {
6606 /* configure that VNTag and VLAN headers must be
6607 * sent in afex mode
6608 */
6609 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6610 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6611 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6612 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6613 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6614 } else {
6615 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6616 bp->path_has_ovlan ? 7 : 6);
6617 }
6618 }
6619
6620 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6621
6622 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6623
6624 if (CNIC_SUPPORT(bp)) {
6625 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6626 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6627 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6628 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6629 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6630 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6631 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6632 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6633 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6634 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6635 }
6636 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6637
6638 if (sizeof(union cdu_context) != 1024)
6639 /* we currently assume that a context is 1024 bytes */
6640 dev_alert(&bp->pdev->dev,
6641 "please adjust the size of cdu_context(%ld)\n",
6642 (long)sizeof(union cdu_context));
6643
6644 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6645 val = (4 << 24) + (0 << 12) + 1024;
6646 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6647
6648 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6649 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6650 /* enable context validation interrupt from CFC */
6651 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6652
6653 /* set the thresholds to prevent CFC/CDU race */
6654 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6655
6656 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6657
6658 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6659 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6660
6661 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6662 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6663
6664 /* Reset PCIE errors for debug */
6665 REG_WR(bp, 0x2814, 0xffffffff);
6666 REG_WR(bp, 0x3820, 0xffffffff);
6667
6668 if (!CHIP_IS_E1x(bp)) {
6669 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6670 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6671 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6672 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6673 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6674 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6675 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6676 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6677 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6678 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6679 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6680 }
6681
6682 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6683 if (!CHIP_IS_E1(bp)) {
6684 /* in E3 this done in per-port section */
6685 if (!CHIP_IS_E3(bp))
6686 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6687 }
6688 if (CHIP_IS_E1H(bp))
6689 /* not applicable for E2 (and above ...) */
6690 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6691
6692 if (CHIP_REV_IS_SLOW(bp))
6693 msleep(200);
6694
6695 /* finish CFC init */
6696 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6697 if (val != 1) {
6698 BNX2X_ERR("CFC LL_INIT failed\n");
6699 return -EBUSY;
6700 }
6701 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6702 if (val != 1) {
6703 BNX2X_ERR("CFC AC_INIT failed\n");
6704 return -EBUSY;
6705 }
6706 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6707 if (val != 1) {
6708 BNX2X_ERR("CFC CAM_INIT failed\n");
6709 return -EBUSY;
6710 }
6711 REG_WR(bp, CFC_REG_DEBUG0, 0);
6712
6713 if (CHIP_IS_E1(bp)) {
6714 /* read NIG statistic
6715 to see if this is our first up since powerup */
6716 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6717 val = *bnx2x_sp(bp, wb_data[0]);
6718
6719 /* do internal memory self test */
6720 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6721 BNX2X_ERR("internal mem self test failed\n");
6722 return -EBUSY;
6723 }
6724 }
6725
6726 bnx2x_setup_fan_failure_detection(bp);
6727
6728 /* clear PXP2 attentions */
6729 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6730
6731 bnx2x_enable_blocks_attention(bp);
6732 bnx2x_enable_blocks_parity(bp);
6733
6734 if (!BP_NOMCP(bp)) {
6735 if (CHIP_IS_E1x(bp))
6736 bnx2x__common_init_phy(bp);
6737 } else
6738 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6739
6740 return 0;
6741 }
6742
6743 /**
6744 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6745 *
6746 * @bp: driver handle
6747 */
6748 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6749 {
6750 int rc = bnx2x_init_hw_common(bp);
6751
6752 if (rc)
6753 return rc;
6754
6755 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6756 if (!BP_NOMCP(bp))
6757 bnx2x__common_init_phy(bp);
6758
6759 return 0;
6760 }
6761
6762 static int bnx2x_init_hw_port(struct bnx2x *bp)
6763 {
6764 int port = BP_PORT(bp);
6765 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6766 u32 low, high;
6767 u32 val;
6768
6769
6770 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
6771
6772 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6773
6774 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6775 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6776 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6777
6778 /* Timers bug workaround: disables the pf_master bit in pglue at
6779 * common phase, we need to enable it here before any dmae access are
6780 * attempted. Therefore we manually added the enable-master to the
6781 * port phase (it also happens in the function phase)
6782 */
6783 if (!CHIP_IS_E1x(bp))
6784 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6785
6786 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6787 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6788 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6789 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6790
6791 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6792 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6793 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6794 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6795
6796 /* QM cid (connection) count */
6797 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6798
6799 if (CNIC_SUPPORT(bp)) {
6800 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6801 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6802 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6803 }
6804
6805 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6806
6807 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6808 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6809
6810 if (IS_MF(bp))
6811 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6812 else if (bp->dev->mtu > 4096) {
6813 if (bp->flags & ONE_PORT_FLAG)
6814 low = 160;
6815 else {
6816 val = bp->dev->mtu;
6817 /* (24*1024 + val*4)/256 */
6818 low = 96 + (val/64) +
6819 ((val % 64) ? 1 : 0);
6820 }
6821 } else
6822 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6823 high = low + 56; /* 14*1024/256 */
6824 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6825 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6826 }
6827
6828 if (CHIP_MODE_IS_4_PORT(bp))
6829 REG_WR(bp, (BP_PORT(bp) ?
6830 BRB1_REG_MAC_GUARANTIED_1 :
6831 BRB1_REG_MAC_GUARANTIED_0), 40);
6832
6833
6834 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6835 if (CHIP_IS_E3B0(bp)) {
6836 if (IS_MF_AFEX(bp)) {
6837 /* configure headers for AFEX mode */
6838 REG_WR(bp, BP_PORT(bp) ?
6839 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6840 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
6841 REG_WR(bp, BP_PORT(bp) ?
6842 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
6843 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
6844 REG_WR(bp, BP_PORT(bp) ?
6845 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
6846 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
6847 } else {
6848 /* Ovlan exists only if we are in multi-function +
6849 * switch-dependent mode, in switch-independent there
6850 * is no ovlan headers
6851 */
6852 REG_WR(bp, BP_PORT(bp) ?
6853 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6854 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6855 (bp->path_has_ovlan ? 7 : 6));
6856 }
6857 }
6858
6859 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6860 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6861 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6862 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6863
6864 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6865 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6866 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6867 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6868
6869 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6870 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6871
6872 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6873
6874 if (CHIP_IS_E1x(bp)) {
6875 /* configure PBF to work without PAUSE mtu 9000 */
6876 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6877
6878 /* update threshold */
6879 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6880 /* update init credit */
6881 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6882
6883 /* probe changes */
6884 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6885 udelay(50);
6886 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6887 }
6888
6889 if (CNIC_SUPPORT(bp))
6890 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6891
6892 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6893 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6894
6895 if (CHIP_IS_E1(bp)) {
6896 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6897 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6898 }
6899 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6900
6901 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6902
6903 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6904 /* init aeu_mask_attn_func_0/1:
6905 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6906 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6907 * bits 4-7 are used for "per vn group attention" */
6908 val = IS_MF(bp) ? 0xF7 : 0x7;
6909 /* Enable DCBX attention for all but E1 */
6910 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6911 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6912
6913 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6914
6915 if (!CHIP_IS_E1x(bp)) {
6916 /* Bit-map indicating which L2 hdrs may appear after the
6917 * basic Ethernet header
6918 */
6919 if (IS_MF_AFEX(bp))
6920 REG_WR(bp, BP_PORT(bp) ?
6921 NIG_REG_P1_HDRS_AFTER_BASIC :
6922 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
6923 else
6924 REG_WR(bp, BP_PORT(bp) ?
6925 NIG_REG_P1_HDRS_AFTER_BASIC :
6926 NIG_REG_P0_HDRS_AFTER_BASIC,
6927 IS_MF_SD(bp) ? 7 : 6);
6928
6929 if (CHIP_IS_E3(bp))
6930 REG_WR(bp, BP_PORT(bp) ?
6931 NIG_REG_LLH1_MF_MODE :
6932 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6933 }
6934 if (!CHIP_IS_E3(bp))
6935 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6936
6937 if (!CHIP_IS_E1(bp)) {
6938 /* 0x2 disable mf_ov, 0x1 enable */
6939 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6940 (IS_MF_SD(bp) ? 0x1 : 0x2));
6941
6942 if (!CHIP_IS_E1x(bp)) {
6943 val = 0;
6944 switch (bp->mf_mode) {
6945 case MULTI_FUNCTION_SD:
6946 val = 1;
6947 break;
6948 case MULTI_FUNCTION_SI:
6949 case MULTI_FUNCTION_AFEX:
6950 val = 2;
6951 break;
6952 }
6953
6954 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6955 NIG_REG_LLH0_CLS_TYPE), val);
6956 }
6957 {
6958 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6959 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6960 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6961 }
6962 }
6963
6964
6965 /* If SPIO5 is set to generate interrupts, enable it for this port */
6966 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6967 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6968 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6969 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6970 val = REG_RD(bp, reg_addr);
6971 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6972 REG_WR(bp, reg_addr, val);
6973 }
6974
6975 return 0;
6976 }
6977
6978 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6979 {
6980 int reg;
6981 u32 wb_write[2];
6982
6983 if (CHIP_IS_E1(bp))
6984 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6985 else
6986 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6987
6988 wb_write[0] = ONCHIP_ADDR1(addr);
6989 wb_write[1] = ONCHIP_ADDR2(addr);
6990 REG_WR_DMAE(bp, reg, wb_write, 2);
6991 }
6992
6993 static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,
6994 u8 idu_sb_id, bool is_Pf)
6995 {
6996 u32 data, ctl, cnt = 100;
6997 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
6998 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
6999 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7000 u32 sb_bit = 1 << (idu_sb_id%32);
7001 u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7002 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7003
7004 /* Not supported in BC mode */
7005 if (CHIP_INT_MODE_IS_BC(bp))
7006 return;
7007
7008 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7009 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7010 IGU_REGULAR_CLEANUP_SET |
7011 IGU_REGULAR_BCLEANUP;
7012
7013 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7014 func_encode << IGU_CTRL_REG_FID_SHIFT |
7015 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7016
7017 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7018 data, igu_addr_data);
7019 REG_WR(bp, igu_addr_data, data);
7020 mmiowb();
7021 barrier();
7022 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7023 ctl, igu_addr_ctl);
7024 REG_WR(bp, igu_addr_ctl, ctl);
7025 mmiowb();
7026 barrier();
7027
7028 /* wait for clean up to finish */
7029 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7030 msleep(20);
7031
7032
7033 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7034 DP(NETIF_MSG_HW,
7035 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7036 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7037 }
7038 }
7039
7040 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7041 {
7042 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7043 }
7044
7045 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7046 {
7047 u32 i, base = FUNC_ILT_BASE(func);
7048 for (i = base; i < base + ILT_PER_FUNC; i++)
7049 bnx2x_ilt_wr(bp, i, 0);
7050 }
7051
7052
7053 void bnx2x_init_searcher(struct bnx2x *bp)
7054 {
7055 int port = BP_PORT(bp);
7056 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7057 /* T1 hash bits value determines the T1 number of entries */
7058 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7059 }
7060
7061 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7062 {
7063 int rc;
7064 struct bnx2x_func_state_params func_params = {NULL};
7065 struct bnx2x_func_switch_update_params *switch_update_params =
7066 &func_params.params.switch_update;
7067
7068 /* Prepare parameters for function state transitions */
7069 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7070 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7071
7072 func_params.f_obj = &bp->func_obj;
7073 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7074
7075 /* Function parameters */
7076 switch_update_params->suspend = suspend;
7077
7078 rc = bnx2x_func_state_change(bp, &func_params);
7079
7080 return rc;
7081 }
7082
7083 int bnx2x_reset_nic_mode(struct bnx2x *bp)
7084 {
7085 int rc, i, port = BP_PORT(bp);
7086 int vlan_en = 0, mac_en[NUM_MACS];
7087
7088
7089 /* Close input from network */
7090 if (bp->mf_mode == SINGLE_FUNCTION) {
7091 bnx2x_set_rx_filter(&bp->link_params, 0);
7092 } else {
7093 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7094 NIG_REG_LLH0_FUNC_EN);
7095 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7096 NIG_REG_LLH0_FUNC_EN, 0);
7097 for (i = 0; i < NUM_MACS; i++) {
7098 mac_en[i] = REG_RD(bp, port ?
7099 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7100 4 * i) :
7101 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7102 4 * i));
7103 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7104 4 * i) :
7105 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7106 }
7107 }
7108
7109 /* Close BMC to host */
7110 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7111 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7112
7113 /* Suspend Tx switching to the PF. Completion of this ramrod
7114 * further guarantees that all the packets of that PF / child
7115 * VFs in BRB were processed by the Parser, so it is safe to
7116 * change the NIC_MODE register.
7117 */
7118 rc = bnx2x_func_switch_update(bp, 1);
7119 if (rc) {
7120 BNX2X_ERR("Can't suspend tx-switching!\n");
7121 return rc;
7122 }
7123
7124 /* Change NIC_MODE register */
7125 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7126
7127 /* Open input from network */
7128 if (bp->mf_mode == SINGLE_FUNCTION) {
7129 bnx2x_set_rx_filter(&bp->link_params, 1);
7130 } else {
7131 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7132 NIG_REG_LLH0_FUNC_EN, vlan_en);
7133 for (i = 0; i < NUM_MACS; i++) {
7134 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7135 4 * i) :
7136 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7137 mac_en[i]);
7138 }
7139 }
7140
7141 /* Enable BMC to host */
7142 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7143 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7144
7145 /* Resume Tx switching to the PF */
7146 rc = bnx2x_func_switch_update(bp, 0);
7147 if (rc) {
7148 BNX2X_ERR("Can't resume tx-switching!\n");
7149 return rc;
7150 }
7151
7152 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7153 return 0;
7154 }
7155
7156 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7157 {
7158 int rc;
7159
7160 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7161
7162 if (CONFIGURE_NIC_MODE(bp)) {
7163 /* Configrue searcher as part of function hw init */
7164 bnx2x_init_searcher(bp);
7165
7166 /* Reset NIC mode */
7167 rc = bnx2x_reset_nic_mode(bp);
7168 if (rc)
7169 BNX2X_ERR("Can't change NIC mode!\n");
7170 return rc;
7171 }
7172
7173 return 0;
7174 }
7175
7176 static int bnx2x_init_hw_func(struct bnx2x *bp)
7177 {
7178 int port = BP_PORT(bp);
7179 int func = BP_FUNC(bp);
7180 int init_phase = PHASE_PF0 + func;
7181 struct bnx2x_ilt *ilt = BP_ILT(bp);
7182 u16 cdu_ilt_start;
7183 u32 addr, val;
7184 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7185 int i, main_mem_width, rc;
7186
7187 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7188
7189 /* FLR cleanup - hmmm */
7190 if (!CHIP_IS_E1x(bp)) {
7191 rc = bnx2x_pf_flr_clnup(bp);
7192 if (rc)
7193 return rc;
7194 }
7195
7196 /* set MSI reconfigure capability */
7197 if (bp->common.int_block == INT_BLOCK_HC) {
7198 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7199 val = REG_RD(bp, addr);
7200 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7201 REG_WR(bp, addr, val);
7202 }
7203
7204 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7205 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7206
7207 ilt = BP_ILT(bp);
7208 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7209
7210 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7211 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7212 ilt->lines[cdu_ilt_start + i].page_mapping =
7213 bp->context[i].cxt_mapping;
7214 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7215 }
7216 bnx2x_ilt_init_op(bp, INITOP_SET);
7217
7218 if (!CONFIGURE_NIC_MODE(bp)) {
7219 bnx2x_init_searcher(bp);
7220 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7221 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7222 } else {
7223 /* Set NIC mode */
7224 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7225 DP(NETIF_MSG_IFUP, "NIC MODE configrued\n");
7226
7227 }
7228
7229 if (!CHIP_IS_E1x(bp)) {
7230 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7231
7232 /* Turn on a single ISR mode in IGU if driver is going to use
7233 * INT#x or MSI
7234 */
7235 if (!(bp->flags & USING_MSIX_FLAG))
7236 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7237 /*
7238 * Timers workaround bug: function init part.
7239 * Need to wait 20msec after initializing ILT,
7240 * needed to make sure there are no requests in
7241 * one of the PXP internal queues with "old" ILT addresses
7242 */
7243 msleep(20);
7244 /*
7245 * Master enable - Due to WB DMAE writes performed before this
7246 * register is re-initialized as part of the regular function
7247 * init
7248 */
7249 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7250 /* Enable the function in IGU */
7251 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7252 }
7253
7254 bp->dmae_ready = 1;
7255
7256 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7257
7258 if (!CHIP_IS_E1x(bp))
7259 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7260
7261 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7262 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7263 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7264 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7265 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7266 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7267 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7268 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7269 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7270 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7271 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7272 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7273 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7274
7275 if (!CHIP_IS_E1x(bp))
7276 REG_WR(bp, QM_REG_PF_EN, 1);
7277
7278 if (!CHIP_IS_E1x(bp)) {
7279 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7280 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7281 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7282 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7283 }
7284 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7285
7286 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7287 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7288 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7289 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7290 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7291 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7292 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7293 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7294 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7295 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7296 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7297 if (!CHIP_IS_E1x(bp))
7298 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7299
7300 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7301
7302 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7303
7304 if (!CHIP_IS_E1x(bp))
7305 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7306
7307 if (IS_MF(bp)) {
7308 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7309 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7310 }
7311
7312 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7313
7314 /* HC init per function */
7315 if (bp->common.int_block == INT_BLOCK_HC) {
7316 if (CHIP_IS_E1H(bp)) {
7317 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7318
7319 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7320 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7321 }
7322 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7323
7324 } else {
7325 int num_segs, sb_idx, prod_offset;
7326
7327 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7328
7329 if (!CHIP_IS_E1x(bp)) {
7330 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7331 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7332 }
7333
7334 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7335
7336 if (!CHIP_IS_E1x(bp)) {
7337 int dsb_idx = 0;
7338 /**
7339 * Producer memory:
7340 * E2 mode: address 0-135 match to the mapping memory;
7341 * 136 - PF0 default prod; 137 - PF1 default prod;
7342 * 138 - PF2 default prod; 139 - PF3 default prod;
7343 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7344 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7345 * 144-147 reserved.
7346 *
7347 * E1.5 mode - In backward compatible mode;
7348 * for non default SB; each even line in the memory
7349 * holds the U producer and each odd line hold
7350 * the C producer. The first 128 producers are for
7351 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7352 * producers are for the DSB for each PF.
7353 * Each PF has five segments: (the order inside each
7354 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7355 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7356 * 144-147 attn prods;
7357 */
7358 /* non-default-status-blocks */
7359 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7360 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7361 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7362 prod_offset = (bp->igu_base_sb + sb_idx) *
7363 num_segs;
7364
7365 for (i = 0; i < num_segs; i++) {
7366 addr = IGU_REG_PROD_CONS_MEMORY +
7367 (prod_offset + i) * 4;
7368 REG_WR(bp, addr, 0);
7369 }
7370 /* send consumer update with value 0 */
7371 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7372 USTORM_ID, 0, IGU_INT_NOP, 1);
7373 bnx2x_igu_clear_sb(bp,
7374 bp->igu_base_sb + sb_idx);
7375 }
7376
7377 /* default-status-blocks */
7378 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7379 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7380
7381 if (CHIP_MODE_IS_4_PORT(bp))
7382 dsb_idx = BP_FUNC(bp);
7383 else
7384 dsb_idx = BP_VN(bp);
7385
7386 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7387 IGU_BC_BASE_DSB_PROD + dsb_idx :
7388 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7389
7390 /*
7391 * igu prods come in chunks of E1HVN_MAX (4) -
7392 * does not matters what is the current chip mode
7393 */
7394 for (i = 0; i < (num_segs * E1HVN_MAX);
7395 i += E1HVN_MAX) {
7396 addr = IGU_REG_PROD_CONS_MEMORY +
7397 (prod_offset + i)*4;
7398 REG_WR(bp, addr, 0);
7399 }
7400 /* send consumer update with 0 */
7401 if (CHIP_INT_MODE_IS_BC(bp)) {
7402 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7403 USTORM_ID, 0, IGU_INT_NOP, 1);
7404 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7405 CSTORM_ID, 0, IGU_INT_NOP, 1);
7406 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7407 XSTORM_ID, 0, IGU_INT_NOP, 1);
7408 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7409 TSTORM_ID, 0, IGU_INT_NOP, 1);
7410 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7411 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7412 } else {
7413 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7414 USTORM_ID, 0, IGU_INT_NOP, 1);
7415 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7416 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7417 }
7418 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7419
7420 /* !!! these should become driver const once
7421 rf-tool supports split-68 const */
7422 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7423 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7424 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7425 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7426 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7427 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7428 }
7429 }
7430
7431 /* Reset PCIE errors for debug */
7432 REG_WR(bp, 0x2114, 0xffffffff);
7433 REG_WR(bp, 0x2120, 0xffffffff);
7434
7435 if (CHIP_IS_E1x(bp)) {
7436 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7437 main_mem_base = HC_REG_MAIN_MEMORY +
7438 BP_PORT(bp) * (main_mem_size * 4);
7439 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7440 main_mem_width = 8;
7441
7442 val = REG_RD(bp, main_mem_prty_clr);
7443 if (val)
7444 DP(NETIF_MSG_HW,
7445 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7446 val);
7447
7448 /* Clear "false" parity errors in MSI-X table */
7449 for (i = main_mem_base;
7450 i < main_mem_base + main_mem_size * 4;
7451 i += main_mem_width) {
7452 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7453 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7454 i, main_mem_width / 4);
7455 }
7456 /* Clear HC parity attention */
7457 REG_RD(bp, main_mem_prty_clr);
7458 }
7459
7460 #ifdef BNX2X_STOP_ON_ERROR
7461 /* Enable STORMs SP logging */
7462 REG_WR8(bp, BAR_USTRORM_INTMEM +
7463 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7464 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7465 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7466 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7467 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7468 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7469 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7470 #endif
7471
7472 bnx2x_phy_probe(&bp->link_params);
7473
7474 return 0;
7475 }
7476
7477
7478 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7479 {
7480 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7481
7482 if (!CHIP_IS_E1x(bp))
7483 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7484 sizeof(struct host_hc_status_block_e2));
7485 else
7486 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7487 sizeof(struct host_hc_status_block_e1x));
7488
7489 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7490 }
7491
7492 void bnx2x_free_mem(struct bnx2x *bp)
7493 {
7494 int i;
7495
7496 /* fastpath */
7497 bnx2x_free_fp_mem(bp);
7498 /* end of fastpath */
7499
7500 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7501 sizeof(struct host_sp_status_block));
7502
7503 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7504 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7505
7506 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7507 sizeof(struct bnx2x_slowpath));
7508
7509 for (i = 0; i < L2_ILT_LINES(bp); i++)
7510 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7511 bp->context[i].size);
7512 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7513
7514 BNX2X_FREE(bp->ilt->lines);
7515
7516 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7517
7518 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7519 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7520 }
7521
7522 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
7523 {
7524 int num_groups;
7525 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
7526
7527 /* number of queues for statistics is number of eth queues + FCoE */
7528 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
7529
7530 /* Total number of FW statistics requests =
7531 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7532 * num of queues
7533 */
7534 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
7535
7536
7537 /* Request is built from stats_query_header and an array of
7538 * stats_query_cmd_group each of which contains
7539 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7540 * configured in the stats_query_header.
7541 */
7542 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
7543 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
7544
7545 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
7546 num_groups * sizeof(struct stats_query_cmd_group);
7547
7548 /* Data for statistics requests + stats_conter
7549 *
7550 * stats_counter holds per-STORM counters that are incremented
7551 * when STORM has finished with the current request.
7552 *
7553 * memory for FCoE offloaded statistics are counted anyway,
7554 * even if they will not be sent.
7555 */
7556 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
7557 sizeof(struct per_pf_stats) +
7558 sizeof(struct fcoe_statistics_params) +
7559 sizeof(struct per_queue_stats) * num_queue_stats +
7560 sizeof(struct stats_counter);
7561
7562 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
7563 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7564
7565 /* Set shortcuts */
7566 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
7567 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
7568
7569 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
7570 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
7571
7572 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
7573 bp->fw_stats_req_sz;
7574 return 0;
7575
7576 alloc_mem_err:
7577 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7578 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7579 BNX2X_ERR("Can't allocate memory\n");
7580 return -ENOMEM;
7581 }
7582
7583 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7584 {
7585 if (!CHIP_IS_E1x(bp))
7586 /* size = the status block + ramrod buffers */
7587 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7588 sizeof(struct host_hc_status_block_e2));
7589 else
7590 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7591 &bp->cnic_sb_mapping,
7592 sizeof(struct
7593 host_hc_status_block_e1x));
7594
7595 if (CONFIGURE_NIC_MODE(bp))
7596 /* allocate searcher T2 table, as it wan't allocated before */
7597 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7598
7599 /* write address to which L5 should insert its values */
7600 bp->cnic_eth_dev.addr_drv_info_to_mcp =
7601 &bp->slowpath->drv_info_to_mcp;
7602
7603 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7604 goto alloc_mem_err;
7605
7606 return 0;
7607
7608 alloc_mem_err:
7609 bnx2x_free_mem_cnic(bp);
7610 BNX2X_ERR("Can't allocate memory\n");
7611 return -ENOMEM;
7612 }
7613
7614 int bnx2x_alloc_mem(struct bnx2x *bp)
7615 {
7616 int i, allocated, context_size;
7617
7618 if (!CONFIGURE_NIC_MODE(bp))
7619 /* allocate searcher T2 table */
7620 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7621
7622 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7623 sizeof(struct host_sp_status_block));
7624
7625 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7626 sizeof(struct bnx2x_slowpath));
7627
7628 /* Allocated memory for FW statistics */
7629 if (bnx2x_alloc_fw_stats_mem(bp))
7630 goto alloc_mem_err;
7631
7632 /* Allocate memory for CDU context:
7633 * This memory is allocated separately and not in the generic ILT
7634 * functions because CDU differs in few aspects:
7635 * 1. There are multiple entities allocating memory for context -
7636 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7637 * its own ILT lines.
7638 * 2. Since CDU page-size is not a single 4KB page (which is the case
7639 * for the other ILT clients), to be efficient we want to support
7640 * allocation of sub-page-size in the last entry.
7641 * 3. Context pointers are used by the driver to pass to FW / update
7642 * the context (for the other ILT clients the pointers are used just to
7643 * free the memory during unload).
7644 */
7645 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7646
7647 for (i = 0, allocated = 0; allocated < context_size; i++) {
7648 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7649 (context_size - allocated));
7650 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7651 &bp->context[i].cxt_mapping,
7652 bp->context[i].size);
7653 allocated += bp->context[i].size;
7654 }
7655 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7656
7657 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7658 goto alloc_mem_err;
7659
7660 /* Slow path ring */
7661 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7662
7663 /* EQ */
7664 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7665 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7666
7667
7668 /* fastpath */
7669 /* need to be done at the end, since it's self adjusting to amount
7670 * of memory available for RSS queues
7671 */
7672 if (bnx2x_alloc_fp_mem(bp))
7673 goto alloc_mem_err;
7674 return 0;
7675
7676 alloc_mem_err:
7677 bnx2x_free_mem(bp);
7678 BNX2X_ERR("Can't allocate memory\n");
7679 return -ENOMEM;
7680 }
7681
7682 /*
7683 * Init service functions
7684 */
7685
7686 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7687 struct bnx2x_vlan_mac_obj *obj, bool set,
7688 int mac_type, unsigned long *ramrod_flags)
7689 {
7690 int rc;
7691 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7692
7693 memset(&ramrod_param, 0, sizeof(ramrod_param));
7694
7695 /* Fill general parameters */
7696 ramrod_param.vlan_mac_obj = obj;
7697 ramrod_param.ramrod_flags = *ramrod_flags;
7698
7699 /* Fill a user request section if needed */
7700 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7701 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7702
7703 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7704
7705 /* Set the command: ADD or DEL */
7706 if (set)
7707 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7708 else
7709 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7710 }
7711
7712 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7713
7714 if (rc == -EEXIST) {
7715 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7716 /* do not treat adding same MAC as error */
7717 rc = 0;
7718 } else if (rc < 0)
7719 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7720
7721 return rc;
7722 }
7723
7724 int bnx2x_del_all_macs(struct bnx2x *bp,
7725 struct bnx2x_vlan_mac_obj *mac_obj,
7726 int mac_type, bool wait_for_comp)
7727 {
7728 int rc;
7729 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7730
7731 /* Wait for completion of requested */
7732 if (wait_for_comp)
7733 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7734
7735 /* Set the mac type of addresses we want to clear */
7736 __set_bit(mac_type, &vlan_mac_flags);
7737
7738 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7739 if (rc < 0)
7740 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7741
7742 return rc;
7743 }
7744
7745 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7746 {
7747 unsigned long ramrod_flags = 0;
7748
7749 if (is_zero_ether_addr(bp->dev->dev_addr) &&
7750 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7751 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7752 "Ignoring Zero MAC for STORAGE SD mode\n");
7753 return 0;
7754 }
7755
7756 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7757
7758 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7759 /* Eth MAC is set on RSS leading client (fp[0]) */
7760 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7761 set, BNX2X_ETH_MAC, &ramrod_flags);
7762 }
7763
7764 int bnx2x_setup_leading(struct bnx2x *bp)
7765 {
7766 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7767 }
7768
7769 /**
7770 * bnx2x_set_int_mode - configure interrupt mode
7771 *
7772 * @bp: driver handle
7773 *
7774 * In case of MSI-X it will also try to enable MSI-X.
7775 */
7776 void bnx2x_set_int_mode(struct bnx2x *bp)
7777 {
7778 switch (int_mode) {
7779 case INT_MODE_MSI:
7780 bnx2x_enable_msi(bp);
7781 /* falling through... */
7782 case INT_MODE_INTx:
7783 bp->num_ethernet_queues = 1;
7784 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
7785 BNX2X_DEV_INFO("set number of queues to 1\n");
7786 break;
7787 default:
7788 /* if we can't use MSI-X we only need one fp,
7789 * so try to enable MSI-X with the requested number of fp's
7790 * and fallback to MSI or legacy INTx with one fp
7791 */
7792 if (bnx2x_enable_msix(bp) ||
7793 bp->flags & USING_SINGLE_MSIX_FLAG) {
7794 /* failed to enable multiple MSI-X */
7795 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7796 bp->num_queues,
7797 1 + bp->num_cnic_queues);
7798
7799 bp->num_queues = 1 + bp->num_cnic_queues;
7800
7801 /* Try to enable MSI */
7802 if (!(bp->flags & USING_SINGLE_MSIX_FLAG) &&
7803 !(bp->flags & DISABLE_MSI_FLAG))
7804 bnx2x_enable_msi(bp);
7805 }
7806 break;
7807 }
7808 }
7809
7810 /* must be called prioir to any HW initializations */
7811 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7812 {
7813 return L2_ILT_LINES(bp);
7814 }
7815
7816 void bnx2x_ilt_set_info(struct bnx2x *bp)
7817 {
7818 struct ilt_client_info *ilt_client;
7819 struct bnx2x_ilt *ilt = BP_ILT(bp);
7820 u16 line = 0;
7821
7822 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7823 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7824
7825 /* CDU */
7826 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7827 ilt_client->client_num = ILT_CLIENT_CDU;
7828 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7829 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7830 ilt_client->start = line;
7831 line += bnx2x_cid_ilt_lines(bp);
7832
7833 if (CNIC_SUPPORT(bp))
7834 line += CNIC_ILT_LINES;
7835 ilt_client->end = line - 1;
7836
7837 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7838 ilt_client->start,
7839 ilt_client->end,
7840 ilt_client->page_size,
7841 ilt_client->flags,
7842 ilog2(ilt_client->page_size >> 12));
7843
7844 /* QM */
7845 if (QM_INIT(bp->qm_cid_count)) {
7846 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7847 ilt_client->client_num = ILT_CLIENT_QM;
7848 ilt_client->page_size = QM_ILT_PAGE_SZ;
7849 ilt_client->flags = 0;
7850 ilt_client->start = line;
7851
7852 /* 4 bytes for each cid */
7853 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7854 QM_ILT_PAGE_SZ);
7855
7856 ilt_client->end = line - 1;
7857
7858 DP(NETIF_MSG_IFUP,
7859 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7860 ilt_client->start,
7861 ilt_client->end,
7862 ilt_client->page_size,
7863 ilt_client->flags,
7864 ilog2(ilt_client->page_size >> 12));
7865
7866 }
7867
7868 if (CNIC_SUPPORT(bp)) {
7869 /* SRC */
7870 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7871 ilt_client->client_num = ILT_CLIENT_SRC;
7872 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7873 ilt_client->flags = 0;
7874 ilt_client->start = line;
7875 line += SRC_ILT_LINES;
7876 ilt_client->end = line - 1;
7877
7878 DP(NETIF_MSG_IFUP,
7879 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7880 ilt_client->start,
7881 ilt_client->end,
7882 ilt_client->page_size,
7883 ilt_client->flags,
7884 ilog2(ilt_client->page_size >> 12));
7885
7886 /* TM */
7887 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7888 ilt_client->client_num = ILT_CLIENT_TM;
7889 ilt_client->page_size = TM_ILT_PAGE_SZ;
7890 ilt_client->flags = 0;
7891 ilt_client->start = line;
7892 line += TM_ILT_LINES;
7893 ilt_client->end = line - 1;
7894
7895 DP(NETIF_MSG_IFUP,
7896 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7897 ilt_client->start,
7898 ilt_client->end,
7899 ilt_client->page_size,
7900 ilt_client->flags,
7901 ilog2(ilt_client->page_size >> 12));
7902 }
7903
7904 BUG_ON(line > ILT_MAX_LINES);
7905 }
7906
7907 /**
7908 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7909 *
7910 * @bp: driver handle
7911 * @fp: pointer to fastpath
7912 * @init_params: pointer to parameters structure
7913 *
7914 * parameters configured:
7915 * - HC configuration
7916 * - Queue's CDU context
7917 */
7918 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7919 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7920 {
7921
7922 u8 cos;
7923 int cxt_index, cxt_offset;
7924
7925 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7926 if (!IS_FCOE_FP(fp)) {
7927 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7928 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7929
7930 /* If HC is supporterd, enable host coalescing in the transition
7931 * to INIT state.
7932 */
7933 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7934 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7935
7936 /* HC rate */
7937 init_params->rx.hc_rate = bp->rx_ticks ?
7938 (1000000 / bp->rx_ticks) : 0;
7939 init_params->tx.hc_rate = bp->tx_ticks ?
7940 (1000000 / bp->tx_ticks) : 0;
7941
7942 /* FW SB ID */
7943 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7944 fp->fw_sb_id;
7945
7946 /*
7947 * CQ index among the SB indices: FCoE clients uses the default
7948 * SB, therefore it's different.
7949 */
7950 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7951 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7952 }
7953
7954 /* set maximum number of COSs supported by this queue */
7955 init_params->max_cos = fp->max_cos;
7956
7957 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
7958 fp->index, init_params->max_cos);
7959
7960 /* set the context pointers queue object */
7961 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
7962 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
7963 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
7964 ILT_PAGE_CIDS);
7965 init_params->cxts[cos] =
7966 &bp->context[cxt_index].vcxt[cxt_offset].eth;
7967 }
7968 }
7969
7970 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7971 struct bnx2x_queue_state_params *q_params,
7972 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7973 int tx_index, bool leading)
7974 {
7975 memset(tx_only_params, 0, sizeof(*tx_only_params));
7976
7977 /* Set the command */
7978 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7979
7980 /* Set tx-only QUEUE flags: don't zero statistics */
7981 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7982
7983 /* choose the index of the cid to send the slow path on */
7984 tx_only_params->cid_index = tx_index;
7985
7986 /* Set general TX_ONLY_SETUP parameters */
7987 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7988
7989 /* Set Tx TX_ONLY_SETUP parameters */
7990 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7991
7992 DP(NETIF_MSG_IFUP,
7993 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
7994 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7995 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7996 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7997
7998 /* send the ramrod */
7999 return bnx2x_queue_state_change(bp, q_params);
8000 }
8001
8002
8003 /**
8004 * bnx2x_setup_queue - setup queue
8005 *
8006 * @bp: driver handle
8007 * @fp: pointer to fastpath
8008 * @leading: is leading
8009 *
8010 * This function performs 2 steps in a Queue state machine
8011 * actually: 1) RESET->INIT 2) INIT->SETUP
8012 */
8013
8014 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8015 bool leading)
8016 {
8017 struct bnx2x_queue_state_params q_params = {NULL};
8018 struct bnx2x_queue_setup_params *setup_params =
8019 &q_params.params.setup;
8020 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8021 &q_params.params.tx_only;
8022 int rc;
8023 u8 tx_index;
8024
8025 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8026
8027 /* reset IGU state skip FCoE L2 queue */
8028 if (!IS_FCOE_FP(fp))
8029 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8030 IGU_INT_ENABLE, 0);
8031
8032 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8033 /* We want to wait for completion in this context */
8034 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8035
8036 /* Prepare the INIT parameters */
8037 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8038
8039 /* Set the command */
8040 q_params.cmd = BNX2X_Q_CMD_INIT;
8041
8042 /* Change the state to INIT */
8043 rc = bnx2x_queue_state_change(bp, &q_params);
8044 if (rc) {
8045 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8046 return rc;
8047 }
8048
8049 DP(NETIF_MSG_IFUP, "init complete\n");
8050
8051
8052 /* Now move the Queue to the SETUP state... */
8053 memset(setup_params, 0, sizeof(*setup_params));
8054
8055 /* Set QUEUE flags */
8056 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8057
8058 /* Set general SETUP parameters */
8059 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8060 FIRST_TX_COS_INDEX);
8061
8062 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8063 &setup_params->rxq_params);
8064
8065 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8066 FIRST_TX_COS_INDEX);
8067
8068 /* Set the command */
8069 q_params.cmd = BNX2X_Q_CMD_SETUP;
8070
8071 if (IS_FCOE_FP(fp))
8072 bp->fcoe_init = true;
8073
8074 /* Change the state to SETUP */
8075 rc = bnx2x_queue_state_change(bp, &q_params);
8076 if (rc) {
8077 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8078 return rc;
8079 }
8080
8081 /* loop through the relevant tx-only indices */
8082 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8083 tx_index < fp->max_cos;
8084 tx_index++) {
8085
8086 /* prepare and send tx-only ramrod*/
8087 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8088 tx_only_params, tx_index, leading);
8089 if (rc) {
8090 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8091 fp->index, tx_index);
8092 return rc;
8093 }
8094 }
8095
8096 return rc;
8097 }
8098
8099 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8100 {
8101 struct bnx2x_fastpath *fp = &bp->fp[index];
8102 struct bnx2x_fp_txdata *txdata;
8103 struct bnx2x_queue_state_params q_params = {NULL};
8104 int rc, tx_index;
8105
8106 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8107
8108 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8109 /* We want to wait for completion in this context */
8110 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8111
8112
8113 /* close tx-only connections */
8114 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8115 tx_index < fp->max_cos;
8116 tx_index++){
8117
8118 /* ascertain this is a normal queue*/
8119 txdata = fp->txdata_ptr[tx_index];
8120
8121 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8122 txdata->txq_index);
8123
8124 /* send halt terminate on tx-only connection */
8125 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8126 memset(&q_params.params.terminate, 0,
8127 sizeof(q_params.params.terminate));
8128 q_params.params.terminate.cid_index = tx_index;
8129
8130 rc = bnx2x_queue_state_change(bp, &q_params);
8131 if (rc)
8132 return rc;
8133
8134 /* send halt terminate on tx-only connection */
8135 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8136 memset(&q_params.params.cfc_del, 0,
8137 sizeof(q_params.params.cfc_del));
8138 q_params.params.cfc_del.cid_index = tx_index;
8139 rc = bnx2x_queue_state_change(bp, &q_params);
8140 if (rc)
8141 return rc;
8142 }
8143 /* Stop the primary connection: */
8144 /* ...halt the connection */
8145 q_params.cmd = BNX2X_Q_CMD_HALT;
8146 rc = bnx2x_queue_state_change(bp, &q_params);
8147 if (rc)
8148 return rc;
8149
8150 /* ...terminate the connection */
8151 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8152 memset(&q_params.params.terminate, 0,
8153 sizeof(q_params.params.terminate));
8154 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8155 rc = bnx2x_queue_state_change(bp, &q_params);
8156 if (rc)
8157 return rc;
8158 /* ...delete cfc entry */
8159 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8160 memset(&q_params.params.cfc_del, 0,
8161 sizeof(q_params.params.cfc_del));
8162 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8163 return bnx2x_queue_state_change(bp, &q_params);
8164 }
8165
8166
8167 static void bnx2x_reset_func(struct bnx2x *bp)
8168 {
8169 int port = BP_PORT(bp);
8170 int func = BP_FUNC(bp);
8171 int i;
8172
8173 /* Disable the function in the FW */
8174 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8175 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8176 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8177 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8178
8179 /* FP SBs */
8180 for_each_eth_queue(bp, i) {
8181 struct bnx2x_fastpath *fp = &bp->fp[i];
8182 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8183 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8184 SB_DISABLED);
8185 }
8186
8187 if (CNIC_LOADED(bp))
8188 /* CNIC SB */
8189 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8190 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8191 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8192
8193 /* SP SB */
8194 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8195 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8196 SB_DISABLED);
8197
8198 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8199 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8200 0);
8201
8202 /* Configure IGU */
8203 if (bp->common.int_block == INT_BLOCK_HC) {
8204 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8205 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8206 } else {
8207 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8208 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8209 }
8210
8211 if (CNIC_LOADED(bp)) {
8212 /* Disable Timer scan */
8213 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8214 /*
8215 * Wait for at least 10ms and up to 2 second for the timers
8216 * scan to complete
8217 */
8218 for (i = 0; i < 200; i++) {
8219 msleep(10);
8220 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8221 break;
8222 }
8223 }
8224 /* Clear ILT */
8225 bnx2x_clear_func_ilt(bp, func);
8226
8227 /* Timers workaround bug for E2: if this is vnic-3,
8228 * we need to set the entire ilt range for this timers.
8229 */
8230 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8231 struct ilt_client_info ilt_cli;
8232 /* use dummy TM client */
8233 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8234 ilt_cli.start = 0;
8235 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8236 ilt_cli.client_num = ILT_CLIENT_TM;
8237
8238 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8239 }
8240
8241 /* this assumes that reset_port() called before reset_func()*/
8242 if (!CHIP_IS_E1x(bp))
8243 bnx2x_pf_disable(bp);
8244
8245 bp->dmae_ready = 0;
8246 }
8247
8248 static void bnx2x_reset_port(struct bnx2x *bp)
8249 {
8250 int port = BP_PORT(bp);
8251 u32 val;
8252
8253 /* Reset physical Link */
8254 bnx2x__link_reset(bp);
8255
8256 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8257
8258 /* Do not rcv packets to BRB */
8259 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8260 /* Do not direct rcv packets that are not for MCP to the BRB */
8261 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8262 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8263
8264 /* Configure AEU */
8265 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8266
8267 msleep(100);
8268 /* Check for BRB port occupancy */
8269 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8270 if (val)
8271 DP(NETIF_MSG_IFDOWN,
8272 "BRB1 is not empty %d blocks are occupied\n", val);
8273
8274 /* TODO: Close Doorbell port? */
8275 }
8276
8277 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8278 {
8279 struct bnx2x_func_state_params func_params = {NULL};
8280
8281 /* Prepare parameters for function state transitions */
8282 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8283
8284 func_params.f_obj = &bp->func_obj;
8285 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8286
8287 func_params.params.hw_init.load_phase = load_code;
8288
8289 return bnx2x_func_state_change(bp, &func_params);
8290 }
8291
8292 static int bnx2x_func_stop(struct bnx2x *bp)
8293 {
8294 struct bnx2x_func_state_params func_params = {NULL};
8295 int rc;
8296
8297 /* Prepare parameters for function state transitions */
8298 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8299 func_params.f_obj = &bp->func_obj;
8300 func_params.cmd = BNX2X_F_CMD_STOP;
8301
8302 /*
8303 * Try to stop the function the 'good way'. If fails (in case
8304 * of a parity error during bnx2x_chip_cleanup()) and we are
8305 * not in a debug mode, perform a state transaction in order to
8306 * enable further HW_RESET transaction.
8307 */
8308 rc = bnx2x_func_state_change(bp, &func_params);
8309 if (rc) {
8310 #ifdef BNX2X_STOP_ON_ERROR
8311 return rc;
8312 #else
8313 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8314 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8315 return bnx2x_func_state_change(bp, &func_params);
8316 #endif
8317 }
8318
8319 return 0;
8320 }
8321
8322 /**
8323 * bnx2x_send_unload_req - request unload mode from the MCP.
8324 *
8325 * @bp: driver handle
8326 * @unload_mode: requested function's unload mode
8327 *
8328 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8329 */
8330 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8331 {
8332 u32 reset_code = 0;
8333 int port = BP_PORT(bp);
8334
8335 /* Select the UNLOAD request mode */
8336 if (unload_mode == UNLOAD_NORMAL)
8337 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8338
8339 else if (bp->flags & NO_WOL_FLAG)
8340 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8341
8342 else if (bp->wol) {
8343 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8344 u8 *mac_addr = bp->dev->dev_addr;
8345 u32 val;
8346 u16 pmc;
8347
8348 /* The mac address is written to entries 1-4 to
8349 * preserve entry 0 which is used by the PMF
8350 */
8351 u8 entry = (BP_VN(bp) + 1)*8;
8352
8353 val = (mac_addr[0] << 8) | mac_addr[1];
8354 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8355
8356 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8357 (mac_addr[4] << 8) | mac_addr[5];
8358 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8359
8360 /* Enable the PME and clear the status */
8361 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8362 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8363 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8364
8365 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8366
8367 } else
8368 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8369
8370 /* Send the request to the MCP */
8371 if (!BP_NOMCP(bp))
8372 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8373 else {
8374 int path = BP_PATH(bp);
8375
8376 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
8377 path, load_count[path][0], load_count[path][1],
8378 load_count[path][2]);
8379 load_count[path][0]--;
8380 load_count[path][1 + port]--;
8381 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
8382 path, load_count[path][0], load_count[path][1],
8383 load_count[path][2]);
8384 if (load_count[path][0] == 0)
8385 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8386 else if (load_count[path][1 + port] == 0)
8387 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8388 else
8389 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8390 }
8391
8392 return reset_code;
8393 }
8394
8395 /**
8396 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8397 *
8398 * @bp: driver handle
8399 * @keep_link: true iff link should be kept up
8400 */
8401 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8402 {
8403 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8404
8405 /* Report UNLOAD_DONE to MCP */
8406 if (!BP_NOMCP(bp))
8407 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8408 }
8409
8410 static int bnx2x_func_wait_started(struct bnx2x *bp)
8411 {
8412 int tout = 50;
8413 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8414
8415 if (!bp->port.pmf)
8416 return 0;
8417
8418 /*
8419 * (assumption: No Attention from MCP at this stage)
8420 * PMF probably in the middle of TXdisable/enable transaction
8421 * 1. Sync IRS for default SB
8422 * 2. Sync SP queue - this guarantes us that attention handling started
8423 * 3. Wait, that TXdisable/enable transaction completes
8424 *
8425 * 1+2 guranty that if DCBx attention was scheduled it already changed
8426 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8427 * received complettion for the transaction the state is TX_STOPPED.
8428 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8429 * transaction.
8430 */
8431
8432 /* make sure default SB ISR is done */
8433 if (msix)
8434 synchronize_irq(bp->msix_table[0].vector);
8435 else
8436 synchronize_irq(bp->pdev->irq);
8437
8438 flush_workqueue(bnx2x_wq);
8439
8440 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8441 BNX2X_F_STATE_STARTED && tout--)
8442 msleep(20);
8443
8444 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8445 BNX2X_F_STATE_STARTED) {
8446 #ifdef BNX2X_STOP_ON_ERROR
8447 BNX2X_ERR("Wrong function state\n");
8448 return -EBUSY;
8449 #else
8450 /*
8451 * Failed to complete the transaction in a "good way"
8452 * Force both transactions with CLR bit
8453 */
8454 struct bnx2x_func_state_params func_params = {NULL};
8455
8456 DP(NETIF_MSG_IFDOWN,
8457 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8458
8459 func_params.f_obj = &bp->func_obj;
8460 __set_bit(RAMROD_DRV_CLR_ONLY,
8461 &func_params.ramrod_flags);
8462
8463 /* STARTED-->TX_ST0PPED */
8464 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8465 bnx2x_func_state_change(bp, &func_params);
8466
8467 /* TX_ST0PPED-->STARTED */
8468 func_params.cmd = BNX2X_F_CMD_TX_START;
8469 return bnx2x_func_state_change(bp, &func_params);
8470 #endif
8471 }
8472
8473 return 0;
8474 }
8475
8476 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8477 {
8478 int port = BP_PORT(bp);
8479 int i, rc = 0;
8480 u8 cos;
8481 struct bnx2x_mcast_ramrod_params rparam = {NULL};
8482 u32 reset_code;
8483
8484 /* Wait until tx fastpath tasks complete */
8485 for_each_tx_queue(bp, i) {
8486 struct bnx2x_fastpath *fp = &bp->fp[i];
8487
8488 for_each_cos_in_tx_queue(fp, cos)
8489 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8490 #ifdef BNX2X_STOP_ON_ERROR
8491 if (rc)
8492 return;
8493 #endif
8494 }
8495
8496 /* Give HW time to discard old tx messages */
8497 usleep_range(1000, 1000);
8498
8499 /* Clean all ETH MACs */
8500 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8501 false);
8502 if (rc < 0)
8503 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8504
8505 /* Clean up UC list */
8506 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8507 true);
8508 if (rc < 0)
8509 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8510 rc);
8511
8512 /* Disable LLH */
8513 if (!CHIP_IS_E1(bp))
8514 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8515
8516 /* Set "drop all" (stop Rx).
8517 * We need to take a netif_addr_lock() here in order to prevent
8518 * a race between the completion code and this code.
8519 */
8520 netif_addr_lock_bh(bp->dev);
8521 /* Schedule the rx_mode command */
8522 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8523 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8524 else
8525 bnx2x_set_storm_rx_mode(bp);
8526
8527 /* Cleanup multicast configuration */
8528 rparam.mcast_obj = &bp->mcast_obj;
8529 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8530 if (rc < 0)
8531 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8532
8533 netif_addr_unlock_bh(bp->dev);
8534
8535
8536
8537 /*
8538 * Send the UNLOAD_REQUEST to the MCP. This will return if
8539 * this function should perform FUNC, PORT or COMMON HW
8540 * reset.
8541 */
8542 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8543
8544 /*
8545 * (assumption: No Attention from MCP at this stage)
8546 * PMF probably in the middle of TXdisable/enable transaction
8547 */
8548 rc = bnx2x_func_wait_started(bp);
8549 if (rc) {
8550 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8551 #ifdef BNX2X_STOP_ON_ERROR
8552 return;
8553 #endif
8554 }
8555
8556 /* Close multi and leading connections
8557 * Completions for ramrods are collected in a synchronous way
8558 */
8559 for_each_eth_queue(bp, i)
8560 if (bnx2x_stop_queue(bp, i))
8561 #ifdef BNX2X_STOP_ON_ERROR
8562 return;
8563 #else
8564 goto unload_error;
8565 #endif
8566
8567 if (CNIC_LOADED(bp)) {
8568 for_each_cnic_queue(bp, i)
8569 if (bnx2x_stop_queue(bp, i))
8570 #ifdef BNX2X_STOP_ON_ERROR
8571 return;
8572 #else
8573 goto unload_error;
8574 #endif
8575 }
8576
8577 /* If SP settings didn't get completed so far - something
8578 * very wrong has happen.
8579 */
8580 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8581 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8582
8583 #ifndef BNX2X_STOP_ON_ERROR
8584 unload_error:
8585 #endif
8586 rc = bnx2x_func_stop(bp);
8587 if (rc) {
8588 BNX2X_ERR("Function stop failed!\n");
8589 #ifdef BNX2X_STOP_ON_ERROR
8590 return;
8591 #endif
8592 }
8593
8594 /* Disable HW interrupts, NAPI */
8595 bnx2x_netif_stop(bp, 1);
8596 /* Delete all NAPI objects */
8597 bnx2x_del_all_napi(bp);
8598 if (CNIC_LOADED(bp))
8599 bnx2x_del_all_napi_cnic(bp);
8600
8601 /* Release IRQs */
8602 bnx2x_free_irq(bp);
8603
8604 /* Reset the chip */
8605 rc = bnx2x_reset_hw(bp, reset_code);
8606 if (rc)
8607 BNX2X_ERR("HW_RESET failed\n");
8608
8609
8610 /* Report UNLOAD_DONE to MCP */
8611 bnx2x_send_unload_done(bp, keep_link);
8612 }
8613
8614 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8615 {
8616 u32 val;
8617
8618 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8619
8620 if (CHIP_IS_E1(bp)) {
8621 int port = BP_PORT(bp);
8622 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8623 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8624
8625 val = REG_RD(bp, addr);
8626 val &= ~(0x300);
8627 REG_WR(bp, addr, val);
8628 } else {
8629 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8630 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8631 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8632 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8633 }
8634 }
8635
8636 /* Close gates #2, #3 and #4: */
8637 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8638 {
8639 u32 val;
8640
8641 /* Gates #2 and #4a are closed/opened for "not E1" only */
8642 if (!CHIP_IS_E1(bp)) {
8643 /* #4 */
8644 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8645 /* #2 */
8646 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8647 }
8648
8649 /* #3 */
8650 if (CHIP_IS_E1x(bp)) {
8651 /* Prevent interrupts from HC on both ports */
8652 val = REG_RD(bp, HC_REG_CONFIG_1);
8653 REG_WR(bp, HC_REG_CONFIG_1,
8654 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8655 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8656
8657 val = REG_RD(bp, HC_REG_CONFIG_0);
8658 REG_WR(bp, HC_REG_CONFIG_0,
8659 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8660 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8661 } else {
8662 /* Prevent incomming interrupts in IGU */
8663 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8664
8665 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8666 (!close) ?
8667 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8668 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8669 }
8670
8671 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8672 close ? "closing" : "opening");
8673 mmiowb();
8674 }
8675
8676 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8677
8678 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8679 {
8680 /* Do some magic... */
8681 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8682 *magic_val = val & SHARED_MF_CLP_MAGIC;
8683 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8684 }
8685
8686 /**
8687 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8688 *
8689 * @bp: driver handle
8690 * @magic_val: old value of the `magic' bit.
8691 */
8692 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8693 {
8694 /* Restore the `magic' bit value... */
8695 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8696 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8697 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8698 }
8699
8700 /**
8701 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8702 *
8703 * @bp: driver handle
8704 * @magic_val: old value of 'magic' bit.
8705 *
8706 * Takes care of CLP configurations.
8707 */
8708 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8709 {
8710 u32 shmem;
8711 u32 validity_offset;
8712
8713 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8714
8715 /* Set `magic' bit in order to save MF config */
8716 if (!CHIP_IS_E1(bp))
8717 bnx2x_clp_reset_prep(bp, magic_val);
8718
8719 /* Get shmem offset */
8720 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8721 validity_offset = offsetof(struct shmem_region, validity_map[0]);
8722
8723 /* Clear validity map flags */
8724 if (shmem > 0)
8725 REG_WR(bp, shmem + validity_offset, 0);
8726 }
8727
8728 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8729 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8730
8731 /**
8732 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8733 *
8734 * @bp: driver handle
8735 */
8736 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8737 {
8738 /* special handling for emulation and FPGA,
8739 wait 10 times longer */
8740 if (CHIP_REV_IS_SLOW(bp))
8741 msleep(MCP_ONE_TIMEOUT*10);
8742 else
8743 msleep(MCP_ONE_TIMEOUT);
8744 }
8745
8746 /*
8747 * initializes bp->common.shmem_base and waits for validity signature to appear
8748 */
8749 static int bnx2x_init_shmem(struct bnx2x *bp)
8750 {
8751 int cnt = 0;
8752 u32 val = 0;
8753
8754 do {
8755 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8756 if (bp->common.shmem_base) {
8757 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8758 if (val & SHR_MEM_VALIDITY_MB)
8759 return 0;
8760 }
8761
8762 bnx2x_mcp_wait_one(bp);
8763
8764 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8765
8766 BNX2X_ERR("BAD MCP validity signature\n");
8767
8768 return -ENODEV;
8769 }
8770
8771 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8772 {
8773 int rc = bnx2x_init_shmem(bp);
8774
8775 /* Restore the `magic' bit value */
8776 if (!CHIP_IS_E1(bp))
8777 bnx2x_clp_reset_done(bp, magic_val);
8778
8779 return rc;
8780 }
8781
8782 static void bnx2x_pxp_prep(struct bnx2x *bp)
8783 {
8784 if (!CHIP_IS_E1(bp)) {
8785 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8786 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8787 mmiowb();
8788 }
8789 }
8790
8791 /*
8792 * Reset the whole chip except for:
8793 * - PCIE core
8794 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8795 * one reset bit)
8796 * - IGU
8797 * - MISC (including AEU)
8798 * - GRC
8799 * - RBCN, RBCP
8800 */
8801 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8802 {
8803 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8804 u32 global_bits2, stay_reset2;
8805
8806 /*
8807 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8808 * (per chip) blocks.
8809 */
8810 global_bits2 =
8811 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8812 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8813
8814 /* Don't reset the following blocks */
8815 not_reset_mask1 =
8816 MISC_REGISTERS_RESET_REG_1_RST_HC |
8817 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8818 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8819
8820 not_reset_mask2 =
8821 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8822 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8823 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8824 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8825 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8826 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8827 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8828 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8829 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8830 MISC_REGISTERS_RESET_REG_2_PGLC;
8831
8832 /*
8833 * Keep the following blocks in reset:
8834 * - all xxMACs are handled by the bnx2x_link code.
8835 */
8836 stay_reset2 =
8837 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8838 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8839 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8840 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8841 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8842 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8843 MISC_REGISTERS_RESET_REG_2_XMAC |
8844 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8845
8846 /* Full reset masks according to the chip */
8847 reset_mask1 = 0xffffffff;
8848
8849 if (CHIP_IS_E1(bp))
8850 reset_mask2 = 0xffff;
8851 else if (CHIP_IS_E1H(bp))
8852 reset_mask2 = 0x1ffff;
8853 else if (CHIP_IS_E2(bp))
8854 reset_mask2 = 0xfffff;
8855 else /* CHIP_IS_E3 */
8856 reset_mask2 = 0x3ffffff;
8857
8858 /* Don't reset global blocks unless we need to */
8859 if (!global)
8860 reset_mask2 &= ~global_bits2;
8861
8862 /*
8863 * In case of attention in the QM, we need to reset PXP
8864 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8865 * because otherwise QM reset would release 'close the gates' shortly
8866 * before resetting the PXP, then the PSWRQ would send a write
8867 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8868 * read the payload data from PSWWR, but PSWWR would not
8869 * respond. The write queue in PGLUE would stuck, dmae commands
8870 * would not return. Therefore it's important to reset the second
8871 * reset register (containing the
8872 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8873 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8874 * bit).
8875 */
8876 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8877 reset_mask2 & (~not_reset_mask2));
8878
8879 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8880 reset_mask1 & (~not_reset_mask1));
8881
8882 barrier();
8883 mmiowb();
8884
8885 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8886 reset_mask2 & (~stay_reset2));
8887
8888 barrier();
8889 mmiowb();
8890
8891 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8892 mmiowb();
8893 }
8894
8895 /**
8896 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8897 * It should get cleared in no more than 1s.
8898 *
8899 * @bp: driver handle
8900 *
8901 * It should get cleared in no more than 1s. Returns 0 if
8902 * pending writes bit gets cleared.
8903 */
8904 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8905 {
8906 u32 cnt = 1000;
8907 u32 pend_bits = 0;
8908
8909 do {
8910 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8911
8912 if (pend_bits == 0)
8913 break;
8914
8915 usleep_range(1000, 1000);
8916 } while (cnt-- > 0);
8917
8918 if (cnt <= 0) {
8919 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8920 pend_bits);
8921 return -EBUSY;
8922 }
8923
8924 return 0;
8925 }
8926
8927 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8928 {
8929 int cnt = 1000;
8930 u32 val = 0;
8931 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8932
8933
8934 /* Empty the Tetris buffer, wait for 1s */
8935 do {
8936 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8937 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8938 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8939 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8940 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8941 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8942 ((port_is_idle_0 & 0x1) == 0x1) &&
8943 ((port_is_idle_1 & 0x1) == 0x1) &&
8944 (pgl_exp_rom2 == 0xffffffff))
8945 break;
8946 usleep_range(1000, 1000);
8947 } while (cnt-- > 0);
8948
8949 if (cnt <= 0) {
8950 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
8951 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8952 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8953 pgl_exp_rom2);
8954 return -EAGAIN;
8955 }
8956
8957 barrier();
8958
8959 /* Close gates #2, #3 and #4 */
8960 bnx2x_set_234_gates(bp, true);
8961
8962 /* Poll for IGU VQs for 57712 and newer chips */
8963 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8964 return -EAGAIN;
8965
8966
8967 /* TBD: Indicate that "process kill" is in progress to MCP */
8968
8969 /* Clear "unprepared" bit */
8970 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8971 barrier();
8972
8973 /* Make sure all is written to the chip before the reset */
8974 mmiowb();
8975
8976 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8977 * PSWHST, GRC and PSWRD Tetris buffer.
8978 */
8979 usleep_range(1000, 1000);
8980
8981 /* Prepare to chip reset: */
8982 /* MCP */
8983 if (global)
8984 bnx2x_reset_mcp_prep(bp, &val);
8985
8986 /* PXP */
8987 bnx2x_pxp_prep(bp);
8988 barrier();
8989
8990 /* reset the chip */
8991 bnx2x_process_kill_chip_reset(bp, global);
8992 barrier();
8993
8994 /* Recover after reset: */
8995 /* MCP */
8996 if (global && bnx2x_reset_mcp_comp(bp, val))
8997 return -EAGAIN;
8998
8999 /* TBD: Add resetting the NO_MCP mode DB here */
9000
9001 /* PXP */
9002 bnx2x_pxp_prep(bp);
9003
9004 /* Open the gates #2, #3 and #4 */
9005 bnx2x_set_234_gates(bp, false);
9006
9007 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9008 * reset state, re-enable attentions. */
9009
9010 return 0;
9011 }
9012
9013 int bnx2x_leader_reset(struct bnx2x *bp)
9014 {
9015 int rc = 0;
9016 bool global = bnx2x_reset_is_global(bp);
9017 u32 load_code;
9018
9019 /* if not going to reset MCP - load "fake" driver to reset HW while
9020 * driver is owner of the HW
9021 */
9022 if (!global && !BP_NOMCP(bp)) {
9023 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9024 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9025 if (!load_code) {
9026 BNX2X_ERR("MCP response failure, aborting\n");
9027 rc = -EAGAIN;
9028 goto exit_leader_reset;
9029 }
9030 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9031 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9032 BNX2X_ERR("MCP unexpected resp, aborting\n");
9033 rc = -EAGAIN;
9034 goto exit_leader_reset2;
9035 }
9036 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9037 if (!load_code) {
9038 BNX2X_ERR("MCP response failure, aborting\n");
9039 rc = -EAGAIN;
9040 goto exit_leader_reset2;
9041 }
9042 }
9043
9044 /* Try to recover after the failure */
9045 if (bnx2x_process_kill(bp, global)) {
9046 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9047 BP_PATH(bp));
9048 rc = -EAGAIN;
9049 goto exit_leader_reset2;
9050 }
9051
9052 /*
9053 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9054 * state.
9055 */
9056 bnx2x_set_reset_done(bp);
9057 if (global)
9058 bnx2x_clear_reset_global(bp);
9059
9060 exit_leader_reset2:
9061 /* unload "fake driver" if it was loaded */
9062 if (!global && !BP_NOMCP(bp)) {
9063 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9064 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9065 }
9066 exit_leader_reset:
9067 bp->is_leader = 0;
9068 bnx2x_release_leader_lock(bp);
9069 smp_mb();
9070 return rc;
9071 }
9072
9073 static void bnx2x_recovery_failed(struct bnx2x *bp)
9074 {
9075 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9076
9077 /* Disconnect this device */
9078 netif_device_detach(bp->dev);
9079
9080 /*
9081 * Block ifup for all function on this engine until "process kill"
9082 * or power cycle.
9083 */
9084 bnx2x_set_reset_in_progress(bp);
9085
9086 /* Shut down the power */
9087 bnx2x_set_power_state(bp, PCI_D3hot);
9088
9089 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9090
9091 smp_mb();
9092 }
9093
9094 /*
9095 * Assumption: runs under rtnl lock. This together with the fact
9096 * that it's called only from bnx2x_sp_rtnl() ensure that it
9097 * will never be called when netif_running(bp->dev) is false.
9098 */
9099 static void bnx2x_parity_recover(struct bnx2x *bp)
9100 {
9101 bool global = false;
9102 u32 error_recovered, error_unrecovered;
9103 bool is_parity;
9104
9105 DP(NETIF_MSG_HW, "Handling parity\n");
9106 while (1) {
9107 switch (bp->recovery_state) {
9108 case BNX2X_RECOVERY_INIT:
9109 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9110 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9111 WARN_ON(!is_parity);
9112
9113 /* Try to get a LEADER_LOCK HW lock */
9114 if (bnx2x_trylock_leader_lock(bp)) {
9115 bnx2x_set_reset_in_progress(bp);
9116 /*
9117 * Check if there is a global attention and if
9118 * there was a global attention, set the global
9119 * reset bit.
9120 */
9121
9122 if (global)
9123 bnx2x_set_reset_global(bp);
9124
9125 bp->is_leader = 1;
9126 }
9127
9128 /* Stop the driver */
9129 /* If interface has been removed - break */
9130 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9131 return;
9132
9133 bp->recovery_state = BNX2X_RECOVERY_WAIT;
9134
9135 /* Ensure "is_leader", MCP command sequence and
9136 * "recovery_state" update values are seen on other
9137 * CPUs.
9138 */
9139 smp_mb();
9140 break;
9141
9142 case BNX2X_RECOVERY_WAIT:
9143 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9144 if (bp->is_leader) {
9145 int other_engine = BP_PATH(bp) ? 0 : 1;
9146 bool other_load_status =
9147 bnx2x_get_load_status(bp, other_engine);
9148 bool load_status =
9149 bnx2x_get_load_status(bp, BP_PATH(bp));
9150 global = bnx2x_reset_is_global(bp);
9151
9152 /*
9153 * In case of a parity in a global block, let
9154 * the first leader that performs a
9155 * leader_reset() reset the global blocks in
9156 * order to clear global attentions. Otherwise
9157 * the the gates will remain closed for that
9158 * engine.
9159 */
9160 if (load_status ||
9161 (global && other_load_status)) {
9162 /* Wait until all other functions get
9163 * down.
9164 */
9165 schedule_delayed_work(&bp->sp_rtnl_task,
9166 HZ/10);
9167 return;
9168 } else {
9169 /* If all other functions got down -
9170 * try to bring the chip back to
9171 * normal. In any case it's an exit
9172 * point for a leader.
9173 */
9174 if (bnx2x_leader_reset(bp)) {
9175 bnx2x_recovery_failed(bp);
9176 return;
9177 }
9178
9179 /* If we are here, means that the
9180 * leader has succeeded and doesn't
9181 * want to be a leader any more. Try
9182 * to continue as a none-leader.
9183 */
9184 break;
9185 }
9186 } else { /* non-leader */
9187 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9188 /* Try to get a LEADER_LOCK HW lock as
9189 * long as a former leader may have
9190 * been unloaded by the user or
9191 * released a leadership by another
9192 * reason.
9193 */
9194 if (bnx2x_trylock_leader_lock(bp)) {
9195 /* I'm a leader now! Restart a
9196 * switch case.
9197 */
9198 bp->is_leader = 1;
9199 break;
9200 }
9201
9202 schedule_delayed_work(&bp->sp_rtnl_task,
9203 HZ/10);
9204 return;
9205
9206 } else {
9207 /*
9208 * If there was a global attention, wait
9209 * for it to be cleared.
9210 */
9211 if (bnx2x_reset_is_global(bp)) {
9212 schedule_delayed_work(
9213 &bp->sp_rtnl_task,
9214 HZ/10);
9215 return;
9216 }
9217
9218 error_recovered =
9219 bp->eth_stats.recoverable_error;
9220 error_unrecovered =
9221 bp->eth_stats.unrecoverable_error;
9222 bp->recovery_state =
9223 BNX2X_RECOVERY_NIC_LOADING;
9224 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9225 error_unrecovered++;
9226 netdev_err(bp->dev,
9227 "Recovery failed. Power cycle needed\n");
9228 /* Disconnect this device */
9229 netif_device_detach(bp->dev);
9230 /* Shut down the power */
9231 bnx2x_set_power_state(
9232 bp, PCI_D3hot);
9233 smp_mb();
9234 } else {
9235 bp->recovery_state =
9236 BNX2X_RECOVERY_DONE;
9237 error_recovered++;
9238 smp_mb();
9239 }
9240 bp->eth_stats.recoverable_error =
9241 error_recovered;
9242 bp->eth_stats.unrecoverable_error =
9243 error_unrecovered;
9244
9245 return;
9246 }
9247 }
9248 default:
9249 return;
9250 }
9251 }
9252 }
9253
9254 static int bnx2x_close(struct net_device *dev);
9255
9256 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9257 * scheduled on a general queue in order to prevent a dead lock.
9258 */
9259 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9260 {
9261 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9262
9263 rtnl_lock();
9264
9265 if (!netif_running(bp->dev))
9266 goto sp_rtnl_exit;
9267
9268 /* if stop on error is defined no recovery flows should be executed */
9269 #ifdef BNX2X_STOP_ON_ERROR
9270 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9271 "you will need to reboot when done\n");
9272 goto sp_rtnl_not_reset;
9273 #endif
9274
9275 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9276 /*
9277 * Clear all pending SP commands as we are going to reset the
9278 * function anyway.
9279 */
9280 bp->sp_rtnl_state = 0;
9281 smp_mb();
9282
9283 bnx2x_parity_recover(bp);
9284
9285 goto sp_rtnl_exit;
9286 }
9287
9288 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9289 /*
9290 * Clear all pending SP commands as we are going to reset the
9291 * function anyway.
9292 */
9293 bp->sp_rtnl_state = 0;
9294 smp_mb();
9295
9296 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9297 bnx2x_nic_load(bp, LOAD_NORMAL);
9298
9299 goto sp_rtnl_exit;
9300 }
9301 #ifdef BNX2X_STOP_ON_ERROR
9302 sp_rtnl_not_reset:
9303 #endif
9304 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9305 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9306 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9307 bnx2x_after_function_update(bp);
9308 /*
9309 * in case of fan failure we need to reset id if the "stop on error"
9310 * debug flag is set, since we trying to prevent permanent overheating
9311 * damage
9312 */
9313 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9314 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9315 netif_device_detach(bp->dev);
9316 bnx2x_close(bp->dev);
9317 }
9318
9319 sp_rtnl_exit:
9320 rtnl_unlock();
9321 }
9322
9323 /* end of nic load/unload */
9324
9325 static void bnx2x_period_task(struct work_struct *work)
9326 {
9327 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9328
9329 if (!netif_running(bp->dev))
9330 goto period_task_exit;
9331
9332 if (CHIP_REV_IS_SLOW(bp)) {
9333 BNX2X_ERR("period task called on emulation, ignoring\n");
9334 goto period_task_exit;
9335 }
9336
9337 bnx2x_acquire_phy_lock(bp);
9338 /*
9339 * The barrier is needed to ensure the ordering between the writing to
9340 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9341 * the reading here.
9342 */
9343 smp_mb();
9344 if (bp->port.pmf) {
9345 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9346
9347 /* Re-queue task in 1 sec */
9348 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9349 }
9350
9351 bnx2x_release_phy_lock(bp);
9352 period_task_exit:
9353 return;
9354 }
9355
9356 /*
9357 * Init service functions
9358 */
9359
9360 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9361 {
9362 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9363 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9364 return base + (BP_ABS_FUNC(bp)) * stride;
9365 }
9366
9367 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
9368 {
9369 u32 reg = bnx2x_get_pretend_reg(bp);
9370
9371 /* Flush all outstanding writes */
9372 mmiowb();
9373
9374 /* Pretend to be function 0 */
9375 REG_WR(bp, reg, 0);
9376 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
9377
9378 /* From now we are in the "like-E1" mode */
9379 bnx2x_int_disable(bp);
9380
9381 /* Flush all outstanding writes */
9382 mmiowb();
9383
9384 /* Restore the original function */
9385 REG_WR(bp, reg, BP_ABS_FUNC(bp));
9386 REG_RD(bp, reg);
9387 }
9388
9389 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
9390 {
9391 if (CHIP_IS_E1(bp))
9392 bnx2x_int_disable(bp);
9393 else
9394 bnx2x_undi_int_disable_e1h(bp);
9395 }
9396
9397 static void __devinit bnx2x_prev_unload_close_mac(struct bnx2x *bp)
9398 {
9399 u32 val, base_addr, offset, mask, reset_reg;
9400 bool mac_stopped = false;
9401 u8 port = BP_PORT(bp);
9402
9403 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9404
9405 if (!CHIP_IS_E3(bp)) {
9406 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9407 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9408 if ((mask & reset_reg) && val) {
9409 u32 wb_data[2];
9410 BNX2X_DEV_INFO("Disable bmac Rx\n");
9411 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9412 : NIG_REG_INGRESS_BMAC0_MEM;
9413 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9414 : BIGMAC_REGISTER_BMAC_CONTROL;
9415
9416 /*
9417 * use rd/wr since we cannot use dmae. This is safe
9418 * since MCP won't access the bus due to the request
9419 * to unload, and no function on the path can be
9420 * loaded at this time.
9421 */
9422 wb_data[0] = REG_RD(bp, base_addr + offset);
9423 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9424 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9425 REG_WR(bp, base_addr + offset, wb_data[0]);
9426 REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
9427
9428 }
9429 BNX2X_DEV_INFO("Disable emac Rx\n");
9430 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
9431
9432 mac_stopped = true;
9433 } else {
9434 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9435 BNX2X_DEV_INFO("Disable xmac Rx\n");
9436 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9437 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9438 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9439 val & ~(1 << 1));
9440 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9441 val | (1 << 1));
9442 REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
9443 mac_stopped = true;
9444 }
9445 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9446 if (mask & reset_reg) {
9447 BNX2X_DEV_INFO("Disable umac Rx\n");
9448 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9449 REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
9450 mac_stopped = true;
9451 }
9452 }
9453
9454 if (mac_stopped)
9455 msleep(20);
9456
9457 }
9458
9459 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9460 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9461 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9462 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9463
9464 static void __devinit bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port,
9465 u8 inc)
9466 {
9467 u16 rcq, bd;
9468 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9469
9470 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9471 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9472
9473 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9474 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9475
9476 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9477 port, bd, rcq);
9478 }
9479
9480 static int __devinit bnx2x_prev_mcp_done(struct bnx2x *bp)
9481 {
9482 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9483 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9484 if (!rc) {
9485 BNX2X_ERR("MCP response failure, aborting\n");
9486 return -EBUSY;
9487 }
9488
9489 return 0;
9490 }
9491
9492 static bool __devinit bnx2x_prev_is_path_marked(struct bnx2x *bp)
9493 {
9494 struct bnx2x_prev_path_list *tmp_list;
9495 int rc = false;
9496
9497 if (down_trylock(&bnx2x_prev_sem))
9498 return false;
9499
9500 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9501 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9502 bp->pdev->bus->number == tmp_list->bus &&
9503 BP_PATH(bp) == tmp_list->path) {
9504 rc = true;
9505 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9506 BP_PATH(bp));
9507 break;
9508 }
9509 }
9510
9511 up(&bnx2x_prev_sem);
9512
9513 return rc;
9514 }
9515
9516 static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp)
9517 {
9518 struct bnx2x_prev_path_list *tmp_list;
9519 int rc;
9520
9521 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9522 if (!tmp_list) {
9523 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9524 return -ENOMEM;
9525 }
9526
9527 tmp_list->bus = bp->pdev->bus->number;
9528 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9529 tmp_list->path = BP_PATH(bp);
9530
9531 rc = down_interruptible(&bnx2x_prev_sem);
9532 if (rc) {
9533 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9534 kfree(tmp_list);
9535 } else {
9536 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9537 BP_PATH(bp));
9538 list_add(&tmp_list->list, &bnx2x_prev_list);
9539 up(&bnx2x_prev_sem);
9540 }
9541
9542 return rc;
9543 }
9544
9545 static int __devinit bnx2x_do_flr(struct bnx2x *bp)
9546 {
9547 int i;
9548 u16 status;
9549 struct pci_dev *dev = bp->pdev;
9550
9551
9552 if (CHIP_IS_E1x(bp)) {
9553 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9554 return -EINVAL;
9555 }
9556
9557 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9558 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9559 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9560 bp->common.bc_ver);
9561 return -EINVAL;
9562 }
9563
9564 /* Wait for Transaction Pending bit clean */
9565 for (i = 0; i < 4; i++) {
9566 if (i)
9567 msleep((1 << (i - 1)) * 100);
9568
9569 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9570 if (!(status & PCI_EXP_DEVSTA_TRPND))
9571 goto clear;
9572 }
9573
9574 dev_err(&dev->dev,
9575 "transaction is not cleared; proceeding with reset anyway\n");
9576
9577 clear:
9578
9579 BNX2X_DEV_INFO("Initiating FLR\n");
9580 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9581
9582 return 0;
9583 }
9584
9585 static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9586 {
9587 int rc;
9588
9589 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9590
9591 /* Test if previous unload process was already finished for this path */
9592 if (bnx2x_prev_is_path_marked(bp))
9593 return bnx2x_prev_mcp_done(bp);
9594
9595 /* If function has FLR capabilities, and existing FW version matches
9596 * the one required, then FLR will be sufficient to clean any residue
9597 * left by previous driver
9598 */
9599 rc = bnx2x_test_firmware_version(bp, false);
9600
9601 if (!rc) {
9602 /* fw version is good */
9603 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9604 rc = bnx2x_do_flr(bp);
9605 }
9606
9607 if (!rc) {
9608 /* FLR was performed */
9609 BNX2X_DEV_INFO("FLR successful\n");
9610 return 0;
9611 }
9612
9613 BNX2X_DEV_INFO("Could not FLR\n");
9614
9615 /* Close the MCP request, return failure*/
9616 rc = bnx2x_prev_mcp_done(bp);
9617 if (!rc)
9618 rc = BNX2X_PREV_WAIT_NEEDED;
9619
9620 return rc;
9621 }
9622
9623 static int __devinit bnx2x_prev_unload_common(struct bnx2x *bp)
9624 {
9625 u32 reset_reg, tmp_reg = 0, rc;
9626 /* It is possible a previous function received 'common' answer,
9627 * but hasn't loaded yet, therefore creating a scenario of
9628 * multiple functions receiving 'common' on the same path.
9629 */
9630 BNX2X_DEV_INFO("Common unload Flow\n");
9631
9632 if (bnx2x_prev_is_path_marked(bp))
9633 return bnx2x_prev_mcp_done(bp);
9634
9635 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9636
9637 /* Reset should be performed after BRB is emptied */
9638 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9639 u32 timer_count = 1000;
9640 bool prev_undi = false;
9641
9642 /* Close the MAC Rx to prevent BRB from filling up */
9643 bnx2x_prev_unload_close_mac(bp);
9644
9645 /* Check if the UNDI driver was previously loaded
9646 * UNDI driver initializes CID offset for normal bell to 0x7
9647 */
9648 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9649 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9650 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9651 if (tmp_reg == 0x7) {
9652 BNX2X_DEV_INFO("UNDI previously loaded\n");
9653 prev_undi = true;
9654 /* clear the UNDI indication */
9655 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9656 }
9657 }
9658 /* wait until BRB is empty */
9659 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9660 while (timer_count) {
9661 u32 prev_brb = tmp_reg;
9662
9663 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9664 if (!tmp_reg)
9665 break;
9666
9667 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9668
9669 /* reset timer as long as BRB actually gets emptied */
9670 if (prev_brb > tmp_reg)
9671 timer_count = 1000;
9672 else
9673 timer_count--;
9674
9675 /* If UNDI resides in memory, manually increment it */
9676 if (prev_undi)
9677 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9678
9679 udelay(10);
9680 }
9681
9682 if (!timer_count)
9683 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9684
9685 }
9686
9687 /* No packets are in the pipeline, path is ready for reset */
9688 bnx2x_reset_common(bp);
9689
9690 rc = bnx2x_prev_mark_path(bp);
9691 if (rc) {
9692 bnx2x_prev_mcp_done(bp);
9693 return rc;
9694 }
9695
9696 return bnx2x_prev_mcp_done(bp);
9697 }
9698
9699 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9700 * and boot began, or when kdump kernel was loaded. Either case would invalidate
9701 * the addresses of the transaction, resulting in was-error bit set in the pci
9702 * causing all hw-to-host pcie transactions to timeout. If this happened we want
9703 * to clear the interrupt which detected this from the pglueb and the was done
9704 * bit
9705 */
9706 static void __devinit bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
9707 {
9708 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9709 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9710 BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9711 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << BP_FUNC(bp));
9712 }
9713 }
9714
9715 static int __devinit bnx2x_prev_unload(struct bnx2x *bp)
9716 {
9717 int time_counter = 10;
9718 u32 rc, fw, hw_lock_reg, hw_lock_val;
9719 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9720
9721 /* clear hw from errors which may have resulted from an interrupted
9722 * dmae transaction.
9723 */
9724 bnx2x_prev_interrupted_dmae(bp);
9725
9726 /* Release previously held locks */
9727 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9728 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9729 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9730
9731 hw_lock_val = (REG_RD(bp, hw_lock_reg));
9732 if (hw_lock_val) {
9733 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9734 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9735 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9736 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9737 }
9738
9739 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9740 REG_WR(bp, hw_lock_reg, 0xffffffff);
9741 } else
9742 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9743
9744 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9745 BNX2X_DEV_INFO("Release previously held alr\n");
9746 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9747 }
9748
9749
9750 do {
9751 /* Lock MCP using an unload request */
9752 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9753 if (!fw) {
9754 BNX2X_ERR("MCP response failure, aborting\n");
9755 rc = -EBUSY;
9756 break;
9757 }
9758
9759 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9760 rc = bnx2x_prev_unload_common(bp);
9761 break;
9762 }
9763
9764 /* non-common reply from MCP night require looping */
9765 rc = bnx2x_prev_unload_uncommon(bp);
9766 if (rc != BNX2X_PREV_WAIT_NEEDED)
9767 break;
9768
9769 msleep(20);
9770 } while (--time_counter);
9771
9772 if (!time_counter || rc) {
9773 BNX2X_ERR("Failed unloading previous driver, aborting\n");
9774 rc = -EBUSY;
9775 }
9776
9777 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
9778
9779 return rc;
9780 }
9781
9782 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
9783 {
9784 u32 val, val2, val3, val4, id, boot_mode;
9785 u16 pmc;
9786
9787 /* Get the chip revision id and number. */
9788 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
9789 val = REG_RD(bp, MISC_REG_CHIP_NUM);
9790 id = ((val & 0xffff) << 16);
9791 val = REG_RD(bp, MISC_REG_CHIP_REV);
9792 id |= ((val & 0xf) << 12);
9793 val = REG_RD(bp, MISC_REG_CHIP_METAL);
9794 id |= ((val & 0xff) << 4);
9795 val = REG_RD(bp, MISC_REG_BOND_ID);
9796 id |= (val & 0xf);
9797 bp->common.chip_id = id;
9798
9799 /* force 57811 according to MISC register */
9800 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
9801 if (CHIP_IS_57810(bp))
9802 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
9803 (bp->common.chip_id & 0x0000FFFF);
9804 else if (CHIP_IS_57810_MF(bp))
9805 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
9806 (bp->common.chip_id & 0x0000FFFF);
9807 bp->common.chip_id |= 0x1;
9808 }
9809
9810 /* Set doorbell size */
9811 bp->db_size = (1 << BNX2X_DB_SHIFT);
9812
9813 if (!CHIP_IS_E1x(bp)) {
9814 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
9815 if ((val & 1) == 0)
9816 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
9817 else
9818 val = (val >> 1) & 1;
9819 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
9820 "2_PORT_MODE");
9821 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
9822 CHIP_2_PORT_MODE;
9823
9824 if (CHIP_MODE_IS_4_PORT(bp))
9825 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
9826 else
9827 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
9828 } else {
9829 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
9830 bp->pfid = bp->pf_num; /* 0..7 */
9831 }
9832
9833 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
9834
9835 bp->link_params.chip_id = bp->common.chip_id;
9836 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
9837
9838 val = (REG_RD(bp, 0x2874) & 0x55);
9839 if ((bp->common.chip_id & 0x1) ||
9840 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
9841 bp->flags |= ONE_PORT_FLAG;
9842 BNX2X_DEV_INFO("single port device\n");
9843 }
9844
9845 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
9846 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
9847 (val & MCPR_NVM_CFG4_FLASH_SIZE));
9848 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
9849 bp->common.flash_size, bp->common.flash_size);
9850
9851 bnx2x_init_shmem(bp);
9852
9853
9854
9855 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
9856 MISC_REG_GENERIC_CR_1 :
9857 MISC_REG_GENERIC_CR_0));
9858
9859 bp->link_params.shmem_base = bp->common.shmem_base;
9860 bp->link_params.shmem2_base = bp->common.shmem2_base;
9861 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
9862 bp->common.shmem_base, bp->common.shmem2_base);
9863
9864 if (!bp->common.shmem_base) {
9865 BNX2X_DEV_INFO("MCP not active\n");
9866 bp->flags |= NO_MCP_FLAG;
9867 return;
9868 }
9869
9870 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
9871 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
9872
9873 bp->link_params.hw_led_mode = ((bp->common.hw_config &
9874 SHARED_HW_CFG_LED_MODE_MASK) >>
9875 SHARED_HW_CFG_LED_MODE_SHIFT);
9876
9877 bp->link_params.feature_config_flags = 0;
9878 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
9879 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
9880 bp->link_params.feature_config_flags |=
9881 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9882 else
9883 bp->link_params.feature_config_flags &=
9884 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9885
9886 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
9887 bp->common.bc_ver = val;
9888 BNX2X_DEV_INFO("bc_ver %X\n", val);
9889 if (val < BNX2X_BC_VER) {
9890 /* for now only warn
9891 * later we might need to enforce this */
9892 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
9893 BNX2X_BC_VER, val);
9894 }
9895 bp->link_params.feature_config_flags |=
9896 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
9897 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
9898
9899 bp->link_params.feature_config_flags |=
9900 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
9901 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
9902 bp->link_params.feature_config_flags |=
9903 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
9904 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
9905 bp->link_params.feature_config_flags |=
9906 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
9907 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
9908 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
9909 BC_SUPPORTS_PFC_STATS : 0;
9910
9911 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
9912 BC_SUPPORTS_FCOE_FEATURES : 0;
9913
9914 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
9915 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
9916 boot_mode = SHMEM_RD(bp,
9917 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
9918 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
9919 switch (boot_mode) {
9920 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
9921 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
9922 break;
9923 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
9924 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
9925 break;
9926 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
9927 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
9928 break;
9929 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
9930 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
9931 break;
9932 }
9933
9934 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
9935 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
9936
9937 BNX2X_DEV_INFO("%sWoL capable\n",
9938 (bp->flags & NO_WOL_FLAG) ? "not " : "");
9939
9940 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
9941 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
9942 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
9943 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
9944
9945 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
9946 val, val2, val3, val4);
9947 }
9948
9949 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
9950 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
9951
9952 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
9953 {
9954 int pfid = BP_FUNC(bp);
9955 int igu_sb_id;
9956 u32 val;
9957 u8 fid, igu_sb_cnt = 0;
9958
9959 bp->igu_base_sb = 0xff;
9960 if (CHIP_INT_MODE_IS_BC(bp)) {
9961 int vn = BP_VN(bp);
9962 igu_sb_cnt = bp->igu_sb_cnt;
9963 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
9964 FP_SB_MAX_E1x;
9965
9966 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
9967 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
9968
9969 return;
9970 }
9971
9972 /* IGU in normal mode - read CAM */
9973 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
9974 igu_sb_id++) {
9975 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
9976 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
9977 continue;
9978 fid = IGU_FID(val);
9979 if ((fid & IGU_FID_ENCODE_IS_PF)) {
9980 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
9981 continue;
9982 if (IGU_VEC(val) == 0)
9983 /* default status block */
9984 bp->igu_dsb_id = igu_sb_id;
9985 else {
9986 if (bp->igu_base_sb == 0xff)
9987 bp->igu_base_sb = igu_sb_id;
9988 igu_sb_cnt++;
9989 }
9990 }
9991 }
9992
9993 #ifdef CONFIG_PCI_MSI
9994 /* Due to new PF resource allocation by MFW T7.4 and above, it's
9995 * optional that number of CAM entries will not be equal to the value
9996 * advertised in PCI.
9997 * Driver should use the minimal value of both as the actual status
9998 * block count
9999 */
10000 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10001 #endif
10002
10003 if (igu_sb_cnt == 0)
10004 BNX2X_ERR("CAM configuration error\n");
10005 }
10006
10007 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
10008 u32 switch_cfg)
10009 {
10010 int cfg_size = 0, idx, port = BP_PORT(bp);
10011
10012 /* Aggregation of supported attributes of all external phys */
10013 bp->port.supported[0] = 0;
10014 bp->port.supported[1] = 0;
10015 switch (bp->link_params.num_phys) {
10016 case 1:
10017 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10018 cfg_size = 1;
10019 break;
10020 case 2:
10021 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10022 cfg_size = 1;
10023 break;
10024 case 3:
10025 if (bp->link_params.multi_phy_config &
10026 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10027 bp->port.supported[1] =
10028 bp->link_params.phy[EXT_PHY1].supported;
10029 bp->port.supported[0] =
10030 bp->link_params.phy[EXT_PHY2].supported;
10031 } else {
10032 bp->port.supported[0] =
10033 bp->link_params.phy[EXT_PHY1].supported;
10034 bp->port.supported[1] =
10035 bp->link_params.phy[EXT_PHY2].supported;
10036 }
10037 cfg_size = 2;
10038 break;
10039 }
10040
10041 if (!(bp->port.supported[0] || bp->port.supported[1])) {
10042 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10043 SHMEM_RD(bp,
10044 dev_info.port_hw_config[port].external_phy_config),
10045 SHMEM_RD(bp,
10046 dev_info.port_hw_config[port].external_phy_config2));
10047 return;
10048 }
10049
10050 if (CHIP_IS_E3(bp))
10051 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10052 else {
10053 switch (switch_cfg) {
10054 case SWITCH_CFG_1G:
10055 bp->port.phy_addr = REG_RD(
10056 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10057 break;
10058 case SWITCH_CFG_10G:
10059 bp->port.phy_addr = REG_RD(
10060 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10061 break;
10062 default:
10063 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10064 bp->port.link_config[0]);
10065 return;
10066 }
10067 }
10068 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10069 /* mask what we support according to speed_cap_mask per configuration */
10070 for (idx = 0; idx < cfg_size; idx++) {
10071 if (!(bp->link_params.speed_cap_mask[idx] &
10072 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10073 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10074
10075 if (!(bp->link_params.speed_cap_mask[idx] &
10076 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10077 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10078
10079 if (!(bp->link_params.speed_cap_mask[idx] &
10080 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10081 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10082
10083 if (!(bp->link_params.speed_cap_mask[idx] &
10084 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10085 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10086
10087 if (!(bp->link_params.speed_cap_mask[idx] &
10088 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10089 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10090 SUPPORTED_1000baseT_Full);
10091
10092 if (!(bp->link_params.speed_cap_mask[idx] &
10093 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10094 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10095
10096 if (!(bp->link_params.speed_cap_mask[idx] &
10097 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10098 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10099
10100 }
10101
10102 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10103 bp->port.supported[1]);
10104 }
10105
10106 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
10107 {
10108 u32 link_config, idx, cfg_size = 0;
10109 bp->port.advertising[0] = 0;
10110 bp->port.advertising[1] = 0;
10111 switch (bp->link_params.num_phys) {
10112 case 1:
10113 case 2:
10114 cfg_size = 1;
10115 break;
10116 case 3:
10117 cfg_size = 2;
10118 break;
10119 }
10120 for (idx = 0; idx < cfg_size; idx++) {
10121 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10122 link_config = bp->port.link_config[idx];
10123 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10124 case PORT_FEATURE_LINK_SPEED_AUTO:
10125 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10126 bp->link_params.req_line_speed[idx] =
10127 SPEED_AUTO_NEG;
10128 bp->port.advertising[idx] |=
10129 bp->port.supported[idx];
10130 if (bp->link_params.phy[EXT_PHY1].type ==
10131 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10132 bp->port.advertising[idx] |=
10133 (SUPPORTED_100baseT_Half |
10134 SUPPORTED_100baseT_Full);
10135 } else {
10136 /* force 10G, no AN */
10137 bp->link_params.req_line_speed[idx] =
10138 SPEED_10000;
10139 bp->port.advertising[idx] |=
10140 (ADVERTISED_10000baseT_Full |
10141 ADVERTISED_FIBRE);
10142 continue;
10143 }
10144 break;
10145
10146 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10147 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10148 bp->link_params.req_line_speed[idx] =
10149 SPEED_10;
10150 bp->port.advertising[idx] |=
10151 (ADVERTISED_10baseT_Full |
10152 ADVERTISED_TP);
10153 } else {
10154 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10155 link_config,
10156 bp->link_params.speed_cap_mask[idx]);
10157 return;
10158 }
10159 break;
10160
10161 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10162 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10163 bp->link_params.req_line_speed[idx] =
10164 SPEED_10;
10165 bp->link_params.req_duplex[idx] =
10166 DUPLEX_HALF;
10167 bp->port.advertising[idx] |=
10168 (ADVERTISED_10baseT_Half |
10169 ADVERTISED_TP);
10170 } else {
10171 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10172 link_config,
10173 bp->link_params.speed_cap_mask[idx]);
10174 return;
10175 }
10176 break;
10177
10178 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10179 if (bp->port.supported[idx] &
10180 SUPPORTED_100baseT_Full) {
10181 bp->link_params.req_line_speed[idx] =
10182 SPEED_100;
10183 bp->port.advertising[idx] |=
10184 (ADVERTISED_100baseT_Full |
10185 ADVERTISED_TP);
10186 } else {
10187 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10188 link_config,
10189 bp->link_params.speed_cap_mask[idx]);
10190 return;
10191 }
10192 break;
10193
10194 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10195 if (bp->port.supported[idx] &
10196 SUPPORTED_100baseT_Half) {
10197 bp->link_params.req_line_speed[idx] =
10198 SPEED_100;
10199 bp->link_params.req_duplex[idx] =
10200 DUPLEX_HALF;
10201 bp->port.advertising[idx] |=
10202 (ADVERTISED_100baseT_Half |
10203 ADVERTISED_TP);
10204 } else {
10205 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10206 link_config,
10207 bp->link_params.speed_cap_mask[idx]);
10208 return;
10209 }
10210 break;
10211
10212 case PORT_FEATURE_LINK_SPEED_1G:
10213 if (bp->port.supported[idx] &
10214 SUPPORTED_1000baseT_Full) {
10215 bp->link_params.req_line_speed[idx] =
10216 SPEED_1000;
10217 bp->port.advertising[idx] |=
10218 (ADVERTISED_1000baseT_Full |
10219 ADVERTISED_TP);
10220 } else {
10221 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10222 link_config,
10223 bp->link_params.speed_cap_mask[idx]);
10224 return;
10225 }
10226 break;
10227
10228 case PORT_FEATURE_LINK_SPEED_2_5G:
10229 if (bp->port.supported[idx] &
10230 SUPPORTED_2500baseX_Full) {
10231 bp->link_params.req_line_speed[idx] =
10232 SPEED_2500;
10233 bp->port.advertising[idx] |=
10234 (ADVERTISED_2500baseX_Full |
10235 ADVERTISED_TP);
10236 } else {
10237 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10238 link_config,
10239 bp->link_params.speed_cap_mask[idx]);
10240 return;
10241 }
10242 break;
10243
10244 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10245 if (bp->port.supported[idx] &
10246 SUPPORTED_10000baseT_Full) {
10247 bp->link_params.req_line_speed[idx] =
10248 SPEED_10000;
10249 bp->port.advertising[idx] |=
10250 (ADVERTISED_10000baseT_Full |
10251 ADVERTISED_FIBRE);
10252 } else {
10253 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10254 link_config,
10255 bp->link_params.speed_cap_mask[idx]);
10256 return;
10257 }
10258 break;
10259 case PORT_FEATURE_LINK_SPEED_20G:
10260 bp->link_params.req_line_speed[idx] = SPEED_20000;
10261
10262 break;
10263 default:
10264 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10265 link_config);
10266 bp->link_params.req_line_speed[idx] =
10267 SPEED_AUTO_NEG;
10268 bp->port.advertising[idx] =
10269 bp->port.supported[idx];
10270 break;
10271 }
10272
10273 bp->link_params.req_flow_ctrl[idx] = (link_config &
10274 PORT_FEATURE_FLOW_CONTROL_MASK);
10275 if ((bp->link_params.req_flow_ctrl[idx] ==
10276 BNX2X_FLOW_CTRL_AUTO) &&
10277 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
10278 bp->link_params.req_flow_ctrl[idx] =
10279 BNX2X_FLOW_CTRL_NONE;
10280 }
10281
10282 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10283 bp->link_params.req_line_speed[idx],
10284 bp->link_params.req_duplex[idx],
10285 bp->link_params.req_flow_ctrl[idx],
10286 bp->port.advertising[idx]);
10287 }
10288 }
10289
10290 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10291 {
10292 mac_hi = cpu_to_be16(mac_hi);
10293 mac_lo = cpu_to_be32(mac_lo);
10294 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
10295 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
10296 }
10297
10298 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
10299 {
10300 int port = BP_PORT(bp);
10301 u32 config;
10302 u32 ext_phy_type, ext_phy_config, eee_mode;
10303
10304 bp->link_params.bp = bp;
10305 bp->link_params.port = port;
10306
10307 bp->link_params.lane_config =
10308 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10309
10310 bp->link_params.speed_cap_mask[0] =
10311 SHMEM_RD(bp,
10312 dev_info.port_hw_config[port].speed_capability_mask);
10313 bp->link_params.speed_cap_mask[1] =
10314 SHMEM_RD(bp,
10315 dev_info.port_hw_config[port].speed_capability_mask2);
10316 bp->port.link_config[0] =
10317 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10318
10319 bp->port.link_config[1] =
10320 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10321
10322 bp->link_params.multi_phy_config =
10323 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10324 /* If the device is capable of WoL, set the default state according
10325 * to the HW
10326 */
10327 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10328 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10329 (config & PORT_FEATURE_WOL_ENABLED));
10330
10331 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10332 bp->link_params.lane_config,
10333 bp->link_params.speed_cap_mask[0],
10334 bp->port.link_config[0]);
10335
10336 bp->link_params.switch_cfg = (bp->port.link_config[0] &
10337 PORT_FEATURE_CONNECTED_SWITCH_MASK);
10338 bnx2x_phy_probe(&bp->link_params);
10339 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10340
10341 bnx2x_link_settings_requested(bp);
10342
10343 /*
10344 * If connected directly, work with the internal PHY, otherwise, work
10345 * with the external PHY
10346 */
10347 ext_phy_config =
10348 SHMEM_RD(bp,
10349 dev_info.port_hw_config[port].external_phy_config);
10350 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10351 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10352 bp->mdio.prtad = bp->port.phy_addr;
10353
10354 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10355 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10356 bp->mdio.prtad =
10357 XGXS_EXT_PHY_ADDR(ext_phy_config);
10358
10359 /*
10360 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
10361 * In MF mode, it is set to cover self test cases
10362 */
10363 if (IS_MF(bp))
10364 bp->port.need_hw_lock = 1;
10365 else
10366 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
10367 bp->common.shmem_base,
10368 bp->common.shmem2_base);
10369
10370 /* Configure link feature according to nvram value */
10371 eee_mode = (((SHMEM_RD(bp, dev_info.
10372 port_feature_config[port].eee_power_mode)) &
10373 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10374 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10375 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10376 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10377 EEE_MODE_ENABLE_LPI |
10378 EEE_MODE_OUTPUT_TIME;
10379 } else {
10380 bp->link_params.eee_mode = 0;
10381 }
10382 }
10383
10384 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10385 {
10386 u32 no_flags = NO_ISCSI_FLAG;
10387 int port = BP_PORT(bp);
10388 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10389 drv_lic_key[port].max_iscsi_conn);
10390
10391 if (!CNIC_SUPPORT(bp)) {
10392 bp->flags |= no_flags;
10393 return;
10394 }
10395
10396 /* Get the number of maximum allowed iSCSI connections */
10397 bp->cnic_eth_dev.max_iscsi_conn =
10398 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10399 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10400
10401 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10402 bp->cnic_eth_dev.max_iscsi_conn);
10403
10404 /*
10405 * If maximum allowed number of connections is zero -
10406 * disable the feature.
10407 */
10408 if (!bp->cnic_eth_dev.max_iscsi_conn)
10409 bp->flags |= no_flags;
10410
10411 }
10412
10413 static void __devinit bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10414 {
10415 /* Port info */
10416 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10417 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10418 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10419 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10420
10421 /* Node info */
10422 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10423 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10424 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10425 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10426 }
10427 static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp)
10428 {
10429 int port = BP_PORT(bp);
10430 int func = BP_ABS_FUNC(bp);
10431 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10432 drv_lic_key[port].max_fcoe_conn);
10433
10434 if (!CNIC_SUPPORT(bp)) {
10435 bp->flags |= NO_FCOE_FLAG;
10436 return;
10437 }
10438
10439 /* Get the number of maximum allowed FCoE connections */
10440 bp->cnic_eth_dev.max_fcoe_conn =
10441 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10442 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10443
10444 /* Read the WWN: */
10445 if (!IS_MF(bp)) {
10446 /* Port info */
10447 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10448 SHMEM_RD(bp,
10449 dev_info.port_hw_config[port].
10450 fcoe_wwn_port_name_upper);
10451 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10452 SHMEM_RD(bp,
10453 dev_info.port_hw_config[port].
10454 fcoe_wwn_port_name_lower);
10455
10456 /* Node info */
10457 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10458 SHMEM_RD(bp,
10459 dev_info.port_hw_config[port].
10460 fcoe_wwn_node_name_upper);
10461 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10462 SHMEM_RD(bp,
10463 dev_info.port_hw_config[port].
10464 fcoe_wwn_node_name_lower);
10465 } else if (!IS_MF_SD(bp)) {
10466 /*
10467 * Read the WWN info only if the FCoE feature is enabled for
10468 * this function.
10469 */
10470 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10471 bnx2x_get_ext_wwn_info(bp, func);
10472
10473 } else if (IS_MF_FCOE_SD(bp))
10474 bnx2x_get_ext_wwn_info(bp, func);
10475
10476 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10477
10478 /*
10479 * If maximum allowed number of connections is zero -
10480 * disable the feature.
10481 */
10482 if (!bp->cnic_eth_dev.max_fcoe_conn)
10483 bp->flags |= NO_FCOE_FLAG;
10484 }
10485
10486 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
10487 {
10488 /*
10489 * iSCSI may be dynamically disabled but reading
10490 * info here we will decrease memory usage by driver
10491 * if the feature is disabled for good
10492 */
10493 bnx2x_get_iscsi_info(bp);
10494 bnx2x_get_fcoe_info(bp);
10495 }
10496
10497 static void __devinit bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
10498 {
10499 u32 val, val2;
10500 int func = BP_ABS_FUNC(bp);
10501 int port = BP_PORT(bp);
10502 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10503 u8 *fip_mac = bp->fip_mac;
10504
10505 if (IS_MF(bp)) {
10506 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10507 * FCoE MAC then the appropriate feature should be disabled.
10508 * In non SD mode features configuration comes from struct
10509 * func_ext_config.
10510 */
10511 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
10512 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10513 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10514 val2 = MF_CFG_RD(bp, func_ext_config[func].
10515 iscsi_mac_addr_upper);
10516 val = MF_CFG_RD(bp, func_ext_config[func].
10517 iscsi_mac_addr_lower);
10518 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10519 BNX2X_DEV_INFO
10520 ("Read iSCSI MAC: %pM\n", iscsi_mac);
10521 } else {
10522 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10523 }
10524
10525 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10526 val2 = MF_CFG_RD(bp, func_ext_config[func].
10527 fcoe_mac_addr_upper);
10528 val = MF_CFG_RD(bp, func_ext_config[func].
10529 fcoe_mac_addr_lower);
10530 bnx2x_set_mac_buf(fip_mac, val, val2);
10531 BNX2X_DEV_INFO
10532 ("Read FCoE L2 MAC: %pM\n", fip_mac);
10533 } else {
10534 bp->flags |= NO_FCOE_FLAG;
10535 }
10536
10537 bp->mf_ext_config = cfg;
10538
10539 } else { /* SD MODE */
10540 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10541 /* use primary mac as iscsi mac */
10542 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
10543
10544 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10545 BNX2X_DEV_INFO
10546 ("Read iSCSI MAC: %pM\n", iscsi_mac);
10547 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
10548 /* use primary mac as fip mac */
10549 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
10550 BNX2X_DEV_INFO("SD FCoE MODE\n");
10551 BNX2X_DEV_INFO
10552 ("Read FIP MAC: %pM\n", fip_mac);
10553 }
10554 }
10555
10556 if (IS_MF_STORAGE_SD(bp))
10557 /* Zero primary MAC configuration */
10558 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10559
10560 if (IS_MF_FCOE_AFEX(bp))
10561 /* use FIP MAC as primary MAC */
10562 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10563
10564 } else {
10565 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10566 iscsi_mac_upper);
10567 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10568 iscsi_mac_lower);
10569 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10570
10571 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10572 fcoe_fip_mac_upper);
10573 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10574 fcoe_fip_mac_lower);
10575 bnx2x_set_mac_buf(fip_mac, val, val2);
10576 }
10577
10578 /* Disable iSCSI OOO if MAC configuration is invalid. */
10579 if (!is_valid_ether_addr(iscsi_mac)) {
10580 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10581 memset(iscsi_mac, 0, ETH_ALEN);
10582 }
10583
10584 /* Disable FCoE if MAC configuration is invalid. */
10585 if (!is_valid_ether_addr(fip_mac)) {
10586 bp->flags |= NO_FCOE_FLAG;
10587 memset(bp->fip_mac, 0, ETH_ALEN);
10588 }
10589 }
10590
10591 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10592 {
10593 u32 val, val2;
10594 int func = BP_ABS_FUNC(bp);
10595 int port = BP_PORT(bp);
10596
10597 /* Zero primary MAC configuration */
10598 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10599
10600 if (BP_NOMCP(bp)) {
10601 BNX2X_ERROR("warning: random MAC workaround active\n");
10602 eth_hw_addr_random(bp->dev);
10603 } else if (IS_MF(bp)) {
10604 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10605 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10606 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10607 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10608 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10609
10610 if (CNIC_SUPPORT(bp))
10611 bnx2x_get_cnic_mac_hwinfo(bp);
10612 } else {
10613 /* in SF read MACs from port configuration */
10614 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10615 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10616 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10617
10618 if (CNIC_SUPPORT(bp))
10619 bnx2x_get_cnic_mac_hwinfo(bp);
10620 }
10621
10622 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10623 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
10624
10625 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10626 dev_err(&bp->pdev->dev,
10627 "bad Ethernet MAC address configuration: %pM\n"
10628 "change it manually before bringing up the appropriate network interface\n",
10629 bp->dev->dev_addr);
10630
10631
10632 }
10633
10634 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
10635 {
10636 int /*abs*/func = BP_ABS_FUNC(bp);
10637 int vn;
10638 u32 val = 0;
10639 int rc = 0;
10640
10641 bnx2x_get_common_hwinfo(bp);
10642
10643 /*
10644 * initialize IGU parameters
10645 */
10646 if (CHIP_IS_E1x(bp)) {
10647 bp->common.int_block = INT_BLOCK_HC;
10648
10649 bp->igu_dsb_id = DEF_SB_IGU_ID;
10650 bp->igu_base_sb = 0;
10651 } else {
10652 bp->common.int_block = INT_BLOCK_IGU;
10653
10654 /* do not allow device reset during IGU info preocessing */
10655 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10656
10657 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
10658
10659 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10660 int tout = 5000;
10661
10662 BNX2X_DEV_INFO("FORCING Normal Mode\n");
10663
10664 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10665 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10666 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10667
10668 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10669 tout--;
10670 usleep_range(1000, 1000);
10671 }
10672
10673 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10674 dev_err(&bp->pdev->dev,
10675 "FORCING Normal Mode failed!!!\n");
10676 return -EPERM;
10677 }
10678 }
10679
10680 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10681 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10682 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10683 } else
10684 BNX2X_DEV_INFO("IGU Normal Mode\n");
10685
10686 bnx2x_get_igu_cam_info(bp);
10687
10688 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10689 }
10690
10691 /*
10692 * set base FW non-default (fast path) status block id, this value is
10693 * used to initialize the fw_sb_id saved on the fp/queue structure to
10694 * determine the id used by the FW.
10695 */
10696 if (CHIP_IS_E1x(bp))
10697 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10698 else /*
10699 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10700 * the same queue are indicated on the same IGU SB). So we prefer
10701 * FW and IGU SBs to be the same value.
10702 */
10703 bp->base_fw_ndsb = bp->igu_base_sb;
10704
10705 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
10706 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10707 bp->igu_sb_cnt, bp->base_fw_ndsb);
10708
10709 /*
10710 * Initialize MF configuration
10711 */
10712
10713 bp->mf_ov = 0;
10714 bp->mf_mode = 0;
10715 vn = BP_VN(bp);
10716
10717 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
10718 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10719 bp->common.shmem2_base, SHMEM2_RD(bp, size),
10720 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
10721
10722 if (SHMEM2_HAS(bp, mf_cfg_addr))
10723 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
10724 else
10725 bp->common.mf_cfg_base = bp->common.shmem_base +
10726 offsetof(struct shmem_region, func_mb) +
10727 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
10728 /*
10729 * get mf configuration:
10730 * 1. existence of MF configuration
10731 * 2. MAC address must be legal (check only upper bytes)
10732 * for Switch-Independent mode;
10733 * OVLAN must be legal for Switch-Dependent mode
10734 * 3. SF_MODE configures specific MF mode
10735 */
10736 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10737 /* get mf configuration */
10738 val = SHMEM_RD(bp,
10739 dev_info.shared_feature_config.config);
10740 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
10741
10742 switch (val) {
10743 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
10744 val = MF_CFG_RD(bp, func_mf_config[func].
10745 mac_upper);
10746 /* check for legal mac (upper bytes)*/
10747 if (val != 0xffff) {
10748 bp->mf_mode = MULTI_FUNCTION_SI;
10749 bp->mf_config[vn] = MF_CFG_RD(bp,
10750 func_mf_config[func].config);
10751 } else
10752 BNX2X_DEV_INFO("illegal MAC address for SI\n");
10753 break;
10754 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
10755 if ((!CHIP_IS_E1x(bp)) &&
10756 (MF_CFG_RD(bp, func_mf_config[func].
10757 mac_upper) != 0xffff) &&
10758 (SHMEM2_HAS(bp,
10759 afex_driver_support))) {
10760 bp->mf_mode = MULTI_FUNCTION_AFEX;
10761 bp->mf_config[vn] = MF_CFG_RD(bp,
10762 func_mf_config[func].config);
10763 } else {
10764 BNX2X_DEV_INFO("can not configure afex mode\n");
10765 }
10766 break;
10767 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
10768 /* get OV configuration */
10769 val = MF_CFG_RD(bp,
10770 func_mf_config[FUNC_0].e1hov_tag);
10771 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
10772
10773 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10774 bp->mf_mode = MULTI_FUNCTION_SD;
10775 bp->mf_config[vn] = MF_CFG_RD(bp,
10776 func_mf_config[func].config);
10777 } else
10778 BNX2X_DEV_INFO("illegal OV for SD\n");
10779 break;
10780 default:
10781 /* Unknown configuration: reset mf_config */
10782 bp->mf_config[vn] = 0;
10783 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
10784 }
10785 }
10786
10787 BNX2X_DEV_INFO("%s function mode\n",
10788 IS_MF(bp) ? "multi" : "single");
10789
10790 switch (bp->mf_mode) {
10791 case MULTI_FUNCTION_SD:
10792 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
10793 FUNC_MF_CFG_E1HOV_TAG_MASK;
10794 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10795 bp->mf_ov = val;
10796 bp->path_has_ovlan = true;
10797
10798 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
10799 func, bp->mf_ov, bp->mf_ov);
10800 } else {
10801 dev_err(&bp->pdev->dev,
10802 "No valid MF OV for func %d, aborting\n",
10803 func);
10804 return -EPERM;
10805 }
10806 break;
10807 case MULTI_FUNCTION_AFEX:
10808 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
10809 break;
10810 case MULTI_FUNCTION_SI:
10811 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
10812 func);
10813 break;
10814 default:
10815 if (vn) {
10816 dev_err(&bp->pdev->dev,
10817 "VN %d is in a single function mode, aborting\n",
10818 vn);
10819 return -EPERM;
10820 }
10821 break;
10822 }
10823
10824 /* check if other port on the path needs ovlan:
10825 * Since MF configuration is shared between ports
10826 * Possible mixed modes are only
10827 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
10828 */
10829 if (CHIP_MODE_IS_4_PORT(bp) &&
10830 !bp->path_has_ovlan &&
10831 !IS_MF(bp) &&
10832 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10833 u8 other_port = !BP_PORT(bp);
10834 u8 other_func = BP_PATH(bp) + 2*other_port;
10835 val = MF_CFG_RD(bp,
10836 func_mf_config[other_func].e1hov_tag);
10837 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
10838 bp->path_has_ovlan = true;
10839 }
10840 }
10841
10842 /* adjust igu_sb_cnt to MF for E1x */
10843 if (CHIP_IS_E1x(bp) && IS_MF(bp))
10844 bp->igu_sb_cnt /= E1HVN_MAX;
10845
10846 /* port info */
10847 bnx2x_get_port_hwinfo(bp);
10848
10849 /* Get MAC addresses */
10850 bnx2x_get_mac_hwinfo(bp);
10851
10852 bnx2x_get_cnic_info(bp);
10853
10854 return rc;
10855 }
10856
10857 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
10858 {
10859 int cnt, i, block_end, rodi;
10860 char vpd_start[BNX2X_VPD_LEN+1];
10861 char str_id_reg[VENDOR_ID_LEN+1];
10862 char str_id_cap[VENDOR_ID_LEN+1];
10863 char *vpd_data;
10864 char *vpd_extended_data = NULL;
10865 u8 len;
10866
10867 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
10868 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
10869
10870 if (cnt < BNX2X_VPD_LEN)
10871 goto out_not_found;
10872
10873 /* VPD RO tag should be first tag after identifier string, hence
10874 * we should be able to find it in first BNX2X_VPD_LEN chars
10875 */
10876 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
10877 PCI_VPD_LRDT_RO_DATA);
10878 if (i < 0)
10879 goto out_not_found;
10880
10881 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
10882 pci_vpd_lrdt_size(&vpd_start[i]);
10883
10884 i += PCI_VPD_LRDT_TAG_SIZE;
10885
10886 if (block_end > BNX2X_VPD_LEN) {
10887 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
10888 if (vpd_extended_data == NULL)
10889 goto out_not_found;
10890
10891 /* read rest of vpd image into vpd_extended_data */
10892 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
10893 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
10894 block_end - BNX2X_VPD_LEN,
10895 vpd_extended_data + BNX2X_VPD_LEN);
10896 if (cnt < (block_end - BNX2X_VPD_LEN))
10897 goto out_not_found;
10898 vpd_data = vpd_extended_data;
10899 } else
10900 vpd_data = vpd_start;
10901
10902 /* now vpd_data holds full vpd content in both cases */
10903
10904 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10905 PCI_VPD_RO_KEYWORD_MFR_ID);
10906 if (rodi < 0)
10907 goto out_not_found;
10908
10909 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10910
10911 if (len != VENDOR_ID_LEN)
10912 goto out_not_found;
10913
10914 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10915
10916 /* vendor specific info */
10917 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
10918 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
10919 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
10920 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
10921
10922 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10923 PCI_VPD_RO_KEYWORD_VENDOR0);
10924 if (rodi >= 0) {
10925 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10926
10927 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10928
10929 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
10930 memcpy(bp->fw_ver, &vpd_data[rodi], len);
10931 bp->fw_ver[len] = ' ';
10932 }
10933 }
10934 kfree(vpd_extended_data);
10935 return;
10936 }
10937 out_not_found:
10938 kfree(vpd_extended_data);
10939 return;
10940 }
10941
10942 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
10943 {
10944 u32 flags = 0;
10945
10946 if (CHIP_REV_IS_FPGA(bp))
10947 SET_FLAGS(flags, MODE_FPGA);
10948 else if (CHIP_REV_IS_EMUL(bp))
10949 SET_FLAGS(flags, MODE_EMUL);
10950 else
10951 SET_FLAGS(flags, MODE_ASIC);
10952
10953 if (CHIP_MODE_IS_4_PORT(bp))
10954 SET_FLAGS(flags, MODE_PORT4);
10955 else
10956 SET_FLAGS(flags, MODE_PORT2);
10957
10958 if (CHIP_IS_E2(bp))
10959 SET_FLAGS(flags, MODE_E2);
10960 else if (CHIP_IS_E3(bp)) {
10961 SET_FLAGS(flags, MODE_E3);
10962 if (CHIP_REV(bp) == CHIP_REV_Ax)
10963 SET_FLAGS(flags, MODE_E3_A0);
10964 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
10965 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
10966 }
10967
10968 if (IS_MF(bp)) {
10969 SET_FLAGS(flags, MODE_MF);
10970 switch (bp->mf_mode) {
10971 case MULTI_FUNCTION_SD:
10972 SET_FLAGS(flags, MODE_MF_SD);
10973 break;
10974 case MULTI_FUNCTION_SI:
10975 SET_FLAGS(flags, MODE_MF_SI);
10976 break;
10977 case MULTI_FUNCTION_AFEX:
10978 SET_FLAGS(flags, MODE_MF_AFEX);
10979 break;
10980 }
10981 } else
10982 SET_FLAGS(flags, MODE_SF);
10983
10984 #if defined(__LITTLE_ENDIAN)
10985 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
10986 #else /*(__BIG_ENDIAN)*/
10987 SET_FLAGS(flags, MODE_BIG_ENDIAN);
10988 #endif
10989 INIT_MODE_FLAGS(bp) = flags;
10990 }
10991
10992 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
10993 {
10994 int func;
10995 int rc;
10996
10997 mutex_init(&bp->port.phy_mutex);
10998 mutex_init(&bp->fw_mb_mutex);
10999 spin_lock_init(&bp->stats_lock);
11000
11001
11002 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11003 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11004 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11005 rc = bnx2x_get_hwinfo(bp);
11006 if (rc)
11007 return rc;
11008
11009 bnx2x_set_modes_bitmap(bp);
11010
11011 rc = bnx2x_alloc_mem_bp(bp);
11012 if (rc)
11013 return rc;
11014
11015 bnx2x_read_fwinfo(bp);
11016
11017 func = BP_FUNC(bp);
11018
11019 /* need to reset chip if undi was active */
11020 if (!BP_NOMCP(bp)) {
11021 /* init fw_seq */
11022 bp->fw_seq =
11023 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11024 DRV_MSG_SEQ_NUMBER_MASK;
11025 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11026
11027 bnx2x_prev_unload(bp);
11028 }
11029
11030
11031 if (CHIP_REV_IS_FPGA(bp))
11032 dev_err(&bp->pdev->dev, "FPGA detected\n");
11033
11034 if (BP_NOMCP(bp) && (func == 0))
11035 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11036
11037 bp->disable_tpa = disable_tpa;
11038 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11039
11040 /* Set TPA flags */
11041 if (bp->disable_tpa) {
11042 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11043 bp->dev->features &= ~NETIF_F_LRO;
11044 } else {
11045 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11046 bp->dev->features |= NETIF_F_LRO;
11047 }
11048
11049 if (CHIP_IS_E1(bp))
11050 bp->dropless_fc = 0;
11051 else
11052 bp->dropless_fc = dropless_fc;
11053
11054 bp->mrrs = mrrs;
11055
11056 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11057
11058 /* make sure that the numbers are in the right granularity */
11059 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11060 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11061
11062 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11063
11064 init_timer(&bp->timer);
11065 bp->timer.expires = jiffies + bp->current_interval;
11066 bp->timer.data = (unsigned long) bp;
11067 bp->timer.function = bnx2x_timer;
11068
11069 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11070 bnx2x_dcbx_init_params(bp);
11071
11072 if (CHIP_IS_E1x(bp))
11073 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11074 else
11075 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11076
11077 /* multiple tx priority */
11078 if (CHIP_IS_E1x(bp))
11079 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11080 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11081 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11082 if (CHIP_IS_E3B0(bp))
11083 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11084
11085 /* We need at least one default status block for slow-path events,
11086 * second status block for the L2 queue, and a third status block for
11087 * CNIC if supproted.
11088 */
11089 if (CNIC_SUPPORT(bp))
11090 bp->min_msix_vec_cnt = 3;
11091 else
11092 bp->min_msix_vec_cnt = 2;
11093 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11094
11095 return rc;
11096 }
11097
11098
11099 /****************************************************************************
11100 * General service functions
11101 ****************************************************************************/
11102
11103 /*
11104 * net_device service functions
11105 */
11106
11107 /* called with rtnl_lock */
11108 static int bnx2x_open(struct net_device *dev)
11109 {
11110 struct bnx2x *bp = netdev_priv(dev);
11111 bool global = false;
11112 int other_engine = BP_PATH(bp) ? 0 : 1;
11113 bool other_load_status, load_status;
11114
11115 bp->stats_init = true;
11116
11117 netif_carrier_off(dev);
11118
11119 bnx2x_set_power_state(bp, PCI_D0);
11120
11121 other_load_status = bnx2x_get_load_status(bp, other_engine);
11122 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11123
11124 /*
11125 * If parity had happen during the unload, then attentions
11126 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11127 * want the first function loaded on the current engine to
11128 * complete the recovery.
11129 */
11130 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11131 bnx2x_chk_parity_attn(bp, &global, true))
11132 do {
11133 /*
11134 * If there are attentions and they are in a global
11135 * blocks, set the GLOBAL_RESET bit regardless whether
11136 * it will be this function that will complete the
11137 * recovery or not.
11138 */
11139 if (global)
11140 bnx2x_set_reset_global(bp);
11141
11142 /*
11143 * Only the first function on the current engine should
11144 * try to recover in open. In case of attentions in
11145 * global blocks only the first in the chip should try
11146 * to recover.
11147 */
11148 if ((!load_status &&
11149 (!global || !other_load_status)) &&
11150 bnx2x_trylock_leader_lock(bp) &&
11151 !bnx2x_leader_reset(bp)) {
11152 netdev_info(bp->dev, "Recovered in open\n");
11153 break;
11154 }
11155
11156 /* recovery has failed... */
11157 bnx2x_set_power_state(bp, PCI_D3hot);
11158 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11159
11160 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11161 "If you still see this message after a few retries then power cycle is required.\n");
11162
11163 return -EAGAIN;
11164 } while (0);
11165
11166 bp->recovery_state = BNX2X_RECOVERY_DONE;
11167 return bnx2x_nic_load(bp, LOAD_OPEN);
11168 }
11169
11170 /* called with rtnl_lock */
11171 static int bnx2x_close(struct net_device *dev)
11172 {
11173 struct bnx2x *bp = netdev_priv(dev);
11174
11175 /* Unload the driver, release IRQs */
11176 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11177
11178 /* Power off */
11179 bnx2x_set_power_state(bp, PCI_D3hot);
11180
11181 return 0;
11182 }
11183
11184 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11185 struct bnx2x_mcast_ramrod_params *p)
11186 {
11187 int mc_count = netdev_mc_count(bp->dev);
11188 struct bnx2x_mcast_list_elem *mc_mac =
11189 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11190 struct netdev_hw_addr *ha;
11191
11192 if (!mc_mac)
11193 return -ENOMEM;
11194
11195 INIT_LIST_HEAD(&p->mcast_list);
11196
11197 netdev_for_each_mc_addr(ha, bp->dev) {
11198 mc_mac->mac = bnx2x_mc_addr(ha);
11199 list_add_tail(&mc_mac->link, &p->mcast_list);
11200 mc_mac++;
11201 }
11202
11203 p->mcast_list_len = mc_count;
11204
11205 return 0;
11206 }
11207
11208 static void bnx2x_free_mcast_macs_list(
11209 struct bnx2x_mcast_ramrod_params *p)
11210 {
11211 struct bnx2x_mcast_list_elem *mc_mac =
11212 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11213 link);
11214
11215 WARN_ON(!mc_mac);
11216 kfree(mc_mac);
11217 }
11218
11219 /**
11220 * bnx2x_set_uc_list - configure a new unicast MACs list.
11221 *
11222 * @bp: driver handle
11223 *
11224 * We will use zero (0) as a MAC type for these MACs.
11225 */
11226 static int bnx2x_set_uc_list(struct bnx2x *bp)
11227 {
11228 int rc;
11229 struct net_device *dev = bp->dev;
11230 struct netdev_hw_addr *ha;
11231 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11232 unsigned long ramrod_flags = 0;
11233
11234 /* First schedule a cleanup up of old configuration */
11235 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11236 if (rc < 0) {
11237 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11238 return rc;
11239 }
11240
11241 netdev_for_each_uc_addr(ha, dev) {
11242 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11243 BNX2X_UC_LIST_MAC, &ramrod_flags);
11244 if (rc == -EEXIST) {
11245 DP(BNX2X_MSG_SP,
11246 "Failed to schedule ADD operations: %d\n", rc);
11247 /* do not treat adding same MAC as error */
11248 rc = 0;
11249
11250 } else if (rc < 0) {
11251
11252 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11253 rc);
11254 return rc;
11255 }
11256 }
11257
11258 /* Execute the pending commands */
11259 __set_bit(RAMROD_CONT, &ramrod_flags);
11260 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11261 BNX2X_UC_LIST_MAC, &ramrod_flags);
11262 }
11263
11264 static int bnx2x_set_mc_list(struct bnx2x *bp)
11265 {
11266 struct net_device *dev = bp->dev;
11267 struct bnx2x_mcast_ramrod_params rparam = {NULL};
11268 int rc = 0;
11269
11270 rparam.mcast_obj = &bp->mcast_obj;
11271
11272 /* first, clear all configured multicast MACs */
11273 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11274 if (rc < 0) {
11275 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11276 return rc;
11277 }
11278
11279 /* then, configure a new MACs list */
11280 if (netdev_mc_count(dev)) {
11281 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11282 if (rc) {
11283 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11284 rc);
11285 return rc;
11286 }
11287
11288 /* Now add the new MACs */
11289 rc = bnx2x_config_mcast(bp, &rparam,
11290 BNX2X_MCAST_CMD_ADD);
11291 if (rc < 0)
11292 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11293 rc);
11294
11295 bnx2x_free_mcast_macs_list(&rparam);
11296 }
11297
11298 return rc;
11299 }
11300
11301
11302 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11303 void bnx2x_set_rx_mode(struct net_device *dev)
11304 {
11305 struct bnx2x *bp = netdev_priv(dev);
11306 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11307
11308 if (bp->state != BNX2X_STATE_OPEN) {
11309 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11310 return;
11311 }
11312
11313 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11314
11315 if (dev->flags & IFF_PROMISC)
11316 rx_mode = BNX2X_RX_MODE_PROMISC;
11317 else if ((dev->flags & IFF_ALLMULTI) ||
11318 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11319 CHIP_IS_E1(bp)))
11320 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11321 else {
11322 /* some multicasts */
11323 if (bnx2x_set_mc_list(bp) < 0)
11324 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11325
11326 if (bnx2x_set_uc_list(bp) < 0)
11327 rx_mode = BNX2X_RX_MODE_PROMISC;
11328 }
11329
11330 bp->rx_mode = rx_mode;
11331 /* handle ISCSI SD mode */
11332 if (IS_MF_ISCSI_SD(bp))
11333 bp->rx_mode = BNX2X_RX_MODE_NONE;
11334
11335 /* Schedule the rx_mode command */
11336 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11337 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11338 return;
11339 }
11340
11341 bnx2x_set_storm_rx_mode(bp);
11342 }
11343
11344 /* called with rtnl_lock */
11345 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11346 int devad, u16 addr)
11347 {
11348 struct bnx2x *bp = netdev_priv(netdev);
11349 u16 value;
11350 int rc;
11351
11352 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11353 prtad, devad, addr);
11354
11355 /* The HW expects different devad if CL22 is used */
11356 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11357
11358 bnx2x_acquire_phy_lock(bp);
11359 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11360 bnx2x_release_phy_lock(bp);
11361 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11362
11363 if (!rc)
11364 rc = value;
11365 return rc;
11366 }
11367
11368 /* called with rtnl_lock */
11369 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11370 u16 addr, u16 value)
11371 {
11372 struct bnx2x *bp = netdev_priv(netdev);
11373 int rc;
11374
11375 DP(NETIF_MSG_LINK,
11376 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11377 prtad, devad, addr, value);
11378
11379 /* The HW expects different devad if CL22 is used */
11380 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11381
11382 bnx2x_acquire_phy_lock(bp);
11383 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11384 bnx2x_release_phy_lock(bp);
11385 return rc;
11386 }
11387
11388 /* called with rtnl_lock */
11389 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11390 {
11391 struct bnx2x *bp = netdev_priv(dev);
11392 struct mii_ioctl_data *mdio = if_mii(ifr);
11393
11394 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11395 mdio->phy_id, mdio->reg_num, mdio->val_in);
11396
11397 if (!netif_running(dev))
11398 return -EAGAIN;
11399
11400 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11401 }
11402
11403 #ifdef CONFIG_NET_POLL_CONTROLLER
11404 static void poll_bnx2x(struct net_device *dev)
11405 {
11406 struct bnx2x *bp = netdev_priv(dev);
11407 int i;
11408
11409 for_each_eth_queue(bp, i) {
11410 struct bnx2x_fastpath *fp = &bp->fp[i];
11411 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11412 }
11413 }
11414 #endif
11415
11416 static int bnx2x_validate_addr(struct net_device *dev)
11417 {
11418 struct bnx2x *bp = netdev_priv(dev);
11419
11420 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11421 BNX2X_ERR("Non-valid Ethernet address\n");
11422 return -EADDRNOTAVAIL;
11423 }
11424 return 0;
11425 }
11426
11427 static const struct net_device_ops bnx2x_netdev_ops = {
11428 .ndo_open = bnx2x_open,
11429 .ndo_stop = bnx2x_close,
11430 .ndo_start_xmit = bnx2x_start_xmit,
11431 .ndo_select_queue = bnx2x_select_queue,
11432 .ndo_set_rx_mode = bnx2x_set_rx_mode,
11433 .ndo_set_mac_address = bnx2x_change_mac_addr,
11434 .ndo_validate_addr = bnx2x_validate_addr,
11435 .ndo_do_ioctl = bnx2x_ioctl,
11436 .ndo_change_mtu = bnx2x_change_mtu,
11437 .ndo_fix_features = bnx2x_fix_features,
11438 .ndo_set_features = bnx2x_set_features,
11439 .ndo_tx_timeout = bnx2x_tx_timeout,
11440 #ifdef CONFIG_NET_POLL_CONTROLLER
11441 .ndo_poll_controller = poll_bnx2x,
11442 #endif
11443 .ndo_setup_tc = bnx2x_setup_tc,
11444
11445 #ifdef NETDEV_FCOE_WWNN
11446 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
11447 #endif
11448 };
11449
11450 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11451 {
11452 struct device *dev = &bp->pdev->dev;
11453
11454 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11455 bp->flags |= USING_DAC_FLAG;
11456 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11457 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11458 return -EIO;
11459 }
11460 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11461 dev_err(dev, "System does not support DMA, aborting\n");
11462 return -EIO;
11463 }
11464
11465 return 0;
11466 }
11467
11468 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
11469 struct net_device *dev,
11470 unsigned long board_type)
11471 {
11472 struct bnx2x *bp;
11473 int rc;
11474 u32 pci_cfg_dword;
11475 bool chip_is_e1x = (board_type == BCM57710 ||
11476 board_type == BCM57711 ||
11477 board_type == BCM57711E);
11478
11479 SET_NETDEV_DEV(dev, &pdev->dev);
11480 bp = netdev_priv(dev);
11481
11482 bp->dev = dev;
11483 bp->pdev = pdev;
11484 bp->flags = 0;
11485
11486 rc = pci_enable_device(pdev);
11487 if (rc) {
11488 dev_err(&bp->pdev->dev,
11489 "Cannot enable PCI device, aborting\n");
11490 goto err_out;
11491 }
11492
11493 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11494 dev_err(&bp->pdev->dev,
11495 "Cannot find PCI device base address, aborting\n");
11496 rc = -ENODEV;
11497 goto err_out_disable;
11498 }
11499
11500 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11501 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
11502 " base address, aborting\n");
11503 rc = -ENODEV;
11504 goto err_out_disable;
11505 }
11506
11507 if (atomic_read(&pdev->enable_cnt) == 1) {
11508 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11509 if (rc) {
11510 dev_err(&bp->pdev->dev,
11511 "Cannot obtain PCI resources, aborting\n");
11512 goto err_out_disable;
11513 }
11514
11515 pci_set_master(pdev);
11516 pci_save_state(pdev);
11517 }
11518
11519 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11520 if (bp->pm_cap == 0) {
11521 dev_err(&bp->pdev->dev,
11522 "Cannot find power management capability, aborting\n");
11523 rc = -EIO;
11524 goto err_out_release;
11525 }
11526
11527 if (!pci_is_pcie(pdev)) {
11528 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11529 rc = -EIO;
11530 goto err_out_release;
11531 }
11532
11533 rc = bnx2x_set_coherency_mask(bp);
11534 if (rc)
11535 goto err_out_release;
11536
11537 dev->mem_start = pci_resource_start(pdev, 0);
11538 dev->base_addr = dev->mem_start;
11539 dev->mem_end = pci_resource_end(pdev, 0);
11540
11541 dev->irq = pdev->irq;
11542
11543 bp->regview = pci_ioremap_bar(pdev, 0);
11544 if (!bp->regview) {
11545 dev_err(&bp->pdev->dev,
11546 "Cannot map register space, aborting\n");
11547 rc = -ENOMEM;
11548 goto err_out_release;
11549 }
11550
11551 /* In E1/E1H use pci device function given by kernel.
11552 * In E2/E3 read physical function from ME register since these chips
11553 * support Physical Device Assignment where kernel BDF maybe arbitrary
11554 * (depending on hypervisor).
11555 */
11556 if (chip_is_e1x)
11557 bp->pf_num = PCI_FUNC(pdev->devfn);
11558 else {/* chip is E2/3*/
11559 pci_read_config_dword(bp->pdev,
11560 PCICFG_ME_REGISTER, &pci_cfg_dword);
11561 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11562 ME_REG_ABS_PF_NUM_SHIFT);
11563 }
11564 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11565
11566 bnx2x_set_power_state(bp, PCI_D0);
11567
11568 /* clean indirect addresses */
11569 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11570 PCICFG_VENDOR_ID_OFFSET);
11571 /*
11572 * Clean the following indirect addresses for all functions since it
11573 * is not used by the driver.
11574 */
11575 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11576 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11577 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11578 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11579
11580 if (chip_is_e1x) {
11581 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11582 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11583 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11584 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11585 }
11586
11587 /*
11588 * Enable internal target-read (in case we are probed after PF FLR).
11589 * Must be done prior to any BAR read access. Only for 57712 and up
11590 */
11591 if (!chip_is_e1x)
11592 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11593
11594 dev->watchdog_timeo = TX_TIMEOUT;
11595
11596 dev->netdev_ops = &bnx2x_netdev_ops;
11597 bnx2x_set_ethtool_ops(dev);
11598
11599 dev->priv_flags |= IFF_UNICAST_FLT;
11600
11601 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11602 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11603 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11604 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
11605
11606 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11607 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11608
11609 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
11610 if (bp->flags & USING_DAC_FLAG)
11611 dev->features |= NETIF_F_HIGHDMA;
11612
11613 /* Add Loopback capability to the device */
11614 dev->hw_features |= NETIF_F_LOOPBACK;
11615
11616 #ifdef BCM_DCBNL
11617 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11618 #endif
11619
11620 /* get_port_hwinfo() will set prtad and mmds properly */
11621 bp->mdio.prtad = MDIO_PRTAD_NONE;
11622 bp->mdio.mmds = 0;
11623 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11624 bp->mdio.dev = dev;
11625 bp->mdio.mdio_read = bnx2x_mdio_read;
11626 bp->mdio.mdio_write = bnx2x_mdio_write;
11627
11628 return 0;
11629
11630 err_out_release:
11631 if (atomic_read(&pdev->enable_cnt) == 1)
11632 pci_release_regions(pdev);
11633
11634 err_out_disable:
11635 pci_disable_device(pdev);
11636 pci_set_drvdata(pdev, NULL);
11637
11638 err_out:
11639 return rc;
11640 }
11641
11642 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
11643 int *width, int *speed)
11644 {
11645 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
11646
11647 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
11648
11649 /* return value of 1=2.5GHz 2=5GHz */
11650 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
11651 }
11652
11653 static int bnx2x_check_firmware(struct bnx2x *bp)
11654 {
11655 const struct firmware *firmware = bp->firmware;
11656 struct bnx2x_fw_file_hdr *fw_hdr;
11657 struct bnx2x_fw_file_section *sections;
11658 u32 offset, len, num_ops;
11659 u16 *ops_offsets;
11660 int i;
11661 const u8 *fw_ver;
11662
11663 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
11664 BNX2X_ERR("Wrong FW size\n");
11665 return -EINVAL;
11666 }
11667
11668 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
11669 sections = (struct bnx2x_fw_file_section *)fw_hdr;
11670
11671 /* Make sure none of the offsets and sizes make us read beyond
11672 * the end of the firmware data */
11673 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
11674 offset = be32_to_cpu(sections[i].offset);
11675 len = be32_to_cpu(sections[i].len);
11676 if (offset + len > firmware->size) {
11677 BNX2X_ERR("Section %d length is out of bounds\n", i);
11678 return -EINVAL;
11679 }
11680 }
11681
11682 /* Likewise for the init_ops offsets */
11683 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
11684 ops_offsets = (u16 *)(firmware->data + offset);
11685 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
11686
11687 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
11688 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
11689 BNX2X_ERR("Section offset %d is out of bounds\n", i);
11690 return -EINVAL;
11691 }
11692 }
11693
11694 /* Check FW version */
11695 offset = be32_to_cpu(fw_hdr->fw_version.offset);
11696 fw_ver = firmware->data + offset;
11697 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
11698 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
11699 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
11700 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
11701 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
11702 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
11703 BCM_5710_FW_MAJOR_VERSION,
11704 BCM_5710_FW_MINOR_VERSION,
11705 BCM_5710_FW_REVISION_VERSION,
11706 BCM_5710_FW_ENGINEERING_VERSION);
11707 return -EINVAL;
11708 }
11709
11710 return 0;
11711 }
11712
11713 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11714 {
11715 const __be32 *source = (const __be32 *)_source;
11716 u32 *target = (u32 *)_target;
11717 u32 i;
11718
11719 for (i = 0; i < n/4; i++)
11720 target[i] = be32_to_cpu(source[i]);
11721 }
11722
11723 /*
11724 Ops array is stored in the following format:
11725 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
11726 */
11727 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
11728 {
11729 const __be32 *source = (const __be32 *)_source;
11730 struct raw_op *target = (struct raw_op *)_target;
11731 u32 i, j, tmp;
11732
11733 for (i = 0, j = 0; i < n/8; i++, j += 2) {
11734 tmp = be32_to_cpu(source[j]);
11735 target[i].op = (tmp >> 24) & 0xff;
11736 target[i].offset = tmp & 0xffffff;
11737 target[i].raw_data = be32_to_cpu(source[j + 1]);
11738 }
11739 }
11740
11741 /* IRO array is stored in the following format:
11742 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
11743 */
11744 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
11745 {
11746 const __be32 *source = (const __be32 *)_source;
11747 struct iro *target = (struct iro *)_target;
11748 u32 i, j, tmp;
11749
11750 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
11751 target[i].base = be32_to_cpu(source[j]);
11752 j++;
11753 tmp = be32_to_cpu(source[j]);
11754 target[i].m1 = (tmp >> 16) & 0xffff;
11755 target[i].m2 = tmp & 0xffff;
11756 j++;
11757 tmp = be32_to_cpu(source[j]);
11758 target[i].m3 = (tmp >> 16) & 0xffff;
11759 target[i].size = tmp & 0xffff;
11760 j++;
11761 }
11762 }
11763
11764 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11765 {
11766 const __be16 *source = (const __be16 *)_source;
11767 u16 *target = (u16 *)_target;
11768 u32 i;
11769
11770 for (i = 0; i < n/2; i++)
11771 target[i] = be16_to_cpu(source[i]);
11772 }
11773
11774 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
11775 do { \
11776 u32 len = be32_to_cpu(fw_hdr->arr.len); \
11777 bp->arr = kmalloc(len, GFP_KERNEL); \
11778 if (!bp->arr) \
11779 goto lbl; \
11780 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
11781 (u8 *)bp->arr, len); \
11782 } while (0)
11783
11784 static int bnx2x_init_firmware(struct bnx2x *bp)
11785 {
11786 const char *fw_file_name;
11787 struct bnx2x_fw_file_hdr *fw_hdr;
11788 int rc;
11789
11790 if (bp->firmware)
11791 return 0;
11792
11793 if (CHIP_IS_E1(bp))
11794 fw_file_name = FW_FILE_NAME_E1;
11795 else if (CHIP_IS_E1H(bp))
11796 fw_file_name = FW_FILE_NAME_E1H;
11797 else if (!CHIP_IS_E1x(bp))
11798 fw_file_name = FW_FILE_NAME_E2;
11799 else {
11800 BNX2X_ERR("Unsupported chip revision\n");
11801 return -EINVAL;
11802 }
11803 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
11804
11805 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
11806 if (rc) {
11807 BNX2X_ERR("Can't load firmware file %s\n",
11808 fw_file_name);
11809 goto request_firmware_exit;
11810 }
11811
11812 rc = bnx2x_check_firmware(bp);
11813 if (rc) {
11814 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
11815 goto request_firmware_exit;
11816 }
11817
11818 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
11819
11820 /* Initialize the pointers to the init arrays */
11821 /* Blob */
11822 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
11823
11824 /* Opcodes */
11825 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
11826
11827 /* Offsets */
11828 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
11829 be16_to_cpu_n);
11830
11831 /* STORMs firmware */
11832 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11833 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
11834 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
11835 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
11836 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11837 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
11838 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
11839 be32_to_cpu(fw_hdr->usem_pram_data.offset);
11840 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11841 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
11842 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
11843 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
11844 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11845 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
11846 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
11847 be32_to_cpu(fw_hdr->csem_pram_data.offset);
11848 /* IRO */
11849 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
11850
11851 return 0;
11852
11853 iro_alloc_err:
11854 kfree(bp->init_ops_offsets);
11855 init_offsets_alloc_err:
11856 kfree(bp->init_ops);
11857 init_ops_alloc_err:
11858 kfree(bp->init_data);
11859 request_firmware_exit:
11860 release_firmware(bp->firmware);
11861 bp->firmware = NULL;
11862
11863 return rc;
11864 }
11865
11866 static void bnx2x_release_firmware(struct bnx2x *bp)
11867 {
11868 kfree(bp->init_ops_offsets);
11869 kfree(bp->init_ops);
11870 kfree(bp->init_data);
11871 release_firmware(bp->firmware);
11872 bp->firmware = NULL;
11873 }
11874
11875
11876 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
11877 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
11878 .init_hw_cmn = bnx2x_init_hw_common,
11879 .init_hw_port = bnx2x_init_hw_port,
11880 .init_hw_func = bnx2x_init_hw_func,
11881
11882 .reset_hw_cmn = bnx2x_reset_common,
11883 .reset_hw_port = bnx2x_reset_port,
11884 .reset_hw_func = bnx2x_reset_func,
11885
11886 .gunzip_init = bnx2x_gunzip_init,
11887 .gunzip_end = bnx2x_gunzip_end,
11888
11889 .init_fw = bnx2x_init_firmware,
11890 .release_fw = bnx2x_release_firmware,
11891 };
11892
11893 void bnx2x__init_func_obj(struct bnx2x *bp)
11894 {
11895 /* Prepare DMAE related driver resources */
11896 bnx2x_setup_dmae(bp);
11897
11898 bnx2x_init_func_obj(bp, &bp->func_obj,
11899 bnx2x_sp(bp, func_rdata),
11900 bnx2x_sp_mapping(bp, func_rdata),
11901 bnx2x_sp(bp, func_afex_rdata),
11902 bnx2x_sp_mapping(bp, func_afex_rdata),
11903 &bnx2x_func_sp_drv);
11904 }
11905
11906 /* must be called after sriov-enable */
11907 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
11908 {
11909 int cid_count = BNX2X_L2_MAX_CID(bp);
11910
11911 if (CNIC_SUPPORT(bp))
11912 cid_count += CNIC_CID_MAX;
11913 return roundup(cid_count, QM_CID_ROUND);
11914 }
11915
11916 /**
11917 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
11918 *
11919 * @dev: pci device
11920 *
11921 */
11922 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
11923 int cnic_cnt)
11924 {
11925 int pos;
11926 u16 control;
11927
11928 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
11929
11930 /*
11931 * If MSI-X is not supported - return number of SBs needed to support
11932 * one fast path queue: one FP queue + SB for CNIC
11933 */
11934 if (!pos)
11935 return 1 + cnic_cnt;
11936
11937 /*
11938 * The value in the PCI configuration space is the index of the last
11939 * entry, namely one less than the actual size of the table, which is
11940 * exactly what we want to return from this function: number of all SBs
11941 * without the default SB.
11942 */
11943 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
11944 return control & PCI_MSIX_FLAGS_QSIZE;
11945 }
11946
11947 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
11948 const struct pci_device_id *ent)
11949 {
11950 struct net_device *dev = NULL;
11951 struct bnx2x *bp;
11952 int pcie_width, pcie_speed;
11953 int rc, max_non_def_sbs;
11954 int rx_count, tx_count, rss_count, doorbell_size;
11955 int cnic_cnt;
11956 /*
11957 * An estimated maximum supported CoS number according to the chip
11958 * version.
11959 * We will try to roughly estimate the maximum number of CoSes this chip
11960 * may support in order to minimize the memory allocated for Tx
11961 * netdev_queue's. This number will be accurately calculated during the
11962 * initialization of bp->max_cos based on the chip versions AND chip
11963 * revision in the bnx2x_init_bp().
11964 */
11965 u8 max_cos_est = 0;
11966
11967 switch (ent->driver_data) {
11968 case BCM57710:
11969 case BCM57711:
11970 case BCM57711E:
11971 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
11972 break;
11973
11974 case BCM57712:
11975 case BCM57712_MF:
11976 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
11977 break;
11978
11979 case BCM57800:
11980 case BCM57800_MF:
11981 case BCM57810:
11982 case BCM57810_MF:
11983 case BCM57840_O:
11984 case BCM57840_4_10:
11985 case BCM57840_2_20:
11986 case BCM57840_MFO:
11987 case BCM57840_MF:
11988 case BCM57811:
11989 case BCM57811_MF:
11990 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
11991 break;
11992
11993 default:
11994 pr_err("Unknown board_type (%ld), aborting\n",
11995 ent->driver_data);
11996 return -ENODEV;
11997 }
11998
11999 cnic_cnt = 1;
12000 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
12001
12002 WARN_ON(!max_non_def_sbs);
12003
12004 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12005 rss_count = max_non_def_sbs - cnic_cnt;
12006
12007 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12008 rx_count = rss_count + cnic_cnt;
12009
12010 /*
12011 * Maximum number of netdev Tx queues:
12012 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
12013 */
12014 tx_count = rss_count * max_cos_est + cnic_cnt;
12015
12016 /* dev zeroed in init_etherdev */
12017 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12018 if (!dev)
12019 return -ENOMEM;
12020
12021 bp = netdev_priv(dev);
12022
12023 bp->igu_sb_cnt = max_non_def_sbs;
12024 bp->msg_enable = debug;
12025 bp->cnic_support = cnic_cnt;
12026
12027 pci_set_drvdata(pdev, dev);
12028
12029 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
12030 if (rc < 0) {
12031 free_netdev(dev);
12032 return rc;
12033 }
12034
12035 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12036 BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs);
12037
12038 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12039 tx_count, rx_count);
12040
12041 rc = bnx2x_init_bp(bp);
12042 if (rc)
12043 goto init_one_exit;
12044
12045 /*
12046 * Map doorbels here as we need the real value of bp->max_cos which
12047 * is initialized in bnx2x_init_bp().
12048 */
12049 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12050 if (doorbell_size > pci_resource_len(pdev, 2)) {
12051 dev_err(&bp->pdev->dev,
12052 "Cannot map doorbells, bar size too small, aborting\n");
12053 rc = -ENOMEM;
12054 goto init_one_exit;
12055 }
12056 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12057 doorbell_size);
12058 if (!bp->doorbells) {
12059 dev_err(&bp->pdev->dev,
12060 "Cannot map doorbell space, aborting\n");
12061 rc = -ENOMEM;
12062 goto init_one_exit;
12063 }
12064
12065 /* calc qm_cid_count */
12066 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12067
12068 /* disable FCOE L2 queue for E1x*/
12069 if (CHIP_IS_E1x(bp))
12070 bp->flags |= NO_FCOE_FLAG;
12071
12072 /* Set bp->num_queues for MSI-X mode*/
12073 bnx2x_set_num_queues(bp);
12074
12075 /* Configure interrupt mode: try to enable MSI-X/MSI if
12076 * needed.
12077 */
12078 bnx2x_set_int_mode(bp);
12079
12080 rc = register_netdev(dev);
12081 if (rc) {
12082 dev_err(&pdev->dev, "Cannot register net device\n");
12083 goto init_one_exit;
12084 }
12085
12086
12087 if (!NO_FCOE(bp)) {
12088 /* Add storage MAC address */
12089 rtnl_lock();
12090 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12091 rtnl_unlock();
12092 }
12093
12094 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12095
12096 BNX2X_DEV_INFO(
12097 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12098 board_info[ent->driver_data].name,
12099 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12100 pcie_width,
12101 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
12102 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
12103 "5GHz (Gen2)" : "2.5GHz",
12104 dev->base_addr, bp->pdev->irq, dev->dev_addr);
12105
12106 return 0;
12107
12108 init_one_exit:
12109 if (bp->regview)
12110 iounmap(bp->regview);
12111
12112 if (bp->doorbells)
12113 iounmap(bp->doorbells);
12114
12115 free_netdev(dev);
12116
12117 if (atomic_read(&pdev->enable_cnt) == 1)
12118 pci_release_regions(pdev);
12119
12120 pci_disable_device(pdev);
12121 pci_set_drvdata(pdev, NULL);
12122
12123 return rc;
12124 }
12125
12126 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
12127 {
12128 struct net_device *dev = pci_get_drvdata(pdev);
12129 struct bnx2x *bp;
12130
12131 if (!dev) {
12132 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12133 return;
12134 }
12135 bp = netdev_priv(dev);
12136
12137 /* Delete storage MAC address */
12138 if (!NO_FCOE(bp)) {
12139 rtnl_lock();
12140 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12141 rtnl_unlock();
12142 }
12143
12144 #ifdef BCM_DCBNL
12145 /* Delete app tlvs from dcbnl */
12146 bnx2x_dcbnl_update_applist(bp, true);
12147 #endif
12148
12149 unregister_netdev(dev);
12150
12151 /* Power on: we can't let PCI layer write to us while we are in D3 */
12152 bnx2x_set_power_state(bp, PCI_D0);
12153
12154 /* Disable MSI/MSI-X */
12155 bnx2x_disable_msi(bp);
12156
12157 /* Power off */
12158 bnx2x_set_power_state(bp, PCI_D3hot);
12159
12160 /* Make sure RESET task is not scheduled before continuing */
12161 cancel_delayed_work_sync(&bp->sp_rtnl_task);
12162
12163 if (bp->regview)
12164 iounmap(bp->regview);
12165
12166 if (bp->doorbells)
12167 iounmap(bp->doorbells);
12168
12169 bnx2x_release_firmware(bp);
12170
12171 bnx2x_free_mem_bp(bp);
12172
12173 free_netdev(dev);
12174
12175 if (atomic_read(&pdev->enable_cnt) == 1)
12176 pci_release_regions(pdev);
12177
12178 pci_disable_device(pdev);
12179 pci_set_drvdata(pdev, NULL);
12180 }
12181
12182 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12183 {
12184 int i;
12185
12186 bp->state = BNX2X_STATE_ERROR;
12187
12188 bp->rx_mode = BNX2X_RX_MODE_NONE;
12189
12190 if (CNIC_LOADED(bp))
12191 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12192
12193 /* Stop Tx */
12194 bnx2x_tx_disable(bp);
12195
12196 bnx2x_netif_stop(bp, 0);
12197 /* Delete all NAPI objects */
12198 bnx2x_del_all_napi(bp);
12199 if (CNIC_LOADED(bp))
12200 bnx2x_del_all_napi_cnic(bp);
12201
12202 del_timer_sync(&bp->timer);
12203
12204 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
12205
12206 /* Release IRQs */
12207 bnx2x_free_irq(bp);
12208
12209 /* Free SKBs, SGEs, TPA pool and driver internals */
12210 bnx2x_free_skbs(bp);
12211
12212 for_each_rx_queue(bp, i)
12213 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12214
12215 bnx2x_free_mem(bp);
12216
12217 bp->state = BNX2X_STATE_CLOSED;
12218
12219 netif_carrier_off(bp->dev);
12220
12221 return 0;
12222 }
12223
12224 static void bnx2x_eeh_recover(struct bnx2x *bp)
12225 {
12226 u32 val;
12227
12228 mutex_init(&bp->port.phy_mutex);
12229
12230
12231 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12232 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12233 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12234 BNX2X_ERR("BAD MCP validity signature\n");
12235 }
12236
12237 /**
12238 * bnx2x_io_error_detected - called when PCI error is detected
12239 * @pdev: Pointer to PCI device
12240 * @state: The current pci connection state
12241 *
12242 * This function is called after a PCI bus error affecting
12243 * this device has been detected.
12244 */
12245 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12246 pci_channel_state_t state)
12247 {
12248 struct net_device *dev = pci_get_drvdata(pdev);
12249 struct bnx2x *bp = netdev_priv(dev);
12250
12251 rtnl_lock();
12252
12253 netif_device_detach(dev);
12254
12255 if (state == pci_channel_io_perm_failure) {
12256 rtnl_unlock();
12257 return PCI_ERS_RESULT_DISCONNECT;
12258 }
12259
12260 if (netif_running(dev))
12261 bnx2x_eeh_nic_unload(bp);
12262
12263 pci_disable_device(pdev);
12264
12265 rtnl_unlock();
12266
12267 /* Request a slot reset */
12268 return PCI_ERS_RESULT_NEED_RESET;
12269 }
12270
12271 /**
12272 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12273 * @pdev: Pointer to PCI device
12274 *
12275 * Restart the card from scratch, as if from a cold-boot.
12276 */
12277 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12278 {
12279 struct net_device *dev = pci_get_drvdata(pdev);
12280 struct bnx2x *bp = netdev_priv(dev);
12281
12282 rtnl_lock();
12283
12284 if (pci_enable_device(pdev)) {
12285 dev_err(&pdev->dev,
12286 "Cannot re-enable PCI device after reset\n");
12287 rtnl_unlock();
12288 return PCI_ERS_RESULT_DISCONNECT;
12289 }
12290
12291 pci_set_master(pdev);
12292 pci_restore_state(pdev);
12293
12294 if (netif_running(dev))
12295 bnx2x_set_power_state(bp, PCI_D0);
12296
12297 rtnl_unlock();
12298
12299 return PCI_ERS_RESULT_RECOVERED;
12300 }
12301
12302 /**
12303 * bnx2x_io_resume - called when traffic can start flowing again
12304 * @pdev: Pointer to PCI device
12305 *
12306 * This callback is called when the error recovery driver tells us that
12307 * its OK to resume normal operation.
12308 */
12309 static void bnx2x_io_resume(struct pci_dev *pdev)
12310 {
12311 struct net_device *dev = pci_get_drvdata(pdev);
12312 struct bnx2x *bp = netdev_priv(dev);
12313
12314 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12315 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12316 return;
12317 }
12318
12319 rtnl_lock();
12320
12321 bnx2x_eeh_recover(bp);
12322
12323 if (netif_running(dev))
12324 bnx2x_nic_load(bp, LOAD_NORMAL);
12325
12326 netif_device_attach(dev);
12327
12328 rtnl_unlock();
12329 }
12330
12331 static const struct pci_error_handlers bnx2x_err_handler = {
12332 .error_detected = bnx2x_io_error_detected,
12333 .slot_reset = bnx2x_io_slot_reset,
12334 .resume = bnx2x_io_resume,
12335 };
12336
12337 static struct pci_driver bnx2x_pci_driver = {
12338 .name = DRV_MODULE_NAME,
12339 .id_table = bnx2x_pci_tbl,
12340 .probe = bnx2x_init_one,
12341 .remove = __devexit_p(bnx2x_remove_one),
12342 .suspend = bnx2x_suspend,
12343 .resume = bnx2x_resume,
12344 .err_handler = &bnx2x_err_handler,
12345 };
12346
12347 static int __init bnx2x_init(void)
12348 {
12349 int ret;
12350
12351 pr_info("%s", version);
12352
12353 bnx2x_wq = create_singlethread_workqueue("bnx2x");
12354 if (bnx2x_wq == NULL) {
12355 pr_err("Cannot create workqueue\n");
12356 return -ENOMEM;
12357 }
12358
12359 ret = pci_register_driver(&bnx2x_pci_driver);
12360 if (ret) {
12361 pr_err("Cannot register driver\n");
12362 destroy_workqueue(bnx2x_wq);
12363 }
12364 return ret;
12365 }
12366
12367 static void __exit bnx2x_cleanup(void)
12368 {
12369 struct list_head *pos, *q;
12370 pci_unregister_driver(&bnx2x_pci_driver);
12371
12372 destroy_workqueue(bnx2x_wq);
12373
12374 /* Free globablly allocated resources */
12375 list_for_each_safe(pos, q, &bnx2x_prev_list) {
12376 struct bnx2x_prev_path_list *tmp =
12377 list_entry(pos, struct bnx2x_prev_path_list, list);
12378 list_del(pos);
12379 kfree(tmp);
12380 }
12381 }
12382
12383 void bnx2x_notify_link_changed(struct bnx2x *bp)
12384 {
12385 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12386 }
12387
12388 module_init(bnx2x_init);
12389 module_exit(bnx2x_cleanup);
12390
12391 /**
12392 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12393 *
12394 * @bp: driver handle
12395 * @set: set or clear the CAM entry
12396 *
12397 * This function will wait until the ramdord completion returns.
12398 * Return 0 if success, -ENODEV if ramrod doesn't return.
12399 */
12400 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12401 {
12402 unsigned long ramrod_flags = 0;
12403
12404 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12405 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12406 &bp->iscsi_l2_mac_obj, true,
12407 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12408 }
12409
12410 /* count denotes the number of new completions we have seen */
12411 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12412 {
12413 struct eth_spe *spe;
12414 int cxt_index, cxt_offset;
12415
12416 #ifdef BNX2X_STOP_ON_ERROR
12417 if (unlikely(bp->panic))
12418 return;
12419 #endif
12420
12421 spin_lock_bh(&bp->spq_lock);
12422 BUG_ON(bp->cnic_spq_pending < count);
12423 bp->cnic_spq_pending -= count;
12424
12425
12426 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12427 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12428 & SPE_HDR_CONN_TYPE) >>
12429 SPE_HDR_CONN_TYPE_SHIFT;
12430 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12431 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12432
12433 /* Set validation for iSCSI L2 client before sending SETUP
12434 * ramrod
12435 */
12436 if (type == ETH_CONNECTION_TYPE) {
12437 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12438 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12439 ILT_PAGE_CIDS;
12440 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12441 (cxt_index * ILT_PAGE_CIDS);
12442 bnx2x_set_ctx_validation(bp,
12443 &bp->context[cxt_index].
12444 vcxt[cxt_offset].eth,
12445 BNX2X_ISCSI_ETH_CID(bp));
12446 }
12447 }
12448
12449 /*
12450 * There may be not more than 8 L2, not more than 8 L5 SPEs
12451 * and in the air. We also check that number of outstanding
12452 * COMMON ramrods is not more than the EQ and SPQ can
12453 * accommodate.
12454 */
12455 if (type == ETH_CONNECTION_TYPE) {
12456 if (!atomic_read(&bp->cq_spq_left))
12457 break;
12458 else
12459 atomic_dec(&bp->cq_spq_left);
12460 } else if (type == NONE_CONNECTION_TYPE) {
12461 if (!atomic_read(&bp->eq_spq_left))
12462 break;
12463 else
12464 atomic_dec(&bp->eq_spq_left);
12465 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12466 (type == FCOE_CONNECTION_TYPE)) {
12467 if (bp->cnic_spq_pending >=
12468 bp->cnic_eth_dev.max_kwqe_pending)
12469 break;
12470 else
12471 bp->cnic_spq_pending++;
12472 } else {
12473 BNX2X_ERR("Unknown SPE type: %d\n", type);
12474 bnx2x_panic();
12475 break;
12476 }
12477
12478 spe = bnx2x_sp_get_next(bp);
12479 *spe = *bp->cnic_kwq_cons;
12480
12481 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
12482 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12483
12484 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12485 bp->cnic_kwq_cons = bp->cnic_kwq;
12486 else
12487 bp->cnic_kwq_cons++;
12488 }
12489 bnx2x_sp_prod_update(bp);
12490 spin_unlock_bh(&bp->spq_lock);
12491 }
12492
12493 static int bnx2x_cnic_sp_queue(struct net_device *dev,
12494 struct kwqe_16 *kwqes[], u32 count)
12495 {
12496 struct bnx2x *bp = netdev_priv(dev);
12497 int i;
12498
12499 #ifdef BNX2X_STOP_ON_ERROR
12500 if (unlikely(bp->panic)) {
12501 BNX2X_ERR("Can't post to SP queue while panic\n");
12502 return -EIO;
12503 }
12504 #endif
12505
12506 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12507 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
12508 BNX2X_ERR("Handling parity error recovery. Try again later\n");
12509 return -EAGAIN;
12510 }
12511
12512 spin_lock_bh(&bp->spq_lock);
12513
12514 for (i = 0; i < count; i++) {
12515 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12516
12517 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12518 break;
12519
12520 *bp->cnic_kwq_prod = *spe;
12521
12522 bp->cnic_kwq_pending++;
12523
12524 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
12525 spe->hdr.conn_and_cmd_data, spe->hdr.type,
12526 spe->data.update_data_addr.hi,
12527 spe->data.update_data_addr.lo,
12528 bp->cnic_kwq_pending);
12529
12530 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12531 bp->cnic_kwq_prod = bp->cnic_kwq;
12532 else
12533 bp->cnic_kwq_prod++;
12534 }
12535
12536 spin_unlock_bh(&bp->spq_lock);
12537
12538 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
12539 bnx2x_cnic_sp_post(bp, 0);
12540
12541 return i;
12542 }
12543
12544 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12545 {
12546 struct cnic_ops *c_ops;
12547 int rc = 0;
12548
12549 mutex_lock(&bp->cnic_mutex);
12550 c_ops = rcu_dereference_protected(bp->cnic_ops,
12551 lockdep_is_held(&bp->cnic_mutex));
12552 if (c_ops)
12553 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12554 mutex_unlock(&bp->cnic_mutex);
12555
12556 return rc;
12557 }
12558
12559 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12560 {
12561 struct cnic_ops *c_ops;
12562 int rc = 0;
12563
12564 rcu_read_lock();
12565 c_ops = rcu_dereference(bp->cnic_ops);
12566 if (c_ops)
12567 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12568 rcu_read_unlock();
12569
12570 return rc;
12571 }
12572
12573 /*
12574 * for commands that have no data
12575 */
12576 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
12577 {
12578 struct cnic_ctl_info ctl = {0};
12579
12580 ctl.cmd = cmd;
12581
12582 return bnx2x_cnic_ctl_send(bp, &ctl);
12583 }
12584
12585 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
12586 {
12587 struct cnic_ctl_info ctl = {0};
12588
12589 /* first we tell CNIC and only then we count this as a completion */
12590 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
12591 ctl.data.comp.cid = cid;
12592 ctl.data.comp.error = err;
12593
12594 bnx2x_cnic_ctl_send_bh(bp, &ctl);
12595 bnx2x_cnic_sp_post(bp, 0);
12596 }
12597
12598
12599 /* Called with netif_addr_lock_bh() taken.
12600 * Sets an rx_mode config for an iSCSI ETH client.
12601 * Doesn't block.
12602 * Completion should be checked outside.
12603 */
12604 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
12605 {
12606 unsigned long accept_flags = 0, ramrod_flags = 0;
12607 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12608 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
12609
12610 if (start) {
12611 /* Start accepting on iSCSI L2 ring. Accept all multicasts
12612 * because it's the only way for UIO Queue to accept
12613 * multicasts (in non-promiscuous mode only one Queue per
12614 * function will receive multicast packets (leading in our
12615 * case).
12616 */
12617 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
12618 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
12619 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
12620 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
12621
12622 /* Clear STOP_PENDING bit if START is requested */
12623 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
12624
12625 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
12626 } else
12627 /* Clear START_PENDING bit if STOP is requested */
12628 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
12629
12630 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
12631 set_bit(sched_state, &bp->sp_state);
12632 else {
12633 __set_bit(RAMROD_RX, &ramrod_flags);
12634 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
12635 ramrod_flags);
12636 }
12637 }
12638
12639
12640 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
12641 {
12642 struct bnx2x *bp = netdev_priv(dev);
12643 int rc = 0;
12644
12645 switch (ctl->cmd) {
12646 case DRV_CTL_CTXTBL_WR_CMD: {
12647 u32 index = ctl->data.io.offset;
12648 dma_addr_t addr = ctl->data.io.dma_addr;
12649
12650 bnx2x_ilt_wr(bp, index, addr);
12651 break;
12652 }
12653
12654 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
12655 int count = ctl->data.credit.credit_count;
12656
12657 bnx2x_cnic_sp_post(bp, count);
12658 break;
12659 }
12660
12661 /* rtnl_lock is held. */
12662 case DRV_CTL_START_L2_CMD: {
12663 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12664 unsigned long sp_bits = 0;
12665
12666 /* Configure the iSCSI classification object */
12667 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
12668 cp->iscsi_l2_client_id,
12669 cp->iscsi_l2_cid, BP_FUNC(bp),
12670 bnx2x_sp(bp, mac_rdata),
12671 bnx2x_sp_mapping(bp, mac_rdata),
12672 BNX2X_FILTER_MAC_PENDING,
12673 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
12674 &bp->macs_pool);
12675
12676 /* Set iSCSI MAC address */
12677 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
12678 if (rc)
12679 break;
12680
12681 mmiowb();
12682 barrier();
12683
12684 /* Start accepting on iSCSI L2 ring */
12685
12686 netif_addr_lock_bh(dev);
12687 bnx2x_set_iscsi_eth_rx_mode(bp, true);
12688 netif_addr_unlock_bh(dev);
12689
12690 /* bits to wait on */
12691 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12692 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
12693
12694 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12695 BNX2X_ERR("rx_mode completion timed out!\n");
12696
12697 break;
12698 }
12699
12700 /* rtnl_lock is held. */
12701 case DRV_CTL_STOP_L2_CMD: {
12702 unsigned long sp_bits = 0;
12703
12704 /* Stop accepting on iSCSI L2 ring */
12705 netif_addr_lock_bh(dev);
12706 bnx2x_set_iscsi_eth_rx_mode(bp, false);
12707 netif_addr_unlock_bh(dev);
12708
12709 /* bits to wait on */
12710 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12711 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
12712
12713 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12714 BNX2X_ERR("rx_mode completion timed out!\n");
12715
12716 mmiowb();
12717 barrier();
12718
12719 /* Unset iSCSI L2 MAC */
12720 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
12721 BNX2X_ISCSI_ETH_MAC, true);
12722 break;
12723 }
12724 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
12725 int count = ctl->data.credit.credit_count;
12726
12727 smp_mb__before_atomic_inc();
12728 atomic_add(count, &bp->cq_spq_left);
12729 smp_mb__after_atomic_inc();
12730 break;
12731 }
12732 case DRV_CTL_ULP_REGISTER_CMD: {
12733 int ulp_type = ctl->data.register_data.ulp_type;
12734
12735 if (CHIP_IS_E3(bp)) {
12736 int idx = BP_FW_MB_IDX(bp);
12737 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12738 int path = BP_PATH(bp);
12739 int port = BP_PORT(bp);
12740 int i;
12741 u32 scratch_offset;
12742 u32 *host_addr;
12743
12744 /* first write capability to shmem2 */
12745 if (ulp_type == CNIC_ULP_ISCSI)
12746 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12747 else if (ulp_type == CNIC_ULP_FCOE)
12748 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12749 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12750
12751 if ((ulp_type != CNIC_ULP_FCOE) ||
12752 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
12753 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
12754 break;
12755
12756 /* if reached here - should write fcoe capabilities */
12757 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
12758 if (!scratch_offset)
12759 break;
12760 scratch_offset += offsetof(struct glob_ncsi_oem_data,
12761 fcoe_features[path][port]);
12762 host_addr = (u32 *) &(ctl->data.register_data.
12763 fcoe_features);
12764 for (i = 0; i < sizeof(struct fcoe_capabilities);
12765 i += 4)
12766 REG_WR(bp, scratch_offset + i,
12767 *(host_addr + i/4));
12768 }
12769 break;
12770 }
12771
12772 case DRV_CTL_ULP_UNREGISTER_CMD: {
12773 int ulp_type = ctl->data.ulp_type;
12774
12775 if (CHIP_IS_E3(bp)) {
12776 int idx = BP_FW_MB_IDX(bp);
12777 u32 cap;
12778
12779 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12780 if (ulp_type == CNIC_ULP_ISCSI)
12781 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12782 else if (ulp_type == CNIC_ULP_FCOE)
12783 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12784 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12785 }
12786 break;
12787 }
12788
12789 default:
12790 BNX2X_ERR("unknown command %x\n", ctl->cmd);
12791 rc = -EINVAL;
12792 }
12793
12794 return rc;
12795 }
12796
12797 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
12798 {
12799 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12800
12801 if (bp->flags & USING_MSIX_FLAG) {
12802 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
12803 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
12804 cp->irq_arr[0].vector = bp->msix_table[1].vector;
12805 } else {
12806 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
12807 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
12808 }
12809 if (!CHIP_IS_E1x(bp))
12810 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
12811 else
12812 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
12813
12814 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
12815 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
12816 cp->irq_arr[1].status_blk = bp->def_status_blk;
12817 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
12818 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
12819
12820 cp->num_irq = 2;
12821 }
12822
12823 void bnx2x_setup_cnic_info(struct bnx2x *bp)
12824 {
12825 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12826
12827
12828 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12829 bnx2x_cid_ilt_lines(bp);
12830 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
12831 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
12832 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
12833
12834 if (NO_ISCSI_OOO(bp))
12835 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
12836 }
12837
12838 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
12839 void *data)
12840 {
12841 struct bnx2x *bp = netdev_priv(dev);
12842 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12843 int rc;
12844
12845 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
12846
12847 if (ops == NULL) {
12848 BNX2X_ERR("NULL ops received\n");
12849 return -EINVAL;
12850 }
12851
12852 if (!CNIC_SUPPORT(bp)) {
12853 BNX2X_ERR("Can't register CNIC when not supported\n");
12854 return -EOPNOTSUPP;
12855 }
12856
12857 if (!CNIC_LOADED(bp)) {
12858 rc = bnx2x_load_cnic(bp);
12859 if (rc) {
12860 BNX2X_ERR("CNIC-related load failed\n");
12861 return rc;
12862 }
12863
12864 }
12865
12866 bp->cnic_enabled = true;
12867
12868 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
12869 if (!bp->cnic_kwq)
12870 return -ENOMEM;
12871
12872 bp->cnic_kwq_cons = bp->cnic_kwq;
12873 bp->cnic_kwq_prod = bp->cnic_kwq;
12874 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
12875
12876 bp->cnic_spq_pending = 0;
12877 bp->cnic_kwq_pending = 0;
12878
12879 bp->cnic_data = data;
12880
12881 cp->num_irq = 0;
12882 cp->drv_state |= CNIC_DRV_STATE_REGD;
12883 cp->iro_arr = bp->iro_arr;
12884
12885 bnx2x_setup_cnic_irq_info(bp);
12886
12887 rcu_assign_pointer(bp->cnic_ops, ops);
12888
12889 return 0;
12890 }
12891
12892 static int bnx2x_unregister_cnic(struct net_device *dev)
12893 {
12894 struct bnx2x *bp = netdev_priv(dev);
12895 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12896
12897 mutex_lock(&bp->cnic_mutex);
12898 cp->drv_state = 0;
12899 RCU_INIT_POINTER(bp->cnic_ops, NULL);
12900 mutex_unlock(&bp->cnic_mutex);
12901 synchronize_rcu();
12902 kfree(bp->cnic_kwq);
12903 bp->cnic_kwq = NULL;
12904
12905 return 0;
12906 }
12907
12908 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
12909 {
12910 struct bnx2x *bp = netdev_priv(dev);
12911 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12912
12913 /* If both iSCSI and FCoE are disabled - return NULL in
12914 * order to indicate CNIC that it should not try to work
12915 * with this device.
12916 */
12917 if (NO_ISCSI(bp) && NO_FCOE(bp))
12918 return NULL;
12919
12920 cp->drv_owner = THIS_MODULE;
12921 cp->chip_id = CHIP_ID(bp);
12922 cp->pdev = bp->pdev;
12923 cp->io_base = bp->regview;
12924 cp->io_base2 = bp->doorbells;
12925 cp->max_kwqe_pending = 8;
12926 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
12927 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12928 bnx2x_cid_ilt_lines(bp);
12929 cp->ctx_tbl_len = CNIC_ILT_LINES;
12930 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
12931 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
12932 cp->drv_ctl = bnx2x_drv_ctl;
12933 cp->drv_register_cnic = bnx2x_register_cnic;
12934 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
12935 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
12936 cp->iscsi_l2_client_id =
12937 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12938 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
12939
12940 if (NO_ISCSI_OOO(bp))
12941 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
12942
12943 if (NO_ISCSI(bp))
12944 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
12945
12946 if (NO_FCOE(bp))
12947 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
12948
12949 BNX2X_DEV_INFO(
12950 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
12951 cp->ctx_blk_size,
12952 cp->ctx_tbl_offset,
12953 cp->ctx_tbl_len,
12954 cp->starting_cid);
12955 return cp;
12956 }
12957 EXPORT_SYMBOL(bnx2x_cnic_probe);
12958
12959
kernel source for telekom puls (alcatel/mediatek)