1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_vfpf.h"
63 #include "bnx2x_dcb.h"
66 #include <linux/firmware.h>
67 #include "bnx2x_fw_file_hdr.h"
69 #define FW_FILE_VERSION \
70 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
71 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
72 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
73 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
74 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
76 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
78 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
80 /* Time in jiffies before concluding the transmitter is hung */
81 #define TX_TIMEOUT (5*HZ)
83 static char version
[] =
84 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
85 DRV_MODULE_NAME
" " DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
87 MODULE_AUTHOR("Eliezer Tamir");
88 MODULE_DESCRIPTION("Broadcom NetXtreme II "
89 "BCM57710/57711/57711E/"
90 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
91 "57840/57840_MF Driver");
92 MODULE_LICENSE("GPL");
93 MODULE_VERSION(DRV_MODULE_VERSION
);
94 MODULE_FIRMWARE(FW_FILE_NAME_E1
);
95 MODULE_FIRMWARE(FW_FILE_NAME_E1H
);
96 MODULE_FIRMWARE(FW_FILE_NAME_E2
);
100 module_param(num_queues
, int, 0);
101 MODULE_PARM_DESC(num_queues
,
102 " Set number of queues (default is as a number of CPUs)");
104 static int disable_tpa
;
105 module_param(disable_tpa
, int, 0);
106 MODULE_PARM_DESC(disable_tpa
, " Disable the TPA (LRO) feature");
108 #define INT_MODE_INTx 1
109 #define INT_MODE_MSI 2
111 module_param(int_mode
, int, 0);
112 MODULE_PARM_DESC(int_mode
, " Force interrupt mode other than MSI-X "
115 static int dropless_fc
;
116 module_param(dropless_fc
, int, 0);
117 MODULE_PARM_DESC(dropless_fc
, " Pause on exhausted host ring");
119 static int mrrs
= -1;
120 module_param(mrrs
, int, 0);
121 MODULE_PARM_DESC(mrrs
, " Force Max Read Req Size (0..3) (for debug)");
124 module_param(debug
, int, 0);
125 MODULE_PARM_DESC(debug
, " Default debug msglevel");
129 struct workqueue_struct
*bnx2x_wq
;
131 struct bnx2x_mac_vals
{
142 enum bnx2x_board_type
{
166 /* indexed by board_type, above */
170 [BCM57710
] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
171 [BCM57711
] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
172 [BCM57711E
] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
173 [BCM57712
] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
174 [BCM57712_MF
] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
175 [BCM57712_VF
] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
176 [BCM57800
] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
177 [BCM57800_MF
] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
178 [BCM57800_VF
] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
179 [BCM57810
] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
180 [BCM57810_MF
] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
181 [BCM57810_VF
] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
182 [BCM57840_4_10
] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
183 [BCM57840_2_20
] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
184 [BCM57840_MF
] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
185 [BCM57840_VF
] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
186 [BCM57811
] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
187 [BCM57811_MF
] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
188 [BCM57840_O
] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
189 [BCM57840_MFO
] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
190 [BCM57811_VF
] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
193 #ifndef PCI_DEVICE_ID_NX2_57710
194 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
196 #ifndef PCI_DEVICE_ID_NX2_57711
197 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
199 #ifndef PCI_DEVICE_ID_NX2_57711E
200 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
202 #ifndef PCI_DEVICE_ID_NX2_57712
203 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
205 #ifndef PCI_DEVICE_ID_NX2_57712_MF
206 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
208 #ifndef PCI_DEVICE_ID_NX2_57712_VF
209 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
211 #ifndef PCI_DEVICE_ID_NX2_57800
212 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
214 #ifndef PCI_DEVICE_ID_NX2_57800_MF
215 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
217 #ifndef PCI_DEVICE_ID_NX2_57800_VF
218 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
220 #ifndef PCI_DEVICE_ID_NX2_57810
221 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
223 #ifndef PCI_DEVICE_ID_NX2_57810_MF
224 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
226 #ifndef PCI_DEVICE_ID_NX2_57840_O
227 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
229 #ifndef PCI_DEVICE_ID_NX2_57810_VF
230 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
232 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
233 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
235 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
236 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
238 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
239 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
241 #ifndef PCI_DEVICE_ID_NX2_57840_MF
242 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
244 #ifndef PCI_DEVICE_ID_NX2_57840_VF
245 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
247 #ifndef PCI_DEVICE_ID_NX2_57811
248 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
250 #ifndef PCI_DEVICE_ID_NX2_57811_MF
251 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
253 #ifndef PCI_DEVICE_ID_NX2_57811_VF
254 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
257 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl
) = {
258 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57710
), BCM57710
},
259 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711
), BCM57711
},
260 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711E
), BCM57711E
},
261 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712
), BCM57712
},
262 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712_MF
), BCM57712_MF
},
263 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712_VF
), BCM57712_VF
},
264 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800
), BCM57800
},
265 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800_MF
), BCM57800_MF
},
266 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800_VF
), BCM57800_VF
},
267 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810
), BCM57810
},
268 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810_MF
), BCM57810_MF
},
269 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_O
), BCM57840_O
},
270 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_4_10
), BCM57840_4_10
},
271 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_2_20
), BCM57840_2_20
},
272 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810_VF
), BCM57810_VF
},
273 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_MFO
), BCM57840_MFO
},
274 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_MF
), BCM57840_MF
},
275 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_VF
), BCM57840_VF
},
276 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57811
), BCM57811
},
277 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57811_MF
), BCM57811_MF
},
278 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57811_VF
), BCM57811_VF
},
282 MODULE_DEVICE_TABLE(pci
, bnx2x_pci_tbl
);
284 /* Global resources for unloading a previously loaded device */
285 #define BNX2X_PREV_WAIT_NEEDED 1
286 static DEFINE_SEMAPHORE(bnx2x_prev_sem
);
287 static LIST_HEAD(bnx2x_prev_list
);
288 /****************************************************************************
289 * General service functions
290 ****************************************************************************/
292 static void __storm_memset_dma_mapping(struct bnx2x
*bp
,
293 u32 addr
, dma_addr_t mapping
)
295 REG_WR(bp
, addr
, U64_LO(mapping
));
296 REG_WR(bp
, addr
+ 4, U64_HI(mapping
));
299 static void storm_memset_spq_addr(struct bnx2x
*bp
,
300 dma_addr_t mapping
, u16 abs_fid
)
302 u32 addr
= XSEM_REG_FAST_MEMORY
+
303 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid
);
305 __storm_memset_dma_mapping(bp
, addr
, mapping
);
308 static void storm_memset_vf_to_pf(struct bnx2x
*bp
, u16 abs_fid
,
311 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_VF_TO_PF_OFFSET(abs_fid
),
313 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_VF_TO_PF_OFFSET(abs_fid
),
315 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_VF_TO_PF_OFFSET(abs_fid
),
317 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_VF_TO_PF_OFFSET(abs_fid
),
321 static void storm_memset_func_en(struct bnx2x
*bp
, u16 abs_fid
,
324 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(abs_fid
),
326 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(abs_fid
),
328 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(abs_fid
),
330 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(abs_fid
),
334 static void storm_memset_eq_data(struct bnx2x
*bp
,
335 struct event_ring_data
*eq_data
,
338 size_t size
= sizeof(struct event_ring_data
);
340 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_DATA_OFFSET(pfid
);
342 __storm_memset_struct(bp
, addr
, size
, (u32
*)eq_data
);
345 static void storm_memset_eq_prod(struct bnx2x
*bp
, u16 eq_prod
,
348 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_PROD_OFFSET(pfid
);
349 REG_WR16(bp
, addr
, eq_prod
);
353 * locking is done by mcp
355 static void bnx2x_reg_wr_ind(struct bnx2x
*bp
, u32 addr
, u32 val
)
357 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
358 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, val
);
359 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
360 PCICFG_VENDOR_ID_OFFSET
);
363 static u32
bnx2x_reg_rd_ind(struct bnx2x
*bp
, u32 addr
)
367 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
368 pci_read_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, &val
);
369 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
370 PCICFG_VENDOR_ID_OFFSET
);
375 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
376 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
377 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
378 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
379 #define DMAE_DP_DST_NONE "dst_addr [none]"
381 void bnx2x_dp_dmae(struct bnx2x
*bp
, struct dmae_command
*dmae
, int msglvl
)
383 u32 src_type
= dmae
->opcode
& DMAE_COMMAND_SRC
;
385 switch (dmae
->opcode
& DMAE_COMMAND_DST
) {
386 case DMAE_CMD_DST_PCI
:
387 if (src_type
== DMAE_CMD_SRC_PCI
)
388 DP(msglvl
, "DMAE: opcode 0x%08x\n"
389 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
390 "comp_addr [%x:%08x], comp_val 0x%08x\n",
391 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
392 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
393 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
396 DP(msglvl
, "DMAE: opcode 0x%08x\n"
397 "src [%08x], len [%d*4], dst [%x:%08x]\n"
398 "comp_addr [%x:%08x], comp_val 0x%08x\n",
399 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
400 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
401 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
404 case DMAE_CMD_DST_GRC
:
405 if (src_type
== DMAE_CMD_SRC_PCI
)
406 DP(msglvl
, "DMAE: opcode 0x%08x\n"
407 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
408 "comp_addr [%x:%08x], comp_val 0x%08x\n",
409 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
410 dmae
->len
, dmae
->dst_addr_lo
>> 2,
411 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
414 DP(msglvl
, "DMAE: opcode 0x%08x\n"
415 "src [%08x], len [%d*4], dst [%08x]\n"
416 "comp_addr [%x:%08x], comp_val 0x%08x\n",
417 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
418 dmae
->len
, dmae
->dst_addr_lo
>> 2,
419 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
423 if (src_type
== DMAE_CMD_SRC_PCI
)
424 DP(msglvl
, "DMAE: opcode 0x%08x\n"
425 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
426 "comp_addr [%x:%08x] comp_val 0x%08x\n",
427 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
428 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
431 DP(msglvl
, "DMAE: opcode 0x%08x\n"
432 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
433 "comp_addr [%x:%08x] comp_val 0x%08x\n",
434 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
435 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
441 /* copy command into DMAE command memory and set DMAE command go */
442 void bnx2x_post_dmae(struct bnx2x
*bp
, struct dmae_command
*dmae
, int idx
)
447 cmd_offset
= (DMAE_REG_CMD_MEM
+ sizeof(struct dmae_command
) * idx
);
448 for (i
= 0; i
< (sizeof(struct dmae_command
)/4); i
++) {
449 REG_WR(bp
, cmd_offset
+ i
*4, *(((u32
*)dmae
) + i
));
451 REG_WR(bp
, dmae_reg_go_c
[idx
], 1);
454 u32
bnx2x_dmae_opcode_add_comp(u32 opcode
, u8 comp_type
)
456 return opcode
| ((comp_type
<< DMAE_COMMAND_C_DST_SHIFT
) |
460 u32
bnx2x_dmae_opcode_clr_src_reset(u32 opcode
)
462 return opcode
& ~DMAE_CMD_SRC_RESET
;
465 u32
bnx2x_dmae_opcode(struct bnx2x
*bp
, u8 src_type
, u8 dst_type
,
466 bool with_comp
, u8 comp_type
)
470 opcode
|= ((src_type
<< DMAE_COMMAND_SRC_SHIFT
) |
471 (dst_type
<< DMAE_COMMAND_DST_SHIFT
));
473 opcode
|= (DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
);
475 opcode
|= (BP_PORT(bp
) ? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
);
476 opcode
|= ((BP_VN(bp
) << DMAE_CMD_E1HVN_SHIFT
) |
477 (BP_VN(bp
) << DMAE_COMMAND_DST_VN_SHIFT
));
478 opcode
|= (DMAE_COM_SET_ERR
<< DMAE_COMMAND_ERR_POLICY_SHIFT
);
481 opcode
|= DMAE_CMD_ENDIANITY_B_DW_SWAP
;
483 opcode
|= DMAE_CMD_ENDIANITY_DW_SWAP
;
486 opcode
= bnx2x_dmae_opcode_add_comp(opcode
, comp_type
);
490 void bnx2x_prep_dmae_with_comp(struct bnx2x
*bp
,
491 struct dmae_command
*dmae
,
492 u8 src_type
, u8 dst_type
)
494 memset(dmae
, 0, sizeof(struct dmae_command
));
497 dmae
->opcode
= bnx2x_dmae_opcode(bp
, src_type
, dst_type
,
498 true, DMAE_COMP_PCI
);
500 /* fill in the completion parameters */
501 dmae
->comp_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_comp
));
502 dmae
->comp_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_comp
));
503 dmae
->comp_val
= DMAE_COMP_VAL
;
506 /* issue a dmae command over the init-channel and wait for completion */
507 int bnx2x_issue_dmae_with_comp(struct bnx2x
*bp
, struct dmae_command
*dmae
)
509 u32
*wb_comp
= bnx2x_sp(bp
, wb_comp
);
510 int cnt
= CHIP_REV_IS_SLOW(bp
) ? (400000) : 4000;
514 * Lock the dmae channel. Disable BHs to prevent a dead-lock
515 * as long as this code is called both from syscall context and
516 * from ndo_set_rx_mode() flow that may be called from BH.
518 spin_lock_bh(&bp
->dmae_lock
);
520 /* reset completion */
523 /* post the command on the channel used for initializations */
524 bnx2x_post_dmae(bp
, dmae
, INIT_DMAE_C(bp
));
526 /* wait for completion */
528 while ((*wb_comp
& ~DMAE_PCI_ERR_FLAG
) != DMAE_COMP_VAL
) {
531 (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
&&
532 bp
->recovery_state
!= BNX2X_RECOVERY_NIC_LOADING
)) {
533 BNX2X_ERR("DMAE timeout!\n");
540 if (*wb_comp
& DMAE_PCI_ERR_FLAG
) {
541 BNX2X_ERR("DMAE PCI error!\n");
546 spin_unlock_bh(&bp
->dmae_lock
);
550 void bnx2x_write_dmae(struct bnx2x
*bp
, dma_addr_t dma_addr
, u32 dst_addr
,
553 struct dmae_command dmae
;
555 if (!bp
->dmae_ready
) {
556 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
559 bnx2x_init_ind_wr(bp
, dst_addr
, data
, len32
);
561 bnx2x_init_str_wr(bp
, dst_addr
, data
, len32
);
565 /* set opcode and fixed command fields */
566 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_PCI
, DMAE_DST_GRC
);
568 /* fill in addresses and len */
569 dmae
.src_addr_lo
= U64_LO(dma_addr
);
570 dmae
.src_addr_hi
= U64_HI(dma_addr
);
571 dmae
.dst_addr_lo
= dst_addr
>> 2;
572 dmae
.dst_addr_hi
= 0;
575 /* issue the command and wait for completion */
576 bnx2x_issue_dmae_with_comp(bp
, &dmae
);
579 void bnx2x_read_dmae(struct bnx2x
*bp
, u32 src_addr
, u32 len32
)
581 struct dmae_command dmae
;
583 if (!bp
->dmae_ready
) {
584 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
588 for (i
= 0; i
< len32
; i
++)
589 data
[i
] = bnx2x_reg_rd_ind(bp
, src_addr
+ i
*4);
591 for (i
= 0; i
< len32
; i
++)
592 data
[i
] = REG_RD(bp
, src_addr
+ i
*4);
597 /* set opcode and fixed command fields */
598 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_GRC
, DMAE_DST_PCI
);
600 /* fill in addresses and len */
601 dmae
.src_addr_lo
= src_addr
>> 2;
602 dmae
.src_addr_hi
= 0;
603 dmae
.dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_data
));
604 dmae
.dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_data
));
607 /* issue the command and wait for completion */
608 bnx2x_issue_dmae_with_comp(bp
, &dmae
);
611 static void bnx2x_write_dmae_phys_len(struct bnx2x
*bp
, dma_addr_t phys_addr
,
614 int dmae_wr_max
= DMAE_LEN32_WR_MAX(bp
);
617 while (len
> dmae_wr_max
) {
618 bnx2x_write_dmae(bp
, phys_addr
+ offset
,
619 addr
+ offset
, dmae_wr_max
);
620 offset
+= dmae_wr_max
* 4;
624 bnx2x_write_dmae(bp
, phys_addr
+ offset
, addr
+ offset
, len
);
627 static int bnx2x_mc_assert(struct bnx2x
*bp
)
631 u32 row0
, row1
, row2
, row3
;
634 last_idx
= REG_RD8(bp
, BAR_XSTRORM_INTMEM
+
635 XSTORM_ASSERT_LIST_INDEX_OFFSET
);
637 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
639 /* print the asserts */
640 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
642 row0
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
643 XSTORM_ASSERT_LIST_OFFSET(i
));
644 row1
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
645 XSTORM_ASSERT_LIST_OFFSET(i
) + 4);
646 row2
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
647 XSTORM_ASSERT_LIST_OFFSET(i
) + 8);
648 row3
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
649 XSTORM_ASSERT_LIST_OFFSET(i
) + 12);
651 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
652 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
653 i
, row3
, row2
, row1
, row0
);
661 last_idx
= REG_RD8(bp
, BAR_TSTRORM_INTMEM
+
662 TSTORM_ASSERT_LIST_INDEX_OFFSET
);
664 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
666 /* print the asserts */
667 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
669 row0
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
670 TSTORM_ASSERT_LIST_OFFSET(i
));
671 row1
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
672 TSTORM_ASSERT_LIST_OFFSET(i
) + 4);
673 row2
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
674 TSTORM_ASSERT_LIST_OFFSET(i
) + 8);
675 row3
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
676 TSTORM_ASSERT_LIST_OFFSET(i
) + 12);
678 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
679 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
680 i
, row3
, row2
, row1
, row0
);
688 last_idx
= REG_RD8(bp
, BAR_CSTRORM_INTMEM
+
689 CSTORM_ASSERT_LIST_INDEX_OFFSET
);
691 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
693 /* print the asserts */
694 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
696 row0
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
697 CSTORM_ASSERT_LIST_OFFSET(i
));
698 row1
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
699 CSTORM_ASSERT_LIST_OFFSET(i
) + 4);
700 row2
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
701 CSTORM_ASSERT_LIST_OFFSET(i
) + 8);
702 row3
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
703 CSTORM_ASSERT_LIST_OFFSET(i
) + 12);
705 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
706 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
707 i
, row3
, row2
, row1
, row0
);
715 last_idx
= REG_RD8(bp
, BAR_USTRORM_INTMEM
+
716 USTORM_ASSERT_LIST_INDEX_OFFSET
);
718 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
720 /* print the asserts */
721 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
723 row0
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
724 USTORM_ASSERT_LIST_OFFSET(i
));
725 row1
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
726 USTORM_ASSERT_LIST_OFFSET(i
) + 4);
727 row2
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
728 USTORM_ASSERT_LIST_OFFSET(i
) + 8);
729 row3
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
730 USTORM_ASSERT_LIST_OFFSET(i
) + 12);
732 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
733 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
734 i
, row3
, row2
, row1
, row0
);
744 void bnx2x_fw_dump_lvl(struct bnx2x
*bp
, const char *lvl
)
750 u32 trace_shmem_base
;
752 BNX2X_ERR("NO MCP - can not dump\n");
755 netdev_printk(lvl
, bp
->dev
, "bc %d.%d.%d\n",
756 (bp
->common
.bc_ver
& 0xff0000) >> 16,
757 (bp
->common
.bc_ver
& 0xff00) >> 8,
758 (bp
->common
.bc_ver
& 0xff));
760 val
= REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
);
761 if (val
== REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
))
762 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl
, val
);
764 if (BP_PATH(bp
) == 0)
765 trace_shmem_base
= bp
->common
.shmem_base
;
767 trace_shmem_base
= SHMEM2_RD(bp
, other_shmem_base_addr
);
768 addr
= trace_shmem_base
- 0x800;
770 /* validate TRCB signature */
771 mark
= REG_RD(bp
, addr
);
772 if (mark
!= MFW_TRACE_SIGNATURE
) {
773 BNX2X_ERR("Trace buffer signature is missing.");
777 /* read cyclic buffer pointer */
779 mark
= REG_RD(bp
, addr
);
780 mark
= (CHIP_IS_E1x(bp
) ? MCP_REG_MCPR_SCRATCH
: MCP_A_REG_MCPR_SCRATCH
)
781 + ((mark
+ 0x3) & ~0x3) - 0x08000000;
782 printk("%s" "begin fw dump (mark 0x%x)\n", lvl
, mark
);
785 for (offset
= mark
; offset
<= trace_shmem_base
; offset
+= 0x8*4) {
786 for (word
= 0; word
< 8; word
++)
787 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
789 pr_cont("%s", (char *)data
);
791 for (offset
= addr
+ 4; offset
<= mark
; offset
+= 0x8*4) {
792 for (word
= 0; word
< 8; word
++)
793 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
795 pr_cont("%s", (char *)data
);
797 printk("%s" "end of fw dump\n", lvl
);
800 static void bnx2x_fw_dump(struct bnx2x
*bp
)
802 bnx2x_fw_dump_lvl(bp
, KERN_ERR
);
805 void bnx2x_panic_dump(struct bnx2x
*bp
)
809 struct hc_sp_status_block_data sp_sb_data
;
810 int func
= BP_FUNC(bp
);
811 #ifdef BNX2X_STOP_ON_ERROR
812 u16 start
= 0, end
= 0;
816 bp
->stats_state
= STATS_STATE_DISABLED
;
817 bp
->eth_stats
.unrecoverable_error
++;
818 DP(BNX2X_MSG_STATS
, "stats_state - DISABLED\n");
820 BNX2X_ERR("begin crash dump -----------------\n");
824 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
825 bp
->def_idx
, bp
->def_att_idx
, bp
->attn_state
,
826 bp
->spq_prod_idx
, bp
->stats_counter
);
827 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
828 bp
->def_status_blk
->atten_status_block
.attn_bits
,
829 bp
->def_status_blk
->atten_status_block
.attn_bits_ack
,
830 bp
->def_status_blk
->atten_status_block
.status_block_id
,
831 bp
->def_status_blk
->atten_status_block
.attn_bits_index
);
833 for (i
= 0; i
< HC_SP_SB_MAX_INDICES
; i
++)
835 bp
->def_status_blk
->sp_sb
.index_values
[i
],
836 (i
== HC_SP_SB_MAX_INDICES
- 1) ? ") " : " ");
838 for (i
= 0; i
< sizeof(struct hc_sp_status_block_data
)/sizeof(u32
); i
++)
839 *((u32
*)&sp_sb_data
+ i
) = REG_RD(bp
, BAR_CSTRORM_INTMEM
+
840 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
) +
843 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
844 sp_sb_data
.igu_sb_id
,
845 sp_sb_data
.igu_seg_id
,
846 sp_sb_data
.p_func
.pf_id
,
847 sp_sb_data
.p_func
.vnic_id
,
848 sp_sb_data
.p_func
.vf_id
,
849 sp_sb_data
.p_func
.vf_valid
,
853 for_each_eth_queue(bp
, i
) {
854 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
856 struct hc_status_block_data_e2 sb_data_e2
;
857 struct hc_status_block_data_e1x sb_data_e1x
;
858 struct hc_status_block_sm
*hc_sm_p
=
860 sb_data_e1x
.common
.state_machine
:
861 sb_data_e2
.common
.state_machine
;
862 struct hc_index_data
*hc_index_p
=
864 sb_data_e1x
.index_data
:
865 sb_data_e2
.index_data
;
868 struct bnx2x_fp_txdata txdata
;
871 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
872 i
, fp
->rx_bd_prod
, fp
->rx_bd_cons
,
874 fp
->rx_comp_cons
, le16_to_cpu(*fp
->rx_cons_sb
));
875 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
876 fp
->rx_sge_prod
, fp
->last_max_sge
,
877 le16_to_cpu(fp
->fp_hc_idx
));
880 for_each_cos_in_tx_queue(fp
, cos
)
882 txdata
= *fp
->txdata_ptr
[cos
];
883 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
884 i
, txdata
.tx_pkt_prod
,
885 txdata
.tx_pkt_cons
, txdata
.tx_bd_prod
,
887 le16_to_cpu(*txdata
.tx_cons_sb
));
890 loop
= CHIP_IS_E1x(bp
) ?
891 HC_SB_MAX_INDICES_E1X
: HC_SB_MAX_INDICES_E2
;
898 BNX2X_ERR(" run indexes (");
899 for (j
= 0; j
< HC_SB_MAX_SM
; j
++)
901 fp
->sb_running_index
[j
],
902 (j
== HC_SB_MAX_SM
- 1) ? ")" : " ");
904 BNX2X_ERR(" indexes (");
905 for (j
= 0; j
< loop
; j
++)
907 fp
->sb_index_values
[j
],
908 (j
== loop
- 1) ? ")" : " ");
910 data_size
= CHIP_IS_E1x(bp
) ?
911 sizeof(struct hc_status_block_data_e1x
) :
912 sizeof(struct hc_status_block_data_e2
);
913 data_size
/= sizeof(u32
);
914 sb_data_p
= CHIP_IS_E1x(bp
) ?
915 (u32
*)&sb_data_e1x
:
917 /* copy sb data in here */
918 for (j
= 0; j
< data_size
; j
++)
919 *(sb_data_p
+ j
) = REG_RD(bp
, BAR_CSTRORM_INTMEM
+
920 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp
->fw_sb_id
) +
923 if (!CHIP_IS_E1x(bp
)) {
924 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
925 sb_data_e2
.common
.p_func
.pf_id
,
926 sb_data_e2
.common
.p_func
.vf_id
,
927 sb_data_e2
.common
.p_func
.vf_valid
,
928 sb_data_e2
.common
.p_func
.vnic_id
,
929 sb_data_e2
.common
.same_igu_sb_1b
,
930 sb_data_e2
.common
.state
);
932 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
933 sb_data_e1x
.common
.p_func
.pf_id
,
934 sb_data_e1x
.common
.p_func
.vf_id
,
935 sb_data_e1x
.common
.p_func
.vf_valid
,
936 sb_data_e1x
.common
.p_func
.vnic_id
,
937 sb_data_e1x
.common
.same_igu_sb_1b
,
938 sb_data_e1x
.common
.state
);
942 for (j
= 0; j
< HC_SB_MAX_SM
; j
++) {
943 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
944 j
, hc_sm_p
[j
].__flags
,
945 hc_sm_p
[j
].igu_sb_id
,
946 hc_sm_p
[j
].igu_seg_id
,
947 hc_sm_p
[j
].time_to_expire
,
948 hc_sm_p
[j
].timer_value
);
952 for (j
= 0; j
< loop
; j
++) {
953 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j
,
955 hc_index_p
[j
].timeout
);
959 #ifdef BNX2X_STOP_ON_ERROR
962 for_each_valid_rx_queue(bp
, i
) {
963 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
965 start
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) - 10);
966 end
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) + 503);
967 for (j
= start
; j
!= end
; j
= RX_BD(j
+ 1)) {
968 u32
*rx_bd
= (u32
*)&fp
->rx_desc_ring
[j
];
969 struct sw_rx_bd
*sw_bd
= &fp
->rx_buf_ring
[j
];
971 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
972 i
, j
, rx_bd
[1], rx_bd
[0], sw_bd
->data
);
975 start
= RX_SGE(fp
->rx_sge_prod
);
976 end
= RX_SGE(fp
->last_max_sge
);
977 for (j
= start
; j
!= end
; j
= RX_SGE(j
+ 1)) {
978 u32
*rx_sge
= (u32
*)&fp
->rx_sge_ring
[j
];
979 struct sw_rx_page
*sw_page
= &fp
->rx_page_ring
[j
];
981 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
982 i
, j
, rx_sge
[1], rx_sge
[0], sw_page
->page
);
985 start
= RCQ_BD(fp
->rx_comp_cons
- 10);
986 end
= RCQ_BD(fp
->rx_comp_cons
+ 503);
987 for (j
= start
; j
!= end
; j
= RCQ_BD(j
+ 1)) {
988 u32
*cqe
= (u32
*)&fp
->rx_comp_ring
[j
];
990 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
991 i
, j
, cqe
[0], cqe
[1], cqe
[2], cqe
[3]);
996 for_each_valid_tx_queue(bp
, i
) {
997 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
998 for_each_cos_in_tx_queue(fp
, cos
) {
999 struct bnx2x_fp_txdata
*txdata
= fp
->txdata_ptr
[cos
];
1001 start
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) - 10);
1002 end
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) + 245);
1003 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
1004 struct sw_tx_bd
*sw_bd
=
1005 &txdata
->tx_buf_ring
[j
];
1007 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1008 i
, cos
, j
, sw_bd
->skb
,
1012 start
= TX_BD(txdata
->tx_bd_cons
- 10);
1013 end
= TX_BD(txdata
->tx_bd_cons
+ 254);
1014 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
1015 u32
*tx_bd
= (u32
*)&txdata
->tx_desc_ring
[j
];
1017 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1018 i
, cos
, j
, tx_bd
[0], tx_bd
[1],
1019 tx_bd
[2], tx_bd
[3]);
1025 bnx2x_mc_assert(bp
);
1026 BNX2X_ERR("end crash dump -----------------\n");
1030 * FLR Support for E2
1032 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1035 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1036 #define FLR_WAIT_INTERVAL 50 /* usec */
1037 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1039 struct pbf_pN_buf_regs
{
1046 struct pbf_pN_cmd_regs
{
1052 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x
*bp
,
1053 struct pbf_pN_buf_regs
*regs
,
1056 u32 init_crd
, crd
, crd_start
, crd_freed
, crd_freed_start
;
1057 u32 cur_cnt
= poll_count
;
1059 crd_freed
= crd_freed_start
= REG_RD(bp
, regs
->crd_freed
);
1060 crd
= crd_start
= REG_RD(bp
, regs
->crd
);
1061 init_crd
= REG_RD(bp
, regs
->init_crd
);
1063 DP(BNX2X_MSG_SP
, "INIT CREDIT[%d] : %x\n", regs
->pN
, init_crd
);
1064 DP(BNX2X_MSG_SP
, "CREDIT[%d] : s:%x\n", regs
->pN
, crd
);
1065 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: s:%x\n", regs
->pN
, crd_freed
);
1067 while ((crd
!= init_crd
) && ((u32
)SUB_S32(crd_freed
, crd_freed_start
) <
1068 (init_crd
- crd_start
))) {
1070 udelay(FLR_WAIT_INTERVAL
);
1071 crd
= REG_RD(bp
, regs
->crd
);
1072 crd_freed
= REG_RD(bp
, regs
->crd_freed
);
1074 DP(BNX2X_MSG_SP
, "PBF tx buffer[%d] timed out\n",
1076 DP(BNX2X_MSG_SP
, "CREDIT[%d] : c:%x\n",
1078 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: c:%x\n",
1079 regs
->pN
, crd_freed
);
1083 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1084 poll_count
-cur_cnt
, FLR_WAIT_INTERVAL
, regs
->pN
);
1087 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x
*bp
,
1088 struct pbf_pN_cmd_regs
*regs
,
1091 u32 occup
, to_free
, freed
, freed_start
;
1092 u32 cur_cnt
= poll_count
;
1094 occup
= to_free
= REG_RD(bp
, regs
->lines_occup
);
1095 freed
= freed_start
= REG_RD(bp
, regs
->lines_freed
);
1097 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n", regs
->pN
, occup
);
1098 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n", regs
->pN
, freed
);
1100 while (occup
&& ((u32
)SUB_S32(freed
, freed_start
) < to_free
)) {
1102 udelay(FLR_WAIT_INTERVAL
);
1103 occup
= REG_RD(bp
, regs
->lines_occup
);
1104 freed
= REG_RD(bp
, regs
->lines_freed
);
1106 DP(BNX2X_MSG_SP
, "PBF cmd queue[%d] timed out\n",
1108 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n",
1110 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n",
1115 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1116 poll_count
-cur_cnt
, FLR_WAIT_INTERVAL
, regs
->pN
);
1119 static u32
bnx2x_flr_clnup_reg_poll(struct bnx2x
*bp
, u32 reg
,
1120 u32 expected
, u32 poll_count
)
1122 u32 cur_cnt
= poll_count
;
1125 while ((val
= REG_RD(bp
, reg
)) != expected
&& cur_cnt
--)
1126 udelay(FLR_WAIT_INTERVAL
);
1131 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x
*bp
, u32 reg
,
1132 char *msg
, u32 poll_cnt
)
1134 u32 val
= bnx2x_flr_clnup_reg_poll(bp
, reg
, 0, poll_cnt
);
1136 BNX2X_ERR("%s usage count=%d\n", msg
, val
);
1142 /* Common routines with VF FLR cleanup */
1143 u32
bnx2x_flr_clnup_poll_count(struct bnx2x
*bp
)
1145 /* adjust polling timeout */
1146 if (CHIP_REV_IS_EMUL(bp
))
1147 return FLR_POLL_CNT
* 2000;
1149 if (CHIP_REV_IS_FPGA(bp
))
1150 return FLR_POLL_CNT
* 120;
1152 return FLR_POLL_CNT
;
1155 void bnx2x_tx_hw_flushed(struct bnx2x
*bp
, u32 poll_count
)
1157 struct pbf_pN_cmd_regs cmd_regs
[] = {
1158 {0, (CHIP_IS_E3B0(bp
)) ?
1159 PBF_REG_TQ_OCCUPANCY_Q0
:
1160 PBF_REG_P0_TQ_OCCUPANCY
,
1161 (CHIP_IS_E3B0(bp
)) ?
1162 PBF_REG_TQ_LINES_FREED_CNT_Q0
:
1163 PBF_REG_P0_TQ_LINES_FREED_CNT
},
1164 {1, (CHIP_IS_E3B0(bp
)) ?
1165 PBF_REG_TQ_OCCUPANCY_Q1
:
1166 PBF_REG_P1_TQ_OCCUPANCY
,
1167 (CHIP_IS_E3B0(bp
)) ?
1168 PBF_REG_TQ_LINES_FREED_CNT_Q1
:
1169 PBF_REG_P1_TQ_LINES_FREED_CNT
},
1170 {4, (CHIP_IS_E3B0(bp
)) ?
1171 PBF_REG_TQ_OCCUPANCY_LB_Q
:
1172 PBF_REG_P4_TQ_OCCUPANCY
,
1173 (CHIP_IS_E3B0(bp
)) ?
1174 PBF_REG_TQ_LINES_FREED_CNT_LB_Q
:
1175 PBF_REG_P4_TQ_LINES_FREED_CNT
}
1178 struct pbf_pN_buf_regs buf_regs
[] = {
1179 {0, (CHIP_IS_E3B0(bp
)) ?
1180 PBF_REG_INIT_CRD_Q0
:
1181 PBF_REG_P0_INIT_CRD
,
1182 (CHIP_IS_E3B0(bp
)) ?
1185 (CHIP_IS_E3B0(bp
)) ?
1186 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0
:
1187 PBF_REG_P0_INTERNAL_CRD_FREED_CNT
},
1188 {1, (CHIP_IS_E3B0(bp
)) ?
1189 PBF_REG_INIT_CRD_Q1
:
1190 PBF_REG_P1_INIT_CRD
,
1191 (CHIP_IS_E3B0(bp
)) ?
1194 (CHIP_IS_E3B0(bp
)) ?
1195 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1
:
1196 PBF_REG_P1_INTERNAL_CRD_FREED_CNT
},
1197 {4, (CHIP_IS_E3B0(bp
)) ?
1198 PBF_REG_INIT_CRD_LB_Q
:
1199 PBF_REG_P4_INIT_CRD
,
1200 (CHIP_IS_E3B0(bp
)) ?
1201 PBF_REG_CREDIT_LB_Q
:
1203 (CHIP_IS_E3B0(bp
)) ?
1204 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q
:
1205 PBF_REG_P4_INTERNAL_CRD_FREED_CNT
},
1210 /* Verify the command queues are flushed P0, P1, P4 */
1211 for (i
= 0; i
< ARRAY_SIZE(cmd_regs
); i
++)
1212 bnx2x_pbf_pN_cmd_flushed(bp
, &cmd_regs
[i
], poll_count
);
1215 /* Verify the transmission buffers are flushed P0, P1, P4 */
1216 for (i
= 0; i
< ARRAY_SIZE(buf_regs
); i
++)
1217 bnx2x_pbf_pN_buf_flushed(bp
, &buf_regs
[i
], poll_count
);
1220 #define OP_GEN_PARAM(param) \
1221 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1223 #define OP_GEN_TYPE(type) \
1224 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1226 #define OP_GEN_AGG_VECT(index) \
1227 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1230 int bnx2x_send_final_clnup(struct bnx2x
*bp
, u8 clnup_func
, u32 poll_cnt
)
1232 struct sdm_op_gen op_gen
= {0};
1234 u32 comp_addr
= BAR_CSTRORM_INTMEM
+
1235 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func
);
1238 if (REG_RD(bp
, comp_addr
)) {
1239 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1243 op_gen
.command
|= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX
);
1244 op_gen
.command
|= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE
);
1245 op_gen
.command
|= OP_GEN_AGG_VECT(clnup_func
);
1246 op_gen
.command
|= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT
;
1248 DP(BNX2X_MSG_SP
, "sending FW Final cleanup\n");
1249 REG_WR(bp
, XSDM_REG_OPERATION_GEN
, op_gen
.command
);
1251 if (bnx2x_flr_clnup_reg_poll(bp
, comp_addr
, 1, poll_cnt
) != 1) {
1252 BNX2X_ERR("FW final cleanup did not succeed\n");
1253 DP(BNX2X_MSG_SP
, "At timeout completion address contained %x\n",
1254 (REG_RD(bp
, comp_addr
)));
1258 /* Zero completion for nxt FLR */
1259 REG_WR(bp
, comp_addr
, 0);
1264 u8
bnx2x_is_pcie_pending(struct pci_dev
*dev
)
1268 pcie_capability_read_word(dev
, PCI_EXP_DEVSTA
, &status
);
1269 return status
& PCI_EXP_DEVSTA_TRPND
;
1272 /* PF FLR specific routines
1274 static int bnx2x_poll_hw_usage_counters(struct bnx2x
*bp
, u32 poll_cnt
)
1277 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1278 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1279 CFC_REG_NUM_LCIDS_INSIDE_PF
,
1280 "CFC PF usage counter timed out",
1285 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1286 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1287 DORQ_REG_PF_USAGE_CNT
,
1288 "DQ PF usage counter timed out",
1292 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1293 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1294 QM_REG_PF_USG_CNT_0
+ 4*BP_FUNC(bp
),
1295 "QM PF usage counter timed out",
1299 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1300 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1301 TM_REG_LIN0_VNIC_UC
+ 4*BP_PORT(bp
),
1302 "Timers VNIC usage counter timed out",
1305 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1306 TM_REG_LIN0_NUM_SCANS
+ 4*BP_PORT(bp
),
1307 "Timers NUM_SCANS usage counter timed out",
1311 /* Wait DMAE PF usage counter to zero */
1312 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1313 dmae_reg_go_c
[INIT_DMAE_C(bp
)],
1314 "DMAE dommand register timed out",
1321 static void bnx2x_hw_enable_status(struct bnx2x
*bp
)
1325 val
= REG_RD(bp
, CFC_REG_WEAK_ENABLE_PF
);
1326 DP(BNX2X_MSG_SP
, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val
);
1328 val
= REG_RD(bp
, PBF_REG_DISABLE_PF
);
1329 DP(BNX2X_MSG_SP
, "PBF_REG_DISABLE_PF is 0x%x\n", val
);
1331 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSI_EN
);
1332 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val
);
1334 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_EN
);
1335 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val
);
1337 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_FUNC_MASK
);
1338 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val
);
1340 val
= REG_RD(bp
, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR
);
1341 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val
);
1343 val
= REG_RD(bp
, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR
);
1344 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val
);
1346 val
= REG_RD(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
);
1347 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1351 static int bnx2x_pf_flr_clnup(struct bnx2x
*bp
)
1353 u32 poll_cnt
= bnx2x_flr_clnup_poll_count(bp
);
1355 DP(BNX2X_MSG_SP
, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp
));
1357 /* Re-enable PF target read access */
1358 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
1360 /* Poll HW usage counters */
1361 DP(BNX2X_MSG_SP
, "Polling usage counters\n");
1362 if (bnx2x_poll_hw_usage_counters(bp
, poll_cnt
))
1365 /* Zero the igu 'trailing edge' and 'leading edge' */
1367 /* Send the FW cleanup command */
1368 if (bnx2x_send_final_clnup(bp
, (u8
)BP_FUNC(bp
), poll_cnt
))
1373 /* Verify TX hw is flushed */
1374 bnx2x_tx_hw_flushed(bp
, poll_cnt
);
1376 /* Wait 100ms (not adjusted according to platform) */
1379 /* Verify no pending pci transactions */
1380 if (bnx2x_is_pcie_pending(bp
->pdev
))
1381 BNX2X_ERR("PCIE Transactions still pending\n");
1384 bnx2x_hw_enable_status(bp
);
1387 * Master enable - Due to WB DMAE writes performed before this
1388 * register is re-initialized as part of the regular function init
1390 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
1395 static void bnx2x_hc_int_enable(struct bnx2x
*bp
)
1397 int port
= BP_PORT(bp
);
1398 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
1399 u32 val
= REG_RD(bp
, addr
);
1400 bool msix
= (bp
->flags
& USING_MSIX_FLAG
) ? true : false;
1401 bool single_msix
= (bp
->flags
& USING_SINGLE_MSIX_FLAG
) ? true : false;
1402 bool msi
= (bp
->flags
& USING_MSI_FLAG
) ? true : false;
1405 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1406 HC_CONFIG_0_REG_INT_LINE_EN_0
);
1407 val
|= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1408 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1410 val
|= HC_CONFIG_0_REG_SINGLE_ISR_EN_0
;
1412 val
&= ~HC_CONFIG_0_REG_INT_LINE_EN_0
;
1413 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1414 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1415 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1417 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1418 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1419 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1420 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1422 if (!CHIP_IS_E1(bp
)) {
1424 "write %x to HC %d (addr 0x%x)\n", val
, port
, addr
);
1426 REG_WR(bp
, addr
, val
);
1428 val
&= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
;
1433 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0x1FFFF);
1436 "write %x to HC %d (addr 0x%x) mode %s\n", val
, port
, addr
,
1437 (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1439 REG_WR(bp
, addr
, val
);
1441 * Ensure that HC_CONFIG is written before leading/trailing edge config
1446 if (!CHIP_IS_E1(bp
)) {
1447 /* init leading/trailing edge */
1449 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1451 /* enable nig and gpio3 attention */
1456 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
1457 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
1460 /* Make sure that interrupts are indeed enabled from here on */
1464 static void bnx2x_igu_int_enable(struct bnx2x
*bp
)
1467 bool msix
= (bp
->flags
& USING_MSIX_FLAG
) ? true : false;
1468 bool single_msix
= (bp
->flags
& USING_SINGLE_MSIX_FLAG
) ? true : false;
1469 bool msi
= (bp
->flags
& USING_MSI_FLAG
) ? true : false;
1471 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
1474 val
&= ~(IGU_PF_CONF_INT_LINE_EN
|
1475 IGU_PF_CONF_SINGLE_ISR_EN
);
1476 val
|= (IGU_PF_CONF_FUNC_EN
|
1477 IGU_PF_CONF_MSI_MSIX_EN
|
1478 IGU_PF_CONF_ATTN_BIT_EN
);
1481 val
|= IGU_PF_CONF_SINGLE_ISR_EN
;
1483 val
&= ~IGU_PF_CONF_INT_LINE_EN
;
1484 val
|= (IGU_PF_CONF_FUNC_EN
|
1485 IGU_PF_CONF_MSI_MSIX_EN
|
1486 IGU_PF_CONF_ATTN_BIT_EN
|
1487 IGU_PF_CONF_SINGLE_ISR_EN
);
1489 val
&= ~IGU_PF_CONF_MSI_MSIX_EN
;
1490 val
|= (IGU_PF_CONF_FUNC_EN
|
1491 IGU_PF_CONF_INT_LINE_EN
|
1492 IGU_PF_CONF_ATTN_BIT_EN
|
1493 IGU_PF_CONF_SINGLE_ISR_EN
);
1496 DP(NETIF_MSG_IFUP
, "write 0x%x to IGU mode %s\n",
1497 val
, (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1499 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1501 if (val
& IGU_PF_CONF_INT_LINE_EN
)
1502 pci_intx(bp
->pdev
, true);
1506 /* init leading/trailing edge */
1508 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1510 /* enable nig and gpio3 attention */
1515 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
1516 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
1518 /* Make sure that interrupts are indeed enabled from here on */
1522 void bnx2x_int_enable(struct bnx2x
*bp
)
1524 if (bp
->common
.int_block
== INT_BLOCK_HC
)
1525 bnx2x_hc_int_enable(bp
);
1527 bnx2x_igu_int_enable(bp
);
1530 static void bnx2x_hc_int_disable(struct bnx2x
*bp
)
1532 int port
= BP_PORT(bp
);
1533 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
1534 u32 val
= REG_RD(bp
, addr
);
1537 * in E1 we must use only PCI configuration space to disable
1538 * MSI/MSIX capablility
1539 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1541 if (CHIP_IS_E1(bp
)) {
1542 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1543 * Use mask register to prevent from HC sending interrupts
1544 * after we exit the function
1546 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0);
1548 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1549 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1550 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1552 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1553 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1554 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1555 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1557 DP(NETIF_MSG_IFDOWN
,
1558 "write %x to HC %d (addr 0x%x)\n",
1561 /* flush all outstanding writes */
1564 REG_WR(bp
, addr
, val
);
1565 if (REG_RD(bp
, addr
) != val
)
1566 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1569 static void bnx2x_igu_int_disable(struct bnx2x
*bp
)
1571 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
1573 val
&= ~(IGU_PF_CONF_MSI_MSIX_EN
|
1574 IGU_PF_CONF_INT_LINE_EN
|
1575 IGU_PF_CONF_ATTN_BIT_EN
);
1577 DP(NETIF_MSG_IFDOWN
, "write %x to IGU\n", val
);
1579 /* flush all outstanding writes */
1582 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1583 if (REG_RD(bp
, IGU_REG_PF_CONFIGURATION
) != val
)
1584 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1587 static void bnx2x_int_disable(struct bnx2x
*bp
)
1589 if (bp
->common
.int_block
== INT_BLOCK_HC
)
1590 bnx2x_hc_int_disable(bp
);
1592 bnx2x_igu_int_disable(bp
);
1595 void bnx2x_int_disable_sync(struct bnx2x
*bp
, int disable_hw
)
1597 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
1601 /* prevent the HW from sending interrupts */
1602 bnx2x_int_disable(bp
);
1604 /* make sure all ISRs are done */
1606 synchronize_irq(bp
->msix_table
[0].vector
);
1608 if (CNIC_SUPPORT(bp
))
1610 for_each_eth_queue(bp
, i
)
1611 synchronize_irq(bp
->msix_table
[offset
++].vector
);
1613 synchronize_irq(bp
->pdev
->irq
);
1615 /* make sure sp_task is not running */
1616 cancel_delayed_work(&bp
->sp_task
);
1617 cancel_delayed_work(&bp
->period_task
);
1618 flush_workqueue(bnx2x_wq
);
1624 * General service functions
1627 /* Return true if succeeded to acquire the lock */
1628 static bool bnx2x_trylock_hw_lock(struct bnx2x
*bp
, u32 resource
)
1631 u32 resource_bit
= (1 << resource
);
1632 int func
= BP_FUNC(bp
);
1633 u32 hw_lock_control_reg
;
1635 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1636 "Trying to take a lock on resource %d\n", resource
);
1638 /* Validating that the resource is within range */
1639 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1640 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1641 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1642 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1647 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1649 hw_lock_control_reg
=
1650 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1652 /* Try to acquire the lock */
1653 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
1654 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1655 if (lock_status
& resource_bit
)
1658 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1659 "Failed to get a lock on resource %d\n", resource
);
1664 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1666 * @bp: driver handle
1668 * Returns the recovery leader resource id according to the engine this function
1669 * belongs to. Currently only only 2 engines is supported.
1671 static int bnx2x_get_leader_lock_resource(struct bnx2x
*bp
)
1674 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1
;
1676 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0
;
1680 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1682 * @bp: driver handle
1684 * Tries to aquire a leader lock for current engine.
1686 static bool bnx2x_trylock_leader_lock(struct bnx2x
*bp
)
1688 return bnx2x_trylock_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
1691 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
);
1693 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1694 static int bnx2x_schedule_sp_task(struct bnx2x
*bp
)
1696 /* Set the interrupt occurred bit for the sp-task to recognize it
1697 * must ack the interrupt and transition according to the IGU
1700 atomic_set(&bp
->interrupt_occurred
, 1);
1702 /* The sp_task must execute only after this bit
1703 * is set, otherwise we will get out of sync and miss all
1704 * further interrupts. Hence, the barrier.
1708 /* schedule sp_task to workqueue */
1709 return queue_delayed_work(bnx2x_wq
, &bp
->sp_task
, 0);
1712 void bnx2x_sp_event(struct bnx2x_fastpath
*fp
, union eth_rx_cqe
*rr_cqe
)
1714 struct bnx2x
*bp
= fp
->bp
;
1715 int cid
= SW_CID(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1716 int command
= CQE_CMD(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1717 enum bnx2x_queue_cmd drv_cmd
= BNX2X_Q_CMD_MAX
;
1718 struct bnx2x_queue_sp_obj
*q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
1721 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1722 fp
->index
, cid
, command
, bp
->state
,
1723 rr_cqe
->ramrod_cqe
.ramrod_type
);
1725 /* If cid is within VF range, replace the slowpath object with the
1726 * one corresponding to this VF
1728 if (cid
>= BNX2X_FIRST_VF_CID
&&
1729 cid
< BNX2X_FIRST_VF_CID
+ BNX2X_VF_CIDS
)
1730 bnx2x_iov_set_queue_sp_obj(bp
, cid
, &q_obj
);
1733 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE
):
1734 DP(BNX2X_MSG_SP
, "got UPDATE ramrod. CID %d\n", cid
);
1735 drv_cmd
= BNX2X_Q_CMD_UPDATE
;
1738 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP
):
1739 DP(BNX2X_MSG_SP
, "got MULTI[%d] setup ramrod\n", cid
);
1740 drv_cmd
= BNX2X_Q_CMD_SETUP
;
1743 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP
):
1744 DP(BNX2X_MSG_SP
, "got MULTI[%d] tx-only setup ramrod\n", cid
);
1745 drv_cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
1748 case (RAMROD_CMD_ID_ETH_HALT
):
1749 DP(BNX2X_MSG_SP
, "got MULTI[%d] halt ramrod\n", cid
);
1750 drv_cmd
= BNX2X_Q_CMD_HALT
;
1753 case (RAMROD_CMD_ID_ETH_TERMINATE
):
1754 DP(BNX2X_MSG_SP
, "got MULTI[%d] teminate ramrod\n", cid
);
1755 drv_cmd
= BNX2X_Q_CMD_TERMINATE
;
1758 case (RAMROD_CMD_ID_ETH_EMPTY
):
1759 DP(BNX2X_MSG_SP
, "got MULTI[%d] empty ramrod\n", cid
);
1760 drv_cmd
= BNX2X_Q_CMD_EMPTY
;
1764 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1765 command
, fp
->index
);
1769 if ((drv_cmd
!= BNX2X_Q_CMD_MAX
) &&
1770 q_obj
->complete_cmd(bp
, q_obj
, drv_cmd
))
1771 /* q_obj->complete_cmd() failure means that this was
1772 * an unexpected completion.
1774 * In this case we don't want to increase the bp->spq_left
1775 * because apparently we haven't sent this command the first
1778 #ifdef BNX2X_STOP_ON_ERROR
1783 /* SRIOV: reschedule any 'in_progress' operations */
1784 bnx2x_iov_sp_event(bp
, cid
, true);
1786 smp_mb__before_atomic_inc();
1787 atomic_inc(&bp
->cq_spq_left
);
1788 /* push the change in bp->spq_left and towards the memory */
1789 smp_mb__after_atomic_inc();
1791 DP(BNX2X_MSG_SP
, "bp->cq_spq_left %x\n", atomic_read(&bp
->cq_spq_left
));
1793 if ((drv_cmd
== BNX2X_Q_CMD_UPDATE
) && (IS_FCOE_FP(fp
)) &&
1794 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
, &bp
->sp_state
))) {
1795 /* if Q update ramrod is completed for last Q in AFEX vif set
1796 * flow, then ACK MCP at the end
1798 * mark pending ACK to MCP bit.
1799 * prevent case that both bits are cleared.
1800 * At the end of load/unload driver checks that
1801 * sp_state is cleaerd, and this order prevents
1804 smp_mb__before_clear_bit();
1805 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
, &bp
->sp_state
);
1807 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
, &bp
->sp_state
);
1808 smp_mb__after_clear_bit();
1810 /* schedule the sp task as mcp ack is required */
1811 bnx2x_schedule_sp_task(bp
);
1817 irqreturn_t
bnx2x_interrupt(int irq
, void *dev_instance
)
1819 struct bnx2x
*bp
= netdev_priv(dev_instance
);
1820 u16 status
= bnx2x_ack_int(bp
);
1825 /* Return here if interrupt is shared and it's not for us */
1826 if (unlikely(status
== 0)) {
1827 DP(NETIF_MSG_INTR
, "not our interrupt!\n");
1830 DP(NETIF_MSG_INTR
, "got an interrupt status 0x%x\n", status
);
1832 #ifdef BNX2X_STOP_ON_ERROR
1833 if (unlikely(bp
->panic
))
1837 for_each_eth_queue(bp
, i
) {
1838 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1840 mask
= 0x2 << (fp
->index
+ CNIC_SUPPORT(bp
));
1841 if (status
& mask
) {
1842 /* Handle Rx or Tx according to SB id */
1843 prefetch(fp
->rx_cons_sb
);
1844 for_each_cos_in_tx_queue(fp
, cos
)
1845 prefetch(fp
->txdata_ptr
[cos
]->tx_cons_sb
);
1846 prefetch(&fp
->sb_running_index
[SM_RX_ID
]);
1847 napi_schedule(&bnx2x_fp(bp
, fp
->index
, napi
));
1852 if (CNIC_SUPPORT(bp
)) {
1854 if (status
& (mask
| 0x1)) {
1855 struct cnic_ops
*c_ops
= NULL
;
1857 if (likely(bp
->state
== BNX2X_STATE_OPEN
)) {
1859 c_ops
= rcu_dereference(bp
->cnic_ops
);
1861 c_ops
->cnic_handler(bp
->cnic_data
,
1870 if (unlikely(status
& 0x1)) {
1872 /* schedule sp task to perform default status block work, ack
1873 * attentions and enable interrupts.
1875 bnx2x_schedule_sp_task(bp
);
1882 if (unlikely(status
))
1883 DP(NETIF_MSG_INTR
, "got an unknown interrupt! (status 0x%x)\n",
1892 * General service functions
1895 int bnx2x_acquire_hw_lock(struct bnx2x
*bp
, u32 resource
)
1898 u32 resource_bit
= (1 << resource
);
1899 int func
= BP_FUNC(bp
);
1900 u32 hw_lock_control_reg
;
1903 /* Validating that the resource is within range */
1904 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1905 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1906 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1911 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1913 hw_lock_control_reg
=
1914 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1917 /* Validating that the resource is not already taken */
1918 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1919 if (lock_status
& resource_bit
) {
1920 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1921 lock_status
, resource_bit
);
1925 /* Try for 5 second every 5ms */
1926 for (cnt
= 0; cnt
< 1000; cnt
++) {
1927 /* Try to acquire the lock */
1928 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
1929 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1930 if (lock_status
& resource_bit
)
1935 BNX2X_ERR("Timeout\n");
1939 int bnx2x_release_leader_lock(struct bnx2x
*bp
)
1941 return bnx2x_release_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
1944 int bnx2x_release_hw_lock(struct bnx2x
*bp
, u32 resource
)
1947 u32 resource_bit
= (1 << resource
);
1948 int func
= BP_FUNC(bp
);
1949 u32 hw_lock_control_reg
;
1951 /* Validating that the resource is within range */
1952 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1953 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1954 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1959 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1961 hw_lock_control_reg
=
1962 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1965 /* Validating that the resource is currently taken */
1966 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1967 if (!(lock_status
& resource_bit
)) {
1968 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1969 lock_status
, resource_bit
);
1973 REG_WR(bp
, hw_lock_control_reg
, resource_bit
);
1978 int bnx2x_get_gpio(struct bnx2x
*bp
, int gpio_num
, u8 port
)
1980 /* The GPIO should be swapped if swap register is set and active */
1981 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
1982 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
1983 int gpio_shift
= gpio_num
+
1984 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
1985 u32 gpio_mask
= (1 << gpio_shift
);
1989 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
1990 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
1994 /* read GPIO value */
1995 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
1997 /* get the requested pin value */
1998 if ((gpio_reg
& gpio_mask
) == gpio_mask
)
2003 DP(NETIF_MSG_LINK
, "pin %d value 0x%x\n", gpio_num
, value
);
2008 int bnx2x_set_gpio(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
2010 /* The GPIO should be swapped if swap register is set and active */
2011 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2012 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2013 int gpio_shift
= gpio_num
+
2014 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2015 u32 gpio_mask
= (1 << gpio_shift
);
2018 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2019 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2023 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2024 /* read GPIO and mask except the float bits */
2025 gpio_reg
= (REG_RD(bp
, MISC_REG_GPIO
) & MISC_REGISTERS_GPIO_FLOAT
);
2028 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
2030 "Set GPIO %d (shift %d) -> output low\n",
2031 gpio_num
, gpio_shift
);
2032 /* clear FLOAT and set CLR */
2033 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2034 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_CLR_POS
);
2037 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
2039 "Set GPIO %d (shift %d) -> output high\n",
2040 gpio_num
, gpio_shift
);
2041 /* clear FLOAT and set SET */
2042 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2043 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_SET_POS
);
2046 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
2048 "Set GPIO %d (shift %d) -> input\n",
2049 gpio_num
, gpio_shift
);
2051 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2058 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
2059 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2064 int bnx2x_set_mult_gpio(struct bnx2x
*bp
, u8 pins
, u32 mode
)
2069 /* Any port swapping should be handled by caller. */
2071 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2072 /* read GPIO and mask except the float bits */
2073 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
2074 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2075 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
2076 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_SET_POS
);
2079 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
2080 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output low\n", pins
);
2082 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
2085 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
2086 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output high\n", pins
);
2088 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_SET_POS
);
2091 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
2092 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> input\n", pins
);
2094 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2098 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode
);
2104 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
2106 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2111 int bnx2x_set_gpio_int(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
2113 /* The GPIO should be swapped if swap register is set and active */
2114 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2115 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2116 int gpio_shift
= gpio_num
+
2117 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2118 u32 gpio_mask
= (1 << gpio_shift
);
2121 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2122 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2126 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2128 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO_INT
);
2131 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR
:
2133 "Clear GPIO INT %d (shift %d) -> output low\n",
2134 gpio_num
, gpio_shift
);
2135 /* clear SET and set CLR */
2136 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2137 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2140 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET
:
2142 "Set GPIO INT %d (shift %d) -> output high\n",
2143 gpio_num
, gpio_shift
);
2144 /* clear CLR and set SET */
2145 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2146 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2153 REG_WR(bp
, MISC_REG_GPIO_INT
, gpio_reg
);
2154 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2159 static int bnx2x_set_spio(struct bnx2x
*bp
, int spio
, u32 mode
)
2163 /* Only 2 SPIOs are configurable */
2164 if ((spio
!= MISC_SPIO_SPIO4
) && (spio
!= MISC_SPIO_SPIO5
)) {
2165 BNX2X_ERR("Invalid SPIO 0x%x\n", spio
);
2169 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2170 /* read SPIO and mask except the float bits */
2171 spio_reg
= (REG_RD(bp
, MISC_REG_SPIO
) & MISC_SPIO_FLOAT
);
2174 case MISC_SPIO_OUTPUT_LOW
:
2175 DP(NETIF_MSG_HW
, "Set SPIO 0x%x -> output low\n", spio
);
2176 /* clear FLOAT and set CLR */
2177 spio_reg
&= ~(spio
<< MISC_SPIO_FLOAT_POS
);
2178 spio_reg
|= (spio
<< MISC_SPIO_CLR_POS
);
2181 case MISC_SPIO_OUTPUT_HIGH
:
2182 DP(NETIF_MSG_HW
, "Set SPIO 0x%x -> output high\n", spio
);
2183 /* clear FLOAT and set SET */
2184 spio_reg
&= ~(spio
<< MISC_SPIO_FLOAT_POS
);
2185 spio_reg
|= (spio
<< MISC_SPIO_SET_POS
);
2188 case MISC_SPIO_INPUT_HI_Z
:
2189 DP(NETIF_MSG_HW
, "Set SPIO 0x%x -> input\n", spio
);
2191 spio_reg
|= (spio
<< MISC_SPIO_FLOAT_POS
);
2198 REG_WR(bp
, MISC_REG_SPIO
, spio_reg
);
2199 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2204 void bnx2x_calc_fc_adv(struct bnx2x
*bp
)
2206 u8 cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
2207 switch (bp
->link_vars
.ieee_fc
&
2208 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
) {
2209 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE
:
2210 bp
->port
.advertising
[cfg_idx
] &= ~(ADVERTISED_Asym_Pause
|
2214 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
:
2215 bp
->port
.advertising
[cfg_idx
] |= (ADVERTISED_Asym_Pause
|
2219 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
:
2220 bp
->port
.advertising
[cfg_idx
] |= ADVERTISED_Asym_Pause
;
2224 bp
->port
.advertising
[cfg_idx
] &= ~(ADVERTISED_Asym_Pause
|
2230 static void bnx2x_set_requested_fc(struct bnx2x
*bp
)
2232 /* Initialize link parameters structure variables
2233 * It is recommended to turn off RX FC for jumbo frames
2234 * for better performance
2236 if (CHIP_IS_E1x(bp
) && (bp
->dev
->mtu
> 5000))
2237 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_TX
;
2239 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_BOTH
;
2242 int bnx2x_initial_phy_init(struct bnx2x
*bp
, int load_mode
)
2244 int rc
, cfx_idx
= bnx2x_get_link_cfg_idx(bp
);
2245 u16 req_line_speed
= bp
->link_params
.req_line_speed
[cfx_idx
];
2247 if (!BP_NOMCP(bp
)) {
2248 bnx2x_set_requested_fc(bp
);
2249 bnx2x_acquire_phy_lock(bp
);
2251 if (load_mode
== LOAD_DIAG
) {
2252 struct link_params
*lp
= &bp
->link_params
;
2253 lp
->loopback_mode
= LOOPBACK_XGXS
;
2254 /* do PHY loopback at 10G speed, if possible */
2255 if (lp
->req_line_speed
[cfx_idx
] < SPEED_10000
) {
2256 if (lp
->speed_cap_mask
[cfx_idx
] &
2257 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
2258 lp
->req_line_speed
[cfx_idx
] =
2261 lp
->req_line_speed
[cfx_idx
] =
2266 if (load_mode
== LOAD_LOOPBACK_EXT
) {
2267 struct link_params
*lp
= &bp
->link_params
;
2268 lp
->loopback_mode
= LOOPBACK_EXT
;
2271 rc
= bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2273 bnx2x_release_phy_lock(bp
);
2275 bnx2x_calc_fc_adv(bp
);
2277 if (bp
->link_vars
.link_up
) {
2278 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2279 bnx2x_link_report(bp
);
2281 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2282 bp
->link_params
.req_line_speed
[cfx_idx
] = req_line_speed
;
2285 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2289 void bnx2x_link_set(struct bnx2x
*bp
)
2291 if (!BP_NOMCP(bp
)) {
2292 bnx2x_acquire_phy_lock(bp
);
2293 bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2294 bnx2x_release_phy_lock(bp
);
2296 bnx2x_calc_fc_adv(bp
);
2298 BNX2X_ERR("Bootcode is missing - can not set link\n");
2301 static void bnx2x__link_reset(struct bnx2x
*bp
)
2303 if (!BP_NOMCP(bp
)) {
2304 bnx2x_acquire_phy_lock(bp
);
2305 bnx2x_lfa_reset(&bp
->link_params
, &bp
->link_vars
);
2306 bnx2x_release_phy_lock(bp
);
2308 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2311 void bnx2x_force_link_reset(struct bnx2x
*bp
)
2313 bnx2x_acquire_phy_lock(bp
);
2314 bnx2x_link_reset(&bp
->link_params
, &bp
->link_vars
, 1);
2315 bnx2x_release_phy_lock(bp
);
2318 u8
bnx2x_link_test(struct bnx2x
*bp
, u8 is_serdes
)
2322 if (!BP_NOMCP(bp
)) {
2323 bnx2x_acquire_phy_lock(bp
);
2324 rc
= bnx2x_test_link(&bp
->link_params
, &bp
->link_vars
,
2326 bnx2x_release_phy_lock(bp
);
2328 BNX2X_ERR("Bootcode is missing - can not test link\n");
2334 /* Calculates the sum of vn_min_rates.
2335 It's needed for further normalizing of the min_rates.
2337 sum of vn_min_rates.
2339 0 - if all the min_rates are 0.
2340 In the later case fainess algorithm should be deactivated.
2341 If not all min_rates are zero then those that are zeroes will be set to 1.
2343 static void bnx2x_calc_vn_min(struct bnx2x
*bp
,
2344 struct cmng_init_input
*input
)
2349 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2350 u32 vn_cfg
= bp
->mf_config
[vn
];
2351 u32 vn_min_rate
= ((vn_cfg
& FUNC_MF_CFG_MIN_BW_MASK
) >>
2352 FUNC_MF_CFG_MIN_BW_SHIFT
) * 100;
2354 /* Skip hidden vns */
2355 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
)
2357 /* If min rate is zero - set it to 1 */
2358 else if (!vn_min_rate
)
2359 vn_min_rate
= DEF_MIN_RATE
;
2363 input
->vnic_min_rate
[vn
] = vn_min_rate
;
2366 /* if ETS or all min rates are zeros - disable fairness */
2367 if (BNX2X_IS_ETS_ENABLED(bp
)) {
2368 input
->flags
.cmng_enables
&=
2369 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2370 DP(NETIF_MSG_IFUP
, "Fairness will be disabled due to ETS\n");
2371 } else if (all_zero
) {
2372 input
->flags
.cmng_enables
&=
2373 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2375 "All MIN values are zeroes fairness will be disabled\n");
2377 input
->flags
.cmng_enables
|=
2378 CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2381 static void bnx2x_calc_vn_max(struct bnx2x
*bp
, int vn
,
2382 struct cmng_init_input
*input
)
2385 u32 vn_cfg
= bp
->mf_config
[vn
];
2387 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
)
2390 u32 maxCfg
= bnx2x_extract_max_cfg(bp
, vn_cfg
);
2393 /* maxCfg in percents of linkspeed */
2394 vn_max_rate
= (bp
->link_vars
.line_speed
* maxCfg
) / 100;
2395 } else /* SD modes */
2396 /* maxCfg is absolute in 100Mb units */
2397 vn_max_rate
= maxCfg
* 100;
2400 DP(NETIF_MSG_IFUP
, "vn %d: vn_max_rate %d\n", vn
, vn_max_rate
);
2402 input
->vnic_max_rate
[vn
] = vn_max_rate
;
2406 static int bnx2x_get_cmng_fns_mode(struct bnx2x
*bp
)
2408 if (CHIP_REV_IS_SLOW(bp
))
2409 return CMNG_FNS_NONE
;
2411 return CMNG_FNS_MINMAX
;
2413 return CMNG_FNS_NONE
;
2416 void bnx2x_read_mf_cfg(struct bnx2x
*bp
)
2418 int vn
, n
= (CHIP_MODE_IS_4_PORT(bp
) ? 2 : 1);
2421 return; /* what should be the default bvalue in this case */
2423 /* For 2 port configuration the absolute function number formula
2425 * abs_func = 2 * vn + BP_PORT + BP_PATH
2427 * and there are 4 functions per port
2429 * For 4 port configuration it is
2430 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2432 * and there are 2 functions per port
2434 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2435 int /*abs*/func
= n
* (2 * vn
+ BP_PORT(bp
)) + BP_PATH(bp
);
2437 if (func
>= E1H_FUNC_MAX
)
2441 MF_CFG_RD(bp
, func_mf_config
[func
].config
);
2443 if (bp
->mf_config
[BP_VN(bp
)] & FUNC_MF_CFG_FUNC_DISABLED
) {
2444 DP(NETIF_MSG_IFUP
, "mf_cfg function disabled\n");
2445 bp
->flags
|= MF_FUNC_DIS
;
2447 DP(NETIF_MSG_IFUP
, "mf_cfg function enabled\n");
2448 bp
->flags
&= ~MF_FUNC_DIS
;
2452 static void bnx2x_cmng_fns_init(struct bnx2x
*bp
, u8 read_cfg
, u8 cmng_type
)
2454 struct cmng_init_input input
;
2455 memset(&input
, 0, sizeof(struct cmng_init_input
));
2457 input
.port_rate
= bp
->link_vars
.line_speed
;
2459 if (cmng_type
== CMNG_FNS_MINMAX
) {
2462 /* read mf conf from shmem */
2464 bnx2x_read_mf_cfg(bp
);
2466 /* vn_weight_sum and enable fairness if not 0 */
2467 bnx2x_calc_vn_min(bp
, &input
);
2469 /* calculate and set min-max rate for each vn */
2471 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++)
2472 bnx2x_calc_vn_max(bp
, vn
, &input
);
2474 /* always enable rate shaping and fairness */
2475 input
.flags
.cmng_enables
|=
2476 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN
;
2478 bnx2x_init_cmng(&input
, &bp
->cmng
);
2482 /* rate shaping and fairness are disabled */
2484 "rate shaping and fairness are disabled\n");
2487 static void storm_memset_cmng(struct bnx2x
*bp
,
2488 struct cmng_init
*cmng
,
2492 size_t size
= sizeof(struct cmng_struct_per_port
);
2494 u32 addr
= BAR_XSTRORM_INTMEM
+
2495 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port
);
2497 __storm_memset_struct(bp
, addr
, size
, (u32
*)&cmng
->port
);
2499 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2500 int func
= func_by_vn(bp
, vn
);
2502 addr
= BAR_XSTRORM_INTMEM
+
2503 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func
);
2504 size
= sizeof(struct rate_shaping_vars_per_vn
);
2505 __storm_memset_struct(bp
, addr
, size
,
2506 (u32
*)&cmng
->vnic
.vnic_max_rate
[vn
]);
2508 addr
= BAR_XSTRORM_INTMEM
+
2509 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func
);
2510 size
= sizeof(struct fairness_vars_per_vn
);
2511 __storm_memset_struct(bp
, addr
, size
,
2512 (u32
*)&cmng
->vnic
.vnic_min_rate
[vn
]);
2516 /* This function is called upon link interrupt */
2517 static void bnx2x_link_attn(struct bnx2x
*bp
)
2519 /* Make sure that we are synced with the current statistics */
2520 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2522 bnx2x_link_update(&bp
->link_params
, &bp
->link_vars
);
2524 if (bp
->link_vars
.link_up
) {
2526 /* dropless flow control */
2527 if (!CHIP_IS_E1(bp
) && bp
->dropless_fc
) {
2528 int port
= BP_PORT(bp
);
2529 u32 pause_enabled
= 0;
2531 if (bp
->link_vars
.flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
2534 REG_WR(bp
, BAR_USTRORM_INTMEM
+
2535 USTORM_ETH_PAUSE_ENABLED_OFFSET(port
),
2539 if (bp
->link_vars
.mac_type
!= MAC_TYPE_EMAC
) {
2540 struct host_port_stats
*pstats
;
2542 pstats
= bnx2x_sp(bp
, port_stats
);
2543 /* reset old mac stats */
2544 memset(&(pstats
->mac_stx
[0]), 0,
2545 sizeof(struct mac_stx
));
2547 if (bp
->state
== BNX2X_STATE_OPEN
)
2548 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2551 if (bp
->link_vars
.link_up
&& bp
->link_vars
.line_speed
) {
2552 int cmng_fns
= bnx2x_get_cmng_fns_mode(bp
);
2554 if (cmng_fns
!= CMNG_FNS_NONE
) {
2555 bnx2x_cmng_fns_init(bp
, false, cmng_fns
);
2556 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
2558 /* rate shaping and fairness are disabled */
2560 "single function mode without fairness\n");
2563 __bnx2x_link_report(bp
);
2566 bnx2x_link_sync_notify(bp
);
2569 void bnx2x__link_status_update(struct bnx2x
*bp
)
2571 if (bp
->state
!= BNX2X_STATE_OPEN
)
2574 /* read updated dcb configuration */
2576 bnx2x_dcbx_pmf_update(bp
);
2577 bnx2x_link_status_update(&bp
->link_params
, &bp
->link_vars
);
2578 if (bp
->link_vars
.link_up
)
2579 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2581 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2582 /* indicate link status */
2583 bnx2x_link_report(bp
);
2586 bp
->port
.supported
[0] |= (SUPPORTED_10baseT_Half
|
2587 SUPPORTED_10baseT_Full
|
2588 SUPPORTED_100baseT_Half
|
2589 SUPPORTED_100baseT_Full
|
2590 SUPPORTED_1000baseT_Full
|
2591 SUPPORTED_2500baseX_Full
|
2592 SUPPORTED_10000baseT_Full
|
2597 SUPPORTED_Asym_Pause
);
2598 bp
->port
.advertising
[0] = bp
->port
.supported
[0];
2600 bp
->link_params
.bp
= bp
;
2601 bp
->link_params
.port
= BP_PORT(bp
);
2602 bp
->link_params
.req_duplex
[0] = DUPLEX_FULL
;
2603 bp
->link_params
.req_flow_ctrl
[0] = BNX2X_FLOW_CTRL_NONE
;
2604 bp
->link_params
.req_line_speed
[0] = SPEED_10000
;
2605 bp
->link_params
.speed_cap_mask
[0] = 0x7f0000;
2606 bp
->link_params
.switch_cfg
= SWITCH_CFG_10G
;
2607 bp
->link_vars
.mac_type
= MAC_TYPE_BMAC
;
2608 bp
->link_vars
.line_speed
= SPEED_10000
;
2609 bp
->link_vars
.link_status
=
2610 (LINK_STATUS_LINK_UP
|
2611 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
);
2612 bp
->link_vars
.link_up
= 1;
2613 bp
->link_vars
.duplex
= DUPLEX_FULL
;
2614 bp
->link_vars
.flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
2615 __bnx2x_link_report(bp
);
2616 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2620 static int bnx2x_afex_func_update(struct bnx2x
*bp
, u16 vifid
,
2621 u16 vlan_val
, u8 allowed_prio
)
2623 struct bnx2x_func_state_params func_params
= {0};
2624 struct bnx2x_func_afex_update_params
*f_update_params
=
2625 &func_params
.params
.afex_update
;
2627 func_params
.f_obj
= &bp
->func_obj
;
2628 func_params
.cmd
= BNX2X_F_CMD_AFEX_UPDATE
;
2630 /* no need to wait for RAMROD completion, so don't
2631 * set RAMROD_COMP_WAIT flag
2634 f_update_params
->vif_id
= vifid
;
2635 f_update_params
->afex_default_vlan
= vlan_val
;
2636 f_update_params
->allowed_priorities
= allowed_prio
;
2638 /* if ramrod can not be sent, response to MCP immediately */
2639 if (bnx2x_func_state_change(bp
, &func_params
) < 0)
2640 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_VIFSET_ACK
, 0);
2645 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x
*bp
, u8 cmd_type
,
2646 u16 vif_index
, u8 func_bit_map
)
2648 struct bnx2x_func_state_params func_params
= {0};
2649 struct bnx2x_func_afex_viflists_params
*update_params
=
2650 &func_params
.params
.afex_viflists
;
2654 /* validate only LIST_SET and LIST_GET are received from switch */
2655 if ((cmd_type
!= VIF_LIST_RULE_GET
) && (cmd_type
!= VIF_LIST_RULE_SET
))
2656 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2659 func_params
.f_obj
= &bp
->func_obj
;
2660 func_params
.cmd
= BNX2X_F_CMD_AFEX_VIFLISTS
;
2662 /* set parameters according to cmd_type */
2663 update_params
->afex_vif_list_command
= cmd_type
;
2664 update_params
->vif_list_index
= cpu_to_le16(vif_index
);
2665 update_params
->func_bit_map
=
2666 (cmd_type
== VIF_LIST_RULE_GET
) ? 0 : func_bit_map
;
2667 update_params
->func_to_clear
= 0;
2669 (cmd_type
== VIF_LIST_RULE_GET
) ?
2670 DRV_MSG_CODE_AFEX_LISTGET_ACK
:
2671 DRV_MSG_CODE_AFEX_LISTSET_ACK
;
2673 /* if ramrod can not be sent, respond to MCP immediately for
2674 * SET and GET requests (other are not triggered from MCP)
2676 rc
= bnx2x_func_state_change(bp
, &func_params
);
2678 bnx2x_fw_command(bp
, drv_msg_code
, 0);
2683 static void bnx2x_handle_afex_cmd(struct bnx2x
*bp
, u32 cmd
)
2685 struct afex_stats afex_stats
;
2686 u32 func
= BP_ABS_FUNC(bp
);
2693 u32 addr_to_write
, vifid
, addrs
, stats_type
, i
;
2695 if (cmd
& DRV_STATUS_AFEX_LISTGET_REQ
) {
2696 vifid
= SHMEM2_RD(bp
, afex_param1_to_driver
[BP_FW_MB_IDX(bp
)]);
2698 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid
);
2699 bnx2x_afex_handle_vif_list_cmd(bp
, VIF_LIST_RULE_GET
, vifid
, 0);
2702 if (cmd
& DRV_STATUS_AFEX_LISTSET_REQ
) {
2703 vifid
= SHMEM2_RD(bp
, afex_param1_to_driver
[BP_FW_MB_IDX(bp
)]);
2704 addrs
= SHMEM2_RD(bp
, afex_param2_to_driver
[BP_FW_MB_IDX(bp
)]);
2706 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2708 bnx2x_afex_handle_vif_list_cmd(bp
, VIF_LIST_RULE_SET
, vifid
,
2712 if (cmd
& DRV_STATUS_AFEX_STATSGET_REQ
) {
2713 addr_to_write
= SHMEM2_RD(bp
,
2714 afex_scratchpad_addr_to_write
[BP_FW_MB_IDX(bp
)]);
2715 stats_type
= SHMEM2_RD(bp
,
2716 afex_param1_to_driver
[BP_FW_MB_IDX(bp
)]);
2719 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2722 bnx2x_afex_collect_stats(bp
, (void *)&afex_stats
, stats_type
);
2724 /* write response to scratchpad, for MCP */
2725 for (i
= 0; i
< (sizeof(struct afex_stats
)/sizeof(u32
)); i
++)
2726 REG_WR(bp
, addr_to_write
+ i
*sizeof(u32
),
2727 *(((u32
*)(&afex_stats
))+i
));
2729 /* send ack message to MCP */
2730 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_STATSGET_ACK
, 0);
2733 if (cmd
& DRV_STATUS_AFEX_VIFSET_REQ
) {
2734 mf_config
= MF_CFG_RD(bp
, func_mf_config
[func
].config
);
2735 bp
->mf_config
[BP_VN(bp
)] = mf_config
;
2737 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2740 /* if VIF_SET is "enabled" */
2741 if (!(mf_config
& FUNC_MF_CFG_FUNC_DISABLED
)) {
2742 /* set rate limit directly to internal RAM */
2743 struct cmng_init_input cmng_input
;
2744 struct rate_shaping_vars_per_vn m_rs_vn
;
2745 size_t size
= sizeof(struct rate_shaping_vars_per_vn
);
2746 u32 addr
= BAR_XSTRORM_INTMEM
+
2747 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp
));
2749 bp
->mf_config
[BP_VN(bp
)] = mf_config
;
2751 bnx2x_calc_vn_max(bp
, BP_VN(bp
), &cmng_input
);
2752 m_rs_vn
.vn_counter
.rate
=
2753 cmng_input
.vnic_max_rate
[BP_VN(bp
)];
2754 m_rs_vn
.vn_counter
.quota
=
2755 (m_rs_vn
.vn_counter
.rate
*
2756 RS_PERIODIC_TIMEOUT_USEC
) / 8;
2758 __storm_memset_struct(bp
, addr
, size
, (u32
*)&m_rs_vn
);
2760 /* read relevant values from mf_cfg struct in shmem */
2762 (MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
2763 FUNC_MF_CFG_E1HOV_TAG_MASK
) >>
2764 FUNC_MF_CFG_E1HOV_TAG_SHIFT
;
2766 (MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
2767 FUNC_MF_CFG_AFEX_VLAN_MASK
) >>
2768 FUNC_MF_CFG_AFEX_VLAN_SHIFT
;
2769 vlan_prio
= (mf_config
&
2770 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK
) >>
2771 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT
;
2772 vlan_val
|= (vlan_prio
<< VLAN_PRIO_SHIFT
);
2775 func_mf_config
[func
].afex_config
) &
2776 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK
) >>
2777 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT
;
2780 func_mf_config
[func
].afex_config
) &
2781 FUNC_MF_CFG_AFEX_COS_FILTER_MASK
) >>
2782 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT
;
2784 /* send ramrod to FW, return in case of failure */
2785 if (bnx2x_afex_func_update(bp
, vif_id
, vlan_val
,
2789 bp
->afex_def_vlan_tag
= vlan_val
;
2790 bp
->afex_vlan_mode
= vlan_mode
;
2792 /* notify link down because BP->flags is disabled */
2793 bnx2x_link_report(bp
);
2795 /* send INVALID VIF ramrod to FW */
2796 bnx2x_afex_func_update(bp
, 0xFFFF, 0, 0);
2798 /* Reset the default afex VLAN */
2799 bp
->afex_def_vlan_tag
= -1;
2804 static void bnx2x_pmf_update(struct bnx2x
*bp
)
2806 int port
= BP_PORT(bp
);
2810 DP(BNX2X_MSG_MCP
, "pmf %d\n", bp
->port
.pmf
);
2813 * We need the mb() to ensure the ordering between the writing to
2814 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2818 /* queue a periodic task */
2819 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2821 bnx2x_dcbx_pmf_update(bp
);
2823 /* enable nig attention */
2824 val
= (0xff0f | (1 << (BP_VN(bp
) + 4)));
2825 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
2826 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
2827 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
2828 } else if (!CHIP_IS_E1x(bp
)) {
2829 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
2830 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
2833 bnx2x_stats_handle(bp
, STATS_EVENT_PMF
);
2841 * General service functions
2844 /* send the MCP a request, block until there is a reply */
2845 u32
bnx2x_fw_command(struct bnx2x
*bp
, u32 command
, u32 param
)
2847 int mb_idx
= BP_FW_MB_IDX(bp
);
2851 u8 delay
= CHIP_REV_IS_SLOW(bp
) ? 100 : 10;
2853 mutex_lock(&bp
->fw_mb_mutex
);
2855 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_param
, param
);
2856 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_header
, (command
| seq
));
2858 DP(BNX2X_MSG_MCP
, "wrote command (%x) to FW MB param 0x%08x\n",
2859 (command
| seq
), param
);
2862 /* let the FW do it's magic ... */
2865 rc
= SHMEM_RD(bp
, func_mb
[mb_idx
].fw_mb_header
);
2867 /* Give the FW up to 5 second (500*10ms) */
2868 } while ((seq
!= (rc
& FW_MSG_SEQ_NUMBER_MASK
)) && (cnt
++ < 500));
2870 DP(BNX2X_MSG_MCP
, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2871 cnt
*delay
, rc
, seq
);
2873 /* is this a reply to our command? */
2874 if (seq
== (rc
& FW_MSG_SEQ_NUMBER_MASK
))
2875 rc
&= FW_MSG_CODE_MASK
;
2878 BNX2X_ERR("FW failed to respond!\n");
2882 mutex_unlock(&bp
->fw_mb_mutex
);
2888 static void storm_memset_func_cfg(struct bnx2x
*bp
,
2889 struct tstorm_eth_function_common_config
*tcfg
,
2892 size_t size
= sizeof(struct tstorm_eth_function_common_config
);
2894 u32 addr
= BAR_TSTRORM_INTMEM
+
2895 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid
);
2897 __storm_memset_struct(bp
, addr
, size
, (u32
*)tcfg
);
2900 void bnx2x_func_init(struct bnx2x
*bp
, struct bnx2x_func_init_params
*p
)
2902 if (CHIP_IS_E1x(bp
)) {
2903 struct tstorm_eth_function_common_config tcfg
= {0};
2905 storm_memset_func_cfg(bp
, &tcfg
, p
->func_id
);
2908 /* Enable the function in the FW */
2909 storm_memset_vf_to_pf(bp
, p
->func_id
, p
->pf_id
);
2910 storm_memset_func_en(bp
, p
->func_id
, 1);
2913 if (p
->func_flgs
& FUNC_FLG_SPQ
) {
2914 storm_memset_spq_addr(bp
, p
->spq_map
, p
->func_id
);
2915 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+
2916 XSTORM_SPQ_PROD_OFFSET(p
->func_id
), p
->spq_prod
);
2921 * bnx2x_get_tx_only_flags - Return common flags
2925 * @zero_stats TRUE if statistics zeroing is needed
2927 * Return the flags that are common for the Tx-only and not normal connections.
2929 static unsigned long bnx2x_get_common_flags(struct bnx2x
*bp
,
2930 struct bnx2x_fastpath
*fp
,
2933 unsigned long flags
= 0;
2935 /* PF driver will always initialize the Queue to an ACTIVE state */
2936 __set_bit(BNX2X_Q_FLG_ACTIVE
, &flags
);
2938 /* tx only connections collect statistics (on the same index as the
2939 * parent connection). The statistics are zeroed when the parent
2940 * connection is initialized.
2943 __set_bit(BNX2X_Q_FLG_STATS
, &flags
);
2945 __set_bit(BNX2X_Q_FLG_ZERO_STATS
, &flags
);
2951 static unsigned long bnx2x_get_q_flags(struct bnx2x
*bp
,
2952 struct bnx2x_fastpath
*fp
,
2955 unsigned long flags
= 0;
2957 /* calculate other queue flags */
2959 __set_bit(BNX2X_Q_FLG_OV
, &flags
);
2961 if (IS_FCOE_FP(fp
)) {
2962 __set_bit(BNX2X_Q_FLG_FCOE
, &flags
);
2963 /* For FCoE - force usage of default priority (for afex) */
2964 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI
, &flags
);
2967 if (!fp
->disable_tpa
) {
2968 __set_bit(BNX2X_Q_FLG_TPA
, &flags
);
2969 __set_bit(BNX2X_Q_FLG_TPA_IPV6
, &flags
);
2970 if (fp
->mode
== TPA_MODE_GRO
)
2971 __set_bit(BNX2X_Q_FLG_TPA_GRO
, &flags
);
2975 __set_bit(BNX2X_Q_FLG_LEADING_RSS
, &flags
);
2976 __set_bit(BNX2X_Q_FLG_MCAST
, &flags
);
2979 /* Always set HW VLAN stripping */
2980 __set_bit(BNX2X_Q_FLG_VLAN
, &flags
);
2982 /* configure silent vlan removal */
2984 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM
, &flags
);
2987 return flags
| bnx2x_get_common_flags(bp
, fp
, true);
2990 static void bnx2x_pf_q_prep_general(struct bnx2x
*bp
,
2991 struct bnx2x_fastpath
*fp
, struct bnx2x_general_setup_params
*gen_init
,
2994 gen_init
->stat_id
= bnx2x_stats_id(fp
);
2995 gen_init
->spcl_id
= fp
->cl_id
;
2997 /* Always use mini-jumbo MTU for FCoE L2 ring */
2999 gen_init
->mtu
= BNX2X_FCOE_MINI_JUMBO_MTU
;
3001 gen_init
->mtu
= bp
->dev
->mtu
;
3003 gen_init
->cos
= cos
;
3006 static void bnx2x_pf_rx_q_prep(struct bnx2x
*bp
,
3007 struct bnx2x_fastpath
*fp
, struct rxq_pause_params
*pause
,
3008 struct bnx2x_rxq_setup_params
*rxq_init
)
3012 u16 tpa_agg_size
= 0;
3014 if (!fp
->disable_tpa
) {
3015 pause
->sge_th_lo
= SGE_TH_LO(bp
);
3016 pause
->sge_th_hi
= SGE_TH_HI(bp
);
3018 /* validate SGE ring has enough to cross high threshold */
3019 WARN_ON(bp
->dropless_fc
&&
3020 pause
->sge_th_hi
+ FW_PREFETCH_CNT
>
3021 MAX_RX_SGE_CNT
* NUM_RX_SGE_PAGES
);
3023 tpa_agg_size
= min_t(u32
,
3024 (min_t(u32
, 8, MAX_SKB_FRAGS
) *
3025 SGE_PAGE_SIZE
* PAGES_PER_SGE
), 0xffff);
3026 max_sge
= SGE_PAGE_ALIGN(bp
->dev
->mtu
) >>
3028 max_sge
= ((max_sge
+ PAGES_PER_SGE
- 1) &
3029 (~(PAGES_PER_SGE
-1))) >> PAGES_PER_SGE_SHIFT
;
3030 sge_sz
= (u16
)min_t(u32
, SGE_PAGE_SIZE
* PAGES_PER_SGE
,
3034 /* pause - not for e1 */
3035 if (!CHIP_IS_E1(bp
)) {
3036 pause
->bd_th_lo
= BD_TH_LO(bp
);
3037 pause
->bd_th_hi
= BD_TH_HI(bp
);
3039 pause
->rcq_th_lo
= RCQ_TH_LO(bp
);
3040 pause
->rcq_th_hi
= RCQ_TH_HI(bp
);
3042 * validate that rings have enough entries to cross
3045 WARN_ON(bp
->dropless_fc
&&
3046 pause
->bd_th_hi
+ FW_PREFETCH_CNT
>
3048 WARN_ON(bp
->dropless_fc
&&
3049 pause
->rcq_th_hi
+ FW_PREFETCH_CNT
>
3050 NUM_RCQ_RINGS
* MAX_RCQ_DESC_CNT
);
3056 rxq_init
->dscr_map
= fp
->rx_desc_mapping
;
3057 rxq_init
->sge_map
= fp
->rx_sge_mapping
;
3058 rxq_init
->rcq_map
= fp
->rx_comp_mapping
;
3059 rxq_init
->rcq_np_map
= fp
->rx_comp_mapping
+ BCM_PAGE_SIZE
;
3061 /* This should be a maximum number of data bytes that may be
3062 * placed on the BD (not including paddings).
3064 rxq_init
->buf_sz
= fp
->rx_buf_size
- BNX2X_FW_RX_ALIGN_START
-
3065 BNX2X_FW_RX_ALIGN_END
- IP_HEADER_ALIGNMENT_PADDING
;
3067 rxq_init
->cl_qzone_id
= fp
->cl_qzone_id
;
3068 rxq_init
->tpa_agg_sz
= tpa_agg_size
;
3069 rxq_init
->sge_buf_sz
= sge_sz
;
3070 rxq_init
->max_sges_pkt
= max_sge
;
3071 rxq_init
->rss_engine_id
= BP_FUNC(bp
);
3072 rxq_init
->mcast_engine_id
= BP_FUNC(bp
);
3074 /* Maximum number or simultaneous TPA aggregation for this Queue.
3076 * For PF Clients it should be the maximum avaliable number.
3077 * VF driver(s) may want to define it to a smaller value.
3079 rxq_init
->max_tpa_queues
= MAX_AGG_QS(bp
);
3081 rxq_init
->cache_line_log
= BNX2X_RX_ALIGN_SHIFT
;
3082 rxq_init
->fw_sb_id
= fp
->fw_sb_id
;
3085 rxq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS
;
3087 rxq_init
->sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
3088 /* configure silent vlan removal
3089 * if multi function mode is afex, then mask default vlan
3091 if (IS_MF_AFEX(bp
)) {
3092 rxq_init
->silent_removal_value
= bp
->afex_def_vlan_tag
;
3093 rxq_init
->silent_removal_mask
= VLAN_VID_MASK
;
3097 static void bnx2x_pf_tx_q_prep(struct bnx2x
*bp
,
3098 struct bnx2x_fastpath
*fp
, struct bnx2x_txq_setup_params
*txq_init
,
3101 txq_init
->dscr_map
= fp
->txdata_ptr
[cos
]->tx_desc_mapping
;
3102 txq_init
->sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
+ cos
;
3103 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_NW
;
3104 txq_init
->fw_sb_id
= fp
->fw_sb_id
;
3107 * set the tss leading client id for TX classfication ==
3108 * leading RSS client id
3110 txq_init
->tss_leading_cl_id
= bnx2x_fp(bp
, 0, cl_id
);
3112 if (IS_FCOE_FP(fp
)) {
3113 txq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS
;
3114 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_FCOE
;
3118 static void bnx2x_pf_init(struct bnx2x
*bp
)
3120 struct bnx2x_func_init_params func_init
= {0};
3121 struct event_ring_data eq_data
= { {0} };
3124 if (!CHIP_IS_E1x(bp
)) {
3125 /* reset IGU PF statistics: MSIX + ATTN */
3127 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
3128 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
3129 (CHIP_MODE_IS_4_PORT(bp
) ?
3130 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
3132 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
3133 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
3134 BNX2X_IGU_STAS_MSG_PF_CNT
*4 +
3135 (CHIP_MODE_IS_4_PORT(bp
) ?
3136 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
3139 /* function setup flags */
3140 flags
= (FUNC_FLG_STATS
| FUNC_FLG_LEADING
| FUNC_FLG_SPQ
);
3142 /* This flag is relevant for E1x only.
3143 * E2 doesn't have a TPA configuration in a function level.
3145 flags
|= (bp
->flags
& TPA_ENABLE_FLAG
) ? FUNC_FLG_TPA
: 0;
3147 func_init
.func_flgs
= flags
;
3148 func_init
.pf_id
= BP_FUNC(bp
);
3149 func_init
.func_id
= BP_FUNC(bp
);
3150 func_init
.spq_map
= bp
->spq_mapping
;
3151 func_init
.spq_prod
= bp
->spq_prod_idx
;
3153 bnx2x_func_init(bp
, &func_init
);
3155 memset(&(bp
->cmng
), 0, sizeof(struct cmng_struct_per_port
));
3158 * Congestion management values depend on the link rate
3159 * There is no active link so initial link rate is set to 10 Gbps.
3160 * When the link comes up The congestion management values are
3161 * re-calculated according to the actual link rate.
3163 bp
->link_vars
.line_speed
= SPEED_10000
;
3164 bnx2x_cmng_fns_init(bp
, true, bnx2x_get_cmng_fns_mode(bp
));
3166 /* Only the PMF sets the HW */
3168 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
3170 /* init Event Queue */
3171 eq_data
.base_addr
.hi
= U64_HI(bp
->eq_mapping
);
3172 eq_data
.base_addr
.lo
= U64_LO(bp
->eq_mapping
);
3173 eq_data
.producer
= bp
->eq_prod
;
3174 eq_data
.index_id
= HC_SP_INDEX_EQ_CONS
;
3175 eq_data
.sb_id
= DEF_SB_ID
;
3176 storm_memset_eq_data(bp
, &eq_data
, BP_FUNC(bp
));
3180 static void bnx2x_e1h_disable(struct bnx2x
*bp
)
3182 int port
= BP_PORT(bp
);
3184 bnx2x_tx_disable(bp
);
3186 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
3189 static void bnx2x_e1h_enable(struct bnx2x
*bp
)
3191 int port
= BP_PORT(bp
);
3193 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 1);
3195 /* Tx queue should be only reenabled */
3196 netif_tx_wake_all_queues(bp
->dev
);
3199 * Should not call netif_carrier_on since it will be called if the link
3200 * is up when checking for link state
3204 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3206 static void bnx2x_drv_info_ether_stat(struct bnx2x
*bp
)
3208 struct eth_stats_info
*ether_stat
=
3209 &bp
->slowpath
->drv_info_to_mcp
.ether_stat
;
3211 strlcpy(ether_stat
->version
, DRV_MODULE_VERSION
,
3212 ETH_STAT_INFO_VERSION_LEN
);
3214 bp
->sp_objs
[0].mac_obj
.get_n_elements(bp
, &bp
->sp_objs
[0].mac_obj
,
3215 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED
,
3216 ether_stat
->mac_local
);
3218 ether_stat
->mtu_size
= bp
->dev
->mtu
;
3220 if (bp
->dev
->features
& NETIF_F_RXCSUM
)
3221 ether_stat
->feature_flags
|= FEATURE_ETH_CHKSUM_OFFLOAD_MASK
;
3222 if (bp
->dev
->features
& NETIF_F_TSO
)
3223 ether_stat
->feature_flags
|= FEATURE_ETH_LSO_MASK
;
3224 ether_stat
->feature_flags
|= bp
->common
.boot_mode
;
3226 ether_stat
->promiscuous_mode
= (bp
->dev
->flags
& IFF_PROMISC
) ? 1 : 0;
3228 ether_stat
->txq_size
= bp
->tx_ring_size
;
3229 ether_stat
->rxq_size
= bp
->rx_ring_size
;
3232 static void bnx2x_drv_info_fcoe_stat(struct bnx2x
*bp
)
3234 struct bnx2x_dcbx_app_params
*app
= &bp
->dcbx_port_params
.app
;
3235 struct fcoe_stats_info
*fcoe_stat
=
3236 &bp
->slowpath
->drv_info_to_mcp
.fcoe_stat
;
3238 if (!CNIC_LOADED(bp
))
3241 memcpy(fcoe_stat
->mac_local
+ MAC_LEADING_ZERO_CNT
,
3242 bp
->fip_mac
, ETH_ALEN
);
3244 fcoe_stat
->qos_priority
=
3245 app
->traffic_type_priority
[LLFC_TRAFFIC_TYPE_FCOE
];
3247 /* insert FCoE stats from ramrod response */
3249 struct tstorm_per_queue_stats
*fcoe_q_tstorm_stats
=
3250 &bp
->fw_stats_data
->queue_stats
[FCOE_IDX(bp
)].
3251 tstorm_queue_statistics
;
3253 struct xstorm_per_queue_stats
*fcoe_q_xstorm_stats
=
3254 &bp
->fw_stats_data
->queue_stats
[FCOE_IDX(bp
)].
3255 xstorm_queue_statistics
;
3257 struct fcoe_statistics_params
*fw_fcoe_stat
=
3258 &bp
->fw_stats_data
->fcoe
;
3260 ADD_64(fcoe_stat
->rx_bytes_hi
, 0, fcoe_stat
->rx_bytes_lo
,
3261 fw_fcoe_stat
->rx_stat0
.fcoe_rx_byte_cnt
);
3263 ADD_64(fcoe_stat
->rx_bytes_hi
,
3264 fcoe_q_tstorm_stats
->rcv_ucast_bytes
.hi
,
3265 fcoe_stat
->rx_bytes_lo
,
3266 fcoe_q_tstorm_stats
->rcv_ucast_bytes
.lo
);
3268 ADD_64(fcoe_stat
->rx_bytes_hi
,
3269 fcoe_q_tstorm_stats
->rcv_bcast_bytes
.hi
,
3270 fcoe_stat
->rx_bytes_lo
,
3271 fcoe_q_tstorm_stats
->rcv_bcast_bytes
.lo
);
3273 ADD_64(fcoe_stat
->rx_bytes_hi
,
3274 fcoe_q_tstorm_stats
->rcv_mcast_bytes
.hi
,
3275 fcoe_stat
->rx_bytes_lo
,
3276 fcoe_q_tstorm_stats
->rcv_mcast_bytes
.lo
);
3278 ADD_64(fcoe_stat
->rx_frames_hi
, 0, fcoe_stat
->rx_frames_lo
,
3279 fw_fcoe_stat
->rx_stat0
.fcoe_rx_pkt_cnt
);
3281 ADD_64(fcoe_stat
->rx_frames_hi
, 0, fcoe_stat
->rx_frames_lo
,
3282 fcoe_q_tstorm_stats
->rcv_ucast_pkts
);
3284 ADD_64(fcoe_stat
->rx_frames_hi
, 0, fcoe_stat
->rx_frames_lo
,
3285 fcoe_q_tstorm_stats
->rcv_bcast_pkts
);
3287 ADD_64(fcoe_stat
->rx_frames_hi
, 0, fcoe_stat
->rx_frames_lo
,
3288 fcoe_q_tstorm_stats
->rcv_mcast_pkts
);
3290 ADD_64(fcoe_stat
->tx_bytes_hi
, 0, fcoe_stat
->tx_bytes_lo
,
3291 fw_fcoe_stat
->tx_stat
.fcoe_tx_byte_cnt
);
3293 ADD_64(fcoe_stat
->tx_bytes_hi
,
3294 fcoe_q_xstorm_stats
->ucast_bytes_sent
.hi
,
3295 fcoe_stat
->tx_bytes_lo
,
3296 fcoe_q_xstorm_stats
->ucast_bytes_sent
.lo
);
3298 ADD_64(fcoe_stat
->tx_bytes_hi
,
3299 fcoe_q_xstorm_stats
->bcast_bytes_sent
.hi
,
3300 fcoe_stat
->tx_bytes_lo
,
3301 fcoe_q_xstorm_stats
->bcast_bytes_sent
.lo
);
3303 ADD_64(fcoe_stat
->tx_bytes_hi
,
3304 fcoe_q_xstorm_stats
->mcast_bytes_sent
.hi
,
3305 fcoe_stat
->tx_bytes_lo
,
3306 fcoe_q_xstorm_stats
->mcast_bytes_sent
.lo
);
3308 ADD_64(fcoe_stat
->tx_frames_hi
, 0, fcoe_stat
->tx_frames_lo
,
3309 fw_fcoe_stat
->tx_stat
.fcoe_tx_pkt_cnt
);
3311 ADD_64(fcoe_stat
->tx_frames_hi
, 0, fcoe_stat
->tx_frames_lo
,
3312 fcoe_q_xstorm_stats
->ucast_pkts_sent
);
3314 ADD_64(fcoe_stat
->tx_frames_hi
, 0, fcoe_stat
->tx_frames_lo
,
3315 fcoe_q_xstorm_stats
->bcast_pkts_sent
);
3317 ADD_64(fcoe_stat
->tx_frames_hi
, 0, fcoe_stat
->tx_frames_lo
,
3318 fcoe_q_xstorm_stats
->mcast_pkts_sent
);
3321 /* ask L5 driver to add data to the struct */
3322 bnx2x_cnic_notify(bp
, CNIC_CTL_FCOE_STATS_GET_CMD
);
3325 static void bnx2x_drv_info_iscsi_stat(struct bnx2x
*bp
)
3327 struct bnx2x_dcbx_app_params
*app
= &bp
->dcbx_port_params
.app
;
3328 struct iscsi_stats_info
*iscsi_stat
=
3329 &bp
->slowpath
->drv_info_to_mcp
.iscsi_stat
;
3331 if (!CNIC_LOADED(bp
))
3334 memcpy(iscsi_stat
->mac_local
+ MAC_LEADING_ZERO_CNT
,
3335 bp
->cnic_eth_dev
.iscsi_mac
, ETH_ALEN
);
3337 iscsi_stat
->qos_priority
=
3338 app
->traffic_type_priority
[LLFC_TRAFFIC_TYPE_ISCSI
];
3340 /* ask L5 driver to add data to the struct */
3341 bnx2x_cnic_notify(bp
, CNIC_CTL_ISCSI_STATS_GET_CMD
);
3344 /* called due to MCP event (on pmf):
3345 * reread new bandwidth configuration
3347 * notify others function about the change
3349 static void bnx2x_config_mf_bw(struct bnx2x
*bp
)
3351 if (bp
->link_vars
.link_up
) {
3352 bnx2x_cmng_fns_init(bp
, true, CMNG_FNS_MINMAX
);
3353 bnx2x_link_sync_notify(bp
);
3355 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
3358 static void bnx2x_set_mf_bw(struct bnx2x
*bp
)
3360 bnx2x_config_mf_bw(bp
);
3361 bnx2x_fw_command(bp
, DRV_MSG_CODE_SET_MF_BW_ACK
, 0);
3364 static void bnx2x_handle_eee_event(struct bnx2x
*bp
)
3366 DP(BNX2X_MSG_MCP
, "EEE - LLDP event\n");
3367 bnx2x_fw_command(bp
, DRV_MSG_CODE_EEE_RESULTS_ACK
, 0);
3370 static void bnx2x_handle_drv_info_req(struct bnx2x
*bp
)
3372 enum drv_info_opcode op_code
;
3373 u32 drv_info_ctl
= SHMEM2_RD(bp
, drv_info_control
);
3375 /* if drv_info version supported by MFW doesn't match - send NACK */
3376 if ((drv_info_ctl
& DRV_INFO_CONTROL_VER_MASK
) != DRV_INFO_CUR_VER
) {
3377 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_NACK
, 0);
3381 op_code
= (drv_info_ctl
& DRV_INFO_CONTROL_OP_CODE_MASK
) >>
3382 DRV_INFO_CONTROL_OP_CODE_SHIFT
;
3384 memset(&bp
->slowpath
->drv_info_to_mcp
, 0,
3385 sizeof(union drv_info_to_mcp
));
3388 case ETH_STATS_OPCODE
:
3389 bnx2x_drv_info_ether_stat(bp
);
3391 case FCOE_STATS_OPCODE
:
3392 bnx2x_drv_info_fcoe_stat(bp
);
3394 case ISCSI_STATS_OPCODE
:
3395 bnx2x_drv_info_iscsi_stat(bp
);
3398 /* if op code isn't supported - send NACK */
3399 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_NACK
, 0);
3403 /* if we got drv_info attn from MFW then these fields are defined in
3406 SHMEM2_WR(bp
, drv_info_host_addr_lo
,
3407 U64_LO(bnx2x_sp_mapping(bp
, drv_info_to_mcp
)));
3408 SHMEM2_WR(bp
, drv_info_host_addr_hi
,
3409 U64_HI(bnx2x_sp_mapping(bp
, drv_info_to_mcp
)));
3411 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_ACK
, 0);
3414 static void bnx2x_dcc_event(struct bnx2x
*bp
, u32 dcc_event
)
3416 DP(BNX2X_MSG_MCP
, "dcc_event 0x%x\n", dcc_event
);
3418 if (dcc_event
& DRV_STATUS_DCC_DISABLE_ENABLE_PF
) {
3421 * This is the only place besides the function initialization
3422 * where the bp->flags can change so it is done without any
3425 if (bp
->mf_config
[BP_VN(bp
)] & FUNC_MF_CFG_FUNC_DISABLED
) {
3426 DP(BNX2X_MSG_MCP
, "mf_cfg function disabled\n");
3427 bp
->flags
|= MF_FUNC_DIS
;
3429 bnx2x_e1h_disable(bp
);
3431 DP(BNX2X_MSG_MCP
, "mf_cfg function enabled\n");
3432 bp
->flags
&= ~MF_FUNC_DIS
;
3434 bnx2x_e1h_enable(bp
);
3436 dcc_event
&= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF
;
3438 if (dcc_event
& DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
) {
3439 bnx2x_config_mf_bw(bp
);
3440 dcc_event
&= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
;
3443 /* Report results to MCP */
3445 bnx2x_fw_command(bp
, DRV_MSG_CODE_DCC_FAILURE
, 0);
3447 bnx2x_fw_command(bp
, DRV_MSG_CODE_DCC_OK
, 0);
3450 /* must be called under the spq lock */
3451 static struct eth_spe
*bnx2x_sp_get_next(struct bnx2x
*bp
)
3453 struct eth_spe
*next_spe
= bp
->spq_prod_bd
;
3455 if (bp
->spq_prod_bd
== bp
->spq_last_bd
) {
3456 bp
->spq_prod_bd
= bp
->spq
;
3457 bp
->spq_prod_idx
= 0;
3458 DP(BNX2X_MSG_SP
, "end of spq\n");
3466 /* must be called under the spq lock */
3467 static void bnx2x_sp_prod_update(struct bnx2x
*bp
)
3469 int func
= BP_FUNC(bp
);
3472 * Make sure that BD data is updated before writing the producer:
3473 * BD data is written to the memory, the producer is read from the
3474 * memory, thus we need a full memory barrier to ensure the ordering.
3478 REG_WR16(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_PROD_OFFSET(func
),
3484 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3486 * @cmd: command to check
3487 * @cmd_type: command type
3489 static bool bnx2x_is_contextless_ramrod(int cmd
, int cmd_type
)
3491 if ((cmd_type
== NONE_CONNECTION_TYPE
) ||
3492 (cmd
== RAMROD_CMD_ID_ETH_FORWARD_SETUP
) ||
3493 (cmd
== RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES
) ||
3494 (cmd
== RAMROD_CMD_ID_ETH_FILTER_RULES
) ||
3495 (cmd
== RAMROD_CMD_ID_ETH_MULTICAST_RULES
) ||
3496 (cmd
== RAMROD_CMD_ID_ETH_SET_MAC
) ||
3497 (cmd
== RAMROD_CMD_ID_ETH_RSS_UPDATE
))
3506 * bnx2x_sp_post - place a single command on an SP ring
3508 * @bp: driver handle
3509 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3510 * @cid: SW CID the command is related to
3511 * @data_hi: command private data address (high 32 bits)
3512 * @data_lo: command private data address (low 32 bits)
3513 * @cmd_type: command type (e.g. NONE, ETH)
3515 * SP data is handled as if it's always an address pair, thus data fields are
3516 * not swapped to little endian in upper functions. Instead this function swaps
3517 * data as if it's two u32 fields.
3519 int bnx2x_sp_post(struct bnx2x
*bp
, int command
, int cid
,
3520 u32 data_hi
, u32 data_lo
, int cmd_type
)
3522 struct eth_spe
*spe
;
3524 bool common
= bnx2x_is_contextless_ramrod(command
, cmd_type
);
3526 #ifdef BNX2X_STOP_ON_ERROR
3527 if (unlikely(bp
->panic
)) {
3528 BNX2X_ERR("Can't post SP when there is panic\n");
3533 spin_lock_bh(&bp
->spq_lock
);
3536 if (!atomic_read(&bp
->eq_spq_left
)) {
3537 BNX2X_ERR("BUG! EQ ring full!\n");
3538 spin_unlock_bh(&bp
->spq_lock
);
3542 } else if (!atomic_read(&bp
->cq_spq_left
)) {
3543 BNX2X_ERR("BUG! SPQ ring full!\n");
3544 spin_unlock_bh(&bp
->spq_lock
);
3549 spe
= bnx2x_sp_get_next(bp
);
3551 /* CID needs port number to be encoded int it */
3552 spe
->hdr
.conn_and_cmd_data
=
3553 cpu_to_le32((command
<< SPE_HDR_CMD_ID_SHIFT
) |
3556 type
= (cmd_type
<< SPE_HDR_CONN_TYPE_SHIFT
) & SPE_HDR_CONN_TYPE
;
3558 type
|= ((BP_FUNC(bp
) << SPE_HDR_FUNCTION_ID_SHIFT
) &
3559 SPE_HDR_FUNCTION_ID
);
3561 spe
->hdr
.type
= cpu_to_le16(type
);
3563 spe
->data
.update_data_addr
.hi
= cpu_to_le32(data_hi
);
3564 spe
->data
.update_data_addr
.lo
= cpu_to_le32(data_lo
);
3567 * It's ok if the actual decrement is issued towards the memory
3568 * somewhere between the spin_lock and spin_unlock. Thus no
3569 * more explict memory barrier is needed.
3572 atomic_dec(&bp
->eq_spq_left
);
3574 atomic_dec(&bp
->cq_spq_left
);
3578 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3579 bp
->spq_prod_idx
, (u32
)U64_HI(bp
->spq_mapping
),
3580 (u32
)(U64_LO(bp
->spq_mapping
) +
3581 (void *)bp
->spq_prod_bd
- (void *)bp
->spq
), command
, common
,
3582 HW_CID(bp
, cid
), data_hi
, data_lo
, type
,
3583 atomic_read(&bp
->cq_spq_left
), atomic_read(&bp
->eq_spq_left
));
3585 bnx2x_sp_prod_update(bp
);
3586 spin_unlock_bh(&bp
->spq_lock
);
3590 /* acquire split MCP access lock register */
3591 static int bnx2x_acquire_alr(struct bnx2x
*bp
)
3597 for (j
= 0; j
< 1000; j
++) {
3599 REG_WR(bp
, GRCBASE_MCP
+ 0x9c, val
);
3600 val
= REG_RD(bp
, GRCBASE_MCP
+ 0x9c);
3601 if (val
& (1L << 31))
3606 if (!(val
& (1L << 31))) {
3607 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3614 /* release split MCP access lock register */
3615 static void bnx2x_release_alr(struct bnx2x
*bp
)
3617 REG_WR(bp
, GRCBASE_MCP
+ 0x9c, 0);
3620 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3621 #define BNX2X_DEF_SB_IDX 0x0002
3623 static u16
bnx2x_update_dsb_idx(struct bnx2x
*bp
)
3625 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
3628 barrier(); /* status block is written to by the chip */
3629 if (bp
->def_att_idx
!= def_sb
->atten_status_block
.attn_bits_index
) {
3630 bp
->def_att_idx
= def_sb
->atten_status_block
.attn_bits_index
;
3631 rc
|= BNX2X_DEF_SB_ATT_IDX
;
3634 if (bp
->def_idx
!= def_sb
->sp_sb
.running_index
) {
3635 bp
->def_idx
= def_sb
->sp_sb
.running_index
;
3636 rc
|= BNX2X_DEF_SB_IDX
;
3639 /* Do not reorder: indecies reading should complete before handling */
3645 * slow path service functions
3648 static void bnx2x_attn_int_asserted(struct bnx2x
*bp
, u32 asserted
)
3650 int port
= BP_PORT(bp
);
3651 u32 aeu_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
3652 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
3653 u32 nig_int_mask_addr
= port
? NIG_REG_MASK_INTERRUPT_PORT1
:
3654 NIG_REG_MASK_INTERRUPT_PORT0
;
3659 if (bp
->attn_state
& asserted
)
3660 BNX2X_ERR("IGU ERROR\n");
3662 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
3663 aeu_mask
= REG_RD(bp
, aeu_addr
);
3665 DP(NETIF_MSG_HW
, "aeu_mask %x newly asserted %x\n",
3666 aeu_mask
, asserted
);
3667 aeu_mask
&= ~(asserted
& 0x3ff);
3668 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
3670 REG_WR(bp
, aeu_addr
, aeu_mask
);
3671 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
3673 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
3674 bp
->attn_state
|= asserted
;
3675 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
3677 if (asserted
& ATTN_HARD_WIRED_MASK
) {
3678 if (asserted
& ATTN_NIG_FOR_FUNC
) {
3680 bnx2x_acquire_phy_lock(bp
);
3682 /* save nig interrupt mask */
3683 nig_mask
= REG_RD(bp
, nig_int_mask_addr
);
3685 /* If nig_mask is not set, no need to call the update
3689 REG_WR(bp
, nig_int_mask_addr
, 0);
3691 bnx2x_link_attn(bp
);
3694 /* handle unicore attn? */
3696 if (asserted
& ATTN_SW_TIMER_4_FUNC
)
3697 DP(NETIF_MSG_HW
, "ATTN_SW_TIMER_4_FUNC!\n");
3699 if (asserted
& GPIO_2_FUNC
)
3700 DP(NETIF_MSG_HW
, "GPIO_2_FUNC!\n");
3702 if (asserted
& GPIO_3_FUNC
)
3703 DP(NETIF_MSG_HW
, "GPIO_3_FUNC!\n");
3705 if (asserted
& GPIO_4_FUNC
)
3706 DP(NETIF_MSG_HW
, "GPIO_4_FUNC!\n");
3709 if (asserted
& ATTN_GENERAL_ATTN_1
) {
3710 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_1!\n");
3711 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_1
, 0x0);
3713 if (asserted
& ATTN_GENERAL_ATTN_2
) {
3714 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_2!\n");
3715 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_2
, 0x0);
3717 if (asserted
& ATTN_GENERAL_ATTN_3
) {
3718 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_3!\n");
3719 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_3
, 0x0);
3722 if (asserted
& ATTN_GENERAL_ATTN_4
) {
3723 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_4!\n");
3724 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_4
, 0x0);
3726 if (asserted
& ATTN_GENERAL_ATTN_5
) {
3727 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_5!\n");
3728 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_5
, 0x0);
3730 if (asserted
& ATTN_GENERAL_ATTN_6
) {
3731 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_6!\n");
3732 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_6
, 0x0);
3736 } /* if hardwired */
3738 if (bp
->common
.int_block
== INT_BLOCK_HC
)
3739 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
3740 COMMAND_REG_ATTN_BITS_SET
);
3742 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_SET_UPPER
*8);
3744 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", asserted
,
3745 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
3746 REG_WR(bp
, reg_addr
, asserted
);
3748 /* now set back the mask */
3749 if (asserted
& ATTN_NIG_FOR_FUNC
) {
3750 /* Verify that IGU ack through BAR was written before restoring
3751 * NIG mask. This loop should exit after 2-3 iterations max.
3753 if (bp
->common
.int_block
!= INT_BLOCK_HC
) {
3754 u32 cnt
= 0, igu_acked
;
3756 igu_acked
= REG_RD(bp
,
3757 IGU_REG_ATTENTION_ACK_BITS
);
3758 } while (((igu_acked
& ATTN_NIG_FOR_FUNC
) == 0) &&
3759 (++cnt
< MAX_IGU_ATTN_ACK_TO
));
3762 "Failed to verify IGU ack on time\n");
3765 REG_WR(bp
, nig_int_mask_addr
, nig_mask
);
3766 bnx2x_release_phy_lock(bp
);
3770 static void bnx2x_fan_failure(struct bnx2x
*bp
)
3772 int port
= BP_PORT(bp
);
3774 /* mark the failure */
3777 dev_info
.port_hw_config
[port
].external_phy_config
);
3779 ext_phy_config
&= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK
;
3780 ext_phy_config
|= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
;
3781 SHMEM_WR(bp
, dev_info
.port_hw_config
[port
].external_phy_config
,
3784 /* log the failure */
3785 netdev_err(bp
->dev
, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3786 "Please contact OEM Support for assistance\n");
3789 * Scheudle device reset (unload)
3790 * This is due to some boards consuming sufficient power when driver is
3791 * up to overheat if fan fails.
3793 smp_mb__before_clear_bit();
3794 set_bit(BNX2X_SP_RTNL_FAN_FAILURE
, &bp
->sp_rtnl_state
);
3795 smp_mb__after_clear_bit();
3796 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
3800 static void bnx2x_attn_int_deasserted0(struct bnx2x
*bp
, u32 attn
)
3802 int port
= BP_PORT(bp
);
3806 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
3807 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
3809 if (attn
& AEU_INPUTS_ATTN_BITS_SPIO5
) {
3811 val
= REG_RD(bp
, reg_offset
);
3812 val
&= ~AEU_INPUTS_ATTN_BITS_SPIO5
;
3813 REG_WR(bp
, reg_offset
, val
);
3815 BNX2X_ERR("SPIO5 hw attention\n");
3817 /* Fan failure attention */
3818 bnx2x_hw_reset_phy(&bp
->link_params
);
3819 bnx2x_fan_failure(bp
);
3822 if ((attn
& bp
->link_vars
.aeu_int_mask
) && bp
->port
.pmf
) {
3823 bnx2x_acquire_phy_lock(bp
);
3824 bnx2x_handle_module_detect_int(&bp
->link_params
);
3825 bnx2x_release_phy_lock(bp
);
3828 if (attn
& HW_INTERRUT_ASSERT_SET_0
) {
3830 val
= REG_RD(bp
, reg_offset
);
3831 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_0
);
3832 REG_WR(bp
, reg_offset
, val
);
3834 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3835 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_0
));
3840 static void bnx2x_attn_int_deasserted1(struct bnx2x
*bp
, u32 attn
)
3844 if (attn
& AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
) {
3846 val
= REG_RD(bp
, DORQ_REG_DORQ_INT_STS_CLR
);
3847 BNX2X_ERR("DB hw attention 0x%x\n", val
);
3848 /* DORQ discard attention */
3850 BNX2X_ERR("FATAL error from DORQ\n");
3853 if (attn
& HW_INTERRUT_ASSERT_SET_1
) {
3855 int port
= BP_PORT(bp
);
3858 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1
:
3859 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1
);
3861 val
= REG_RD(bp
, reg_offset
);
3862 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_1
);
3863 REG_WR(bp
, reg_offset
, val
);
3865 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3866 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_1
));
3871 static void bnx2x_attn_int_deasserted2(struct bnx2x
*bp
, u32 attn
)
3875 if (attn
& AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT
) {
3877 val
= REG_RD(bp
, CFC_REG_CFC_INT_STS_CLR
);
3878 BNX2X_ERR("CFC hw attention 0x%x\n", val
);
3879 /* CFC error attention */
3881 BNX2X_ERR("FATAL error from CFC\n");
3884 if (attn
& AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT
) {
3885 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_0
);
3886 BNX2X_ERR("PXP hw attention-0 0x%x\n", val
);
3887 /* RQ_USDMDP_FIFO_OVERFLOW */
3889 BNX2X_ERR("FATAL error from PXP\n");
3891 if (!CHIP_IS_E1x(bp
)) {
3892 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_1
);
3893 BNX2X_ERR("PXP hw attention-1 0x%x\n", val
);
3897 if (attn
& HW_INTERRUT_ASSERT_SET_2
) {
3899 int port
= BP_PORT(bp
);
3902 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2
:
3903 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2
);
3905 val
= REG_RD(bp
, reg_offset
);
3906 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_2
);
3907 REG_WR(bp
, reg_offset
, val
);
3909 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3910 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_2
));
3915 static void bnx2x_attn_int_deasserted3(struct bnx2x
*bp
, u32 attn
)
3919 if (attn
& EVEREST_GEN_ATTN_IN_USE_MASK
) {
3921 if (attn
& BNX2X_PMF_LINK_ASSERT
) {
3922 int func
= BP_FUNC(bp
);
3924 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
3925 bnx2x_read_mf_cfg(bp
);
3926 bp
->mf_config
[BP_VN(bp
)] = MF_CFG_RD(bp
,
3927 func_mf_config
[BP_ABS_FUNC(bp
)].config
);
3929 func_mb
[BP_FW_MB_IDX(bp
)].drv_status
);
3930 if (val
& DRV_STATUS_DCC_EVENT_MASK
)
3932 (val
& DRV_STATUS_DCC_EVENT_MASK
));
3934 if (val
& DRV_STATUS_SET_MF_BW
)
3935 bnx2x_set_mf_bw(bp
);
3937 if (val
& DRV_STATUS_DRV_INFO_REQ
)
3938 bnx2x_handle_drv_info_req(bp
);
3940 if (val
& DRV_STATUS_VF_DISABLED
)
3941 bnx2x_vf_handle_flr_event(bp
);
3943 if ((bp
->port
.pmf
== 0) && (val
& DRV_STATUS_PMF
))
3944 bnx2x_pmf_update(bp
);
3947 (val
& DRV_STATUS_DCBX_NEGOTIATION_RESULTS
) &&
3948 bp
->dcbx_enabled
> 0)
3949 /* start dcbx state machine */
3950 bnx2x_dcbx_set_params(bp
,
3951 BNX2X_DCBX_STATE_NEG_RECEIVED
);
3952 if (val
& DRV_STATUS_AFEX_EVENT_MASK
)
3953 bnx2x_handle_afex_cmd(bp
,
3954 val
& DRV_STATUS_AFEX_EVENT_MASK
);
3955 if (val
& DRV_STATUS_EEE_NEGOTIATION_RESULTS
)
3956 bnx2x_handle_eee_event(bp
);
3957 if (bp
->link_vars
.periodic_flags
&
3958 PERIODIC_FLAGS_LINK_EVENT
) {
3959 /* sync with link */
3960 bnx2x_acquire_phy_lock(bp
);
3961 bp
->link_vars
.periodic_flags
&=
3962 ~PERIODIC_FLAGS_LINK_EVENT
;
3963 bnx2x_release_phy_lock(bp
);
3965 bnx2x_link_sync_notify(bp
);
3966 bnx2x_link_report(bp
);
3968 /* Always call it here: bnx2x_link_report() will
3969 * prevent the link indication duplication.
3971 bnx2x__link_status_update(bp
);
3972 } else if (attn
& BNX2X_MC_ASSERT_BITS
) {
3974 BNX2X_ERR("MC assert!\n");
3975 bnx2x_mc_assert(bp
);
3976 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_10
, 0);
3977 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_9
, 0);
3978 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_8
, 0);
3979 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_7
, 0);
3982 } else if (attn
& BNX2X_MCP_ASSERT
) {
3984 BNX2X_ERR("MCP assert!\n");
3985 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_11
, 0);
3989 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn
);
3992 if (attn
& EVEREST_LATCHED_ATTN_IN_USE_MASK
) {
3993 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn
);
3994 if (attn
& BNX2X_GRC_TIMEOUT
) {
3995 val
= CHIP_IS_E1(bp
) ? 0 :
3996 REG_RD(bp
, MISC_REG_GRC_TIMEOUT_ATTN
);
3997 BNX2X_ERR("GRC time-out 0x%08x\n", val
);
3999 if (attn
& BNX2X_GRC_RSV
) {
4000 val
= CHIP_IS_E1(bp
) ? 0 :
4001 REG_RD(bp
, MISC_REG_GRC_RSV_ATTN
);
4002 BNX2X_ERR("GRC reserved 0x%08x\n", val
);
4004 REG_WR(bp
, MISC_REG_AEU_CLR_LATCH_SIGNAL
, 0x7ff);
4010 * 0-7 - Engine0 load counter.
4011 * 8-15 - Engine1 load counter.
4012 * 16 - Engine0 RESET_IN_PROGRESS bit.
4013 * 17 - Engine1 RESET_IN_PROGRESS bit.
4014 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4016 * 19 - Engine1 ONE_IS_LOADED.
4017 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4018 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4019 * just the one belonging to its engine).
4022 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4024 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4025 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4026 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4027 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4028 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4029 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4030 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4033 * Set the GLOBAL_RESET bit.
4035 * Should be run under rtnl lock
4037 void bnx2x_set_reset_global(struct bnx2x
*bp
)
4040 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4041 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4042 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
| BNX2X_GLOBAL_RESET_BIT
);
4043 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4047 * Clear the GLOBAL_RESET bit.
4049 * Should be run under rtnl lock
4051 static void bnx2x_clear_reset_global(struct bnx2x
*bp
)
4054 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4055 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4056 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
& (~BNX2X_GLOBAL_RESET_BIT
));
4057 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4061 * Checks the GLOBAL_RESET bit.
4063 * should be run under rtnl lock
4065 static bool bnx2x_reset_is_global(struct bnx2x
*bp
)
4067 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4069 DP(NETIF_MSG_HW
, "GEN_REG_VAL=0x%08x\n", val
);
4070 return (val
& BNX2X_GLOBAL_RESET_BIT
) ? true : false;
4074 * Clear RESET_IN_PROGRESS bit for the current engine.
4076 * Should be run under rtnl lock
4078 static void bnx2x_set_reset_done(struct bnx2x
*bp
)
4081 u32 bit
= BP_PATH(bp
) ?
4082 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
4083 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4084 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4088 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4090 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4094 * Set RESET_IN_PROGRESS for the current engine.
4096 * should be run under rtnl lock
4098 void bnx2x_set_reset_in_progress(struct bnx2x
*bp
)
4101 u32 bit
= BP_PATH(bp
) ?
4102 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
4103 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4104 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4108 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4109 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4113 * Checks the RESET_IN_PROGRESS bit for the given engine.
4114 * should be run under rtnl lock
4116 bool bnx2x_reset_is_done(struct bnx2x
*bp
, int engine
)
4118 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4120 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
4122 /* return false if bit is set */
4123 return (val
& bit
) ? false : true;
4127 * set pf load for the current pf.
4129 * should be run under rtnl lock
4131 void bnx2x_set_pf_load(struct bnx2x
*bp
)
4134 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
4135 BNX2X_PATH0_LOAD_CNT_MASK
;
4136 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
4137 BNX2X_PATH0_LOAD_CNT_SHIFT
;
4139 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4140 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4142 DP(NETIF_MSG_IFUP
, "Old GEN_REG_VAL=0x%08x\n", val
);
4144 /* get the current counter value */
4145 val1
= (val
& mask
) >> shift
;
4147 /* set bit of that PF */
4148 val1
|= (1 << bp
->pf_num
);
4150 /* clear the old value */
4153 /* set the new one */
4154 val
|= ((val1
<< shift
) & mask
);
4156 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4157 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4161 * bnx2x_clear_pf_load - clear pf load mark
4163 * @bp: driver handle
4165 * Should be run under rtnl lock.
4166 * Decrements the load counter for the current engine. Returns
4167 * whether other functions are still loaded
4169 bool bnx2x_clear_pf_load(struct bnx2x
*bp
)
4172 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
4173 BNX2X_PATH0_LOAD_CNT_MASK
;
4174 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
4175 BNX2X_PATH0_LOAD_CNT_SHIFT
;
4177 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4178 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4179 DP(NETIF_MSG_IFDOWN
, "Old GEN_REG_VAL=0x%08x\n", val
);
4181 /* get the current counter value */
4182 val1
= (val
& mask
) >> shift
;
4184 /* clear bit of that PF */
4185 val1
&= ~(1 << bp
->pf_num
);
4187 /* clear the old value */
4190 /* set the new one */
4191 val
|= ((val1
<< shift
) & mask
);
4193 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4194 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4199 * Read the load status for the current engine.
4201 * should be run under rtnl lock
4203 static bool bnx2x_get_load_status(struct bnx2x
*bp
, int engine
)
4205 u32 mask
= (engine
? BNX2X_PATH1_LOAD_CNT_MASK
:
4206 BNX2X_PATH0_LOAD_CNT_MASK
);
4207 u32 shift
= (engine
? BNX2X_PATH1_LOAD_CNT_SHIFT
:
4208 BNX2X_PATH0_LOAD_CNT_SHIFT
);
4209 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4211 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "GLOB_REG=0x%08x\n", val
);
4213 val
= (val
& mask
) >> shift
;
4215 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "load mask for engine %d = 0x%x\n",
4221 static void _print_next_block(int idx
, const char *blk
)
4223 pr_cont("%s%s", idx
? ", " : "", blk
);
4226 static int bnx2x_check_blocks_with_parity0(u32 sig
, int par_num
,
4231 for (i
= 0; sig
; i
++) {
4232 cur_bit
= ((u32
)0x1 << i
);
4233 if (sig
& cur_bit
) {
4235 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR
:
4237 _print_next_block(par_num
++, "BRB");
4239 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR
:
4241 _print_next_block(par_num
++, "PARSER");
4243 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR
:
4245 _print_next_block(par_num
++, "TSDM");
4247 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR
:
4249 _print_next_block(par_num
++,
4252 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR
:
4254 _print_next_block(par_num
++, "TCM");
4256 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR
:
4258 _print_next_block(par_num
++, "TSEMI");
4260 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR
:
4262 _print_next_block(par_num
++, "XPB");
4274 static int bnx2x_check_blocks_with_parity1(u32 sig
, int par_num
,
4275 bool *global
, bool print
)
4279 for (i
= 0; sig
; i
++) {
4280 cur_bit
= ((u32
)0x1 << i
);
4281 if (sig
& cur_bit
) {
4283 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR
:
4285 _print_next_block(par_num
++, "PBF");
4287 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR
:
4289 _print_next_block(par_num
++, "QM");
4291 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR
:
4293 _print_next_block(par_num
++, "TM");
4295 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR
:
4297 _print_next_block(par_num
++, "XSDM");
4299 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR
:
4301 _print_next_block(par_num
++, "XCM");
4303 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR
:
4305 _print_next_block(par_num
++, "XSEMI");
4307 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR
:
4309 _print_next_block(par_num
++,
4312 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR
:
4314 _print_next_block(par_num
++, "NIG");
4316 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR
:
4318 _print_next_block(par_num
++,
4322 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR
:
4324 _print_next_block(par_num
++, "DEBUG");
4326 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR
:
4328 _print_next_block(par_num
++, "USDM");
4330 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR
:
4332 _print_next_block(par_num
++, "UCM");
4334 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR
:
4336 _print_next_block(par_num
++, "USEMI");
4338 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR
:
4340 _print_next_block(par_num
++, "UPB");
4342 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR
:
4344 _print_next_block(par_num
++, "CSDM");
4346 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR
:
4348 _print_next_block(par_num
++, "CCM");
4360 static int bnx2x_check_blocks_with_parity2(u32 sig
, int par_num
,
4365 for (i
= 0; sig
; i
++) {
4366 cur_bit
= ((u32
)0x1 << i
);
4367 if (sig
& cur_bit
) {
4369 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR
:
4371 _print_next_block(par_num
++, "CSEMI");
4373 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR
:
4375 _print_next_block(par_num
++, "PXP");
4377 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
:
4379 _print_next_block(par_num
++,
4380 "PXPPCICLOCKCLIENT");
4382 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR
:
4384 _print_next_block(par_num
++, "CFC");
4386 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR
:
4388 _print_next_block(par_num
++, "CDU");
4390 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR
:
4392 _print_next_block(par_num
++, "DMAE");
4394 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR
:
4396 _print_next_block(par_num
++, "IGU");
4398 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR
:
4400 _print_next_block(par_num
++, "MISC");
4412 static int bnx2x_check_blocks_with_parity3(u32 sig
, int par_num
,
4413 bool *global
, bool print
)
4417 for (i
= 0; sig
; i
++) {
4418 cur_bit
= ((u32
)0x1 << i
);
4419 if (sig
& cur_bit
) {
4421 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY
:
4423 _print_next_block(par_num
++, "MCP ROM");
4426 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY
:
4428 _print_next_block(par_num
++,
4432 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY
:
4434 _print_next_block(par_num
++,
4438 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
:
4440 _print_next_block(par_num
++,
4454 static int bnx2x_check_blocks_with_parity4(u32 sig
, int par_num
,
4459 for (i
= 0; sig
; i
++) {
4460 cur_bit
= ((u32
)0x1 << i
);
4461 if (sig
& cur_bit
) {
4463 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
:
4465 _print_next_block(par_num
++, "PGLUE_B");
4467 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
:
4469 _print_next_block(par_num
++, "ATC");
4481 static bool bnx2x_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
,
4484 if ((sig
[0] & HW_PRTY_ASSERT_SET_0
) ||
4485 (sig
[1] & HW_PRTY_ASSERT_SET_1
) ||
4486 (sig
[2] & HW_PRTY_ASSERT_SET_2
) ||
4487 (sig
[3] & HW_PRTY_ASSERT_SET_3
) ||
4488 (sig
[4] & HW_PRTY_ASSERT_SET_4
)) {
4490 DP(NETIF_MSG_HW
, "Was parity error: HW block parity attention:\n"
4491 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4492 sig
[0] & HW_PRTY_ASSERT_SET_0
,
4493 sig
[1] & HW_PRTY_ASSERT_SET_1
,
4494 sig
[2] & HW_PRTY_ASSERT_SET_2
,
4495 sig
[3] & HW_PRTY_ASSERT_SET_3
,
4496 sig
[4] & HW_PRTY_ASSERT_SET_4
);
4499 "Parity errors detected in blocks: ");
4500 par_num
= bnx2x_check_blocks_with_parity0(
4501 sig
[0] & HW_PRTY_ASSERT_SET_0
, par_num
, print
);
4502 par_num
= bnx2x_check_blocks_with_parity1(
4503 sig
[1] & HW_PRTY_ASSERT_SET_1
, par_num
, global
, print
);
4504 par_num
= bnx2x_check_blocks_with_parity2(
4505 sig
[2] & HW_PRTY_ASSERT_SET_2
, par_num
, print
);
4506 par_num
= bnx2x_check_blocks_with_parity3(
4507 sig
[3] & HW_PRTY_ASSERT_SET_3
, par_num
, global
, print
);
4508 par_num
= bnx2x_check_blocks_with_parity4(
4509 sig
[4] & HW_PRTY_ASSERT_SET_4
, par_num
, print
);
4520 * bnx2x_chk_parity_attn - checks for parity attentions.
4522 * @bp: driver handle
4523 * @global: true if there was a global attention
4524 * @print: show parity attention in syslog
4526 bool bnx2x_chk_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
)
4528 struct attn_route attn
= { {0} };
4529 int port
= BP_PORT(bp
);
4531 attn
.sig
[0] = REG_RD(bp
,
4532 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+
4534 attn
.sig
[1] = REG_RD(bp
,
4535 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+
4537 attn
.sig
[2] = REG_RD(bp
,
4538 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+
4540 attn
.sig
[3] = REG_RD(bp
,
4541 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+
4544 if (!CHIP_IS_E1x(bp
))
4545 attn
.sig
[4] = REG_RD(bp
,
4546 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+
4549 return bnx2x_parity_attn(bp
, global
, print
, attn
.sig
);
4553 static void bnx2x_attn_int_deasserted4(struct bnx2x
*bp
, u32 attn
)
4556 if (attn
& AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT
) {
4558 val
= REG_RD(bp
, PGLUE_B_REG_PGLUE_B_INT_STS_CLR
);
4559 BNX2X_ERR("PGLUE hw attention 0x%x\n", val
);
4560 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR
)
4561 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4562 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR
)
4563 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4564 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN
)
4565 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4566 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN
)
4567 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4569 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN
)
4570 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4572 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN
)
4573 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4574 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN
)
4575 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4576 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN
)
4577 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4578 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW
)
4579 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4581 if (attn
& AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT
) {
4582 val
= REG_RD(bp
, ATC_REG_ATC_INT_STS_CLR
);
4583 BNX2X_ERR("ATC hw attention 0x%x\n", val
);
4584 if (val
& ATC_ATC_INT_STS_REG_ADDRESS_ERROR
)
4585 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4586 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND
)
4587 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4588 if (val
& ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS
)
4589 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4590 if (val
& ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT
)
4591 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4592 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR
)
4593 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4594 if (val
& ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU
)
4595 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4598 if (attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
4599 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)) {
4600 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4601 (u32
)(attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
4602 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)));
4607 static void bnx2x_attn_int_deasserted(struct bnx2x
*bp
, u32 deasserted
)
4609 struct attn_route attn
, *group_mask
;
4610 int port
= BP_PORT(bp
);
4615 bool global
= false;
4617 /* need to take HW lock because MCP or other port might also
4618 try to handle this event */
4619 bnx2x_acquire_alr(bp
);
4621 if (bnx2x_chk_parity_attn(bp
, &global
, true)) {
4622 #ifndef BNX2X_STOP_ON_ERROR
4623 bp
->recovery_state
= BNX2X_RECOVERY_INIT
;
4624 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
4625 /* Disable HW interrupts */
4626 bnx2x_int_disable(bp
);
4627 /* In case of parity errors don't handle attentions so that
4628 * other function would "see" parity errors.
4633 bnx2x_release_alr(bp
);
4637 attn
.sig
[0] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ port
*4);
4638 attn
.sig
[1] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+ port
*4);
4639 attn
.sig
[2] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+ port
*4);
4640 attn
.sig
[3] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+ port
*4);
4641 if (!CHIP_IS_E1x(bp
))
4643 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+ port
*4);
4647 DP(NETIF_MSG_HW
, "attn: %08x %08x %08x %08x %08x\n",
4648 attn
.sig
[0], attn
.sig
[1], attn
.sig
[2], attn
.sig
[3], attn
.sig
[4]);
4650 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
4651 if (deasserted
& (1 << index
)) {
4652 group_mask
= &bp
->attn_group
[index
];
4654 DP(NETIF_MSG_HW
, "group[%d]: %08x %08x %08x %08x %08x\n",
4656 group_mask
->sig
[0], group_mask
->sig
[1],
4657 group_mask
->sig
[2], group_mask
->sig
[3],
4658 group_mask
->sig
[4]);
4660 bnx2x_attn_int_deasserted4(bp
,
4661 attn
.sig
[4] & group_mask
->sig
[4]);
4662 bnx2x_attn_int_deasserted3(bp
,
4663 attn
.sig
[3] & group_mask
->sig
[3]);
4664 bnx2x_attn_int_deasserted1(bp
,
4665 attn
.sig
[1] & group_mask
->sig
[1]);
4666 bnx2x_attn_int_deasserted2(bp
,
4667 attn
.sig
[2] & group_mask
->sig
[2]);
4668 bnx2x_attn_int_deasserted0(bp
,
4669 attn
.sig
[0] & group_mask
->sig
[0]);
4673 bnx2x_release_alr(bp
);
4675 if (bp
->common
.int_block
== INT_BLOCK_HC
)
4676 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
4677 COMMAND_REG_ATTN_BITS_CLR
);
4679 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_CLR_UPPER
*8);
4682 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", val
,
4683 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
4684 REG_WR(bp
, reg_addr
, val
);
4686 if (~bp
->attn_state
& deasserted
)
4687 BNX2X_ERR("IGU ERROR\n");
4689 reg_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
4690 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
4692 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4693 aeu_mask
= REG_RD(bp
, reg_addr
);
4695 DP(NETIF_MSG_HW
, "aeu_mask %x newly deasserted %x\n",
4696 aeu_mask
, deasserted
);
4697 aeu_mask
|= (deasserted
& 0x3ff);
4698 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
4700 REG_WR(bp
, reg_addr
, aeu_mask
);
4701 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4703 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
4704 bp
->attn_state
&= ~deasserted
;
4705 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
4708 static void bnx2x_attn_int(struct bnx2x
*bp
)
4710 /* read local copy of bits */
4711 u32 attn_bits
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
4713 u32 attn_ack
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
4715 u32 attn_state
= bp
->attn_state
;
4717 /* look for changed bits */
4718 u32 asserted
= attn_bits
& ~attn_ack
& ~attn_state
;
4719 u32 deasserted
= ~attn_bits
& attn_ack
& attn_state
;
4722 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4723 attn_bits
, attn_ack
, asserted
, deasserted
);
4725 if (~(attn_bits
^ attn_ack
) & (attn_bits
^ attn_state
))
4726 BNX2X_ERR("BAD attention state\n");
4728 /* handle bits that were raised */
4730 bnx2x_attn_int_asserted(bp
, asserted
);
4733 bnx2x_attn_int_deasserted(bp
, deasserted
);
4736 void bnx2x_igu_ack_sb(struct bnx2x
*bp
, u8 igu_sb_id
, u8 segment
,
4737 u16 index
, u8 op
, u8 update
)
4739 u32 igu_addr
= bp
->igu_base_addr
;
4740 igu_addr
+= (IGU_CMD_INT_ACK_BASE
+ igu_sb_id
)*8;
4741 bnx2x_igu_ack_sb_gen(bp
, igu_sb_id
, segment
, index
, op
, update
,
4745 static void bnx2x_update_eq_prod(struct bnx2x
*bp
, u16 prod
)
4747 /* No memory barriers */
4748 storm_memset_eq_prod(bp
, prod
, BP_FUNC(bp
));
4749 mmiowb(); /* keep prod updates ordered */
4752 static int bnx2x_cnic_handle_cfc_del(struct bnx2x
*bp
, u32 cid
,
4753 union event_ring_elem
*elem
)
4755 u8 err
= elem
->message
.error
;
4757 if (!bp
->cnic_eth_dev
.starting_cid
||
4758 (cid
< bp
->cnic_eth_dev
.starting_cid
&&
4759 cid
!= bp
->cnic_eth_dev
.iscsi_l2_cid
))
4762 DP(BNX2X_MSG_SP
, "got delete ramrod for CNIC CID %d\n", cid
);
4764 if (unlikely(err
)) {
4766 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4768 bnx2x_panic_dump(bp
);
4770 bnx2x_cnic_cfc_comp(bp
, cid
, err
);
4774 static void bnx2x_handle_mcast_eqe(struct bnx2x
*bp
)
4776 struct bnx2x_mcast_ramrod_params rparam
;
4779 memset(&rparam
, 0, sizeof(rparam
));
4781 rparam
.mcast_obj
= &bp
->mcast_obj
;
4783 netif_addr_lock_bh(bp
->dev
);
4785 /* Clear pending state for the last command */
4786 bp
->mcast_obj
.raw
.clear_pending(&bp
->mcast_obj
.raw
);
4788 /* If there are pending mcast commands - send them */
4789 if (bp
->mcast_obj
.check_pending(&bp
->mcast_obj
)) {
4790 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_CONT
);
4792 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4796 netif_addr_unlock_bh(bp
->dev
);
4799 static void bnx2x_handle_classification_eqe(struct bnx2x
*bp
,
4800 union event_ring_elem
*elem
)
4802 unsigned long ramrod_flags
= 0;
4804 u32 cid
= elem
->message
.data
.eth_event
.echo
& BNX2X_SWCID_MASK
;
4805 struct bnx2x_vlan_mac_obj
*vlan_mac_obj
;
4807 /* Always push next commands out, don't wait here */
4808 __set_bit(RAMROD_CONT
, &ramrod_flags
);
4810 switch (elem
->message
.data
.eth_event
.echo
>> BNX2X_SWCID_SHIFT
) {
4811 case BNX2X_FILTER_MAC_PENDING
:
4812 DP(BNX2X_MSG_SP
, "Got SETUP_MAC completions\n");
4813 if (CNIC_LOADED(bp
) && (cid
== BNX2X_ISCSI_ETH_CID(bp
)))
4814 vlan_mac_obj
= &bp
->iscsi_l2_mac_obj
;
4816 vlan_mac_obj
= &bp
->sp_objs
[cid
].mac_obj
;
4819 case BNX2X_FILTER_MCAST_PENDING
:
4820 DP(BNX2X_MSG_SP
, "Got SETUP_MCAST completions\n");
4821 /* This is only relevant for 57710 where multicast MACs are
4822 * configured as unicast MACs using the same ramrod.
4824 bnx2x_handle_mcast_eqe(bp
);
4827 BNX2X_ERR("Unsupported classification command: %d\n",
4828 elem
->message
.data
.eth_event
.echo
);
4832 rc
= vlan_mac_obj
->complete(bp
, vlan_mac_obj
, elem
, &ramrod_flags
);
4835 BNX2X_ERR("Failed to schedule new commands: %d\n", rc
);
4837 DP(BNX2X_MSG_SP
, "Scheduled next pending commands...\n");
4841 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
);
4843 static void bnx2x_handle_rx_mode_eqe(struct bnx2x
*bp
)
4845 netif_addr_lock_bh(bp
->dev
);
4847 clear_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
4849 /* Send rx_mode command again if was requested */
4850 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
))
4851 bnx2x_set_storm_rx_mode(bp
);
4852 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
,
4854 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
4855 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
,
4857 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
4859 netif_addr_unlock_bh(bp
->dev
);
4862 static void bnx2x_after_afex_vif_lists(struct bnx2x
*bp
,
4863 union event_ring_elem
*elem
)
4865 if (elem
->message
.data
.vif_list_event
.echo
== VIF_LIST_RULE_GET
) {
4867 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4868 elem
->message
.data
.vif_list_event
.func_bit_map
);
4869 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_LISTGET_ACK
,
4870 elem
->message
.data
.vif_list_event
.func_bit_map
);
4871 } else if (elem
->message
.data
.vif_list_event
.echo
==
4872 VIF_LIST_RULE_SET
) {
4873 DP(BNX2X_MSG_SP
, "afex: ramrod completed VIF LIST_SET\n");
4874 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_LISTSET_ACK
, 0);
4878 /* called with rtnl_lock */
4879 static void bnx2x_after_function_update(struct bnx2x
*bp
)
4882 struct bnx2x_fastpath
*fp
;
4883 struct bnx2x_queue_state_params queue_params
= {NULL
};
4884 struct bnx2x_queue_update_params
*q_update_params
=
4885 &queue_params
.params
.update
;
4887 /* Send Q update command with afex vlan removal values for all Qs */
4888 queue_params
.cmd
= BNX2X_Q_CMD_UPDATE
;
4890 /* set silent vlan removal values according to vlan mode */
4891 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG
,
4892 &q_update_params
->update_flags
);
4893 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM
,
4894 &q_update_params
->update_flags
);
4895 __set_bit(RAMROD_COMP_WAIT
, &queue_params
.ramrod_flags
);
4897 /* in access mode mark mask and value are 0 to strip all vlans */
4898 if (bp
->afex_vlan_mode
== FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE
) {
4899 q_update_params
->silent_removal_value
= 0;
4900 q_update_params
->silent_removal_mask
= 0;
4902 q_update_params
->silent_removal_value
=
4903 (bp
->afex_def_vlan_tag
& VLAN_VID_MASK
);
4904 q_update_params
->silent_removal_mask
= VLAN_VID_MASK
;
4907 for_each_eth_queue(bp
, q
) {
4908 /* Set the appropriate Queue object */
4910 queue_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
4912 /* send the ramrod */
4913 rc
= bnx2x_queue_state_change(bp
, &queue_params
);
4915 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4920 fp
= &bp
->fp
[FCOE_IDX(bp
)];
4921 queue_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
4923 /* clear pending completion bit */
4924 __clear_bit(RAMROD_COMP_WAIT
, &queue_params
.ramrod_flags
);
4926 /* mark latest Q bit */
4927 smp_mb__before_clear_bit();
4928 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
, &bp
->sp_state
);
4929 smp_mb__after_clear_bit();
4931 /* send Q update ramrod for FCoE Q */
4932 rc
= bnx2x_queue_state_change(bp
, &queue_params
);
4934 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4937 /* If no FCoE ring - ACK MCP now */
4938 bnx2x_link_report(bp
);
4939 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_VIFSET_ACK
, 0);
4943 static struct bnx2x_queue_sp_obj
*bnx2x_cid_to_q_obj(
4944 struct bnx2x
*bp
, u32 cid
)
4946 DP(BNX2X_MSG_SP
, "retrieving fp from cid %d\n", cid
);
4948 if (CNIC_LOADED(bp
) && (cid
== BNX2X_FCOE_ETH_CID(bp
)))
4949 return &bnx2x_fcoe_sp_obj(bp
, q_obj
);
4951 return &bp
->sp_objs
[CID_TO_FP(cid
, bp
)].q_obj
;
4954 static void bnx2x_eq_int(struct bnx2x
*bp
)
4956 u16 hw_cons
, sw_cons
, sw_prod
;
4957 union event_ring_elem
*elem
;
4961 int rc
, spqe_cnt
= 0;
4962 struct bnx2x_queue_sp_obj
*q_obj
;
4963 struct bnx2x_func_sp_obj
*f_obj
= &bp
->func_obj
;
4964 struct bnx2x_raw_obj
*rss_raw
= &bp
->rss_conf_obj
.raw
;
4966 hw_cons
= le16_to_cpu(*bp
->eq_cons_sb
);
4968 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4969 * when we get the the next-page we nned to adjust so the loop
4970 * condition below will be met. The next element is the size of a
4971 * regular element and hence incrementing by 1
4973 if ((hw_cons
& EQ_DESC_MAX_PAGE
) == EQ_DESC_MAX_PAGE
)
4976 /* This function may never run in parallel with itself for a
4977 * specific bp, thus there is no need in "paired" read memory
4980 sw_cons
= bp
->eq_cons
;
4981 sw_prod
= bp
->eq_prod
;
4983 DP(BNX2X_MSG_SP
, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4984 hw_cons
, sw_cons
, atomic_read(&bp
->eq_spq_left
));
4986 for (; sw_cons
!= hw_cons
;
4987 sw_prod
= NEXT_EQ_IDX(sw_prod
), sw_cons
= NEXT_EQ_IDX(sw_cons
)) {
4990 elem
= &bp
->eq_ring
[EQ_DESC(sw_cons
)];
4992 rc
= bnx2x_iov_eq_sp_event(bp
, elem
);
4994 DP(BNX2X_MSG_IOV
, "bnx2x_iov_eq_sp_event returned %d\n",
4998 cid
= SW_CID(elem
->message
.data
.cfc_del_event
.cid
);
4999 opcode
= elem
->message
.opcode
;
5002 /* handle eq element */
5004 case EVENT_RING_OPCODE_VF_PF_CHANNEL
:
5005 DP(BNX2X_MSG_IOV
, "vf pf channel element on eq\n");
5006 bnx2x_vf_mbx(bp
, &elem
->message
.data
.vf_pf_event
);
5009 case EVENT_RING_OPCODE_STAT_QUERY
:
5010 DP(BNX2X_MSG_SP
| BNX2X_MSG_STATS
,
5011 "got statistics comp event %d\n",
5013 /* nothing to do with stats comp */
5016 case EVENT_RING_OPCODE_CFC_DEL
:
5017 /* handle according to cid range */
5019 * we may want to verify here that the bp state is
5023 "got delete ramrod for MULTI[%d]\n", cid
);
5025 if (CNIC_LOADED(bp
) &&
5026 !bnx2x_cnic_handle_cfc_del(bp
, cid
, elem
))
5029 q_obj
= bnx2x_cid_to_q_obj(bp
, cid
);
5031 if (q_obj
->complete_cmd(bp
, q_obj
, BNX2X_Q_CMD_CFC_DEL
))
5038 case EVENT_RING_OPCODE_STOP_TRAFFIC
:
5039 DP(BNX2X_MSG_SP
| BNX2X_MSG_DCB
, "got STOP TRAFFIC\n");
5040 if (f_obj
->complete_cmd(bp
, f_obj
,
5041 BNX2X_F_CMD_TX_STOP
))
5043 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_PAUSED
);
5046 case EVENT_RING_OPCODE_START_TRAFFIC
:
5047 DP(BNX2X_MSG_SP
| BNX2X_MSG_DCB
, "got START TRAFFIC\n");
5048 if (f_obj
->complete_cmd(bp
, f_obj
,
5049 BNX2X_F_CMD_TX_START
))
5051 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_RELEASED
);
5054 case EVENT_RING_OPCODE_FUNCTION_UPDATE
:
5055 echo
= elem
->message
.data
.function_update_event
.echo
;
5056 if (echo
== SWITCH_UPDATE
) {
5057 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
5058 "got FUNC_SWITCH_UPDATE ramrod\n");
5059 if (f_obj
->complete_cmd(
5060 bp
, f_obj
, BNX2X_F_CMD_SWITCH_UPDATE
))
5064 DP(BNX2X_MSG_SP
| BNX2X_MSG_MCP
,
5065 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5066 f_obj
->complete_cmd(bp
, f_obj
,
5067 BNX2X_F_CMD_AFEX_UPDATE
);
5069 /* We will perform the Queues update from
5070 * sp_rtnl task as all Queue SP operations
5071 * should run under rtnl_lock.
5073 smp_mb__before_clear_bit();
5074 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE
,
5075 &bp
->sp_rtnl_state
);
5076 smp_mb__after_clear_bit();
5078 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
5083 case EVENT_RING_OPCODE_AFEX_VIF_LISTS
:
5084 f_obj
->complete_cmd(bp
, f_obj
,
5085 BNX2X_F_CMD_AFEX_VIFLISTS
);
5086 bnx2x_after_afex_vif_lists(bp
, elem
);
5088 case EVENT_RING_OPCODE_FUNCTION_START
:
5089 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
5090 "got FUNC_START ramrod\n");
5091 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_START
))
5096 case EVENT_RING_OPCODE_FUNCTION_STOP
:
5097 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
5098 "got FUNC_STOP ramrod\n");
5099 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_STOP
))
5105 switch (opcode
| bp
->state
) {
5106 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
5108 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
5109 BNX2X_STATE_OPENING_WAIT4_PORT
):
5110 cid
= elem
->message
.data
.eth_event
.echo
&
5112 DP(BNX2X_MSG_SP
, "got RSS_UPDATE ramrod. CID %d\n",
5114 rss_raw
->clear_pending(rss_raw
);
5117 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_OPEN
):
5118 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_DIAG
):
5119 case (EVENT_RING_OPCODE_SET_MAC
|
5120 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5121 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
5123 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
5125 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
5126 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5127 DP(BNX2X_MSG_SP
, "got (un)set mac ramrod\n");
5128 bnx2x_handle_classification_eqe(bp
, elem
);
5131 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
5133 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
5135 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
5136 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5137 DP(BNX2X_MSG_SP
, "got mcast ramrod\n");
5138 bnx2x_handle_mcast_eqe(bp
);
5141 case (EVENT_RING_OPCODE_FILTERS_RULES
|
5143 case (EVENT_RING_OPCODE_FILTERS_RULES
|
5145 case (EVENT_RING_OPCODE_FILTERS_RULES
|
5146 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5147 DP(BNX2X_MSG_SP
, "got rx_mode ramrod\n");
5148 bnx2x_handle_rx_mode_eqe(bp
);
5151 /* unknown event log error and continue */
5152 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5153 elem
->message
.opcode
, bp
->state
);
5159 smp_mb__before_atomic_inc();
5160 atomic_add(spqe_cnt
, &bp
->eq_spq_left
);
5162 bp
->eq_cons
= sw_cons
;
5163 bp
->eq_prod
= sw_prod
;
5164 /* Make sure that above mem writes were issued towards the memory */
5167 /* update producer */
5168 bnx2x_update_eq_prod(bp
, bp
->eq_prod
);
5171 static void bnx2x_sp_task(struct work_struct
*work
)
5173 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_task
.work
);
5175 DP(BNX2X_MSG_SP
, "sp task invoked\n");
5177 /* make sure the atomic interupt_occurred has been written */
5179 if (atomic_read(&bp
->interrupt_occurred
)) {
5181 /* what work needs to be performed? */
5182 u16 status
= bnx2x_update_dsb_idx(bp
);
5184 DP(BNX2X_MSG_SP
, "status %x\n", status
);
5185 DP(BNX2X_MSG_SP
, "setting interrupt_occurred to 0\n");
5186 atomic_set(&bp
->interrupt_occurred
, 0);
5189 if (status
& BNX2X_DEF_SB_ATT_IDX
) {
5191 status
&= ~BNX2X_DEF_SB_ATT_IDX
;
5194 /* SP events: STAT_QUERY and others */
5195 if (status
& BNX2X_DEF_SB_IDX
) {
5196 struct bnx2x_fastpath
*fp
= bnx2x_fcoe_fp(bp
);
5198 if (FCOE_INIT(bp
) &&
5199 (bnx2x_has_rx_work(fp
) || bnx2x_has_tx_work(fp
))) {
5200 /* Prevent local bottom-halves from running as
5201 * we are going to change the local NAPI list.
5204 napi_schedule(&bnx2x_fcoe(bp
, napi
));
5208 /* Handle EQ completions */
5210 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
,
5211 le16_to_cpu(bp
->def_idx
), IGU_INT_NOP
, 1);
5213 status
&= ~BNX2X_DEF_SB_IDX
;
5216 /* if status is non zero then perhaps something went wrong */
5217 if (unlikely(status
))
5219 "got an unknown interrupt! (status 0x%x)\n", status
);
5221 /* ack status block only if something was actually handled */
5222 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, ATTENTION_ID
,
5223 le16_to_cpu(bp
->def_att_idx
), IGU_INT_ENABLE
, 1);
5227 /* must be called after the EQ processing (since eq leads to sriov
5228 * ramrod completion flows).
5229 * This flow may have been scheduled by the arrival of a ramrod
5230 * completion, or by the sriov code rescheduling itself.
5232 bnx2x_iov_sp_task(bp
);
5234 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5235 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
,
5237 bnx2x_link_report(bp
);
5238 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_VIFSET_ACK
, 0);
5242 irqreturn_t
bnx2x_msix_sp_int(int irq
, void *dev_instance
)
5244 struct net_device
*dev
= dev_instance
;
5245 struct bnx2x
*bp
= netdev_priv(dev
);
5247 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0,
5248 IGU_INT_DISABLE
, 0);
5250 #ifdef BNX2X_STOP_ON_ERROR
5251 if (unlikely(bp
->panic
))
5255 if (CNIC_LOADED(bp
)) {
5256 struct cnic_ops
*c_ops
;
5259 c_ops
= rcu_dereference(bp
->cnic_ops
);
5261 c_ops
->cnic_handler(bp
->cnic_data
, NULL
);
5265 /* schedule sp task to perform default status block work, ack
5266 * attentions and enable interrupts.
5268 bnx2x_schedule_sp_task(bp
);
5273 /* end of slow path */
5276 void bnx2x_drv_pulse(struct bnx2x
*bp
)
5278 SHMEM_WR(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_pulse_mb
,
5279 bp
->fw_drv_pulse_wr_seq
);
5282 static void bnx2x_timer(unsigned long data
)
5284 struct bnx2x
*bp
= (struct bnx2x
*) data
;
5286 if (!netif_running(bp
->dev
))
5291 int mb_idx
= BP_FW_MB_IDX(bp
);
5295 ++bp
->fw_drv_pulse_wr_seq
;
5296 bp
->fw_drv_pulse_wr_seq
&= DRV_PULSE_SEQ_MASK
;
5297 /* TBD - add SYSTEM_TIME */
5298 drv_pulse
= bp
->fw_drv_pulse_wr_seq
;
5299 bnx2x_drv_pulse(bp
);
5301 mcp_pulse
= (SHMEM_RD(bp
, func_mb
[mb_idx
].mcp_pulse_mb
) &
5302 MCP_PULSE_SEQ_MASK
);
5303 /* The delta between driver pulse and mcp response
5304 * should be 1 (before mcp response) or 0 (after mcp response)
5306 if ((drv_pulse
!= mcp_pulse
) &&
5307 (drv_pulse
!= ((mcp_pulse
+ 1) & MCP_PULSE_SEQ_MASK
))) {
5308 /* someone lost a heartbeat... */
5309 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5310 drv_pulse
, mcp_pulse
);
5314 if (bp
->state
== BNX2X_STATE_OPEN
)
5315 bnx2x_stats_handle(bp
, STATS_EVENT_UPDATE
);
5317 /* sample pf vf bulletin board for new posts from pf */
5319 bnx2x_sample_bulletin(bp
);
5321 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5324 /* end of Statistics */
5329 * nic init service functions
5332 static void bnx2x_fill(struct bnx2x
*bp
, u32 addr
, int fill
, u32 len
)
5335 if (!(len
%4) && !(addr
%4))
5336 for (i
= 0; i
< len
; i
+= 4)
5337 REG_WR(bp
, addr
+ i
, fill
);
5339 for (i
= 0; i
< len
; i
++)
5340 REG_WR8(bp
, addr
+ i
, fill
);
5344 /* helper: writes FP SP data to FW - data_size in dwords */
5345 static void bnx2x_wr_fp_sb_data(struct bnx2x
*bp
,
5351 for (index
= 0; index
< data_size
; index
++)
5352 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
5353 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id
) +
5355 *(sb_data_p
+ index
));
5358 static void bnx2x_zero_fp_sb(struct bnx2x
*bp
, int fw_sb_id
)
5362 struct hc_status_block_data_e2 sb_data_e2
;
5363 struct hc_status_block_data_e1x sb_data_e1x
;
5365 /* disable the function first */
5366 if (!CHIP_IS_E1x(bp
)) {
5367 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
5368 sb_data_e2
.common
.state
= SB_DISABLED
;
5369 sb_data_e2
.common
.p_func
.vf_valid
= false;
5370 sb_data_p
= (u32
*)&sb_data_e2
;
5371 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
5373 memset(&sb_data_e1x
, 0,
5374 sizeof(struct hc_status_block_data_e1x
));
5375 sb_data_e1x
.common
.state
= SB_DISABLED
;
5376 sb_data_e1x
.common
.p_func
.vf_valid
= false;
5377 sb_data_p
= (u32
*)&sb_data_e1x
;
5378 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
5380 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
5382 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5383 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id
), 0,
5384 CSTORM_STATUS_BLOCK_SIZE
);
5385 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5386 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id
), 0,
5387 CSTORM_SYNC_BLOCK_SIZE
);
5390 /* helper: writes SP SB data to FW */
5391 static void bnx2x_wr_sp_sb_data(struct bnx2x
*bp
,
5392 struct hc_sp_status_block_data
*sp_sb_data
)
5394 int func
= BP_FUNC(bp
);
5396 for (i
= 0; i
< sizeof(struct hc_sp_status_block_data
)/sizeof(u32
); i
++)
5397 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
5398 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
) +
5400 *((u32
*)sp_sb_data
+ i
));
5403 static void bnx2x_zero_sp_sb(struct bnx2x
*bp
)
5405 int func
= BP_FUNC(bp
);
5406 struct hc_sp_status_block_data sp_sb_data
;
5407 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
5409 sp_sb_data
.state
= SB_DISABLED
;
5410 sp_sb_data
.p_func
.vf_valid
= false;
5412 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
5414 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5415 CSTORM_SP_STATUS_BLOCK_OFFSET(func
), 0,
5416 CSTORM_SP_STATUS_BLOCK_SIZE
);
5417 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5418 CSTORM_SP_SYNC_BLOCK_OFFSET(func
), 0,
5419 CSTORM_SP_SYNC_BLOCK_SIZE
);
5424 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm
*hc_sm
,
5425 int igu_sb_id
, int igu_seg_id
)
5427 hc_sm
->igu_sb_id
= igu_sb_id
;
5428 hc_sm
->igu_seg_id
= igu_seg_id
;
5429 hc_sm
->timer_value
= 0xFF;
5430 hc_sm
->time_to_expire
= 0xFFFFFFFF;
5434 /* allocates state machine ids. */
5435 static void bnx2x_map_sb_state_machines(struct hc_index_data
*index_data
)
5437 /* zero out state machine indices */
5439 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5442 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5443 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5444 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5445 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5449 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
|=
5450 SM_RX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5453 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
|=
5454 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5455 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
|=
5456 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5457 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
|=
5458 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5459 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
|=
5460 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5463 void bnx2x_init_sb(struct bnx2x
*bp
, dma_addr_t mapping
, int vfid
,
5464 u8 vf_valid
, int fw_sb_id
, int igu_sb_id
)
5468 struct hc_status_block_data_e2 sb_data_e2
;
5469 struct hc_status_block_data_e1x sb_data_e1x
;
5470 struct hc_status_block_sm
*hc_sm_p
;
5474 if (CHIP_INT_MODE_IS_BC(bp
))
5475 igu_seg_id
= HC_SEG_ACCESS_NORM
;
5477 igu_seg_id
= IGU_SEG_ACCESS_NORM
;
5479 bnx2x_zero_fp_sb(bp
, fw_sb_id
);
5481 if (!CHIP_IS_E1x(bp
)) {
5482 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
5483 sb_data_e2
.common
.state
= SB_ENABLED
;
5484 sb_data_e2
.common
.p_func
.pf_id
= BP_FUNC(bp
);
5485 sb_data_e2
.common
.p_func
.vf_id
= vfid
;
5486 sb_data_e2
.common
.p_func
.vf_valid
= vf_valid
;
5487 sb_data_e2
.common
.p_func
.vnic_id
= BP_VN(bp
);
5488 sb_data_e2
.common
.same_igu_sb_1b
= true;
5489 sb_data_e2
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
5490 sb_data_e2
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
5491 hc_sm_p
= sb_data_e2
.common
.state_machine
;
5492 sb_data_p
= (u32
*)&sb_data_e2
;
5493 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
5494 bnx2x_map_sb_state_machines(sb_data_e2
.index_data
);
5496 memset(&sb_data_e1x
, 0,
5497 sizeof(struct hc_status_block_data_e1x
));
5498 sb_data_e1x
.common
.state
= SB_ENABLED
;
5499 sb_data_e1x
.common
.p_func
.pf_id
= BP_FUNC(bp
);
5500 sb_data_e1x
.common
.p_func
.vf_id
= 0xff;
5501 sb_data_e1x
.common
.p_func
.vf_valid
= false;
5502 sb_data_e1x
.common
.p_func
.vnic_id
= BP_VN(bp
);
5503 sb_data_e1x
.common
.same_igu_sb_1b
= true;
5504 sb_data_e1x
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
5505 sb_data_e1x
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
5506 hc_sm_p
= sb_data_e1x
.common
.state_machine
;
5507 sb_data_p
= (u32
*)&sb_data_e1x
;
5508 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
5509 bnx2x_map_sb_state_machines(sb_data_e1x
.index_data
);
5512 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_RX_ID
],
5513 igu_sb_id
, igu_seg_id
);
5514 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_TX_ID
],
5515 igu_sb_id
, igu_seg_id
);
5517 DP(NETIF_MSG_IFUP
, "Init FW SB %d\n", fw_sb_id
);
5519 /* write indecies to HW */
5520 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
5523 static void bnx2x_update_coalesce_sb(struct bnx2x
*bp
, u8 fw_sb_id
,
5524 u16 tx_usec
, u16 rx_usec
)
5526 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
, HC_INDEX_ETH_RX_CQ_CONS
,
5528 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
5529 HC_INDEX_ETH_TX_CQ_CONS_COS0
, false,
5531 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
5532 HC_INDEX_ETH_TX_CQ_CONS_COS1
, false,
5534 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
5535 HC_INDEX_ETH_TX_CQ_CONS_COS2
, false,
5539 static void bnx2x_init_def_sb(struct bnx2x
*bp
)
5541 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
5542 dma_addr_t mapping
= bp
->def_status_blk_mapping
;
5543 int igu_sp_sb_index
;
5545 int port
= BP_PORT(bp
);
5546 int func
= BP_FUNC(bp
);
5547 int reg_offset
, reg_offset_en5
;
5550 struct hc_sp_status_block_data sp_sb_data
;
5551 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
5553 if (CHIP_INT_MODE_IS_BC(bp
)) {
5554 igu_sp_sb_index
= DEF_SB_IGU_ID
;
5555 igu_seg_id
= HC_SEG_ACCESS_DEF
;
5557 igu_sp_sb_index
= bp
->igu_dsb_id
;
5558 igu_seg_id
= IGU_SEG_ACCESS_DEF
;
5562 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
5563 atten_status_block
);
5564 def_sb
->atten_status_block
.status_block_id
= igu_sp_sb_index
;
5568 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
5569 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
5570 reg_offset_en5
= (port
? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0
:
5571 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0
);
5572 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
5574 /* take care of sig[0]..sig[4] */
5575 for (sindex
= 0; sindex
< 4; sindex
++)
5576 bp
->attn_group
[index
].sig
[sindex
] =
5577 REG_RD(bp
, reg_offset
+ sindex
*0x4 + 0x10*index
);
5579 if (!CHIP_IS_E1x(bp
))
5581 * enable5 is separate from the rest of the registers,
5582 * and therefore the address skip is 4
5583 * and not 16 between the different groups
5585 bp
->attn_group
[index
].sig
[4] = REG_RD(bp
,
5586 reg_offset_en5
+ 0x4*index
);
5588 bp
->attn_group
[index
].sig
[4] = 0;
5591 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
5592 reg_offset
= (port
? HC_REG_ATTN_MSG1_ADDR_L
:
5593 HC_REG_ATTN_MSG0_ADDR_L
);
5595 REG_WR(bp
, reg_offset
, U64_LO(section
));
5596 REG_WR(bp
, reg_offset
+ 4, U64_HI(section
));
5597 } else if (!CHIP_IS_E1x(bp
)) {
5598 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_L
, U64_LO(section
));
5599 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_H
, U64_HI(section
));
5602 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
5605 bnx2x_zero_sp_sb(bp
);
5607 sp_sb_data
.state
= SB_ENABLED
;
5608 sp_sb_data
.host_sb_addr
.lo
= U64_LO(section
);
5609 sp_sb_data
.host_sb_addr
.hi
= U64_HI(section
);
5610 sp_sb_data
.igu_sb_id
= igu_sp_sb_index
;
5611 sp_sb_data
.igu_seg_id
= igu_seg_id
;
5612 sp_sb_data
.p_func
.pf_id
= func
;
5613 sp_sb_data
.p_func
.vnic_id
= BP_VN(bp
);
5614 sp_sb_data
.p_func
.vf_id
= 0xff;
5616 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
5618 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0, IGU_INT_ENABLE
, 0);
5621 void bnx2x_update_coalesce(struct bnx2x
*bp
)
5625 for_each_eth_queue(bp
, i
)
5626 bnx2x_update_coalesce_sb(bp
, bp
->fp
[i
].fw_sb_id
,
5627 bp
->tx_ticks
, bp
->rx_ticks
);
5630 static void bnx2x_init_sp_ring(struct bnx2x
*bp
)
5632 spin_lock_init(&bp
->spq_lock
);
5633 atomic_set(&bp
->cq_spq_left
, MAX_SPQ_PENDING
);
5635 bp
->spq_prod_idx
= 0;
5636 bp
->dsb_sp_prod
= BNX2X_SP_DSB_INDEX
;
5637 bp
->spq_prod_bd
= bp
->spq
;
5638 bp
->spq_last_bd
= bp
->spq_prod_bd
+ MAX_SP_DESC_CNT
;
5641 static void bnx2x_init_eq_ring(struct bnx2x
*bp
)
5644 for (i
= 1; i
<= NUM_EQ_PAGES
; i
++) {
5645 union event_ring_elem
*elem
=
5646 &bp
->eq_ring
[EQ_DESC_CNT_PAGE
* i
- 1];
5648 elem
->next_page
.addr
.hi
=
5649 cpu_to_le32(U64_HI(bp
->eq_mapping
+
5650 BCM_PAGE_SIZE
* (i
% NUM_EQ_PAGES
)));
5651 elem
->next_page
.addr
.lo
=
5652 cpu_to_le32(U64_LO(bp
->eq_mapping
+
5653 BCM_PAGE_SIZE
*(i
% NUM_EQ_PAGES
)));
5656 bp
->eq_prod
= NUM_EQ_DESC
;
5657 bp
->eq_cons_sb
= BNX2X_EQ_INDEX
;
5658 /* we want a warning message before it gets rought... */
5659 atomic_set(&bp
->eq_spq_left
,
5660 min_t(int, MAX_SP_DESC_CNT
- MAX_SPQ_PENDING
, NUM_EQ_DESC
) - 1);
5664 /* called with netif_addr_lock_bh() */
5665 void bnx2x_set_q_rx_mode(struct bnx2x
*bp
, u8 cl_id
,
5666 unsigned long rx_mode_flags
,
5667 unsigned long rx_accept_flags
,
5668 unsigned long tx_accept_flags
,
5669 unsigned long ramrod_flags
)
5671 struct bnx2x_rx_mode_ramrod_params ramrod_param
;
5674 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
5676 /* Prepare ramrod parameters */
5677 ramrod_param
.cid
= 0;
5678 ramrod_param
.cl_id
= cl_id
;
5679 ramrod_param
.rx_mode_obj
= &bp
->rx_mode_obj
;
5680 ramrod_param
.func_id
= BP_FUNC(bp
);
5682 ramrod_param
.pstate
= &bp
->sp_state
;
5683 ramrod_param
.state
= BNX2X_FILTER_RX_MODE_PENDING
;
5685 ramrod_param
.rdata
= bnx2x_sp(bp
, rx_mode_rdata
);
5686 ramrod_param
.rdata_mapping
= bnx2x_sp_mapping(bp
, rx_mode_rdata
);
5688 set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
5690 ramrod_param
.ramrod_flags
= ramrod_flags
;
5691 ramrod_param
.rx_mode_flags
= rx_mode_flags
;
5693 ramrod_param
.rx_accept_flags
= rx_accept_flags
;
5694 ramrod_param
.tx_accept_flags
= tx_accept_flags
;
5696 rc
= bnx2x_config_rx_mode(bp
, &ramrod_param
);
5698 BNX2X_ERR("Set rx_mode %d failed\n", bp
->rx_mode
);
5703 /* called with netif_addr_lock_bh() */
5704 void bnx2x_set_storm_rx_mode(struct bnx2x
*bp
)
5706 unsigned long rx_mode_flags
= 0, ramrod_flags
= 0;
5707 unsigned long rx_accept_flags
= 0, tx_accept_flags
= 0;
5711 /* Configure rx_mode of FCoE Queue */
5712 __set_bit(BNX2X_RX_MODE_FCOE_ETH
, &rx_mode_flags
);
5714 switch (bp
->rx_mode
) {
5715 case BNX2X_RX_MODE_NONE
:
5717 * 'drop all' supersedes any accept flags that may have been
5718 * passed to the function.
5721 case BNX2X_RX_MODE_NORMAL
:
5722 __set_bit(BNX2X_ACCEPT_UNICAST
, &rx_accept_flags
);
5723 __set_bit(BNX2X_ACCEPT_MULTICAST
, &rx_accept_flags
);
5724 __set_bit(BNX2X_ACCEPT_BROADCAST
, &rx_accept_flags
);
5726 /* internal switching mode */
5727 __set_bit(BNX2X_ACCEPT_UNICAST
, &tx_accept_flags
);
5728 __set_bit(BNX2X_ACCEPT_MULTICAST
, &tx_accept_flags
);
5729 __set_bit(BNX2X_ACCEPT_BROADCAST
, &tx_accept_flags
);
5732 case BNX2X_RX_MODE_ALLMULTI
:
5733 __set_bit(BNX2X_ACCEPT_UNICAST
, &rx_accept_flags
);
5734 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &rx_accept_flags
);
5735 __set_bit(BNX2X_ACCEPT_BROADCAST
, &rx_accept_flags
);
5737 /* internal switching mode */
5738 __set_bit(BNX2X_ACCEPT_UNICAST
, &tx_accept_flags
);
5739 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &tx_accept_flags
);
5740 __set_bit(BNX2X_ACCEPT_BROADCAST
, &tx_accept_flags
);
5743 case BNX2X_RX_MODE_PROMISC
:
5744 /* According to deffinition of SI mode, iface in promisc mode
5745 * should receive matched and unmatched (in resolution of port)
5748 __set_bit(BNX2X_ACCEPT_UNMATCHED
, &rx_accept_flags
);
5749 __set_bit(BNX2X_ACCEPT_UNICAST
, &rx_accept_flags
);
5750 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &rx_accept_flags
);
5751 __set_bit(BNX2X_ACCEPT_BROADCAST
, &rx_accept_flags
);
5753 /* internal switching mode */
5754 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &tx_accept_flags
);
5755 __set_bit(BNX2X_ACCEPT_BROADCAST
, &tx_accept_flags
);
5758 __set_bit(BNX2X_ACCEPT_ALL_UNICAST
, &tx_accept_flags
);
5760 __set_bit(BNX2X_ACCEPT_UNICAST
, &tx_accept_flags
);
5764 BNX2X_ERR("Unknown rx_mode: %d\n", bp
->rx_mode
);
5768 if (bp
->rx_mode
!= BNX2X_RX_MODE_NONE
) {
5769 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &rx_accept_flags
);
5770 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &tx_accept_flags
);
5773 __set_bit(RAMROD_RX
, &ramrod_flags
);
5774 __set_bit(RAMROD_TX
, &ramrod_flags
);
5776 bnx2x_set_q_rx_mode(bp
, bp
->fp
->cl_id
, rx_mode_flags
, rx_accept_flags
,
5777 tx_accept_flags
, ramrod_flags
);
5780 static void bnx2x_init_internal_common(struct bnx2x
*bp
)
5786 * In switch independent mode, the TSTORM needs to accept
5787 * packets that failed classification, since approximate match
5788 * mac addresses aren't written to NIG LLH
5790 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
5791 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET
, 2);
5792 else if (!CHIP_IS_E1(bp
)) /* 57710 doesn't support MF */
5793 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
5794 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET
, 0);
5796 /* Zero this manually as its initialization is
5797 currently missing in the initTool */
5798 for (i
= 0; i
< (USTORM_AGG_DATA_SIZE
>> 2); i
++)
5799 REG_WR(bp
, BAR_USTRORM_INTMEM
+
5800 USTORM_AGG_DATA_OFFSET
+ i
* 4, 0);
5801 if (!CHIP_IS_E1x(bp
)) {
5802 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_IGU_MODE_OFFSET
,
5803 CHIP_INT_MODE_IS_BC(bp
) ?
5804 HC_IGU_BC_MODE
: HC_IGU_NBC_MODE
);
5808 static void bnx2x_init_internal(struct bnx2x
*bp
, u32 load_code
)
5810 switch (load_code
) {
5811 case FW_MSG_CODE_DRV_LOAD_COMMON
:
5812 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
:
5813 bnx2x_init_internal_common(bp
);
5816 case FW_MSG_CODE_DRV_LOAD_PORT
:
5820 case FW_MSG_CODE_DRV_LOAD_FUNCTION
:
5821 /* internal memory per function is
5822 initialized inside bnx2x_pf_init */
5826 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code
);
5831 static inline u8
bnx2x_fp_igu_sb_id(struct bnx2x_fastpath
*fp
)
5833 return fp
->bp
->igu_base_sb
+ fp
->index
+ CNIC_SUPPORT(fp
->bp
);
5836 static inline u8
bnx2x_fp_fw_sb_id(struct bnx2x_fastpath
*fp
)
5838 return fp
->bp
->base_fw_ndsb
+ fp
->index
+ CNIC_SUPPORT(fp
->bp
);
5841 static u8
bnx2x_fp_cl_id(struct bnx2x_fastpath
*fp
)
5843 if (CHIP_IS_E1x(fp
->bp
))
5844 return BP_L_ID(fp
->bp
) + fp
->index
;
5845 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5846 return bnx2x_fp_igu_sb_id(fp
);
5849 static void bnx2x_init_eth_fp(struct bnx2x
*bp
, int fp_idx
)
5851 struct bnx2x_fastpath
*fp
= &bp
->fp
[fp_idx
];
5853 unsigned long q_type
= 0;
5854 u32 cids
[BNX2X_MULTI_TX_COS
] = { 0 };
5855 fp
->rx_queue
= fp_idx
;
5857 fp
->cl_id
= bnx2x_fp_cl_id(fp
);
5858 fp
->fw_sb_id
= bnx2x_fp_fw_sb_id(fp
);
5859 fp
->igu_sb_id
= bnx2x_fp_igu_sb_id(fp
);
5860 /* qZone id equals to FW (per path) client id */
5861 fp
->cl_qzone_id
= bnx2x_fp_qzone_id(fp
);
5864 fp
->ustorm_rx_prods_offset
= bnx2x_rx_ustorm_prods_offset(fp
);
5866 /* Setup SB indicies */
5867 fp
->rx_cons_sb
= BNX2X_RX_SB_INDEX
;
5869 /* Configure Queue State object */
5870 __set_bit(BNX2X_Q_TYPE_HAS_RX
, &q_type
);
5871 __set_bit(BNX2X_Q_TYPE_HAS_TX
, &q_type
);
5873 BUG_ON(fp
->max_cos
> BNX2X_MULTI_TX_COS
);
5876 for_each_cos_in_tx_queue(fp
, cos
) {
5877 bnx2x_init_txdata(bp
, fp
->txdata_ptr
[cos
],
5878 CID_COS_TO_TX_ONLY_CID(fp
->cid
, cos
, bp
),
5879 FP_COS_TO_TXQ(fp
, cos
, bp
),
5880 BNX2X_TX_SB_INDEX_BASE
+ cos
, fp
);
5881 cids
[cos
] = fp
->txdata_ptr
[cos
]->cid
;
5884 /* nothing more for vf to do here */
5888 bnx2x_init_sb(bp
, fp
->status_blk_mapping
, BNX2X_VF_ID_INVALID
, false,
5889 fp
->fw_sb_id
, fp
->igu_sb_id
);
5890 bnx2x_update_fpsb_idx(fp
);
5891 bnx2x_init_queue_obj(bp
, &bnx2x_sp_obj(bp
, fp
).q_obj
, fp
->cl_id
, cids
,
5892 fp
->max_cos
, BP_FUNC(bp
), bnx2x_sp(bp
, q_rdata
),
5893 bnx2x_sp_mapping(bp
, q_rdata
), q_type
);
5896 * Configure classification DBs: Always enable Tx switching
5898 bnx2x_init_vlan_mac_fp_objs(fp
, BNX2X_OBJ_TYPE_RX_TX
);
5901 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5902 fp_idx
, bp
, fp
->status_blk
.e2_sb
, fp
->cl_id
, fp
->fw_sb_id
,
5906 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata
*txdata
)
5910 for (i
= 1; i
<= NUM_TX_RINGS
; i
++) {
5911 struct eth_tx_next_bd
*tx_next_bd
=
5912 &txdata
->tx_desc_ring
[TX_DESC_CNT
* i
- 1].next_bd
;
5914 tx_next_bd
->addr_hi
=
5915 cpu_to_le32(U64_HI(txdata
->tx_desc_mapping
+
5916 BCM_PAGE_SIZE
*(i
% NUM_TX_RINGS
)));
5917 tx_next_bd
->addr_lo
=
5918 cpu_to_le32(U64_LO(txdata
->tx_desc_mapping
+
5919 BCM_PAGE_SIZE
*(i
% NUM_TX_RINGS
)));
5922 SET_FLAG(txdata
->tx_db
.data
.header
.header
, DOORBELL_HDR_DB_TYPE
, 1);
5923 txdata
->tx_db
.data
.zero_fill1
= 0;
5924 txdata
->tx_db
.data
.prod
= 0;
5926 txdata
->tx_pkt_prod
= 0;
5927 txdata
->tx_pkt_cons
= 0;
5928 txdata
->tx_bd_prod
= 0;
5929 txdata
->tx_bd_cons
= 0;
5933 static void bnx2x_init_tx_rings_cnic(struct bnx2x
*bp
)
5937 for_each_tx_queue_cnic(bp
, i
)
5938 bnx2x_init_tx_ring_one(bp
->fp
[i
].txdata_ptr
[0]);
5940 static void bnx2x_init_tx_rings(struct bnx2x
*bp
)
5945 for_each_eth_queue(bp
, i
)
5946 for_each_cos_in_tx_queue(&bp
->fp
[i
], cos
)
5947 bnx2x_init_tx_ring_one(bp
->fp
[i
].txdata_ptr
[cos
]);
5950 void bnx2x_nic_init_cnic(struct bnx2x
*bp
)
5953 bnx2x_init_fcoe_fp(bp
);
5955 bnx2x_init_sb(bp
, bp
->cnic_sb_mapping
,
5956 BNX2X_VF_ID_INVALID
, false,
5957 bnx2x_cnic_fw_sb_id(bp
), bnx2x_cnic_igu_sb_id(bp
));
5959 /* ensure status block indices were read */
5961 bnx2x_init_rx_rings_cnic(bp
);
5962 bnx2x_init_tx_rings_cnic(bp
);
5969 void bnx2x_nic_init(struct bnx2x
*bp
, u32 load_code
)
5973 for_each_eth_queue(bp
, i
)
5974 bnx2x_init_eth_fp(bp
, i
);
5976 /* ensure status block indices were read */
5978 bnx2x_init_rx_rings(bp
);
5979 bnx2x_init_tx_rings(bp
);
5984 /* Initialize MOD_ABS interrupts */
5985 bnx2x_init_mod_abs_int(bp
, &bp
->link_vars
, bp
->common
.chip_id
,
5986 bp
->common
.shmem_base
, bp
->common
.shmem2_base
,
5989 bnx2x_init_def_sb(bp
);
5990 bnx2x_update_dsb_idx(bp
);
5991 bnx2x_init_sp_ring(bp
);
5992 bnx2x_init_eq_ring(bp
);
5993 bnx2x_init_internal(bp
, load_code
);
5995 bnx2x_stats_init(bp
);
5997 /* flush all before enabling interrupts */
6001 bnx2x_int_enable(bp
);
6003 /* Check for SPIO5 */
6004 bnx2x_attn_int_deasserted0(bp
,
6005 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ BP_PORT(bp
)*4) &
6006 AEU_INPUTS_ATTN_BITS_SPIO5
);
6009 /* end of nic init */
6012 * gzip service functions
6015 static int bnx2x_gunzip_init(struct bnx2x
*bp
)
6017 bp
->gunzip_buf
= dma_alloc_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
,
6018 &bp
->gunzip_mapping
, GFP_KERNEL
);
6019 if (bp
->gunzip_buf
== NULL
)
6022 bp
->strm
= kmalloc(sizeof(*bp
->strm
), GFP_KERNEL
);
6023 if (bp
->strm
== NULL
)
6026 bp
->strm
->workspace
= vmalloc(zlib_inflate_workspacesize());
6027 if (bp
->strm
->workspace
== NULL
)
6037 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
6038 bp
->gunzip_mapping
);
6039 bp
->gunzip_buf
= NULL
;
6042 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6046 static void bnx2x_gunzip_end(struct bnx2x
*bp
)
6049 vfree(bp
->strm
->workspace
);
6054 if (bp
->gunzip_buf
) {
6055 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
6056 bp
->gunzip_mapping
);
6057 bp
->gunzip_buf
= NULL
;
6061 static int bnx2x_gunzip(struct bnx2x
*bp
, const u8
*zbuf
, int len
)
6065 /* check gzip header */
6066 if ((zbuf
[0] != 0x1f) || (zbuf
[1] != 0x8b) || (zbuf
[2] != Z_DEFLATED
)) {
6067 BNX2X_ERR("Bad gzip header\n");
6075 if (zbuf
[3] & FNAME
)
6076 while ((zbuf
[n
++] != 0) && (n
< len
));
6078 bp
->strm
->next_in
= (typeof(bp
->strm
->next_in
))zbuf
+ n
;
6079 bp
->strm
->avail_in
= len
- n
;
6080 bp
->strm
->next_out
= bp
->gunzip_buf
;
6081 bp
->strm
->avail_out
= FW_BUF_SIZE
;
6083 rc
= zlib_inflateInit2(bp
->strm
, -MAX_WBITS
);
6087 rc
= zlib_inflate(bp
->strm
, Z_FINISH
);
6088 if ((rc
!= Z_OK
) && (rc
!= Z_STREAM_END
))
6089 netdev_err(bp
->dev
, "Firmware decompression error: %s\n",
6092 bp
->gunzip_outlen
= (FW_BUF_SIZE
- bp
->strm
->avail_out
);
6093 if (bp
->gunzip_outlen
& 0x3)
6095 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6097 bp
->gunzip_outlen
>>= 2;
6099 zlib_inflateEnd(bp
->strm
);
6101 if (rc
== Z_STREAM_END
)
6107 /* nic load/unload */
6110 * General service functions
6113 /* send a NIG loopback debug packet */
6114 static void bnx2x_lb_pckt(struct bnx2x
*bp
)
6118 /* Ethernet source and destination addresses */
6119 wb_write
[0] = 0x55555555;
6120 wb_write
[1] = 0x55555555;
6121 wb_write
[2] = 0x20; /* SOP */
6122 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
6124 /* NON-IP protocol */
6125 wb_write
[0] = 0x09000000;
6126 wb_write
[1] = 0x55555555;
6127 wb_write
[2] = 0x10; /* EOP, eop_bvalid = 0 */
6128 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
6131 /* some of the internal memories
6132 * are not directly readable from the driver
6133 * to test them we send debug packets
6135 static int bnx2x_int_mem_test(struct bnx2x
*bp
)
6141 if (CHIP_REV_IS_FPGA(bp
))
6143 else if (CHIP_REV_IS_EMUL(bp
))
6148 /* Disable inputs of parser neighbor blocks */
6149 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
6150 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
6151 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
6152 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
6154 /* Write 0 to parser credits for CFC search request */
6155 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
6157 /* send Ethernet packet */
6160 /* TODO do i reset NIG statistic? */
6161 /* Wait until NIG register shows 1 packet of size 0x10 */
6162 count
= 1000 * factor
;
6165 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
6166 val
= *bnx2x_sp(bp
, wb_data
[0]);
6174 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
6178 /* Wait until PRS register shows 1 packet */
6179 count
= 1000 * factor
;
6181 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
6189 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
6193 /* Reset and init BRB, PRS */
6194 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
6196 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
6198 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
6199 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
6201 DP(NETIF_MSG_HW
, "part2\n");
6203 /* Disable inputs of parser neighbor blocks */
6204 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
6205 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
6206 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
6207 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
6209 /* Write 0 to parser credits for CFC search request */
6210 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
6212 /* send 10 Ethernet packets */
6213 for (i
= 0; i
< 10; i
++)
6216 /* Wait until NIG register shows 10 + 1
6217 packets of size 11*0x10 = 0xb0 */
6218 count
= 1000 * factor
;
6221 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
6222 val
= *bnx2x_sp(bp
, wb_data
[0]);
6230 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
6234 /* Wait until PRS register shows 2 packets */
6235 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
6237 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
6239 /* Write 1 to parser credits for CFC search request */
6240 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x1);
6242 /* Wait until PRS register shows 3 packets */
6243 msleep(10 * factor
);
6244 /* Wait until NIG register shows 1 packet of size 0x10 */
6245 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
6247 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
6249 /* clear NIG EOP FIFO */
6250 for (i
= 0; i
< 11; i
++)
6251 REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_FIFO
);
6252 val
= REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_EMPTY
);
6254 BNX2X_ERR("clear of NIG failed\n");
6258 /* Reset and init BRB, PRS, NIG */
6259 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
6261 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
6263 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
6264 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
6265 if (!CNIC_SUPPORT(bp
))
6267 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
6269 /* Enable inputs of parser neighbor blocks */
6270 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x7fffffff);
6271 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x1);
6272 REG_WR(bp
, CFC_REG_DEBUG0
, 0x0);
6273 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x1);
6275 DP(NETIF_MSG_HW
, "done\n");
6280 static void bnx2x_enable_blocks_attention(struct bnx2x
*bp
)
6284 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
6285 if (!CHIP_IS_E1x(bp
))
6286 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0x40);
6288 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0);
6289 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
6290 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
6292 * mask read length error interrupts in brb for parser
6293 * (parsing unit and 'checksum and crc' unit)
6294 * these errors are legal (PU reads fixed length and CAC can cause
6295 * read length error on truncated packets)
6297 REG_WR(bp
, BRB1_REG_BRB1_INT_MASK
, 0xFC00);
6298 REG_WR(bp
, QM_REG_QM_INT_MASK
, 0);
6299 REG_WR(bp
, TM_REG_TM_INT_MASK
, 0);
6300 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_0
, 0);
6301 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_1
, 0);
6302 REG_WR(bp
, XCM_REG_XCM_INT_MASK
, 0);
6303 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6304 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6305 REG_WR(bp
, USDM_REG_USDM_INT_MASK_0
, 0);
6306 REG_WR(bp
, USDM_REG_USDM_INT_MASK_1
, 0);
6307 REG_WR(bp
, UCM_REG_UCM_INT_MASK
, 0);
6308 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6309 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6310 REG_WR(bp
, GRCBASE_UPB
+ PB_REG_PB_INT_MASK
, 0);
6311 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_0
, 0);
6312 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_1
, 0);
6313 REG_WR(bp
, CCM_REG_CCM_INT_MASK
, 0);
6314 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6315 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6317 val
= PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
|
6318 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
|
6319 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
;
6320 if (!CHIP_IS_E1x(bp
))
6321 val
|= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
|
6322 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED
;
6323 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
, val
);
6325 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_0
, 0);
6326 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_1
, 0);
6327 REG_WR(bp
, TCM_REG_TCM_INT_MASK
, 0);
6328 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6330 if (!CHIP_IS_E1x(bp
))
6331 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6332 REG_WR(bp
, TSEM_REG_TSEM_INT_MASK_1
, 0x07ff);
6334 REG_WR(bp
, CDU_REG_CDU_INT_MASK
, 0);
6335 REG_WR(bp
, DMAE_REG_DMAE_INT_MASK
, 0);
6336 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6337 REG_WR(bp
, PBF_REG_PBF_INT_MASK
, 0x18); /* bit 3,4 masked */
6340 static void bnx2x_reset_common(struct bnx2x
*bp
)
6345 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
6348 if (CHIP_IS_E3(bp
)) {
6349 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
6350 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
6353 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
, val
);
6356 static void bnx2x_setup_dmae(struct bnx2x
*bp
)
6359 spin_lock_init(&bp
->dmae_lock
);
6362 static void bnx2x_init_pxp(struct bnx2x
*bp
)
6365 int r_order
, w_order
;
6367 pcie_capability_read_word(bp
->pdev
, PCI_EXP_DEVCTL
, &devctl
);
6368 DP(NETIF_MSG_HW
, "read 0x%x from devctl\n", devctl
);
6369 w_order
= ((devctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
6371 r_order
= ((devctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
6373 DP(NETIF_MSG_HW
, "force read order to %d\n", bp
->mrrs
);
6377 bnx2x_init_pxp_arb(bp
, r_order
, w_order
);
6380 static void bnx2x_setup_fan_failure_detection(struct bnx2x
*bp
)
6390 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config2
) &
6391 SHARED_HW_CFG_FAN_FAILURE_MASK
;
6393 if (val
== SHARED_HW_CFG_FAN_FAILURE_ENABLED
)
6397 * The fan failure mechanism is usually related to the PHY type since
6398 * the power consumption of the board is affected by the PHY. Currently,
6399 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6401 else if (val
== SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE
)
6402 for (port
= PORT_0
; port
< PORT_MAX
; port
++) {
6404 bnx2x_fan_failure_det_req(
6406 bp
->common
.shmem_base
,
6407 bp
->common
.shmem2_base
,
6411 DP(NETIF_MSG_HW
, "fan detection setting: %d\n", is_required
);
6413 if (is_required
== 0)
6416 /* Fan failure is indicated by SPIO 5 */
6417 bnx2x_set_spio(bp
, MISC_SPIO_SPIO5
, MISC_SPIO_INPUT_HI_Z
);
6419 /* set to active low mode */
6420 val
= REG_RD(bp
, MISC_REG_SPIO_INT
);
6421 val
|= (MISC_SPIO_SPIO5
<< MISC_SPIO_INT_OLD_SET_POS
);
6422 REG_WR(bp
, MISC_REG_SPIO_INT
, val
);
6424 /* enable interrupt to signal the IGU */
6425 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
6426 val
|= MISC_SPIO_SPIO5
;
6427 REG_WR(bp
, MISC_REG_SPIO_EVENT_EN
, val
);
6430 void bnx2x_pf_disable(struct bnx2x
*bp
)
6432 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
6433 val
&= ~IGU_PF_CONF_FUNC_EN
;
6435 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
6436 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 0);
6437 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 0);
6440 static void bnx2x__common_init_phy(struct bnx2x
*bp
)
6442 u32 shmem_base
[2], shmem2_base
[2];
6443 /* Avoid common init in case MFW supports LFA */
6444 if (SHMEM2_RD(bp
, size
) >
6445 (u32
)offsetof(struct shmem2_region
, lfa_host_addr
[BP_PORT(bp
)]))
6447 shmem_base
[0] = bp
->common
.shmem_base
;
6448 shmem2_base
[0] = bp
->common
.shmem2_base
;
6449 if (!CHIP_IS_E1x(bp
)) {
6451 SHMEM2_RD(bp
, other_shmem_base_addr
);
6453 SHMEM2_RD(bp
, other_shmem2_base_addr
);
6455 bnx2x_acquire_phy_lock(bp
);
6456 bnx2x_common_init_phy(bp
, shmem_base
, shmem2_base
,
6457 bp
->common
.chip_id
);
6458 bnx2x_release_phy_lock(bp
);
6462 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6464 * @bp: driver handle
6466 static int bnx2x_init_hw_common(struct bnx2x
*bp
)
6470 DP(NETIF_MSG_HW
, "starting common init func %d\n", BP_ABS_FUNC(bp
));
6473 * take the UNDI lock to protect undi_unload flow from accessing
6474 * registers while we're resetting the chip
6476 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
6478 bnx2x_reset_common(bp
);
6479 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0xffffffff);
6482 if (CHIP_IS_E3(bp
)) {
6483 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
6484 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
6486 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
, val
);
6488 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
6490 bnx2x_init_block(bp
, BLOCK_MISC
, PHASE_COMMON
);
6492 if (!CHIP_IS_E1x(bp
)) {
6496 * 4-port mode or 2-port mode we need to turn of master-enable
6497 * for everyone, after that, turn it back on for self.
6498 * so, we disregard multi-function or not, and always disable
6499 * for all functions on the given path, this means 0,2,4,6 for
6500 * path 0 and 1,3,5,7 for path 1
6502 for (abs_func_id
= BP_PATH(bp
);
6503 abs_func_id
< E2_FUNC_MAX
*2; abs_func_id
+= 2) {
6504 if (abs_func_id
== BP_ABS_FUNC(bp
)) {
6506 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
,
6511 bnx2x_pretend_func(bp
, abs_func_id
);
6512 /* clear pf enable */
6513 bnx2x_pf_disable(bp
);
6514 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
6518 bnx2x_init_block(bp
, BLOCK_PXP
, PHASE_COMMON
);
6519 if (CHIP_IS_E1(bp
)) {
6520 /* enable HW interrupt from PXP on USDM overflow
6521 bit 16 on INT_MASK_0 */
6522 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
6525 bnx2x_init_block(bp
, BLOCK_PXP2
, PHASE_COMMON
);
6529 REG_WR(bp
, PXP2_REG_RQ_QM_ENDIAN_M
, 1);
6530 REG_WR(bp
, PXP2_REG_RQ_TM_ENDIAN_M
, 1);
6531 REG_WR(bp
, PXP2_REG_RQ_SRC_ENDIAN_M
, 1);
6532 REG_WR(bp
, PXP2_REG_RQ_CDU_ENDIAN_M
, 1);
6533 REG_WR(bp
, PXP2_REG_RQ_DBG_ENDIAN_M
, 1);
6534 /* make sure this value is 0 */
6535 REG_WR(bp
, PXP2_REG_RQ_HC_ENDIAN_M
, 0);
6537 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6538 REG_WR(bp
, PXP2_REG_RD_QM_SWAP_MODE
, 1);
6539 REG_WR(bp
, PXP2_REG_RD_TM_SWAP_MODE
, 1);
6540 REG_WR(bp
, PXP2_REG_RD_SRC_SWAP_MODE
, 1);
6541 REG_WR(bp
, PXP2_REG_RD_CDURD_SWAP_MODE
, 1);
6544 bnx2x_ilt_init_page_size(bp
, INITOP_SET
);
6546 if (CHIP_REV_IS_FPGA(bp
) && CHIP_IS_E1H(bp
))
6547 REG_WR(bp
, PXP2_REG_PGL_TAGS_LIMIT
, 0x1);
6549 /* let the HW do it's magic ... */
6551 /* finish PXP init */
6552 val
= REG_RD(bp
, PXP2_REG_RQ_CFG_DONE
);
6554 BNX2X_ERR("PXP2 CFG failed\n");
6557 val
= REG_RD(bp
, PXP2_REG_RD_INIT_DONE
);
6559 BNX2X_ERR("PXP2 RD_INIT failed\n");
6563 /* Timers bug workaround E2 only. We need to set the entire ILT to
6564 * have entries with value "0" and valid bit on.
6565 * This needs to be done by the first PF that is loaded in a path
6566 * (i.e. common phase)
6568 if (!CHIP_IS_E1x(bp
)) {
6569 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6570 * (i.e. vnic3) to start even if it is marked as "scan-off".
6571 * This occurs when a different function (func2,3) is being marked
6572 * as "scan-off". Real-life scenario for example: if a driver is being
6573 * load-unloaded while func6,7 are down. This will cause the timer to access
6574 * the ilt, translate to a logical address and send a request to read/write.
6575 * Since the ilt for the function that is down is not valid, this will cause
6576 * a translation error which is unrecoverable.
6577 * The Workaround is intended to make sure that when this happens nothing fatal
6578 * will occur. The workaround:
6579 * 1. First PF driver which loads on a path will:
6580 * a. After taking the chip out of reset, by using pretend,
6581 * it will write "0" to the following registers of
6583 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6584 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6585 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6586 * And for itself it will write '1' to
6587 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6588 * dmae-operations (writing to pram for example.)
6589 * note: can be done for only function 6,7 but cleaner this
6591 * b. Write zero+valid to the entire ILT.
6592 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6593 * VNIC3 (of that port). The range allocated will be the
6594 * entire ILT. This is needed to prevent ILT range error.
6595 * 2. Any PF driver load flow:
6596 * a. ILT update with the physical addresses of the allocated
6598 * b. Wait 20msec. - note that this timeout is needed to make
6599 * sure there are no requests in one of the PXP internal
6600 * queues with "old" ILT addresses.
6601 * c. PF enable in the PGLC.
6602 * d. Clear the was_error of the PF in the PGLC. (could have
6603 * occured while driver was down)
6604 * e. PF enable in the CFC (WEAK + STRONG)
6605 * f. Timers scan enable
6606 * 3. PF driver unload flow:
6607 * a. Clear the Timers scan_en.
6608 * b. Polling for scan_on=0 for that PF.
6609 * c. Clear the PF enable bit in the PXP.
6610 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6611 * e. Write zero+valid to all ILT entries (The valid bit must
6613 * f. If this is VNIC 3 of a port then also init
6614 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6615 * to the last enrty in the ILT.
6618 * Currently the PF error in the PGLC is non recoverable.
6619 * In the future the there will be a recovery routine for this error.
6620 * Currently attention is masked.
6621 * Having an MCP lock on the load/unload process does not guarantee that
6622 * there is no Timer disable during Func6/7 enable. This is because the
6623 * Timers scan is currently being cleared by the MCP on FLR.
6624 * Step 2.d can be done only for PF6/7 and the driver can also check if
6625 * there is error before clearing it. But the flow above is simpler and
6627 * All ILT entries are written by zero+valid and not just PF6/7
6628 * ILT entries since in the future the ILT entries allocation for
6629 * PF-s might be dynamic.
6631 struct ilt_client_info ilt_cli
;
6632 struct bnx2x_ilt ilt
;
6633 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
6634 memset(&ilt
, 0, sizeof(struct bnx2x_ilt
));
6636 /* initialize dummy TM client */
6638 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
6639 ilt_cli
.client_num
= ILT_CLIENT_TM
;
6641 /* Step 1: set zeroes to all ilt page entries with valid bit on
6642 * Step 2: set the timers first/last ilt entry to point
6643 * to the entire range to prevent ILT range error for 3rd/4th
6644 * vnic (this code assumes existance of the vnic)
6646 * both steps performed by call to bnx2x_ilt_client_init_op()
6647 * with dummy TM client
6649 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6650 * and his brother are split registers
6652 bnx2x_pretend_func(bp
, (BP_PATH(bp
) + 6));
6653 bnx2x_ilt_client_init_op_ilt(bp
, &ilt
, &ilt_cli
, INITOP_CLEAR
);
6654 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
6656 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN
, BNX2X_PXP_DRAM_ALIGN
);
6657 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_RD
, BNX2X_PXP_DRAM_ALIGN
);
6658 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_SEL
, 1);
6662 REG_WR(bp
, PXP2_REG_RQ_DISABLE_INPUTS
, 0);
6663 REG_WR(bp
, PXP2_REG_RD_DISABLE_INPUTS
, 0);
6665 if (!CHIP_IS_E1x(bp
)) {
6666 int factor
= CHIP_REV_IS_EMUL(bp
) ? 1000 :
6667 (CHIP_REV_IS_FPGA(bp
) ? 400 : 0);
6668 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, PHASE_COMMON
);
6670 bnx2x_init_block(bp
, BLOCK_ATC
, PHASE_COMMON
);
6672 /* let the HW do it's magic ... */
6675 val
= REG_RD(bp
, ATC_REG_ATC_INIT_DONE
);
6676 } while (factor
-- && (val
!= 1));
6679 BNX2X_ERR("ATC_INIT failed\n");
6684 bnx2x_init_block(bp
, BLOCK_DMAE
, PHASE_COMMON
);
6686 bnx2x_iov_init_dmae(bp
);
6688 /* clean the DMAE memory */
6690 bnx2x_init_fill(bp
, TSEM_REG_PRAM
, 0, 8, 1);
6692 bnx2x_init_block(bp
, BLOCK_TCM
, PHASE_COMMON
);
6694 bnx2x_init_block(bp
, BLOCK_UCM
, PHASE_COMMON
);
6696 bnx2x_init_block(bp
, BLOCK_CCM
, PHASE_COMMON
);
6698 bnx2x_init_block(bp
, BLOCK_XCM
, PHASE_COMMON
);
6700 bnx2x_read_dmae(bp
, XSEM_REG_PASSIVE_BUFFER
, 3);
6701 bnx2x_read_dmae(bp
, CSEM_REG_PASSIVE_BUFFER
, 3);
6702 bnx2x_read_dmae(bp
, TSEM_REG_PASSIVE_BUFFER
, 3);
6703 bnx2x_read_dmae(bp
, USEM_REG_PASSIVE_BUFFER
, 3);
6705 bnx2x_init_block(bp
, BLOCK_QM
, PHASE_COMMON
);
6708 /* QM queues pointers table */
6709 bnx2x_qm_init_ptr_table(bp
, bp
->qm_cid_count
, INITOP_SET
);
6711 /* soft reset pulse */
6712 REG_WR(bp
, QM_REG_SOFT_RESET
, 1);
6713 REG_WR(bp
, QM_REG_SOFT_RESET
, 0);
6715 if (CNIC_SUPPORT(bp
))
6716 bnx2x_init_block(bp
, BLOCK_TM
, PHASE_COMMON
);
6718 bnx2x_init_block(bp
, BLOCK_DORQ
, PHASE_COMMON
);
6719 REG_WR(bp
, DORQ_REG_DPM_CID_OFST
, BNX2X_DB_SHIFT
);
6720 if (!CHIP_REV_IS_SLOW(bp
))
6721 /* enable hw interrupt from doorbell Q */
6722 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
6724 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
6726 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
6727 REG_WR(bp
, PRS_REG_A_PRSU_20
, 0xf);
6729 if (!CHIP_IS_E1(bp
))
6730 REG_WR(bp
, PRS_REG_E1HOV_MODE
, bp
->path_has_ovlan
);
6732 if (!CHIP_IS_E1x(bp
) && !CHIP_IS_E3B0(bp
)) {
6733 if (IS_MF_AFEX(bp
)) {
6734 /* configure that VNTag and VLAN headers must be
6735 * received in afex mode
6737 REG_WR(bp
, PRS_REG_HDRS_AFTER_BASIC
, 0xE);
6738 REG_WR(bp
, PRS_REG_MUST_HAVE_HDRS
, 0xA);
6739 REG_WR(bp
, PRS_REG_HDRS_AFTER_TAG_0
, 0x6);
6740 REG_WR(bp
, PRS_REG_TAG_ETHERTYPE_0
, 0x8926);
6741 REG_WR(bp
, PRS_REG_TAG_LEN_0
, 0x4);
6743 /* Bit-map indicating which L2 hdrs may appear
6744 * after the basic Ethernet header
6746 REG_WR(bp
, PRS_REG_HDRS_AFTER_BASIC
,
6747 bp
->path_has_ovlan
? 7 : 6);
6751 bnx2x_init_block(bp
, BLOCK_TSDM
, PHASE_COMMON
);
6752 bnx2x_init_block(bp
, BLOCK_CSDM
, PHASE_COMMON
);
6753 bnx2x_init_block(bp
, BLOCK_USDM
, PHASE_COMMON
);
6754 bnx2x_init_block(bp
, BLOCK_XSDM
, PHASE_COMMON
);
6756 if (!CHIP_IS_E1x(bp
)) {
6757 /* reset VFC memories */
6758 REG_WR(bp
, TSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
6759 VFC_MEMORIES_RST_REG_CAM_RST
|
6760 VFC_MEMORIES_RST_REG_RAM_RST
);
6761 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
6762 VFC_MEMORIES_RST_REG_CAM_RST
|
6763 VFC_MEMORIES_RST_REG_RAM_RST
);
6768 bnx2x_init_block(bp
, BLOCK_TSEM
, PHASE_COMMON
);
6769 bnx2x_init_block(bp
, BLOCK_USEM
, PHASE_COMMON
);
6770 bnx2x_init_block(bp
, BLOCK_CSEM
, PHASE_COMMON
);
6771 bnx2x_init_block(bp
, BLOCK_XSEM
, PHASE_COMMON
);
6774 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
6776 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
,
6779 bnx2x_init_block(bp
, BLOCK_UPB
, PHASE_COMMON
);
6780 bnx2x_init_block(bp
, BLOCK_XPB
, PHASE_COMMON
);
6781 bnx2x_init_block(bp
, BLOCK_PBF
, PHASE_COMMON
);
6783 if (!CHIP_IS_E1x(bp
)) {
6784 if (IS_MF_AFEX(bp
)) {
6785 /* configure that VNTag and VLAN headers must be
6788 REG_WR(bp
, PBF_REG_HDRS_AFTER_BASIC
, 0xE);
6789 REG_WR(bp
, PBF_REG_MUST_HAVE_HDRS
, 0xA);
6790 REG_WR(bp
, PBF_REG_HDRS_AFTER_TAG_0
, 0x6);
6791 REG_WR(bp
, PBF_REG_TAG_ETHERTYPE_0
, 0x8926);
6792 REG_WR(bp
, PBF_REG_TAG_LEN_0
, 0x4);
6794 REG_WR(bp
, PBF_REG_HDRS_AFTER_BASIC
,
6795 bp
->path_has_ovlan
? 7 : 6);
6799 REG_WR(bp
, SRC_REG_SOFT_RST
, 1);
6801 bnx2x_init_block(bp
, BLOCK_SRC
, PHASE_COMMON
);
6803 if (CNIC_SUPPORT(bp
)) {
6804 REG_WR(bp
, SRC_REG_KEYSEARCH_0
, 0x63285672);
6805 REG_WR(bp
, SRC_REG_KEYSEARCH_1
, 0x24b8f2cc);
6806 REG_WR(bp
, SRC_REG_KEYSEARCH_2
, 0x223aef9b);
6807 REG_WR(bp
, SRC_REG_KEYSEARCH_3
, 0x26001e3a);
6808 REG_WR(bp
, SRC_REG_KEYSEARCH_4
, 0x7ae91116);
6809 REG_WR(bp
, SRC_REG_KEYSEARCH_5
, 0x5ce5230b);
6810 REG_WR(bp
, SRC_REG_KEYSEARCH_6
, 0x298d8adf);
6811 REG_WR(bp
, SRC_REG_KEYSEARCH_7
, 0x6eb0ff09);
6812 REG_WR(bp
, SRC_REG_KEYSEARCH_8
, 0x1830f82f);
6813 REG_WR(bp
, SRC_REG_KEYSEARCH_9
, 0x01e46be7);
6815 REG_WR(bp
, SRC_REG_SOFT_RST
, 0);
6817 if (sizeof(union cdu_context
) != 1024)
6818 /* we currently assume that a context is 1024 bytes */
6819 dev_alert(&bp
->pdev
->dev
,
6820 "please adjust the size of cdu_context(%ld)\n",
6821 (long)sizeof(union cdu_context
));
6823 bnx2x_init_block(bp
, BLOCK_CDU
, PHASE_COMMON
);
6824 val
= (4 << 24) + (0 << 12) + 1024;
6825 REG_WR(bp
, CDU_REG_CDU_GLOBAL_PARAMS
, val
);
6827 bnx2x_init_block(bp
, BLOCK_CFC
, PHASE_COMMON
);
6828 REG_WR(bp
, CFC_REG_INIT_REG
, 0x7FF);
6829 /* enable context validation interrupt from CFC */
6830 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
6832 /* set the thresholds to prevent CFC/CDU race */
6833 REG_WR(bp
, CFC_REG_DEBUG0
, 0x20020000);
6835 bnx2x_init_block(bp
, BLOCK_HC
, PHASE_COMMON
);
6837 if (!CHIP_IS_E1x(bp
) && BP_NOMCP(bp
))
6838 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x36);
6840 bnx2x_init_block(bp
, BLOCK_IGU
, PHASE_COMMON
);
6841 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, PHASE_COMMON
);
6843 /* Reset PCIE errors for debug */
6844 REG_WR(bp
, 0x2814, 0xffffffff);
6845 REG_WR(bp
, 0x3820, 0xffffffff);
6847 if (!CHIP_IS_E1x(bp
)) {
6848 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_CONTROL_5
,
6849 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1
|
6850 PXPCS_TL_CONTROL_5_ERR_UNSPPORT
));
6851 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC345_STAT
,
6852 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4
|
6853 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3
|
6854 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2
));
6855 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC678_STAT
,
6856 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7
|
6857 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6
|
6858 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5
));
6861 bnx2x_init_block(bp
, BLOCK_NIG
, PHASE_COMMON
);
6862 if (!CHIP_IS_E1(bp
)) {
6863 /* in E3 this done in per-port section */
6864 if (!CHIP_IS_E3(bp
))
6865 REG_WR(bp
, NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
6867 if (CHIP_IS_E1H(bp
))
6868 /* not applicable for E2 (and above ...) */
6869 REG_WR(bp
, NIG_REG_LLH_E1HOV_MODE
, IS_MF_SD(bp
));
6871 if (CHIP_REV_IS_SLOW(bp
))
6874 /* finish CFC init */
6875 val
= reg_poll(bp
, CFC_REG_LL_INIT_DONE
, 1, 100, 10);
6877 BNX2X_ERR("CFC LL_INIT failed\n");
6880 val
= reg_poll(bp
, CFC_REG_AC_INIT_DONE
, 1, 100, 10);
6882 BNX2X_ERR("CFC AC_INIT failed\n");
6885 val
= reg_poll(bp
, CFC_REG_CAM_INIT_DONE
, 1, 100, 10);
6887 BNX2X_ERR("CFC CAM_INIT failed\n");
6890 REG_WR(bp
, CFC_REG_DEBUG0
, 0);
6892 if (CHIP_IS_E1(bp
)) {
6893 /* read NIG statistic
6894 to see if this is our first up since powerup */
6895 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
6896 val
= *bnx2x_sp(bp
, wb_data
[0]);
6898 /* do internal memory self test */
6899 if ((val
== 0) && bnx2x_int_mem_test(bp
)) {
6900 BNX2X_ERR("internal mem self test failed\n");
6905 bnx2x_setup_fan_failure_detection(bp
);
6907 /* clear PXP2 attentions */
6908 REG_RD(bp
, PXP2_REG_PXP2_INT_STS_CLR_0
);
6910 bnx2x_enable_blocks_attention(bp
);
6911 bnx2x_enable_blocks_parity(bp
);
6913 if (!BP_NOMCP(bp
)) {
6914 if (CHIP_IS_E1x(bp
))
6915 bnx2x__common_init_phy(bp
);
6917 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6923 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6925 * @bp: driver handle
6927 static int bnx2x_init_hw_common_chip(struct bnx2x
*bp
)
6929 int rc
= bnx2x_init_hw_common(bp
);
6934 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6936 bnx2x__common_init_phy(bp
);
6941 static int bnx2x_init_hw_port(struct bnx2x
*bp
)
6943 int port
= BP_PORT(bp
);
6944 int init_phase
= port
? PHASE_PORT1
: PHASE_PORT0
;
6949 DP(NETIF_MSG_HW
, "starting port init port %d\n", port
);
6951 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
6953 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
6954 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
6955 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
6957 /* Timers bug workaround: disables the pf_master bit in pglue at
6958 * common phase, we need to enable it here before any dmae access are
6959 * attempted. Therefore we manually added the enable-master to the
6960 * port phase (it also happens in the function phase)
6962 if (!CHIP_IS_E1x(bp
))
6963 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
6965 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
6966 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
6967 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
6968 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
6970 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
6971 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
6972 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
6973 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
6975 /* QM cid (connection) count */
6976 bnx2x_qm_init_cid_count(bp
, bp
->qm_cid_count
, INITOP_SET
);
6978 if (CNIC_SUPPORT(bp
)) {
6979 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
6980 REG_WR(bp
, TM_REG_LIN0_SCAN_TIME
+ port
*4, 20);
6981 REG_WR(bp
, TM_REG_LIN0_MAX_ACTIVE_CID
+ port
*4, 31);
6984 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
6986 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
6988 if (CHIP_IS_E1(bp
) || CHIP_IS_E1H(bp
)) {
6991 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 160 : 246);
6992 else if (bp
->dev
->mtu
> 4096) {
6993 if (bp
->flags
& ONE_PORT_FLAG
)
6997 /* (24*1024 + val*4)/256 */
6998 low
= 96 + (val
/64) +
6999 ((val
% 64) ? 1 : 0);
7002 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 80 : 160);
7003 high
= low
+ 56; /* 14*1024/256 */
7004 REG_WR(bp
, BRB1_REG_PAUSE_LOW_THRESHOLD_0
+ port
*4, low
);
7005 REG_WR(bp
, BRB1_REG_PAUSE_HIGH_THRESHOLD_0
+ port
*4, high
);
7008 if (CHIP_MODE_IS_4_PORT(bp
))
7009 REG_WR(bp
, (BP_PORT(bp
) ?
7010 BRB1_REG_MAC_GUARANTIED_1
:
7011 BRB1_REG_MAC_GUARANTIED_0
), 40);
7014 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
7015 if (CHIP_IS_E3B0(bp
)) {
7016 if (IS_MF_AFEX(bp
)) {
7017 /* configure headers for AFEX mode */
7018 REG_WR(bp
, BP_PORT(bp
) ?
7019 PRS_REG_HDRS_AFTER_BASIC_PORT_1
:
7020 PRS_REG_HDRS_AFTER_BASIC_PORT_0
, 0xE);
7021 REG_WR(bp
, BP_PORT(bp
) ?
7022 PRS_REG_HDRS_AFTER_TAG_0_PORT_1
:
7023 PRS_REG_HDRS_AFTER_TAG_0_PORT_0
, 0x6);
7024 REG_WR(bp
, BP_PORT(bp
) ?
7025 PRS_REG_MUST_HAVE_HDRS_PORT_1
:
7026 PRS_REG_MUST_HAVE_HDRS_PORT_0
, 0xA);
7028 /* Ovlan exists only if we are in multi-function +
7029 * switch-dependent mode, in switch-independent there
7030 * is no ovlan headers
7032 REG_WR(bp
, BP_PORT(bp
) ?
7033 PRS_REG_HDRS_AFTER_BASIC_PORT_1
:
7034 PRS_REG_HDRS_AFTER_BASIC_PORT_0
,
7035 (bp
->path_has_ovlan
? 7 : 6));
7039 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
7040 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
7041 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
7042 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
7044 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
7045 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
7046 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
7047 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
7049 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
7050 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
7052 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
7054 if (CHIP_IS_E1x(bp
)) {
7055 /* configure PBF to work without PAUSE mtu 9000 */
7056 REG_WR(bp
, PBF_REG_P0_PAUSE_ENABLE
+ port
*4, 0);
7058 /* update threshold */
7059 REG_WR(bp
, PBF_REG_P0_ARB_THRSH
+ port
*4, (9040/16));
7060 /* update init credit */
7061 REG_WR(bp
, PBF_REG_P0_INIT_CRD
+ port
*4, (9040/16) + 553 - 22);
7064 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 1);
7066 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 0);
7069 if (CNIC_SUPPORT(bp
))
7070 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
7072 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
7073 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
7075 if (CHIP_IS_E1(bp
)) {
7076 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
7077 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
7079 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
7081 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
7083 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
7084 /* init aeu_mask_attn_func_0/1:
7085 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
7086 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
7087 * bits 4-7 are used for "per vn group attention" */
7088 val
= IS_MF(bp
) ? 0xF7 : 0x7;
7089 /* Enable DCBX attention for all but E1 */
7090 val
|= CHIP_IS_E1(bp
) ? 0 : 0x10;
7091 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, val
);
7093 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
7095 if (!CHIP_IS_E1x(bp
)) {
7096 /* Bit-map indicating which L2 hdrs may appear after the
7097 * basic Ethernet header
7100 REG_WR(bp
, BP_PORT(bp
) ?
7101 NIG_REG_P1_HDRS_AFTER_BASIC
:
7102 NIG_REG_P0_HDRS_AFTER_BASIC
, 0xE);
7104 REG_WR(bp
, BP_PORT(bp
) ?
7105 NIG_REG_P1_HDRS_AFTER_BASIC
:
7106 NIG_REG_P0_HDRS_AFTER_BASIC
,
7107 IS_MF_SD(bp
) ? 7 : 6);
7110 REG_WR(bp
, BP_PORT(bp
) ?
7111 NIG_REG_LLH1_MF_MODE
:
7112 NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
7114 if (!CHIP_IS_E3(bp
))
7115 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4, 1);
7117 if (!CHIP_IS_E1(bp
)) {
7118 /* 0x2 disable mf_ov, 0x1 enable */
7119 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK_MF
+ port
*4,
7120 (IS_MF_SD(bp
) ? 0x1 : 0x2));
7122 if (!CHIP_IS_E1x(bp
)) {
7124 switch (bp
->mf_mode
) {
7125 case MULTI_FUNCTION_SD
:
7128 case MULTI_FUNCTION_SI
:
7129 case MULTI_FUNCTION_AFEX
:
7134 REG_WR(bp
, (BP_PORT(bp
) ? NIG_REG_LLH1_CLS_TYPE
:
7135 NIG_REG_LLH0_CLS_TYPE
), val
);
7138 REG_WR(bp
, NIG_REG_LLFC_ENABLE_0
+ port
*4, 0);
7139 REG_WR(bp
, NIG_REG_LLFC_OUT_EN_0
+ port
*4, 0);
7140 REG_WR(bp
, NIG_REG_PAUSE_ENABLE_0
+ port
*4, 1);
7145 /* If SPIO5 is set to generate interrupts, enable it for this port */
7146 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
7147 if (val
& MISC_SPIO_SPIO5
) {
7148 u32 reg_addr
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
7149 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
7150 val
= REG_RD(bp
, reg_addr
);
7151 val
|= AEU_INPUTS_ATTN_BITS_SPIO5
;
7152 REG_WR(bp
, reg_addr
, val
);
7158 static void bnx2x_ilt_wr(struct bnx2x
*bp
, u32 index
, dma_addr_t addr
)
7164 reg
= PXP2_REG_RQ_ONCHIP_AT
+ index
*8;
7166 reg
= PXP2_REG_RQ_ONCHIP_AT_B0
+ index
*8;
7168 wb_write
[0] = ONCHIP_ADDR1(addr
);
7169 wb_write
[1] = ONCHIP_ADDR2(addr
);
7170 REG_WR_DMAE(bp
, reg
, wb_write
, 2);
7173 void bnx2x_igu_clear_sb_gen(struct bnx2x
*bp
, u8 func
, u8 idu_sb_id
, bool is_pf
)
7175 u32 data
, ctl
, cnt
= 100;
7176 u32 igu_addr_data
= IGU_REG_COMMAND_REG_32LSB_DATA
;
7177 u32 igu_addr_ctl
= IGU_REG_COMMAND_REG_CTRL
;
7178 u32 igu_addr_ack
= IGU_REG_CSTORM_TYPE_0_SB_CLEANUP
+ (idu_sb_id
/32)*4;
7179 u32 sb_bit
= 1 << (idu_sb_id
%32);
7180 u32 func_encode
= func
| (is_pf
? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT
;
7181 u32 addr_encode
= IGU_CMD_E2_PROD_UPD_BASE
+ idu_sb_id
;
7183 /* Not supported in BC mode */
7184 if (CHIP_INT_MODE_IS_BC(bp
))
7187 data
= (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7188 << IGU_REGULAR_CLEANUP_TYPE_SHIFT
) |
7189 IGU_REGULAR_CLEANUP_SET
|
7190 IGU_REGULAR_BCLEANUP
;
7192 ctl
= addr_encode
<< IGU_CTRL_REG_ADDRESS_SHIFT
|
7193 func_encode
<< IGU_CTRL_REG_FID_SHIFT
|
7194 IGU_CTRL_CMD_TYPE_WR
<< IGU_CTRL_REG_TYPE_SHIFT
;
7196 DP(NETIF_MSG_HW
, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7197 data
, igu_addr_data
);
7198 REG_WR(bp
, igu_addr_data
, data
);
7201 DP(NETIF_MSG_HW
, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7203 REG_WR(bp
, igu_addr_ctl
, ctl
);
7207 /* wait for clean up to finish */
7208 while (!(REG_RD(bp
, igu_addr_ack
) & sb_bit
) && --cnt
)
7212 if (!(REG_RD(bp
, igu_addr_ack
) & sb_bit
)) {
7214 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7215 idu_sb_id
, idu_sb_id
/32, idu_sb_id
%32, cnt
);
7219 static void bnx2x_igu_clear_sb(struct bnx2x
*bp
, u8 idu_sb_id
)
7221 bnx2x_igu_clear_sb_gen(bp
, BP_FUNC(bp
), idu_sb_id
, true /*PF*/);
7224 static void bnx2x_clear_func_ilt(struct bnx2x
*bp
, u32 func
)
7226 u32 i
, base
= FUNC_ILT_BASE(func
);
7227 for (i
= base
; i
< base
+ ILT_PER_FUNC
; i
++)
7228 bnx2x_ilt_wr(bp
, i
, 0);
7232 static void bnx2x_init_searcher(struct bnx2x
*bp
)
7234 int port
= BP_PORT(bp
);
7235 bnx2x_src_init_t2(bp
, bp
->t2
, bp
->t2_mapping
, SRC_CONN_NUM
);
7236 /* T1 hash bits value determines the T1 number of entries */
7237 REG_WR(bp
, SRC_REG_NUMBER_HASH_BITS0
+ port
*4, SRC_HASH_BITS
);
7240 static inline int bnx2x_func_switch_update(struct bnx2x
*bp
, int suspend
)
7243 struct bnx2x_func_state_params func_params
= {NULL
};
7244 struct bnx2x_func_switch_update_params
*switch_update_params
=
7245 &func_params
.params
.switch_update
;
7247 /* Prepare parameters for function state transitions */
7248 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
7249 __set_bit(RAMROD_RETRY
, &func_params
.ramrod_flags
);
7251 func_params
.f_obj
= &bp
->func_obj
;
7252 func_params
.cmd
= BNX2X_F_CMD_SWITCH_UPDATE
;
7254 /* Function parameters */
7255 switch_update_params
->suspend
= suspend
;
7257 rc
= bnx2x_func_state_change(bp
, &func_params
);
7262 static int bnx2x_reset_nic_mode(struct bnx2x
*bp
)
7264 int rc
, i
, port
= BP_PORT(bp
);
7265 int vlan_en
= 0, mac_en
[NUM_MACS
];
7268 /* Close input from network */
7269 if (bp
->mf_mode
== SINGLE_FUNCTION
) {
7270 bnx2x_set_rx_filter(&bp
->link_params
, 0);
7272 vlan_en
= REG_RD(bp
, port
? NIG_REG_LLH1_FUNC_EN
:
7273 NIG_REG_LLH0_FUNC_EN
);
7274 REG_WR(bp
, port
? NIG_REG_LLH1_FUNC_EN
:
7275 NIG_REG_LLH0_FUNC_EN
, 0);
7276 for (i
= 0; i
< NUM_MACS
; i
++) {
7277 mac_en
[i
] = REG_RD(bp
, port
?
7278 (NIG_REG_LLH1_FUNC_MEM_ENABLE
+
7280 (NIG_REG_LLH0_FUNC_MEM_ENABLE
+
7282 REG_WR(bp
, port
? (NIG_REG_LLH1_FUNC_MEM_ENABLE
+
7284 (NIG_REG_LLH0_FUNC_MEM_ENABLE
+ 4 * i
), 0);
7288 /* Close BMC to host */
7289 REG_WR(bp
, port
? NIG_REG_P0_TX_MNG_HOST_ENABLE
:
7290 NIG_REG_P1_TX_MNG_HOST_ENABLE
, 0);
7292 /* Suspend Tx switching to the PF. Completion of this ramrod
7293 * further guarantees that all the packets of that PF / child
7294 * VFs in BRB were processed by the Parser, so it is safe to
7295 * change the NIC_MODE register.
7297 rc
= bnx2x_func_switch_update(bp
, 1);
7299 BNX2X_ERR("Can't suspend tx-switching!\n");
7303 /* Change NIC_MODE register */
7304 REG_WR(bp
, PRS_REG_NIC_MODE
, 0);
7306 /* Open input from network */
7307 if (bp
->mf_mode
== SINGLE_FUNCTION
) {
7308 bnx2x_set_rx_filter(&bp
->link_params
, 1);
7310 REG_WR(bp
, port
? NIG_REG_LLH1_FUNC_EN
:
7311 NIG_REG_LLH0_FUNC_EN
, vlan_en
);
7312 for (i
= 0; i
< NUM_MACS
; i
++) {
7313 REG_WR(bp
, port
? (NIG_REG_LLH1_FUNC_MEM_ENABLE
+
7315 (NIG_REG_LLH0_FUNC_MEM_ENABLE
+ 4 * i
),
7320 /* Enable BMC to host */
7321 REG_WR(bp
, port
? NIG_REG_P0_TX_MNG_HOST_ENABLE
:
7322 NIG_REG_P1_TX_MNG_HOST_ENABLE
, 1);
7324 /* Resume Tx switching to the PF */
7325 rc
= bnx2x_func_switch_update(bp
, 0);
7327 BNX2X_ERR("Can't resume tx-switching!\n");
7331 DP(NETIF_MSG_IFUP
, "NIC MODE disabled\n");
7335 int bnx2x_init_hw_func_cnic(struct bnx2x
*bp
)
7339 bnx2x_ilt_init_op_cnic(bp
, INITOP_SET
);
7341 if (CONFIGURE_NIC_MODE(bp
)) {
7342 /* Configrue searcher as part of function hw init */
7343 bnx2x_init_searcher(bp
);
7345 /* Reset NIC mode */
7346 rc
= bnx2x_reset_nic_mode(bp
);
7348 BNX2X_ERR("Can't change NIC mode!\n");
7355 static int bnx2x_init_hw_func(struct bnx2x
*bp
)
7357 int port
= BP_PORT(bp
);
7358 int func
= BP_FUNC(bp
);
7359 int init_phase
= PHASE_PF0
+ func
;
7360 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
7363 u32 main_mem_base
, main_mem_size
, main_mem_prty_clr
;
7364 int i
, main_mem_width
, rc
;
7366 DP(NETIF_MSG_HW
, "starting func init func %d\n", func
);
7368 /* FLR cleanup - hmmm */
7369 if (!CHIP_IS_E1x(bp
)) {
7370 rc
= bnx2x_pf_flr_clnup(bp
);
7375 /* set MSI reconfigure capability */
7376 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
7377 addr
= (port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
);
7378 val
= REG_RD(bp
, addr
);
7379 val
|= HC_CONFIG_0_REG_MSI_ATTN_EN_0
;
7380 REG_WR(bp
, addr
, val
);
7383 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
7384 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
7387 cdu_ilt_start
= ilt
->clients
[ILT_CLIENT_CDU
].start
;
7390 cdu_ilt_start
+= BNX2X_FIRST_VF_CID
/ILT_PAGE_CIDS
;
7391 cdu_ilt_start
= bnx2x_iov_init_ilt(bp
, cdu_ilt_start
);
7393 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7394 * those of the VFs, so start line should be reset
7396 cdu_ilt_start
= ilt
->clients
[ILT_CLIENT_CDU
].start
;
7397 for (i
= 0; i
< L2_ILT_LINES(bp
); i
++) {
7398 ilt
->lines
[cdu_ilt_start
+ i
].page
= bp
->context
[i
].vcxt
;
7399 ilt
->lines
[cdu_ilt_start
+ i
].page_mapping
=
7400 bp
->context
[i
].cxt_mapping
;
7401 ilt
->lines
[cdu_ilt_start
+ i
].size
= bp
->context
[i
].size
;
7404 bnx2x_ilt_init_op(bp
, INITOP_SET
);
7406 if (!CONFIGURE_NIC_MODE(bp
)) {
7407 bnx2x_init_searcher(bp
);
7408 REG_WR(bp
, PRS_REG_NIC_MODE
, 0);
7409 DP(NETIF_MSG_IFUP
, "NIC MODE disabled\n");
7412 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
7413 DP(NETIF_MSG_IFUP
, "NIC MODE configrued\n");
7417 if (!CHIP_IS_E1x(bp
)) {
7418 u32 pf_conf
= IGU_PF_CONF_FUNC_EN
;
7420 /* Turn on a single ISR mode in IGU if driver is going to use
7423 if (!(bp
->flags
& USING_MSIX_FLAG
))
7424 pf_conf
|= IGU_PF_CONF_SINGLE_ISR_EN
;
7426 * Timers workaround bug: function init part.
7427 * Need to wait 20msec after initializing ILT,
7428 * needed to make sure there are no requests in
7429 * one of the PXP internal queues with "old" ILT addresses
7433 * Master enable - Due to WB DMAE writes performed before this
7434 * register is re-initialized as part of the regular function
7437 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
7438 /* Enable the function in IGU */
7439 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, pf_conf
);
7444 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
7446 if (!CHIP_IS_E1x(bp
))
7447 REG_WR(bp
, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR
, func
);
7449 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
7450 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
7451 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
7452 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
7453 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
7454 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
7455 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
7456 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
7457 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
7458 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
7459 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
7460 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
7461 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
7463 if (!CHIP_IS_E1x(bp
))
7464 REG_WR(bp
, QM_REG_PF_EN
, 1);
7466 if (!CHIP_IS_E1x(bp
)) {
7467 REG_WR(bp
, TSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
7468 REG_WR(bp
, USEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
7469 REG_WR(bp
, CSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
7470 REG_WR(bp
, XSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
7472 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
7474 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
7475 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
7477 bnx2x_iov_init_dq(bp
);
7479 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
7480 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
7481 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
7482 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
7483 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
7484 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
7485 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
7486 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
7487 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
7488 if (!CHIP_IS_E1x(bp
))
7489 REG_WR(bp
, PBF_REG_DISABLE_PF
, 0);
7491 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
7493 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
7495 if (!CHIP_IS_E1x(bp
))
7496 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 1);
7499 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 1);
7500 REG_WR(bp
, NIG_REG_LLH0_FUNC_VLAN_ID
+ port
*8, bp
->mf_ov
);
7503 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
7505 /* HC init per function */
7506 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
7507 if (CHIP_IS_E1H(bp
)) {
7508 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
7510 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
7511 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
7513 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
7516 int num_segs
, sb_idx
, prod_offset
;
7518 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
7520 if (!CHIP_IS_E1x(bp
)) {
7521 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
7522 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
7525 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
7527 if (!CHIP_IS_E1x(bp
)) {
7531 * E2 mode: address 0-135 match to the mapping memory;
7532 * 136 - PF0 default prod; 137 - PF1 default prod;
7533 * 138 - PF2 default prod; 139 - PF3 default prod;
7534 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7535 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7538 * E1.5 mode - In backward compatible mode;
7539 * for non default SB; each even line in the memory
7540 * holds the U producer and each odd line hold
7541 * the C producer. The first 128 producers are for
7542 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7543 * producers are for the DSB for each PF.
7544 * Each PF has five segments: (the order inside each
7545 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7546 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7547 * 144-147 attn prods;
7549 /* non-default-status-blocks */
7550 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
7551 IGU_BC_NDSB_NUM_SEGS
: IGU_NORM_NDSB_NUM_SEGS
;
7552 for (sb_idx
= 0; sb_idx
< bp
->igu_sb_cnt
; sb_idx
++) {
7553 prod_offset
= (bp
->igu_base_sb
+ sb_idx
) *
7556 for (i
= 0; i
< num_segs
; i
++) {
7557 addr
= IGU_REG_PROD_CONS_MEMORY
+
7558 (prod_offset
+ i
) * 4;
7559 REG_WR(bp
, addr
, 0);
7561 /* send consumer update with value 0 */
7562 bnx2x_ack_sb(bp
, bp
->igu_base_sb
+ sb_idx
,
7563 USTORM_ID
, 0, IGU_INT_NOP
, 1);
7564 bnx2x_igu_clear_sb(bp
,
7565 bp
->igu_base_sb
+ sb_idx
);
7568 /* default-status-blocks */
7569 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
7570 IGU_BC_DSB_NUM_SEGS
: IGU_NORM_DSB_NUM_SEGS
;
7572 if (CHIP_MODE_IS_4_PORT(bp
))
7573 dsb_idx
= BP_FUNC(bp
);
7575 dsb_idx
= BP_VN(bp
);
7577 prod_offset
= (CHIP_INT_MODE_IS_BC(bp
) ?
7578 IGU_BC_BASE_DSB_PROD
+ dsb_idx
:
7579 IGU_NORM_BASE_DSB_PROD
+ dsb_idx
);
7582 * igu prods come in chunks of E1HVN_MAX (4) -
7583 * does not matters what is the current chip mode
7585 for (i
= 0; i
< (num_segs
* E1HVN_MAX
);
7587 addr
= IGU_REG_PROD_CONS_MEMORY
+
7588 (prod_offset
+ i
)*4;
7589 REG_WR(bp
, addr
, 0);
7591 /* send consumer update with 0 */
7592 if (CHIP_INT_MODE_IS_BC(bp
)) {
7593 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
7594 USTORM_ID
, 0, IGU_INT_NOP
, 1);
7595 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
7596 CSTORM_ID
, 0, IGU_INT_NOP
, 1);
7597 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
7598 XSTORM_ID
, 0, IGU_INT_NOP
, 1);
7599 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
7600 TSTORM_ID
, 0, IGU_INT_NOP
, 1);
7601 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
7602 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
7604 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
7605 USTORM_ID
, 0, IGU_INT_NOP
, 1);
7606 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
7607 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
7609 bnx2x_igu_clear_sb(bp
, bp
->igu_dsb_id
);
7611 /* !!! these should become driver const once
7612 rf-tool supports split-68 const */
7613 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_LSB
, 0);
7614 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_MSB
, 0);
7615 REG_WR(bp
, IGU_REG_SB_MASK_LSB
, 0);
7616 REG_WR(bp
, IGU_REG_SB_MASK_MSB
, 0);
7617 REG_WR(bp
, IGU_REG_PBA_STATUS_LSB
, 0);
7618 REG_WR(bp
, IGU_REG_PBA_STATUS_MSB
, 0);
7622 /* Reset PCIE errors for debug */
7623 REG_WR(bp
, 0x2114, 0xffffffff);
7624 REG_WR(bp
, 0x2120, 0xffffffff);
7626 if (CHIP_IS_E1x(bp
)) {
7627 main_mem_size
= HC_REG_MAIN_MEMORY_SIZE
/ 2; /*dwords*/
7628 main_mem_base
= HC_REG_MAIN_MEMORY
+
7629 BP_PORT(bp
) * (main_mem_size
* 4);
7630 main_mem_prty_clr
= HC_REG_HC_PRTY_STS_CLR
;
7633 val
= REG_RD(bp
, main_mem_prty_clr
);
7636 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7639 /* Clear "false" parity errors in MSI-X table */
7640 for (i
= main_mem_base
;
7641 i
< main_mem_base
+ main_mem_size
* 4;
7642 i
+= main_mem_width
) {
7643 bnx2x_read_dmae(bp
, i
, main_mem_width
/ 4);
7644 bnx2x_write_dmae(bp
, bnx2x_sp_mapping(bp
, wb_data
),
7645 i
, main_mem_width
/ 4);
7647 /* Clear HC parity attention */
7648 REG_RD(bp
, main_mem_prty_clr
);
7651 #ifdef BNX2X_STOP_ON_ERROR
7652 /* Enable STORMs SP logging */
7653 REG_WR8(bp
, BAR_USTRORM_INTMEM
+
7654 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
7655 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
7656 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
7657 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
7658 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
7659 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+
7660 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
7663 bnx2x_phy_probe(&bp
->link_params
);
7669 void bnx2x_free_mem_cnic(struct bnx2x
*bp
)
7671 bnx2x_ilt_mem_op_cnic(bp
, ILT_MEMOP_FREE
);
7673 if (!CHIP_IS_E1x(bp
))
7674 BNX2X_PCI_FREE(bp
->cnic_sb
.e2_sb
, bp
->cnic_sb_mapping
,
7675 sizeof(struct host_hc_status_block_e2
));
7677 BNX2X_PCI_FREE(bp
->cnic_sb
.e1x_sb
, bp
->cnic_sb_mapping
,
7678 sizeof(struct host_hc_status_block_e1x
));
7680 BNX2X_PCI_FREE(bp
->t2
, bp
->t2_mapping
, SRC_T2_SZ
);
7683 void bnx2x_free_mem(struct bnx2x
*bp
)
7688 bnx2x_free_fp_mem(bp
);
7689 /* end of fastpath */
7691 BNX2X_PCI_FREE(bp
->def_status_blk
, bp
->def_status_blk_mapping
,
7692 sizeof(struct host_sp_status_block
));
7694 BNX2X_PCI_FREE(bp
->fw_stats
, bp
->fw_stats_mapping
,
7695 bp
->fw_stats_data_sz
+ bp
->fw_stats_req_sz
);
7697 BNX2X_PCI_FREE(bp
->slowpath
, bp
->slowpath_mapping
,
7698 sizeof(struct bnx2x_slowpath
));
7700 for (i
= 0; i
< L2_ILT_LINES(bp
); i
++)
7701 BNX2X_PCI_FREE(bp
->context
[i
].vcxt
, bp
->context
[i
].cxt_mapping
,
7702 bp
->context
[i
].size
);
7703 bnx2x_ilt_mem_op(bp
, ILT_MEMOP_FREE
);
7705 BNX2X_FREE(bp
->ilt
->lines
);
7707 BNX2X_PCI_FREE(bp
->spq
, bp
->spq_mapping
, BCM_PAGE_SIZE
);
7709 BNX2X_PCI_FREE(bp
->eq_ring
, bp
->eq_mapping
,
7710 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
7714 int bnx2x_alloc_mem_cnic(struct bnx2x
*bp
)
7716 if (!CHIP_IS_E1x(bp
))
7717 /* size = the status block + ramrod buffers */
7718 BNX2X_PCI_ALLOC(bp
->cnic_sb
.e2_sb
, &bp
->cnic_sb_mapping
,
7719 sizeof(struct host_hc_status_block_e2
));
7721 BNX2X_PCI_ALLOC(bp
->cnic_sb
.e1x_sb
,
7722 &bp
->cnic_sb_mapping
,
7724 host_hc_status_block_e1x
));
7726 if (CONFIGURE_NIC_MODE(bp
))
7727 /* allocate searcher T2 table, as it wan't allocated before */
7728 BNX2X_PCI_ALLOC(bp
->t2
, &bp
->t2_mapping
, SRC_T2_SZ
);
7730 /* write address to which L5 should insert its values */
7731 bp
->cnic_eth_dev
.addr_drv_info_to_mcp
=
7732 &bp
->slowpath
->drv_info_to_mcp
;
7734 if (bnx2x_ilt_mem_op_cnic(bp
, ILT_MEMOP_ALLOC
))
7740 bnx2x_free_mem_cnic(bp
);
7741 BNX2X_ERR("Can't allocate memory\n");
7745 int bnx2x_alloc_mem(struct bnx2x
*bp
)
7747 int i
, allocated
, context_size
;
7749 if (!CONFIGURE_NIC_MODE(bp
))
7750 /* allocate searcher T2 table */
7751 BNX2X_PCI_ALLOC(bp
->t2
, &bp
->t2_mapping
, SRC_T2_SZ
);
7753 BNX2X_PCI_ALLOC(bp
->def_status_blk
, &bp
->def_status_blk_mapping
,
7754 sizeof(struct host_sp_status_block
));
7756 BNX2X_PCI_ALLOC(bp
->slowpath
, &bp
->slowpath_mapping
,
7757 sizeof(struct bnx2x_slowpath
));
7759 /* Allocate memory for CDU context:
7760 * This memory is allocated separately and not in the generic ILT
7761 * functions because CDU differs in few aspects:
7762 * 1. There are multiple entities allocating memory for context -
7763 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7764 * its own ILT lines.
7765 * 2. Since CDU page-size is not a single 4KB page (which is the case
7766 * for the other ILT clients), to be efficient we want to support
7767 * allocation of sub-page-size in the last entry.
7768 * 3. Context pointers are used by the driver to pass to FW / update
7769 * the context (for the other ILT clients the pointers are used just to
7770 * free the memory during unload).
7772 context_size
= sizeof(union cdu_context
) * BNX2X_L2_CID_COUNT(bp
);
7774 for (i
= 0, allocated
= 0; allocated
< context_size
; i
++) {
7775 bp
->context
[i
].size
= min(CDU_ILT_PAGE_SZ
,
7776 (context_size
- allocated
));
7777 BNX2X_PCI_ALLOC(bp
->context
[i
].vcxt
,
7778 &bp
->context
[i
].cxt_mapping
,
7779 bp
->context
[i
].size
);
7780 allocated
+= bp
->context
[i
].size
;
7782 BNX2X_ALLOC(bp
->ilt
->lines
, sizeof(struct ilt_line
) * ILT_MAX_LINES
);
7784 if (bnx2x_ilt_mem_op(bp
, ILT_MEMOP_ALLOC
))
7787 if (bnx2x_iov_alloc_mem(bp
))
7790 /* Slow path ring */
7791 BNX2X_PCI_ALLOC(bp
->spq
, &bp
->spq_mapping
, BCM_PAGE_SIZE
);
7794 BNX2X_PCI_ALLOC(bp
->eq_ring
, &bp
->eq_mapping
,
7795 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
7801 BNX2X_ERR("Can't allocate memory\n");
7806 * Init service functions
7809 int bnx2x_set_mac_one(struct bnx2x
*bp
, u8
*mac
,
7810 struct bnx2x_vlan_mac_obj
*obj
, bool set
,
7811 int mac_type
, unsigned long *ramrod_flags
)
7814 struct bnx2x_vlan_mac_ramrod_params ramrod_param
;
7816 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
7818 /* Fill general parameters */
7819 ramrod_param
.vlan_mac_obj
= obj
;
7820 ramrod_param
.ramrod_flags
= *ramrod_flags
;
7822 /* Fill a user request section if needed */
7823 if (!test_bit(RAMROD_CONT
, ramrod_flags
)) {
7824 memcpy(ramrod_param
.user_req
.u
.mac
.mac
, mac
, ETH_ALEN
);
7826 __set_bit(mac_type
, &ramrod_param
.user_req
.vlan_mac_flags
);
7828 /* Set the command: ADD or DEL */
7830 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_ADD
;
7832 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_DEL
;
7835 rc
= bnx2x_config_vlan_mac(bp
, &ramrod_param
);
7837 if (rc
== -EEXIST
) {
7838 DP(BNX2X_MSG_SP
, "Failed to schedule ADD operations: %d\n", rc
);
7839 /* do not treat adding same MAC as error */
7842 BNX2X_ERR("%s MAC failed\n", (set
? "Set" : "Del"));
7847 int bnx2x_del_all_macs(struct bnx2x
*bp
,
7848 struct bnx2x_vlan_mac_obj
*mac_obj
,
7849 int mac_type
, bool wait_for_comp
)
7852 unsigned long ramrod_flags
= 0, vlan_mac_flags
= 0;
7854 /* Wait for completion of requested */
7856 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
7858 /* Set the mac type of addresses we want to clear */
7859 __set_bit(mac_type
, &vlan_mac_flags
);
7861 rc
= mac_obj
->delete_all(bp
, mac_obj
, &vlan_mac_flags
, &ramrod_flags
);
7863 BNX2X_ERR("Failed to delete MACs: %d\n", rc
);
7868 int bnx2x_set_eth_mac(struct bnx2x
*bp
, bool set
)
7870 unsigned long ramrod_flags
= 0;
7872 if (is_zero_ether_addr(bp
->dev
->dev_addr
) &&
7873 (IS_MF_STORAGE_SD(bp
) || IS_MF_FCOE_AFEX(bp
))) {
7874 DP(NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
,
7875 "Ignoring Zero MAC for STORAGE SD mode\n");
7879 DP(NETIF_MSG_IFUP
, "Adding Eth MAC\n");
7881 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
7882 /* Eth MAC is set on RSS leading client (fp[0]) */
7883 return bnx2x_set_mac_one(bp
, bp
->dev
->dev_addr
, &bp
->sp_objs
->mac_obj
,
7884 set
, BNX2X_ETH_MAC
, &ramrod_flags
);
7887 int bnx2x_setup_leading(struct bnx2x
*bp
)
7889 return bnx2x_setup_queue(bp
, &bp
->fp
[0], 1);
7893 * bnx2x_set_int_mode - configure interrupt mode
7895 * @bp: driver handle
7897 * In case of MSI-X it will also try to enable MSI-X.
7899 int bnx2x_set_int_mode(struct bnx2x
*bp
)
7903 if (IS_VF(bp
) && int_mode
!= BNX2X_INT_MODE_MSIX
)
7907 case BNX2X_INT_MODE_MSIX
:
7908 /* attempt to enable msix */
7909 rc
= bnx2x_enable_msix(bp
);
7915 /* vfs use only msix */
7916 if (rc
&& IS_VF(bp
))
7919 /* failed to enable multiple MSI-X */
7920 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7922 1 + bp
->num_cnic_queues
);
7924 /* falling through... */
7925 case BNX2X_INT_MODE_MSI
:
7926 bnx2x_enable_msi(bp
);
7928 /* falling through... */
7929 case BNX2X_INT_MODE_INTX
:
7930 bp
->num_ethernet_queues
= 1;
7931 bp
->num_queues
= bp
->num_ethernet_queues
+ bp
->num_cnic_queues
;
7932 BNX2X_DEV_INFO("set number of queues to 1\n");
7935 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
7941 /* must be called prior to any HW initializations */
7942 static inline u16
bnx2x_cid_ilt_lines(struct bnx2x
*bp
)
7945 return (BNX2X_FIRST_VF_CID
+ BNX2X_VF_CIDS
)/ILT_PAGE_CIDS
;
7946 return L2_ILT_LINES(bp
);
7949 void bnx2x_ilt_set_info(struct bnx2x
*bp
)
7951 struct ilt_client_info
*ilt_client
;
7952 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
7955 ilt
->start_line
= FUNC_ILT_BASE(BP_FUNC(bp
));
7956 DP(BNX2X_MSG_SP
, "ilt starts at line %d\n", ilt
->start_line
);
7959 ilt_client
= &ilt
->clients
[ILT_CLIENT_CDU
];
7960 ilt_client
->client_num
= ILT_CLIENT_CDU
;
7961 ilt_client
->page_size
= CDU_ILT_PAGE_SZ
;
7962 ilt_client
->flags
= ILT_CLIENT_SKIP_MEM
;
7963 ilt_client
->start
= line
;
7964 line
+= bnx2x_cid_ilt_lines(bp
);
7966 if (CNIC_SUPPORT(bp
))
7967 line
+= CNIC_ILT_LINES
;
7968 ilt_client
->end
= line
- 1;
7970 DP(NETIF_MSG_IFUP
, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7973 ilt_client
->page_size
,
7975 ilog2(ilt_client
->page_size
>> 12));
7978 if (QM_INIT(bp
->qm_cid_count
)) {
7979 ilt_client
= &ilt
->clients
[ILT_CLIENT_QM
];
7980 ilt_client
->client_num
= ILT_CLIENT_QM
;
7981 ilt_client
->page_size
= QM_ILT_PAGE_SZ
;
7982 ilt_client
->flags
= 0;
7983 ilt_client
->start
= line
;
7985 /* 4 bytes for each cid */
7986 line
+= DIV_ROUND_UP(bp
->qm_cid_count
* QM_QUEUES_PER_FUNC
* 4,
7989 ilt_client
->end
= line
- 1;
7992 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7995 ilt_client
->page_size
,
7997 ilog2(ilt_client
->page_size
>> 12));
8001 if (CNIC_SUPPORT(bp
)) {
8003 ilt_client
= &ilt
->clients
[ILT_CLIENT_SRC
];
8004 ilt_client
->client_num
= ILT_CLIENT_SRC
;
8005 ilt_client
->page_size
= SRC_ILT_PAGE_SZ
;
8006 ilt_client
->flags
= 0;
8007 ilt_client
->start
= line
;
8008 line
+= SRC_ILT_LINES
;
8009 ilt_client
->end
= line
- 1;
8012 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8015 ilt_client
->page_size
,
8017 ilog2(ilt_client
->page_size
>> 12));
8020 ilt_client
= &ilt
->clients
[ILT_CLIENT_TM
];
8021 ilt_client
->client_num
= ILT_CLIENT_TM
;
8022 ilt_client
->page_size
= TM_ILT_PAGE_SZ
;
8023 ilt_client
->flags
= 0;
8024 ilt_client
->start
= line
;
8025 line
+= TM_ILT_LINES
;
8026 ilt_client
->end
= line
- 1;
8029 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8032 ilt_client
->page_size
,
8034 ilog2(ilt_client
->page_size
>> 12));
8037 BUG_ON(line
> ILT_MAX_LINES
);
8041 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8043 * @bp: driver handle
8044 * @fp: pointer to fastpath
8045 * @init_params: pointer to parameters structure
8047 * parameters configured:
8048 * - HC configuration
8049 * - Queue's CDU context
8051 static void bnx2x_pf_q_prep_init(struct bnx2x
*bp
,
8052 struct bnx2x_fastpath
*fp
, struct bnx2x_queue_init_params
*init_params
)
8056 int cxt_index
, cxt_offset
;
8058 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8059 if (!IS_FCOE_FP(fp
)) {
8060 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->rx
.flags
);
8061 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->tx
.flags
);
8063 /* If HC is supporterd, enable host coalescing in the transition
8066 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->rx
.flags
);
8067 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->tx
.flags
);
8070 init_params
->rx
.hc_rate
= bp
->rx_ticks
?
8071 (1000000 / bp
->rx_ticks
) : 0;
8072 init_params
->tx
.hc_rate
= bp
->tx_ticks
?
8073 (1000000 / bp
->tx_ticks
) : 0;
8076 init_params
->rx
.fw_sb_id
= init_params
->tx
.fw_sb_id
=
8080 * CQ index among the SB indices: FCoE clients uses the default
8081 * SB, therefore it's different.
8083 init_params
->rx
.sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
8084 init_params
->tx
.sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
;
8087 /* set maximum number of COSs supported by this queue */
8088 init_params
->max_cos
= fp
->max_cos
;
8090 DP(NETIF_MSG_IFUP
, "fp: %d setting queue params max cos to: %d\n",
8091 fp
->index
, init_params
->max_cos
);
8093 /* set the context pointers queue object */
8094 for (cos
= FIRST_TX_COS_INDEX
; cos
< init_params
->max_cos
; cos
++) {
8095 cxt_index
= fp
->txdata_ptr
[cos
]->cid
/ ILT_PAGE_CIDS
;
8096 cxt_offset
= fp
->txdata_ptr
[cos
]->cid
- (cxt_index
*
8098 init_params
->cxts
[cos
] =
8099 &bp
->context
[cxt_index
].vcxt
[cxt_offset
].eth
;
8103 static int bnx2x_setup_tx_only(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
8104 struct bnx2x_queue_state_params
*q_params
,
8105 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
,
8106 int tx_index
, bool leading
)
8108 memset(tx_only_params
, 0, sizeof(*tx_only_params
));
8110 /* Set the command */
8111 q_params
->cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
8113 /* Set tx-only QUEUE flags: don't zero statistics */
8114 tx_only_params
->flags
= bnx2x_get_common_flags(bp
, fp
, false);
8116 /* choose the index of the cid to send the slow path on */
8117 tx_only_params
->cid_index
= tx_index
;
8119 /* Set general TX_ONLY_SETUP parameters */
8120 bnx2x_pf_q_prep_general(bp
, fp
, &tx_only_params
->gen_params
, tx_index
);
8122 /* Set Tx TX_ONLY_SETUP parameters */
8123 bnx2x_pf_tx_q_prep(bp
, fp
, &tx_only_params
->txq_params
, tx_index
);
8126 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8127 tx_index
, q_params
->q_obj
->cids
[FIRST_TX_COS_INDEX
],
8128 q_params
->q_obj
->cids
[tx_index
], q_params
->q_obj
->cl_id
,
8129 tx_only_params
->gen_params
.spcl_id
, tx_only_params
->flags
);
8131 /* send the ramrod */
8132 return bnx2x_queue_state_change(bp
, q_params
);
8137 * bnx2x_setup_queue - setup queue
8139 * @bp: driver handle
8140 * @fp: pointer to fastpath
8141 * @leading: is leading
8143 * This function performs 2 steps in a Queue state machine
8144 * actually: 1) RESET->INIT 2) INIT->SETUP
8147 int bnx2x_setup_queue(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
8150 struct bnx2x_queue_state_params q_params
= {NULL
};
8151 struct bnx2x_queue_setup_params
*setup_params
=
8152 &q_params
.params
.setup
;
8153 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
=
8154 &q_params
.params
.tx_only
;
8158 DP(NETIF_MSG_IFUP
, "setting up queue %d\n", fp
->index
);
8160 /* reset IGU state skip FCoE L2 queue */
8161 if (!IS_FCOE_FP(fp
))
8162 bnx2x_ack_sb(bp
, fp
->igu_sb_id
, USTORM_ID
, 0,
8165 q_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
8166 /* We want to wait for completion in this context */
8167 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
8169 /* Prepare the INIT parameters */
8170 bnx2x_pf_q_prep_init(bp
, fp
, &q_params
.params
.init
);
8172 /* Set the command */
8173 q_params
.cmd
= BNX2X_Q_CMD_INIT
;
8175 /* Change the state to INIT */
8176 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8178 BNX2X_ERR("Queue(%d) INIT failed\n", fp
->index
);
8182 DP(NETIF_MSG_IFUP
, "init complete\n");
8185 /* Now move the Queue to the SETUP state... */
8186 memset(setup_params
, 0, sizeof(*setup_params
));
8188 /* Set QUEUE flags */
8189 setup_params
->flags
= bnx2x_get_q_flags(bp
, fp
, leading
);
8191 /* Set general SETUP parameters */
8192 bnx2x_pf_q_prep_general(bp
, fp
, &setup_params
->gen_params
,
8193 FIRST_TX_COS_INDEX
);
8195 bnx2x_pf_rx_q_prep(bp
, fp
, &setup_params
->pause_params
,
8196 &setup_params
->rxq_params
);
8198 bnx2x_pf_tx_q_prep(bp
, fp
, &setup_params
->txq_params
,
8199 FIRST_TX_COS_INDEX
);
8201 /* Set the command */
8202 q_params
.cmd
= BNX2X_Q_CMD_SETUP
;
8205 bp
->fcoe_init
= true;
8207 /* Change the state to SETUP */
8208 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8210 BNX2X_ERR("Queue(%d) SETUP failed\n", fp
->index
);
8214 /* loop through the relevant tx-only indices */
8215 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
8216 tx_index
< fp
->max_cos
;
8219 /* prepare and send tx-only ramrod*/
8220 rc
= bnx2x_setup_tx_only(bp
, fp
, &q_params
,
8221 tx_only_params
, tx_index
, leading
);
8223 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8224 fp
->index
, tx_index
);
8232 static int bnx2x_stop_queue(struct bnx2x
*bp
, int index
)
8234 struct bnx2x_fastpath
*fp
= &bp
->fp
[index
];
8235 struct bnx2x_fp_txdata
*txdata
;
8236 struct bnx2x_queue_state_params q_params
= {NULL
};
8239 DP(NETIF_MSG_IFDOWN
, "stopping queue %d cid %d\n", index
, fp
->cid
);
8241 q_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
8242 /* We want to wait for completion in this context */
8243 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
8246 /* close tx-only connections */
8247 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
8248 tx_index
< fp
->max_cos
;
8251 /* ascertain this is a normal queue*/
8252 txdata
= fp
->txdata_ptr
[tx_index
];
8254 DP(NETIF_MSG_IFDOWN
, "stopping tx-only queue %d\n",
8257 /* send halt terminate on tx-only connection */
8258 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
8259 memset(&q_params
.params
.terminate
, 0,
8260 sizeof(q_params
.params
.terminate
));
8261 q_params
.params
.terminate
.cid_index
= tx_index
;
8263 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8267 /* send halt terminate on tx-only connection */
8268 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
8269 memset(&q_params
.params
.cfc_del
, 0,
8270 sizeof(q_params
.params
.cfc_del
));
8271 q_params
.params
.cfc_del
.cid_index
= tx_index
;
8272 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8276 /* Stop the primary connection: */
8277 /* ...halt the connection */
8278 q_params
.cmd
= BNX2X_Q_CMD_HALT
;
8279 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8283 /* ...terminate the connection */
8284 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
8285 memset(&q_params
.params
.terminate
, 0,
8286 sizeof(q_params
.params
.terminate
));
8287 q_params
.params
.terminate
.cid_index
= FIRST_TX_COS_INDEX
;
8288 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8291 /* ...delete cfc entry */
8292 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
8293 memset(&q_params
.params
.cfc_del
, 0,
8294 sizeof(q_params
.params
.cfc_del
));
8295 q_params
.params
.cfc_del
.cid_index
= FIRST_TX_COS_INDEX
;
8296 return bnx2x_queue_state_change(bp
, &q_params
);
8300 static void bnx2x_reset_func(struct bnx2x
*bp
)
8302 int port
= BP_PORT(bp
);
8303 int func
= BP_FUNC(bp
);
8306 /* Disable the function in the FW */
8307 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(func
), 0);
8308 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(func
), 0);
8309 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(func
), 0);
8310 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(func
), 0);
8313 for_each_eth_queue(bp
, i
) {
8314 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
8315 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8316 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp
->fw_sb_id
),
8320 if (CNIC_LOADED(bp
))
8322 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8323 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8324 (bnx2x_cnic_fw_sb_id(bp
)), SB_DISABLED
);
8327 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8328 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func
),
8331 for (i
= 0; i
< XSTORM_SPQ_DATA_SIZE
/ 4; i
++)
8332 REG_WR(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_DATA_OFFSET(func
),
8336 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
8337 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
8338 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
8340 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
8341 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
8344 if (CNIC_LOADED(bp
)) {
8345 /* Disable Timer scan */
8346 REG_WR(bp
, TM_REG_EN_LINEAR0_TIMER
+ port
*4, 0);
8348 * Wait for at least 10ms and up to 2 second for the timers
8351 for (i
= 0; i
< 200; i
++) {
8353 if (!REG_RD(bp
, TM_REG_LIN0_SCAN_ON
+ port
*4))
8358 bnx2x_clear_func_ilt(bp
, func
);
8360 /* Timers workaround bug for E2: if this is vnic-3,
8361 * we need to set the entire ilt range for this timers.
8363 if (!CHIP_IS_E1x(bp
) && BP_VN(bp
) == 3) {
8364 struct ilt_client_info ilt_cli
;
8365 /* use dummy TM client */
8366 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
8368 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
8369 ilt_cli
.client_num
= ILT_CLIENT_TM
;
8371 bnx2x_ilt_boundry_init_op(bp
, &ilt_cli
, 0, INITOP_CLEAR
);
8374 /* this assumes that reset_port() called before reset_func()*/
8375 if (!CHIP_IS_E1x(bp
))
8376 bnx2x_pf_disable(bp
);
8381 static void bnx2x_reset_port(struct bnx2x
*bp
)
8383 int port
= BP_PORT(bp
);
8386 /* Reset physical Link */
8387 bnx2x__link_reset(bp
);
8389 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
8391 /* Do not rcv packets to BRB */
8392 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK
+ port
*4, 0x0);
8393 /* Do not direct rcv packets that are not for MCP to the BRB */
8394 REG_WR(bp
, (port
? NIG_REG_LLH1_BRB1_NOT_MCP
:
8395 NIG_REG_LLH0_BRB1_NOT_MCP
), 0x0);
8398 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, 0);
8401 /* Check for BRB port occupancy */
8402 val
= REG_RD(bp
, BRB1_REG_PORT_NUM_OCC_BLOCKS_0
+ port
*4);
8404 DP(NETIF_MSG_IFDOWN
,
8405 "BRB1 is not empty %d blocks are occupied\n", val
);
8407 /* TODO: Close Doorbell port? */
8410 static int bnx2x_reset_hw(struct bnx2x
*bp
, u32 load_code
)
8412 struct bnx2x_func_state_params func_params
= {NULL
};
8414 /* Prepare parameters for function state transitions */
8415 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
8417 func_params
.f_obj
= &bp
->func_obj
;
8418 func_params
.cmd
= BNX2X_F_CMD_HW_RESET
;
8420 func_params
.params
.hw_init
.load_phase
= load_code
;
8422 return bnx2x_func_state_change(bp
, &func_params
);
8425 static int bnx2x_func_stop(struct bnx2x
*bp
)
8427 struct bnx2x_func_state_params func_params
= {NULL
};
8430 /* Prepare parameters for function state transitions */
8431 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
8432 func_params
.f_obj
= &bp
->func_obj
;
8433 func_params
.cmd
= BNX2X_F_CMD_STOP
;
8436 * Try to stop the function the 'good way'. If fails (in case
8437 * of a parity error during bnx2x_chip_cleanup()) and we are
8438 * not in a debug mode, perform a state transaction in order to
8439 * enable further HW_RESET transaction.
8441 rc
= bnx2x_func_state_change(bp
, &func_params
);
8443 #ifdef BNX2X_STOP_ON_ERROR
8446 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8447 __set_bit(RAMROD_DRV_CLR_ONLY
, &func_params
.ramrod_flags
);
8448 return bnx2x_func_state_change(bp
, &func_params
);
8456 * bnx2x_send_unload_req - request unload mode from the MCP.
8458 * @bp: driver handle
8459 * @unload_mode: requested function's unload mode
8461 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8463 u32
bnx2x_send_unload_req(struct bnx2x
*bp
, int unload_mode
)
8466 int port
= BP_PORT(bp
);
8468 /* Select the UNLOAD request mode */
8469 if (unload_mode
== UNLOAD_NORMAL
)
8470 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
8472 else if (bp
->flags
& NO_WOL_FLAG
)
8473 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
;
8476 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
8477 u8
*mac_addr
= bp
->dev
->dev_addr
;
8481 /* The mac address is written to entries 1-4 to
8482 * preserve entry 0 which is used by the PMF
8484 u8 entry
= (BP_VN(bp
) + 1)*8;
8486 val
= (mac_addr
[0] << 8) | mac_addr
[1];
8487 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
, val
);
8489 val
= (mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
8490 (mac_addr
[4] << 8) | mac_addr
[5];
8491 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
+ 4, val
);
8493 /* Enable the PME and clear the status */
8494 pci_read_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
, &pmc
);
8495 pmc
|= PCI_PM_CTRL_PME_ENABLE
| PCI_PM_CTRL_PME_STATUS
;
8496 pci_write_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
, pmc
);
8498 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_EN
;
8501 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
8503 /* Send the request to the MCP */
8505 reset_code
= bnx2x_fw_command(bp
, reset_code
, 0);
8507 int path
= BP_PATH(bp
);
8509 DP(NETIF_MSG_IFDOWN
, "NO MCP - load counts[%d] %d, %d, %d\n",
8510 path
, load_count
[path
][0], load_count
[path
][1],
8511 load_count
[path
][2]);
8512 load_count
[path
][0]--;
8513 load_count
[path
][1 + port
]--;
8514 DP(NETIF_MSG_IFDOWN
, "NO MCP - new load counts[%d] %d, %d, %d\n",
8515 path
, load_count
[path
][0], load_count
[path
][1],
8516 load_count
[path
][2]);
8517 if (load_count
[path
][0] == 0)
8518 reset_code
= FW_MSG_CODE_DRV_UNLOAD_COMMON
;
8519 else if (load_count
[path
][1 + port
] == 0)
8520 reset_code
= FW_MSG_CODE_DRV_UNLOAD_PORT
;
8522 reset_code
= FW_MSG_CODE_DRV_UNLOAD_FUNCTION
;
8529 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8531 * @bp: driver handle
8532 * @keep_link: true iff link should be kept up
8534 void bnx2x_send_unload_done(struct bnx2x
*bp
, bool keep_link
)
8536 u32 reset_param
= keep_link
? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET
: 0;
8538 /* Report UNLOAD_DONE to MCP */
8540 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, reset_param
);
8543 static int bnx2x_func_wait_started(struct bnx2x
*bp
)
8546 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
8552 * (assumption: No Attention from MCP at this stage)
8553 * PMF probably in the middle of TXdisable/enable transaction
8554 * 1. Sync IRS for default SB
8555 * 2. Sync SP queue - this guarantes us that attention handling started
8556 * 3. Wait, that TXdisable/enable transaction completes
8558 * 1+2 guranty that if DCBx attention was scheduled it already changed
8559 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8560 * received complettion for the transaction the state is TX_STOPPED.
8561 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8565 /* make sure default SB ISR is done */
8567 synchronize_irq(bp
->msix_table
[0].vector
);
8569 synchronize_irq(bp
->pdev
->irq
);
8571 flush_workqueue(bnx2x_wq
);
8573 while (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
8574 BNX2X_F_STATE_STARTED
&& tout
--)
8577 if (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
8578 BNX2X_F_STATE_STARTED
) {
8579 #ifdef BNX2X_STOP_ON_ERROR
8580 BNX2X_ERR("Wrong function state\n");
8584 * Failed to complete the transaction in a "good way"
8585 * Force both transactions with CLR bit
8587 struct bnx2x_func_state_params func_params
= {NULL
};
8589 DP(NETIF_MSG_IFDOWN
,
8590 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8592 func_params
.f_obj
= &bp
->func_obj
;
8593 __set_bit(RAMROD_DRV_CLR_ONLY
,
8594 &func_params
.ramrod_flags
);
8596 /* STARTED-->TX_ST0PPED */
8597 func_params
.cmd
= BNX2X_F_CMD_TX_STOP
;
8598 bnx2x_func_state_change(bp
, &func_params
);
8600 /* TX_ST0PPED-->STARTED */
8601 func_params
.cmd
= BNX2X_F_CMD_TX_START
;
8602 return bnx2x_func_state_change(bp
, &func_params
);
8609 void bnx2x_chip_cleanup(struct bnx2x
*bp
, int unload_mode
, bool keep_link
)
8611 int port
= BP_PORT(bp
);
8614 struct bnx2x_mcast_ramrod_params rparam
= {NULL
};
8617 /* Wait until tx fastpath tasks complete */
8618 for_each_tx_queue(bp
, i
) {
8619 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
8621 for_each_cos_in_tx_queue(fp
, cos
)
8622 rc
= bnx2x_clean_tx_queue(bp
, fp
->txdata_ptr
[cos
]);
8623 #ifdef BNX2X_STOP_ON_ERROR
8629 /* Give HW time to discard old tx messages */
8630 usleep_range(1000, 1000);
8632 /* Clean all ETH MACs */
8633 rc
= bnx2x_del_all_macs(bp
, &bp
->sp_objs
[0].mac_obj
, BNX2X_ETH_MAC
,
8636 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc
);
8638 /* Clean up UC list */
8639 rc
= bnx2x_del_all_macs(bp
, &bp
->sp_objs
[0].mac_obj
, BNX2X_UC_LIST_MAC
,
8642 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8646 if (!CHIP_IS_E1(bp
))
8647 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
8649 /* Set "drop all" (stop Rx).
8650 * We need to take a netif_addr_lock() here in order to prevent
8651 * a race between the completion code and this code.
8653 netif_addr_lock_bh(bp
->dev
);
8654 /* Schedule the rx_mode command */
8655 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
8656 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
8658 bnx2x_set_storm_rx_mode(bp
);
8660 /* Cleanup multicast configuration */
8661 rparam
.mcast_obj
= &bp
->mcast_obj
;
8662 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
8664 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc
);
8666 netif_addr_unlock_bh(bp
->dev
);
8668 bnx2x_iov_chip_cleanup(bp
);
8672 * Send the UNLOAD_REQUEST to the MCP. This will return if
8673 * this function should perform FUNC, PORT or COMMON HW
8676 reset_code
= bnx2x_send_unload_req(bp
, unload_mode
);
8679 * (assumption: No Attention from MCP at this stage)
8680 * PMF probably in the middle of TXdisable/enable transaction
8682 rc
= bnx2x_func_wait_started(bp
);
8684 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8685 #ifdef BNX2X_STOP_ON_ERROR
8690 /* Close multi and leading connections
8691 * Completions for ramrods are collected in a synchronous way
8693 for_each_eth_queue(bp
, i
)
8694 if (bnx2x_stop_queue(bp
, i
))
8695 #ifdef BNX2X_STOP_ON_ERROR
8701 if (CNIC_LOADED(bp
)) {
8702 for_each_cnic_queue(bp
, i
)
8703 if (bnx2x_stop_queue(bp
, i
))
8704 #ifdef BNX2X_STOP_ON_ERROR
8711 /* If SP settings didn't get completed so far - something
8712 * very wrong has happen.
8714 if (!bnx2x_wait_sp_comp(bp
, ~0x0UL
))
8715 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8717 #ifndef BNX2X_STOP_ON_ERROR
8720 rc
= bnx2x_func_stop(bp
);
8722 BNX2X_ERR("Function stop failed!\n");
8723 #ifdef BNX2X_STOP_ON_ERROR
8728 /* Disable HW interrupts, NAPI */
8729 bnx2x_netif_stop(bp
, 1);
8730 /* Delete all NAPI objects */
8731 bnx2x_del_all_napi(bp
);
8732 if (CNIC_LOADED(bp
))
8733 bnx2x_del_all_napi_cnic(bp
);
8738 /* Reset the chip */
8739 rc
= bnx2x_reset_hw(bp
, reset_code
);
8741 BNX2X_ERR("HW_RESET failed\n");
8744 /* Report UNLOAD_DONE to MCP */
8745 bnx2x_send_unload_done(bp
, keep_link
);
8748 void bnx2x_disable_close_the_gate(struct bnx2x
*bp
)
8752 DP(NETIF_MSG_IFDOWN
, "Disabling \"close the gates\"\n");
8754 if (CHIP_IS_E1(bp
)) {
8755 int port
= BP_PORT(bp
);
8756 u32 addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
8757 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
8759 val
= REG_RD(bp
, addr
);
8761 REG_WR(bp
, addr
, val
);
8763 val
= REG_RD(bp
, MISC_REG_AEU_GENERAL_MASK
);
8764 val
&= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK
|
8765 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK
);
8766 REG_WR(bp
, MISC_REG_AEU_GENERAL_MASK
, val
);
8770 /* Close gates #2, #3 and #4: */
8771 static void bnx2x_set_234_gates(struct bnx2x
*bp
, bool close
)
8775 /* Gates #2 and #4a are closed/opened for "not E1" only */
8776 if (!CHIP_IS_E1(bp
)) {
8778 REG_WR(bp
, PXP_REG_HST_DISCARD_DOORBELLS
, !!close
);
8780 REG_WR(bp
, PXP_REG_HST_DISCARD_INTERNAL_WRITES
, !!close
);
8784 if (CHIP_IS_E1x(bp
)) {
8785 /* Prevent interrupts from HC on both ports */
8786 val
= REG_RD(bp
, HC_REG_CONFIG_1
);
8787 REG_WR(bp
, HC_REG_CONFIG_1
,
8788 (!close
) ? (val
| HC_CONFIG_1_REG_BLOCK_DISABLE_1
) :
8789 (val
& ~(u32
)HC_CONFIG_1_REG_BLOCK_DISABLE_1
));
8791 val
= REG_RD(bp
, HC_REG_CONFIG_0
);
8792 REG_WR(bp
, HC_REG_CONFIG_0
,
8793 (!close
) ? (val
| HC_CONFIG_0_REG_BLOCK_DISABLE_0
) :
8794 (val
& ~(u32
)HC_CONFIG_0_REG_BLOCK_DISABLE_0
));
8796 /* Prevent incomming interrupts in IGU */
8797 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
8799 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
,
8801 (val
| IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
) :
8802 (val
& ~(u32
)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
));
8805 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "%s gates #2, #3 and #4\n",
8806 close
? "closing" : "opening");
8810 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8812 static void bnx2x_clp_reset_prep(struct bnx2x
*bp
, u32
*magic_val
)
8814 /* Do some magic... */
8815 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
8816 *magic_val
= val
& SHARED_MF_CLP_MAGIC
;
8817 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
, val
| SHARED_MF_CLP_MAGIC
);
8821 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8823 * @bp: driver handle
8824 * @magic_val: old value of the `magic' bit.
8826 static void bnx2x_clp_reset_done(struct bnx2x
*bp
, u32 magic_val
)
8828 /* Restore the `magic' bit value... */
8829 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
8830 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
,
8831 (val
& (~SHARED_MF_CLP_MAGIC
)) | magic_val
);
8835 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8837 * @bp: driver handle
8838 * @magic_val: old value of 'magic' bit.
8840 * Takes care of CLP configurations.
8842 static void bnx2x_reset_mcp_prep(struct bnx2x
*bp
, u32
*magic_val
)
8845 u32 validity_offset
;
8847 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "Starting\n");
8849 /* Set `magic' bit in order to save MF config */
8850 if (!CHIP_IS_E1(bp
))
8851 bnx2x_clp_reset_prep(bp
, magic_val
);
8853 /* Get shmem offset */
8854 shmem
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
8856 offsetof(struct shmem_region
, validity_map
[BP_PORT(bp
)]);
8858 /* Clear validity map flags */
8860 REG_WR(bp
, shmem
+ validity_offset
, 0);
8863 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8864 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8867 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8869 * @bp: driver handle
8871 static void bnx2x_mcp_wait_one(struct bnx2x
*bp
)
8873 /* special handling for emulation and FPGA,
8874 wait 10 times longer */
8875 if (CHIP_REV_IS_SLOW(bp
))
8876 msleep(MCP_ONE_TIMEOUT
*10);
8878 msleep(MCP_ONE_TIMEOUT
);
8882 * initializes bp->common.shmem_base and waits for validity signature to appear
8884 static int bnx2x_init_shmem(struct bnx2x
*bp
)
8890 bp
->common
.shmem_base
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
8891 if (bp
->common
.shmem_base
) {
8892 val
= SHMEM_RD(bp
, validity_map
[BP_PORT(bp
)]);
8893 if (val
& SHR_MEM_VALIDITY_MB
)
8897 bnx2x_mcp_wait_one(bp
);
8899 } while (cnt
++ < (MCP_TIMEOUT
/ MCP_ONE_TIMEOUT
));
8901 BNX2X_ERR("BAD MCP validity signature\n");
8906 static int bnx2x_reset_mcp_comp(struct bnx2x
*bp
, u32 magic_val
)
8908 int rc
= bnx2x_init_shmem(bp
);
8910 /* Restore the `magic' bit value */
8911 if (!CHIP_IS_E1(bp
))
8912 bnx2x_clp_reset_done(bp
, magic_val
);
8917 static void bnx2x_pxp_prep(struct bnx2x
*bp
)
8919 if (!CHIP_IS_E1(bp
)) {
8920 REG_WR(bp
, PXP2_REG_RD_START_INIT
, 0);
8921 REG_WR(bp
, PXP2_REG_RQ_RBC_DONE
, 0);
8927 * Reset the whole chip except for:
8929 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8932 * - MISC (including AEU)
8936 static void bnx2x_process_kill_chip_reset(struct bnx2x
*bp
, bool global
)
8938 u32 not_reset_mask1
, reset_mask1
, not_reset_mask2
, reset_mask2
;
8939 u32 global_bits2
, stay_reset2
;
8942 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8943 * (per chip) blocks.
8946 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU
|
8947 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE
;
8949 /* Don't reset the following blocks.
8950 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
8951 * reset, as in 4 port device they might still be owned
8952 * by the MCP (there is only one leader per path).
8955 MISC_REGISTERS_RESET_REG_1_RST_HC
|
8956 MISC_REGISTERS_RESET_REG_1_RST_PXPV
|
8957 MISC_REGISTERS_RESET_REG_1_RST_PXP
;
8960 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO
|
8961 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
|
8962 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE
|
8963 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE
|
8964 MISC_REGISTERS_RESET_REG_2_RST_RBCN
|
8965 MISC_REGISTERS_RESET_REG_2_RST_GRC
|
8966 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE
|
8967 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B
|
8968 MISC_REGISTERS_RESET_REG_2_RST_ATC
|
8969 MISC_REGISTERS_RESET_REG_2_PGLC
|
8970 MISC_REGISTERS_RESET_REG_2_RST_BMAC0
|
8971 MISC_REGISTERS_RESET_REG_2_RST_BMAC1
|
8972 MISC_REGISTERS_RESET_REG_2_RST_EMAC0
|
8973 MISC_REGISTERS_RESET_REG_2_RST_EMAC1
|
8974 MISC_REGISTERS_RESET_REG_2_UMAC0
|
8975 MISC_REGISTERS_RESET_REG_2_UMAC1
;
8978 * Keep the following blocks in reset:
8979 * - all xxMACs are handled by the bnx2x_link code.
8982 MISC_REGISTERS_RESET_REG_2_XMAC
|
8983 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT
;
8985 /* Full reset masks according to the chip */
8986 reset_mask1
= 0xffffffff;
8989 reset_mask2
= 0xffff;
8990 else if (CHIP_IS_E1H(bp
))
8991 reset_mask2
= 0x1ffff;
8992 else if (CHIP_IS_E2(bp
))
8993 reset_mask2
= 0xfffff;
8994 else /* CHIP_IS_E3 */
8995 reset_mask2
= 0x3ffffff;
8997 /* Don't reset global blocks unless we need to */
8999 reset_mask2
&= ~global_bits2
;
9002 * In case of attention in the QM, we need to reset PXP
9003 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9004 * because otherwise QM reset would release 'close the gates' shortly
9005 * before resetting the PXP, then the PSWRQ would send a write
9006 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9007 * read the payload data from PSWWR, but PSWWR would not
9008 * respond. The write queue in PGLUE would stuck, dmae commands
9009 * would not return. Therefore it's important to reset the second
9010 * reset register (containing the
9011 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9012 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9015 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
9016 reset_mask2
& (~not_reset_mask2
));
9018 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
9019 reset_mask1
& (~not_reset_mask1
));
9024 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
9025 reset_mask2
& (~stay_reset2
));
9030 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, reset_mask1
);
9035 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9036 * It should get cleared in no more than 1s.
9038 * @bp: driver handle
9040 * It should get cleared in no more than 1s. Returns 0 if
9041 * pending writes bit gets cleared.
9043 static int bnx2x_er_poll_igu_vq(struct bnx2x
*bp
)
9049 pend_bits
= REG_RD(bp
, IGU_REG_PENDING_BITS_STATUS
);
9054 usleep_range(1000, 1000);
9055 } while (cnt
-- > 0);
9058 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9066 static int bnx2x_process_kill(struct bnx2x
*bp
, bool global
)
9070 u32 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
, pgl_exp_rom2
;
9074 /* Empty the Tetris buffer, wait for 1s */
9076 sr_cnt
= REG_RD(bp
, PXP2_REG_RD_SR_CNT
);
9077 blk_cnt
= REG_RD(bp
, PXP2_REG_RD_BLK_CNT
);
9078 port_is_idle_0
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_0
);
9079 port_is_idle_1
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_1
);
9080 pgl_exp_rom2
= REG_RD(bp
, PXP2_REG_PGL_EXP_ROM2
);
9082 tags_63_32
= REG_RD(bp
, PGLUE_B_REG_TAGS_63_32
);
9084 if ((sr_cnt
== 0x7e) && (blk_cnt
== 0xa0) &&
9085 ((port_is_idle_0
& 0x1) == 0x1) &&
9086 ((port_is_idle_1
& 0x1) == 0x1) &&
9087 (pgl_exp_rom2
== 0xffffffff) &&
9088 (!CHIP_IS_E3(bp
) || (tags_63_32
== 0xffffffff)))
9090 usleep_range(1000, 1000);
9091 } while (cnt
-- > 0);
9094 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9095 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9096 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
,
9103 /* Close gates #2, #3 and #4 */
9104 bnx2x_set_234_gates(bp
, true);
9106 /* Poll for IGU VQs for 57712 and newer chips */
9107 if (!CHIP_IS_E1x(bp
) && bnx2x_er_poll_igu_vq(bp
))
9111 /* TBD: Indicate that "process kill" is in progress to MCP */
9113 /* Clear "unprepared" bit */
9114 REG_WR(bp
, MISC_REG_UNPREPARED
, 0);
9117 /* Make sure all is written to the chip before the reset */
9120 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9121 * PSWHST, GRC and PSWRD Tetris buffer.
9123 usleep_range(1000, 1000);
9125 /* Prepare to chip reset: */
9128 bnx2x_reset_mcp_prep(bp
, &val
);
9134 /* reset the chip */
9135 bnx2x_process_kill_chip_reset(bp
, global
);
9138 /* Recover after reset: */
9140 if (global
&& bnx2x_reset_mcp_comp(bp
, val
))
9143 /* TBD: Add resetting the NO_MCP mode DB here */
9145 /* Open the gates #2, #3 and #4 */
9146 bnx2x_set_234_gates(bp
, false);
9148 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9149 * reset state, re-enable attentions. */
9154 static int bnx2x_leader_reset(struct bnx2x
*bp
)
9157 bool global
= bnx2x_reset_is_global(bp
);
9160 /* if not going to reset MCP - load "fake" driver to reset HW while
9161 * driver is owner of the HW
9163 if (!global
&& !BP_NOMCP(bp
)) {
9164 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_REQ
,
9165 DRV_MSG_CODE_LOAD_REQ_WITH_LFA
);
9167 BNX2X_ERR("MCP response failure, aborting\n");
9169 goto exit_leader_reset
;
9171 if ((load_code
!= FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
) &&
9172 (load_code
!= FW_MSG_CODE_DRV_LOAD_COMMON
)) {
9173 BNX2X_ERR("MCP unexpected resp, aborting\n");
9175 goto exit_leader_reset2
;
9177 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_DONE
, 0);
9179 BNX2X_ERR("MCP response failure, aborting\n");
9181 goto exit_leader_reset2
;
9185 /* Try to recover after the failure */
9186 if (bnx2x_process_kill(bp
, global
)) {
9187 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9190 goto exit_leader_reset2
;
9194 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9197 bnx2x_set_reset_done(bp
);
9199 bnx2x_clear_reset_global(bp
);
9202 /* unload "fake driver" if it was loaded */
9203 if (!global
&& !BP_NOMCP(bp
)) {
9204 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
, 0);
9205 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, 0);
9209 bnx2x_release_leader_lock(bp
);
9214 static void bnx2x_recovery_failed(struct bnx2x
*bp
)
9216 netdev_err(bp
->dev
, "Recovery has failed. Power cycle is needed.\n");
9218 /* Disconnect this device */
9219 netif_device_detach(bp
->dev
);
9222 * Block ifup for all function on this engine until "process kill"
9225 bnx2x_set_reset_in_progress(bp
);
9227 /* Shut down the power */
9228 bnx2x_set_power_state(bp
, PCI_D3hot
);
9230 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
9236 * Assumption: runs under rtnl lock. This together with the fact
9237 * that it's called only from bnx2x_sp_rtnl() ensure that it
9238 * will never be called when netif_running(bp->dev) is false.
9240 static void bnx2x_parity_recover(struct bnx2x
*bp
)
9242 bool global
= false;
9243 u32 error_recovered
, error_unrecovered
;
9246 DP(NETIF_MSG_HW
, "Handling parity\n");
9248 switch (bp
->recovery_state
) {
9249 case BNX2X_RECOVERY_INIT
:
9250 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_INIT\n");
9251 is_parity
= bnx2x_chk_parity_attn(bp
, &global
, false);
9252 WARN_ON(!is_parity
);
9254 /* Try to get a LEADER_LOCK HW lock */
9255 if (bnx2x_trylock_leader_lock(bp
)) {
9256 bnx2x_set_reset_in_progress(bp
);
9258 * Check if there is a global attention and if
9259 * there was a global attention, set the global
9264 bnx2x_set_reset_global(bp
);
9269 /* Stop the driver */
9270 /* If interface has been removed - break */
9271 if (bnx2x_nic_unload(bp
, UNLOAD_RECOVERY
, false))
9274 bp
->recovery_state
= BNX2X_RECOVERY_WAIT
;
9276 /* Ensure "is_leader", MCP command sequence and
9277 * "recovery_state" update values are seen on other
9283 case BNX2X_RECOVERY_WAIT
:
9284 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_WAIT\n");
9285 if (bp
->is_leader
) {
9286 int other_engine
= BP_PATH(bp
) ? 0 : 1;
9287 bool other_load_status
=
9288 bnx2x_get_load_status(bp
, other_engine
);
9290 bnx2x_get_load_status(bp
, BP_PATH(bp
));
9291 global
= bnx2x_reset_is_global(bp
);
9294 * In case of a parity in a global block, let
9295 * the first leader that performs a
9296 * leader_reset() reset the global blocks in
9297 * order to clear global attentions. Otherwise
9298 * the the gates will remain closed for that
9302 (global
&& other_load_status
)) {
9303 /* Wait until all other functions get
9306 schedule_delayed_work(&bp
->sp_rtnl_task
,
9310 /* If all other functions got down -
9311 * try to bring the chip back to
9312 * normal. In any case it's an exit
9313 * point for a leader.
9315 if (bnx2x_leader_reset(bp
)) {
9316 bnx2x_recovery_failed(bp
);
9320 /* If we are here, means that the
9321 * leader has succeeded and doesn't
9322 * want to be a leader any more. Try
9323 * to continue as a none-leader.
9327 } else { /* non-leader */
9328 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
))) {
9329 /* Try to get a LEADER_LOCK HW lock as
9330 * long as a former leader may have
9331 * been unloaded by the user or
9332 * released a leadership by another
9335 if (bnx2x_trylock_leader_lock(bp
)) {
9336 /* I'm a leader now! Restart a
9343 schedule_delayed_work(&bp
->sp_rtnl_task
,
9349 * If there was a global attention, wait
9350 * for it to be cleared.
9352 if (bnx2x_reset_is_global(bp
)) {
9353 schedule_delayed_work(
9360 bp
->eth_stats
.recoverable_error
;
9362 bp
->eth_stats
.unrecoverable_error
;
9363 bp
->recovery_state
=
9364 BNX2X_RECOVERY_NIC_LOADING
;
9365 if (bnx2x_nic_load(bp
, LOAD_NORMAL
)) {
9366 error_unrecovered
++;
9368 "Recovery failed. Power cycle needed\n");
9369 /* Disconnect this device */
9370 netif_device_detach(bp
->dev
);
9371 /* Shut down the power */
9372 bnx2x_set_power_state(
9376 bp
->recovery_state
=
9377 BNX2X_RECOVERY_DONE
;
9381 bp
->eth_stats
.recoverable_error
=
9383 bp
->eth_stats
.unrecoverable_error
=
9395 static int bnx2x_close(struct net_device
*dev
);
9397 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9398 * scheduled on a general queue in order to prevent a dead lock.
9400 static void bnx2x_sp_rtnl_task(struct work_struct
*work
)
9402 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_rtnl_task
.work
);
9406 if (!netif_running(bp
->dev
)) {
9411 /* if stop on error is defined no recovery flows should be executed */
9412 #ifdef BNX2X_STOP_ON_ERROR
9413 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9414 "you will need to reboot when done\n");
9415 goto sp_rtnl_not_reset
;
9418 if (unlikely(bp
->recovery_state
!= BNX2X_RECOVERY_DONE
)) {
9420 * Clear all pending SP commands as we are going to reset the
9423 bp
->sp_rtnl_state
= 0;
9426 bnx2x_parity_recover(bp
);
9432 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT
, &bp
->sp_rtnl_state
)) {
9434 * Clear all pending SP commands as we are going to reset the
9437 bp
->sp_rtnl_state
= 0;
9440 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
, true);
9441 bnx2x_nic_load(bp
, LOAD_NORMAL
);
9446 #ifdef BNX2X_STOP_ON_ERROR
9449 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC
, &bp
->sp_rtnl_state
))
9450 bnx2x_setup_tc(bp
->dev
, bp
->dcbx_port_params
.ets
.num_of_cos
);
9451 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE
, &bp
->sp_rtnl_state
))
9452 bnx2x_after_function_update(bp
);
9454 * in case of fan failure we need to reset id if the "stop on error"
9455 * debug flag is set, since we trying to prevent permanent overheating
9458 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE
, &bp
->sp_rtnl_state
)) {
9459 DP(NETIF_MSG_HW
, "fan failure detected. Unloading driver\n");
9460 netif_device_detach(bp
->dev
);
9461 bnx2x_close(bp
->dev
);
9466 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST
, &bp
->sp_rtnl_state
)) {
9468 "sending set mcast vf pf channel message from rtnl sp-task\n");
9469 bnx2x_vfpf_set_mcast(bp
->dev
);
9472 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE
,
9473 &bp
->sp_rtnl_state
)) {
9475 "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9476 bnx2x_vfpf_storm_rx_mode(bp
);
9479 /* work which needs rtnl lock not-taken (as it takes the lock itself and
9480 * can be called from other contexts as well)
9484 /* enable SR-IOV if applicable */
9485 if (IS_SRIOV(bp
) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV
,
9486 &bp
->sp_rtnl_state
))
9487 bnx2x_enable_sriov(bp
);
9490 static void bnx2x_period_task(struct work_struct
*work
)
9492 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, period_task
.work
);
9494 if (!netif_running(bp
->dev
))
9495 goto period_task_exit
;
9497 if (CHIP_REV_IS_SLOW(bp
)) {
9498 BNX2X_ERR("period task called on emulation, ignoring\n");
9499 goto period_task_exit
;
9502 bnx2x_acquire_phy_lock(bp
);
9504 * The barrier is needed to ensure the ordering between the writing to
9505 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9510 bnx2x_period_func(&bp
->link_params
, &bp
->link_vars
);
9512 /* Re-queue task in 1 sec */
9513 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 1*HZ
);
9516 bnx2x_release_phy_lock(bp
);
9522 * Init service functions
9525 u32
bnx2x_get_pretend_reg(struct bnx2x
*bp
)
9527 u32 base
= PXP2_REG_PGL_PRETEND_FUNC_F0
;
9528 u32 stride
= PXP2_REG_PGL_PRETEND_FUNC_F1
- base
;
9529 return base
+ (BP_ABS_FUNC(bp
)) * stride
;
9532 static void bnx2x_undi_int_disable_e1h(struct bnx2x
*bp
)
9534 u32 reg
= bnx2x_get_pretend_reg(bp
);
9536 /* Flush all outstanding writes */
9539 /* Pretend to be function 0 */
9541 REG_RD(bp
, reg
); /* Flush the GRC transaction (in the chip) */
9543 /* From now we are in the "like-E1" mode */
9544 bnx2x_int_disable(bp
);
9546 /* Flush all outstanding writes */
9549 /* Restore the original function */
9550 REG_WR(bp
, reg
, BP_ABS_FUNC(bp
));
9554 static inline void bnx2x_undi_int_disable(struct bnx2x
*bp
)
9557 bnx2x_int_disable(bp
);
9559 bnx2x_undi_int_disable_e1h(bp
);
9562 static void bnx2x_prev_unload_close_mac(struct bnx2x
*bp
,
9563 struct bnx2x_mac_vals
*vals
)
9565 u32 val
, base_addr
, offset
, mask
, reset_reg
;
9566 bool mac_stopped
= false;
9567 u8 port
= BP_PORT(bp
);
9569 /* reset addresses as they also mark which values were changed */
9570 vals
->bmac_addr
= 0;
9571 vals
->umac_addr
= 0;
9572 vals
->xmac_addr
= 0;
9573 vals
->emac_addr
= 0;
9575 reset_reg
= REG_RD(bp
, MISC_REG_RESET_REG_2
);
9577 if (!CHIP_IS_E3(bp
)) {
9578 val
= REG_RD(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
* 4);
9579 mask
= MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
;
9580 if ((mask
& reset_reg
) && val
) {
9582 BNX2X_DEV_INFO("Disable bmac Rx\n");
9583 base_addr
= BP_PORT(bp
) ? NIG_REG_INGRESS_BMAC1_MEM
9584 : NIG_REG_INGRESS_BMAC0_MEM
;
9585 offset
= CHIP_IS_E2(bp
) ? BIGMAC2_REGISTER_BMAC_CONTROL
9586 : BIGMAC_REGISTER_BMAC_CONTROL
;
9589 * use rd/wr since we cannot use dmae. This is safe
9590 * since MCP won't access the bus due to the request
9591 * to unload, and no function on the path can be
9592 * loaded at this time.
9594 wb_data
[0] = REG_RD(bp
, base_addr
+ offset
);
9595 wb_data
[1] = REG_RD(bp
, base_addr
+ offset
+ 0x4);
9596 vals
->bmac_addr
= base_addr
+ offset
;
9597 vals
->bmac_val
[0] = wb_data
[0];
9598 vals
->bmac_val
[1] = wb_data
[1];
9599 wb_data
[0] &= ~BMAC_CONTROL_RX_ENABLE
;
9600 REG_WR(bp
, vals
->bmac_addr
, wb_data
[0]);
9601 REG_WR(bp
, vals
->bmac_addr
+ 0x4, wb_data
[1]);
9604 BNX2X_DEV_INFO("Disable emac Rx\n");
9605 vals
->emac_addr
= NIG_REG_NIG_EMAC0_EN
+ BP_PORT(bp
)*4;
9606 vals
->emac_val
= REG_RD(bp
, vals
->emac_addr
);
9607 REG_WR(bp
, vals
->emac_addr
, 0);
9610 if (reset_reg
& MISC_REGISTERS_RESET_REG_2_XMAC
) {
9611 BNX2X_DEV_INFO("Disable xmac Rx\n");
9612 base_addr
= BP_PORT(bp
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
9613 val
= REG_RD(bp
, base_addr
+ XMAC_REG_PFC_CTRL_HI
);
9614 REG_WR(bp
, base_addr
+ XMAC_REG_PFC_CTRL_HI
,
9616 REG_WR(bp
, base_addr
+ XMAC_REG_PFC_CTRL_HI
,
9618 vals
->xmac_addr
= base_addr
+ XMAC_REG_CTRL
;
9619 vals
->xmac_val
= REG_RD(bp
, vals
->xmac_addr
);
9620 REG_WR(bp
, vals
->xmac_addr
, 0);
9623 mask
= MISC_REGISTERS_RESET_REG_2_UMAC0
<< port
;
9624 if (mask
& reset_reg
) {
9625 BNX2X_DEV_INFO("Disable umac Rx\n");
9626 base_addr
= BP_PORT(bp
) ? GRCBASE_UMAC1
: GRCBASE_UMAC0
;
9627 vals
->umac_addr
= base_addr
+ UMAC_REG_COMMAND_CONFIG
;
9628 vals
->umac_val
= REG_RD(bp
, vals
->umac_addr
);
9629 REG_WR(bp
, vals
->umac_addr
, 0);
9639 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9640 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9641 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9642 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9644 static void bnx2x_prev_unload_undi_inc(struct bnx2x
*bp
, u8 port
, u8 inc
)
9647 u32 tmp_reg
= REG_RD(bp
, BNX2X_PREV_UNDI_PROD_ADDR(port
));
9649 rcq
= BNX2X_PREV_UNDI_RCQ(tmp_reg
) + inc
;
9650 bd
= BNX2X_PREV_UNDI_BD(tmp_reg
) + inc
;
9652 tmp_reg
= BNX2X_PREV_UNDI_PROD(rcq
, bd
);
9653 REG_WR(bp
, BNX2X_PREV_UNDI_PROD_ADDR(port
), tmp_reg
);
9655 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9659 static int bnx2x_prev_mcp_done(struct bnx2x
*bp
)
9661 u32 rc
= bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
,
9662 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET
);
9664 BNX2X_ERR("MCP response failure, aborting\n");
9671 static struct bnx2x_prev_path_list
*
9672 bnx2x_prev_path_get_entry(struct bnx2x
*bp
)
9674 struct bnx2x_prev_path_list
*tmp_list
;
9676 list_for_each_entry(tmp_list
, &bnx2x_prev_list
, list
)
9677 if (PCI_SLOT(bp
->pdev
->devfn
) == tmp_list
->slot
&&
9678 bp
->pdev
->bus
->number
== tmp_list
->bus
&&
9679 BP_PATH(bp
) == tmp_list
->path
)
9685 static bool bnx2x_prev_is_path_marked(struct bnx2x
*bp
)
9687 struct bnx2x_prev_path_list
*tmp_list
;
9690 if (down_trylock(&bnx2x_prev_sem
))
9693 list_for_each_entry(tmp_list
, &bnx2x_prev_list
, list
) {
9694 if (PCI_SLOT(bp
->pdev
->devfn
) == tmp_list
->slot
&&
9695 bp
->pdev
->bus
->number
== tmp_list
->bus
&&
9696 BP_PATH(bp
) == tmp_list
->path
) {
9698 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9704 up(&bnx2x_prev_sem
);
9709 static int bnx2x_prev_mark_path(struct bnx2x
*bp
, bool after_undi
)
9711 struct bnx2x_prev_path_list
*tmp_list
;
9714 tmp_list
= kmalloc(sizeof(struct bnx2x_prev_path_list
), GFP_KERNEL
);
9716 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9720 tmp_list
->bus
= bp
->pdev
->bus
->number
;
9721 tmp_list
->slot
= PCI_SLOT(bp
->pdev
->devfn
);
9722 tmp_list
->path
= BP_PATH(bp
);
9723 tmp_list
->undi
= after_undi
? (1 << BP_PORT(bp
)) : 0;
9725 rc
= down_interruptible(&bnx2x_prev_sem
);
9727 BNX2X_ERR("Received %d when tried to take lock\n", rc
);
9730 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9732 list_add(&tmp_list
->list
, &bnx2x_prev_list
);
9733 up(&bnx2x_prev_sem
);
9739 static int bnx2x_do_flr(struct bnx2x
*bp
)
9743 struct pci_dev
*dev
= bp
->pdev
;
9746 if (CHIP_IS_E1x(bp
)) {
9747 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9751 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9752 if (bp
->common
.bc_ver
< REQ_BC_VER_4_INITIATE_FLR
) {
9753 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9758 /* Wait for Transaction Pending bit clean */
9759 for (i
= 0; i
< 4; i
++) {
9761 msleep((1 << (i
- 1)) * 100);
9763 pcie_capability_read_word(dev
, PCI_EXP_DEVSTA
, &status
);
9764 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
9769 "transaction is not cleared; proceeding with reset anyway\n");
9773 BNX2X_DEV_INFO("Initiating FLR\n");
9774 bnx2x_fw_command(bp
, DRV_MSG_CODE_INITIATE_FLR
, 0);
9779 static int bnx2x_prev_unload_uncommon(struct bnx2x
*bp
)
9783 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9785 /* Test if previous unload process was already finished for this path */
9786 if (bnx2x_prev_is_path_marked(bp
))
9787 return bnx2x_prev_mcp_done(bp
);
9789 /* If function has FLR capabilities, and existing FW version matches
9790 * the one required, then FLR will be sufficient to clean any residue
9791 * left by previous driver
9793 rc
= bnx2x_nic_load_analyze_req(bp
, FW_MSG_CODE_DRV_LOAD_FUNCTION
);
9796 /* fw version is good */
9797 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9798 rc
= bnx2x_do_flr(bp
);
9802 /* FLR was performed */
9803 BNX2X_DEV_INFO("FLR successful\n");
9807 BNX2X_DEV_INFO("Could not FLR\n");
9809 /* Close the MCP request, return failure*/
9810 rc
= bnx2x_prev_mcp_done(bp
);
9812 rc
= BNX2X_PREV_WAIT_NEEDED
;
9817 static int bnx2x_prev_unload_common(struct bnx2x
*bp
)
9819 u32 reset_reg
, tmp_reg
= 0, rc
;
9820 bool prev_undi
= false;
9821 struct bnx2x_mac_vals mac_vals
;
9823 /* It is possible a previous function received 'common' answer,
9824 * but hasn't loaded yet, therefore creating a scenario of
9825 * multiple functions receiving 'common' on the same path.
9827 BNX2X_DEV_INFO("Common unload Flow\n");
9829 memset(&mac_vals
, 0, sizeof(mac_vals
));
9831 if (bnx2x_prev_is_path_marked(bp
))
9832 return bnx2x_prev_mcp_done(bp
);
9834 reset_reg
= REG_RD(bp
, MISC_REG_RESET_REG_1
);
9836 /* Reset should be performed after BRB is emptied */
9837 if (reset_reg
& MISC_REGISTERS_RESET_REG_1_RST_BRB1
) {
9838 u32 timer_count
= 1000;
9840 /* Close the MAC Rx to prevent BRB from filling up */
9841 bnx2x_prev_unload_close_mac(bp
, &mac_vals
);
9843 /* close LLH filters towards the BRB */
9844 bnx2x_set_rx_filter(&bp
->link_params
, 0);
9846 /* Check if the UNDI driver was previously loaded
9847 * UNDI driver initializes CID offset for normal bell to 0x7
9849 reset_reg
= REG_RD(bp
, MISC_REG_RESET_REG_1
);
9850 if (reset_reg
& MISC_REGISTERS_RESET_REG_1_RST_DORQ
) {
9851 tmp_reg
= REG_RD(bp
, DORQ_REG_NORM_CID_OFST
);
9852 if (tmp_reg
== 0x7) {
9853 BNX2X_DEV_INFO("UNDI previously loaded\n");
9855 /* clear the UNDI indication */
9856 REG_WR(bp
, DORQ_REG_NORM_CID_OFST
, 0);
9859 /* wait until BRB is empty */
9860 tmp_reg
= REG_RD(bp
, BRB1_REG_NUM_OF_FULL_BLOCKS
);
9861 while (timer_count
) {
9862 u32 prev_brb
= tmp_reg
;
9864 tmp_reg
= REG_RD(bp
, BRB1_REG_NUM_OF_FULL_BLOCKS
);
9868 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg
);
9870 /* reset timer as long as BRB actually gets emptied */
9871 if (prev_brb
> tmp_reg
)
9876 /* If UNDI resides in memory, manually increment it */
9878 bnx2x_prev_unload_undi_inc(bp
, BP_PORT(bp
), 1);
9884 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9888 /* No packets are in the pipeline, path is ready for reset */
9889 bnx2x_reset_common(bp
);
9891 if (mac_vals
.xmac_addr
)
9892 REG_WR(bp
, mac_vals
.xmac_addr
, mac_vals
.xmac_val
);
9893 if (mac_vals
.umac_addr
)
9894 REG_WR(bp
, mac_vals
.umac_addr
, mac_vals
.umac_val
);
9895 if (mac_vals
.emac_addr
)
9896 REG_WR(bp
, mac_vals
.emac_addr
, mac_vals
.emac_val
);
9897 if (mac_vals
.bmac_addr
) {
9898 REG_WR(bp
, mac_vals
.bmac_addr
, mac_vals
.bmac_val
[0]);
9899 REG_WR(bp
, mac_vals
.bmac_addr
+ 4, mac_vals
.bmac_val
[1]);
9902 rc
= bnx2x_prev_mark_path(bp
, prev_undi
);
9904 bnx2x_prev_mcp_done(bp
);
9908 return bnx2x_prev_mcp_done(bp
);
9911 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9912 * and boot began, or when kdump kernel was loaded. Either case would invalidate
9913 * the addresses of the transaction, resulting in was-error bit set in the pci
9914 * causing all hw-to-host pcie transactions to timeout. If this happened we want
9915 * to clear the interrupt which detected this from the pglueb and the was done
9918 static void bnx2x_prev_interrupted_dmae(struct bnx2x
*bp
)
9920 if (!CHIP_IS_E1x(bp
)) {
9921 u32 val
= REG_RD(bp
, PGLUE_B_REG_PGLUE_B_INT_STS
);
9922 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN
) {
9923 BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9924 REG_WR(bp
, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR
,
9930 static int bnx2x_prev_unload(struct bnx2x
*bp
)
9932 int time_counter
= 10;
9933 u32 rc
, fw
, hw_lock_reg
, hw_lock_val
;
9934 struct bnx2x_prev_path_list
*prev_list
;
9935 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9937 /* clear hw from errors which may have resulted from an interrupted
9940 bnx2x_prev_interrupted_dmae(bp
);
9942 /* Release previously held locks */
9943 hw_lock_reg
= (BP_FUNC(bp
) <= 5) ?
9944 (MISC_REG_DRIVER_CONTROL_1
+ BP_FUNC(bp
) * 8) :
9945 (MISC_REG_DRIVER_CONTROL_7
+ (BP_FUNC(bp
) - 6) * 8);
9947 hw_lock_val
= (REG_RD(bp
, hw_lock_reg
));
9949 if (hw_lock_val
& HW_LOCK_RESOURCE_NVRAM
) {
9950 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9951 REG_WR(bp
, MCP_REG_MCPR_NVM_SW_ARB
,
9952 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1
<< BP_PORT(bp
)));
9955 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9956 REG_WR(bp
, hw_lock_reg
, 0xffffffff);
9958 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9960 if (MCPR_ACCESS_LOCK_LOCK
& REG_RD(bp
, MCP_REG_MCPR_ACCESS_LOCK
)) {
9961 BNX2X_DEV_INFO("Release previously held alr\n");
9962 REG_WR(bp
, MCP_REG_MCPR_ACCESS_LOCK
, 0);
9967 /* Lock MCP using an unload request */
9968 fw
= bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
, 0);
9970 BNX2X_ERR("MCP response failure, aborting\n");
9975 if (fw
== FW_MSG_CODE_DRV_UNLOAD_COMMON
) {
9976 rc
= bnx2x_prev_unload_common(bp
);
9980 /* non-common reply from MCP night require looping */
9981 rc
= bnx2x_prev_unload_uncommon(bp
);
9982 if (rc
!= BNX2X_PREV_WAIT_NEEDED
)
9986 } while (--time_counter
);
9988 if (!time_counter
|| rc
) {
9989 BNX2X_ERR("Failed unloading previous driver, aborting\n");
9993 /* Mark function if its port was used to boot from SAN */
9994 prev_list
= bnx2x_prev_path_get_entry(bp
);
9995 if (prev_list
&& (prev_list
->undi
& (1 << BP_PORT(bp
))))
9996 bp
->link_params
.feature_config_flags
|=
9997 FEATURE_CONFIG_BOOT_FROM_SAN
;
9999 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc
);
10004 static void bnx2x_get_common_hwinfo(struct bnx2x
*bp
)
10006 u32 val
, val2
, val3
, val4
, id
, boot_mode
;
10009 /* Get the chip revision id and number. */
10010 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10011 val
= REG_RD(bp
, MISC_REG_CHIP_NUM
);
10012 id
= ((val
& 0xffff) << 16);
10013 val
= REG_RD(bp
, MISC_REG_CHIP_REV
);
10014 id
|= ((val
& 0xf) << 12);
10015 val
= REG_RD(bp
, MISC_REG_CHIP_METAL
);
10016 id
|= ((val
& 0xff) << 4);
10017 val
= REG_RD(bp
, MISC_REG_BOND_ID
);
10019 bp
->common
.chip_id
= id
;
10021 /* force 57811 according to MISC register */
10022 if (REG_RD(bp
, MISC_REG_CHIP_TYPE
) & MISC_REG_CHIP_TYPE_57811_MASK
) {
10023 if (CHIP_IS_57810(bp
))
10024 bp
->common
.chip_id
= (CHIP_NUM_57811
<< 16) |
10025 (bp
->common
.chip_id
& 0x0000FFFF);
10026 else if (CHIP_IS_57810_MF(bp
))
10027 bp
->common
.chip_id
= (CHIP_NUM_57811_MF
<< 16) |
10028 (bp
->common
.chip_id
& 0x0000FFFF);
10029 bp
->common
.chip_id
|= 0x1;
10032 /* Set doorbell size */
10033 bp
->db_size
= (1 << BNX2X_DB_SHIFT
);
10035 if (!CHIP_IS_E1x(bp
)) {
10036 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN_OVWR
);
10037 if ((val
& 1) == 0)
10038 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN
);
10040 val
= (val
>> 1) & 1;
10041 BNX2X_DEV_INFO("chip is in %s\n", val
? "4_PORT_MODE" :
10043 bp
->common
.chip_port_mode
= val
? CHIP_4_PORT_MODE
:
10046 if (CHIP_MODE_IS_4_PORT(bp
))
10047 bp
->pfid
= (bp
->pf_num
>> 1); /* 0..3 */
10049 bp
->pfid
= (bp
->pf_num
& 0x6); /* 0, 2, 4, 6 */
10051 bp
->common
.chip_port_mode
= CHIP_PORT_MODE_NONE
; /* N/A */
10052 bp
->pfid
= bp
->pf_num
; /* 0..7 */
10055 BNX2X_DEV_INFO("pf_id: %x", bp
->pfid
);
10057 bp
->link_params
.chip_id
= bp
->common
.chip_id
;
10058 BNX2X_DEV_INFO("chip ID is 0x%x\n", id
);
10060 val
= (REG_RD(bp
, 0x2874) & 0x55);
10061 if ((bp
->common
.chip_id
& 0x1) ||
10062 (CHIP_IS_E1(bp
) && val
) || (CHIP_IS_E1H(bp
) && (val
== 0x55))) {
10063 bp
->flags
|= ONE_PORT_FLAG
;
10064 BNX2X_DEV_INFO("single port device\n");
10067 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_CFG4
);
10068 bp
->common
.flash_size
= (BNX2X_NVRAM_1MB_SIZE
<<
10069 (val
& MCPR_NVM_CFG4_FLASH_SIZE
));
10070 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10071 bp
->common
.flash_size
, bp
->common
.flash_size
);
10073 bnx2x_init_shmem(bp
);
10077 bp
->common
.shmem2_base
= REG_RD(bp
, (BP_PATH(bp
) ?
10078 MISC_REG_GENERIC_CR_1
:
10079 MISC_REG_GENERIC_CR_0
));
10081 bp
->link_params
.shmem_base
= bp
->common
.shmem_base
;
10082 bp
->link_params
.shmem2_base
= bp
->common
.shmem2_base
;
10083 if (SHMEM2_RD(bp
, size
) >
10084 (u32
)offsetof(struct shmem2_region
, lfa_host_addr
[BP_PORT(bp
)]))
10085 bp
->link_params
.lfa_base
=
10086 REG_RD(bp
, bp
->common
.shmem2_base
+
10087 (u32
)offsetof(struct shmem2_region
,
10088 lfa_host_addr
[BP_PORT(bp
)]));
10090 bp
->link_params
.lfa_base
= 0;
10091 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10092 bp
->common
.shmem_base
, bp
->common
.shmem2_base
);
10094 if (!bp
->common
.shmem_base
) {
10095 BNX2X_DEV_INFO("MCP not active\n");
10096 bp
->flags
|= NO_MCP_FLAG
;
10100 bp
->common
.hw_config
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config
);
10101 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp
->common
.hw_config
);
10103 bp
->link_params
.hw_led_mode
= ((bp
->common
.hw_config
&
10104 SHARED_HW_CFG_LED_MODE_MASK
) >>
10105 SHARED_HW_CFG_LED_MODE_SHIFT
);
10107 bp
->link_params
.feature_config_flags
= 0;
10108 val
= SHMEM_RD(bp
, dev_info
.shared_feature_config
.config
);
10109 if (val
& SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED
)
10110 bp
->link_params
.feature_config_flags
|=
10111 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
10113 bp
->link_params
.feature_config_flags
&=
10114 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
10116 val
= SHMEM_RD(bp
, dev_info
.bc_rev
) >> 8;
10117 bp
->common
.bc_ver
= val
;
10118 BNX2X_DEV_INFO("bc_ver %X\n", val
);
10119 if (val
< BNX2X_BC_VER
) {
10120 /* for now only warn
10121 * later we might need to enforce this */
10122 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10123 BNX2X_BC_VER
, val
);
10125 bp
->link_params
.feature_config_flags
|=
10126 (val
>= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL
) ?
10127 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY
: 0;
10129 bp
->link_params
.feature_config_flags
|=
10130 (val
>= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL
) ?
10131 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY
: 0;
10132 bp
->link_params
.feature_config_flags
|=
10133 (val
>= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED
) ?
10134 FEATURE_CONFIG_BC_SUPPORTS_AFEX
: 0;
10135 bp
->link_params
.feature_config_flags
|=
10136 (val
>= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED
) ?
10137 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED
: 0;
10139 bp
->link_params
.feature_config_flags
|=
10140 (val
>= REQ_BC_VER_4_MT_SUPPORTED
) ?
10141 FEATURE_CONFIG_MT_SUPPORT
: 0;
10143 bp
->flags
|= (val
>= REQ_BC_VER_4_PFC_STATS_SUPPORTED
) ?
10144 BC_SUPPORTS_PFC_STATS
: 0;
10146 bp
->flags
|= (val
>= REQ_BC_VER_4_FCOE_FEATURES
) ?
10147 BC_SUPPORTS_FCOE_FEATURES
: 0;
10149 bp
->flags
|= (val
>= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF
) ?
10150 BC_SUPPORTS_DCBX_MSG_NON_PMF
: 0;
10151 boot_mode
= SHMEM_RD(bp
,
10152 dev_info
.port_feature_config
[BP_PORT(bp
)].mba_config
) &
10153 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK
;
10154 switch (boot_mode
) {
10155 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE
:
10156 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_PXE
;
10158 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB
:
10159 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_ISCSI
;
10161 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT
:
10162 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_FCOE
;
10164 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE
:
10165 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_NONE
;
10169 pci_read_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_PMC
, &pmc
);
10170 bp
->flags
|= (pmc
& PCI_PM_CAP_PME_D3cold
) ? 0 : NO_WOL_FLAG
;
10172 BNX2X_DEV_INFO("%sWoL capable\n",
10173 (bp
->flags
& NO_WOL_FLAG
) ? "not " : "");
10175 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
);
10176 val2
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[4]);
10177 val3
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[8]);
10178 val4
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[12]);
10180 dev_info(&bp
->pdev
->dev
, "part number %X-%X-%X-%X\n",
10181 val
, val2
, val3
, val4
);
10184 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10185 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10187 static int bnx2x_get_igu_cam_info(struct bnx2x
*bp
)
10189 int pfid
= BP_FUNC(bp
);
10192 u8 fid
, igu_sb_cnt
= 0;
10194 bp
->igu_base_sb
= 0xff;
10195 if (CHIP_INT_MODE_IS_BC(bp
)) {
10196 int vn
= BP_VN(bp
);
10197 igu_sb_cnt
= bp
->igu_sb_cnt
;
10198 bp
->igu_base_sb
= (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
) *
10201 bp
->igu_dsb_id
= E1HVN_MAX
* FP_SB_MAX_E1x
+
10202 (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
);
10207 /* IGU in normal mode - read CAM */
10208 for (igu_sb_id
= 0; igu_sb_id
< IGU_REG_MAPPING_MEMORY_SIZE
;
10210 val
= REG_RD(bp
, IGU_REG_MAPPING_MEMORY
+ igu_sb_id
* 4);
10211 if (!(val
& IGU_REG_MAPPING_MEMORY_VALID
))
10213 fid
= IGU_FID(val
);
10214 if ((fid
& IGU_FID_ENCODE_IS_PF
)) {
10215 if ((fid
& IGU_FID_PF_NUM_MASK
) != pfid
)
10217 if (IGU_VEC(val
) == 0)
10218 /* default status block */
10219 bp
->igu_dsb_id
= igu_sb_id
;
10221 if (bp
->igu_base_sb
== 0xff)
10222 bp
->igu_base_sb
= igu_sb_id
;
10228 #ifdef CONFIG_PCI_MSI
10229 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10230 * optional that number of CAM entries will not be equal to the value
10231 * advertised in PCI.
10232 * Driver should use the minimal value of both as the actual status
10235 bp
->igu_sb_cnt
= min_t(int, bp
->igu_sb_cnt
, igu_sb_cnt
);
10238 if (igu_sb_cnt
== 0) {
10239 BNX2X_ERR("CAM configuration error\n");
10246 static void bnx2x_link_settings_supported(struct bnx2x
*bp
, u32 switch_cfg
)
10248 int cfg_size
= 0, idx
, port
= BP_PORT(bp
);
10250 /* Aggregation of supported attributes of all external phys */
10251 bp
->port
.supported
[0] = 0;
10252 bp
->port
.supported
[1] = 0;
10253 switch (bp
->link_params
.num_phys
) {
10255 bp
->port
.supported
[0] = bp
->link_params
.phy
[INT_PHY
].supported
;
10259 bp
->port
.supported
[0] = bp
->link_params
.phy
[EXT_PHY1
].supported
;
10263 if (bp
->link_params
.multi_phy_config
&
10264 PORT_HW_CFG_PHY_SWAPPED_ENABLED
) {
10265 bp
->port
.supported
[1] =
10266 bp
->link_params
.phy
[EXT_PHY1
].supported
;
10267 bp
->port
.supported
[0] =
10268 bp
->link_params
.phy
[EXT_PHY2
].supported
;
10270 bp
->port
.supported
[0] =
10271 bp
->link_params
.phy
[EXT_PHY1
].supported
;
10272 bp
->port
.supported
[1] =
10273 bp
->link_params
.phy
[EXT_PHY2
].supported
;
10279 if (!(bp
->port
.supported
[0] || bp
->port
.supported
[1])) {
10280 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10282 dev_info
.port_hw_config
[port
].external_phy_config
),
10284 dev_info
.port_hw_config
[port
].external_phy_config2
));
10288 if (CHIP_IS_E3(bp
))
10289 bp
->port
.phy_addr
= REG_RD(bp
, MISC_REG_WC0_CTRL_PHY_ADDR
);
10291 switch (switch_cfg
) {
10292 case SWITCH_CFG_1G
:
10293 bp
->port
.phy_addr
= REG_RD(
10294 bp
, NIG_REG_SERDES0_CTRL_PHY_ADDR
+ port
*0x10);
10296 case SWITCH_CFG_10G
:
10297 bp
->port
.phy_addr
= REG_RD(
10298 bp
, NIG_REG_XGXS0_CTRL_PHY_ADDR
+ port
*0x18);
10301 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10302 bp
->port
.link_config
[0]);
10306 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp
->port
.phy_addr
);
10307 /* mask what we support according to speed_cap_mask per configuration */
10308 for (idx
= 0; idx
< cfg_size
; idx
++) {
10309 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
10310 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
))
10311 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Half
;
10313 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
10314 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
))
10315 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Full
;
10317 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
10318 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
))
10319 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Half
;
10321 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
10322 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
))
10323 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Full
;
10325 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
10326 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
))
10327 bp
->port
.supported
[idx
] &= ~(SUPPORTED_1000baseT_Half
|
10328 SUPPORTED_1000baseT_Full
);
10330 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
10331 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
))
10332 bp
->port
.supported
[idx
] &= ~SUPPORTED_2500baseX_Full
;
10334 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
10335 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
))
10336 bp
->port
.supported
[idx
] &= ~SUPPORTED_10000baseT_Full
;
10340 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp
->port
.supported
[0],
10341 bp
->port
.supported
[1]);
10344 static void bnx2x_link_settings_requested(struct bnx2x
*bp
)
10346 u32 link_config
, idx
, cfg_size
= 0;
10347 bp
->port
.advertising
[0] = 0;
10348 bp
->port
.advertising
[1] = 0;
10349 switch (bp
->link_params
.num_phys
) {
10358 for (idx
= 0; idx
< cfg_size
; idx
++) {
10359 bp
->link_params
.req_duplex
[idx
] = DUPLEX_FULL
;
10360 link_config
= bp
->port
.link_config
[idx
];
10361 switch (link_config
& PORT_FEATURE_LINK_SPEED_MASK
) {
10362 case PORT_FEATURE_LINK_SPEED_AUTO
:
10363 if (bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
) {
10364 bp
->link_params
.req_line_speed
[idx
] =
10366 bp
->port
.advertising
[idx
] |=
10367 bp
->port
.supported
[idx
];
10368 if (bp
->link_params
.phy
[EXT_PHY1
].type
==
10369 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
)
10370 bp
->port
.advertising
[idx
] |=
10371 (SUPPORTED_100baseT_Half
|
10372 SUPPORTED_100baseT_Full
);
10374 /* force 10G, no AN */
10375 bp
->link_params
.req_line_speed
[idx
] =
10377 bp
->port
.advertising
[idx
] |=
10378 (ADVERTISED_10000baseT_Full
|
10384 case PORT_FEATURE_LINK_SPEED_10M_FULL
:
10385 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Full
) {
10386 bp
->link_params
.req_line_speed
[idx
] =
10388 bp
->port
.advertising
[idx
] |=
10389 (ADVERTISED_10baseT_Full
|
10392 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10394 bp
->link_params
.speed_cap_mask
[idx
]);
10399 case PORT_FEATURE_LINK_SPEED_10M_HALF
:
10400 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Half
) {
10401 bp
->link_params
.req_line_speed
[idx
] =
10403 bp
->link_params
.req_duplex
[idx
] =
10405 bp
->port
.advertising
[idx
] |=
10406 (ADVERTISED_10baseT_Half
|
10409 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10411 bp
->link_params
.speed_cap_mask
[idx
]);
10416 case PORT_FEATURE_LINK_SPEED_100M_FULL
:
10417 if (bp
->port
.supported
[idx
] &
10418 SUPPORTED_100baseT_Full
) {
10419 bp
->link_params
.req_line_speed
[idx
] =
10421 bp
->port
.advertising
[idx
] |=
10422 (ADVERTISED_100baseT_Full
|
10425 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10427 bp
->link_params
.speed_cap_mask
[idx
]);
10432 case PORT_FEATURE_LINK_SPEED_100M_HALF
:
10433 if (bp
->port
.supported
[idx
] &
10434 SUPPORTED_100baseT_Half
) {
10435 bp
->link_params
.req_line_speed
[idx
] =
10437 bp
->link_params
.req_duplex
[idx
] =
10439 bp
->port
.advertising
[idx
] |=
10440 (ADVERTISED_100baseT_Half
|
10443 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10445 bp
->link_params
.speed_cap_mask
[idx
]);
10450 case PORT_FEATURE_LINK_SPEED_1G
:
10451 if (bp
->port
.supported
[idx
] &
10452 SUPPORTED_1000baseT_Full
) {
10453 bp
->link_params
.req_line_speed
[idx
] =
10455 bp
->port
.advertising
[idx
] |=
10456 (ADVERTISED_1000baseT_Full
|
10459 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10461 bp
->link_params
.speed_cap_mask
[idx
]);
10466 case PORT_FEATURE_LINK_SPEED_2_5G
:
10467 if (bp
->port
.supported
[idx
] &
10468 SUPPORTED_2500baseX_Full
) {
10469 bp
->link_params
.req_line_speed
[idx
] =
10471 bp
->port
.advertising
[idx
] |=
10472 (ADVERTISED_2500baseX_Full
|
10475 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10477 bp
->link_params
.speed_cap_mask
[idx
]);
10482 case PORT_FEATURE_LINK_SPEED_10G_CX4
:
10483 if (bp
->port
.supported
[idx
] &
10484 SUPPORTED_10000baseT_Full
) {
10485 bp
->link_params
.req_line_speed
[idx
] =
10487 bp
->port
.advertising
[idx
] |=
10488 (ADVERTISED_10000baseT_Full
|
10491 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10493 bp
->link_params
.speed_cap_mask
[idx
]);
10497 case PORT_FEATURE_LINK_SPEED_20G
:
10498 bp
->link_params
.req_line_speed
[idx
] = SPEED_20000
;
10502 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10504 bp
->link_params
.req_line_speed
[idx
] =
10506 bp
->port
.advertising
[idx
] =
10507 bp
->port
.supported
[idx
];
10511 bp
->link_params
.req_flow_ctrl
[idx
] = (link_config
&
10512 PORT_FEATURE_FLOW_CONTROL_MASK
);
10513 if (bp
->link_params
.req_flow_ctrl
[idx
] ==
10514 BNX2X_FLOW_CTRL_AUTO
) {
10515 if (!(bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
))
10516 bp
->link_params
.req_flow_ctrl
[idx
] =
10517 BNX2X_FLOW_CTRL_NONE
;
10519 bnx2x_set_requested_fc(bp
);
10522 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10523 bp
->link_params
.req_line_speed
[idx
],
10524 bp
->link_params
.req_duplex
[idx
],
10525 bp
->link_params
.req_flow_ctrl
[idx
],
10526 bp
->port
.advertising
[idx
]);
10530 static void bnx2x_set_mac_buf(u8
*mac_buf
, u32 mac_lo
, u16 mac_hi
)
10532 mac_hi
= cpu_to_be16(mac_hi
);
10533 mac_lo
= cpu_to_be32(mac_lo
);
10534 memcpy(mac_buf
, &mac_hi
, sizeof(mac_hi
));
10535 memcpy(mac_buf
+ sizeof(mac_hi
), &mac_lo
, sizeof(mac_lo
));
10538 static void bnx2x_get_port_hwinfo(struct bnx2x
*bp
)
10540 int port
= BP_PORT(bp
);
10542 u32 ext_phy_type
, ext_phy_config
, eee_mode
;
10544 bp
->link_params
.bp
= bp
;
10545 bp
->link_params
.port
= port
;
10547 bp
->link_params
.lane_config
=
10548 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].lane_config
);
10550 bp
->link_params
.speed_cap_mask
[0] =
10552 dev_info
.port_hw_config
[port
].speed_capability_mask
);
10553 bp
->link_params
.speed_cap_mask
[1] =
10555 dev_info
.port_hw_config
[port
].speed_capability_mask2
);
10556 bp
->port
.link_config
[0] =
10557 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config
);
10559 bp
->port
.link_config
[1] =
10560 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config2
);
10562 bp
->link_params
.multi_phy_config
=
10563 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].multi_phy_config
);
10564 /* If the device is capable of WoL, set the default state according
10567 config
= SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].config
);
10568 bp
->wol
= (!(bp
->flags
& NO_WOL_FLAG
) &&
10569 (config
& PORT_FEATURE_WOL_ENABLED
));
10571 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10572 bp
->link_params
.lane_config
,
10573 bp
->link_params
.speed_cap_mask
[0],
10574 bp
->port
.link_config
[0]);
10576 bp
->link_params
.switch_cfg
= (bp
->port
.link_config
[0] &
10577 PORT_FEATURE_CONNECTED_SWITCH_MASK
);
10578 bnx2x_phy_probe(&bp
->link_params
);
10579 bnx2x_link_settings_supported(bp
, bp
->link_params
.switch_cfg
);
10581 bnx2x_link_settings_requested(bp
);
10584 * If connected directly, work with the internal PHY, otherwise, work
10585 * with the external PHY
10589 dev_info
.port_hw_config
[port
].external_phy_config
);
10590 ext_phy_type
= XGXS_EXT_PHY_TYPE(ext_phy_config
);
10591 if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)
10592 bp
->mdio
.prtad
= bp
->port
.phy_addr
;
10594 else if ((ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
) &&
10595 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
))
10597 XGXS_EXT_PHY_ADDR(ext_phy_config
);
10599 /* Configure link feature according to nvram value */
10600 eee_mode
= (((SHMEM_RD(bp
, dev_info
.
10601 port_feature_config
[port
].eee_power_mode
)) &
10602 PORT_FEAT_CFG_EEE_POWER_MODE_MASK
) >>
10603 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT
);
10604 if (eee_mode
!= PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED
) {
10605 bp
->link_params
.eee_mode
= EEE_MODE_ADV_LPI
|
10606 EEE_MODE_ENABLE_LPI
|
10607 EEE_MODE_OUTPUT_TIME
;
10609 bp
->link_params
.eee_mode
= 0;
10613 void bnx2x_get_iscsi_info(struct bnx2x
*bp
)
10615 u32 no_flags
= NO_ISCSI_FLAG
;
10616 int port
= BP_PORT(bp
);
10617 u32 max_iscsi_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
10618 drv_lic_key
[port
].max_iscsi_conn
);
10620 if (!CNIC_SUPPORT(bp
)) {
10621 bp
->flags
|= no_flags
;
10625 /* Get the number of maximum allowed iSCSI connections */
10626 bp
->cnic_eth_dev
.max_iscsi_conn
=
10627 (max_iscsi_conn
& BNX2X_MAX_ISCSI_INIT_CONN_MASK
) >>
10628 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT
;
10630 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10631 bp
->cnic_eth_dev
.max_iscsi_conn
);
10634 * If maximum allowed number of connections is zero -
10635 * disable the feature.
10637 if (!bp
->cnic_eth_dev
.max_iscsi_conn
)
10638 bp
->flags
|= no_flags
;
10642 static void bnx2x_get_ext_wwn_info(struct bnx2x
*bp
, int func
)
10645 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
10646 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_port_name_upper
);
10647 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
10648 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_port_name_lower
);
10651 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
10652 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_node_name_upper
);
10653 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
10654 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_node_name_lower
);
10656 static void bnx2x_get_fcoe_info(struct bnx2x
*bp
)
10658 int port
= BP_PORT(bp
);
10659 int func
= BP_ABS_FUNC(bp
);
10660 u32 max_fcoe_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
10661 drv_lic_key
[port
].max_fcoe_conn
);
10663 if (!CNIC_SUPPORT(bp
)) {
10664 bp
->flags
|= NO_FCOE_FLAG
;
10668 /* Get the number of maximum allowed FCoE connections */
10669 bp
->cnic_eth_dev
.max_fcoe_conn
=
10670 (max_fcoe_conn
& BNX2X_MAX_FCOE_INIT_CONN_MASK
) >>
10671 BNX2X_MAX_FCOE_INIT_CONN_SHIFT
;
10673 /* Read the WWN: */
10676 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
10678 dev_info
.port_hw_config
[port
].
10679 fcoe_wwn_port_name_upper
);
10680 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
10682 dev_info
.port_hw_config
[port
].
10683 fcoe_wwn_port_name_lower
);
10686 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
10688 dev_info
.port_hw_config
[port
].
10689 fcoe_wwn_node_name_upper
);
10690 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
10692 dev_info
.port_hw_config
[port
].
10693 fcoe_wwn_node_name_lower
);
10694 } else if (!IS_MF_SD(bp
)) {
10696 * Read the WWN info only if the FCoE feature is enabled for
10699 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp
) && !CHIP_IS_E1x(bp
))
10700 bnx2x_get_ext_wwn_info(bp
, func
);
10702 } else if (IS_MF_FCOE_SD(bp
) && !CHIP_IS_E1x(bp
)) {
10703 bnx2x_get_ext_wwn_info(bp
, func
);
10706 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp
->cnic_eth_dev
.max_fcoe_conn
);
10709 * If maximum allowed number of connections is zero -
10710 * disable the feature.
10712 if (!bp
->cnic_eth_dev
.max_fcoe_conn
)
10713 bp
->flags
|= NO_FCOE_FLAG
;
10716 static void bnx2x_get_cnic_info(struct bnx2x
*bp
)
10719 * iSCSI may be dynamically disabled but reading
10720 * info here we will decrease memory usage by driver
10721 * if the feature is disabled for good
10723 bnx2x_get_iscsi_info(bp
);
10724 bnx2x_get_fcoe_info(bp
);
10727 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x
*bp
)
10730 int func
= BP_ABS_FUNC(bp
);
10731 int port
= BP_PORT(bp
);
10732 u8
*iscsi_mac
= bp
->cnic_eth_dev
.iscsi_mac
;
10733 u8
*fip_mac
= bp
->fip_mac
;
10736 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10737 * FCoE MAC then the appropriate feature should be disabled.
10738 * In non SD mode features configuration comes from struct
10741 if (!IS_MF_SD(bp
) && !CHIP_IS_E1x(bp
)) {
10742 u32 cfg
= MF_CFG_RD(bp
, func_ext_config
[func
].func_cfg
);
10743 if (cfg
& MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD
) {
10744 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
10745 iscsi_mac_addr_upper
);
10746 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
10747 iscsi_mac_addr_lower
);
10748 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
10750 ("Read iSCSI MAC: %pM\n", iscsi_mac
);
10752 bp
->flags
|= NO_ISCSI_OOO_FLAG
| NO_ISCSI_FLAG
;
10755 if (cfg
& MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
) {
10756 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
10757 fcoe_mac_addr_upper
);
10758 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
10759 fcoe_mac_addr_lower
);
10760 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
10762 ("Read FCoE L2 MAC: %pM\n", fip_mac
);
10764 bp
->flags
|= NO_FCOE_FLAG
;
10767 bp
->mf_ext_config
= cfg
;
10769 } else { /* SD MODE */
10770 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp
)) {
10771 /* use primary mac as iscsi mac */
10772 memcpy(iscsi_mac
, bp
->dev
->dev_addr
, ETH_ALEN
);
10774 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10776 ("Read iSCSI MAC: %pM\n", iscsi_mac
);
10777 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp
)) {
10778 /* use primary mac as fip mac */
10779 memcpy(fip_mac
, bp
->dev
->dev_addr
, ETH_ALEN
);
10780 BNX2X_DEV_INFO("SD FCoE MODE\n");
10782 ("Read FIP MAC: %pM\n", fip_mac
);
10786 if (IS_MF_STORAGE_SD(bp
))
10787 /* Zero primary MAC configuration */
10788 memset(bp
->dev
->dev_addr
, 0, ETH_ALEN
);
10790 if (IS_MF_FCOE_AFEX(bp
))
10791 /* use FIP MAC as primary MAC */
10792 memcpy(bp
->dev
->dev_addr
, fip_mac
, ETH_ALEN
);
10795 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
10797 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
10799 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
10801 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
10802 fcoe_fip_mac_upper
);
10803 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
10804 fcoe_fip_mac_lower
);
10805 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
10808 /* Disable iSCSI OOO if MAC configuration is invalid. */
10809 if (!is_valid_ether_addr(iscsi_mac
)) {
10810 bp
->flags
|= NO_ISCSI_OOO_FLAG
| NO_ISCSI_FLAG
;
10811 memset(iscsi_mac
, 0, ETH_ALEN
);
10814 /* Disable FCoE if MAC configuration is invalid. */
10815 if (!is_valid_ether_addr(fip_mac
)) {
10816 bp
->flags
|= NO_FCOE_FLAG
;
10817 memset(bp
->fip_mac
, 0, ETH_ALEN
);
10821 static void bnx2x_get_mac_hwinfo(struct bnx2x
*bp
)
10824 int func
= BP_ABS_FUNC(bp
);
10825 int port
= BP_PORT(bp
);
10827 /* Zero primary MAC configuration */
10828 memset(bp
->dev
->dev_addr
, 0, ETH_ALEN
);
10830 if (BP_NOMCP(bp
)) {
10831 BNX2X_ERROR("warning: random MAC workaround active\n");
10832 eth_hw_addr_random(bp
->dev
);
10833 } else if (IS_MF(bp
)) {
10834 val2
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_upper
);
10835 val
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_lower
);
10836 if ((val2
!= FUNC_MF_CFG_UPPERMAC_DEFAULT
) &&
10837 (val
!= FUNC_MF_CFG_LOWERMAC_DEFAULT
))
10838 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
10840 if (CNIC_SUPPORT(bp
))
10841 bnx2x_get_cnic_mac_hwinfo(bp
);
10843 /* in SF read MACs from port configuration */
10844 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_upper
);
10845 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_lower
);
10846 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
10848 if (CNIC_SUPPORT(bp
))
10849 bnx2x_get_cnic_mac_hwinfo(bp
);
10852 memcpy(bp
->link_params
.mac_addr
, bp
->dev
->dev_addr
, ETH_ALEN
);
10854 if (!bnx2x_is_valid_ether_addr(bp
, bp
->dev
->dev_addr
))
10855 dev_err(&bp
->pdev
->dev
,
10856 "bad Ethernet MAC address configuration: %pM\n"
10857 "change it manually before bringing up the appropriate network interface\n",
10858 bp
->dev
->dev_addr
);
10861 static bool bnx2x_get_dropless_info(struct bnx2x
*bp
)
10866 if (IS_MF(bp
) && !CHIP_IS_E1x(bp
)) {
10867 /* Take function: tmp = func */
10868 tmp
= BP_ABS_FUNC(bp
);
10869 cfg
= MF_CFG_RD(bp
, func_ext_config
[tmp
].func_cfg
);
10870 cfg
= !!(cfg
& MACP_FUNC_CFG_PAUSE_ON_HOST_RING
);
10872 /* Take port: tmp = port */
10875 dev_info
.port_hw_config
[tmp
].generic_features
);
10876 cfg
= !!(cfg
& PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED
);
10881 static int bnx2x_get_hwinfo(struct bnx2x
*bp
)
10883 int /*abs*/func
= BP_ABS_FUNC(bp
);
10888 bnx2x_get_common_hwinfo(bp
);
10891 * initialize IGU parameters
10893 if (CHIP_IS_E1x(bp
)) {
10894 bp
->common
.int_block
= INT_BLOCK_HC
;
10896 bp
->igu_dsb_id
= DEF_SB_IGU_ID
;
10897 bp
->igu_base_sb
= 0;
10899 bp
->common
.int_block
= INT_BLOCK_IGU
;
10901 /* do not allow device reset during IGU info preocessing */
10902 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
10904 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
10906 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
10909 BNX2X_DEV_INFO("FORCING Normal Mode\n");
10911 val
&= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
);
10912 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
, val
);
10913 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x7f);
10915 while (tout
&& REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
10917 usleep_range(1000, 1000);
10920 if (REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
10921 dev_err(&bp
->pdev
->dev
,
10922 "FORCING Normal Mode failed!!!\n");
10923 bnx2x_release_hw_lock(bp
,
10924 HW_LOCK_RESOURCE_RESET
);
10929 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
10930 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10931 bp
->common
.int_block
|= INT_BLOCK_MODE_BW_COMP
;
10933 BNX2X_DEV_INFO("IGU Normal Mode\n");
10935 rc
= bnx2x_get_igu_cam_info(bp
);
10936 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
10942 * set base FW non-default (fast path) status block id, this value is
10943 * used to initialize the fw_sb_id saved on the fp/queue structure to
10944 * determine the id used by the FW.
10946 if (CHIP_IS_E1x(bp
))
10947 bp
->base_fw_ndsb
= BP_PORT(bp
) * FP_SB_MAX_E1x
+ BP_L_ID(bp
);
10949 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10950 * the same queue are indicated on the same IGU SB). So we prefer
10951 * FW and IGU SBs to be the same value.
10953 bp
->base_fw_ndsb
= bp
->igu_base_sb
;
10955 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
10956 "base_fw_ndsb %d\n", bp
->igu_dsb_id
, bp
->igu_base_sb
,
10957 bp
->igu_sb_cnt
, bp
->base_fw_ndsb
);
10960 * Initialize MF configuration
10967 if (!CHIP_IS_E1(bp
) && !BP_NOMCP(bp
)) {
10968 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10969 bp
->common
.shmem2_base
, SHMEM2_RD(bp
, size
),
10970 (u32
)offsetof(struct shmem2_region
, mf_cfg_addr
));
10972 if (SHMEM2_HAS(bp
, mf_cfg_addr
))
10973 bp
->common
.mf_cfg_base
= SHMEM2_RD(bp
, mf_cfg_addr
);
10975 bp
->common
.mf_cfg_base
= bp
->common
.shmem_base
+
10976 offsetof(struct shmem_region
, func_mb
) +
10977 E1H_FUNC_MAX
* sizeof(struct drv_func_mb
);
10979 * get mf configuration:
10980 * 1. existence of MF configuration
10981 * 2. MAC address must be legal (check only upper bytes)
10982 * for Switch-Independent mode;
10983 * OVLAN must be legal for Switch-Dependent mode
10984 * 3. SF_MODE configures specific MF mode
10986 if (bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
10987 /* get mf configuration */
10989 dev_info
.shared_feature_config
.config
);
10990 val
&= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK
;
10993 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT
:
10994 val
= MF_CFG_RD(bp
, func_mf_config
[func
].
10996 /* check for legal mac (upper bytes)*/
10997 if (val
!= 0xffff) {
10998 bp
->mf_mode
= MULTI_FUNCTION_SI
;
10999 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
11000 func_mf_config
[func
].config
);
11002 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11004 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE
:
11005 if ((!CHIP_IS_E1x(bp
)) &&
11006 (MF_CFG_RD(bp
, func_mf_config
[func
].
11007 mac_upper
) != 0xffff) &&
11009 afex_driver_support
))) {
11010 bp
->mf_mode
= MULTI_FUNCTION_AFEX
;
11011 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
11012 func_mf_config
[func
].config
);
11014 BNX2X_DEV_INFO("can not configure afex mode\n");
11017 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED
:
11018 /* get OV configuration */
11019 val
= MF_CFG_RD(bp
,
11020 func_mf_config
[FUNC_0
].e1hov_tag
);
11021 val
&= FUNC_MF_CFG_E1HOV_TAG_MASK
;
11023 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
11024 bp
->mf_mode
= MULTI_FUNCTION_SD
;
11025 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
11026 func_mf_config
[func
].config
);
11028 BNX2X_DEV_INFO("illegal OV for SD\n");
11031 /* Unknown configuration: reset mf_config */
11032 bp
->mf_config
[vn
] = 0;
11033 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val
);
11037 BNX2X_DEV_INFO("%s function mode\n",
11038 IS_MF(bp
) ? "multi" : "single");
11040 switch (bp
->mf_mode
) {
11041 case MULTI_FUNCTION_SD
:
11042 val
= MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
11043 FUNC_MF_CFG_E1HOV_TAG_MASK
;
11044 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
11046 bp
->path_has_ovlan
= true;
11048 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11049 func
, bp
->mf_ov
, bp
->mf_ov
);
11051 dev_err(&bp
->pdev
->dev
,
11052 "No valid MF OV for func %d, aborting\n",
11057 case MULTI_FUNCTION_AFEX
:
11058 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func
);
11060 case MULTI_FUNCTION_SI
:
11061 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11066 dev_err(&bp
->pdev
->dev
,
11067 "VN %d is in a single function mode, aborting\n",
11074 /* check if other port on the path needs ovlan:
11075 * Since MF configuration is shared between ports
11076 * Possible mixed modes are only
11077 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11079 if (CHIP_MODE_IS_4_PORT(bp
) &&
11080 !bp
->path_has_ovlan
&&
11082 bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
11083 u8 other_port
= !BP_PORT(bp
);
11084 u8 other_func
= BP_PATH(bp
) + 2*other_port
;
11085 val
= MF_CFG_RD(bp
,
11086 func_mf_config
[other_func
].e1hov_tag
);
11087 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
)
11088 bp
->path_has_ovlan
= true;
11092 /* adjust igu_sb_cnt to MF for E1x */
11093 if (CHIP_IS_E1x(bp
) && IS_MF(bp
))
11094 bp
->igu_sb_cnt
/= E1HVN_MAX
;
11097 bnx2x_get_port_hwinfo(bp
);
11099 /* Get MAC addresses */
11100 bnx2x_get_mac_hwinfo(bp
);
11102 bnx2x_get_cnic_info(bp
);
11107 static void bnx2x_read_fwinfo(struct bnx2x
*bp
)
11109 int cnt
, i
, block_end
, rodi
;
11110 char vpd_start
[BNX2X_VPD_LEN
+1];
11111 char str_id_reg
[VENDOR_ID_LEN
+1];
11112 char str_id_cap
[VENDOR_ID_LEN
+1];
11114 char *vpd_extended_data
= NULL
;
11117 cnt
= pci_read_vpd(bp
->pdev
, 0, BNX2X_VPD_LEN
, vpd_start
);
11118 memset(bp
->fw_ver
, 0, sizeof(bp
->fw_ver
));
11120 if (cnt
< BNX2X_VPD_LEN
)
11121 goto out_not_found
;
11123 /* VPD RO tag should be first tag after identifier string, hence
11124 * we should be able to find it in first BNX2X_VPD_LEN chars
11126 i
= pci_vpd_find_tag(vpd_start
, 0, BNX2X_VPD_LEN
,
11127 PCI_VPD_LRDT_RO_DATA
);
11129 goto out_not_found
;
11131 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+
11132 pci_vpd_lrdt_size(&vpd_start
[i
]);
11134 i
+= PCI_VPD_LRDT_TAG_SIZE
;
11136 if (block_end
> BNX2X_VPD_LEN
) {
11137 vpd_extended_data
= kmalloc(block_end
, GFP_KERNEL
);
11138 if (vpd_extended_data
== NULL
)
11139 goto out_not_found
;
11141 /* read rest of vpd image into vpd_extended_data */
11142 memcpy(vpd_extended_data
, vpd_start
, BNX2X_VPD_LEN
);
11143 cnt
= pci_read_vpd(bp
->pdev
, BNX2X_VPD_LEN
,
11144 block_end
- BNX2X_VPD_LEN
,
11145 vpd_extended_data
+ BNX2X_VPD_LEN
);
11146 if (cnt
< (block_end
- BNX2X_VPD_LEN
))
11147 goto out_not_found
;
11148 vpd_data
= vpd_extended_data
;
11150 vpd_data
= vpd_start
;
11152 /* now vpd_data holds full vpd content in both cases */
11154 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
11155 PCI_VPD_RO_KEYWORD_MFR_ID
);
11157 goto out_not_found
;
11159 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
11161 if (len
!= VENDOR_ID_LEN
)
11162 goto out_not_found
;
11164 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
11166 /* vendor specific info */
11167 snprintf(str_id_reg
, VENDOR_ID_LEN
+ 1, "%04x", PCI_VENDOR_ID_DELL
);
11168 snprintf(str_id_cap
, VENDOR_ID_LEN
+ 1, "%04X", PCI_VENDOR_ID_DELL
);
11169 if (!strncmp(str_id_reg
, &vpd_data
[rodi
], VENDOR_ID_LEN
) ||
11170 !strncmp(str_id_cap
, &vpd_data
[rodi
], VENDOR_ID_LEN
)) {
11172 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
11173 PCI_VPD_RO_KEYWORD_VENDOR0
);
11175 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
11177 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
11179 if (len
< 32 && (len
+ rodi
) <= BNX2X_VPD_LEN
) {
11180 memcpy(bp
->fw_ver
, &vpd_data
[rodi
], len
);
11181 bp
->fw_ver
[len
] = ' ';
11184 kfree(vpd_extended_data
);
11188 kfree(vpd_extended_data
);
11192 static void bnx2x_set_modes_bitmap(struct bnx2x
*bp
)
11196 if (CHIP_REV_IS_FPGA(bp
))
11197 SET_FLAGS(flags
, MODE_FPGA
);
11198 else if (CHIP_REV_IS_EMUL(bp
))
11199 SET_FLAGS(flags
, MODE_EMUL
);
11201 SET_FLAGS(flags
, MODE_ASIC
);
11203 if (CHIP_MODE_IS_4_PORT(bp
))
11204 SET_FLAGS(flags
, MODE_PORT4
);
11206 SET_FLAGS(flags
, MODE_PORT2
);
11208 if (CHIP_IS_E2(bp
))
11209 SET_FLAGS(flags
, MODE_E2
);
11210 else if (CHIP_IS_E3(bp
)) {
11211 SET_FLAGS(flags
, MODE_E3
);
11212 if (CHIP_REV(bp
) == CHIP_REV_Ax
)
11213 SET_FLAGS(flags
, MODE_E3_A0
);
11214 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11215 SET_FLAGS(flags
, MODE_E3_B0
| MODE_COS3
);
11219 SET_FLAGS(flags
, MODE_MF
);
11220 switch (bp
->mf_mode
) {
11221 case MULTI_FUNCTION_SD
:
11222 SET_FLAGS(flags
, MODE_MF_SD
);
11224 case MULTI_FUNCTION_SI
:
11225 SET_FLAGS(flags
, MODE_MF_SI
);
11227 case MULTI_FUNCTION_AFEX
:
11228 SET_FLAGS(flags
, MODE_MF_AFEX
);
11232 SET_FLAGS(flags
, MODE_SF
);
11234 #if defined(__LITTLE_ENDIAN)
11235 SET_FLAGS(flags
, MODE_LITTLE_ENDIAN
);
11236 #else /*(__BIG_ENDIAN)*/
11237 SET_FLAGS(flags
, MODE_BIG_ENDIAN
);
11239 INIT_MODE_FLAGS(bp
) = flags
;
11242 static int bnx2x_init_bp(struct bnx2x
*bp
)
11247 mutex_init(&bp
->port
.phy_mutex
);
11248 mutex_init(&bp
->fw_mb_mutex
);
11249 spin_lock_init(&bp
->stats_lock
);
11252 INIT_DELAYED_WORK(&bp
->sp_task
, bnx2x_sp_task
);
11253 INIT_DELAYED_WORK(&bp
->sp_rtnl_task
, bnx2x_sp_rtnl_task
);
11254 INIT_DELAYED_WORK(&bp
->period_task
, bnx2x_period_task
);
11256 rc
= bnx2x_get_hwinfo(bp
);
11260 random_ether_addr(bp
->dev
->dev_addr
);
11263 bnx2x_set_modes_bitmap(bp
);
11265 rc
= bnx2x_alloc_mem_bp(bp
);
11269 bnx2x_read_fwinfo(bp
);
11271 func
= BP_FUNC(bp
);
11273 /* need to reset chip if undi was active */
11274 if (IS_PF(bp
) && !BP_NOMCP(bp
)) {
11277 SHMEM_RD(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_mb_header
) &
11278 DRV_MSG_SEQ_NUMBER_MASK
;
11279 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp
->fw_seq
);
11281 bnx2x_prev_unload(bp
);
11285 if (CHIP_REV_IS_FPGA(bp
))
11286 dev_err(&bp
->pdev
->dev
, "FPGA detected\n");
11288 if (BP_NOMCP(bp
) && (func
== 0))
11289 dev_err(&bp
->pdev
->dev
, "MCP disabled, must load devices in order!\n");
11291 bp
->disable_tpa
= disable_tpa
;
11292 bp
->disable_tpa
|= IS_MF_STORAGE_SD(bp
) || IS_MF_FCOE_AFEX(bp
);
11294 /* Set TPA flags */
11295 if (bp
->disable_tpa
) {
11296 bp
->flags
&= ~(TPA_ENABLE_FLAG
| GRO_ENABLE_FLAG
);
11297 bp
->dev
->features
&= ~NETIF_F_LRO
;
11299 bp
->flags
|= (TPA_ENABLE_FLAG
| GRO_ENABLE_FLAG
);
11300 bp
->dev
->features
|= NETIF_F_LRO
;
11303 if (CHIP_IS_E1(bp
))
11304 bp
->dropless_fc
= 0;
11306 bp
->dropless_fc
= dropless_fc
| bnx2x_get_dropless_info(bp
);
11310 bp
->tx_ring_size
= IS_MF_FCOE_AFEX(bp
) ? 0 : MAX_TX_AVAIL
;
11312 bp
->rx_ring_size
= MAX_RX_AVAIL
;
11314 /* make sure that the numbers are in the right granularity */
11315 bp
->tx_ticks
= (50 / BNX2X_BTR
) * BNX2X_BTR
;
11316 bp
->rx_ticks
= (25 / BNX2X_BTR
) * BNX2X_BTR
;
11318 bp
->current_interval
= CHIP_REV_IS_SLOW(bp
) ? 5*HZ
: HZ
;
11320 init_timer(&bp
->timer
);
11321 bp
->timer
.expires
= jiffies
+ bp
->current_interval
;
11322 bp
->timer
.data
= (unsigned long) bp
;
11323 bp
->timer
.function
= bnx2x_timer
;
11325 if (SHMEM2_HAS(bp
, dcbx_lldp_params_offset
) &&
11326 SHMEM2_HAS(bp
, dcbx_lldp_dcbx_stat_offset
) &&
11327 SHMEM2_RD(bp
, dcbx_lldp_params_offset
) &&
11328 SHMEM2_RD(bp
, dcbx_lldp_dcbx_stat_offset
)) {
11329 bnx2x_dcbx_set_state(bp
, true, BNX2X_DCBX_ENABLED_ON_NEG_ON
);
11330 bnx2x_dcbx_init_params(bp
);
11332 bnx2x_dcbx_set_state(bp
, false, BNX2X_DCBX_ENABLED_OFF
);
11335 if (CHIP_IS_E1x(bp
))
11336 bp
->cnic_base_cl_id
= FP_SB_MAX_E1x
;
11338 bp
->cnic_base_cl_id
= FP_SB_MAX_E2
;
11340 /* multiple tx priority */
11343 else if (CHIP_IS_E1x(bp
))
11344 bp
->max_cos
= BNX2X_MULTI_TX_COS_E1X
;
11345 else if (CHIP_IS_E2(bp
) || CHIP_IS_E3A0(bp
))
11346 bp
->max_cos
= BNX2X_MULTI_TX_COS_E2_E3A0
;
11347 else if (CHIP_IS_E3B0(bp
))
11348 bp
->max_cos
= BNX2X_MULTI_TX_COS_E3B0
;
11350 BNX2X_ERR("unknown chip %x revision %x\n",
11351 CHIP_NUM(bp
), CHIP_REV(bp
));
11352 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp
->max_cos
);
11354 /* We need at least one default status block for slow-path events,
11355 * second status block for the L2 queue, and a third status block for
11356 * CNIC if supproted.
11358 if (CNIC_SUPPORT(bp
))
11359 bp
->min_msix_vec_cnt
= 3;
11361 bp
->min_msix_vec_cnt
= 2;
11362 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp
->min_msix_vec_cnt
);
11368 /****************************************************************************
11369 * General service functions
11370 ****************************************************************************/
11373 * net_device service functions
11376 static int bnx2x_open_epilog(struct bnx2x
*bp
)
11378 /* Enable sriov via delayed work. This must be done via delayed work
11379 * because it causes the probe of the vf devices to be run, which invoke
11380 * register_netdevice which must have rtnl lock taken. As we are holding
11381 * the lock right now, that could only work if the probe would not take
11382 * the lock. However, as the probe of the vf may be called from other
11383 * contexts as well (such as passthrough to vm failes) it can't assume
11384 * the lock is being held for it. Using delayed work here allows the
11385 * probe code to simply take the lock (i.e. wait for it to be released
11386 * if it is being held).
11388 smp_mb__before_clear_bit();
11389 set_bit(BNX2X_SP_RTNL_ENABLE_SRIOV
, &bp
->sp_rtnl_state
);
11390 smp_mb__after_clear_bit();
11391 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
11396 /* called with rtnl_lock */
11397 static int bnx2x_open(struct net_device
*dev
)
11399 struct bnx2x
*bp
= netdev_priv(dev
);
11400 bool global
= false;
11401 int other_engine
= BP_PATH(bp
) ? 0 : 1;
11402 bool other_load_status
, load_status
;
11405 bp
->stats_init
= true;
11407 netif_carrier_off(dev
);
11409 bnx2x_set_power_state(bp
, PCI_D0
);
11411 /* If parity had happen during the unload, then attentions
11412 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11413 * want the first function loaded on the current engine to
11414 * complete the recovery.
11415 * Parity recovery is only relevant for PF driver.
11418 other_load_status
= bnx2x_get_load_status(bp
, other_engine
);
11419 load_status
= bnx2x_get_load_status(bp
, BP_PATH(bp
));
11420 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
)) ||
11421 bnx2x_chk_parity_attn(bp
, &global
, true)) {
11423 /* If there are attentions and they are in a
11424 * global blocks, set the GLOBAL_RESET bit
11425 * regardless whether it will be this function
11426 * that will complete the recovery or not.
11429 bnx2x_set_reset_global(bp
);
11431 /* Only the first function on the current
11432 * engine should try to recover in open. In case
11433 * of attentions in global blocks only the first
11434 * in the chip should try to recover.
11436 if ((!load_status
&&
11437 (!global
|| !other_load_status
)) &&
11438 bnx2x_trylock_leader_lock(bp
) &&
11439 !bnx2x_leader_reset(bp
)) {
11440 netdev_info(bp
->dev
,
11441 "Recovered in open\n");
11445 /* recovery has failed... */
11446 bnx2x_set_power_state(bp
, PCI_D3hot
);
11447 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
11449 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11450 "If you still see this message after a few retries then power cycle is required.\n");
11457 bp
->recovery_state
= BNX2X_RECOVERY_DONE
;
11458 rc
= bnx2x_nic_load(bp
, LOAD_OPEN
);
11461 return bnx2x_open_epilog(bp
);
11464 /* called with rtnl_lock */
11465 static int bnx2x_close(struct net_device
*dev
)
11467 struct bnx2x
*bp
= netdev_priv(dev
);
11469 /* Unload the driver, release IRQs */
11470 bnx2x_nic_unload(bp
, UNLOAD_CLOSE
, false);
11473 bnx2x_set_power_state(bp
, PCI_D3hot
);
11478 static int bnx2x_init_mcast_macs_list(struct bnx2x
*bp
,
11479 struct bnx2x_mcast_ramrod_params
*p
)
11481 int mc_count
= netdev_mc_count(bp
->dev
);
11482 struct bnx2x_mcast_list_elem
*mc_mac
=
11483 kzalloc(sizeof(*mc_mac
) * mc_count
, GFP_ATOMIC
);
11484 struct netdev_hw_addr
*ha
;
11489 INIT_LIST_HEAD(&p
->mcast_list
);
11491 netdev_for_each_mc_addr(ha
, bp
->dev
) {
11492 mc_mac
->mac
= bnx2x_mc_addr(ha
);
11493 list_add_tail(&mc_mac
->link
, &p
->mcast_list
);
11497 p
->mcast_list_len
= mc_count
;
11502 static void bnx2x_free_mcast_macs_list(
11503 struct bnx2x_mcast_ramrod_params
*p
)
11505 struct bnx2x_mcast_list_elem
*mc_mac
=
11506 list_first_entry(&p
->mcast_list
, struct bnx2x_mcast_list_elem
,
11514 * bnx2x_set_uc_list - configure a new unicast MACs list.
11516 * @bp: driver handle
11518 * We will use zero (0) as a MAC type for these MACs.
11520 static int bnx2x_set_uc_list(struct bnx2x
*bp
)
11523 struct net_device
*dev
= bp
->dev
;
11524 struct netdev_hw_addr
*ha
;
11525 struct bnx2x_vlan_mac_obj
*mac_obj
= &bp
->sp_objs
->mac_obj
;
11526 unsigned long ramrod_flags
= 0;
11528 /* First schedule a cleanup up of old configuration */
11529 rc
= bnx2x_del_all_macs(bp
, mac_obj
, BNX2X_UC_LIST_MAC
, false);
11531 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc
);
11535 netdev_for_each_uc_addr(ha
, dev
) {
11536 rc
= bnx2x_set_mac_one(bp
, bnx2x_uc_addr(ha
), mac_obj
, true,
11537 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
11538 if (rc
== -EEXIST
) {
11540 "Failed to schedule ADD operations: %d\n", rc
);
11541 /* do not treat adding same MAC as error */
11544 } else if (rc
< 0) {
11546 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11552 /* Execute the pending commands */
11553 __set_bit(RAMROD_CONT
, &ramrod_flags
);
11554 return bnx2x_set_mac_one(bp
, NULL
, mac_obj
, false /* don't care */,
11555 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
11558 static int bnx2x_set_mc_list(struct bnx2x
*bp
)
11560 struct net_device
*dev
= bp
->dev
;
11561 struct bnx2x_mcast_ramrod_params rparam
= {NULL
};
11564 rparam
.mcast_obj
= &bp
->mcast_obj
;
11566 /* first, clear all configured multicast MACs */
11567 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
11569 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc
);
11573 /* then, configure a new MACs list */
11574 if (netdev_mc_count(dev
)) {
11575 rc
= bnx2x_init_mcast_macs_list(bp
, &rparam
);
11577 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11582 /* Now add the new MACs */
11583 rc
= bnx2x_config_mcast(bp
, &rparam
,
11584 BNX2X_MCAST_CMD_ADD
);
11586 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11589 bnx2x_free_mcast_macs_list(&rparam
);
11596 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11597 void bnx2x_set_rx_mode(struct net_device
*dev
)
11599 struct bnx2x
*bp
= netdev_priv(dev
);
11600 u32 rx_mode
= BNX2X_RX_MODE_NORMAL
;
11602 if (bp
->state
!= BNX2X_STATE_OPEN
) {
11603 DP(NETIF_MSG_IFUP
, "state is %x, returning\n", bp
->state
);
11607 DP(NETIF_MSG_IFUP
, "dev->flags = %x\n", bp
->dev
->flags
);
11609 if (dev
->flags
& IFF_PROMISC
)
11610 rx_mode
= BNX2X_RX_MODE_PROMISC
;
11611 else if ((dev
->flags
& IFF_ALLMULTI
) ||
11612 ((netdev_mc_count(dev
) > BNX2X_MAX_MULTICAST
) &&
11614 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
11617 /* some multicasts */
11618 if (bnx2x_set_mc_list(bp
) < 0)
11619 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
11621 if (bnx2x_set_uc_list(bp
) < 0)
11622 rx_mode
= BNX2X_RX_MODE_PROMISC
;
11624 /* configuring mcast to a vf involves sleeping (when we
11625 * wait for the pf's response). Since this function is
11626 * called from non sleepable context we must schedule
11627 * a work item for this purpose
11629 smp_mb__before_clear_bit();
11630 set_bit(BNX2X_SP_RTNL_VFPF_MCAST
,
11631 &bp
->sp_rtnl_state
);
11632 smp_mb__after_clear_bit();
11633 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
11637 bp
->rx_mode
= rx_mode
;
11638 /* handle ISCSI SD mode */
11639 if (IS_MF_ISCSI_SD(bp
))
11640 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
11642 /* Schedule the rx_mode command */
11643 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
)) {
11644 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
11649 bnx2x_set_storm_rx_mode(bp
);
11651 /* configuring rx mode to storms in a vf involves sleeping (when
11652 * we wait for the pf's response). Since this function is
11653 * called from non sleepable context we must schedule
11654 * a work item for this purpose
11656 smp_mb__before_clear_bit();
11657 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE
,
11658 &bp
->sp_rtnl_state
);
11659 smp_mb__after_clear_bit();
11660 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
11664 /* called with rtnl_lock */
11665 static int bnx2x_mdio_read(struct net_device
*netdev
, int prtad
,
11666 int devad
, u16 addr
)
11668 struct bnx2x
*bp
= netdev_priv(netdev
);
11672 DP(NETIF_MSG_LINK
, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11673 prtad
, devad
, addr
);
11675 /* The HW expects different devad if CL22 is used */
11676 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
11678 bnx2x_acquire_phy_lock(bp
);
11679 rc
= bnx2x_phy_read(&bp
->link_params
, prtad
, devad
, addr
, &value
);
11680 bnx2x_release_phy_lock(bp
);
11681 DP(NETIF_MSG_LINK
, "mdio_read_val 0x%x rc = 0x%x\n", value
, rc
);
11688 /* called with rtnl_lock */
11689 static int bnx2x_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
11690 u16 addr
, u16 value
)
11692 struct bnx2x
*bp
= netdev_priv(netdev
);
11696 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11697 prtad
, devad
, addr
, value
);
11699 /* The HW expects different devad if CL22 is used */
11700 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
11702 bnx2x_acquire_phy_lock(bp
);
11703 rc
= bnx2x_phy_write(&bp
->link_params
, prtad
, devad
, addr
, value
);
11704 bnx2x_release_phy_lock(bp
);
11708 /* called with rtnl_lock */
11709 static int bnx2x_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
11711 struct bnx2x
*bp
= netdev_priv(dev
);
11712 struct mii_ioctl_data
*mdio
= if_mii(ifr
);
11714 DP(NETIF_MSG_LINK
, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11715 mdio
->phy_id
, mdio
->reg_num
, mdio
->val_in
);
11717 if (!netif_running(dev
))
11720 return mdio_mii_ioctl(&bp
->mdio
, mdio
, cmd
);
11723 #ifdef CONFIG_NET_POLL_CONTROLLER
11724 static void poll_bnx2x(struct net_device
*dev
)
11726 struct bnx2x
*bp
= netdev_priv(dev
);
11729 for_each_eth_queue(bp
, i
) {
11730 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
11731 napi_schedule(&bnx2x_fp(bp
, fp
->index
, napi
));
11736 static int bnx2x_validate_addr(struct net_device
*dev
)
11738 struct bnx2x
*bp
= netdev_priv(dev
);
11740 if (!bnx2x_is_valid_ether_addr(bp
, dev
->dev_addr
)) {
11741 BNX2X_ERR("Non-valid Ethernet address\n");
11742 return -EADDRNOTAVAIL
;
11747 static const struct net_device_ops bnx2x_netdev_ops
= {
11748 .ndo_open
= bnx2x_open
,
11749 .ndo_stop
= bnx2x_close
,
11750 .ndo_start_xmit
= bnx2x_start_xmit
,
11751 .ndo_select_queue
= bnx2x_select_queue
,
11752 .ndo_set_rx_mode
= bnx2x_set_rx_mode
,
11753 .ndo_set_mac_address
= bnx2x_change_mac_addr
,
11754 .ndo_validate_addr
= bnx2x_validate_addr
,
11755 .ndo_do_ioctl
= bnx2x_ioctl
,
11756 .ndo_change_mtu
= bnx2x_change_mtu
,
11757 .ndo_fix_features
= bnx2x_fix_features
,
11758 .ndo_set_features
= bnx2x_set_features
,
11759 .ndo_tx_timeout
= bnx2x_tx_timeout
,
11760 #ifdef CONFIG_NET_POLL_CONTROLLER
11761 .ndo_poll_controller
= poll_bnx2x
,
11763 .ndo_setup_tc
= bnx2x_setup_tc
,
11764 #ifdef CONFIG_BNX2X_SRIOV
11765 .ndo_set_vf_mac
= bnx2x_set_vf_mac
,
11767 #ifdef NETDEV_FCOE_WWNN
11768 .ndo_fcoe_get_wwn
= bnx2x_fcoe_get_wwn
,
11772 static int bnx2x_set_coherency_mask(struct bnx2x
*bp
)
11774 struct device
*dev
= &bp
->pdev
->dev
;
11776 if (dma_set_mask(dev
, DMA_BIT_MASK(64)) == 0) {
11777 bp
->flags
|= USING_DAC_FLAG
;
11778 if (dma_set_coherent_mask(dev
, DMA_BIT_MASK(64)) != 0) {
11779 dev_err(dev
, "dma_set_coherent_mask failed, aborting\n");
11782 } else if (dma_set_mask(dev
, DMA_BIT_MASK(32)) != 0) {
11783 dev_err(dev
, "System does not support DMA, aborting\n");
11790 static int bnx2x_init_dev(struct bnx2x
*bp
, struct pci_dev
*pdev
,
11791 struct net_device
*dev
, unsigned long board_type
)
11795 bool chip_is_e1x
= (board_type
== BCM57710
||
11796 board_type
== BCM57711
||
11797 board_type
== BCM57711E
);
11799 SET_NETDEV_DEV(dev
, &pdev
->dev
);
11804 rc
= pci_enable_device(pdev
);
11806 dev_err(&bp
->pdev
->dev
,
11807 "Cannot enable PCI device, aborting\n");
11811 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
11812 dev_err(&bp
->pdev
->dev
,
11813 "Cannot find PCI device base address, aborting\n");
11815 goto err_out_disable
;
11818 if (IS_PF(bp
) && !(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
11819 dev_err(&bp
->pdev
->dev
, "Cannot find second PCI device base address, aborting\n");
11821 goto err_out_disable
;
11824 pci_read_config_dword(pdev
, PCICFG_REVISION_ID_OFFSET
, &pci_cfg_dword
);
11825 if ((pci_cfg_dword
& PCICFG_REVESION_ID_MASK
) ==
11826 PCICFG_REVESION_ID_ERROR_VAL
) {
11827 pr_err("PCI device error, probably due to fan failure, aborting\n");
11829 goto err_out_disable
;
11832 if (atomic_read(&pdev
->enable_cnt
) == 1) {
11833 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
11835 dev_err(&bp
->pdev
->dev
,
11836 "Cannot obtain PCI resources, aborting\n");
11837 goto err_out_disable
;
11840 pci_set_master(pdev
);
11841 pci_save_state(pdev
);
11845 bp
->pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
11846 if (bp
->pm_cap
== 0) {
11847 dev_err(&bp
->pdev
->dev
,
11848 "Cannot find power management capability, aborting\n");
11850 goto err_out_release
;
11854 if (!pci_is_pcie(pdev
)) {
11855 dev_err(&bp
->pdev
->dev
, "Not PCI Express, aborting\n");
11857 goto err_out_release
;
11860 rc
= bnx2x_set_coherency_mask(bp
);
11862 goto err_out_release
;
11864 dev
->mem_start
= pci_resource_start(pdev
, 0);
11865 dev
->base_addr
= dev
->mem_start
;
11866 dev
->mem_end
= pci_resource_end(pdev
, 0);
11868 dev
->irq
= pdev
->irq
;
11870 bp
->regview
= pci_ioremap_bar(pdev
, 0);
11871 if (!bp
->regview
) {
11872 dev_err(&bp
->pdev
->dev
,
11873 "Cannot map register space, aborting\n");
11875 goto err_out_release
;
11878 /* In E1/E1H use pci device function given by kernel.
11879 * In E2/E3 read physical function from ME register since these chips
11880 * support Physical Device Assignment where kernel BDF maybe arbitrary
11881 * (depending on hypervisor).
11884 bp
->pf_num
= PCI_FUNC(pdev
->devfn
);
11885 else {/* chip is E2/3*/
11886 pci_read_config_dword(bp
->pdev
,
11887 PCICFG_ME_REGISTER
, &pci_cfg_dword
);
11888 bp
->pf_num
= (u8
)((pci_cfg_dword
& ME_REG_ABS_PF_NUM
) >>
11889 ME_REG_ABS_PF_NUM_SHIFT
);
11891 BNX2X_DEV_INFO("me reg PF num: %d\n", bp
->pf_num
);
11893 bnx2x_set_power_state(bp
, PCI_D0
);
11895 /* clean indirect addresses */
11896 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
11897 PCICFG_VENDOR_ID_OFFSET
);
11899 * Clean the following indirect addresses for all functions since it
11900 * is not used by the driver.
11903 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F0
, 0);
11904 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F0
, 0);
11905 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F0
, 0);
11906 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F0
, 0);
11909 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F1
, 0);
11910 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F1
, 0);
11911 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F1
, 0);
11912 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F1
, 0);
11915 /* Enable internal target-read (in case we are probed after PF
11916 * FLR). Must be done prior to any BAR read access. Only for
11921 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
11924 dev
->watchdog_timeo
= TX_TIMEOUT
;
11926 dev
->netdev_ops
= &bnx2x_netdev_ops
;
11927 bnx2x_set_ethtool_ops(dev
);
11929 dev
->priv_flags
|= IFF_UNICAST_FLT
;
11931 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
11932 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
|
11933 NETIF_F_RXCSUM
| NETIF_F_LRO
| NETIF_F_GRO
|
11934 NETIF_F_RXHASH
| NETIF_F_HW_VLAN_TX
;
11936 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
11937 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
| NETIF_F_HIGHDMA
;
11939 dev
->features
|= dev
->hw_features
| NETIF_F_HW_VLAN_RX
;
11940 if (bp
->flags
& USING_DAC_FLAG
)
11941 dev
->features
|= NETIF_F_HIGHDMA
;
11943 /* Add Loopback capability to the device */
11944 dev
->hw_features
|= NETIF_F_LOOPBACK
;
11947 dev
->dcbnl_ops
= &bnx2x_dcbnl_ops
;
11950 /* get_port_hwinfo() will set prtad and mmds properly */
11951 bp
->mdio
.prtad
= MDIO_PRTAD_NONE
;
11953 bp
->mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
11954 bp
->mdio
.dev
= dev
;
11955 bp
->mdio
.mdio_read
= bnx2x_mdio_read
;
11956 bp
->mdio
.mdio_write
= bnx2x_mdio_write
;
11961 if (atomic_read(&pdev
->enable_cnt
) == 1)
11962 pci_release_regions(pdev
);
11965 pci_disable_device(pdev
);
11966 pci_set_drvdata(pdev
, NULL
);
11972 static void bnx2x_get_pcie_width_speed(struct bnx2x
*bp
, int *width
, int *speed
)
11976 pci_read_config_dword(bp
->pdev
, PCICFG_LINK_CONTROL
, &val
);
11977 *width
= (val
& PCICFG_LINK_WIDTH
) >> PCICFG_LINK_WIDTH_SHIFT
;
11979 /* return value of 1=2.5GHz 2=5GHz */
11980 *speed
= (val
& PCICFG_LINK_SPEED
) >> PCICFG_LINK_SPEED_SHIFT
;
11983 static int bnx2x_check_firmware(struct bnx2x
*bp
)
11985 const struct firmware
*firmware
= bp
->firmware
;
11986 struct bnx2x_fw_file_hdr
*fw_hdr
;
11987 struct bnx2x_fw_file_section
*sections
;
11988 u32 offset
, len
, num_ops
;
11993 if (firmware
->size
< sizeof(struct bnx2x_fw_file_hdr
)) {
11994 BNX2X_ERR("Wrong FW size\n");
11998 fw_hdr
= (struct bnx2x_fw_file_hdr
*)firmware
->data
;
11999 sections
= (struct bnx2x_fw_file_section
*)fw_hdr
;
12001 /* Make sure none of the offsets and sizes make us read beyond
12002 * the end of the firmware data */
12003 for (i
= 0; i
< sizeof(*fw_hdr
) / sizeof(*sections
); i
++) {
12004 offset
= be32_to_cpu(sections
[i
].offset
);
12005 len
= be32_to_cpu(sections
[i
].len
);
12006 if (offset
+ len
> firmware
->size
) {
12007 BNX2X_ERR("Section %d length is out of bounds\n", i
);
12012 /* Likewise for the init_ops offsets */
12013 offset
= be32_to_cpu(fw_hdr
->init_ops_offsets
.offset
);
12014 ops_offsets
= (u16
*)(firmware
->data
+ offset
);
12015 num_ops
= be32_to_cpu(fw_hdr
->init_ops
.len
) / sizeof(struct raw_op
);
12017 for (i
= 0; i
< be32_to_cpu(fw_hdr
->init_ops_offsets
.len
) / 2; i
++) {
12018 if (be16_to_cpu(ops_offsets
[i
]) > num_ops
) {
12019 BNX2X_ERR("Section offset %d is out of bounds\n", i
);
12024 /* Check FW version */
12025 offset
= be32_to_cpu(fw_hdr
->fw_version
.offset
);
12026 fw_ver
= firmware
->data
+ offset
;
12027 if ((fw_ver
[0] != BCM_5710_FW_MAJOR_VERSION
) ||
12028 (fw_ver
[1] != BCM_5710_FW_MINOR_VERSION
) ||
12029 (fw_ver
[2] != BCM_5710_FW_REVISION_VERSION
) ||
12030 (fw_ver
[3] != BCM_5710_FW_ENGINEERING_VERSION
)) {
12031 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12032 fw_ver
[0], fw_ver
[1], fw_ver
[2], fw_ver
[3],
12033 BCM_5710_FW_MAJOR_VERSION
,
12034 BCM_5710_FW_MINOR_VERSION
,
12035 BCM_5710_FW_REVISION_VERSION
,
12036 BCM_5710_FW_ENGINEERING_VERSION
);
12043 static void be32_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
12045 const __be32
*source
= (const __be32
*)_source
;
12046 u32
*target
= (u32
*)_target
;
12049 for (i
= 0; i
< n
/4; i
++)
12050 target
[i
] = be32_to_cpu(source
[i
]);
12054 Ops array is stored in the following format:
12055 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12057 static void bnx2x_prep_ops(const u8
*_source
, u8
*_target
, u32 n
)
12059 const __be32
*source
= (const __be32
*)_source
;
12060 struct raw_op
*target
= (struct raw_op
*)_target
;
12063 for (i
= 0, j
= 0; i
< n
/8; i
++, j
+= 2) {
12064 tmp
= be32_to_cpu(source
[j
]);
12065 target
[i
].op
= (tmp
>> 24) & 0xff;
12066 target
[i
].offset
= tmp
& 0xffffff;
12067 target
[i
].raw_data
= be32_to_cpu(source
[j
+ 1]);
12071 /* IRO array is stored in the following format:
12072 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12074 static void bnx2x_prep_iro(const u8
*_source
, u8
*_target
, u32 n
)
12076 const __be32
*source
= (const __be32
*)_source
;
12077 struct iro
*target
= (struct iro
*)_target
;
12080 for (i
= 0, j
= 0; i
< n
/sizeof(struct iro
); i
++) {
12081 target
[i
].base
= be32_to_cpu(source
[j
]);
12083 tmp
= be32_to_cpu(source
[j
]);
12084 target
[i
].m1
= (tmp
>> 16) & 0xffff;
12085 target
[i
].m2
= tmp
& 0xffff;
12087 tmp
= be32_to_cpu(source
[j
]);
12088 target
[i
].m3
= (tmp
>> 16) & 0xffff;
12089 target
[i
].size
= tmp
& 0xffff;
12094 static void be16_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
12096 const __be16
*source
= (const __be16
*)_source
;
12097 u16
*target
= (u16
*)_target
;
12100 for (i
= 0; i
< n
/2; i
++)
12101 target
[i
] = be16_to_cpu(source
[i
]);
12104 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12106 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12107 bp->arr = kmalloc(len, GFP_KERNEL); \
12110 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12111 (u8 *)bp->arr, len); \
12114 static int bnx2x_init_firmware(struct bnx2x
*bp
)
12116 const char *fw_file_name
;
12117 struct bnx2x_fw_file_hdr
*fw_hdr
;
12123 if (CHIP_IS_E1(bp
))
12124 fw_file_name
= FW_FILE_NAME_E1
;
12125 else if (CHIP_IS_E1H(bp
))
12126 fw_file_name
= FW_FILE_NAME_E1H
;
12127 else if (!CHIP_IS_E1x(bp
))
12128 fw_file_name
= FW_FILE_NAME_E2
;
12130 BNX2X_ERR("Unsupported chip revision\n");
12133 BNX2X_DEV_INFO("Loading %s\n", fw_file_name
);
12135 rc
= request_firmware(&bp
->firmware
, fw_file_name
, &bp
->pdev
->dev
);
12137 BNX2X_ERR("Can't load firmware file %s\n",
12139 goto request_firmware_exit
;
12142 rc
= bnx2x_check_firmware(bp
);
12144 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name
);
12145 goto request_firmware_exit
;
12148 fw_hdr
= (struct bnx2x_fw_file_hdr
*)bp
->firmware
->data
;
12150 /* Initialize the pointers to the init arrays */
12152 BNX2X_ALLOC_AND_SET(init_data
, request_firmware_exit
, be32_to_cpu_n
);
12155 BNX2X_ALLOC_AND_SET(init_ops
, init_ops_alloc_err
, bnx2x_prep_ops
);
12158 BNX2X_ALLOC_AND_SET(init_ops_offsets
, init_offsets_alloc_err
,
12161 /* STORMs firmware */
12162 INIT_TSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
12163 be32_to_cpu(fw_hdr
->tsem_int_table_data
.offset
);
12164 INIT_TSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
12165 be32_to_cpu(fw_hdr
->tsem_pram_data
.offset
);
12166 INIT_USEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
12167 be32_to_cpu(fw_hdr
->usem_int_table_data
.offset
);
12168 INIT_USEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
12169 be32_to_cpu(fw_hdr
->usem_pram_data
.offset
);
12170 INIT_XSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
12171 be32_to_cpu(fw_hdr
->xsem_int_table_data
.offset
);
12172 INIT_XSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
12173 be32_to_cpu(fw_hdr
->xsem_pram_data
.offset
);
12174 INIT_CSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
12175 be32_to_cpu(fw_hdr
->csem_int_table_data
.offset
);
12176 INIT_CSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
12177 be32_to_cpu(fw_hdr
->csem_pram_data
.offset
);
12179 BNX2X_ALLOC_AND_SET(iro_arr
, iro_alloc_err
, bnx2x_prep_iro
);
12184 kfree(bp
->init_ops_offsets
);
12185 init_offsets_alloc_err
:
12186 kfree(bp
->init_ops
);
12187 init_ops_alloc_err
:
12188 kfree(bp
->init_data
);
12189 request_firmware_exit
:
12190 release_firmware(bp
->firmware
);
12191 bp
->firmware
= NULL
;
12196 static void bnx2x_release_firmware(struct bnx2x
*bp
)
12198 kfree(bp
->init_ops_offsets
);
12199 kfree(bp
->init_ops
);
12200 kfree(bp
->init_data
);
12201 release_firmware(bp
->firmware
);
12202 bp
->firmware
= NULL
;
12206 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv
= {
12207 .init_hw_cmn_chip
= bnx2x_init_hw_common_chip
,
12208 .init_hw_cmn
= bnx2x_init_hw_common
,
12209 .init_hw_port
= bnx2x_init_hw_port
,
12210 .init_hw_func
= bnx2x_init_hw_func
,
12212 .reset_hw_cmn
= bnx2x_reset_common
,
12213 .reset_hw_port
= bnx2x_reset_port
,
12214 .reset_hw_func
= bnx2x_reset_func
,
12216 .gunzip_init
= bnx2x_gunzip_init
,
12217 .gunzip_end
= bnx2x_gunzip_end
,
12219 .init_fw
= bnx2x_init_firmware
,
12220 .release_fw
= bnx2x_release_firmware
,
12223 void bnx2x__init_func_obj(struct bnx2x
*bp
)
12225 /* Prepare DMAE related driver resources */
12226 bnx2x_setup_dmae(bp
);
12228 bnx2x_init_func_obj(bp
, &bp
->func_obj
,
12229 bnx2x_sp(bp
, func_rdata
),
12230 bnx2x_sp_mapping(bp
, func_rdata
),
12231 bnx2x_sp(bp
, func_afex_rdata
),
12232 bnx2x_sp_mapping(bp
, func_afex_rdata
),
12233 &bnx2x_func_sp_drv
);
12236 /* must be called after sriov-enable */
12237 static int bnx2x_set_qm_cid_count(struct bnx2x
*bp
)
12239 int cid_count
= BNX2X_L2_MAX_CID(bp
);
12242 cid_count
+= BNX2X_VF_CIDS
;
12244 if (CNIC_SUPPORT(bp
))
12245 cid_count
+= CNIC_CID_MAX
;
12247 return roundup(cid_count
, QM_CID_ROUND
);
12251 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12256 static int bnx2x_get_num_non_def_sbs(struct pci_dev
*pdev
,
12257 int cnic_cnt
, bool is_vf
)
12262 pos
= pci_find_capability(pdev
, PCI_CAP_ID_MSIX
);
12265 * If MSI-X is not supported - return number of SBs needed to support
12266 * one fast path queue: one FP queue + SB for CNIC
12269 dev_info(&pdev
->dev
, "no msix capability found\n");
12270 return 1 + cnic_cnt
;
12272 dev_info(&pdev
->dev
, "msix capability found\n");
12275 * The value in the PCI configuration space is the index of the last
12276 * entry, namely one less than the actual size of the table, which is
12277 * exactly what we want to return from this function: number of all SBs
12278 * without the default SB.
12279 * For VFs there is no default SB, then we return (index+1).
12281 pci_read_config_word(pdev
, pos
+ PCI_MSI_FLAGS
, &control
);
12283 index
= control
& PCI_MSIX_FLAGS_QSIZE
;
12285 return is_vf
? index
+ 1 : index
;
12288 static int set_max_cos_est(int chip_id
)
12294 return BNX2X_MULTI_TX_COS_E1X
;
12298 return BNX2X_MULTI_TX_COS_E2_E3A0
;
12304 case BCM57840_4_10
:
12305 case BCM57840_2_20
:
12314 return BNX2X_MULTI_TX_COS_E3B0
;
12317 pr_err("Unknown board_type (%d), aborting\n", chip_id
);
12322 static int set_is_vf(int chip_id
)
12336 struct cnic_eth_dev
*bnx2x_cnic_probe(struct net_device
*dev
);
12338 static int bnx2x_init_one(struct pci_dev
*pdev
,
12339 const struct pci_device_id
*ent
)
12341 struct net_device
*dev
= NULL
;
12343 int pcie_width
, pcie_speed
;
12344 int rc
, max_non_def_sbs
;
12345 int rx_count
, tx_count
, rss_count
, doorbell_size
;
12350 /* An estimated maximum supported CoS number according to the chip
12352 * We will try to roughly estimate the maximum number of CoSes this chip
12353 * may support in order to minimize the memory allocated for Tx
12354 * netdev_queue's. This number will be accurately calculated during the
12355 * initialization of bp->max_cos based on the chip versions AND chip
12356 * revision in the bnx2x_init_bp().
12358 max_cos_est
= set_max_cos_est(ent
->driver_data
);
12359 if (max_cos_est
< 0)
12360 return max_cos_est
;
12361 is_vf
= set_is_vf(ent
->driver_data
);
12362 cnic_cnt
= is_vf
? 0 : 1;
12364 max_non_def_sbs
= bnx2x_get_num_non_def_sbs(pdev
, cnic_cnt
, is_vf
);
12366 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12367 rss_count
= is_vf
? 1 : max_non_def_sbs
- cnic_cnt
;
12372 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12373 rx_count
= rss_count
+ cnic_cnt
;
12375 /* Maximum number of netdev Tx queues:
12376 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
12378 tx_count
= rss_count
* max_cos_est
+ cnic_cnt
;
12380 /* dev zeroed in init_etherdev */
12381 dev
= alloc_etherdev_mqs(sizeof(*bp
), tx_count
, rx_count
);
12385 bp
= netdev_priv(dev
);
12389 bp
->flags
|= IS_VF_FLAG
;
12391 bp
->igu_sb_cnt
= max_non_def_sbs
;
12392 bp
->igu_base_addr
= IS_VF(bp
) ? PXP_VF_ADDR_IGU_START
: BAR_IGU_INTMEM
;
12393 bp
->msg_enable
= debug
;
12394 bp
->cnic_support
= cnic_cnt
;
12395 bp
->cnic_probe
= bnx2x_cnic_probe
;
12397 pci_set_drvdata(pdev
, dev
);
12399 rc
= bnx2x_init_dev(bp
, pdev
, dev
, ent
->driver_data
);
12405 BNX2X_DEV_INFO("This is a %s function\n",
12406 IS_PF(bp
) ? "physical" : "virtual");
12407 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp
) ? "on" : "off");
12408 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs
);
12409 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12410 tx_count
, rx_count
);
12412 rc
= bnx2x_init_bp(bp
);
12414 goto init_one_exit
;
12416 /* Map doorbells here as we need the real value of bp->max_cos which
12417 * is initialized in bnx2x_init_bp() to determine the number of
12421 bnx2x_vf_map_doorbells(bp
);
12422 rc
= bnx2x_vf_pci_alloc(bp
);
12424 goto init_one_exit
;
12426 doorbell_size
= BNX2X_L2_MAX_CID(bp
) * (1 << BNX2X_DB_SHIFT
);
12427 if (doorbell_size
> pci_resource_len(pdev
, 2)) {
12428 dev_err(&bp
->pdev
->dev
,
12429 "Cannot map doorbells, bar size too small, aborting\n");
12431 goto init_one_exit
;
12433 bp
->doorbells
= ioremap_nocache(pci_resource_start(pdev
, 2),
12436 if (!bp
->doorbells
) {
12437 dev_err(&bp
->pdev
->dev
,
12438 "Cannot map doorbell space, aborting\n");
12440 goto init_one_exit
;
12444 rc
= bnx2x_vfpf_acquire(bp
, tx_count
, rx_count
);
12446 goto init_one_exit
;
12449 /* Enable SRIOV if capability found in configuration space.
12450 * Once the generic SR-IOV framework makes it in from the
12451 * pci tree this will be revised, to allow dynamic control
12452 * over the number of VFs. Right now, change the num of vfs
12453 * param below to enable SR-IOV.
12455 rc
= bnx2x_iov_init_one(bp
, int_mode
, 0/*num vfs*/);
12457 goto init_one_exit
;
12459 /* calc qm_cid_count */
12460 bp
->qm_cid_count
= bnx2x_set_qm_cid_count(bp
);
12461 BNX2X_DEV_INFO("qm_cid_count %d\n", bp
->qm_cid_count
);
12463 /* disable FCOE L2 queue for E1x*/
12464 if (CHIP_IS_E1x(bp
))
12465 bp
->flags
|= NO_FCOE_FLAG
;
12467 /* disable FCOE for 57840 device, until FW supports it */
12468 switch (ent
->driver_data
) {
12470 case BCM57840_4_10
:
12471 case BCM57840_2_20
:
12474 bp
->flags
|= NO_FCOE_FLAG
;
12477 /* Set bp->num_queues for MSI-X mode*/
12478 bnx2x_set_num_queues(bp
);
12480 /* Configure interrupt mode: try to enable MSI-X/MSI if
12483 rc
= bnx2x_set_int_mode(bp
);
12485 dev_err(&pdev
->dev
, "Cannot set interrupts\n");
12486 goto init_one_exit
;
12489 /* register the net device */
12490 rc
= register_netdev(dev
);
12492 dev_err(&pdev
->dev
, "Cannot register net device\n");
12493 goto init_one_exit
;
12495 BNX2X_DEV_INFO("device name after netdev register %s\n", dev
->name
);
12498 if (!NO_FCOE(bp
)) {
12499 /* Add storage MAC address */
12501 dev_addr_add(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
12505 bnx2x_get_pcie_width_speed(bp
, &pcie_width
, &pcie_speed
);
12506 BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12507 pcie_width
, pcie_speed
);
12510 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12511 board_info
[ent
->driver_data
].name
,
12512 (CHIP_REV(bp
) >> 12) + 'A', (CHIP_METAL(bp
) >> 4),
12514 ((!CHIP_IS_E2(bp
) && pcie_speed
== 2) ||
12515 (CHIP_IS_E2(bp
) && pcie_speed
== 1)) ?
12516 "5GHz (Gen2)" : "2.5GHz",
12517 dev
->base_addr
, bp
->pdev
->irq
, dev
->dev_addr
);
12523 iounmap(bp
->regview
);
12525 if (IS_PF(bp
) && bp
->doorbells
)
12526 iounmap(bp
->doorbells
);
12530 if (atomic_read(&pdev
->enable_cnt
) == 1)
12531 pci_release_regions(pdev
);
12533 pci_disable_device(pdev
);
12534 pci_set_drvdata(pdev
, NULL
);
12539 static void bnx2x_remove_one(struct pci_dev
*pdev
)
12541 struct net_device
*dev
= pci_get_drvdata(pdev
);
12545 dev_err(&pdev
->dev
, "BAD net device from bnx2x_init_one\n");
12548 bp
= netdev_priv(dev
);
12550 /* Delete storage MAC address */
12551 if (!NO_FCOE(bp
)) {
12553 dev_addr_del(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
12558 /* Delete app tlvs from dcbnl */
12559 bnx2x_dcbnl_update_applist(bp
, true);
12562 unregister_netdev(dev
);
12564 /* Power on: we can't let PCI layer write to us while we are in D3 */
12566 bnx2x_set_power_state(bp
, PCI_D0
);
12568 /* Disable MSI/MSI-X */
12569 bnx2x_disable_msi(bp
);
12573 bnx2x_set_power_state(bp
, PCI_D3hot
);
12575 /* Make sure RESET task is not scheduled before continuing */
12576 cancel_delayed_work_sync(&bp
->sp_rtnl_task
);
12578 bnx2x_iov_remove_one(bp
);
12580 /* send message via vfpf channel to release the resources of this vf */
12582 bnx2x_vfpf_release(bp
);
12585 iounmap(bp
->regview
);
12587 /* for vf doorbells are part of the regview and were unmapped along with
12588 * it. FW is only loaded by PF.
12592 iounmap(bp
->doorbells
);
12594 bnx2x_release_firmware(bp
);
12596 bnx2x_free_mem_bp(bp
);
12600 if (atomic_read(&pdev
->enable_cnt
) == 1)
12601 pci_release_regions(pdev
);
12603 pci_disable_device(pdev
);
12604 pci_set_drvdata(pdev
, NULL
);
12607 static int bnx2x_eeh_nic_unload(struct bnx2x
*bp
)
12611 bp
->state
= BNX2X_STATE_ERROR
;
12613 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
12615 if (CNIC_LOADED(bp
))
12616 bnx2x_cnic_notify(bp
, CNIC_CTL_STOP_CMD
);
12619 bnx2x_tx_disable(bp
);
12621 bnx2x_netif_stop(bp
, 0);
12622 /* Delete all NAPI objects */
12623 bnx2x_del_all_napi(bp
);
12624 if (CNIC_LOADED(bp
))
12625 bnx2x_del_all_napi_cnic(bp
);
12627 del_timer_sync(&bp
->timer
);
12629 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
12632 bnx2x_free_irq(bp
);
12634 /* Free SKBs, SGEs, TPA pool and driver internals */
12635 bnx2x_free_skbs(bp
);
12637 for_each_rx_queue(bp
, i
)
12638 bnx2x_free_rx_sge_range(bp
, bp
->fp
+ i
, NUM_RX_SGE
);
12640 bnx2x_free_mem(bp
);
12642 bp
->state
= BNX2X_STATE_CLOSED
;
12644 netif_carrier_off(bp
->dev
);
12649 static void bnx2x_eeh_recover(struct bnx2x
*bp
)
12653 mutex_init(&bp
->port
.phy_mutex
);
12656 val
= SHMEM_RD(bp
, validity_map
[BP_PORT(bp
)]);
12657 if ((val
& (SHR_MEM_VALIDITY_DEV_INFO
| SHR_MEM_VALIDITY_MB
))
12658 != (SHR_MEM_VALIDITY_DEV_INFO
| SHR_MEM_VALIDITY_MB
))
12659 BNX2X_ERR("BAD MCP validity signature\n");
12663 * bnx2x_io_error_detected - called when PCI error is detected
12664 * @pdev: Pointer to PCI device
12665 * @state: The current pci connection state
12667 * This function is called after a PCI bus error affecting
12668 * this device has been detected.
12670 static pci_ers_result_t
bnx2x_io_error_detected(struct pci_dev
*pdev
,
12671 pci_channel_state_t state
)
12673 struct net_device
*dev
= pci_get_drvdata(pdev
);
12674 struct bnx2x
*bp
= netdev_priv(dev
);
12678 netif_device_detach(dev
);
12680 if (state
== pci_channel_io_perm_failure
) {
12682 return PCI_ERS_RESULT_DISCONNECT
;
12685 if (netif_running(dev
))
12686 bnx2x_eeh_nic_unload(bp
);
12688 pci_disable_device(pdev
);
12692 /* Request a slot reset */
12693 return PCI_ERS_RESULT_NEED_RESET
;
12697 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12698 * @pdev: Pointer to PCI device
12700 * Restart the card from scratch, as if from a cold-boot.
12702 static pci_ers_result_t
bnx2x_io_slot_reset(struct pci_dev
*pdev
)
12704 struct net_device
*dev
= pci_get_drvdata(pdev
);
12705 struct bnx2x
*bp
= netdev_priv(dev
);
12709 if (pci_enable_device(pdev
)) {
12710 dev_err(&pdev
->dev
,
12711 "Cannot re-enable PCI device after reset\n");
12713 return PCI_ERS_RESULT_DISCONNECT
;
12716 pci_set_master(pdev
);
12717 pci_restore_state(pdev
);
12719 if (netif_running(dev
))
12720 bnx2x_set_power_state(bp
, PCI_D0
);
12724 return PCI_ERS_RESULT_RECOVERED
;
12728 * bnx2x_io_resume - called when traffic can start flowing again
12729 * @pdev: Pointer to PCI device
12731 * This callback is called when the error recovery driver tells us that
12732 * its OK to resume normal operation.
12734 static void bnx2x_io_resume(struct pci_dev
*pdev
)
12736 struct net_device
*dev
= pci_get_drvdata(pdev
);
12737 struct bnx2x
*bp
= netdev_priv(dev
);
12739 if (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) {
12740 netdev_err(bp
->dev
, "Handling parity error recovery. Try again later\n");
12746 bnx2x_eeh_recover(bp
);
12748 if (netif_running(dev
))
12749 bnx2x_nic_load(bp
, LOAD_NORMAL
);
12751 netif_device_attach(dev
);
12756 static const struct pci_error_handlers bnx2x_err_handler
= {
12757 .error_detected
= bnx2x_io_error_detected
,
12758 .slot_reset
= bnx2x_io_slot_reset
,
12759 .resume
= bnx2x_io_resume
,
12762 static struct pci_driver bnx2x_pci_driver
= {
12763 .name
= DRV_MODULE_NAME
,
12764 .id_table
= bnx2x_pci_tbl
,
12765 .probe
= bnx2x_init_one
,
12766 .remove
= bnx2x_remove_one
,
12767 .suspend
= bnx2x_suspend
,
12768 .resume
= bnx2x_resume
,
12769 .err_handler
= &bnx2x_err_handler
,
12772 static int __init
bnx2x_init(void)
12776 pr_info("%s", version
);
12778 bnx2x_wq
= create_singlethread_workqueue("bnx2x");
12779 if (bnx2x_wq
== NULL
) {
12780 pr_err("Cannot create workqueue\n");
12784 ret
= pci_register_driver(&bnx2x_pci_driver
);
12786 pr_err("Cannot register driver\n");
12787 destroy_workqueue(bnx2x_wq
);
12792 static void __exit
bnx2x_cleanup(void)
12794 struct list_head
*pos
, *q
;
12795 pci_unregister_driver(&bnx2x_pci_driver
);
12797 destroy_workqueue(bnx2x_wq
);
12799 /* Free globablly allocated resources */
12800 list_for_each_safe(pos
, q
, &bnx2x_prev_list
) {
12801 struct bnx2x_prev_path_list
*tmp
=
12802 list_entry(pos
, struct bnx2x_prev_path_list
, list
);
12808 void bnx2x_notify_link_changed(struct bnx2x
*bp
)
12810 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ BP_FUNC(bp
)*sizeof(u32
), 1);
12813 module_init(bnx2x_init
);
12814 module_exit(bnx2x_cleanup
);
12817 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12819 * @bp: driver handle
12820 * @set: set or clear the CAM entry
12822 * This function will wait until the ramdord completion returns.
12823 * Return 0 if success, -ENODEV if ramrod doesn't return.
12825 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x
*bp
)
12827 unsigned long ramrod_flags
= 0;
12829 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
12830 return bnx2x_set_mac_one(bp
, bp
->cnic_eth_dev
.iscsi_mac
,
12831 &bp
->iscsi_l2_mac_obj
, true,
12832 BNX2X_ISCSI_ETH_MAC
, &ramrod_flags
);
12835 /* count denotes the number of new completions we have seen */
12836 static void bnx2x_cnic_sp_post(struct bnx2x
*bp
, int count
)
12838 struct eth_spe
*spe
;
12839 int cxt_index
, cxt_offset
;
12841 #ifdef BNX2X_STOP_ON_ERROR
12842 if (unlikely(bp
->panic
))
12846 spin_lock_bh(&bp
->spq_lock
);
12847 BUG_ON(bp
->cnic_spq_pending
< count
);
12848 bp
->cnic_spq_pending
-= count
;
12851 for (; bp
->cnic_kwq_pending
; bp
->cnic_kwq_pending
--) {
12852 u16 type
= (le16_to_cpu(bp
->cnic_kwq_cons
->hdr
.type
)
12853 & SPE_HDR_CONN_TYPE
) >>
12854 SPE_HDR_CONN_TYPE_SHIFT
;
12855 u8 cmd
= (le32_to_cpu(bp
->cnic_kwq_cons
->hdr
.conn_and_cmd_data
)
12856 >> SPE_HDR_CMD_ID_SHIFT
) & 0xff;
12858 /* Set validation for iSCSI L2 client before sending SETUP
12861 if (type
== ETH_CONNECTION_TYPE
) {
12862 if (cmd
== RAMROD_CMD_ID_ETH_CLIENT_SETUP
) {
12863 cxt_index
= BNX2X_ISCSI_ETH_CID(bp
) /
12865 cxt_offset
= BNX2X_ISCSI_ETH_CID(bp
) -
12866 (cxt_index
* ILT_PAGE_CIDS
);
12867 bnx2x_set_ctx_validation(bp
,
12868 &bp
->context
[cxt_index
].
12869 vcxt
[cxt_offset
].eth
,
12870 BNX2X_ISCSI_ETH_CID(bp
));
12875 * There may be not more than 8 L2, not more than 8 L5 SPEs
12876 * and in the air. We also check that number of outstanding
12877 * COMMON ramrods is not more than the EQ and SPQ can
12880 if (type
== ETH_CONNECTION_TYPE
) {
12881 if (!atomic_read(&bp
->cq_spq_left
))
12884 atomic_dec(&bp
->cq_spq_left
);
12885 } else if (type
== NONE_CONNECTION_TYPE
) {
12886 if (!atomic_read(&bp
->eq_spq_left
))
12889 atomic_dec(&bp
->eq_spq_left
);
12890 } else if ((type
== ISCSI_CONNECTION_TYPE
) ||
12891 (type
== FCOE_CONNECTION_TYPE
)) {
12892 if (bp
->cnic_spq_pending
>=
12893 bp
->cnic_eth_dev
.max_kwqe_pending
)
12896 bp
->cnic_spq_pending
++;
12898 BNX2X_ERR("Unknown SPE type: %d\n", type
);
12903 spe
= bnx2x_sp_get_next(bp
);
12904 *spe
= *bp
->cnic_kwq_cons
;
12906 DP(BNX2X_MSG_SP
, "pending on SPQ %d, on KWQ %d count %d\n",
12907 bp
->cnic_spq_pending
, bp
->cnic_kwq_pending
, count
);
12909 if (bp
->cnic_kwq_cons
== bp
->cnic_kwq_last
)
12910 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
12912 bp
->cnic_kwq_cons
++;
12914 bnx2x_sp_prod_update(bp
);
12915 spin_unlock_bh(&bp
->spq_lock
);
12918 static int bnx2x_cnic_sp_queue(struct net_device
*dev
,
12919 struct kwqe_16
*kwqes
[], u32 count
)
12921 struct bnx2x
*bp
= netdev_priv(dev
);
12924 #ifdef BNX2X_STOP_ON_ERROR
12925 if (unlikely(bp
->panic
)) {
12926 BNX2X_ERR("Can't post to SP queue while panic\n");
12931 if ((bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) &&
12932 (bp
->recovery_state
!= BNX2X_RECOVERY_NIC_LOADING
)) {
12933 BNX2X_ERR("Handling parity error recovery. Try again later\n");
12937 spin_lock_bh(&bp
->spq_lock
);
12939 for (i
= 0; i
< count
; i
++) {
12940 struct eth_spe
*spe
= (struct eth_spe
*)kwqes
[i
];
12942 if (bp
->cnic_kwq_pending
== MAX_SP_DESC_CNT
)
12945 *bp
->cnic_kwq_prod
= *spe
;
12947 bp
->cnic_kwq_pending
++;
12949 DP(BNX2X_MSG_SP
, "L5 SPQE %x %x %x:%x pos %d\n",
12950 spe
->hdr
.conn_and_cmd_data
, spe
->hdr
.type
,
12951 spe
->data
.update_data_addr
.hi
,
12952 spe
->data
.update_data_addr
.lo
,
12953 bp
->cnic_kwq_pending
);
12955 if (bp
->cnic_kwq_prod
== bp
->cnic_kwq_last
)
12956 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
12958 bp
->cnic_kwq_prod
++;
12961 spin_unlock_bh(&bp
->spq_lock
);
12963 if (bp
->cnic_spq_pending
< bp
->cnic_eth_dev
.max_kwqe_pending
)
12964 bnx2x_cnic_sp_post(bp
, 0);
12969 static int bnx2x_cnic_ctl_send(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
12971 struct cnic_ops
*c_ops
;
12974 mutex_lock(&bp
->cnic_mutex
);
12975 c_ops
= rcu_dereference_protected(bp
->cnic_ops
,
12976 lockdep_is_held(&bp
->cnic_mutex
));
12978 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
12979 mutex_unlock(&bp
->cnic_mutex
);
12984 static int bnx2x_cnic_ctl_send_bh(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
12986 struct cnic_ops
*c_ops
;
12990 c_ops
= rcu_dereference(bp
->cnic_ops
);
12992 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
12999 * for commands that have no data
13001 int bnx2x_cnic_notify(struct bnx2x
*bp
, int cmd
)
13003 struct cnic_ctl_info ctl
= {0};
13007 return bnx2x_cnic_ctl_send(bp
, &ctl
);
13010 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
)
13012 struct cnic_ctl_info ctl
= {0};
13014 /* first we tell CNIC and only then we count this as a completion */
13015 ctl
.cmd
= CNIC_CTL_COMPLETION_CMD
;
13016 ctl
.data
.comp
.cid
= cid
;
13017 ctl
.data
.comp
.error
= err
;
13019 bnx2x_cnic_ctl_send_bh(bp
, &ctl
);
13020 bnx2x_cnic_sp_post(bp
, 0);
13024 /* Called with netif_addr_lock_bh() taken.
13025 * Sets an rx_mode config for an iSCSI ETH client.
13027 * Completion should be checked outside.
13029 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
)
13031 unsigned long accept_flags
= 0, ramrod_flags
= 0;
13032 u8 cl_id
= bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
13033 int sched_state
= BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
;
13036 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13037 * because it's the only way for UIO Queue to accept
13038 * multicasts (in non-promiscuous mode only one Queue per
13039 * function will receive multicast packets (leading in our
13042 __set_bit(BNX2X_ACCEPT_UNICAST
, &accept_flags
);
13043 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &accept_flags
);
13044 __set_bit(BNX2X_ACCEPT_BROADCAST
, &accept_flags
);
13045 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &accept_flags
);
13047 /* Clear STOP_PENDING bit if START is requested */
13048 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &bp
->sp_state
);
13050 sched_state
= BNX2X_FILTER_ISCSI_ETH_START_SCHED
;
13052 /* Clear START_PENDING bit if STOP is requested */
13053 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &bp
->sp_state
);
13055 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
13056 set_bit(sched_state
, &bp
->sp_state
);
13058 __set_bit(RAMROD_RX
, &ramrod_flags
);
13059 bnx2x_set_q_rx_mode(bp
, cl_id
, 0, accept_flags
, 0,
13065 static int bnx2x_drv_ctl(struct net_device
*dev
, struct drv_ctl_info
*ctl
)
13067 struct bnx2x
*bp
= netdev_priv(dev
);
13070 switch (ctl
->cmd
) {
13071 case DRV_CTL_CTXTBL_WR_CMD
: {
13072 u32 index
= ctl
->data
.io
.offset
;
13073 dma_addr_t addr
= ctl
->data
.io
.dma_addr
;
13075 bnx2x_ilt_wr(bp
, index
, addr
);
13079 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD
: {
13080 int count
= ctl
->data
.credit
.credit_count
;
13082 bnx2x_cnic_sp_post(bp
, count
);
13086 /* rtnl_lock is held. */
13087 case DRV_CTL_START_L2_CMD
: {
13088 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
13089 unsigned long sp_bits
= 0;
13091 /* Configure the iSCSI classification object */
13092 bnx2x_init_mac_obj(bp
, &bp
->iscsi_l2_mac_obj
,
13093 cp
->iscsi_l2_client_id
,
13094 cp
->iscsi_l2_cid
, BP_FUNC(bp
),
13095 bnx2x_sp(bp
, mac_rdata
),
13096 bnx2x_sp_mapping(bp
, mac_rdata
),
13097 BNX2X_FILTER_MAC_PENDING
,
13098 &bp
->sp_state
, BNX2X_OBJ_TYPE_RX
,
13101 /* Set iSCSI MAC address */
13102 rc
= bnx2x_set_iscsi_eth_mac_addr(bp
);
13109 /* Start accepting on iSCSI L2 ring */
13111 netif_addr_lock_bh(dev
);
13112 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
13113 netif_addr_unlock_bh(dev
);
13115 /* bits to wait on */
13116 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
13117 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &sp_bits
);
13119 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
13120 BNX2X_ERR("rx_mode completion timed out!\n");
13125 /* rtnl_lock is held. */
13126 case DRV_CTL_STOP_L2_CMD
: {
13127 unsigned long sp_bits
= 0;
13129 /* Stop accepting on iSCSI L2 ring */
13130 netif_addr_lock_bh(dev
);
13131 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
13132 netif_addr_unlock_bh(dev
);
13134 /* bits to wait on */
13135 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
13136 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &sp_bits
);
13138 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
13139 BNX2X_ERR("rx_mode completion timed out!\n");
13144 /* Unset iSCSI L2 MAC */
13145 rc
= bnx2x_del_all_macs(bp
, &bp
->iscsi_l2_mac_obj
,
13146 BNX2X_ISCSI_ETH_MAC
, true);
13149 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD
: {
13150 int count
= ctl
->data
.credit
.credit_count
;
13152 smp_mb__before_atomic_inc();
13153 atomic_add(count
, &bp
->cq_spq_left
);
13154 smp_mb__after_atomic_inc();
13157 case DRV_CTL_ULP_REGISTER_CMD
: {
13158 int ulp_type
= ctl
->data
.register_data
.ulp_type
;
13160 if (CHIP_IS_E3(bp
)) {
13161 int idx
= BP_FW_MB_IDX(bp
);
13162 u32 cap
= SHMEM2_RD(bp
, drv_capabilities_flag
[idx
]);
13163 int path
= BP_PATH(bp
);
13164 int port
= BP_PORT(bp
);
13166 u32 scratch_offset
;
13169 /* first write capability to shmem2 */
13170 if (ulp_type
== CNIC_ULP_ISCSI
)
13171 cap
|= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI
;
13172 else if (ulp_type
== CNIC_ULP_FCOE
)
13173 cap
|= DRV_FLAGS_CAPABILITIES_LOADED_FCOE
;
13174 SHMEM2_WR(bp
, drv_capabilities_flag
[idx
], cap
);
13176 if ((ulp_type
!= CNIC_ULP_FCOE
) ||
13177 (!SHMEM2_HAS(bp
, ncsi_oem_data_addr
)) ||
13178 (!(bp
->flags
& BC_SUPPORTS_FCOE_FEATURES
)))
13181 /* if reached here - should write fcoe capabilities */
13182 scratch_offset
= SHMEM2_RD(bp
, ncsi_oem_data_addr
);
13183 if (!scratch_offset
)
13185 scratch_offset
+= offsetof(struct glob_ncsi_oem_data
,
13186 fcoe_features
[path
][port
]);
13187 host_addr
= (u32
*) &(ctl
->data
.register_data
.
13189 for (i
= 0; i
< sizeof(struct fcoe_capabilities
);
13191 REG_WR(bp
, scratch_offset
+ i
,
13192 *(host_addr
+ i
/4));
13197 case DRV_CTL_ULP_UNREGISTER_CMD
: {
13198 int ulp_type
= ctl
->data
.ulp_type
;
13200 if (CHIP_IS_E3(bp
)) {
13201 int idx
= BP_FW_MB_IDX(bp
);
13204 cap
= SHMEM2_RD(bp
, drv_capabilities_flag
[idx
]);
13205 if (ulp_type
== CNIC_ULP_ISCSI
)
13206 cap
&= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI
;
13207 else if (ulp_type
== CNIC_ULP_FCOE
)
13208 cap
&= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE
;
13209 SHMEM2_WR(bp
, drv_capabilities_flag
[idx
], cap
);
13215 BNX2X_ERR("unknown command %x\n", ctl
->cmd
);
13222 void bnx2x_setup_cnic_irq_info(struct bnx2x
*bp
)
13224 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
13226 if (bp
->flags
& USING_MSIX_FLAG
) {
13227 cp
->drv_state
|= CNIC_DRV_STATE_USING_MSIX
;
13228 cp
->irq_arr
[0].irq_flags
|= CNIC_IRQ_FL_MSIX
;
13229 cp
->irq_arr
[0].vector
= bp
->msix_table
[1].vector
;
13231 cp
->drv_state
&= ~CNIC_DRV_STATE_USING_MSIX
;
13232 cp
->irq_arr
[0].irq_flags
&= ~CNIC_IRQ_FL_MSIX
;
13234 if (!CHIP_IS_E1x(bp
))
13235 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e2_sb
;
13237 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e1x_sb
;
13239 cp
->irq_arr
[0].status_blk_num
= bnx2x_cnic_fw_sb_id(bp
);
13240 cp
->irq_arr
[0].status_blk_num2
= bnx2x_cnic_igu_sb_id(bp
);
13241 cp
->irq_arr
[1].status_blk
= bp
->def_status_blk
;
13242 cp
->irq_arr
[1].status_blk_num
= DEF_SB_ID
;
13243 cp
->irq_arr
[1].status_blk_num2
= DEF_SB_IGU_ID
;
13248 void bnx2x_setup_cnic_info(struct bnx2x
*bp
)
13250 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
13253 cp
->ctx_tbl_offset
= FUNC_ILT_BASE(BP_FUNC(bp
)) +
13254 bnx2x_cid_ilt_lines(bp
);
13255 cp
->starting_cid
= bnx2x_cid_ilt_lines(bp
) * ILT_PAGE_CIDS
;
13256 cp
->fcoe_init_cid
= BNX2X_FCOE_ETH_CID(bp
);
13257 cp
->iscsi_l2_cid
= BNX2X_ISCSI_ETH_CID(bp
);
13259 if (NO_ISCSI_OOO(bp
))
13260 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI_OOO
;
13263 static int bnx2x_register_cnic(struct net_device
*dev
, struct cnic_ops
*ops
,
13266 struct bnx2x
*bp
= netdev_priv(dev
);
13267 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
13270 DP(NETIF_MSG_IFUP
, "Register_cnic called\n");
13273 BNX2X_ERR("NULL ops received\n");
13277 if (!CNIC_SUPPORT(bp
)) {
13278 BNX2X_ERR("Can't register CNIC when not supported\n");
13279 return -EOPNOTSUPP
;
13282 if (!CNIC_LOADED(bp
)) {
13283 rc
= bnx2x_load_cnic(bp
);
13285 BNX2X_ERR("CNIC-related load failed\n");
13291 bp
->cnic_enabled
= true;
13293 bp
->cnic_kwq
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
13297 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
13298 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
13299 bp
->cnic_kwq_last
= bp
->cnic_kwq
+ MAX_SP_DESC_CNT
;
13301 bp
->cnic_spq_pending
= 0;
13302 bp
->cnic_kwq_pending
= 0;
13304 bp
->cnic_data
= data
;
13307 cp
->drv_state
|= CNIC_DRV_STATE_REGD
;
13308 cp
->iro_arr
= bp
->iro_arr
;
13310 bnx2x_setup_cnic_irq_info(bp
);
13312 rcu_assign_pointer(bp
->cnic_ops
, ops
);
13317 static int bnx2x_unregister_cnic(struct net_device
*dev
)
13319 struct bnx2x
*bp
= netdev_priv(dev
);
13320 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
13322 mutex_lock(&bp
->cnic_mutex
);
13324 RCU_INIT_POINTER(bp
->cnic_ops
, NULL
);
13325 mutex_unlock(&bp
->cnic_mutex
);
13327 kfree(bp
->cnic_kwq
);
13328 bp
->cnic_kwq
= NULL
;
13333 struct cnic_eth_dev
*bnx2x_cnic_probe(struct net_device
*dev
)
13335 struct bnx2x
*bp
= netdev_priv(dev
);
13336 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
13338 /* If both iSCSI and FCoE are disabled - return NULL in
13339 * order to indicate CNIC that it should not try to work
13340 * with this device.
13342 if (NO_ISCSI(bp
) && NO_FCOE(bp
))
13345 cp
->drv_owner
= THIS_MODULE
;
13346 cp
->chip_id
= CHIP_ID(bp
);
13347 cp
->pdev
= bp
->pdev
;
13348 cp
->io_base
= bp
->regview
;
13349 cp
->io_base2
= bp
->doorbells
;
13350 cp
->max_kwqe_pending
= 8;
13351 cp
->ctx_blk_size
= CDU_ILT_PAGE_SZ
;
13352 cp
->ctx_tbl_offset
= FUNC_ILT_BASE(BP_FUNC(bp
)) +
13353 bnx2x_cid_ilt_lines(bp
);
13354 cp
->ctx_tbl_len
= CNIC_ILT_LINES
;
13355 cp
->starting_cid
= bnx2x_cid_ilt_lines(bp
) * ILT_PAGE_CIDS
;
13356 cp
->drv_submit_kwqes_16
= bnx2x_cnic_sp_queue
;
13357 cp
->drv_ctl
= bnx2x_drv_ctl
;
13358 cp
->drv_register_cnic
= bnx2x_register_cnic
;
13359 cp
->drv_unregister_cnic
= bnx2x_unregister_cnic
;
13360 cp
->fcoe_init_cid
= BNX2X_FCOE_ETH_CID(bp
);
13361 cp
->iscsi_l2_client_id
=
13362 bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
13363 cp
->iscsi_l2_cid
= BNX2X_ISCSI_ETH_CID(bp
);
13365 if (NO_ISCSI_OOO(bp
))
13366 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI_OOO
;
13369 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI
;
13372 cp
->drv_state
|= CNIC_DRV_STATE_NO_FCOE
;
13375 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13377 cp
->ctx_tbl_offset
,
13383 u32
bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath
*fp
)
13385 struct bnx2x
*bp
= fp
->bp
;
13386 u32 offset
= BAR_USTRORM_INTMEM
;
13389 return bnx2x_vf_ustorm_prods_offset(bp
, fp
);
13390 else if (!CHIP_IS_E1x(bp
))
13391 offset
+= USTORM_RX_PRODS_E2_OFFSET(fp
->cl_qzone_id
);
13393 offset
+= USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp
), fp
->cl_id
);
13398 /* called only on E1H or E2.
13399 * When pretending to be PF, the pretend value is the function number 0...7
13400 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13403 int bnx2x_pretend_func(struct bnx2x
*bp
, u16 pretend_func_val
)
13407 if (CHIP_IS_E1H(bp
) && pretend_func_val
>= E1H_FUNC_MAX
)
13410 /* get my own pretend register */
13411 pretend_reg
= bnx2x_get_pretend_reg(bp
);
13412 REG_WR(bp
, pretend_reg
, pretend_func_val
);
13413 REG_RD(bp
, pretend_reg
);