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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2012 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if.h>
43 #include <linux/if_vlan.h>
44 #include <net/ip.h>
45 #include <net/ipv6.h>
46 #include <net/tcp.h>
47 #include <net/checksum.h>
48 #include <net/ip6_checksum.h>
49 #include <linux/workqueue.h>
50 #include <linux/crc32.h>
51 #include <linux/crc32c.h>
52 #include <linux/prefetch.h>
53 #include <linux/zlib.h>
54 #include <linux/io.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
57
58 #include "bnx2x.h"
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_dcb.h"
63 #include "bnx2x_sp.h"
64
65 #include <linux/firmware.h>
66 #include "bnx2x_fw_file_hdr.h"
67 /* FW files */
68 #define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
76
77 /* Time in jiffies before concluding the transmitter is hung */
78 #define TX_TIMEOUT (5*HZ)
79
80 static char version[] __devinitdata =
81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
83
84 MODULE_AUTHOR("Eliezer Tamir");
85 MODULE_DESCRIPTION("Broadcom NetXtreme II "
86 "BCM57710/57711/57711E/"
87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
88 "57840/57840_MF Driver");
89 MODULE_LICENSE("GPL");
90 MODULE_VERSION(DRV_MODULE_VERSION);
91 MODULE_FIRMWARE(FW_FILE_NAME_E1);
92 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
93 MODULE_FIRMWARE(FW_FILE_NAME_E2);
94
95 static int multi_mode = 1;
96 module_param(multi_mode, int, 0);
97 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
98 "(0 Disable; 1 Enable (default))");
99
100 int num_queues;
101 module_param(num_queues, int, 0);
102 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
103 " (default is as a number of CPUs)");
104
105 static int disable_tpa;
106 module_param(disable_tpa, int, 0);
107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
108
109 #define INT_MODE_INTx 1
110 #define INT_MODE_MSI 2
111 static int int_mode;
112 module_param(int_mode, int, 0);
113 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
114 "(1 INT#x; 2 MSI)");
115
116 static int dropless_fc;
117 module_param(dropless_fc, int, 0);
118 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
119
120 static int mrrs = -1;
121 module_param(mrrs, int, 0);
122 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
123
124 static int debug;
125 module_param(debug, int, 0);
126 MODULE_PARM_DESC(debug, " Default debug msglevel");
127
128
129
130 struct workqueue_struct *bnx2x_wq;
131
132 enum bnx2x_board_type {
133 BCM57710 = 0,
134 BCM57711,
135 BCM57711E,
136 BCM57712,
137 BCM57712_MF,
138 BCM57800,
139 BCM57800_MF,
140 BCM57810,
141 BCM57810_MF,
142 BCM57840,
143 BCM57840_MF
144 };
145
146 /* indexed by board_type, above */
147 static struct {
148 char *name;
149 } board_info[] __devinitdata = {
150 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
151 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
152 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
153 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
155 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
157 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
159 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
161 "Ethernet Multi Function"}
162 };
163
164 #ifndef PCI_DEVICE_ID_NX2_57710
165 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
166 #endif
167 #ifndef PCI_DEVICE_ID_NX2_57711
168 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
169 #endif
170 #ifndef PCI_DEVICE_ID_NX2_57711E
171 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
172 #endif
173 #ifndef PCI_DEVICE_ID_NX2_57712
174 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
175 #endif
176 #ifndef PCI_DEVICE_ID_NX2_57712_MF
177 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
178 #endif
179 #ifndef PCI_DEVICE_ID_NX2_57800
180 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
181 #endif
182 #ifndef PCI_DEVICE_ID_NX2_57800_MF
183 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
184 #endif
185 #ifndef PCI_DEVICE_ID_NX2_57810
186 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
187 #endif
188 #ifndef PCI_DEVICE_ID_NX2_57810_MF
189 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
190 #endif
191 #ifndef PCI_DEVICE_ID_NX2_57840
192 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
193 #endif
194 #ifndef PCI_DEVICE_ID_NX2_57840_MF
195 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
196 #endif
197 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
198 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
209 { 0 }
210 };
211
212 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
213
214 /****************************************************************************
215 * General service functions
216 ****************************************************************************/
217
218 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
219 u32 addr, dma_addr_t mapping)
220 {
221 REG_WR(bp, addr, U64_LO(mapping));
222 REG_WR(bp, addr + 4, U64_HI(mapping));
223 }
224
225 static inline void storm_memset_spq_addr(struct bnx2x *bp,
226 dma_addr_t mapping, u16 abs_fid)
227 {
228 u32 addr = XSEM_REG_FAST_MEMORY +
229 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
230
231 __storm_memset_dma_mapping(bp, addr, mapping);
232 }
233
234 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
235 u16 pf_id)
236 {
237 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
238 pf_id);
239 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
240 pf_id);
241 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
242 pf_id);
243 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
244 pf_id);
245 }
246
247 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
248 u8 enable)
249 {
250 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
251 enable);
252 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
253 enable);
254 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
255 enable);
256 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
257 enable);
258 }
259
260 static inline void storm_memset_eq_data(struct bnx2x *bp,
261 struct event_ring_data *eq_data,
262 u16 pfid)
263 {
264 size_t size = sizeof(struct event_ring_data);
265
266 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
267
268 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
269 }
270
271 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
272 u16 pfid)
273 {
274 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
275 REG_WR16(bp, addr, eq_prod);
276 }
277
278 /* used only at init
279 * locking is done by mcp
280 */
281 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
282 {
283 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
284 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
285 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
286 PCICFG_VENDOR_ID_OFFSET);
287 }
288
289 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
290 {
291 u32 val;
292
293 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
294 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
295 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
296 PCICFG_VENDOR_ID_OFFSET);
297
298 return val;
299 }
300
301 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
302 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
303 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
304 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
305 #define DMAE_DP_DST_NONE "dst_addr [none]"
306
307 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
308 int msglvl)
309 {
310 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
311
312 switch (dmae->opcode & DMAE_COMMAND_DST) {
313 case DMAE_CMD_DST_PCI:
314 if (src_type == DMAE_CMD_SRC_PCI)
315 DP(msglvl, "DMAE: opcode 0x%08x\n"
316 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
317 "comp_addr [%x:%08x], comp_val 0x%08x\n",
318 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
319 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
320 dmae->comp_addr_hi, dmae->comp_addr_lo,
321 dmae->comp_val);
322 else
323 DP(msglvl, "DMAE: opcode 0x%08x\n"
324 "src [%08x], len [%d*4], dst [%x:%08x]\n"
325 "comp_addr [%x:%08x], comp_val 0x%08x\n",
326 dmae->opcode, dmae->src_addr_lo >> 2,
327 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
328 dmae->comp_addr_hi, dmae->comp_addr_lo,
329 dmae->comp_val);
330 break;
331 case DMAE_CMD_DST_GRC:
332 if (src_type == DMAE_CMD_SRC_PCI)
333 DP(msglvl, "DMAE: opcode 0x%08x\n"
334 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
335 "comp_addr [%x:%08x], comp_val 0x%08x\n",
336 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
337 dmae->len, dmae->dst_addr_lo >> 2,
338 dmae->comp_addr_hi, dmae->comp_addr_lo,
339 dmae->comp_val);
340 else
341 DP(msglvl, "DMAE: opcode 0x%08x\n"
342 "src [%08x], len [%d*4], dst [%08x]\n"
343 "comp_addr [%x:%08x], comp_val 0x%08x\n",
344 dmae->opcode, dmae->src_addr_lo >> 2,
345 dmae->len, dmae->dst_addr_lo >> 2,
346 dmae->comp_addr_hi, dmae->comp_addr_lo,
347 dmae->comp_val);
348 break;
349 default:
350 if (src_type == DMAE_CMD_SRC_PCI)
351 DP(msglvl, "DMAE: opcode 0x%08x\n"
352 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
353 "comp_addr [%x:%08x] comp_val 0x%08x\n",
354 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
355 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
356 dmae->comp_val);
357 else
358 DP(msglvl, "DMAE: opcode 0x%08x\n"
359 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
360 "comp_addr [%x:%08x] comp_val 0x%08x\n",
361 dmae->opcode, dmae->src_addr_lo >> 2,
362 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
363 dmae->comp_val);
364 break;
365 }
366
367 }
368
369 /* copy command into DMAE command memory and set DMAE command go */
370 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
371 {
372 u32 cmd_offset;
373 int i;
374
375 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
376 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
377 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
378 }
379 REG_WR(bp, dmae_reg_go_c[idx], 1);
380 }
381
382 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
383 {
384 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
385 DMAE_CMD_C_ENABLE);
386 }
387
388 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
389 {
390 return opcode & ~DMAE_CMD_SRC_RESET;
391 }
392
393 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
394 bool with_comp, u8 comp_type)
395 {
396 u32 opcode = 0;
397
398 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
399 (dst_type << DMAE_COMMAND_DST_SHIFT));
400
401 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
402
403 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
404 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
405 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
406 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
407
408 #ifdef __BIG_ENDIAN
409 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
410 #else
411 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
412 #endif
413 if (with_comp)
414 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
415 return opcode;
416 }
417
418 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
419 struct dmae_command *dmae,
420 u8 src_type, u8 dst_type)
421 {
422 memset(dmae, 0, sizeof(struct dmae_command));
423
424 /* set the opcode */
425 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
426 true, DMAE_COMP_PCI);
427
428 /* fill in the completion parameters */
429 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
430 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
431 dmae->comp_val = DMAE_COMP_VAL;
432 }
433
434 /* issue a dmae command over the init-channel and wailt for completion */
435 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
436 struct dmae_command *dmae)
437 {
438 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
439 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
440 int rc = 0;
441
442 /*
443 * Lock the dmae channel. Disable BHs to prevent a dead-lock
444 * as long as this code is called both from syscall context and
445 * from ndo_set_rx_mode() flow that may be called from BH.
446 */
447 spin_lock_bh(&bp->dmae_lock);
448
449 /* reset completion */
450 *wb_comp = 0;
451
452 /* post the command on the channel used for initializations */
453 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
454
455 /* wait for completion */
456 udelay(5);
457 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
458
459 if (!cnt ||
460 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
461 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
462 BNX2X_ERR("DMAE timeout!\n");
463 rc = DMAE_TIMEOUT;
464 goto unlock;
465 }
466 cnt--;
467 udelay(50);
468 }
469 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
470 BNX2X_ERR("DMAE PCI error!\n");
471 rc = DMAE_PCI_ERROR;
472 }
473
474 unlock:
475 spin_unlock_bh(&bp->dmae_lock);
476 return rc;
477 }
478
479 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
480 u32 len32)
481 {
482 struct dmae_command dmae;
483
484 if (!bp->dmae_ready) {
485 u32 *data = bnx2x_sp(bp, wb_data[0]);
486
487 if (CHIP_IS_E1(bp))
488 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
489 else
490 bnx2x_init_str_wr(bp, dst_addr, data, len32);
491 return;
492 }
493
494 /* set opcode and fixed command fields */
495 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
496
497 /* fill in addresses and len */
498 dmae.src_addr_lo = U64_LO(dma_addr);
499 dmae.src_addr_hi = U64_HI(dma_addr);
500 dmae.dst_addr_lo = dst_addr >> 2;
501 dmae.dst_addr_hi = 0;
502 dmae.len = len32;
503
504 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
505
506 /* issue the command and wait for completion */
507 bnx2x_issue_dmae_with_comp(bp, &dmae);
508 }
509
510 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
511 {
512 struct dmae_command dmae;
513
514 if (!bp->dmae_ready) {
515 u32 *data = bnx2x_sp(bp, wb_data[0]);
516 int i;
517
518 if (CHIP_IS_E1(bp))
519 for (i = 0; i < len32; i++)
520 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
521 else
522 for (i = 0; i < len32; i++)
523 data[i] = REG_RD(bp, src_addr + i*4);
524
525 return;
526 }
527
528 /* set opcode and fixed command fields */
529 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
530
531 /* fill in addresses and len */
532 dmae.src_addr_lo = src_addr >> 2;
533 dmae.src_addr_hi = 0;
534 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
535 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
536 dmae.len = len32;
537
538 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
539
540 /* issue the command and wait for completion */
541 bnx2x_issue_dmae_with_comp(bp, &dmae);
542 }
543
544 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
545 u32 addr, u32 len)
546 {
547 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
548 int offset = 0;
549
550 while (len > dmae_wr_max) {
551 bnx2x_write_dmae(bp, phys_addr + offset,
552 addr + offset, dmae_wr_max);
553 offset += dmae_wr_max * 4;
554 len -= dmae_wr_max;
555 }
556
557 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
558 }
559
560 /* used only for slowpath so not inlined */
561 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
562 {
563 u32 wb_write[2];
564
565 wb_write[0] = val_hi;
566 wb_write[1] = val_lo;
567 REG_WR_DMAE(bp, reg, wb_write, 2);
568 }
569
570 #ifdef USE_WB_RD
571 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
572 {
573 u32 wb_data[2];
574
575 REG_RD_DMAE(bp, reg, wb_data, 2);
576
577 return HILO_U64(wb_data[0], wb_data[1]);
578 }
579 #endif
580
581 static int bnx2x_mc_assert(struct bnx2x *bp)
582 {
583 char last_idx;
584 int i, rc = 0;
585 u32 row0, row1, row2, row3;
586
587 /* XSTORM */
588 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
589 XSTORM_ASSERT_LIST_INDEX_OFFSET);
590 if (last_idx)
591 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
592
593 /* print the asserts */
594 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
595
596 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
597 XSTORM_ASSERT_LIST_OFFSET(i));
598 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
599 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
600 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
601 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
602 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
603 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
604
605 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
606 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
607 i, row3, row2, row1, row0);
608 rc++;
609 } else {
610 break;
611 }
612 }
613
614 /* TSTORM */
615 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
616 TSTORM_ASSERT_LIST_INDEX_OFFSET);
617 if (last_idx)
618 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
619
620 /* print the asserts */
621 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
622
623 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
624 TSTORM_ASSERT_LIST_OFFSET(i));
625 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
626 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
627 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
628 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
629 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
630 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
631
632 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
633 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
634 i, row3, row2, row1, row0);
635 rc++;
636 } else {
637 break;
638 }
639 }
640
641 /* CSTORM */
642 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
643 CSTORM_ASSERT_LIST_INDEX_OFFSET);
644 if (last_idx)
645 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
646
647 /* print the asserts */
648 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
649
650 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
651 CSTORM_ASSERT_LIST_OFFSET(i));
652 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
653 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
654 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
655 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
656 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
657 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
658
659 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
660 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
661 i, row3, row2, row1, row0);
662 rc++;
663 } else {
664 break;
665 }
666 }
667
668 /* USTORM */
669 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
670 USTORM_ASSERT_LIST_INDEX_OFFSET);
671 if (last_idx)
672 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
673
674 /* print the asserts */
675 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
676
677 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
678 USTORM_ASSERT_LIST_OFFSET(i));
679 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
680 USTORM_ASSERT_LIST_OFFSET(i) + 4);
681 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
682 USTORM_ASSERT_LIST_OFFSET(i) + 8);
683 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
684 USTORM_ASSERT_LIST_OFFSET(i) + 12);
685
686 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
687 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
688 i, row3, row2, row1, row0);
689 rc++;
690 } else {
691 break;
692 }
693 }
694
695 return rc;
696 }
697
698 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
699 {
700 u32 addr, val;
701 u32 mark, offset;
702 __be32 data[9];
703 int word;
704 u32 trace_shmem_base;
705 if (BP_NOMCP(bp)) {
706 BNX2X_ERR("NO MCP - can not dump\n");
707 return;
708 }
709 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
710 (bp->common.bc_ver & 0xff0000) >> 16,
711 (bp->common.bc_ver & 0xff00) >> 8,
712 (bp->common.bc_ver & 0xff));
713
714 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
715 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
716 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
717
718 if (BP_PATH(bp) == 0)
719 trace_shmem_base = bp->common.shmem_base;
720 else
721 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
722 addr = trace_shmem_base - 0x0800 + 4;
723 mark = REG_RD(bp, addr);
724 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
725 + ((mark + 0x3) & ~0x3) - 0x08000000;
726 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
727
728 printk("%s", lvl);
729 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
730 for (word = 0; word < 8; word++)
731 data[word] = htonl(REG_RD(bp, offset + 4*word));
732 data[8] = 0x0;
733 pr_cont("%s", (char *)data);
734 }
735 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
736 for (word = 0; word < 8; word++)
737 data[word] = htonl(REG_RD(bp, offset + 4*word));
738 data[8] = 0x0;
739 pr_cont("%s", (char *)data);
740 }
741 printk("%s" "end of fw dump\n", lvl);
742 }
743
744 static inline void bnx2x_fw_dump(struct bnx2x *bp)
745 {
746 bnx2x_fw_dump_lvl(bp, KERN_ERR);
747 }
748
749 void bnx2x_panic_dump(struct bnx2x *bp)
750 {
751 int i;
752 u16 j;
753 struct hc_sp_status_block_data sp_sb_data;
754 int func = BP_FUNC(bp);
755 #ifdef BNX2X_STOP_ON_ERROR
756 u16 start = 0, end = 0;
757 u8 cos;
758 #endif
759
760 bp->stats_state = STATS_STATE_DISABLED;
761 bp->eth_stats.unrecoverable_error++;
762 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
763
764 BNX2X_ERR("begin crash dump -----------------\n");
765
766 /* Indices */
767 /* Common */
768 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
769 bp->def_idx, bp->def_att_idx, bp->attn_state,
770 bp->spq_prod_idx, bp->stats_counter);
771 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
772 bp->def_status_blk->atten_status_block.attn_bits,
773 bp->def_status_blk->atten_status_block.attn_bits_ack,
774 bp->def_status_blk->atten_status_block.status_block_id,
775 bp->def_status_blk->atten_status_block.attn_bits_index);
776 BNX2X_ERR(" def (");
777 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
778 pr_cont("0x%x%s",
779 bp->def_status_blk->sp_sb.index_values[i],
780 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
781
782 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
783 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
784 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
785 i*sizeof(u32));
786
787 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
788 sp_sb_data.igu_sb_id,
789 sp_sb_data.igu_seg_id,
790 sp_sb_data.p_func.pf_id,
791 sp_sb_data.p_func.vnic_id,
792 sp_sb_data.p_func.vf_id,
793 sp_sb_data.p_func.vf_valid,
794 sp_sb_data.state);
795
796
797 for_each_eth_queue(bp, i) {
798 struct bnx2x_fastpath *fp = &bp->fp[i];
799 int loop;
800 struct hc_status_block_data_e2 sb_data_e2;
801 struct hc_status_block_data_e1x sb_data_e1x;
802 struct hc_status_block_sm *hc_sm_p =
803 CHIP_IS_E1x(bp) ?
804 sb_data_e1x.common.state_machine :
805 sb_data_e2.common.state_machine;
806 struct hc_index_data *hc_index_p =
807 CHIP_IS_E1x(bp) ?
808 sb_data_e1x.index_data :
809 sb_data_e2.index_data;
810 u8 data_size, cos;
811 u32 *sb_data_p;
812 struct bnx2x_fp_txdata txdata;
813
814 /* Rx */
815 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
816 i, fp->rx_bd_prod, fp->rx_bd_cons,
817 fp->rx_comp_prod,
818 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
819 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
820 fp->rx_sge_prod, fp->last_max_sge,
821 le16_to_cpu(fp->fp_hc_idx));
822
823 /* Tx */
824 for_each_cos_in_tx_queue(fp, cos)
825 {
826 txdata = fp->txdata[cos];
827 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
828 i, txdata.tx_pkt_prod,
829 txdata.tx_pkt_cons, txdata.tx_bd_prod,
830 txdata.tx_bd_cons,
831 le16_to_cpu(*txdata.tx_cons_sb));
832 }
833
834 loop = CHIP_IS_E1x(bp) ?
835 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
836
837 /* host sb data */
838
839 #ifdef BCM_CNIC
840 if (IS_FCOE_FP(fp))
841 continue;
842 #endif
843 BNX2X_ERR(" run indexes (");
844 for (j = 0; j < HC_SB_MAX_SM; j++)
845 pr_cont("0x%x%s",
846 fp->sb_running_index[j],
847 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
848
849 BNX2X_ERR(" indexes (");
850 for (j = 0; j < loop; j++)
851 pr_cont("0x%x%s",
852 fp->sb_index_values[j],
853 (j == loop - 1) ? ")" : " ");
854 /* fw sb data */
855 data_size = CHIP_IS_E1x(bp) ?
856 sizeof(struct hc_status_block_data_e1x) :
857 sizeof(struct hc_status_block_data_e2);
858 data_size /= sizeof(u32);
859 sb_data_p = CHIP_IS_E1x(bp) ?
860 (u32 *)&sb_data_e1x :
861 (u32 *)&sb_data_e2;
862 /* copy sb data in here */
863 for (j = 0; j < data_size; j++)
864 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
865 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
866 j * sizeof(u32));
867
868 if (!CHIP_IS_E1x(bp)) {
869 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
870 sb_data_e2.common.p_func.pf_id,
871 sb_data_e2.common.p_func.vf_id,
872 sb_data_e2.common.p_func.vf_valid,
873 sb_data_e2.common.p_func.vnic_id,
874 sb_data_e2.common.same_igu_sb_1b,
875 sb_data_e2.common.state);
876 } else {
877 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
878 sb_data_e1x.common.p_func.pf_id,
879 sb_data_e1x.common.p_func.vf_id,
880 sb_data_e1x.common.p_func.vf_valid,
881 sb_data_e1x.common.p_func.vnic_id,
882 sb_data_e1x.common.same_igu_sb_1b,
883 sb_data_e1x.common.state);
884 }
885
886 /* SB_SMs data */
887 for (j = 0; j < HC_SB_MAX_SM; j++) {
888 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
889 j, hc_sm_p[j].__flags,
890 hc_sm_p[j].igu_sb_id,
891 hc_sm_p[j].igu_seg_id,
892 hc_sm_p[j].time_to_expire,
893 hc_sm_p[j].timer_value);
894 }
895
896 /* Indecies data */
897 for (j = 0; j < loop; j++) {
898 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
899 hc_index_p[j].flags,
900 hc_index_p[j].timeout);
901 }
902 }
903
904 #ifdef BNX2X_STOP_ON_ERROR
905 /* Rings */
906 /* Rx */
907 for_each_rx_queue(bp, i) {
908 struct bnx2x_fastpath *fp = &bp->fp[i];
909
910 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
911 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
912 for (j = start; j != end; j = RX_BD(j + 1)) {
913 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
914 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
915
916 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
917 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
918 }
919
920 start = RX_SGE(fp->rx_sge_prod);
921 end = RX_SGE(fp->last_max_sge);
922 for (j = start; j != end; j = RX_SGE(j + 1)) {
923 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
924 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
925
926 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
927 i, j, rx_sge[1], rx_sge[0], sw_page->page);
928 }
929
930 start = RCQ_BD(fp->rx_comp_cons - 10);
931 end = RCQ_BD(fp->rx_comp_cons + 503);
932 for (j = start; j != end; j = RCQ_BD(j + 1)) {
933 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
934
935 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
936 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
937 }
938 }
939
940 /* Tx */
941 for_each_tx_queue(bp, i) {
942 struct bnx2x_fastpath *fp = &bp->fp[i];
943 for_each_cos_in_tx_queue(fp, cos) {
944 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
945
946 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
947 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
948 for (j = start; j != end; j = TX_BD(j + 1)) {
949 struct sw_tx_bd *sw_bd =
950 &txdata->tx_buf_ring[j];
951
952 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
953 i, cos, j, sw_bd->skb,
954 sw_bd->first_bd);
955 }
956
957 start = TX_BD(txdata->tx_bd_cons - 10);
958 end = TX_BD(txdata->tx_bd_cons + 254);
959 for (j = start; j != end; j = TX_BD(j + 1)) {
960 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
961
962 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
963 i, cos, j, tx_bd[0], tx_bd[1],
964 tx_bd[2], tx_bd[3]);
965 }
966 }
967 }
968 #endif
969 bnx2x_fw_dump(bp);
970 bnx2x_mc_assert(bp);
971 BNX2X_ERR("end crash dump -----------------\n");
972 }
973
974 /*
975 * FLR Support for E2
976 *
977 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
978 * initialization.
979 */
980 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
981 #define FLR_WAIT_INTERVAL 50 /* usec */
982 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
983
984 struct pbf_pN_buf_regs {
985 int pN;
986 u32 init_crd;
987 u32 crd;
988 u32 crd_freed;
989 };
990
991 struct pbf_pN_cmd_regs {
992 int pN;
993 u32 lines_occup;
994 u32 lines_freed;
995 };
996
997 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
998 struct pbf_pN_buf_regs *regs,
999 u32 poll_count)
1000 {
1001 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1002 u32 cur_cnt = poll_count;
1003
1004 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1005 crd = crd_start = REG_RD(bp, regs->crd);
1006 init_crd = REG_RD(bp, regs->init_crd);
1007
1008 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1009 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1010 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1011
1012 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1013 (init_crd - crd_start))) {
1014 if (cur_cnt--) {
1015 udelay(FLR_WAIT_INTERVAL);
1016 crd = REG_RD(bp, regs->crd);
1017 crd_freed = REG_RD(bp, regs->crd_freed);
1018 } else {
1019 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1020 regs->pN);
1021 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1022 regs->pN, crd);
1023 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1024 regs->pN, crd_freed);
1025 break;
1026 }
1027 }
1028 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1029 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1030 }
1031
1032 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1033 struct pbf_pN_cmd_regs *regs,
1034 u32 poll_count)
1035 {
1036 u32 occup, to_free, freed, freed_start;
1037 u32 cur_cnt = poll_count;
1038
1039 occup = to_free = REG_RD(bp, regs->lines_occup);
1040 freed = freed_start = REG_RD(bp, regs->lines_freed);
1041
1042 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1043 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1044
1045 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1046 if (cur_cnt--) {
1047 udelay(FLR_WAIT_INTERVAL);
1048 occup = REG_RD(bp, regs->lines_occup);
1049 freed = REG_RD(bp, regs->lines_freed);
1050 } else {
1051 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1052 regs->pN);
1053 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1054 regs->pN, occup);
1055 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1056 regs->pN, freed);
1057 break;
1058 }
1059 }
1060 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1061 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1062 }
1063
1064 static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1065 u32 expected, u32 poll_count)
1066 {
1067 u32 cur_cnt = poll_count;
1068 u32 val;
1069
1070 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1071 udelay(FLR_WAIT_INTERVAL);
1072
1073 return val;
1074 }
1075
1076 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1077 char *msg, u32 poll_cnt)
1078 {
1079 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1080 if (val != 0) {
1081 BNX2X_ERR("%s usage count=%d\n", msg, val);
1082 return 1;
1083 }
1084 return 0;
1085 }
1086
1087 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1088 {
1089 /* adjust polling timeout */
1090 if (CHIP_REV_IS_EMUL(bp))
1091 return FLR_POLL_CNT * 2000;
1092
1093 if (CHIP_REV_IS_FPGA(bp))
1094 return FLR_POLL_CNT * 120;
1095
1096 return FLR_POLL_CNT;
1097 }
1098
1099 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1100 {
1101 struct pbf_pN_cmd_regs cmd_regs[] = {
1102 {0, (CHIP_IS_E3B0(bp)) ?
1103 PBF_REG_TQ_OCCUPANCY_Q0 :
1104 PBF_REG_P0_TQ_OCCUPANCY,
1105 (CHIP_IS_E3B0(bp)) ?
1106 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1107 PBF_REG_P0_TQ_LINES_FREED_CNT},
1108 {1, (CHIP_IS_E3B0(bp)) ?
1109 PBF_REG_TQ_OCCUPANCY_Q1 :
1110 PBF_REG_P1_TQ_OCCUPANCY,
1111 (CHIP_IS_E3B0(bp)) ?
1112 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1113 PBF_REG_P1_TQ_LINES_FREED_CNT},
1114 {4, (CHIP_IS_E3B0(bp)) ?
1115 PBF_REG_TQ_OCCUPANCY_LB_Q :
1116 PBF_REG_P4_TQ_OCCUPANCY,
1117 (CHIP_IS_E3B0(bp)) ?
1118 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1119 PBF_REG_P4_TQ_LINES_FREED_CNT}
1120 };
1121
1122 struct pbf_pN_buf_regs buf_regs[] = {
1123 {0, (CHIP_IS_E3B0(bp)) ?
1124 PBF_REG_INIT_CRD_Q0 :
1125 PBF_REG_P0_INIT_CRD ,
1126 (CHIP_IS_E3B0(bp)) ?
1127 PBF_REG_CREDIT_Q0 :
1128 PBF_REG_P0_CREDIT,
1129 (CHIP_IS_E3B0(bp)) ?
1130 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1131 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1132 {1, (CHIP_IS_E3B0(bp)) ?
1133 PBF_REG_INIT_CRD_Q1 :
1134 PBF_REG_P1_INIT_CRD,
1135 (CHIP_IS_E3B0(bp)) ?
1136 PBF_REG_CREDIT_Q1 :
1137 PBF_REG_P1_CREDIT,
1138 (CHIP_IS_E3B0(bp)) ?
1139 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1140 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1141 {4, (CHIP_IS_E3B0(bp)) ?
1142 PBF_REG_INIT_CRD_LB_Q :
1143 PBF_REG_P4_INIT_CRD,
1144 (CHIP_IS_E3B0(bp)) ?
1145 PBF_REG_CREDIT_LB_Q :
1146 PBF_REG_P4_CREDIT,
1147 (CHIP_IS_E3B0(bp)) ?
1148 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1149 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1150 };
1151
1152 int i;
1153
1154 /* Verify the command queues are flushed P0, P1, P4 */
1155 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1156 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1157
1158
1159 /* Verify the transmission buffers are flushed P0, P1, P4 */
1160 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1161 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1162 }
1163
1164 #define OP_GEN_PARAM(param) \
1165 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1166
1167 #define OP_GEN_TYPE(type) \
1168 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1169
1170 #define OP_GEN_AGG_VECT(index) \
1171 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1172
1173
1174 static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1175 u32 poll_cnt)
1176 {
1177 struct sdm_op_gen op_gen = {0};
1178
1179 u32 comp_addr = BAR_CSTRORM_INTMEM +
1180 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1181 int ret = 0;
1182
1183 if (REG_RD(bp, comp_addr)) {
1184 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1185 return 1;
1186 }
1187
1188 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1189 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1190 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1191 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1192
1193 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1194 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1195
1196 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1197 BNX2X_ERR("FW final cleanup did not succeed\n");
1198 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1199 (REG_RD(bp, comp_addr)));
1200 ret = 1;
1201 }
1202 /* Zero completion for nxt FLR */
1203 REG_WR(bp, comp_addr, 0);
1204
1205 return ret;
1206 }
1207
1208 static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1209 {
1210 int pos;
1211 u16 status;
1212
1213 pos = pci_pcie_cap(dev);
1214 if (!pos)
1215 return false;
1216
1217 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1218 return status & PCI_EXP_DEVSTA_TRPND;
1219 }
1220
1221 /* PF FLR specific routines
1222 */
1223 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1224 {
1225
1226 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1227 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1228 CFC_REG_NUM_LCIDS_INSIDE_PF,
1229 "CFC PF usage counter timed out",
1230 poll_cnt))
1231 return 1;
1232
1233
1234 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1235 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1236 DORQ_REG_PF_USAGE_CNT,
1237 "DQ PF usage counter timed out",
1238 poll_cnt))
1239 return 1;
1240
1241 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1242 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1243 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1244 "QM PF usage counter timed out",
1245 poll_cnt))
1246 return 1;
1247
1248 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1249 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1250 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1251 "Timers VNIC usage counter timed out",
1252 poll_cnt))
1253 return 1;
1254 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1255 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1256 "Timers NUM_SCANS usage counter timed out",
1257 poll_cnt))
1258 return 1;
1259
1260 /* Wait DMAE PF usage counter to zero */
1261 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1262 dmae_reg_go_c[INIT_DMAE_C(bp)],
1263 "DMAE dommand register timed out",
1264 poll_cnt))
1265 return 1;
1266
1267 return 0;
1268 }
1269
1270 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1271 {
1272 u32 val;
1273
1274 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1275 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1276
1277 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1278 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1279
1280 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1281 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1282
1283 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1284 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1285
1286 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1287 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1288
1289 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1290 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1291
1292 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1293 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1294
1295 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1296 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1297 val);
1298 }
1299
1300 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1301 {
1302 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1303
1304 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1305
1306 /* Re-enable PF target read access */
1307 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1308
1309 /* Poll HW usage counters */
1310 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1311 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1312 return -EBUSY;
1313
1314 /* Zero the igu 'trailing edge' and 'leading edge' */
1315
1316 /* Send the FW cleanup command */
1317 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1318 return -EBUSY;
1319
1320 /* ATC cleanup */
1321
1322 /* Verify TX hw is flushed */
1323 bnx2x_tx_hw_flushed(bp, poll_cnt);
1324
1325 /* Wait 100ms (not adjusted according to platform) */
1326 msleep(100);
1327
1328 /* Verify no pending pci transactions */
1329 if (bnx2x_is_pcie_pending(bp->pdev))
1330 BNX2X_ERR("PCIE Transactions still pending\n");
1331
1332 /* Debug */
1333 bnx2x_hw_enable_status(bp);
1334
1335 /*
1336 * Master enable - Due to WB DMAE writes performed before this
1337 * register is re-initialized as part of the regular function init
1338 */
1339 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1340
1341 return 0;
1342 }
1343
1344 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1345 {
1346 int port = BP_PORT(bp);
1347 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1348 u32 val = REG_RD(bp, addr);
1349 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1350 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1351
1352 if (msix) {
1353 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1354 HC_CONFIG_0_REG_INT_LINE_EN_0);
1355 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1356 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1357 } else if (msi) {
1358 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1359 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1360 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1361 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1362 } else {
1363 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1364 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1365 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1366 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1367
1368 if (!CHIP_IS_E1(bp)) {
1369 DP(NETIF_MSG_IFUP,
1370 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1371
1372 REG_WR(bp, addr, val);
1373
1374 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1375 }
1376 }
1377
1378 if (CHIP_IS_E1(bp))
1379 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1380
1381 DP(NETIF_MSG_IFUP,
1382 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1383 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1384
1385 REG_WR(bp, addr, val);
1386 /*
1387 * Ensure that HC_CONFIG is written before leading/trailing edge config
1388 */
1389 mmiowb();
1390 barrier();
1391
1392 if (!CHIP_IS_E1(bp)) {
1393 /* init leading/trailing edge */
1394 if (IS_MF(bp)) {
1395 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1396 if (bp->port.pmf)
1397 /* enable nig and gpio3 attention */
1398 val |= 0x1100;
1399 } else
1400 val = 0xffff;
1401
1402 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1403 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1404 }
1405
1406 /* Make sure that interrupts are indeed enabled from here on */
1407 mmiowb();
1408 }
1409
1410 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1411 {
1412 u32 val;
1413 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1414 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1415
1416 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1417
1418 if (msix) {
1419 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1420 IGU_PF_CONF_SINGLE_ISR_EN);
1421 val |= (IGU_PF_CONF_FUNC_EN |
1422 IGU_PF_CONF_MSI_MSIX_EN |
1423 IGU_PF_CONF_ATTN_BIT_EN);
1424 } else if (msi) {
1425 val &= ~IGU_PF_CONF_INT_LINE_EN;
1426 val |= (IGU_PF_CONF_FUNC_EN |
1427 IGU_PF_CONF_MSI_MSIX_EN |
1428 IGU_PF_CONF_ATTN_BIT_EN |
1429 IGU_PF_CONF_SINGLE_ISR_EN);
1430 } else {
1431 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1432 val |= (IGU_PF_CONF_FUNC_EN |
1433 IGU_PF_CONF_INT_LINE_EN |
1434 IGU_PF_CONF_ATTN_BIT_EN |
1435 IGU_PF_CONF_SINGLE_ISR_EN);
1436 }
1437
1438 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1439 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1440
1441 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1442
1443 barrier();
1444
1445 /* init leading/trailing edge */
1446 if (IS_MF(bp)) {
1447 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1448 if (bp->port.pmf)
1449 /* enable nig and gpio3 attention */
1450 val |= 0x1100;
1451 } else
1452 val = 0xffff;
1453
1454 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1455 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1456
1457 /* Make sure that interrupts are indeed enabled from here on */
1458 mmiowb();
1459 }
1460
1461 void bnx2x_int_enable(struct bnx2x *bp)
1462 {
1463 if (bp->common.int_block == INT_BLOCK_HC)
1464 bnx2x_hc_int_enable(bp);
1465 else
1466 bnx2x_igu_int_enable(bp);
1467 }
1468
1469 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1470 {
1471 int port = BP_PORT(bp);
1472 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1473 u32 val = REG_RD(bp, addr);
1474
1475 /*
1476 * in E1 we must use only PCI configuration space to disable
1477 * MSI/MSIX capablility
1478 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1479 */
1480 if (CHIP_IS_E1(bp)) {
1481 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1482 * Use mask register to prevent from HC sending interrupts
1483 * after we exit the function
1484 */
1485 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1486
1487 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1488 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1489 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1490 } else
1491 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1492 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1493 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1494 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1495
1496 DP(NETIF_MSG_IFDOWN,
1497 "write %x to HC %d (addr 0x%x)\n",
1498 val, port, addr);
1499
1500 /* flush all outstanding writes */
1501 mmiowb();
1502
1503 REG_WR(bp, addr, val);
1504 if (REG_RD(bp, addr) != val)
1505 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1506 }
1507
1508 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1509 {
1510 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1511
1512 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1513 IGU_PF_CONF_INT_LINE_EN |
1514 IGU_PF_CONF_ATTN_BIT_EN);
1515
1516 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
1517
1518 /* flush all outstanding writes */
1519 mmiowb();
1520
1521 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1522 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1523 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1524 }
1525
1526 void bnx2x_int_disable(struct bnx2x *bp)
1527 {
1528 if (bp->common.int_block == INT_BLOCK_HC)
1529 bnx2x_hc_int_disable(bp);
1530 else
1531 bnx2x_igu_int_disable(bp);
1532 }
1533
1534 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1535 {
1536 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1537 int i, offset;
1538
1539 if (disable_hw)
1540 /* prevent the HW from sending interrupts */
1541 bnx2x_int_disable(bp);
1542
1543 /* make sure all ISRs are done */
1544 if (msix) {
1545 synchronize_irq(bp->msix_table[0].vector);
1546 offset = 1;
1547 #ifdef BCM_CNIC
1548 offset++;
1549 #endif
1550 for_each_eth_queue(bp, i)
1551 synchronize_irq(bp->msix_table[offset++].vector);
1552 } else
1553 synchronize_irq(bp->pdev->irq);
1554
1555 /* make sure sp_task is not running */
1556 cancel_delayed_work(&bp->sp_task);
1557 cancel_delayed_work(&bp->period_task);
1558 flush_workqueue(bnx2x_wq);
1559 }
1560
1561 /* fast path */
1562
1563 /*
1564 * General service functions
1565 */
1566
1567 /* Return true if succeeded to acquire the lock */
1568 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1569 {
1570 u32 lock_status;
1571 u32 resource_bit = (1 << resource);
1572 int func = BP_FUNC(bp);
1573 u32 hw_lock_control_reg;
1574
1575 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1576 "Trying to take a lock on resource %d\n", resource);
1577
1578 /* Validating that the resource is within range */
1579 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1580 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1581 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1582 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1583 return false;
1584 }
1585
1586 if (func <= 5)
1587 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1588 else
1589 hw_lock_control_reg =
1590 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1591
1592 /* Try to acquire the lock */
1593 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1594 lock_status = REG_RD(bp, hw_lock_control_reg);
1595 if (lock_status & resource_bit)
1596 return true;
1597
1598 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1599 "Failed to get a lock on resource %d\n", resource);
1600 return false;
1601 }
1602
1603 /**
1604 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1605 *
1606 * @bp: driver handle
1607 *
1608 * Returns the recovery leader resource id according to the engine this function
1609 * belongs to. Currently only only 2 engines is supported.
1610 */
1611 static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1612 {
1613 if (BP_PATH(bp))
1614 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1615 else
1616 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1617 }
1618
1619 /**
1620 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1621 *
1622 * @bp: driver handle
1623 *
1624 * Tries to aquire a leader lock for cuurent engine.
1625 */
1626 static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1627 {
1628 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1629 }
1630
1631 #ifdef BCM_CNIC
1632 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1633 #endif
1634
1635 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1636 {
1637 struct bnx2x *bp = fp->bp;
1638 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1639 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1640 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1641 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
1642
1643 DP(BNX2X_MSG_SP,
1644 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1645 fp->index, cid, command, bp->state,
1646 rr_cqe->ramrod_cqe.ramrod_type);
1647
1648 switch (command) {
1649 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1650 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1651 drv_cmd = BNX2X_Q_CMD_UPDATE;
1652 break;
1653
1654 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1655 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1656 drv_cmd = BNX2X_Q_CMD_SETUP;
1657 break;
1658
1659 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1660 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1661 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1662 break;
1663
1664 case (RAMROD_CMD_ID_ETH_HALT):
1665 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1666 drv_cmd = BNX2X_Q_CMD_HALT;
1667 break;
1668
1669 case (RAMROD_CMD_ID_ETH_TERMINATE):
1670 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1671 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1672 break;
1673
1674 case (RAMROD_CMD_ID_ETH_EMPTY):
1675 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1676 drv_cmd = BNX2X_Q_CMD_EMPTY;
1677 break;
1678
1679 default:
1680 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1681 command, fp->index);
1682 return;
1683 }
1684
1685 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1686 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1687 /* q_obj->complete_cmd() failure means that this was
1688 * an unexpected completion.
1689 *
1690 * In this case we don't want to increase the bp->spq_left
1691 * because apparently we haven't sent this command the first
1692 * place.
1693 */
1694 #ifdef BNX2X_STOP_ON_ERROR
1695 bnx2x_panic();
1696 #else
1697 return;
1698 #endif
1699
1700 smp_mb__before_atomic_inc();
1701 atomic_inc(&bp->cq_spq_left);
1702 /* push the change in bp->spq_left and towards the memory */
1703 smp_mb__after_atomic_inc();
1704
1705 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1706
1707 return;
1708 }
1709
1710 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1711 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1712 {
1713 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1714
1715 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1716 start);
1717 }
1718
1719 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1720 {
1721 struct bnx2x *bp = netdev_priv(dev_instance);
1722 u16 status = bnx2x_ack_int(bp);
1723 u16 mask;
1724 int i;
1725 u8 cos;
1726
1727 /* Return here if interrupt is shared and it's not for us */
1728 if (unlikely(status == 0)) {
1729 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1730 return IRQ_NONE;
1731 }
1732 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1733
1734 #ifdef BNX2X_STOP_ON_ERROR
1735 if (unlikely(bp->panic))
1736 return IRQ_HANDLED;
1737 #endif
1738
1739 for_each_eth_queue(bp, i) {
1740 struct bnx2x_fastpath *fp = &bp->fp[i];
1741
1742 mask = 0x2 << (fp->index + CNIC_PRESENT);
1743 if (status & mask) {
1744 /* Handle Rx or Tx according to SB id */
1745 prefetch(fp->rx_cons_sb);
1746 for_each_cos_in_tx_queue(fp, cos)
1747 prefetch(fp->txdata[cos].tx_cons_sb);
1748 prefetch(&fp->sb_running_index[SM_RX_ID]);
1749 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1750 status &= ~mask;
1751 }
1752 }
1753
1754 #ifdef BCM_CNIC
1755 mask = 0x2;
1756 if (status & (mask | 0x1)) {
1757 struct cnic_ops *c_ops = NULL;
1758
1759 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1760 rcu_read_lock();
1761 c_ops = rcu_dereference(bp->cnic_ops);
1762 if (c_ops)
1763 c_ops->cnic_handler(bp->cnic_data, NULL);
1764 rcu_read_unlock();
1765 }
1766
1767 status &= ~mask;
1768 }
1769 #endif
1770
1771 if (unlikely(status & 0x1)) {
1772 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1773
1774 status &= ~0x1;
1775 if (!status)
1776 return IRQ_HANDLED;
1777 }
1778
1779 if (unlikely(status))
1780 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1781 status);
1782
1783 return IRQ_HANDLED;
1784 }
1785
1786 /* Link */
1787
1788 /*
1789 * General service functions
1790 */
1791
1792 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1793 {
1794 u32 lock_status;
1795 u32 resource_bit = (1 << resource);
1796 int func = BP_FUNC(bp);
1797 u32 hw_lock_control_reg;
1798 int cnt;
1799
1800 /* Validating that the resource is within range */
1801 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1802 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1803 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1804 return -EINVAL;
1805 }
1806
1807 if (func <= 5) {
1808 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1809 } else {
1810 hw_lock_control_reg =
1811 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1812 }
1813
1814 /* Validating that the resource is not already taken */
1815 lock_status = REG_RD(bp, hw_lock_control_reg);
1816 if (lock_status & resource_bit) {
1817 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1818 lock_status, resource_bit);
1819 return -EEXIST;
1820 }
1821
1822 /* Try for 5 second every 5ms */
1823 for (cnt = 0; cnt < 1000; cnt++) {
1824 /* Try to acquire the lock */
1825 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1826 lock_status = REG_RD(bp, hw_lock_control_reg);
1827 if (lock_status & resource_bit)
1828 return 0;
1829
1830 msleep(5);
1831 }
1832 BNX2X_ERR("Timeout\n");
1833 return -EAGAIN;
1834 }
1835
1836 int bnx2x_release_leader_lock(struct bnx2x *bp)
1837 {
1838 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1839 }
1840
1841 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1842 {
1843 u32 lock_status;
1844 u32 resource_bit = (1 << resource);
1845 int func = BP_FUNC(bp);
1846 u32 hw_lock_control_reg;
1847
1848 /* Validating that the resource is within range */
1849 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1850 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1851 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1852 return -EINVAL;
1853 }
1854
1855 if (func <= 5) {
1856 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1857 } else {
1858 hw_lock_control_reg =
1859 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1860 }
1861
1862 /* Validating that the resource is currently taken */
1863 lock_status = REG_RD(bp, hw_lock_control_reg);
1864 if (!(lock_status & resource_bit)) {
1865 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1866 lock_status, resource_bit);
1867 return -EFAULT;
1868 }
1869
1870 REG_WR(bp, hw_lock_control_reg, resource_bit);
1871 return 0;
1872 }
1873
1874
1875 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1876 {
1877 /* The GPIO should be swapped if swap register is set and active */
1878 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1879 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1880 int gpio_shift = gpio_num +
1881 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1882 u32 gpio_mask = (1 << gpio_shift);
1883 u32 gpio_reg;
1884 int value;
1885
1886 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1887 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1888 return -EINVAL;
1889 }
1890
1891 /* read GPIO value */
1892 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1893
1894 /* get the requested pin value */
1895 if ((gpio_reg & gpio_mask) == gpio_mask)
1896 value = 1;
1897 else
1898 value = 0;
1899
1900 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1901
1902 return value;
1903 }
1904
1905 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1906 {
1907 /* The GPIO should be swapped if swap register is set and active */
1908 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1909 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1910 int gpio_shift = gpio_num +
1911 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1912 u32 gpio_mask = (1 << gpio_shift);
1913 u32 gpio_reg;
1914
1915 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1916 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1917 return -EINVAL;
1918 }
1919
1920 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1921 /* read GPIO and mask except the float bits */
1922 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1923
1924 switch (mode) {
1925 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1926 DP(NETIF_MSG_LINK,
1927 "Set GPIO %d (shift %d) -> output low\n",
1928 gpio_num, gpio_shift);
1929 /* clear FLOAT and set CLR */
1930 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1931 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1932 break;
1933
1934 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1935 DP(NETIF_MSG_LINK,
1936 "Set GPIO %d (shift %d) -> output high\n",
1937 gpio_num, gpio_shift);
1938 /* clear FLOAT and set SET */
1939 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1940 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1941 break;
1942
1943 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1944 DP(NETIF_MSG_LINK,
1945 "Set GPIO %d (shift %d) -> input\n",
1946 gpio_num, gpio_shift);
1947 /* set FLOAT */
1948 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1949 break;
1950
1951 default:
1952 break;
1953 }
1954
1955 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1956 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1957
1958 return 0;
1959 }
1960
1961 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1962 {
1963 u32 gpio_reg = 0;
1964 int rc = 0;
1965
1966 /* Any port swapping should be handled by caller. */
1967
1968 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1969 /* read GPIO and mask except the float bits */
1970 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1971 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1972 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1973 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1974
1975 switch (mode) {
1976 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1977 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
1978 /* set CLR */
1979 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
1980 break;
1981
1982 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1983 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
1984 /* set SET */
1985 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
1986 break;
1987
1988 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1989 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
1990 /* set FLOAT */
1991 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1992 break;
1993
1994 default:
1995 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
1996 rc = -EINVAL;
1997 break;
1998 }
1999
2000 if (rc == 0)
2001 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2002
2003 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2004
2005 return rc;
2006 }
2007
2008 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2009 {
2010 /* The GPIO should be swapped if swap register is set and active */
2011 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2012 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2013 int gpio_shift = gpio_num +
2014 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2015 u32 gpio_mask = (1 << gpio_shift);
2016 u32 gpio_reg;
2017
2018 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2019 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2020 return -EINVAL;
2021 }
2022
2023 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2024 /* read GPIO int */
2025 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2026
2027 switch (mode) {
2028 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2029 DP(NETIF_MSG_LINK,
2030 "Clear GPIO INT %d (shift %d) -> output low\n",
2031 gpio_num, gpio_shift);
2032 /* clear SET and set CLR */
2033 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2034 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2035 break;
2036
2037 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2038 DP(NETIF_MSG_LINK,
2039 "Set GPIO INT %d (shift %d) -> output high\n",
2040 gpio_num, gpio_shift);
2041 /* clear CLR and set SET */
2042 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2043 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2044 break;
2045
2046 default:
2047 break;
2048 }
2049
2050 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2051 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2052
2053 return 0;
2054 }
2055
2056 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2057 {
2058 u32 spio_mask = (1 << spio_num);
2059 u32 spio_reg;
2060
2061 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2062 (spio_num > MISC_REGISTERS_SPIO_7)) {
2063 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2064 return -EINVAL;
2065 }
2066
2067 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2068 /* read SPIO and mask except the float bits */
2069 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2070
2071 switch (mode) {
2072 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2073 DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num);
2074 /* clear FLOAT and set CLR */
2075 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2076 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2077 break;
2078
2079 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2080 DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num);
2081 /* clear FLOAT and set SET */
2082 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2083 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2084 break;
2085
2086 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2087 DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num);
2088 /* set FLOAT */
2089 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2090 break;
2091
2092 default:
2093 break;
2094 }
2095
2096 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2097 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2098
2099 return 0;
2100 }
2101
2102 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2103 {
2104 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2105 switch (bp->link_vars.ieee_fc &
2106 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2107 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2108 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2109 ADVERTISED_Pause);
2110 break;
2111
2112 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2113 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2114 ADVERTISED_Pause);
2115 break;
2116
2117 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2118 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2119 break;
2120
2121 default:
2122 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2123 ADVERTISED_Pause);
2124 break;
2125 }
2126 }
2127
2128 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2129 {
2130 if (!BP_NOMCP(bp)) {
2131 u8 rc;
2132 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2133 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2134 /*
2135 * Initialize link parameters structure variables
2136 * It is recommended to turn off RX FC for jumbo frames
2137 * for better performance
2138 */
2139 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2140 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2141 else
2142 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2143
2144 bnx2x_acquire_phy_lock(bp);
2145
2146 if (load_mode == LOAD_DIAG) {
2147 struct link_params *lp = &bp->link_params;
2148 lp->loopback_mode = LOOPBACK_XGXS;
2149 /* do PHY loopback at 10G speed, if possible */
2150 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2151 if (lp->speed_cap_mask[cfx_idx] &
2152 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2153 lp->req_line_speed[cfx_idx] =
2154 SPEED_10000;
2155 else
2156 lp->req_line_speed[cfx_idx] =
2157 SPEED_1000;
2158 }
2159 }
2160
2161 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2162
2163 bnx2x_release_phy_lock(bp);
2164
2165 bnx2x_calc_fc_adv(bp);
2166
2167 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2168 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2169 bnx2x_link_report(bp);
2170 } else
2171 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2172 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2173 return rc;
2174 }
2175 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2176 return -EINVAL;
2177 }
2178
2179 void bnx2x_link_set(struct bnx2x *bp)
2180 {
2181 if (!BP_NOMCP(bp)) {
2182 bnx2x_acquire_phy_lock(bp);
2183 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2184 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2185 bnx2x_release_phy_lock(bp);
2186
2187 bnx2x_calc_fc_adv(bp);
2188 } else
2189 BNX2X_ERR("Bootcode is missing - can not set link\n");
2190 }
2191
2192 static void bnx2x__link_reset(struct bnx2x *bp)
2193 {
2194 if (!BP_NOMCP(bp)) {
2195 bnx2x_acquire_phy_lock(bp);
2196 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2197 bnx2x_release_phy_lock(bp);
2198 } else
2199 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2200 }
2201
2202 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2203 {
2204 u8 rc = 0;
2205
2206 if (!BP_NOMCP(bp)) {
2207 bnx2x_acquire_phy_lock(bp);
2208 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2209 is_serdes);
2210 bnx2x_release_phy_lock(bp);
2211 } else
2212 BNX2X_ERR("Bootcode is missing - can not test link\n");
2213
2214 return rc;
2215 }
2216
2217 static void bnx2x_init_port_minmax(struct bnx2x *bp)
2218 {
2219 u32 r_param = bp->link_vars.line_speed / 8;
2220 u32 fair_periodic_timeout_usec;
2221 u32 t_fair;
2222
2223 memset(&(bp->cmng.rs_vars), 0,
2224 sizeof(struct rate_shaping_vars_per_port));
2225 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2226
2227 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2228 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2229
2230 /* this is the threshold below which no timer arming will occur
2231 1.25 coefficient is for the threshold to be a little bigger
2232 than the real time, to compensate for timer in-accuracy */
2233 bp->cmng.rs_vars.rs_threshold =
2234 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2235
2236 /* resolution of fairness timer */
2237 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2238 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2239 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2240
2241 /* this is the threshold below which we won't arm the timer anymore */
2242 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2243
2244 /* we multiply by 1e3/8 to get bytes/msec.
2245 We don't want the credits to pass a credit
2246 of the t_fair*FAIR_MEM (algorithm resolution) */
2247 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2248 /* since each tick is 4 usec */
2249 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2250 }
2251
2252 /* Calculates the sum of vn_min_rates.
2253 It's needed for further normalizing of the min_rates.
2254 Returns:
2255 sum of vn_min_rates.
2256 or
2257 0 - if all the min_rates are 0.
2258 In the later case fainess algorithm should be deactivated.
2259 If not all min_rates are zero then those that are zeroes will be set to 1.
2260 */
2261 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2262 {
2263 int all_zero = 1;
2264 int vn;
2265
2266 bp->vn_weight_sum = 0;
2267 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2268 u32 vn_cfg = bp->mf_config[vn];
2269 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2270 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2271
2272 /* Skip hidden vns */
2273 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2274 continue;
2275
2276 /* If min rate is zero - set it to 1 */
2277 if (!vn_min_rate)
2278 vn_min_rate = DEF_MIN_RATE;
2279 else
2280 all_zero = 0;
2281
2282 bp->vn_weight_sum += vn_min_rate;
2283 }
2284
2285 /* if ETS or all min rates are zeros - disable fairness */
2286 if (BNX2X_IS_ETS_ENABLED(bp)) {
2287 bp->cmng.flags.cmng_enables &=
2288 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2289 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2290 } else if (all_zero) {
2291 bp->cmng.flags.cmng_enables &=
2292 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2293 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2294 " fairness will be disabled\n");
2295 } else
2296 bp->cmng.flags.cmng_enables |=
2297 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2298 }
2299
2300 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
2301 {
2302 struct rate_shaping_vars_per_vn m_rs_vn;
2303 struct fairness_vars_per_vn m_fair_vn;
2304 u32 vn_cfg = bp->mf_config[vn];
2305 int func = func_by_vn(bp, vn);
2306 u16 vn_min_rate, vn_max_rate;
2307 int i;
2308
2309 /* If function is hidden - set min and max to zeroes */
2310 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2311 vn_min_rate = 0;
2312 vn_max_rate = 0;
2313
2314 } else {
2315 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2316
2317 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2318 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2319 /* If fairness is enabled (not all min rates are zeroes) and
2320 if current min rate is zero - set it to 1.
2321 This is a requirement of the algorithm. */
2322 if (bp->vn_weight_sum && (vn_min_rate == 0))
2323 vn_min_rate = DEF_MIN_RATE;
2324
2325 if (IS_MF_SI(bp))
2326 /* maxCfg in percents of linkspeed */
2327 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2328 else
2329 /* maxCfg is absolute in 100Mb units */
2330 vn_max_rate = maxCfg * 100;
2331 }
2332
2333 DP(NETIF_MSG_IFUP,
2334 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2335 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2336
2337 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2338 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2339
2340 /* global vn counter - maximal Mbps for this vn */
2341 m_rs_vn.vn_counter.rate = vn_max_rate;
2342
2343 /* quota - number of bytes transmitted in this period */
2344 m_rs_vn.vn_counter.quota =
2345 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2346
2347 if (bp->vn_weight_sum) {
2348 /* credit for each period of the fairness algorithm:
2349 number of bytes in T_FAIR (the vn share the port rate).
2350 vn_weight_sum should not be larger than 10000, thus
2351 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2352 than zero */
2353 m_fair_vn.vn_credit_delta =
2354 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2355 (8 * bp->vn_weight_sum))),
2356 (bp->cmng.fair_vars.fair_threshold +
2357 MIN_ABOVE_THRESH));
2358 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2359 m_fair_vn.vn_credit_delta);
2360 }
2361
2362 /* Store it to internal memory */
2363 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2364 REG_WR(bp, BAR_XSTRORM_INTMEM +
2365 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2366 ((u32 *)(&m_rs_vn))[i]);
2367
2368 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2369 REG_WR(bp, BAR_XSTRORM_INTMEM +
2370 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2371 ((u32 *)(&m_fair_vn))[i]);
2372 }
2373
2374 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2375 {
2376 if (CHIP_REV_IS_SLOW(bp))
2377 return CMNG_FNS_NONE;
2378 if (IS_MF(bp))
2379 return CMNG_FNS_MINMAX;
2380
2381 return CMNG_FNS_NONE;
2382 }
2383
2384 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2385 {
2386 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2387
2388 if (BP_NOMCP(bp))
2389 return; /* what should be the default bvalue in this case */
2390
2391 /* For 2 port configuration the absolute function number formula
2392 * is:
2393 * abs_func = 2 * vn + BP_PORT + BP_PATH
2394 *
2395 * and there are 4 functions per port
2396 *
2397 * For 4 port configuration it is
2398 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2399 *
2400 * and there are 2 functions per port
2401 */
2402 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2403 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2404
2405 if (func >= E1H_FUNC_MAX)
2406 break;
2407
2408 bp->mf_config[vn] =
2409 MF_CFG_RD(bp, func_mf_config[func].config);
2410 }
2411 }
2412
2413 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2414 {
2415
2416 if (cmng_type == CMNG_FNS_MINMAX) {
2417 int vn;
2418
2419 /* clear cmng_enables */
2420 bp->cmng.flags.cmng_enables = 0;
2421
2422 /* read mf conf from shmem */
2423 if (read_cfg)
2424 bnx2x_read_mf_cfg(bp);
2425
2426 /* Init rate shaping and fairness contexts */
2427 bnx2x_init_port_minmax(bp);
2428
2429 /* vn_weight_sum and enable fairness if not 0 */
2430 bnx2x_calc_vn_weight_sum(bp);
2431
2432 /* calculate and set min-max rate for each vn */
2433 if (bp->port.pmf)
2434 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2435 bnx2x_init_vn_minmax(bp, vn);
2436
2437 /* always enable rate shaping and fairness */
2438 bp->cmng.flags.cmng_enables |=
2439 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2440 if (!bp->vn_weight_sum)
2441 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2442 " fairness will be disabled\n");
2443 return;
2444 }
2445
2446 /* rate shaping and fairness are disabled */
2447 DP(NETIF_MSG_IFUP,
2448 "rate shaping and fairness are disabled\n");
2449 }
2450
2451 /* This function is called upon link interrupt */
2452 static void bnx2x_link_attn(struct bnx2x *bp)
2453 {
2454 /* Make sure that we are synced with the current statistics */
2455 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2456
2457 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2458
2459 if (bp->link_vars.link_up) {
2460
2461 /* dropless flow control */
2462 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2463 int port = BP_PORT(bp);
2464 u32 pause_enabled = 0;
2465
2466 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2467 pause_enabled = 1;
2468
2469 REG_WR(bp, BAR_USTRORM_INTMEM +
2470 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2471 pause_enabled);
2472 }
2473
2474 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2475 struct host_port_stats *pstats;
2476
2477 pstats = bnx2x_sp(bp, port_stats);
2478 /* reset old mac stats */
2479 memset(&(pstats->mac_stx[0]), 0,
2480 sizeof(struct mac_stx));
2481 }
2482 if (bp->state == BNX2X_STATE_OPEN)
2483 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2484 }
2485
2486 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2487 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2488
2489 if (cmng_fns != CMNG_FNS_NONE) {
2490 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2491 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2492 } else
2493 /* rate shaping and fairness are disabled */
2494 DP(NETIF_MSG_IFUP,
2495 "single function mode without fairness\n");
2496 }
2497
2498 __bnx2x_link_report(bp);
2499
2500 if (IS_MF(bp))
2501 bnx2x_link_sync_notify(bp);
2502 }
2503
2504 void bnx2x__link_status_update(struct bnx2x *bp)
2505 {
2506 if (bp->state != BNX2X_STATE_OPEN)
2507 return;
2508
2509 /* read updated dcb configuration */
2510 bnx2x_dcbx_pmf_update(bp);
2511
2512 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2513
2514 if (bp->link_vars.link_up)
2515 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2516 else
2517 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2518
2519 /* indicate link status */
2520 bnx2x_link_report(bp);
2521 }
2522
2523 static void bnx2x_pmf_update(struct bnx2x *bp)
2524 {
2525 int port = BP_PORT(bp);
2526 u32 val;
2527
2528 bp->port.pmf = 1;
2529 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2530
2531 /*
2532 * We need the mb() to ensure the ordering between the writing to
2533 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2534 */
2535 smp_mb();
2536
2537 /* queue a periodic task */
2538 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2539
2540 bnx2x_dcbx_pmf_update(bp);
2541
2542 /* enable nig attention */
2543 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2544 if (bp->common.int_block == INT_BLOCK_HC) {
2545 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2546 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2547 } else if (!CHIP_IS_E1x(bp)) {
2548 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2549 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2550 }
2551
2552 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2553 }
2554
2555 /* end of Link */
2556
2557 /* slow path */
2558
2559 /*
2560 * General service functions
2561 */
2562
2563 /* send the MCP a request, block until there is a reply */
2564 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2565 {
2566 int mb_idx = BP_FW_MB_IDX(bp);
2567 u32 seq;
2568 u32 rc = 0;
2569 u32 cnt = 1;
2570 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2571
2572 mutex_lock(&bp->fw_mb_mutex);
2573 seq = ++bp->fw_seq;
2574 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2575 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2576
2577 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2578 (command | seq), param);
2579
2580 do {
2581 /* let the FW do it's magic ... */
2582 msleep(delay);
2583
2584 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2585
2586 /* Give the FW up to 5 second (500*10ms) */
2587 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2588
2589 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2590 cnt*delay, rc, seq);
2591
2592 /* is this a reply to our command? */
2593 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2594 rc &= FW_MSG_CODE_MASK;
2595 else {
2596 /* FW BUG! */
2597 BNX2X_ERR("FW failed to respond!\n");
2598 bnx2x_fw_dump(bp);
2599 rc = 0;
2600 }
2601 mutex_unlock(&bp->fw_mb_mutex);
2602
2603 return rc;
2604 }
2605
2606
2607 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2608 {
2609 if (CHIP_IS_E1x(bp)) {
2610 struct tstorm_eth_function_common_config tcfg = {0};
2611
2612 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2613 }
2614
2615 /* Enable the function in the FW */
2616 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2617 storm_memset_func_en(bp, p->func_id, 1);
2618
2619 /* spq */
2620 if (p->func_flgs & FUNC_FLG_SPQ) {
2621 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2622 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2623 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2624 }
2625 }
2626
2627 /**
2628 * bnx2x_get_tx_only_flags - Return common flags
2629 *
2630 * @bp device handle
2631 * @fp queue handle
2632 * @zero_stats TRUE if statistics zeroing is needed
2633 *
2634 * Return the flags that are common for the Tx-only and not normal connections.
2635 */
2636 static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2637 struct bnx2x_fastpath *fp,
2638 bool zero_stats)
2639 {
2640 unsigned long flags = 0;
2641
2642 /* PF driver will always initialize the Queue to an ACTIVE state */
2643 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2644
2645 /* tx only connections collect statistics (on the same index as the
2646 * parent connection). The statistics are zeroed when the parent
2647 * connection is initialized.
2648 */
2649
2650 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2651 if (zero_stats)
2652 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2653
2654
2655 return flags;
2656 }
2657
2658 static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2659 struct bnx2x_fastpath *fp,
2660 bool leading)
2661 {
2662 unsigned long flags = 0;
2663
2664 /* calculate other queue flags */
2665 if (IS_MF_SD(bp))
2666 __set_bit(BNX2X_Q_FLG_OV, &flags);
2667
2668 if (IS_FCOE_FP(fp))
2669 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2670
2671 if (!fp->disable_tpa) {
2672 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2673 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2674 if (fp->mode == TPA_MODE_GRO)
2675 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2676 }
2677
2678 if (leading) {
2679 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2680 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2681 }
2682
2683 /* Always set HW VLAN stripping */
2684 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2685
2686
2687 return flags | bnx2x_get_common_flags(bp, fp, true);
2688 }
2689
2690 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2691 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2692 u8 cos)
2693 {
2694 gen_init->stat_id = bnx2x_stats_id(fp);
2695 gen_init->spcl_id = fp->cl_id;
2696
2697 /* Always use mini-jumbo MTU for FCoE L2 ring */
2698 if (IS_FCOE_FP(fp))
2699 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2700 else
2701 gen_init->mtu = bp->dev->mtu;
2702
2703 gen_init->cos = cos;
2704 }
2705
2706 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2707 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2708 struct bnx2x_rxq_setup_params *rxq_init)
2709 {
2710 u8 max_sge = 0;
2711 u16 sge_sz = 0;
2712 u16 tpa_agg_size = 0;
2713
2714 if (!fp->disable_tpa) {
2715 pause->sge_th_lo = SGE_TH_LO(bp);
2716 pause->sge_th_hi = SGE_TH_HI(bp);
2717
2718 /* validate SGE ring has enough to cross high threshold */
2719 WARN_ON(bp->dropless_fc &&
2720 pause->sge_th_hi + FW_PREFETCH_CNT >
2721 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2722
2723 tpa_agg_size = min_t(u32,
2724 (min_t(u32, 8, MAX_SKB_FRAGS) *
2725 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2726 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2727 SGE_PAGE_SHIFT;
2728 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2729 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2730 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2731 0xffff);
2732 }
2733
2734 /* pause - not for e1 */
2735 if (!CHIP_IS_E1(bp)) {
2736 pause->bd_th_lo = BD_TH_LO(bp);
2737 pause->bd_th_hi = BD_TH_HI(bp);
2738
2739 pause->rcq_th_lo = RCQ_TH_LO(bp);
2740 pause->rcq_th_hi = RCQ_TH_HI(bp);
2741 /*
2742 * validate that rings have enough entries to cross
2743 * high thresholds
2744 */
2745 WARN_ON(bp->dropless_fc &&
2746 pause->bd_th_hi + FW_PREFETCH_CNT >
2747 bp->rx_ring_size);
2748 WARN_ON(bp->dropless_fc &&
2749 pause->rcq_th_hi + FW_PREFETCH_CNT >
2750 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2751
2752 pause->pri_map = 1;
2753 }
2754
2755 /* rxq setup */
2756 rxq_init->dscr_map = fp->rx_desc_mapping;
2757 rxq_init->sge_map = fp->rx_sge_mapping;
2758 rxq_init->rcq_map = fp->rx_comp_mapping;
2759 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2760
2761 /* This should be a maximum number of data bytes that may be
2762 * placed on the BD (not including paddings).
2763 */
2764 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2765 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
2766
2767 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2768 rxq_init->tpa_agg_sz = tpa_agg_size;
2769 rxq_init->sge_buf_sz = sge_sz;
2770 rxq_init->max_sges_pkt = max_sge;
2771 rxq_init->rss_engine_id = BP_FUNC(bp);
2772 rxq_init->mcast_engine_id = BP_FUNC(bp);
2773
2774 /* Maximum number or simultaneous TPA aggregation for this Queue.
2775 *
2776 * For PF Clients it should be the maximum avaliable number.
2777 * VF driver(s) may want to define it to a smaller value.
2778 */
2779 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2780
2781 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2782 rxq_init->fw_sb_id = fp->fw_sb_id;
2783
2784 if (IS_FCOE_FP(fp))
2785 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2786 else
2787 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2788 }
2789
2790 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2791 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2792 u8 cos)
2793 {
2794 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2795 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2796 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2797 txq_init->fw_sb_id = fp->fw_sb_id;
2798
2799 /*
2800 * set the tss leading client id for TX classfication ==
2801 * leading RSS client id
2802 */
2803 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2804
2805 if (IS_FCOE_FP(fp)) {
2806 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2807 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2808 }
2809 }
2810
2811 static void bnx2x_pf_init(struct bnx2x *bp)
2812 {
2813 struct bnx2x_func_init_params func_init = {0};
2814 struct event_ring_data eq_data = { {0} };
2815 u16 flags;
2816
2817 if (!CHIP_IS_E1x(bp)) {
2818 /* reset IGU PF statistics: MSIX + ATTN */
2819 /* PF */
2820 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2821 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2822 (CHIP_MODE_IS_4_PORT(bp) ?
2823 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2824 /* ATTN */
2825 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2826 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2827 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2828 (CHIP_MODE_IS_4_PORT(bp) ?
2829 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2830 }
2831
2832 /* function setup flags */
2833 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2834
2835 /* This flag is relevant for E1x only.
2836 * E2 doesn't have a TPA configuration in a function level.
2837 */
2838 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2839
2840 func_init.func_flgs = flags;
2841 func_init.pf_id = BP_FUNC(bp);
2842 func_init.func_id = BP_FUNC(bp);
2843 func_init.spq_map = bp->spq_mapping;
2844 func_init.spq_prod = bp->spq_prod_idx;
2845
2846 bnx2x_func_init(bp, &func_init);
2847
2848 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2849
2850 /*
2851 * Congestion management values depend on the link rate
2852 * There is no active link so initial link rate is set to 10 Gbps.
2853 * When the link comes up The congestion management values are
2854 * re-calculated according to the actual link rate.
2855 */
2856 bp->link_vars.line_speed = SPEED_10000;
2857 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2858
2859 /* Only the PMF sets the HW */
2860 if (bp->port.pmf)
2861 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2862
2863 /* init Event Queue */
2864 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2865 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2866 eq_data.producer = bp->eq_prod;
2867 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2868 eq_data.sb_id = DEF_SB_ID;
2869 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2870 }
2871
2872
2873 static void bnx2x_e1h_disable(struct bnx2x *bp)
2874 {
2875 int port = BP_PORT(bp);
2876
2877 bnx2x_tx_disable(bp);
2878
2879 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2880 }
2881
2882 static void bnx2x_e1h_enable(struct bnx2x *bp)
2883 {
2884 int port = BP_PORT(bp);
2885
2886 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2887
2888 /* Tx queue should be only reenabled */
2889 netif_tx_wake_all_queues(bp->dev);
2890
2891 /*
2892 * Should not call netif_carrier_on since it will be called if the link
2893 * is up when checking for link state
2894 */
2895 }
2896
2897 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
2898
2899 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
2900 {
2901 struct eth_stats_info *ether_stat =
2902 &bp->slowpath->drv_info_to_mcp.ether_stat;
2903
2904 /* leave last char as NULL */
2905 memcpy(ether_stat->version, DRV_MODULE_VERSION,
2906 ETH_STAT_INFO_VERSION_LEN - 1);
2907
2908 bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj,
2909 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
2910 ether_stat->mac_local);
2911
2912 ether_stat->mtu_size = bp->dev->mtu;
2913
2914 if (bp->dev->features & NETIF_F_RXCSUM)
2915 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
2916 if (bp->dev->features & NETIF_F_TSO)
2917 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
2918 ether_stat->feature_flags |= bp->common.boot_mode;
2919
2920 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
2921
2922 ether_stat->txq_size = bp->tx_ring_size;
2923 ether_stat->rxq_size = bp->rx_ring_size;
2924 }
2925
2926 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
2927 {
2928 #ifdef BCM_CNIC
2929 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
2930 struct fcoe_stats_info *fcoe_stat =
2931 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
2932
2933 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN);
2934
2935 fcoe_stat->qos_priority =
2936 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
2937
2938 /* insert FCoE stats from ramrod response */
2939 if (!NO_FCOE(bp)) {
2940 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
2941 &bp->fw_stats_data->queue_stats[FCOE_IDX].
2942 tstorm_queue_statistics;
2943
2944 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
2945 &bp->fw_stats_data->queue_stats[FCOE_IDX].
2946 xstorm_queue_statistics;
2947
2948 struct fcoe_statistics_params *fw_fcoe_stat =
2949 &bp->fw_stats_data->fcoe;
2950
2951 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
2952 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
2953
2954 ADD_64(fcoe_stat->rx_bytes_hi,
2955 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
2956 fcoe_stat->rx_bytes_lo,
2957 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
2958
2959 ADD_64(fcoe_stat->rx_bytes_hi,
2960 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
2961 fcoe_stat->rx_bytes_lo,
2962 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
2963
2964 ADD_64(fcoe_stat->rx_bytes_hi,
2965 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
2966 fcoe_stat->rx_bytes_lo,
2967 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
2968
2969 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2970 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
2971
2972 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2973 fcoe_q_tstorm_stats->rcv_ucast_pkts);
2974
2975 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2976 fcoe_q_tstorm_stats->rcv_bcast_pkts);
2977
2978 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2979 fcoe_q_tstorm_stats->rcv_mcast_pkts);
2980
2981 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
2982 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
2983
2984 ADD_64(fcoe_stat->tx_bytes_hi,
2985 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
2986 fcoe_stat->tx_bytes_lo,
2987 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
2988
2989 ADD_64(fcoe_stat->tx_bytes_hi,
2990 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
2991 fcoe_stat->tx_bytes_lo,
2992 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
2993
2994 ADD_64(fcoe_stat->tx_bytes_hi,
2995 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
2996 fcoe_stat->tx_bytes_lo,
2997 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
2998
2999 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3000 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3001
3002 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3003 fcoe_q_xstorm_stats->ucast_pkts_sent);
3004
3005 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3006 fcoe_q_xstorm_stats->bcast_pkts_sent);
3007
3008 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3009 fcoe_q_xstorm_stats->mcast_pkts_sent);
3010 }
3011
3012 /* ask L5 driver to add data to the struct */
3013 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3014 #endif
3015 }
3016
3017 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3018 {
3019 #ifdef BCM_CNIC
3020 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3021 struct iscsi_stats_info *iscsi_stat =
3022 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3023
3024 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3025
3026 iscsi_stat->qos_priority =
3027 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3028
3029 /* ask L5 driver to add data to the struct */
3030 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3031 #endif
3032 }
3033
3034 /* called due to MCP event (on pmf):
3035 * reread new bandwidth configuration
3036 * configure FW
3037 * notify others function about the change
3038 */
3039 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
3040 {
3041 if (bp->link_vars.link_up) {
3042 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3043 bnx2x_link_sync_notify(bp);
3044 }
3045 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3046 }
3047
3048 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
3049 {
3050 bnx2x_config_mf_bw(bp);
3051 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3052 }
3053
3054 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3055 {
3056 enum drv_info_opcode op_code;
3057 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3058
3059 /* if drv_info version supported by MFW doesn't match - send NACK */
3060 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3061 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3062 return;
3063 }
3064
3065 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3066 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3067
3068 memset(&bp->slowpath->drv_info_to_mcp, 0,
3069 sizeof(union drv_info_to_mcp));
3070
3071 switch (op_code) {
3072 case ETH_STATS_OPCODE:
3073 bnx2x_drv_info_ether_stat(bp);
3074 break;
3075 case FCOE_STATS_OPCODE:
3076 bnx2x_drv_info_fcoe_stat(bp);
3077 break;
3078 case ISCSI_STATS_OPCODE:
3079 bnx2x_drv_info_iscsi_stat(bp);
3080 break;
3081 default:
3082 /* if op code isn't supported - send NACK */
3083 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3084 return;
3085 }
3086
3087 /* if we got drv_info attn from MFW then these fields are defined in
3088 * shmem2 for sure
3089 */
3090 SHMEM2_WR(bp, drv_info_host_addr_lo,
3091 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3092 SHMEM2_WR(bp, drv_info_host_addr_hi,
3093 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3094
3095 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3096 }
3097
3098 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3099 {
3100 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3101
3102 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3103
3104 /*
3105 * This is the only place besides the function initialization
3106 * where the bp->flags can change so it is done without any
3107 * locks
3108 */
3109 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3110 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3111 bp->flags |= MF_FUNC_DIS;
3112
3113 bnx2x_e1h_disable(bp);
3114 } else {
3115 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3116 bp->flags &= ~MF_FUNC_DIS;
3117
3118 bnx2x_e1h_enable(bp);
3119 }
3120 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3121 }
3122 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3123 bnx2x_config_mf_bw(bp);
3124 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3125 }
3126
3127 /* Report results to MCP */
3128 if (dcc_event)
3129 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3130 else
3131 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3132 }
3133
3134 /* must be called under the spq lock */
3135 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3136 {
3137 struct eth_spe *next_spe = bp->spq_prod_bd;
3138
3139 if (bp->spq_prod_bd == bp->spq_last_bd) {
3140 bp->spq_prod_bd = bp->spq;
3141 bp->spq_prod_idx = 0;
3142 DP(BNX2X_MSG_SP, "end of spq\n");
3143 } else {
3144 bp->spq_prod_bd++;
3145 bp->spq_prod_idx++;
3146 }
3147 return next_spe;
3148 }
3149
3150 /* must be called under the spq lock */
3151 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
3152 {
3153 int func = BP_FUNC(bp);
3154
3155 /*
3156 * Make sure that BD data is updated before writing the producer:
3157 * BD data is written to the memory, the producer is read from the
3158 * memory, thus we need a full memory barrier to ensure the ordering.
3159 */
3160 mb();
3161
3162 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3163 bp->spq_prod_idx);
3164 mmiowb();
3165 }
3166
3167 /**
3168 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3169 *
3170 * @cmd: command to check
3171 * @cmd_type: command type
3172 */
3173 static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3174 {
3175 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3176 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3177 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3178 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3179 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3180 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3181 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3182 return true;
3183 else
3184 return false;
3185
3186 }
3187
3188
3189 /**
3190 * bnx2x_sp_post - place a single command on an SP ring
3191 *
3192 * @bp: driver handle
3193 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3194 * @cid: SW CID the command is related to
3195 * @data_hi: command private data address (high 32 bits)
3196 * @data_lo: command private data address (low 32 bits)
3197 * @cmd_type: command type (e.g. NONE, ETH)
3198 *
3199 * SP data is handled as if it's always an address pair, thus data fields are
3200 * not swapped to little endian in upper functions. Instead this function swaps
3201 * data as if it's two u32 fields.
3202 */
3203 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3204 u32 data_hi, u32 data_lo, int cmd_type)
3205 {
3206 struct eth_spe *spe;
3207 u16 type;
3208 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3209
3210 #ifdef BNX2X_STOP_ON_ERROR
3211 if (unlikely(bp->panic)) {
3212 BNX2X_ERR("Can't post SP when there is panic\n");
3213 return -EIO;
3214 }
3215 #endif
3216
3217 spin_lock_bh(&bp->spq_lock);
3218
3219 if (common) {
3220 if (!atomic_read(&bp->eq_spq_left)) {
3221 BNX2X_ERR("BUG! EQ ring full!\n");
3222 spin_unlock_bh(&bp->spq_lock);
3223 bnx2x_panic();
3224 return -EBUSY;
3225 }
3226 } else if (!atomic_read(&bp->cq_spq_left)) {
3227 BNX2X_ERR("BUG! SPQ ring full!\n");
3228 spin_unlock_bh(&bp->spq_lock);
3229 bnx2x_panic();
3230 return -EBUSY;
3231 }
3232
3233 spe = bnx2x_sp_get_next(bp);
3234
3235 /* CID needs port number to be encoded int it */
3236 spe->hdr.conn_and_cmd_data =
3237 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3238 HW_CID(bp, cid));
3239
3240 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3241
3242 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3243 SPE_HDR_FUNCTION_ID);
3244
3245 spe->hdr.type = cpu_to_le16(type);
3246
3247 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3248 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3249
3250 /*
3251 * It's ok if the actual decrement is issued towards the memory
3252 * somewhere between the spin_lock and spin_unlock. Thus no
3253 * more explict memory barrier is needed.
3254 */
3255 if (common)
3256 atomic_dec(&bp->eq_spq_left);
3257 else
3258 atomic_dec(&bp->cq_spq_left);
3259
3260
3261 DP(BNX2X_MSG_SP,
3262 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3263 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3264 (u32)(U64_LO(bp->spq_mapping) +
3265 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3266 HW_CID(bp, cid), data_hi, data_lo, type,
3267 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3268
3269 bnx2x_sp_prod_update(bp);
3270 spin_unlock_bh(&bp->spq_lock);
3271 return 0;
3272 }
3273
3274 /* acquire split MCP access lock register */
3275 static int bnx2x_acquire_alr(struct bnx2x *bp)
3276 {
3277 u32 j, val;
3278 int rc = 0;
3279
3280 might_sleep();
3281 for (j = 0; j < 1000; j++) {
3282 val = (1UL << 31);
3283 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3284 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3285 if (val & (1L << 31))
3286 break;
3287
3288 msleep(5);
3289 }
3290 if (!(val & (1L << 31))) {
3291 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3292 rc = -EBUSY;
3293 }
3294
3295 return rc;
3296 }
3297
3298 /* release split MCP access lock register */
3299 static void bnx2x_release_alr(struct bnx2x *bp)
3300 {
3301 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3302 }
3303
3304 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3305 #define BNX2X_DEF_SB_IDX 0x0002
3306
3307 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3308 {
3309 struct host_sp_status_block *def_sb = bp->def_status_blk;
3310 u16 rc = 0;
3311
3312 barrier(); /* status block is written to by the chip */
3313 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3314 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3315 rc |= BNX2X_DEF_SB_ATT_IDX;
3316 }
3317
3318 if (bp->def_idx != def_sb->sp_sb.running_index) {
3319 bp->def_idx = def_sb->sp_sb.running_index;
3320 rc |= BNX2X_DEF_SB_IDX;
3321 }
3322
3323 /* Do not reorder: indecies reading should complete before handling */
3324 barrier();
3325 return rc;
3326 }
3327
3328 /*
3329 * slow path service functions
3330 */
3331
3332 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3333 {
3334 int port = BP_PORT(bp);
3335 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3336 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3337 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3338 NIG_REG_MASK_INTERRUPT_PORT0;
3339 u32 aeu_mask;
3340 u32 nig_mask = 0;
3341 u32 reg_addr;
3342
3343 if (bp->attn_state & asserted)
3344 BNX2X_ERR("IGU ERROR\n");
3345
3346 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3347 aeu_mask = REG_RD(bp, aeu_addr);
3348
3349 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3350 aeu_mask, asserted);
3351 aeu_mask &= ~(asserted & 0x3ff);
3352 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3353
3354 REG_WR(bp, aeu_addr, aeu_mask);
3355 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3356
3357 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3358 bp->attn_state |= asserted;
3359 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3360
3361 if (asserted & ATTN_HARD_WIRED_MASK) {
3362 if (asserted & ATTN_NIG_FOR_FUNC) {
3363
3364 bnx2x_acquire_phy_lock(bp);
3365
3366 /* save nig interrupt mask */
3367 nig_mask = REG_RD(bp, nig_int_mask_addr);
3368
3369 /* If nig_mask is not set, no need to call the update
3370 * function.
3371 */
3372 if (nig_mask) {
3373 REG_WR(bp, nig_int_mask_addr, 0);
3374
3375 bnx2x_link_attn(bp);
3376 }
3377
3378 /* handle unicore attn? */
3379 }
3380 if (asserted & ATTN_SW_TIMER_4_FUNC)
3381 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3382
3383 if (asserted & GPIO_2_FUNC)
3384 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3385
3386 if (asserted & GPIO_3_FUNC)
3387 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3388
3389 if (asserted & GPIO_4_FUNC)
3390 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3391
3392 if (port == 0) {
3393 if (asserted & ATTN_GENERAL_ATTN_1) {
3394 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3395 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3396 }
3397 if (asserted & ATTN_GENERAL_ATTN_2) {
3398 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3399 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3400 }
3401 if (asserted & ATTN_GENERAL_ATTN_3) {
3402 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3403 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3404 }
3405 } else {
3406 if (asserted & ATTN_GENERAL_ATTN_4) {
3407 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3408 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3409 }
3410 if (asserted & ATTN_GENERAL_ATTN_5) {
3411 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3412 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3413 }
3414 if (asserted & ATTN_GENERAL_ATTN_6) {
3415 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3416 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3417 }
3418 }
3419
3420 } /* if hardwired */
3421
3422 if (bp->common.int_block == INT_BLOCK_HC)
3423 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3424 COMMAND_REG_ATTN_BITS_SET);
3425 else
3426 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3427
3428 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3429 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3430 REG_WR(bp, reg_addr, asserted);
3431
3432 /* now set back the mask */
3433 if (asserted & ATTN_NIG_FOR_FUNC) {
3434 REG_WR(bp, nig_int_mask_addr, nig_mask);
3435 bnx2x_release_phy_lock(bp);
3436 }
3437 }
3438
3439 static inline void bnx2x_fan_failure(struct bnx2x *bp)
3440 {
3441 int port = BP_PORT(bp);
3442 u32 ext_phy_config;
3443 /* mark the failure */
3444 ext_phy_config =
3445 SHMEM_RD(bp,
3446 dev_info.port_hw_config[port].external_phy_config);
3447
3448 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3449 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3450 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3451 ext_phy_config);
3452
3453 /* log the failure */
3454 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3455 "Please contact OEM Support for assistance\n");
3456
3457 /*
3458 * Scheudle device reset (unload)
3459 * This is due to some boards consuming sufficient power when driver is
3460 * up to overheat if fan fails.
3461 */
3462 smp_mb__before_clear_bit();
3463 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3464 smp_mb__after_clear_bit();
3465 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3466
3467 }
3468
3469 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3470 {
3471 int port = BP_PORT(bp);
3472 int reg_offset;
3473 u32 val;
3474
3475 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3476 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3477
3478 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3479
3480 val = REG_RD(bp, reg_offset);
3481 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3482 REG_WR(bp, reg_offset, val);
3483
3484 BNX2X_ERR("SPIO5 hw attention\n");
3485
3486 /* Fan failure attention */
3487 bnx2x_hw_reset_phy(&bp->link_params);
3488 bnx2x_fan_failure(bp);
3489 }
3490
3491 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3492 bnx2x_acquire_phy_lock(bp);
3493 bnx2x_handle_module_detect_int(&bp->link_params);
3494 bnx2x_release_phy_lock(bp);
3495 }
3496
3497 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3498
3499 val = REG_RD(bp, reg_offset);
3500 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3501 REG_WR(bp, reg_offset, val);
3502
3503 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3504 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3505 bnx2x_panic();
3506 }
3507 }
3508
3509 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3510 {
3511 u32 val;
3512
3513 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3514
3515 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3516 BNX2X_ERR("DB hw attention 0x%x\n", val);
3517 /* DORQ discard attention */
3518 if (val & 0x2)
3519 BNX2X_ERR("FATAL error from DORQ\n");
3520 }
3521
3522 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3523
3524 int port = BP_PORT(bp);
3525 int reg_offset;
3526
3527 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3528 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3529
3530 val = REG_RD(bp, reg_offset);
3531 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3532 REG_WR(bp, reg_offset, val);
3533
3534 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3535 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3536 bnx2x_panic();
3537 }
3538 }
3539
3540 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3541 {
3542 u32 val;
3543
3544 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3545
3546 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3547 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3548 /* CFC error attention */
3549 if (val & 0x2)
3550 BNX2X_ERR("FATAL error from CFC\n");
3551 }
3552
3553 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3554 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3555 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3556 /* RQ_USDMDP_FIFO_OVERFLOW */
3557 if (val & 0x18000)
3558 BNX2X_ERR("FATAL error from PXP\n");
3559
3560 if (!CHIP_IS_E1x(bp)) {
3561 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3562 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3563 }
3564 }
3565
3566 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3567
3568 int port = BP_PORT(bp);
3569 int reg_offset;
3570
3571 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3572 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3573
3574 val = REG_RD(bp, reg_offset);
3575 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3576 REG_WR(bp, reg_offset, val);
3577
3578 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3579 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3580 bnx2x_panic();
3581 }
3582 }
3583
3584 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3585 {
3586 u32 val;
3587
3588 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3589
3590 if (attn & BNX2X_PMF_LINK_ASSERT) {
3591 int func = BP_FUNC(bp);
3592
3593 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3594 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3595 func_mf_config[BP_ABS_FUNC(bp)].config);
3596 val = SHMEM_RD(bp,
3597 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3598 if (val & DRV_STATUS_DCC_EVENT_MASK)
3599 bnx2x_dcc_event(bp,
3600 (val & DRV_STATUS_DCC_EVENT_MASK));
3601
3602 if (val & DRV_STATUS_SET_MF_BW)
3603 bnx2x_set_mf_bw(bp);
3604
3605 if (val & DRV_STATUS_DRV_INFO_REQ)
3606 bnx2x_handle_drv_info_req(bp);
3607 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3608 bnx2x_pmf_update(bp);
3609
3610 if (bp->port.pmf &&
3611 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3612 bp->dcbx_enabled > 0)
3613 /* start dcbx state machine */
3614 bnx2x_dcbx_set_params(bp,
3615 BNX2X_DCBX_STATE_NEG_RECEIVED);
3616 if (bp->link_vars.periodic_flags &
3617 PERIODIC_FLAGS_LINK_EVENT) {
3618 /* sync with link */
3619 bnx2x_acquire_phy_lock(bp);
3620 bp->link_vars.periodic_flags &=
3621 ~PERIODIC_FLAGS_LINK_EVENT;
3622 bnx2x_release_phy_lock(bp);
3623 if (IS_MF(bp))
3624 bnx2x_link_sync_notify(bp);
3625 bnx2x_link_report(bp);
3626 }
3627 /* Always call it here: bnx2x_link_report() will
3628 * prevent the link indication duplication.
3629 */
3630 bnx2x__link_status_update(bp);
3631 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3632
3633 BNX2X_ERR("MC assert!\n");
3634 bnx2x_mc_assert(bp);
3635 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3636 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3637 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3638 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3639 bnx2x_panic();
3640
3641 } else if (attn & BNX2X_MCP_ASSERT) {
3642
3643 BNX2X_ERR("MCP assert!\n");
3644 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3645 bnx2x_fw_dump(bp);
3646
3647 } else
3648 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3649 }
3650
3651 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3652 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3653 if (attn & BNX2X_GRC_TIMEOUT) {
3654 val = CHIP_IS_E1(bp) ? 0 :
3655 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3656 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3657 }
3658 if (attn & BNX2X_GRC_RSV) {
3659 val = CHIP_IS_E1(bp) ? 0 :
3660 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3661 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3662 }
3663 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3664 }
3665 }
3666
3667 /*
3668 * Bits map:
3669 * 0-7 - Engine0 load counter.
3670 * 8-15 - Engine1 load counter.
3671 * 16 - Engine0 RESET_IN_PROGRESS bit.
3672 * 17 - Engine1 RESET_IN_PROGRESS bit.
3673 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3674 * on the engine
3675 * 19 - Engine1 ONE_IS_LOADED.
3676 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3677 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3678 * just the one belonging to its engine).
3679 *
3680 */
3681 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3682
3683 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3684 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3685 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3686 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3687 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3688 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3689 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3690
3691 /*
3692 * Set the GLOBAL_RESET bit.
3693 *
3694 * Should be run under rtnl lock
3695 */
3696 void bnx2x_set_reset_global(struct bnx2x *bp)
3697 {
3698 u32 val;
3699 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3700 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3701 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3702 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3703 }
3704
3705 /*
3706 * Clear the GLOBAL_RESET bit.
3707 *
3708 * Should be run under rtnl lock
3709 */
3710 static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3711 {
3712 u32 val;
3713 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3714 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3715 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3716 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3717 }
3718
3719 /*
3720 * Checks the GLOBAL_RESET bit.
3721 *
3722 * should be run under rtnl lock
3723 */
3724 static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3725 {
3726 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3727
3728 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3729 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3730 }
3731
3732 /*
3733 * Clear RESET_IN_PROGRESS bit for the current engine.
3734 *
3735 * Should be run under rtnl lock
3736 */
3737 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3738 {
3739 u32 val;
3740 u32 bit = BP_PATH(bp) ?
3741 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3742 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3743 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3744
3745 /* Clear the bit */
3746 val &= ~bit;
3747 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3748
3749 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3750 }
3751
3752 /*
3753 * Set RESET_IN_PROGRESS for the current engine.
3754 *
3755 * should be run under rtnl lock
3756 */
3757 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3758 {
3759 u32 val;
3760 u32 bit = BP_PATH(bp) ?
3761 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3762 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3763 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3764
3765 /* Set the bit */
3766 val |= bit;
3767 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3768 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3769 }
3770
3771 /*
3772 * Checks the RESET_IN_PROGRESS bit for the given engine.
3773 * should be run under rtnl lock
3774 */
3775 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3776 {
3777 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3778 u32 bit = engine ?
3779 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3780
3781 /* return false if bit is set */
3782 return (val & bit) ? false : true;
3783 }
3784
3785 /*
3786 * set pf load for the current pf.
3787 *
3788 * should be run under rtnl lock
3789 */
3790 void bnx2x_set_pf_load(struct bnx2x *bp)
3791 {
3792 u32 val1, val;
3793 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3794 BNX2X_PATH0_LOAD_CNT_MASK;
3795 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3796 BNX2X_PATH0_LOAD_CNT_SHIFT;
3797
3798 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3799 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3800
3801 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
3802
3803 /* get the current counter value */
3804 val1 = (val & mask) >> shift;
3805
3806 /* set bit of that PF */
3807 val1 |= (1 << bp->pf_num);
3808
3809 /* clear the old value */
3810 val &= ~mask;
3811
3812 /* set the new one */
3813 val |= ((val1 << shift) & mask);
3814
3815 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3816 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3817 }
3818
3819 /**
3820 * bnx2x_clear_pf_load - clear pf load mark
3821 *
3822 * @bp: driver handle
3823 *
3824 * Should be run under rtnl lock.
3825 * Decrements the load counter for the current engine. Returns
3826 * whether other functions are still loaded
3827 */
3828 bool bnx2x_clear_pf_load(struct bnx2x *bp)
3829 {
3830 u32 val1, val;
3831 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3832 BNX2X_PATH0_LOAD_CNT_MASK;
3833 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3834 BNX2X_PATH0_LOAD_CNT_SHIFT;
3835
3836 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3837 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3838 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
3839
3840 /* get the current counter value */
3841 val1 = (val & mask) >> shift;
3842
3843 /* clear bit of that PF */
3844 val1 &= ~(1 << bp->pf_num);
3845
3846 /* clear the old value */
3847 val &= ~mask;
3848
3849 /* set the new one */
3850 val |= ((val1 << shift) & mask);
3851
3852 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3853 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3854 return val1 != 0;
3855 }
3856
3857 /*
3858 * Read the load status for the current engine.
3859 *
3860 * should be run under rtnl lock
3861 */
3862 static inline bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
3863 {
3864 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3865 BNX2X_PATH0_LOAD_CNT_MASK);
3866 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3867 BNX2X_PATH0_LOAD_CNT_SHIFT);
3868 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3869
3870 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
3871
3872 val = (val & mask) >> shift;
3873
3874 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
3875 engine, val);
3876
3877 return val != 0;
3878 }
3879
3880 /*
3881 * Reset the load status for the current engine.
3882 */
3883 static inline void bnx2x_clear_load_status(struct bnx2x *bp)
3884 {
3885 u32 val;
3886 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3887 BNX2X_PATH0_LOAD_CNT_MASK);
3888 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3889 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3890 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
3891 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3892 }
3893
3894 static inline void _print_next_block(int idx, const char *blk)
3895 {
3896 pr_cont("%s%s", idx ? ", " : "", blk);
3897 }
3898
3899 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3900 bool print)
3901 {
3902 int i = 0;
3903 u32 cur_bit = 0;
3904 for (i = 0; sig; i++) {
3905 cur_bit = ((u32)0x1 << i);
3906 if (sig & cur_bit) {
3907 switch (cur_bit) {
3908 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3909 if (print)
3910 _print_next_block(par_num++, "BRB");
3911 break;
3912 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3913 if (print)
3914 _print_next_block(par_num++, "PARSER");
3915 break;
3916 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3917 if (print)
3918 _print_next_block(par_num++, "TSDM");
3919 break;
3920 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3921 if (print)
3922 _print_next_block(par_num++,
3923 "SEARCHER");
3924 break;
3925 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3926 if (print)
3927 _print_next_block(par_num++, "TCM");
3928 break;
3929 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3930 if (print)
3931 _print_next_block(par_num++, "TSEMI");
3932 break;
3933 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3934 if (print)
3935 _print_next_block(par_num++, "XPB");
3936 break;
3937 }
3938
3939 /* Clear the bit */
3940 sig &= ~cur_bit;
3941 }
3942 }
3943
3944 return par_num;
3945 }
3946
3947 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3948 bool *global, bool print)
3949 {
3950 int i = 0;
3951 u32 cur_bit = 0;
3952 for (i = 0; sig; i++) {
3953 cur_bit = ((u32)0x1 << i);
3954 if (sig & cur_bit) {
3955 switch (cur_bit) {
3956 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3957 if (print)
3958 _print_next_block(par_num++, "PBF");
3959 break;
3960 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3961 if (print)
3962 _print_next_block(par_num++, "QM");
3963 break;
3964 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3965 if (print)
3966 _print_next_block(par_num++, "TM");
3967 break;
3968 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3969 if (print)
3970 _print_next_block(par_num++, "XSDM");
3971 break;
3972 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3973 if (print)
3974 _print_next_block(par_num++, "XCM");
3975 break;
3976 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3977 if (print)
3978 _print_next_block(par_num++, "XSEMI");
3979 break;
3980 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3981 if (print)
3982 _print_next_block(par_num++,
3983 "DOORBELLQ");
3984 break;
3985 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3986 if (print)
3987 _print_next_block(par_num++, "NIG");
3988 break;
3989 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3990 if (print)
3991 _print_next_block(par_num++,
3992 "VAUX PCI CORE");
3993 *global = true;
3994 break;
3995 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3996 if (print)
3997 _print_next_block(par_num++, "DEBUG");
3998 break;
3999 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4000 if (print)
4001 _print_next_block(par_num++, "USDM");
4002 break;
4003 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4004 if (print)
4005 _print_next_block(par_num++, "UCM");
4006 break;
4007 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4008 if (print)
4009 _print_next_block(par_num++, "USEMI");
4010 break;
4011 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4012 if (print)
4013 _print_next_block(par_num++, "UPB");
4014 break;
4015 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4016 if (print)
4017 _print_next_block(par_num++, "CSDM");
4018 break;
4019 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4020 if (print)
4021 _print_next_block(par_num++, "CCM");
4022 break;
4023 }
4024
4025 /* Clear the bit */
4026 sig &= ~cur_bit;
4027 }
4028 }
4029
4030 return par_num;
4031 }
4032
4033 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4034 bool print)
4035 {
4036 int i = 0;
4037 u32 cur_bit = 0;
4038 for (i = 0; sig; i++) {
4039 cur_bit = ((u32)0x1 << i);
4040 if (sig & cur_bit) {
4041 switch (cur_bit) {
4042 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4043 if (print)
4044 _print_next_block(par_num++, "CSEMI");
4045 break;
4046 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4047 if (print)
4048 _print_next_block(par_num++, "PXP");
4049 break;
4050 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4051 if (print)
4052 _print_next_block(par_num++,
4053 "PXPPCICLOCKCLIENT");
4054 break;
4055 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4056 if (print)
4057 _print_next_block(par_num++, "CFC");
4058 break;
4059 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4060 if (print)
4061 _print_next_block(par_num++, "CDU");
4062 break;
4063 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4064 if (print)
4065 _print_next_block(par_num++, "DMAE");
4066 break;
4067 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4068 if (print)
4069 _print_next_block(par_num++, "IGU");
4070 break;
4071 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4072 if (print)
4073 _print_next_block(par_num++, "MISC");
4074 break;
4075 }
4076
4077 /* Clear the bit */
4078 sig &= ~cur_bit;
4079 }
4080 }
4081
4082 return par_num;
4083 }
4084
4085 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4086 bool *global, bool print)
4087 {
4088 int i = 0;
4089 u32 cur_bit = 0;
4090 for (i = 0; sig; i++) {
4091 cur_bit = ((u32)0x1 << i);
4092 if (sig & cur_bit) {
4093 switch (cur_bit) {
4094 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4095 if (print)
4096 _print_next_block(par_num++, "MCP ROM");
4097 *global = true;
4098 break;
4099 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4100 if (print)
4101 _print_next_block(par_num++,
4102 "MCP UMP RX");
4103 *global = true;
4104 break;
4105 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4106 if (print)
4107 _print_next_block(par_num++,
4108 "MCP UMP TX");
4109 *global = true;
4110 break;
4111 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4112 if (print)
4113 _print_next_block(par_num++,
4114 "MCP SCPAD");
4115 *global = true;
4116 break;
4117 }
4118
4119 /* Clear the bit */
4120 sig &= ~cur_bit;
4121 }
4122 }
4123
4124 return par_num;
4125 }
4126
4127 static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4128 bool print)
4129 {
4130 int i = 0;
4131 u32 cur_bit = 0;
4132 for (i = 0; sig; i++) {
4133 cur_bit = ((u32)0x1 << i);
4134 if (sig & cur_bit) {
4135 switch (cur_bit) {
4136 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4137 if (print)
4138 _print_next_block(par_num++, "PGLUE_B");
4139 break;
4140 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4141 if (print)
4142 _print_next_block(par_num++, "ATC");
4143 break;
4144 }
4145
4146 /* Clear the bit */
4147 sig &= ~cur_bit;
4148 }
4149 }
4150
4151 return par_num;
4152 }
4153
4154 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4155 u32 *sig)
4156 {
4157 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4158 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4159 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4160 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4161 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4162 int par_num = 0;
4163 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4164 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4165 sig[0] & HW_PRTY_ASSERT_SET_0,
4166 sig[1] & HW_PRTY_ASSERT_SET_1,
4167 sig[2] & HW_PRTY_ASSERT_SET_2,
4168 sig[3] & HW_PRTY_ASSERT_SET_3,
4169 sig[4] & HW_PRTY_ASSERT_SET_4);
4170 if (print)
4171 netdev_err(bp->dev,
4172 "Parity errors detected in blocks: ");
4173 par_num = bnx2x_check_blocks_with_parity0(
4174 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4175 par_num = bnx2x_check_blocks_with_parity1(
4176 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4177 par_num = bnx2x_check_blocks_with_parity2(
4178 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4179 par_num = bnx2x_check_blocks_with_parity3(
4180 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4181 par_num = bnx2x_check_blocks_with_parity4(
4182 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4183
4184 if (print)
4185 pr_cont("\n");
4186
4187 return true;
4188 } else
4189 return false;
4190 }
4191
4192 /**
4193 * bnx2x_chk_parity_attn - checks for parity attentions.
4194 *
4195 * @bp: driver handle
4196 * @global: true if there was a global attention
4197 * @print: show parity attention in syslog
4198 */
4199 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4200 {
4201 struct attn_route attn = { {0} };
4202 int port = BP_PORT(bp);
4203
4204 attn.sig[0] = REG_RD(bp,
4205 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4206 port*4);
4207 attn.sig[1] = REG_RD(bp,
4208 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4209 port*4);
4210 attn.sig[2] = REG_RD(bp,
4211 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4212 port*4);
4213 attn.sig[3] = REG_RD(bp,
4214 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4215 port*4);
4216
4217 if (!CHIP_IS_E1x(bp))
4218 attn.sig[4] = REG_RD(bp,
4219 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4220 port*4);
4221
4222 return bnx2x_parity_attn(bp, global, print, attn.sig);
4223 }
4224
4225
4226 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4227 {
4228 u32 val;
4229 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4230
4231 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4232 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4233 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4234 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4235 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4236 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4237 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4238 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4239 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4240 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4241 if (val &
4242 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4243 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4244 if (val &
4245 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4246 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4247 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4248 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4249 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4250 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4251 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4252 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4253 }
4254 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4255 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4256 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4257 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4258 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4259 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4260 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4261 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4262 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4263 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4264 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4265 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4266 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4267 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4268 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4269 }
4270
4271 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4272 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4273 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4274 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4275 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4276 }
4277
4278 }
4279
4280 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4281 {
4282 struct attn_route attn, *group_mask;
4283 int port = BP_PORT(bp);
4284 int index;
4285 u32 reg_addr;
4286 u32 val;
4287 u32 aeu_mask;
4288 bool global = false;
4289
4290 /* need to take HW lock because MCP or other port might also
4291 try to handle this event */
4292 bnx2x_acquire_alr(bp);
4293
4294 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4295 #ifndef BNX2X_STOP_ON_ERROR
4296 bp->recovery_state = BNX2X_RECOVERY_INIT;
4297 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4298 /* Disable HW interrupts */
4299 bnx2x_int_disable(bp);
4300 /* In case of parity errors don't handle attentions so that
4301 * other function would "see" parity errors.
4302 */
4303 #else
4304 bnx2x_panic();
4305 #endif
4306 bnx2x_release_alr(bp);
4307 return;
4308 }
4309
4310 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4311 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4312 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4313 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4314 if (!CHIP_IS_E1x(bp))
4315 attn.sig[4] =
4316 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4317 else
4318 attn.sig[4] = 0;
4319
4320 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4321 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4322
4323 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4324 if (deasserted & (1 << index)) {
4325 group_mask = &bp->attn_group[index];
4326
4327 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4328 index,
4329 group_mask->sig[0], group_mask->sig[1],
4330 group_mask->sig[2], group_mask->sig[3],
4331 group_mask->sig[4]);
4332
4333 bnx2x_attn_int_deasserted4(bp,
4334 attn.sig[4] & group_mask->sig[4]);
4335 bnx2x_attn_int_deasserted3(bp,
4336 attn.sig[3] & group_mask->sig[3]);
4337 bnx2x_attn_int_deasserted1(bp,
4338 attn.sig[1] & group_mask->sig[1]);
4339 bnx2x_attn_int_deasserted2(bp,
4340 attn.sig[2] & group_mask->sig[2]);
4341 bnx2x_attn_int_deasserted0(bp,
4342 attn.sig[0] & group_mask->sig[0]);
4343 }
4344 }
4345
4346 bnx2x_release_alr(bp);
4347
4348 if (bp->common.int_block == INT_BLOCK_HC)
4349 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4350 COMMAND_REG_ATTN_BITS_CLR);
4351 else
4352 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4353
4354 val = ~deasserted;
4355 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4356 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4357 REG_WR(bp, reg_addr, val);
4358
4359 if (~bp->attn_state & deasserted)
4360 BNX2X_ERR("IGU ERROR\n");
4361
4362 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4363 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4364
4365 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4366 aeu_mask = REG_RD(bp, reg_addr);
4367
4368 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4369 aeu_mask, deasserted);
4370 aeu_mask |= (deasserted & 0x3ff);
4371 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4372
4373 REG_WR(bp, reg_addr, aeu_mask);
4374 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4375
4376 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4377 bp->attn_state &= ~deasserted;
4378 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4379 }
4380
4381 static void bnx2x_attn_int(struct bnx2x *bp)
4382 {
4383 /* read local copy of bits */
4384 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4385 attn_bits);
4386 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4387 attn_bits_ack);
4388 u32 attn_state = bp->attn_state;
4389
4390 /* look for changed bits */
4391 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4392 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4393
4394 DP(NETIF_MSG_HW,
4395 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4396 attn_bits, attn_ack, asserted, deasserted);
4397
4398 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4399 BNX2X_ERR("BAD attention state\n");
4400
4401 /* handle bits that were raised */
4402 if (asserted)
4403 bnx2x_attn_int_asserted(bp, asserted);
4404
4405 if (deasserted)
4406 bnx2x_attn_int_deasserted(bp, deasserted);
4407 }
4408
4409 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4410 u16 index, u8 op, u8 update)
4411 {
4412 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4413
4414 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4415 igu_addr);
4416 }
4417
4418 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4419 {
4420 /* No memory barriers */
4421 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4422 mmiowb(); /* keep prod updates ordered */
4423 }
4424
4425 #ifdef BCM_CNIC
4426 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4427 union event_ring_elem *elem)
4428 {
4429 u8 err = elem->message.error;
4430
4431 if (!bp->cnic_eth_dev.starting_cid ||
4432 (cid < bp->cnic_eth_dev.starting_cid &&
4433 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4434 return 1;
4435
4436 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4437
4438 if (unlikely(err)) {
4439
4440 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4441 cid);
4442 bnx2x_panic_dump(bp);
4443 }
4444 bnx2x_cnic_cfc_comp(bp, cid, err);
4445 return 0;
4446 }
4447 #endif
4448
4449 static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4450 {
4451 struct bnx2x_mcast_ramrod_params rparam;
4452 int rc;
4453
4454 memset(&rparam, 0, sizeof(rparam));
4455
4456 rparam.mcast_obj = &bp->mcast_obj;
4457
4458 netif_addr_lock_bh(bp->dev);
4459
4460 /* Clear pending state for the last command */
4461 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4462
4463 /* If there are pending mcast commands - send them */
4464 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4465 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4466 if (rc < 0)
4467 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4468 rc);
4469 }
4470
4471 netif_addr_unlock_bh(bp->dev);
4472 }
4473
4474 static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4475 union event_ring_elem *elem)
4476 {
4477 unsigned long ramrod_flags = 0;
4478 int rc = 0;
4479 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4480 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4481
4482 /* Always push next commands out, don't wait here */
4483 __set_bit(RAMROD_CONT, &ramrod_flags);
4484
4485 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4486 case BNX2X_FILTER_MAC_PENDING:
4487 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4488 #ifdef BCM_CNIC
4489 if (cid == BNX2X_ISCSI_ETH_CID)
4490 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4491 else
4492 #endif
4493 vlan_mac_obj = &bp->fp[cid].mac_obj;
4494
4495 break;
4496 case BNX2X_FILTER_MCAST_PENDING:
4497 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4498 /* This is only relevant for 57710 where multicast MACs are
4499 * configured as unicast MACs using the same ramrod.
4500 */
4501 bnx2x_handle_mcast_eqe(bp);
4502 return;
4503 default:
4504 BNX2X_ERR("Unsupported classification command: %d\n",
4505 elem->message.data.eth_event.echo);
4506 return;
4507 }
4508
4509 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4510
4511 if (rc < 0)
4512 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4513 else if (rc > 0)
4514 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4515
4516 }
4517
4518 #ifdef BCM_CNIC
4519 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4520 #endif
4521
4522 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4523 {
4524 netif_addr_lock_bh(bp->dev);
4525
4526 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4527
4528 /* Send rx_mode command again if was requested */
4529 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4530 bnx2x_set_storm_rx_mode(bp);
4531 #ifdef BCM_CNIC
4532 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4533 &bp->sp_state))
4534 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4535 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4536 &bp->sp_state))
4537 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4538 #endif
4539
4540 netif_addr_unlock_bh(bp->dev);
4541 }
4542
4543 static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4544 struct bnx2x *bp, u32 cid)
4545 {
4546 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4547 #ifdef BCM_CNIC
4548 if (cid == BNX2X_FCOE_ETH_CID)
4549 return &bnx2x_fcoe(bp, q_obj);
4550 else
4551 #endif
4552 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
4553 }
4554
4555 static void bnx2x_eq_int(struct bnx2x *bp)
4556 {
4557 u16 hw_cons, sw_cons, sw_prod;
4558 union event_ring_elem *elem;
4559 u32 cid;
4560 u8 opcode;
4561 int spqe_cnt = 0;
4562 struct bnx2x_queue_sp_obj *q_obj;
4563 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4564 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4565
4566 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4567
4568 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4569 * when we get the the next-page we nned to adjust so the loop
4570 * condition below will be met. The next element is the size of a
4571 * regular element and hence incrementing by 1
4572 */
4573 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4574 hw_cons++;
4575
4576 /* This function may never run in parallel with itself for a
4577 * specific bp, thus there is no need in "paired" read memory
4578 * barrier here.
4579 */
4580 sw_cons = bp->eq_cons;
4581 sw_prod = bp->eq_prod;
4582
4583 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4584 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4585
4586 for (; sw_cons != hw_cons;
4587 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4588
4589
4590 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4591
4592 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4593 opcode = elem->message.opcode;
4594
4595
4596 /* handle eq element */
4597 switch (opcode) {
4598 case EVENT_RING_OPCODE_STAT_QUERY:
4599 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
4600 "got statistics comp event %d\n",
4601 bp->stats_comp++);
4602 /* nothing to do with stats comp */
4603 goto next_spqe;
4604
4605 case EVENT_RING_OPCODE_CFC_DEL:
4606 /* handle according to cid range */
4607 /*
4608 * we may want to verify here that the bp state is
4609 * HALTING
4610 */
4611 DP(BNX2X_MSG_SP,
4612 "got delete ramrod for MULTI[%d]\n", cid);
4613 #ifdef BCM_CNIC
4614 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4615 goto next_spqe;
4616 #endif
4617 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4618
4619 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4620 break;
4621
4622
4623
4624 goto next_spqe;
4625
4626 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4627 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
4628 if (f_obj->complete_cmd(bp, f_obj,
4629 BNX2X_F_CMD_TX_STOP))
4630 break;
4631 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4632 goto next_spqe;
4633
4634 case EVENT_RING_OPCODE_START_TRAFFIC:
4635 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
4636 if (f_obj->complete_cmd(bp, f_obj,
4637 BNX2X_F_CMD_TX_START))
4638 break;
4639 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4640 goto next_spqe;
4641 case EVENT_RING_OPCODE_FUNCTION_START:
4642 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4643 "got FUNC_START ramrod\n");
4644 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4645 break;
4646
4647 goto next_spqe;
4648
4649 case EVENT_RING_OPCODE_FUNCTION_STOP:
4650 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4651 "got FUNC_STOP ramrod\n");
4652 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4653 break;
4654
4655 goto next_spqe;
4656 }
4657
4658 switch (opcode | bp->state) {
4659 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4660 BNX2X_STATE_OPEN):
4661 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4662 BNX2X_STATE_OPENING_WAIT4_PORT):
4663 cid = elem->message.data.eth_event.echo &
4664 BNX2X_SWCID_MASK;
4665 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4666 cid);
4667 rss_raw->clear_pending(rss_raw);
4668 break;
4669
4670 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4671 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4672 case (EVENT_RING_OPCODE_SET_MAC |
4673 BNX2X_STATE_CLOSING_WAIT4_HALT):
4674 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4675 BNX2X_STATE_OPEN):
4676 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4677 BNX2X_STATE_DIAG):
4678 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4679 BNX2X_STATE_CLOSING_WAIT4_HALT):
4680 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4681 bnx2x_handle_classification_eqe(bp, elem);
4682 break;
4683
4684 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4685 BNX2X_STATE_OPEN):
4686 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4687 BNX2X_STATE_DIAG):
4688 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4689 BNX2X_STATE_CLOSING_WAIT4_HALT):
4690 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4691 bnx2x_handle_mcast_eqe(bp);
4692 break;
4693
4694 case (EVENT_RING_OPCODE_FILTERS_RULES |
4695 BNX2X_STATE_OPEN):
4696 case (EVENT_RING_OPCODE_FILTERS_RULES |
4697 BNX2X_STATE_DIAG):
4698 case (EVENT_RING_OPCODE_FILTERS_RULES |
4699 BNX2X_STATE_CLOSING_WAIT4_HALT):
4700 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4701 bnx2x_handle_rx_mode_eqe(bp);
4702 break;
4703 default:
4704 /* unknown event log error and continue */
4705 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4706 elem->message.opcode, bp->state);
4707 }
4708 next_spqe:
4709 spqe_cnt++;
4710 } /* for */
4711
4712 smp_mb__before_atomic_inc();
4713 atomic_add(spqe_cnt, &bp->eq_spq_left);
4714
4715 bp->eq_cons = sw_cons;
4716 bp->eq_prod = sw_prod;
4717 /* Make sure that above mem writes were issued towards the memory */
4718 smp_wmb();
4719
4720 /* update producer */
4721 bnx2x_update_eq_prod(bp, bp->eq_prod);
4722 }
4723
4724 static void bnx2x_sp_task(struct work_struct *work)
4725 {
4726 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4727 u16 status;
4728
4729 status = bnx2x_update_dsb_idx(bp);
4730 /* if (status == 0) */
4731 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4732
4733 DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status);
4734
4735 /* HW attentions */
4736 if (status & BNX2X_DEF_SB_ATT_IDX) {
4737 bnx2x_attn_int(bp);
4738 status &= ~BNX2X_DEF_SB_ATT_IDX;
4739 }
4740
4741 /* SP events: STAT_QUERY and others */
4742 if (status & BNX2X_DEF_SB_IDX) {
4743 #ifdef BCM_CNIC
4744 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
4745
4746 if ((!NO_FCOE(bp)) &&
4747 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4748 /*
4749 * Prevent local bottom-halves from running as
4750 * we are going to change the local NAPI list.
4751 */
4752 local_bh_disable();
4753 napi_schedule(&bnx2x_fcoe(bp, napi));
4754 local_bh_enable();
4755 }
4756 #endif
4757 /* Handle EQ completions */
4758 bnx2x_eq_int(bp);
4759
4760 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4761 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4762
4763 status &= ~BNX2X_DEF_SB_IDX;
4764 }
4765
4766 if (unlikely(status))
4767 DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n",
4768 status);
4769
4770 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4771 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
4772 }
4773
4774 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
4775 {
4776 struct net_device *dev = dev_instance;
4777 struct bnx2x *bp = netdev_priv(dev);
4778
4779 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4780 IGU_INT_DISABLE, 0);
4781
4782 #ifdef BNX2X_STOP_ON_ERROR
4783 if (unlikely(bp->panic))
4784 return IRQ_HANDLED;
4785 #endif
4786
4787 #ifdef BCM_CNIC
4788 {
4789 struct cnic_ops *c_ops;
4790
4791 rcu_read_lock();
4792 c_ops = rcu_dereference(bp->cnic_ops);
4793 if (c_ops)
4794 c_ops->cnic_handler(bp->cnic_data, NULL);
4795 rcu_read_unlock();
4796 }
4797 #endif
4798 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
4799
4800 return IRQ_HANDLED;
4801 }
4802
4803 /* end of slow path */
4804
4805
4806 void bnx2x_drv_pulse(struct bnx2x *bp)
4807 {
4808 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4809 bp->fw_drv_pulse_wr_seq);
4810 }
4811
4812
4813 static void bnx2x_timer(unsigned long data)
4814 {
4815 struct bnx2x *bp = (struct bnx2x *) data;
4816
4817 if (!netif_running(bp->dev))
4818 return;
4819
4820 if (!BP_NOMCP(bp)) {
4821 int mb_idx = BP_FW_MB_IDX(bp);
4822 u32 drv_pulse;
4823 u32 mcp_pulse;
4824
4825 ++bp->fw_drv_pulse_wr_seq;
4826 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4827 /* TBD - add SYSTEM_TIME */
4828 drv_pulse = bp->fw_drv_pulse_wr_seq;
4829 bnx2x_drv_pulse(bp);
4830
4831 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
4832 MCP_PULSE_SEQ_MASK);
4833 /* The delta between driver pulse and mcp response
4834 * should be 1 (before mcp response) or 0 (after mcp response)
4835 */
4836 if ((drv_pulse != mcp_pulse) &&
4837 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4838 /* someone lost a heartbeat... */
4839 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4840 drv_pulse, mcp_pulse);
4841 }
4842 }
4843
4844 if (bp->state == BNX2X_STATE_OPEN)
4845 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4846
4847 mod_timer(&bp->timer, jiffies + bp->current_interval);
4848 }
4849
4850 /* end of Statistics */
4851
4852 /* nic init */
4853
4854 /*
4855 * nic init service functions
4856 */
4857
4858 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
4859 {
4860 u32 i;
4861 if (!(len%4) && !(addr%4))
4862 for (i = 0; i < len; i += 4)
4863 REG_WR(bp, addr + i, fill);
4864 else
4865 for (i = 0; i < len; i++)
4866 REG_WR8(bp, addr + i, fill);
4867
4868 }
4869
4870 /* helper: writes FP SP data to FW - data_size in dwords */
4871 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4872 int fw_sb_id,
4873 u32 *sb_data_p,
4874 u32 data_size)
4875 {
4876 int index;
4877 for (index = 0; index < data_size; index++)
4878 REG_WR(bp, BAR_CSTRORM_INTMEM +
4879 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4880 sizeof(u32)*index,
4881 *(sb_data_p + index));
4882 }
4883
4884 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4885 {
4886 u32 *sb_data_p;
4887 u32 data_size = 0;
4888 struct hc_status_block_data_e2 sb_data_e2;
4889 struct hc_status_block_data_e1x sb_data_e1x;
4890
4891 /* disable the function first */
4892 if (!CHIP_IS_E1x(bp)) {
4893 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4894 sb_data_e2.common.state = SB_DISABLED;
4895 sb_data_e2.common.p_func.vf_valid = false;
4896 sb_data_p = (u32 *)&sb_data_e2;
4897 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4898 } else {
4899 memset(&sb_data_e1x, 0,
4900 sizeof(struct hc_status_block_data_e1x));
4901 sb_data_e1x.common.state = SB_DISABLED;
4902 sb_data_e1x.common.p_func.vf_valid = false;
4903 sb_data_p = (u32 *)&sb_data_e1x;
4904 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4905 }
4906 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4907
4908 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4909 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4910 CSTORM_STATUS_BLOCK_SIZE);
4911 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4912 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4913 CSTORM_SYNC_BLOCK_SIZE);
4914 }
4915
4916 /* helper: writes SP SB data to FW */
4917 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4918 struct hc_sp_status_block_data *sp_sb_data)
4919 {
4920 int func = BP_FUNC(bp);
4921 int i;
4922 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4923 REG_WR(bp, BAR_CSTRORM_INTMEM +
4924 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4925 i*sizeof(u32),
4926 *((u32 *)sp_sb_data + i));
4927 }
4928
4929 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4930 {
4931 int func = BP_FUNC(bp);
4932 struct hc_sp_status_block_data sp_sb_data;
4933 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4934
4935 sp_sb_data.state = SB_DISABLED;
4936 sp_sb_data.p_func.vf_valid = false;
4937
4938 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4939
4940 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4941 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4942 CSTORM_SP_STATUS_BLOCK_SIZE);
4943 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4944 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4945 CSTORM_SP_SYNC_BLOCK_SIZE);
4946
4947 }
4948
4949
4950 static inline
4951 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4952 int igu_sb_id, int igu_seg_id)
4953 {
4954 hc_sm->igu_sb_id = igu_sb_id;
4955 hc_sm->igu_seg_id = igu_seg_id;
4956 hc_sm->timer_value = 0xFF;
4957 hc_sm->time_to_expire = 0xFFFFFFFF;
4958 }
4959
4960
4961 /* allocates state machine ids. */
4962 static inline
4963 void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4964 {
4965 /* zero out state machine indices */
4966 /* rx indices */
4967 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4968
4969 /* tx indices */
4970 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4971 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4972 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4973 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4974
4975 /* map indices */
4976 /* rx indices */
4977 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4978 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4979
4980 /* tx indices */
4981 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4982 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4983 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4984 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4985 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4986 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4987 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4988 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4989 }
4990
4991 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4992 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4993 {
4994 int igu_seg_id;
4995
4996 struct hc_status_block_data_e2 sb_data_e2;
4997 struct hc_status_block_data_e1x sb_data_e1x;
4998 struct hc_status_block_sm *hc_sm_p;
4999 int data_size;
5000 u32 *sb_data_p;
5001
5002 if (CHIP_INT_MODE_IS_BC(bp))
5003 igu_seg_id = HC_SEG_ACCESS_NORM;
5004 else
5005 igu_seg_id = IGU_SEG_ACCESS_NORM;
5006
5007 bnx2x_zero_fp_sb(bp, fw_sb_id);
5008
5009 if (!CHIP_IS_E1x(bp)) {
5010 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5011 sb_data_e2.common.state = SB_ENABLED;
5012 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5013 sb_data_e2.common.p_func.vf_id = vfid;
5014 sb_data_e2.common.p_func.vf_valid = vf_valid;
5015 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5016 sb_data_e2.common.same_igu_sb_1b = true;
5017 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5018 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5019 hc_sm_p = sb_data_e2.common.state_machine;
5020 sb_data_p = (u32 *)&sb_data_e2;
5021 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5022 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5023 } else {
5024 memset(&sb_data_e1x, 0,
5025 sizeof(struct hc_status_block_data_e1x));
5026 sb_data_e1x.common.state = SB_ENABLED;
5027 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5028 sb_data_e1x.common.p_func.vf_id = 0xff;
5029 sb_data_e1x.common.p_func.vf_valid = false;
5030 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5031 sb_data_e1x.common.same_igu_sb_1b = true;
5032 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5033 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5034 hc_sm_p = sb_data_e1x.common.state_machine;
5035 sb_data_p = (u32 *)&sb_data_e1x;
5036 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5037 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5038 }
5039
5040 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5041 igu_sb_id, igu_seg_id);
5042 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5043 igu_sb_id, igu_seg_id);
5044
5045 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5046
5047 /* write indecies to HW */
5048 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5049 }
5050
5051 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5052 u16 tx_usec, u16 rx_usec)
5053 {
5054 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5055 false, rx_usec);
5056 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5057 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5058 tx_usec);
5059 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5060 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5061 tx_usec);
5062 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5063 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5064 tx_usec);
5065 }
5066
5067 static void bnx2x_init_def_sb(struct bnx2x *bp)
5068 {
5069 struct host_sp_status_block *def_sb = bp->def_status_blk;
5070 dma_addr_t mapping = bp->def_status_blk_mapping;
5071 int igu_sp_sb_index;
5072 int igu_seg_id;
5073 int port = BP_PORT(bp);
5074 int func = BP_FUNC(bp);
5075 int reg_offset, reg_offset_en5;
5076 u64 section;
5077 int index;
5078 struct hc_sp_status_block_data sp_sb_data;
5079 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5080
5081 if (CHIP_INT_MODE_IS_BC(bp)) {
5082 igu_sp_sb_index = DEF_SB_IGU_ID;
5083 igu_seg_id = HC_SEG_ACCESS_DEF;
5084 } else {
5085 igu_sp_sb_index = bp->igu_dsb_id;
5086 igu_seg_id = IGU_SEG_ACCESS_DEF;
5087 }
5088
5089 /* ATTN */
5090 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5091 atten_status_block);
5092 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5093
5094 bp->attn_state = 0;
5095
5096 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5097 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5098 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5099 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5100 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5101 int sindex;
5102 /* take care of sig[0]..sig[4] */
5103 for (sindex = 0; sindex < 4; sindex++)
5104 bp->attn_group[index].sig[sindex] =
5105 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5106
5107 if (!CHIP_IS_E1x(bp))
5108 /*
5109 * enable5 is separate from the rest of the registers,
5110 * and therefore the address skip is 4
5111 * and not 16 between the different groups
5112 */
5113 bp->attn_group[index].sig[4] = REG_RD(bp,
5114 reg_offset_en5 + 0x4*index);
5115 else
5116 bp->attn_group[index].sig[4] = 0;
5117 }
5118
5119 if (bp->common.int_block == INT_BLOCK_HC) {
5120 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5121 HC_REG_ATTN_MSG0_ADDR_L);
5122
5123 REG_WR(bp, reg_offset, U64_LO(section));
5124 REG_WR(bp, reg_offset + 4, U64_HI(section));
5125 } else if (!CHIP_IS_E1x(bp)) {
5126 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5127 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5128 }
5129
5130 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5131 sp_sb);
5132
5133 bnx2x_zero_sp_sb(bp);
5134
5135 sp_sb_data.state = SB_ENABLED;
5136 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5137 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5138 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5139 sp_sb_data.igu_seg_id = igu_seg_id;
5140 sp_sb_data.p_func.pf_id = func;
5141 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5142 sp_sb_data.p_func.vf_id = 0xff;
5143
5144 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5145
5146 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5147 }
5148
5149 void bnx2x_update_coalesce(struct bnx2x *bp)
5150 {
5151 int i;
5152
5153 for_each_eth_queue(bp, i)
5154 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5155 bp->tx_ticks, bp->rx_ticks);
5156 }
5157
5158 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5159 {
5160 spin_lock_init(&bp->spq_lock);
5161 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5162
5163 bp->spq_prod_idx = 0;
5164 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5165 bp->spq_prod_bd = bp->spq;
5166 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5167 }
5168
5169 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5170 {
5171 int i;
5172 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5173 union event_ring_elem *elem =
5174 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5175
5176 elem->next_page.addr.hi =
5177 cpu_to_le32(U64_HI(bp->eq_mapping +
5178 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5179 elem->next_page.addr.lo =
5180 cpu_to_le32(U64_LO(bp->eq_mapping +
5181 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5182 }
5183 bp->eq_cons = 0;
5184 bp->eq_prod = NUM_EQ_DESC;
5185 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5186 /* we want a warning message before it gets rought... */
5187 atomic_set(&bp->eq_spq_left,
5188 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5189 }
5190
5191
5192 /* called with netif_addr_lock_bh() */
5193 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5194 unsigned long rx_mode_flags,
5195 unsigned long rx_accept_flags,
5196 unsigned long tx_accept_flags,
5197 unsigned long ramrod_flags)
5198 {
5199 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5200 int rc;
5201
5202 memset(&ramrod_param, 0, sizeof(ramrod_param));
5203
5204 /* Prepare ramrod parameters */
5205 ramrod_param.cid = 0;
5206 ramrod_param.cl_id = cl_id;
5207 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5208 ramrod_param.func_id = BP_FUNC(bp);
5209
5210 ramrod_param.pstate = &bp->sp_state;
5211 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5212
5213 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5214 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5215
5216 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5217
5218 ramrod_param.ramrod_flags = ramrod_flags;
5219 ramrod_param.rx_mode_flags = rx_mode_flags;
5220
5221 ramrod_param.rx_accept_flags = rx_accept_flags;
5222 ramrod_param.tx_accept_flags = tx_accept_flags;
5223
5224 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5225 if (rc < 0) {
5226 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5227 return;
5228 }
5229 }
5230
5231 /* called with netif_addr_lock_bh() */
5232 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5233 {
5234 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5235 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5236
5237 #ifdef BCM_CNIC
5238 if (!NO_FCOE(bp))
5239
5240 /* Configure rx_mode of FCoE Queue */
5241 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5242 #endif
5243
5244 switch (bp->rx_mode) {
5245 case BNX2X_RX_MODE_NONE:
5246 /*
5247 * 'drop all' supersedes any accept flags that may have been
5248 * passed to the function.
5249 */
5250 break;
5251 case BNX2X_RX_MODE_NORMAL:
5252 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5253 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5254 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5255
5256 /* internal switching mode */
5257 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5258 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5259 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5260
5261 break;
5262 case BNX2X_RX_MODE_ALLMULTI:
5263 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5264 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5265 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5266
5267 /* internal switching mode */
5268 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5269 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5270 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5271
5272 break;
5273 case BNX2X_RX_MODE_PROMISC:
5274 /* According to deffinition of SI mode, iface in promisc mode
5275 * should receive matched and unmatched (in resolution of port)
5276 * unicast packets.
5277 */
5278 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5279 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5280 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5281 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5282
5283 /* internal switching mode */
5284 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5285 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5286
5287 if (IS_MF_SI(bp))
5288 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5289 else
5290 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5291
5292 break;
5293 default:
5294 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5295 return;
5296 }
5297
5298 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5299 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5300 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5301 }
5302
5303 __set_bit(RAMROD_RX, &ramrod_flags);
5304 __set_bit(RAMROD_TX, &ramrod_flags);
5305
5306 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5307 tx_accept_flags, ramrod_flags);
5308 }
5309
5310 static void bnx2x_init_internal_common(struct bnx2x *bp)
5311 {
5312 int i;
5313
5314 if (IS_MF_SI(bp))
5315 /*
5316 * In switch independent mode, the TSTORM needs to accept
5317 * packets that failed classification, since approximate match
5318 * mac addresses aren't written to NIG LLH
5319 */
5320 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5321 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5322 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5323 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5324 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5325
5326 /* Zero this manually as its initialization is
5327 currently missing in the initTool */
5328 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5329 REG_WR(bp, BAR_USTRORM_INTMEM +
5330 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5331 if (!CHIP_IS_E1x(bp)) {
5332 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5333 CHIP_INT_MODE_IS_BC(bp) ?
5334 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5335 }
5336 }
5337
5338 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5339 {
5340 switch (load_code) {
5341 case FW_MSG_CODE_DRV_LOAD_COMMON:
5342 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5343 bnx2x_init_internal_common(bp);
5344 /* no break */
5345
5346 case FW_MSG_CODE_DRV_LOAD_PORT:
5347 /* nothing to do */
5348 /* no break */
5349
5350 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5351 /* internal memory per function is
5352 initialized inside bnx2x_pf_init */
5353 break;
5354
5355 default:
5356 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5357 break;
5358 }
5359 }
5360
5361 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5362 {
5363 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5364 }
5365
5366 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5367 {
5368 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5369 }
5370
5371 static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5372 {
5373 if (CHIP_IS_E1x(fp->bp))
5374 return BP_L_ID(fp->bp) + fp->index;
5375 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5376 return bnx2x_fp_igu_sb_id(fp);
5377 }
5378
5379 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5380 {
5381 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5382 u8 cos;
5383 unsigned long q_type = 0;
5384 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5385 fp->rx_queue = fp_idx;
5386 fp->cid = fp_idx;
5387 fp->cl_id = bnx2x_fp_cl_id(fp);
5388 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5389 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5390 /* qZone id equals to FW (per path) client id */
5391 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5392
5393 /* init shortcut */
5394 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5395
5396 /* Setup SB indicies */
5397 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5398
5399 /* Configure Queue State object */
5400 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5401 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5402
5403 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5404
5405 /* init tx data */
5406 for_each_cos_in_tx_queue(fp, cos) {
5407 bnx2x_init_txdata(bp, &fp->txdata[cos],
5408 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5409 FP_COS_TO_TXQ(fp, cos),
5410 BNX2X_TX_SB_INDEX_BASE + cos);
5411 cids[cos] = fp->txdata[cos].cid;
5412 }
5413
5414 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5415 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5416 bnx2x_sp_mapping(bp, q_rdata), q_type);
5417
5418 /**
5419 * Configure classification DBs: Always enable Tx switching
5420 */
5421 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5422
5423 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5424 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5425 fp->igu_sb_id);
5426 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5427 fp->fw_sb_id, fp->igu_sb_id);
5428
5429 bnx2x_update_fpsb_idx(fp);
5430 }
5431
5432 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5433 {
5434 int i;
5435
5436 for_each_eth_queue(bp, i)
5437 bnx2x_init_eth_fp(bp, i);
5438 #ifdef BCM_CNIC
5439 if (!NO_FCOE(bp))
5440 bnx2x_init_fcoe_fp(bp);
5441
5442 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5443 BNX2X_VF_ID_INVALID, false,
5444 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5445
5446 #endif
5447
5448 /* Initialize MOD_ABS interrupts */
5449 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5450 bp->common.shmem_base, bp->common.shmem2_base,
5451 BP_PORT(bp));
5452 /* ensure status block indices were read */
5453 rmb();
5454
5455 bnx2x_init_def_sb(bp);
5456 bnx2x_update_dsb_idx(bp);
5457 bnx2x_init_rx_rings(bp);
5458 bnx2x_init_tx_rings(bp);
5459 bnx2x_init_sp_ring(bp);
5460 bnx2x_init_eq_ring(bp);
5461 bnx2x_init_internal(bp, load_code);
5462 bnx2x_pf_init(bp);
5463 bnx2x_stats_init(bp);
5464
5465 /* flush all before enabling interrupts */
5466 mb();
5467 mmiowb();
5468
5469 bnx2x_int_enable(bp);
5470
5471 /* Check for SPIO5 */
5472 bnx2x_attn_int_deasserted0(bp,
5473 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5474 AEU_INPUTS_ATTN_BITS_SPIO5);
5475 }
5476
5477 /* end of nic init */
5478
5479 /*
5480 * gzip service functions
5481 */
5482
5483 static int bnx2x_gunzip_init(struct bnx2x *bp)
5484 {
5485 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5486 &bp->gunzip_mapping, GFP_KERNEL);
5487 if (bp->gunzip_buf == NULL)
5488 goto gunzip_nomem1;
5489
5490 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5491 if (bp->strm == NULL)
5492 goto gunzip_nomem2;
5493
5494 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5495 if (bp->strm->workspace == NULL)
5496 goto gunzip_nomem3;
5497
5498 return 0;
5499
5500 gunzip_nomem3:
5501 kfree(bp->strm);
5502 bp->strm = NULL;
5503
5504 gunzip_nomem2:
5505 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5506 bp->gunzip_mapping);
5507 bp->gunzip_buf = NULL;
5508
5509 gunzip_nomem1:
5510 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
5511 return -ENOMEM;
5512 }
5513
5514 static void bnx2x_gunzip_end(struct bnx2x *bp)
5515 {
5516 if (bp->strm) {
5517 vfree(bp->strm->workspace);
5518 kfree(bp->strm);
5519 bp->strm = NULL;
5520 }
5521
5522 if (bp->gunzip_buf) {
5523 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5524 bp->gunzip_mapping);
5525 bp->gunzip_buf = NULL;
5526 }
5527 }
5528
5529 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5530 {
5531 int n, rc;
5532
5533 /* check gzip header */
5534 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5535 BNX2X_ERR("Bad gzip header\n");
5536 return -EINVAL;
5537 }
5538
5539 n = 10;
5540
5541 #define FNAME 0x8
5542
5543 if (zbuf[3] & FNAME)
5544 while ((zbuf[n++] != 0) && (n < len));
5545
5546 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5547 bp->strm->avail_in = len - n;
5548 bp->strm->next_out = bp->gunzip_buf;
5549 bp->strm->avail_out = FW_BUF_SIZE;
5550
5551 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5552 if (rc != Z_OK)
5553 return rc;
5554
5555 rc = zlib_inflate(bp->strm, Z_FINISH);
5556 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5557 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5558 bp->strm->msg);
5559
5560 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5561 if (bp->gunzip_outlen & 0x3)
5562 netdev_err(bp->dev,
5563 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
5564 bp->gunzip_outlen);
5565 bp->gunzip_outlen >>= 2;
5566
5567 zlib_inflateEnd(bp->strm);
5568
5569 if (rc == Z_STREAM_END)
5570 return 0;
5571
5572 return rc;
5573 }
5574
5575 /* nic load/unload */
5576
5577 /*
5578 * General service functions
5579 */
5580
5581 /* send a NIG loopback debug packet */
5582 static void bnx2x_lb_pckt(struct bnx2x *bp)
5583 {
5584 u32 wb_write[3];
5585
5586 /* Ethernet source and destination addresses */
5587 wb_write[0] = 0x55555555;
5588 wb_write[1] = 0x55555555;
5589 wb_write[2] = 0x20; /* SOP */
5590 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5591
5592 /* NON-IP protocol */
5593 wb_write[0] = 0x09000000;
5594 wb_write[1] = 0x55555555;
5595 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5596 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5597 }
5598
5599 /* some of the internal memories
5600 * are not directly readable from the driver
5601 * to test them we send debug packets
5602 */
5603 static int bnx2x_int_mem_test(struct bnx2x *bp)
5604 {
5605 int factor;
5606 int count, i;
5607 u32 val = 0;
5608
5609 if (CHIP_REV_IS_FPGA(bp))
5610 factor = 120;
5611 else if (CHIP_REV_IS_EMUL(bp))
5612 factor = 200;
5613 else
5614 factor = 1;
5615
5616 /* Disable inputs of parser neighbor blocks */
5617 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5618 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5619 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5620 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5621
5622 /* Write 0 to parser credits for CFC search request */
5623 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5624
5625 /* send Ethernet packet */
5626 bnx2x_lb_pckt(bp);
5627
5628 /* TODO do i reset NIG statistic? */
5629 /* Wait until NIG register shows 1 packet of size 0x10 */
5630 count = 1000 * factor;
5631 while (count) {
5632
5633 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5634 val = *bnx2x_sp(bp, wb_data[0]);
5635 if (val == 0x10)
5636 break;
5637
5638 msleep(10);
5639 count--;
5640 }
5641 if (val != 0x10) {
5642 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5643 return -1;
5644 }
5645
5646 /* Wait until PRS register shows 1 packet */
5647 count = 1000 * factor;
5648 while (count) {
5649 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5650 if (val == 1)
5651 break;
5652
5653 msleep(10);
5654 count--;
5655 }
5656 if (val != 0x1) {
5657 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5658 return -2;
5659 }
5660
5661 /* Reset and init BRB, PRS */
5662 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5663 msleep(50);
5664 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5665 msleep(50);
5666 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5667 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5668
5669 DP(NETIF_MSG_HW, "part2\n");
5670
5671 /* Disable inputs of parser neighbor blocks */
5672 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5673 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5674 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5675 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5676
5677 /* Write 0 to parser credits for CFC search request */
5678 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5679
5680 /* send 10 Ethernet packets */
5681 for (i = 0; i < 10; i++)
5682 bnx2x_lb_pckt(bp);
5683
5684 /* Wait until NIG register shows 10 + 1
5685 packets of size 11*0x10 = 0xb0 */
5686 count = 1000 * factor;
5687 while (count) {
5688
5689 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5690 val = *bnx2x_sp(bp, wb_data[0]);
5691 if (val == 0xb0)
5692 break;
5693
5694 msleep(10);
5695 count--;
5696 }
5697 if (val != 0xb0) {
5698 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5699 return -3;
5700 }
5701
5702 /* Wait until PRS register shows 2 packets */
5703 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5704 if (val != 2)
5705 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5706
5707 /* Write 1 to parser credits for CFC search request */
5708 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5709
5710 /* Wait until PRS register shows 3 packets */
5711 msleep(10 * factor);
5712 /* Wait until NIG register shows 1 packet of size 0x10 */
5713 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5714 if (val != 3)
5715 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5716
5717 /* clear NIG EOP FIFO */
5718 for (i = 0; i < 11; i++)
5719 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5720 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5721 if (val != 1) {
5722 BNX2X_ERR("clear of NIG failed\n");
5723 return -4;
5724 }
5725
5726 /* Reset and init BRB, PRS, NIG */
5727 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5728 msleep(50);
5729 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5730 msleep(50);
5731 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5732 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5733 #ifndef BCM_CNIC
5734 /* set NIC mode */
5735 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5736 #endif
5737
5738 /* Enable inputs of parser neighbor blocks */
5739 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5740 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5741 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5742 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5743
5744 DP(NETIF_MSG_HW, "done\n");
5745
5746 return 0; /* OK */
5747 }
5748
5749 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
5750 {
5751 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5752 if (!CHIP_IS_E1x(bp))
5753 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5754 else
5755 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5756 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5757 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5758 /*
5759 * mask read length error interrupts in brb for parser
5760 * (parsing unit and 'checksum and crc' unit)
5761 * these errors are legal (PU reads fixed length and CAC can cause
5762 * read length error on truncated packets)
5763 */
5764 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
5765 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5766 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5767 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5768 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5769 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5770 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5771 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5772 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5773 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5774 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5775 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5776 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5777 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5778 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5779 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5780 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5781 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5782 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5783
5784 if (CHIP_REV_IS_FPGA(bp))
5785 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5786 else if (!CHIP_IS_E1x(bp))
5787 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5788 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5789 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5790 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5791 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5792 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
5793 else
5794 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5795 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5796 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5797 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5798 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5799
5800 if (!CHIP_IS_E1x(bp))
5801 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5802 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5803
5804 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5805 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5806 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5807 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
5808 }
5809
5810 static void bnx2x_reset_common(struct bnx2x *bp)
5811 {
5812 u32 val = 0x1400;
5813
5814 /* reset_common */
5815 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5816 0xd3ffff7f);
5817
5818 if (CHIP_IS_E3(bp)) {
5819 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5820 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5821 }
5822
5823 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5824 }
5825
5826 static void bnx2x_setup_dmae(struct bnx2x *bp)
5827 {
5828 bp->dmae_ready = 0;
5829 spin_lock_init(&bp->dmae_lock);
5830 }
5831
5832 static void bnx2x_init_pxp(struct bnx2x *bp)
5833 {
5834 u16 devctl;
5835 int r_order, w_order;
5836
5837 pci_read_config_word(bp->pdev,
5838 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
5839 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5840 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5841 if (bp->mrrs == -1)
5842 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5843 else {
5844 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5845 r_order = bp->mrrs;
5846 }
5847
5848 bnx2x_init_pxp_arb(bp, r_order, w_order);
5849 }
5850
5851 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5852 {
5853 int is_required;
5854 u32 val;
5855 int port;
5856
5857 if (BP_NOMCP(bp))
5858 return;
5859
5860 is_required = 0;
5861 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5862 SHARED_HW_CFG_FAN_FAILURE_MASK;
5863
5864 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5865 is_required = 1;
5866
5867 /*
5868 * The fan failure mechanism is usually related to the PHY type since
5869 * the power consumption of the board is affected by the PHY. Currently,
5870 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5871 */
5872 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5873 for (port = PORT_0; port < PORT_MAX; port++) {
5874 is_required |=
5875 bnx2x_fan_failure_det_req(
5876 bp,
5877 bp->common.shmem_base,
5878 bp->common.shmem2_base,
5879 port);
5880 }
5881
5882 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5883
5884 if (is_required == 0)
5885 return;
5886
5887 /* Fan failure is indicated by SPIO 5 */
5888 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5889 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5890
5891 /* set to active low mode */
5892 val = REG_RD(bp, MISC_REG_SPIO_INT);
5893 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5894 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5895 REG_WR(bp, MISC_REG_SPIO_INT, val);
5896
5897 /* enable interrupt to signal the IGU */
5898 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5899 val |= (1 << MISC_REGISTERS_SPIO_5);
5900 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5901 }
5902
5903 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5904 {
5905 u32 offset = 0;
5906
5907 if (CHIP_IS_E1(bp))
5908 return;
5909 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5910 return;
5911
5912 switch (BP_ABS_FUNC(bp)) {
5913 case 0:
5914 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5915 break;
5916 case 1:
5917 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5918 break;
5919 case 2:
5920 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5921 break;
5922 case 3:
5923 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5924 break;
5925 case 4:
5926 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5927 break;
5928 case 5:
5929 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5930 break;
5931 case 6:
5932 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5933 break;
5934 case 7:
5935 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5936 break;
5937 default:
5938 return;
5939 }
5940
5941 REG_WR(bp, offset, pretend_func_num);
5942 REG_RD(bp, offset);
5943 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5944 }
5945
5946 void bnx2x_pf_disable(struct bnx2x *bp)
5947 {
5948 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5949 val &= ~IGU_PF_CONF_FUNC_EN;
5950
5951 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5952 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5953 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5954 }
5955
5956 static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5957 {
5958 u32 shmem_base[2], shmem2_base[2];
5959 shmem_base[0] = bp->common.shmem_base;
5960 shmem2_base[0] = bp->common.shmem2_base;
5961 if (!CHIP_IS_E1x(bp)) {
5962 shmem_base[1] =
5963 SHMEM2_RD(bp, other_shmem_base_addr);
5964 shmem2_base[1] =
5965 SHMEM2_RD(bp, other_shmem2_base_addr);
5966 }
5967 bnx2x_acquire_phy_lock(bp);
5968 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5969 bp->common.chip_id);
5970 bnx2x_release_phy_lock(bp);
5971 }
5972
5973 /**
5974 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5975 *
5976 * @bp: driver handle
5977 */
5978 static int bnx2x_init_hw_common(struct bnx2x *bp)
5979 {
5980 u32 val;
5981
5982 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
5983
5984 /*
5985 * take the UNDI lock to protect undi_unload flow from accessing
5986 * registers while we're resetting the chip
5987 */
5988 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
5989
5990 bnx2x_reset_common(bp);
5991 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5992
5993 val = 0xfffc;
5994 if (CHIP_IS_E3(bp)) {
5995 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5996 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5997 }
5998 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5999
6000 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6001
6002 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6003
6004 if (!CHIP_IS_E1x(bp)) {
6005 u8 abs_func_id;
6006
6007 /**
6008 * 4-port mode or 2-port mode we need to turn of master-enable
6009 * for everyone, after that, turn it back on for self.
6010 * so, we disregard multi-function or not, and always disable
6011 * for all functions on the given path, this means 0,2,4,6 for
6012 * path 0 and 1,3,5,7 for path 1
6013 */
6014 for (abs_func_id = BP_PATH(bp);
6015 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6016 if (abs_func_id == BP_ABS_FUNC(bp)) {
6017 REG_WR(bp,
6018 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6019 1);
6020 continue;
6021 }
6022
6023 bnx2x_pretend_func(bp, abs_func_id);
6024 /* clear pf enable */
6025 bnx2x_pf_disable(bp);
6026 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6027 }
6028 }
6029
6030 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6031 if (CHIP_IS_E1(bp)) {
6032 /* enable HW interrupt from PXP on USDM overflow
6033 bit 16 on INT_MASK_0 */
6034 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6035 }
6036
6037 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6038 bnx2x_init_pxp(bp);
6039
6040 #ifdef __BIG_ENDIAN
6041 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6042 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6043 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6044 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6045 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6046 /* make sure this value is 0 */
6047 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6048
6049 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6050 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6051 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6052 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6053 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6054 #endif
6055
6056 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6057
6058 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6059 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6060
6061 /* let the HW do it's magic ... */
6062 msleep(100);
6063 /* finish PXP init */
6064 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6065 if (val != 1) {
6066 BNX2X_ERR("PXP2 CFG failed\n");
6067 return -EBUSY;
6068 }
6069 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6070 if (val != 1) {
6071 BNX2X_ERR("PXP2 RD_INIT failed\n");
6072 return -EBUSY;
6073 }
6074
6075 /* Timers bug workaround E2 only. We need to set the entire ILT to
6076 * have entries with value "0" and valid bit on.
6077 * This needs to be done by the first PF that is loaded in a path
6078 * (i.e. common phase)
6079 */
6080 if (!CHIP_IS_E1x(bp)) {
6081 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6082 * (i.e. vnic3) to start even if it is marked as "scan-off".
6083 * This occurs when a different function (func2,3) is being marked
6084 * as "scan-off". Real-life scenario for example: if a driver is being
6085 * load-unloaded while func6,7 are down. This will cause the timer to access
6086 * the ilt, translate to a logical address and send a request to read/write.
6087 * Since the ilt for the function that is down is not valid, this will cause
6088 * a translation error which is unrecoverable.
6089 * The Workaround is intended to make sure that when this happens nothing fatal
6090 * will occur. The workaround:
6091 * 1. First PF driver which loads on a path will:
6092 * a. After taking the chip out of reset, by using pretend,
6093 * it will write "0" to the following registers of
6094 * the other vnics.
6095 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6096 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6097 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6098 * And for itself it will write '1' to
6099 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6100 * dmae-operations (writing to pram for example.)
6101 * note: can be done for only function 6,7 but cleaner this
6102 * way.
6103 * b. Write zero+valid to the entire ILT.
6104 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6105 * VNIC3 (of that port). The range allocated will be the
6106 * entire ILT. This is needed to prevent ILT range error.
6107 * 2. Any PF driver load flow:
6108 * a. ILT update with the physical addresses of the allocated
6109 * logical pages.
6110 * b. Wait 20msec. - note that this timeout is needed to make
6111 * sure there are no requests in one of the PXP internal
6112 * queues with "old" ILT addresses.
6113 * c. PF enable in the PGLC.
6114 * d. Clear the was_error of the PF in the PGLC. (could have
6115 * occured while driver was down)
6116 * e. PF enable in the CFC (WEAK + STRONG)
6117 * f. Timers scan enable
6118 * 3. PF driver unload flow:
6119 * a. Clear the Timers scan_en.
6120 * b. Polling for scan_on=0 for that PF.
6121 * c. Clear the PF enable bit in the PXP.
6122 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6123 * e. Write zero+valid to all ILT entries (The valid bit must
6124 * stay set)
6125 * f. If this is VNIC 3 of a port then also init
6126 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6127 * to the last enrty in the ILT.
6128 *
6129 * Notes:
6130 * Currently the PF error in the PGLC is non recoverable.
6131 * In the future the there will be a recovery routine for this error.
6132 * Currently attention is masked.
6133 * Having an MCP lock on the load/unload process does not guarantee that
6134 * there is no Timer disable during Func6/7 enable. This is because the
6135 * Timers scan is currently being cleared by the MCP on FLR.
6136 * Step 2.d can be done only for PF6/7 and the driver can also check if
6137 * there is error before clearing it. But the flow above is simpler and
6138 * more general.
6139 * All ILT entries are written by zero+valid and not just PF6/7
6140 * ILT entries since in the future the ILT entries allocation for
6141 * PF-s might be dynamic.
6142 */
6143 struct ilt_client_info ilt_cli;
6144 struct bnx2x_ilt ilt;
6145 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6146 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6147
6148 /* initialize dummy TM client */
6149 ilt_cli.start = 0;
6150 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6151 ilt_cli.client_num = ILT_CLIENT_TM;
6152
6153 /* Step 1: set zeroes to all ilt page entries with valid bit on
6154 * Step 2: set the timers first/last ilt entry to point
6155 * to the entire range to prevent ILT range error for 3rd/4th
6156 * vnic (this code assumes existance of the vnic)
6157 *
6158 * both steps performed by call to bnx2x_ilt_client_init_op()
6159 * with dummy TM client
6160 *
6161 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6162 * and his brother are split registers
6163 */
6164 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6165 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6166 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6167
6168 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6169 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6170 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6171 }
6172
6173
6174 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6175 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6176
6177 if (!CHIP_IS_E1x(bp)) {
6178 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6179 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6180 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6181
6182 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6183
6184 /* let the HW do it's magic ... */
6185 do {
6186 msleep(200);
6187 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6188 } while (factor-- && (val != 1));
6189
6190 if (val != 1) {
6191 BNX2X_ERR("ATC_INIT failed\n");
6192 return -EBUSY;
6193 }
6194 }
6195
6196 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6197
6198 /* clean the DMAE memory */
6199 bp->dmae_ready = 1;
6200 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6201
6202 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6203
6204 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6205
6206 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6207
6208 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6209
6210 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6211 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6212 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6213 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6214
6215 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6216
6217
6218 /* QM queues pointers table */
6219 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6220
6221 /* soft reset pulse */
6222 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6223 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6224
6225 #ifdef BCM_CNIC
6226 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6227 #endif
6228
6229 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6230 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6231 if (!CHIP_REV_IS_SLOW(bp))
6232 /* enable hw interrupt from doorbell Q */
6233 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6234
6235 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6236
6237 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6238 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6239
6240 if (!CHIP_IS_E1(bp))
6241 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6242
6243 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6244 /* Bit-map indicating which L2 hdrs may appear
6245 * after the basic Ethernet header
6246 */
6247 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6248 bp->path_has_ovlan ? 7 : 6);
6249
6250 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6251 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6252 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6253 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6254
6255 if (!CHIP_IS_E1x(bp)) {
6256 /* reset VFC memories */
6257 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6258 VFC_MEMORIES_RST_REG_CAM_RST |
6259 VFC_MEMORIES_RST_REG_RAM_RST);
6260 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6261 VFC_MEMORIES_RST_REG_CAM_RST |
6262 VFC_MEMORIES_RST_REG_RAM_RST);
6263
6264 msleep(20);
6265 }
6266
6267 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6268 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6269 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6270 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6271
6272 /* sync semi rtc */
6273 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6274 0x80000000);
6275 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6276 0x80000000);
6277
6278 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6279 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6280 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6281
6282 if (!CHIP_IS_E1x(bp))
6283 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6284 bp->path_has_ovlan ? 7 : 6);
6285
6286 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6287
6288 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6289
6290 #ifdef BCM_CNIC
6291 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6292 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6293 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6294 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6295 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6296 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6297 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6298 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6299 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6300 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6301 #endif
6302 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6303
6304 if (sizeof(union cdu_context) != 1024)
6305 /* we currently assume that a context is 1024 bytes */
6306 dev_alert(&bp->pdev->dev,
6307 "please adjust the size of cdu_context(%ld)\n",
6308 (long)sizeof(union cdu_context));
6309
6310 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6311 val = (4 << 24) + (0 << 12) + 1024;
6312 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6313
6314 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6315 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6316 /* enable context validation interrupt from CFC */
6317 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6318
6319 /* set the thresholds to prevent CFC/CDU race */
6320 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6321
6322 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6323
6324 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6325 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6326
6327 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6328 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6329
6330 /* Reset PCIE errors for debug */
6331 REG_WR(bp, 0x2814, 0xffffffff);
6332 REG_WR(bp, 0x3820, 0xffffffff);
6333
6334 if (!CHIP_IS_E1x(bp)) {
6335 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6336 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6337 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6338 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6339 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6340 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6341 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6342 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6343 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6344 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6345 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6346 }
6347
6348 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6349 if (!CHIP_IS_E1(bp)) {
6350 /* in E3 this done in per-port section */
6351 if (!CHIP_IS_E3(bp))
6352 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6353 }
6354 if (CHIP_IS_E1H(bp))
6355 /* not applicable for E2 (and above ...) */
6356 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6357
6358 if (CHIP_REV_IS_SLOW(bp))
6359 msleep(200);
6360
6361 /* finish CFC init */
6362 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6363 if (val != 1) {
6364 BNX2X_ERR("CFC LL_INIT failed\n");
6365 return -EBUSY;
6366 }
6367 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6368 if (val != 1) {
6369 BNX2X_ERR("CFC AC_INIT failed\n");
6370 return -EBUSY;
6371 }
6372 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6373 if (val != 1) {
6374 BNX2X_ERR("CFC CAM_INIT failed\n");
6375 return -EBUSY;
6376 }
6377 REG_WR(bp, CFC_REG_DEBUG0, 0);
6378
6379 if (CHIP_IS_E1(bp)) {
6380 /* read NIG statistic
6381 to see if this is our first up since powerup */
6382 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6383 val = *bnx2x_sp(bp, wb_data[0]);
6384
6385 /* do internal memory self test */
6386 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6387 BNX2X_ERR("internal mem self test failed\n");
6388 return -EBUSY;
6389 }
6390 }
6391
6392 bnx2x_setup_fan_failure_detection(bp);
6393
6394 /* clear PXP2 attentions */
6395 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6396
6397 bnx2x_enable_blocks_attention(bp);
6398 bnx2x_enable_blocks_parity(bp);
6399
6400 if (!BP_NOMCP(bp)) {
6401 if (CHIP_IS_E1x(bp))
6402 bnx2x__common_init_phy(bp);
6403 } else
6404 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6405
6406 return 0;
6407 }
6408
6409 /**
6410 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6411 *
6412 * @bp: driver handle
6413 */
6414 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6415 {
6416 int rc = bnx2x_init_hw_common(bp);
6417
6418 if (rc)
6419 return rc;
6420
6421 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6422 if (!BP_NOMCP(bp))
6423 bnx2x__common_init_phy(bp);
6424
6425 return 0;
6426 }
6427
6428 static int bnx2x_init_hw_port(struct bnx2x *bp)
6429 {
6430 int port = BP_PORT(bp);
6431 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6432 u32 low, high;
6433 u32 val;
6434
6435 bnx2x__link_reset(bp);
6436
6437 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
6438
6439 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6440
6441 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6442 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6443 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6444
6445 /* Timers bug workaround: disables the pf_master bit in pglue at
6446 * common phase, we need to enable it here before any dmae access are
6447 * attempted. Therefore we manually added the enable-master to the
6448 * port phase (it also happens in the function phase)
6449 */
6450 if (!CHIP_IS_E1x(bp))
6451 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6452
6453 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6454 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6455 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6456 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6457
6458 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6459 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6460 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6461 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6462
6463 /* QM cid (connection) count */
6464 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6465
6466 #ifdef BCM_CNIC
6467 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6468 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6469 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6470 #endif
6471
6472 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6473
6474 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6475 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6476
6477 if (IS_MF(bp))
6478 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6479 else if (bp->dev->mtu > 4096) {
6480 if (bp->flags & ONE_PORT_FLAG)
6481 low = 160;
6482 else {
6483 val = bp->dev->mtu;
6484 /* (24*1024 + val*4)/256 */
6485 low = 96 + (val/64) +
6486 ((val % 64) ? 1 : 0);
6487 }
6488 } else
6489 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6490 high = low + 56; /* 14*1024/256 */
6491 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6492 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6493 }
6494
6495 if (CHIP_MODE_IS_4_PORT(bp))
6496 REG_WR(bp, (BP_PORT(bp) ?
6497 BRB1_REG_MAC_GUARANTIED_1 :
6498 BRB1_REG_MAC_GUARANTIED_0), 40);
6499
6500
6501 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6502 if (CHIP_IS_E3B0(bp))
6503 /* Ovlan exists only if we are in multi-function +
6504 * switch-dependent mode, in switch-independent there
6505 * is no ovlan headers
6506 */
6507 REG_WR(bp, BP_PORT(bp) ?
6508 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6509 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6510 (bp->path_has_ovlan ? 7 : 6));
6511
6512 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6513 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6514 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6515 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6516
6517 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6518 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6519 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6520 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6521
6522 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6523 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6524
6525 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6526
6527 if (CHIP_IS_E1x(bp)) {
6528 /* configure PBF to work without PAUSE mtu 9000 */
6529 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6530
6531 /* update threshold */
6532 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6533 /* update init credit */
6534 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6535
6536 /* probe changes */
6537 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6538 udelay(50);
6539 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6540 }
6541
6542 #ifdef BCM_CNIC
6543 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6544 #endif
6545 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6546 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6547
6548 if (CHIP_IS_E1(bp)) {
6549 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6550 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6551 }
6552 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6553
6554 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6555
6556 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6557 /* init aeu_mask_attn_func_0/1:
6558 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6559 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6560 * bits 4-7 are used for "per vn group attention" */
6561 val = IS_MF(bp) ? 0xF7 : 0x7;
6562 /* Enable DCBX attention for all but E1 */
6563 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6564 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6565
6566 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6567
6568 if (!CHIP_IS_E1x(bp)) {
6569 /* Bit-map indicating which L2 hdrs may appear after the
6570 * basic Ethernet header
6571 */
6572 REG_WR(bp, BP_PORT(bp) ?
6573 NIG_REG_P1_HDRS_AFTER_BASIC :
6574 NIG_REG_P0_HDRS_AFTER_BASIC,
6575 IS_MF_SD(bp) ? 7 : 6);
6576
6577 if (CHIP_IS_E3(bp))
6578 REG_WR(bp, BP_PORT(bp) ?
6579 NIG_REG_LLH1_MF_MODE :
6580 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6581 }
6582 if (!CHIP_IS_E3(bp))
6583 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6584
6585 if (!CHIP_IS_E1(bp)) {
6586 /* 0x2 disable mf_ov, 0x1 enable */
6587 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6588 (IS_MF_SD(bp) ? 0x1 : 0x2));
6589
6590 if (!CHIP_IS_E1x(bp)) {
6591 val = 0;
6592 switch (bp->mf_mode) {
6593 case MULTI_FUNCTION_SD:
6594 val = 1;
6595 break;
6596 case MULTI_FUNCTION_SI:
6597 val = 2;
6598 break;
6599 }
6600
6601 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6602 NIG_REG_LLH0_CLS_TYPE), val);
6603 }
6604 {
6605 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6606 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6607 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6608 }
6609 }
6610
6611
6612 /* If SPIO5 is set to generate interrupts, enable it for this port */
6613 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6614 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6615 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6616 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6617 val = REG_RD(bp, reg_addr);
6618 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6619 REG_WR(bp, reg_addr, val);
6620 }
6621
6622 return 0;
6623 }
6624
6625 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6626 {
6627 int reg;
6628
6629 if (CHIP_IS_E1(bp))
6630 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6631 else
6632 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6633
6634 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6635 }
6636
6637 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6638 {
6639 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
6640 }
6641
6642 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6643 {
6644 u32 i, base = FUNC_ILT_BASE(func);
6645 for (i = base; i < base + ILT_PER_FUNC; i++)
6646 bnx2x_ilt_wr(bp, i, 0);
6647 }
6648
6649 static int bnx2x_init_hw_func(struct bnx2x *bp)
6650 {
6651 int port = BP_PORT(bp);
6652 int func = BP_FUNC(bp);
6653 int init_phase = PHASE_PF0 + func;
6654 struct bnx2x_ilt *ilt = BP_ILT(bp);
6655 u16 cdu_ilt_start;
6656 u32 addr, val;
6657 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6658 int i, main_mem_width, rc;
6659
6660 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
6661
6662 /* FLR cleanup - hmmm */
6663 if (!CHIP_IS_E1x(bp)) {
6664 rc = bnx2x_pf_flr_clnup(bp);
6665 if (rc)
6666 return rc;
6667 }
6668
6669 /* set MSI reconfigure capability */
6670 if (bp->common.int_block == INT_BLOCK_HC) {
6671 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6672 val = REG_RD(bp, addr);
6673 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6674 REG_WR(bp, addr, val);
6675 }
6676
6677 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6678 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6679
6680 ilt = BP_ILT(bp);
6681 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
6682
6683 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6684 ilt->lines[cdu_ilt_start + i].page =
6685 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6686 ilt->lines[cdu_ilt_start + i].page_mapping =
6687 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6688 /* cdu ilt pages are allocated manually so there's no need to
6689 set the size */
6690 }
6691 bnx2x_ilt_init_op(bp, INITOP_SET);
6692
6693 #ifdef BCM_CNIC
6694 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
6695
6696 /* T1 hash bits value determines the T1 number of entries */
6697 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6698 #endif
6699
6700 #ifndef BCM_CNIC
6701 /* set NIC mode */
6702 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6703 #endif /* BCM_CNIC */
6704
6705 if (!CHIP_IS_E1x(bp)) {
6706 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6707
6708 /* Turn on a single ISR mode in IGU if driver is going to use
6709 * INT#x or MSI
6710 */
6711 if (!(bp->flags & USING_MSIX_FLAG))
6712 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6713 /*
6714 * Timers workaround bug: function init part.
6715 * Need to wait 20msec after initializing ILT,
6716 * needed to make sure there are no requests in
6717 * one of the PXP internal queues with "old" ILT addresses
6718 */
6719 msleep(20);
6720 /*
6721 * Master enable - Due to WB DMAE writes performed before this
6722 * register is re-initialized as part of the regular function
6723 * init
6724 */
6725 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6726 /* Enable the function in IGU */
6727 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6728 }
6729
6730 bp->dmae_ready = 1;
6731
6732 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6733
6734 if (!CHIP_IS_E1x(bp))
6735 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6736
6737 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6738 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6739 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6740 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6741 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6742 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6743 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6744 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6745 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6746 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6747 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6748 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6749 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6750
6751 if (!CHIP_IS_E1x(bp))
6752 REG_WR(bp, QM_REG_PF_EN, 1);
6753
6754 if (!CHIP_IS_E1x(bp)) {
6755 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6756 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6757 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6758 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6759 }
6760 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6761
6762 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6763 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6764 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6765 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6766 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6767 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6768 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6769 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6770 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6771 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6772 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6773 if (!CHIP_IS_E1x(bp))
6774 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6775
6776 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6777
6778 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6779
6780 if (!CHIP_IS_E1x(bp))
6781 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6782
6783 if (IS_MF(bp)) {
6784 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
6785 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
6786 }
6787
6788 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6789
6790 /* HC init per function */
6791 if (bp->common.int_block == INT_BLOCK_HC) {
6792 if (CHIP_IS_E1H(bp)) {
6793 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6794
6795 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6796 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6797 }
6798 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6799
6800 } else {
6801 int num_segs, sb_idx, prod_offset;
6802
6803 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6804
6805 if (!CHIP_IS_E1x(bp)) {
6806 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6807 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6808 }
6809
6810 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6811
6812 if (!CHIP_IS_E1x(bp)) {
6813 int dsb_idx = 0;
6814 /**
6815 * Producer memory:
6816 * E2 mode: address 0-135 match to the mapping memory;
6817 * 136 - PF0 default prod; 137 - PF1 default prod;
6818 * 138 - PF2 default prod; 139 - PF3 default prod;
6819 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6820 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6821 * 144-147 reserved.
6822 *
6823 * E1.5 mode - In backward compatible mode;
6824 * for non default SB; each even line in the memory
6825 * holds the U producer and each odd line hold
6826 * the C producer. The first 128 producers are for
6827 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6828 * producers are for the DSB for each PF.
6829 * Each PF has five segments: (the order inside each
6830 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6831 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6832 * 144-147 attn prods;
6833 */
6834 /* non-default-status-blocks */
6835 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6836 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6837 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6838 prod_offset = (bp->igu_base_sb + sb_idx) *
6839 num_segs;
6840
6841 for (i = 0; i < num_segs; i++) {
6842 addr = IGU_REG_PROD_CONS_MEMORY +
6843 (prod_offset + i) * 4;
6844 REG_WR(bp, addr, 0);
6845 }
6846 /* send consumer update with value 0 */
6847 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6848 USTORM_ID, 0, IGU_INT_NOP, 1);
6849 bnx2x_igu_clear_sb(bp,
6850 bp->igu_base_sb + sb_idx);
6851 }
6852
6853 /* default-status-blocks */
6854 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6855 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6856
6857 if (CHIP_MODE_IS_4_PORT(bp))
6858 dsb_idx = BP_FUNC(bp);
6859 else
6860 dsb_idx = BP_VN(bp);
6861
6862 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6863 IGU_BC_BASE_DSB_PROD + dsb_idx :
6864 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6865
6866 /*
6867 * igu prods come in chunks of E1HVN_MAX (4) -
6868 * does not matters what is the current chip mode
6869 */
6870 for (i = 0; i < (num_segs * E1HVN_MAX);
6871 i += E1HVN_MAX) {
6872 addr = IGU_REG_PROD_CONS_MEMORY +
6873 (prod_offset + i)*4;
6874 REG_WR(bp, addr, 0);
6875 }
6876 /* send consumer update with 0 */
6877 if (CHIP_INT_MODE_IS_BC(bp)) {
6878 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6879 USTORM_ID, 0, IGU_INT_NOP, 1);
6880 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6881 CSTORM_ID, 0, IGU_INT_NOP, 1);
6882 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6883 XSTORM_ID, 0, IGU_INT_NOP, 1);
6884 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6885 TSTORM_ID, 0, IGU_INT_NOP, 1);
6886 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6887 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6888 } else {
6889 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6890 USTORM_ID, 0, IGU_INT_NOP, 1);
6891 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6892 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6893 }
6894 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6895
6896 /* !!! these should become driver const once
6897 rf-tool supports split-68 const */
6898 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6899 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6900 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6901 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6902 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6903 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6904 }
6905 }
6906
6907 /* Reset PCIE errors for debug */
6908 REG_WR(bp, 0x2114, 0xffffffff);
6909 REG_WR(bp, 0x2120, 0xffffffff);
6910
6911 if (CHIP_IS_E1x(bp)) {
6912 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6913 main_mem_base = HC_REG_MAIN_MEMORY +
6914 BP_PORT(bp) * (main_mem_size * 4);
6915 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6916 main_mem_width = 8;
6917
6918 val = REG_RD(bp, main_mem_prty_clr);
6919 if (val)
6920 DP(NETIF_MSG_HW,
6921 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
6922 val);
6923
6924 /* Clear "false" parity errors in MSI-X table */
6925 for (i = main_mem_base;
6926 i < main_mem_base + main_mem_size * 4;
6927 i += main_mem_width) {
6928 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6929 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6930 i, main_mem_width / 4);
6931 }
6932 /* Clear HC parity attention */
6933 REG_RD(bp, main_mem_prty_clr);
6934 }
6935
6936 #ifdef BNX2X_STOP_ON_ERROR
6937 /* Enable STORMs SP logging */
6938 REG_WR8(bp, BAR_USTRORM_INTMEM +
6939 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6940 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6941 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6942 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6943 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6944 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6945 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6946 #endif
6947
6948 bnx2x_phy_probe(&bp->link_params);
6949
6950 return 0;
6951 }
6952
6953
6954 void bnx2x_free_mem(struct bnx2x *bp)
6955 {
6956 /* fastpath */
6957 bnx2x_free_fp_mem(bp);
6958 /* end of fastpath */
6959
6960 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6961 sizeof(struct host_sp_status_block));
6962
6963 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6964 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6965
6966 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6967 sizeof(struct bnx2x_slowpath));
6968
6969 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6970 bp->context.size);
6971
6972 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6973
6974 BNX2X_FREE(bp->ilt->lines);
6975
6976 #ifdef BCM_CNIC
6977 if (!CHIP_IS_E1x(bp))
6978 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6979 sizeof(struct host_hc_status_block_e2));
6980 else
6981 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6982 sizeof(struct host_hc_status_block_e1x));
6983
6984 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
6985 #endif
6986
6987 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6988
6989 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6990 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6991 }
6992
6993 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6994 {
6995 int num_groups;
6996 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
6997
6998 /* number of queues for statistics is number of eth queues + FCoE */
6999 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
7000
7001 /* Total number of FW statistics requests =
7002 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7003 * num of queues
7004 */
7005 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
7006
7007
7008 /* Request is built from stats_query_header and an array of
7009 * stats_query_cmd_group each of which contains
7010 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7011 * configured in the stats_query_header.
7012 */
7013 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
7014 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
7015
7016 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
7017 num_groups * sizeof(struct stats_query_cmd_group);
7018
7019 /* Data for statistics requests + stats_conter
7020 *
7021 * stats_counter holds per-STORM counters that are incremented
7022 * when STORM has finished with the current request.
7023 *
7024 * memory for FCoE offloaded statistics are counted anyway,
7025 * even if they will not be sent.
7026 */
7027 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
7028 sizeof(struct per_pf_stats) +
7029 sizeof(struct fcoe_statistics_params) +
7030 sizeof(struct per_queue_stats) * num_queue_stats +
7031 sizeof(struct stats_counter);
7032
7033 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
7034 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7035
7036 /* Set shortcuts */
7037 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
7038 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
7039
7040 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
7041 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
7042
7043 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
7044 bp->fw_stats_req_sz;
7045 return 0;
7046
7047 alloc_mem_err:
7048 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7049 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7050 BNX2X_ERR("Can't allocate memory\n");
7051 return -ENOMEM;
7052 }
7053
7054
7055 int bnx2x_alloc_mem(struct bnx2x *bp)
7056 {
7057 #ifdef BCM_CNIC
7058 if (!CHIP_IS_E1x(bp))
7059 /* size = the status block + ramrod buffers */
7060 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7061 sizeof(struct host_hc_status_block_e2));
7062 else
7063 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
7064 sizeof(struct host_hc_status_block_e1x));
7065
7066 /* allocate searcher T2 table */
7067 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7068 #endif
7069
7070
7071 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7072 sizeof(struct host_sp_status_block));
7073
7074 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7075 sizeof(struct bnx2x_slowpath));
7076
7077 #ifdef BCM_CNIC
7078 /* write address to which L5 should insert its values */
7079 bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp;
7080 #endif
7081
7082 /* Allocated memory for FW statistics */
7083 if (bnx2x_alloc_fw_stats_mem(bp))
7084 goto alloc_mem_err;
7085
7086 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7087
7088 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
7089 bp->context.size);
7090
7091 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7092
7093 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7094 goto alloc_mem_err;
7095
7096 /* Slow path ring */
7097 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7098
7099 /* EQ */
7100 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7101 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7102
7103
7104 /* fastpath */
7105 /* need to be done at the end, since it's self adjusting to amount
7106 * of memory available for RSS queues
7107 */
7108 if (bnx2x_alloc_fp_mem(bp))
7109 goto alloc_mem_err;
7110 return 0;
7111
7112 alloc_mem_err:
7113 bnx2x_free_mem(bp);
7114 BNX2X_ERR("Can't allocate memory\n");
7115 return -ENOMEM;
7116 }
7117
7118 /*
7119 * Init service functions
7120 */
7121
7122 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7123 struct bnx2x_vlan_mac_obj *obj, bool set,
7124 int mac_type, unsigned long *ramrod_flags)
7125 {
7126 int rc;
7127 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7128
7129 memset(&ramrod_param, 0, sizeof(ramrod_param));
7130
7131 /* Fill general parameters */
7132 ramrod_param.vlan_mac_obj = obj;
7133 ramrod_param.ramrod_flags = *ramrod_flags;
7134
7135 /* Fill a user request section if needed */
7136 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7137 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7138
7139 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7140
7141 /* Set the command: ADD or DEL */
7142 if (set)
7143 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7144 else
7145 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7146 }
7147
7148 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7149 if (rc < 0)
7150 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7151 return rc;
7152 }
7153
7154 int bnx2x_del_all_macs(struct bnx2x *bp,
7155 struct bnx2x_vlan_mac_obj *mac_obj,
7156 int mac_type, bool wait_for_comp)
7157 {
7158 int rc;
7159 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7160
7161 /* Wait for completion of requested */
7162 if (wait_for_comp)
7163 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7164
7165 /* Set the mac type of addresses we want to clear */
7166 __set_bit(mac_type, &vlan_mac_flags);
7167
7168 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7169 if (rc < 0)
7170 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7171
7172 return rc;
7173 }
7174
7175 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7176 {
7177 unsigned long ramrod_flags = 0;
7178
7179 #ifdef BCM_CNIC
7180 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_ISCSI_SD(bp)) {
7181 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7182 "Ignoring Zero MAC for STORAGE SD mode\n");
7183 return 0;
7184 }
7185 #endif
7186
7187 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7188
7189 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7190 /* Eth MAC is set on RSS leading client (fp[0]) */
7191 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
7192 BNX2X_ETH_MAC, &ramrod_flags);
7193 }
7194
7195 int bnx2x_setup_leading(struct bnx2x *bp)
7196 {
7197 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7198 }
7199
7200 /**
7201 * bnx2x_set_int_mode - configure interrupt mode
7202 *
7203 * @bp: driver handle
7204 *
7205 * In case of MSI-X it will also try to enable MSI-X.
7206 */
7207 static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
7208 {
7209 switch (int_mode) {
7210 case INT_MODE_MSI:
7211 bnx2x_enable_msi(bp);
7212 /* falling through... */
7213 case INT_MODE_INTx:
7214 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7215 BNX2X_DEV_INFO("set number of queues to 1\n");
7216 break;
7217 default:
7218 /* Set number of queues according to bp->multi_mode value */
7219 bnx2x_set_num_queues(bp);
7220
7221 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
7222
7223 /* if we can't use MSI-X we only need one fp,
7224 * so try to enable MSI-X with the requested number of fp's
7225 * and fallback to MSI or legacy INTx with one fp
7226 */
7227 if (bnx2x_enable_msix(bp)) {
7228 /* failed to enable MSI-X */
7229 BNX2X_DEV_INFO("Failed to enable MSI-X (%d), set number of queues to %d\n",
7230 bp->num_queues, 1 + NON_ETH_CONTEXT_USE);
7231
7232 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7233
7234 /* Try to enable MSI */
7235 if (!(bp->flags & DISABLE_MSI_FLAG))
7236 bnx2x_enable_msi(bp);
7237 }
7238 break;
7239 }
7240 }
7241
7242 /* must be called prioir to any HW initializations */
7243 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7244 {
7245 return L2_ILT_LINES(bp);
7246 }
7247
7248 void bnx2x_ilt_set_info(struct bnx2x *bp)
7249 {
7250 struct ilt_client_info *ilt_client;
7251 struct bnx2x_ilt *ilt = BP_ILT(bp);
7252 u16 line = 0;
7253
7254 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7255 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7256
7257 /* CDU */
7258 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7259 ilt_client->client_num = ILT_CLIENT_CDU;
7260 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7261 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7262 ilt_client->start = line;
7263 line += bnx2x_cid_ilt_lines(bp);
7264 #ifdef BCM_CNIC
7265 line += CNIC_ILT_LINES;
7266 #endif
7267 ilt_client->end = line - 1;
7268
7269 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7270 ilt_client->start,
7271 ilt_client->end,
7272 ilt_client->page_size,
7273 ilt_client->flags,
7274 ilog2(ilt_client->page_size >> 12));
7275
7276 /* QM */
7277 if (QM_INIT(bp->qm_cid_count)) {
7278 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7279 ilt_client->client_num = ILT_CLIENT_QM;
7280 ilt_client->page_size = QM_ILT_PAGE_SZ;
7281 ilt_client->flags = 0;
7282 ilt_client->start = line;
7283
7284 /* 4 bytes for each cid */
7285 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7286 QM_ILT_PAGE_SZ);
7287
7288 ilt_client->end = line - 1;
7289
7290 DP(NETIF_MSG_IFUP,
7291 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7292 ilt_client->start,
7293 ilt_client->end,
7294 ilt_client->page_size,
7295 ilt_client->flags,
7296 ilog2(ilt_client->page_size >> 12));
7297
7298 }
7299 /* SRC */
7300 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7301 #ifdef BCM_CNIC
7302 ilt_client->client_num = ILT_CLIENT_SRC;
7303 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7304 ilt_client->flags = 0;
7305 ilt_client->start = line;
7306 line += SRC_ILT_LINES;
7307 ilt_client->end = line - 1;
7308
7309 DP(NETIF_MSG_IFUP,
7310 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7311 ilt_client->start,
7312 ilt_client->end,
7313 ilt_client->page_size,
7314 ilt_client->flags,
7315 ilog2(ilt_client->page_size >> 12));
7316
7317 #else
7318 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7319 #endif
7320
7321 /* TM */
7322 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7323 #ifdef BCM_CNIC
7324 ilt_client->client_num = ILT_CLIENT_TM;
7325 ilt_client->page_size = TM_ILT_PAGE_SZ;
7326 ilt_client->flags = 0;
7327 ilt_client->start = line;
7328 line += TM_ILT_LINES;
7329 ilt_client->end = line - 1;
7330
7331 DP(NETIF_MSG_IFUP,
7332 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7333 ilt_client->start,
7334 ilt_client->end,
7335 ilt_client->page_size,
7336 ilt_client->flags,
7337 ilog2(ilt_client->page_size >> 12));
7338
7339 #else
7340 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7341 #endif
7342 BUG_ON(line > ILT_MAX_LINES);
7343 }
7344
7345 /**
7346 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7347 *
7348 * @bp: driver handle
7349 * @fp: pointer to fastpath
7350 * @init_params: pointer to parameters structure
7351 *
7352 * parameters configured:
7353 * - HC configuration
7354 * - Queue's CDU context
7355 */
7356 static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7357 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7358 {
7359
7360 u8 cos;
7361 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7362 if (!IS_FCOE_FP(fp)) {
7363 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7364 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7365
7366 /* If HC is supporterd, enable host coalescing in the transition
7367 * to INIT state.
7368 */
7369 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7370 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7371
7372 /* HC rate */
7373 init_params->rx.hc_rate = bp->rx_ticks ?
7374 (1000000 / bp->rx_ticks) : 0;
7375 init_params->tx.hc_rate = bp->tx_ticks ?
7376 (1000000 / bp->tx_ticks) : 0;
7377
7378 /* FW SB ID */
7379 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7380 fp->fw_sb_id;
7381
7382 /*
7383 * CQ index among the SB indices: FCoE clients uses the default
7384 * SB, therefore it's different.
7385 */
7386 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7387 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7388 }
7389
7390 /* set maximum number of COSs supported by this queue */
7391 init_params->max_cos = fp->max_cos;
7392
7393 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
7394 fp->index, init_params->max_cos);
7395
7396 /* set the context pointers queue object */
7397 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7398 init_params->cxts[cos] =
7399 &bp->context.vcxt[fp->txdata[cos].cid].eth;
7400 }
7401
7402 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7403 struct bnx2x_queue_state_params *q_params,
7404 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7405 int tx_index, bool leading)
7406 {
7407 memset(tx_only_params, 0, sizeof(*tx_only_params));
7408
7409 /* Set the command */
7410 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7411
7412 /* Set tx-only QUEUE flags: don't zero statistics */
7413 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7414
7415 /* choose the index of the cid to send the slow path on */
7416 tx_only_params->cid_index = tx_index;
7417
7418 /* Set general TX_ONLY_SETUP parameters */
7419 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7420
7421 /* Set Tx TX_ONLY_SETUP parameters */
7422 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7423
7424 DP(NETIF_MSG_IFUP,
7425 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
7426 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7427 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7428 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7429
7430 /* send the ramrod */
7431 return bnx2x_queue_state_change(bp, q_params);
7432 }
7433
7434
7435 /**
7436 * bnx2x_setup_queue - setup queue
7437 *
7438 * @bp: driver handle
7439 * @fp: pointer to fastpath
7440 * @leading: is leading
7441 *
7442 * This function performs 2 steps in a Queue state machine
7443 * actually: 1) RESET->INIT 2) INIT->SETUP
7444 */
7445
7446 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7447 bool leading)
7448 {
7449 struct bnx2x_queue_state_params q_params = {0};
7450 struct bnx2x_queue_setup_params *setup_params =
7451 &q_params.params.setup;
7452 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7453 &q_params.params.tx_only;
7454 int rc;
7455 u8 tx_index;
7456
7457 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
7458
7459 /* reset IGU state skip FCoE L2 queue */
7460 if (!IS_FCOE_FP(fp))
7461 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7462 IGU_INT_ENABLE, 0);
7463
7464 q_params.q_obj = &fp->q_obj;
7465 /* We want to wait for completion in this context */
7466 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7467
7468 /* Prepare the INIT parameters */
7469 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7470
7471 /* Set the command */
7472 q_params.cmd = BNX2X_Q_CMD_INIT;
7473
7474 /* Change the state to INIT */
7475 rc = bnx2x_queue_state_change(bp, &q_params);
7476 if (rc) {
7477 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7478 return rc;
7479 }
7480
7481 DP(NETIF_MSG_IFUP, "init complete\n");
7482
7483
7484 /* Now move the Queue to the SETUP state... */
7485 memset(setup_params, 0, sizeof(*setup_params));
7486
7487 /* Set QUEUE flags */
7488 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7489
7490 /* Set general SETUP parameters */
7491 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7492 FIRST_TX_COS_INDEX);
7493
7494 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7495 &setup_params->rxq_params);
7496
7497 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7498 FIRST_TX_COS_INDEX);
7499
7500 /* Set the command */
7501 q_params.cmd = BNX2X_Q_CMD_SETUP;
7502
7503 /* Change the state to SETUP */
7504 rc = bnx2x_queue_state_change(bp, &q_params);
7505 if (rc) {
7506 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7507 return rc;
7508 }
7509
7510 /* loop through the relevant tx-only indices */
7511 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7512 tx_index < fp->max_cos;
7513 tx_index++) {
7514
7515 /* prepare and send tx-only ramrod*/
7516 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7517 tx_only_params, tx_index, leading);
7518 if (rc) {
7519 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7520 fp->index, tx_index);
7521 return rc;
7522 }
7523 }
7524
7525 return rc;
7526 }
7527
7528 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7529 {
7530 struct bnx2x_fastpath *fp = &bp->fp[index];
7531 struct bnx2x_fp_txdata *txdata;
7532 struct bnx2x_queue_state_params q_params = {0};
7533 int rc, tx_index;
7534
7535 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
7536
7537 q_params.q_obj = &fp->q_obj;
7538 /* We want to wait for completion in this context */
7539 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7540
7541
7542 /* close tx-only connections */
7543 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7544 tx_index < fp->max_cos;
7545 tx_index++){
7546
7547 /* ascertain this is a normal queue*/
7548 txdata = &fp->txdata[tx_index];
7549
7550 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
7551 txdata->txq_index);
7552
7553 /* send halt terminate on tx-only connection */
7554 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7555 memset(&q_params.params.terminate, 0,
7556 sizeof(q_params.params.terminate));
7557 q_params.params.terminate.cid_index = tx_index;
7558
7559 rc = bnx2x_queue_state_change(bp, &q_params);
7560 if (rc)
7561 return rc;
7562
7563 /* send halt terminate on tx-only connection */
7564 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7565 memset(&q_params.params.cfc_del, 0,
7566 sizeof(q_params.params.cfc_del));
7567 q_params.params.cfc_del.cid_index = tx_index;
7568 rc = bnx2x_queue_state_change(bp, &q_params);
7569 if (rc)
7570 return rc;
7571 }
7572 /* Stop the primary connection: */
7573 /* ...halt the connection */
7574 q_params.cmd = BNX2X_Q_CMD_HALT;
7575 rc = bnx2x_queue_state_change(bp, &q_params);
7576 if (rc)
7577 return rc;
7578
7579 /* ...terminate the connection */
7580 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7581 memset(&q_params.params.terminate, 0,
7582 sizeof(q_params.params.terminate));
7583 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
7584 rc = bnx2x_queue_state_change(bp, &q_params);
7585 if (rc)
7586 return rc;
7587 /* ...delete cfc entry */
7588 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7589 memset(&q_params.params.cfc_del, 0,
7590 sizeof(q_params.params.cfc_del));
7591 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
7592 return bnx2x_queue_state_change(bp, &q_params);
7593 }
7594
7595
7596 static void bnx2x_reset_func(struct bnx2x *bp)
7597 {
7598 int port = BP_PORT(bp);
7599 int func = BP_FUNC(bp);
7600 int i;
7601
7602 /* Disable the function in the FW */
7603 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7604 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7605 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7606 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7607
7608 /* FP SBs */
7609 for_each_eth_queue(bp, i) {
7610 struct bnx2x_fastpath *fp = &bp->fp[i];
7611 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7612 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7613 SB_DISABLED);
7614 }
7615
7616 #ifdef BCM_CNIC
7617 /* CNIC SB */
7618 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7619 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7620 SB_DISABLED);
7621 #endif
7622 /* SP SB */
7623 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7624 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7625 SB_DISABLED);
7626
7627 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7628 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7629 0);
7630
7631 /* Configure IGU */
7632 if (bp->common.int_block == INT_BLOCK_HC) {
7633 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7634 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7635 } else {
7636 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7637 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7638 }
7639
7640 #ifdef BCM_CNIC
7641 /* Disable Timer scan */
7642 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7643 /*
7644 * Wait for at least 10ms and up to 2 second for the timers scan to
7645 * complete
7646 */
7647 for (i = 0; i < 200; i++) {
7648 msleep(10);
7649 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7650 break;
7651 }
7652 #endif
7653 /* Clear ILT */
7654 bnx2x_clear_func_ilt(bp, func);
7655
7656 /* Timers workaround bug for E2: if this is vnic-3,
7657 * we need to set the entire ilt range for this timers.
7658 */
7659 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
7660 struct ilt_client_info ilt_cli;
7661 /* use dummy TM client */
7662 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7663 ilt_cli.start = 0;
7664 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7665 ilt_cli.client_num = ILT_CLIENT_TM;
7666
7667 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7668 }
7669
7670 /* this assumes that reset_port() called before reset_func()*/
7671 if (!CHIP_IS_E1x(bp))
7672 bnx2x_pf_disable(bp);
7673
7674 bp->dmae_ready = 0;
7675 }
7676
7677 static void bnx2x_reset_port(struct bnx2x *bp)
7678 {
7679 int port = BP_PORT(bp);
7680 u32 val;
7681
7682 /* Reset physical Link */
7683 bnx2x__link_reset(bp);
7684
7685 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7686
7687 /* Do not rcv packets to BRB */
7688 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7689 /* Do not direct rcv packets that are not for MCP to the BRB */
7690 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7691 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7692
7693 /* Configure AEU */
7694 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7695
7696 msleep(100);
7697 /* Check for BRB port occupancy */
7698 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7699 if (val)
7700 DP(NETIF_MSG_IFDOWN,
7701 "BRB1 is not empty %d blocks are occupied\n", val);
7702
7703 /* TODO: Close Doorbell port? */
7704 }
7705
7706 static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
7707 {
7708 struct bnx2x_func_state_params func_params = {0};
7709
7710 /* Prepare parameters for function state transitions */
7711 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7712
7713 func_params.f_obj = &bp->func_obj;
7714 func_params.cmd = BNX2X_F_CMD_HW_RESET;
7715
7716 func_params.params.hw_init.load_phase = load_code;
7717
7718 return bnx2x_func_state_change(bp, &func_params);
7719 }
7720
7721 static inline int bnx2x_func_stop(struct bnx2x *bp)
7722 {
7723 struct bnx2x_func_state_params func_params = {0};
7724 int rc;
7725
7726 /* Prepare parameters for function state transitions */
7727 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7728 func_params.f_obj = &bp->func_obj;
7729 func_params.cmd = BNX2X_F_CMD_STOP;
7730
7731 /*
7732 * Try to stop the function the 'good way'. If fails (in case
7733 * of a parity error during bnx2x_chip_cleanup()) and we are
7734 * not in a debug mode, perform a state transaction in order to
7735 * enable further HW_RESET transaction.
7736 */
7737 rc = bnx2x_func_state_change(bp, &func_params);
7738 if (rc) {
7739 #ifdef BNX2X_STOP_ON_ERROR
7740 return rc;
7741 #else
7742 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
7743 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7744 return bnx2x_func_state_change(bp, &func_params);
7745 #endif
7746 }
7747
7748 return 0;
7749 }
7750
7751 /**
7752 * bnx2x_send_unload_req - request unload mode from the MCP.
7753 *
7754 * @bp: driver handle
7755 * @unload_mode: requested function's unload mode
7756 *
7757 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7758 */
7759 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7760 {
7761 u32 reset_code = 0;
7762 int port = BP_PORT(bp);
7763
7764 /* Select the UNLOAD request mode */
7765 if (unload_mode == UNLOAD_NORMAL)
7766 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7767
7768 else if (bp->flags & NO_WOL_FLAG)
7769 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7770
7771 else if (bp->wol) {
7772 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7773 u8 *mac_addr = bp->dev->dev_addr;
7774 u32 val;
7775 u16 pmc;
7776
7777 /* The mac address is written to entries 1-4 to
7778 * preserve entry 0 which is used by the PMF
7779 */
7780 u8 entry = (BP_VN(bp) + 1)*8;
7781
7782 val = (mac_addr[0] << 8) | mac_addr[1];
7783 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7784
7785 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7786 (mac_addr[4] << 8) | mac_addr[5];
7787 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7788
7789 /* Enable the PME and clear the status */
7790 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
7791 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
7792 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
7793
7794 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7795
7796 } else
7797 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7798
7799 /* Send the request to the MCP */
7800 if (!BP_NOMCP(bp))
7801 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7802 else {
7803 int path = BP_PATH(bp);
7804
7805 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
7806 path, load_count[path][0], load_count[path][1],
7807 load_count[path][2]);
7808 load_count[path][0]--;
7809 load_count[path][1 + port]--;
7810 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
7811 path, load_count[path][0], load_count[path][1],
7812 load_count[path][2]);
7813 if (load_count[path][0] == 0)
7814 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7815 else if (load_count[path][1 + port] == 0)
7816 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7817 else
7818 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7819 }
7820
7821 return reset_code;
7822 }
7823
7824 /**
7825 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7826 *
7827 * @bp: driver handle
7828 */
7829 void bnx2x_send_unload_done(struct bnx2x *bp)
7830 {
7831 /* Report UNLOAD_DONE to MCP */
7832 if (!BP_NOMCP(bp))
7833 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7834 }
7835
7836 static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7837 {
7838 int tout = 50;
7839 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7840
7841 if (!bp->port.pmf)
7842 return 0;
7843
7844 /*
7845 * (assumption: No Attention from MCP at this stage)
7846 * PMF probably in the middle of TXdisable/enable transaction
7847 * 1. Sync IRS for default SB
7848 * 2. Sync SP queue - this guarantes us that attention handling started
7849 * 3. Wait, that TXdisable/enable transaction completes
7850 *
7851 * 1+2 guranty that if DCBx attention was scheduled it already changed
7852 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7853 * received complettion for the transaction the state is TX_STOPPED.
7854 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7855 * transaction.
7856 */
7857
7858 /* make sure default SB ISR is done */
7859 if (msix)
7860 synchronize_irq(bp->msix_table[0].vector);
7861 else
7862 synchronize_irq(bp->pdev->irq);
7863
7864 flush_workqueue(bnx2x_wq);
7865
7866 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7867 BNX2X_F_STATE_STARTED && tout--)
7868 msleep(20);
7869
7870 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7871 BNX2X_F_STATE_STARTED) {
7872 #ifdef BNX2X_STOP_ON_ERROR
7873 BNX2X_ERR("Wrong function state\n");
7874 return -EBUSY;
7875 #else
7876 /*
7877 * Failed to complete the transaction in a "good way"
7878 * Force both transactions with CLR bit
7879 */
7880 struct bnx2x_func_state_params func_params = {0};
7881
7882 DP(NETIF_MSG_IFDOWN,
7883 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7884
7885 func_params.f_obj = &bp->func_obj;
7886 __set_bit(RAMROD_DRV_CLR_ONLY,
7887 &func_params.ramrod_flags);
7888
7889 /* STARTED-->TX_ST0PPED */
7890 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7891 bnx2x_func_state_change(bp, &func_params);
7892
7893 /* TX_ST0PPED-->STARTED */
7894 func_params.cmd = BNX2X_F_CMD_TX_START;
7895 return bnx2x_func_state_change(bp, &func_params);
7896 #endif
7897 }
7898
7899 return 0;
7900 }
7901
7902 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7903 {
7904 int port = BP_PORT(bp);
7905 int i, rc = 0;
7906 u8 cos;
7907 struct bnx2x_mcast_ramrod_params rparam = {0};
7908 u32 reset_code;
7909
7910 /* Wait until tx fastpath tasks complete */
7911 for_each_tx_queue(bp, i) {
7912 struct bnx2x_fastpath *fp = &bp->fp[i];
7913
7914 for_each_cos_in_tx_queue(fp, cos)
7915 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
7916 #ifdef BNX2X_STOP_ON_ERROR
7917 if (rc)
7918 return;
7919 #endif
7920 }
7921
7922 /* Give HW time to discard old tx messages */
7923 usleep_range(1000, 1000);
7924
7925 /* Clean all ETH MACs */
7926 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7927 if (rc < 0)
7928 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7929
7930 /* Clean up UC list */
7931 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7932 true);
7933 if (rc < 0)
7934 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
7935 rc);
7936
7937 /* Disable LLH */
7938 if (!CHIP_IS_E1(bp))
7939 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7940
7941 /* Set "drop all" (stop Rx).
7942 * We need to take a netif_addr_lock() here in order to prevent
7943 * a race between the completion code and this code.
7944 */
7945 netif_addr_lock_bh(bp->dev);
7946 /* Schedule the rx_mode command */
7947 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7948 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7949 else
7950 bnx2x_set_storm_rx_mode(bp);
7951
7952 /* Cleanup multicast configuration */
7953 rparam.mcast_obj = &bp->mcast_obj;
7954 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7955 if (rc < 0)
7956 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7957
7958 netif_addr_unlock_bh(bp->dev);
7959
7960
7961
7962 /*
7963 * Send the UNLOAD_REQUEST to the MCP. This will return if
7964 * this function should perform FUNC, PORT or COMMON HW
7965 * reset.
7966 */
7967 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7968
7969 /*
7970 * (assumption: No Attention from MCP at this stage)
7971 * PMF probably in the middle of TXdisable/enable transaction
7972 */
7973 rc = bnx2x_func_wait_started(bp);
7974 if (rc) {
7975 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7976 #ifdef BNX2X_STOP_ON_ERROR
7977 return;
7978 #endif
7979 }
7980
7981 /* Close multi and leading connections
7982 * Completions for ramrods are collected in a synchronous way
7983 */
7984 for_each_queue(bp, i)
7985 if (bnx2x_stop_queue(bp, i))
7986 #ifdef BNX2X_STOP_ON_ERROR
7987 return;
7988 #else
7989 goto unload_error;
7990 #endif
7991 /* If SP settings didn't get completed so far - something
7992 * very wrong has happen.
7993 */
7994 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7995 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
7996
7997 #ifndef BNX2X_STOP_ON_ERROR
7998 unload_error:
7999 #endif
8000 rc = bnx2x_func_stop(bp);
8001 if (rc) {
8002 BNX2X_ERR("Function stop failed!\n");
8003 #ifdef BNX2X_STOP_ON_ERROR
8004 return;
8005 #endif
8006 }
8007
8008 /* Disable HW interrupts, NAPI */
8009 bnx2x_netif_stop(bp, 1);
8010
8011 /* Release IRQs */
8012 bnx2x_free_irq(bp);
8013
8014 /* Reset the chip */
8015 rc = bnx2x_reset_hw(bp, reset_code);
8016 if (rc)
8017 BNX2X_ERR("HW_RESET failed\n");
8018
8019
8020 /* Report UNLOAD_DONE to MCP */
8021 bnx2x_send_unload_done(bp);
8022 }
8023
8024 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8025 {
8026 u32 val;
8027
8028 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8029
8030 if (CHIP_IS_E1(bp)) {
8031 int port = BP_PORT(bp);
8032 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8033 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8034
8035 val = REG_RD(bp, addr);
8036 val &= ~(0x300);
8037 REG_WR(bp, addr, val);
8038 } else {
8039 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8040 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8041 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8042 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8043 }
8044 }
8045
8046 /* Close gates #2, #3 and #4: */
8047 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8048 {
8049 u32 val;
8050
8051 /* Gates #2 and #4a are closed/opened for "not E1" only */
8052 if (!CHIP_IS_E1(bp)) {
8053 /* #4 */
8054 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8055 /* #2 */
8056 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8057 }
8058
8059 /* #3 */
8060 if (CHIP_IS_E1x(bp)) {
8061 /* Prevent interrupts from HC on both ports */
8062 val = REG_RD(bp, HC_REG_CONFIG_1);
8063 REG_WR(bp, HC_REG_CONFIG_1,
8064 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8065 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8066
8067 val = REG_RD(bp, HC_REG_CONFIG_0);
8068 REG_WR(bp, HC_REG_CONFIG_0,
8069 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8070 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8071 } else {
8072 /* Prevent incomming interrupts in IGU */
8073 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8074
8075 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8076 (!close) ?
8077 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8078 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8079 }
8080
8081 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8082 close ? "closing" : "opening");
8083 mmiowb();
8084 }
8085
8086 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8087
8088 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8089 {
8090 /* Do some magic... */
8091 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8092 *magic_val = val & SHARED_MF_CLP_MAGIC;
8093 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8094 }
8095
8096 /**
8097 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8098 *
8099 * @bp: driver handle
8100 * @magic_val: old value of the `magic' bit.
8101 */
8102 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8103 {
8104 /* Restore the `magic' bit value... */
8105 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8106 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8107 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8108 }
8109
8110 /**
8111 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8112 *
8113 * @bp: driver handle
8114 * @magic_val: old value of 'magic' bit.
8115 *
8116 * Takes care of CLP configurations.
8117 */
8118 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8119 {
8120 u32 shmem;
8121 u32 validity_offset;
8122
8123 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8124
8125 /* Set `magic' bit in order to save MF config */
8126 if (!CHIP_IS_E1(bp))
8127 bnx2x_clp_reset_prep(bp, magic_val);
8128
8129 /* Get shmem offset */
8130 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8131 validity_offset = offsetof(struct shmem_region, validity_map[0]);
8132
8133 /* Clear validity map flags */
8134 if (shmem > 0)
8135 REG_WR(bp, shmem + validity_offset, 0);
8136 }
8137
8138 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8139 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8140
8141 /**
8142 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8143 *
8144 * @bp: driver handle
8145 */
8146 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
8147 {
8148 /* special handling for emulation and FPGA,
8149 wait 10 times longer */
8150 if (CHIP_REV_IS_SLOW(bp))
8151 msleep(MCP_ONE_TIMEOUT*10);
8152 else
8153 msleep(MCP_ONE_TIMEOUT);
8154 }
8155
8156 /*
8157 * initializes bp->common.shmem_base and waits for validity signature to appear
8158 */
8159 static int bnx2x_init_shmem(struct bnx2x *bp)
8160 {
8161 int cnt = 0;
8162 u32 val = 0;
8163
8164 do {
8165 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8166 if (bp->common.shmem_base) {
8167 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8168 if (val & SHR_MEM_VALIDITY_MB)
8169 return 0;
8170 }
8171
8172 bnx2x_mcp_wait_one(bp);
8173
8174 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8175
8176 BNX2X_ERR("BAD MCP validity signature\n");
8177
8178 return -ENODEV;
8179 }
8180
8181 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8182 {
8183 int rc = bnx2x_init_shmem(bp);
8184
8185 /* Restore the `magic' bit value */
8186 if (!CHIP_IS_E1(bp))
8187 bnx2x_clp_reset_done(bp, magic_val);
8188
8189 return rc;
8190 }
8191
8192 static void bnx2x_pxp_prep(struct bnx2x *bp)
8193 {
8194 if (!CHIP_IS_E1(bp)) {
8195 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8196 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8197 mmiowb();
8198 }
8199 }
8200
8201 /*
8202 * Reset the whole chip except for:
8203 * - PCIE core
8204 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8205 * one reset bit)
8206 * - IGU
8207 * - MISC (including AEU)
8208 * - GRC
8209 * - RBCN, RBCP
8210 */
8211 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8212 {
8213 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8214 u32 global_bits2, stay_reset2;
8215
8216 /*
8217 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8218 * (per chip) blocks.
8219 */
8220 global_bits2 =
8221 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8222 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8223
8224 /* Don't reset the following blocks */
8225 not_reset_mask1 =
8226 MISC_REGISTERS_RESET_REG_1_RST_HC |
8227 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8228 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8229
8230 not_reset_mask2 =
8231 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8232 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8233 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8234 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8235 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8236 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8237 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8238 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8239 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8240 MISC_REGISTERS_RESET_REG_2_PGLC;
8241
8242 /*
8243 * Keep the following blocks in reset:
8244 * - all xxMACs are handled by the bnx2x_link code.
8245 */
8246 stay_reset2 =
8247 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8248 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8249 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8250 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8251 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8252 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8253 MISC_REGISTERS_RESET_REG_2_XMAC |
8254 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8255
8256 /* Full reset masks according to the chip */
8257 reset_mask1 = 0xffffffff;
8258
8259 if (CHIP_IS_E1(bp))
8260 reset_mask2 = 0xffff;
8261 else if (CHIP_IS_E1H(bp))
8262 reset_mask2 = 0x1ffff;
8263 else if (CHIP_IS_E2(bp))
8264 reset_mask2 = 0xfffff;
8265 else /* CHIP_IS_E3 */
8266 reset_mask2 = 0x3ffffff;
8267
8268 /* Don't reset global blocks unless we need to */
8269 if (!global)
8270 reset_mask2 &= ~global_bits2;
8271
8272 /*
8273 * In case of attention in the QM, we need to reset PXP
8274 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8275 * because otherwise QM reset would release 'close the gates' shortly
8276 * before resetting the PXP, then the PSWRQ would send a write
8277 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8278 * read the payload data from PSWWR, but PSWWR would not
8279 * respond. The write queue in PGLUE would stuck, dmae commands
8280 * would not return. Therefore it's important to reset the second
8281 * reset register (containing the
8282 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8283 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8284 * bit).
8285 */
8286 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8287 reset_mask2 & (~not_reset_mask2));
8288
8289 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8290 reset_mask1 & (~not_reset_mask1));
8291
8292 barrier();
8293 mmiowb();
8294
8295 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8296 reset_mask2 & (~stay_reset2));
8297
8298 barrier();
8299 mmiowb();
8300
8301 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8302 mmiowb();
8303 }
8304
8305 /**
8306 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8307 * It should get cleared in no more than 1s.
8308 *
8309 * @bp: driver handle
8310 *
8311 * It should get cleared in no more than 1s. Returns 0 if
8312 * pending writes bit gets cleared.
8313 */
8314 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8315 {
8316 u32 cnt = 1000;
8317 u32 pend_bits = 0;
8318
8319 do {
8320 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8321
8322 if (pend_bits == 0)
8323 break;
8324
8325 usleep_range(1000, 1000);
8326 } while (cnt-- > 0);
8327
8328 if (cnt <= 0) {
8329 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8330 pend_bits);
8331 return -EBUSY;
8332 }
8333
8334 return 0;
8335 }
8336
8337 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8338 {
8339 int cnt = 1000;
8340 u32 val = 0;
8341 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8342
8343
8344 /* Empty the Tetris buffer, wait for 1s */
8345 do {
8346 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8347 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8348 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8349 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8350 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8351 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8352 ((port_is_idle_0 & 0x1) == 0x1) &&
8353 ((port_is_idle_1 & 0x1) == 0x1) &&
8354 (pgl_exp_rom2 == 0xffffffff))
8355 break;
8356 usleep_range(1000, 1000);
8357 } while (cnt-- > 0);
8358
8359 if (cnt <= 0) {
8360 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
8361 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8362 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8363 pgl_exp_rom2);
8364 return -EAGAIN;
8365 }
8366
8367 barrier();
8368
8369 /* Close gates #2, #3 and #4 */
8370 bnx2x_set_234_gates(bp, true);
8371
8372 /* Poll for IGU VQs for 57712 and newer chips */
8373 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8374 return -EAGAIN;
8375
8376
8377 /* TBD: Indicate that "process kill" is in progress to MCP */
8378
8379 /* Clear "unprepared" bit */
8380 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8381 barrier();
8382
8383 /* Make sure all is written to the chip before the reset */
8384 mmiowb();
8385
8386 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8387 * PSWHST, GRC and PSWRD Tetris buffer.
8388 */
8389 usleep_range(1000, 1000);
8390
8391 /* Prepare to chip reset: */
8392 /* MCP */
8393 if (global)
8394 bnx2x_reset_mcp_prep(bp, &val);
8395
8396 /* PXP */
8397 bnx2x_pxp_prep(bp);
8398 barrier();
8399
8400 /* reset the chip */
8401 bnx2x_process_kill_chip_reset(bp, global);
8402 barrier();
8403
8404 /* Recover after reset: */
8405 /* MCP */
8406 if (global && bnx2x_reset_mcp_comp(bp, val))
8407 return -EAGAIN;
8408
8409 /* TBD: Add resetting the NO_MCP mode DB here */
8410
8411 /* PXP */
8412 bnx2x_pxp_prep(bp);
8413
8414 /* Open the gates #2, #3 and #4 */
8415 bnx2x_set_234_gates(bp, false);
8416
8417 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8418 * reset state, re-enable attentions. */
8419
8420 return 0;
8421 }
8422
8423 int bnx2x_leader_reset(struct bnx2x *bp)
8424 {
8425 int rc = 0;
8426 bool global = bnx2x_reset_is_global(bp);
8427 u32 load_code;
8428
8429 /* if not going to reset MCP - load "fake" driver to reset HW while
8430 * driver is owner of the HW
8431 */
8432 if (!global && !BP_NOMCP(bp)) {
8433 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0);
8434 if (!load_code) {
8435 BNX2X_ERR("MCP response failure, aborting\n");
8436 rc = -EAGAIN;
8437 goto exit_leader_reset;
8438 }
8439 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
8440 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
8441 BNX2X_ERR("MCP unexpected resp, aborting\n");
8442 rc = -EAGAIN;
8443 goto exit_leader_reset2;
8444 }
8445 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
8446 if (!load_code) {
8447 BNX2X_ERR("MCP response failure, aborting\n");
8448 rc = -EAGAIN;
8449 goto exit_leader_reset2;
8450 }
8451 }
8452
8453 /* Try to recover after the failure */
8454 if (bnx2x_process_kill(bp, global)) {
8455 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
8456 BP_PATH(bp));
8457 rc = -EAGAIN;
8458 goto exit_leader_reset2;
8459 }
8460
8461 /*
8462 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8463 * state.
8464 */
8465 bnx2x_set_reset_done(bp);
8466 if (global)
8467 bnx2x_clear_reset_global(bp);
8468
8469 exit_leader_reset2:
8470 /* unload "fake driver" if it was loaded */
8471 if (!global && !BP_NOMCP(bp)) {
8472 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
8473 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8474 }
8475 exit_leader_reset:
8476 bp->is_leader = 0;
8477 bnx2x_release_leader_lock(bp);
8478 smp_mb();
8479 return rc;
8480 }
8481
8482 static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8483 {
8484 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8485
8486 /* Disconnect this device */
8487 netif_device_detach(bp->dev);
8488
8489 /*
8490 * Block ifup for all function on this engine until "process kill"
8491 * or power cycle.
8492 */
8493 bnx2x_set_reset_in_progress(bp);
8494
8495 /* Shut down the power */
8496 bnx2x_set_power_state(bp, PCI_D3hot);
8497
8498 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8499
8500 smp_mb();
8501 }
8502
8503 /*
8504 * Assumption: runs under rtnl lock. This together with the fact
8505 * that it's called only from bnx2x_sp_rtnl() ensure that it
8506 * will never be called when netif_running(bp->dev) is false.
8507 */
8508 static void bnx2x_parity_recover(struct bnx2x *bp)
8509 {
8510 bool global = false;
8511 u32 error_recovered, error_unrecovered;
8512 bool is_parity;
8513
8514 DP(NETIF_MSG_HW, "Handling parity\n");
8515 while (1) {
8516 switch (bp->recovery_state) {
8517 case BNX2X_RECOVERY_INIT:
8518 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8519 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
8520 WARN_ON(!is_parity);
8521
8522 /* Try to get a LEADER_LOCK HW lock */
8523 if (bnx2x_trylock_leader_lock(bp)) {
8524 bnx2x_set_reset_in_progress(bp);
8525 /*
8526 * Check if there is a global attention and if
8527 * there was a global attention, set the global
8528 * reset bit.
8529 */
8530
8531 if (global)
8532 bnx2x_set_reset_global(bp);
8533
8534 bp->is_leader = 1;
8535 }
8536
8537 /* Stop the driver */
8538 /* If interface has been removed - break */
8539 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8540 return;
8541
8542 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8543
8544 /* Ensure "is_leader", MCP command sequence and
8545 * "recovery_state" update values are seen on other
8546 * CPUs.
8547 */
8548 smp_mb();
8549 break;
8550
8551 case BNX2X_RECOVERY_WAIT:
8552 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8553 if (bp->is_leader) {
8554 int other_engine = BP_PATH(bp) ? 0 : 1;
8555 bool other_load_status =
8556 bnx2x_get_load_status(bp, other_engine);
8557 bool load_status =
8558 bnx2x_get_load_status(bp, BP_PATH(bp));
8559 global = bnx2x_reset_is_global(bp);
8560
8561 /*
8562 * In case of a parity in a global block, let
8563 * the first leader that performs a
8564 * leader_reset() reset the global blocks in
8565 * order to clear global attentions. Otherwise
8566 * the the gates will remain closed for that
8567 * engine.
8568 */
8569 if (load_status ||
8570 (global && other_load_status)) {
8571 /* Wait until all other functions get
8572 * down.
8573 */
8574 schedule_delayed_work(&bp->sp_rtnl_task,
8575 HZ/10);
8576 return;
8577 } else {
8578 /* If all other functions got down -
8579 * try to bring the chip back to
8580 * normal. In any case it's an exit
8581 * point for a leader.
8582 */
8583 if (bnx2x_leader_reset(bp)) {
8584 bnx2x_recovery_failed(bp);
8585 return;
8586 }
8587
8588 /* If we are here, means that the
8589 * leader has succeeded and doesn't
8590 * want to be a leader any more. Try
8591 * to continue as a none-leader.
8592 */
8593 break;
8594 }
8595 } else { /* non-leader */
8596 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
8597 /* Try to get a LEADER_LOCK HW lock as
8598 * long as a former leader may have
8599 * been unloaded by the user or
8600 * released a leadership by another
8601 * reason.
8602 */
8603 if (bnx2x_trylock_leader_lock(bp)) {
8604 /* I'm a leader now! Restart a
8605 * switch case.
8606 */
8607 bp->is_leader = 1;
8608 break;
8609 }
8610
8611 schedule_delayed_work(&bp->sp_rtnl_task,
8612 HZ/10);
8613 return;
8614
8615 } else {
8616 /*
8617 * If there was a global attention, wait
8618 * for it to be cleared.
8619 */
8620 if (bnx2x_reset_is_global(bp)) {
8621 schedule_delayed_work(
8622 &bp->sp_rtnl_task,
8623 HZ/10);
8624 return;
8625 }
8626
8627 error_recovered =
8628 bp->eth_stats.recoverable_error;
8629 error_unrecovered =
8630 bp->eth_stats.unrecoverable_error;
8631 bp->recovery_state =
8632 BNX2X_RECOVERY_NIC_LOADING;
8633 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
8634 error_unrecovered++;
8635 netdev_err(bp->dev,
8636 "Recovery failed. Power cycle needed\n");
8637 /* Disconnect this device */
8638 netif_device_detach(bp->dev);
8639 /* Shut down the power */
8640 bnx2x_set_power_state(
8641 bp, PCI_D3hot);
8642 smp_mb();
8643 } else {
8644 bp->recovery_state =
8645 BNX2X_RECOVERY_DONE;
8646 error_recovered++;
8647 smp_mb();
8648 }
8649 bp->eth_stats.recoverable_error =
8650 error_recovered;
8651 bp->eth_stats.unrecoverable_error =
8652 error_unrecovered;
8653
8654 return;
8655 }
8656 }
8657 default:
8658 return;
8659 }
8660 }
8661 }
8662
8663 static int bnx2x_close(struct net_device *dev);
8664
8665 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8666 * scheduled on a general queue in order to prevent a dead lock.
8667 */
8668 static void bnx2x_sp_rtnl_task(struct work_struct *work)
8669 {
8670 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
8671
8672 rtnl_lock();
8673
8674 if (!netif_running(bp->dev))
8675 goto sp_rtnl_exit;
8676
8677 /* if stop on error is defined no recovery flows should be executed */
8678 #ifdef BNX2X_STOP_ON_ERROR
8679 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
8680 "you will need to reboot when done\n");
8681 goto sp_rtnl_not_reset;
8682 #endif
8683
8684 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8685 /*
8686 * Clear all pending SP commands as we are going to reset the
8687 * function anyway.
8688 */
8689 bp->sp_rtnl_state = 0;
8690 smp_mb();
8691
8692 bnx2x_parity_recover(bp);
8693
8694 goto sp_rtnl_exit;
8695 }
8696
8697 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
8698 /*
8699 * Clear all pending SP commands as we are going to reset the
8700 * function anyway.
8701 */
8702 bp->sp_rtnl_state = 0;
8703 smp_mb();
8704
8705 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8706 bnx2x_nic_load(bp, LOAD_NORMAL);
8707
8708 goto sp_rtnl_exit;
8709 }
8710 #ifdef BNX2X_STOP_ON_ERROR
8711 sp_rtnl_not_reset:
8712 #endif
8713 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8714 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
8715
8716 /*
8717 * in case of fan failure we need to reset id if the "stop on error"
8718 * debug flag is set, since we trying to prevent permanent overheating
8719 * damage
8720 */
8721 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
8722 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8723 netif_device_detach(bp->dev);
8724 bnx2x_close(bp->dev);
8725 }
8726
8727 sp_rtnl_exit:
8728 rtnl_unlock();
8729 }
8730
8731 /* end of nic load/unload */
8732
8733 static void bnx2x_period_task(struct work_struct *work)
8734 {
8735 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8736
8737 if (!netif_running(bp->dev))
8738 goto period_task_exit;
8739
8740 if (CHIP_REV_IS_SLOW(bp)) {
8741 BNX2X_ERR("period task called on emulation, ignoring\n");
8742 goto period_task_exit;
8743 }
8744
8745 bnx2x_acquire_phy_lock(bp);
8746 /*
8747 * The barrier is needed to ensure the ordering between the writing to
8748 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8749 * the reading here.
8750 */
8751 smp_mb();
8752 if (bp->port.pmf) {
8753 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8754
8755 /* Re-queue task in 1 sec */
8756 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8757 }
8758
8759 bnx2x_release_phy_lock(bp);
8760 period_task_exit:
8761 return;
8762 }
8763
8764 /*
8765 * Init service functions
8766 */
8767
8768 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
8769 {
8770 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8771 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8772 return base + (BP_ABS_FUNC(bp)) * stride;
8773 }
8774
8775 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
8776 {
8777 u32 reg = bnx2x_get_pretend_reg(bp);
8778
8779 /* Flush all outstanding writes */
8780 mmiowb();
8781
8782 /* Pretend to be function 0 */
8783 REG_WR(bp, reg, 0);
8784 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
8785
8786 /* From now we are in the "like-E1" mode */
8787 bnx2x_int_disable(bp);
8788
8789 /* Flush all outstanding writes */
8790 mmiowb();
8791
8792 /* Restore the original function */
8793 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8794 REG_RD(bp, reg);
8795 }
8796
8797 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
8798 {
8799 if (CHIP_IS_E1(bp))
8800 bnx2x_int_disable(bp);
8801 else
8802 bnx2x_undi_int_disable_e1h(bp);
8803 }
8804
8805 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8806 {
8807 u32 val;
8808
8809 /* possibly another driver is trying to reset the chip */
8810 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8811
8812 /* check if doorbell queue is reset */
8813 if (REG_RD(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET)
8814 & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
8815
8816 /*
8817 * Check if it is the UNDI driver
8818 * UNDI driver initializes CID offset for normal bell to 0x7
8819 */
8820 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8821 if (val == 0x7) {
8822 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8823 /* save our pf_num */
8824 int orig_pf_num = bp->pf_num;
8825 int port;
8826 u32 swap_en, swap_val, value;
8827
8828 /* clear the UNDI indication */
8829 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8830
8831 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8832
8833 /* try unload UNDI on port 0 */
8834 bp->pf_num = 0;
8835 bp->fw_seq =
8836 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8837 DRV_MSG_SEQ_NUMBER_MASK);
8838 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8839
8840 /* if UNDI is loaded on the other port */
8841 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8842
8843 /* send "DONE" for previous unload */
8844 bnx2x_fw_command(bp,
8845 DRV_MSG_CODE_UNLOAD_DONE, 0);
8846
8847 /* unload UNDI on port 1 */
8848 bp->pf_num = 1;
8849 bp->fw_seq =
8850 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8851 DRV_MSG_SEQ_NUMBER_MASK);
8852 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8853
8854 bnx2x_fw_command(bp, reset_code, 0);
8855 }
8856
8857 bnx2x_undi_int_disable(bp);
8858 port = BP_PORT(bp);
8859
8860 /* close input traffic and wait for it */
8861 /* Do not rcv packets to BRB */
8862 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8863 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
8864 /* Do not direct rcv packets that are not for MCP to
8865 * the BRB */
8866 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8867 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8868 /* clear AEU */
8869 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8870 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
8871 msleep(10);
8872
8873 /* save NIG port swap info */
8874 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8875 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8876 /* reset device */
8877 REG_WR(bp,
8878 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8879 0xd3ffffff);
8880
8881 value = 0x1400;
8882 if (CHIP_IS_E3(bp)) {
8883 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8884 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8885 }
8886
8887 REG_WR(bp,
8888 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8889 value);
8890
8891 /* take the NIG out of reset and restore swap values */
8892 REG_WR(bp,
8893 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8894 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8895 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8896 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8897
8898 /* send unload done to the MCP */
8899 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8900
8901 /* restore our func and fw_seq */
8902 bp->pf_num = orig_pf_num;
8903 }
8904 }
8905
8906 /* now it's safe to release the lock */
8907 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8908 }
8909
8910 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8911 {
8912 u32 val, val2, val3, val4, id, boot_mode;
8913 u16 pmc;
8914
8915 /* Get the chip revision id and number. */
8916 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8917 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8918 id = ((val & 0xffff) << 16);
8919 val = REG_RD(bp, MISC_REG_CHIP_REV);
8920 id |= ((val & 0xf) << 12);
8921 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8922 id |= ((val & 0xff) << 4);
8923 val = REG_RD(bp, MISC_REG_BOND_ID);
8924 id |= (val & 0xf);
8925 bp->common.chip_id = id;
8926
8927 /* Set doorbell size */
8928 bp->db_size = (1 << BNX2X_DB_SHIFT);
8929
8930 if (!CHIP_IS_E1x(bp)) {
8931 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8932 if ((val & 1) == 0)
8933 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8934 else
8935 val = (val >> 1) & 1;
8936 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8937 "2_PORT_MODE");
8938 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8939 CHIP_2_PORT_MODE;
8940
8941 if (CHIP_MODE_IS_4_PORT(bp))
8942 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8943 else
8944 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8945 } else {
8946 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8947 bp->pfid = bp->pf_num; /* 0..7 */
8948 }
8949
8950 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
8951
8952 bp->link_params.chip_id = bp->common.chip_id;
8953 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
8954
8955 val = (REG_RD(bp, 0x2874) & 0x55);
8956 if ((bp->common.chip_id & 0x1) ||
8957 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8958 bp->flags |= ONE_PORT_FLAG;
8959 BNX2X_DEV_INFO("single port device\n");
8960 }
8961
8962 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
8963 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
8964 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8965 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8966 bp->common.flash_size, bp->common.flash_size);
8967
8968 bnx2x_init_shmem(bp);
8969
8970
8971
8972 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8973 MISC_REG_GENERIC_CR_1 :
8974 MISC_REG_GENERIC_CR_0));
8975
8976 bp->link_params.shmem_base = bp->common.shmem_base;
8977 bp->link_params.shmem2_base = bp->common.shmem2_base;
8978 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8979 bp->common.shmem_base, bp->common.shmem2_base);
8980
8981 if (!bp->common.shmem_base) {
8982 BNX2X_DEV_INFO("MCP not active\n");
8983 bp->flags |= NO_MCP_FLAG;
8984 return;
8985 }
8986
8987 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
8988 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
8989
8990 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8991 SHARED_HW_CFG_LED_MODE_MASK) >>
8992 SHARED_HW_CFG_LED_MODE_SHIFT);
8993
8994 bp->link_params.feature_config_flags = 0;
8995 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8996 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8997 bp->link_params.feature_config_flags |=
8998 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8999 else
9000 bp->link_params.feature_config_flags &=
9001 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9002
9003 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
9004 bp->common.bc_ver = val;
9005 BNX2X_DEV_INFO("bc_ver %X\n", val);
9006 if (val < BNX2X_BC_VER) {
9007 /* for now only warn
9008 * later we might need to enforce this */
9009 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
9010 BNX2X_BC_VER, val);
9011 }
9012 bp->link_params.feature_config_flags |=
9013 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
9014 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
9015
9016 bp->link_params.feature_config_flags |=
9017 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
9018 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
9019
9020 bp->link_params.feature_config_flags |=
9021 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
9022 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
9023 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
9024 BC_SUPPORTS_PFC_STATS : 0;
9025
9026 boot_mode = SHMEM_RD(bp,
9027 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
9028 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
9029 switch (boot_mode) {
9030 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
9031 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
9032 break;
9033 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
9034 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
9035 break;
9036 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
9037 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
9038 break;
9039 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
9040 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
9041 break;
9042 }
9043
9044 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
9045 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
9046
9047 BNX2X_DEV_INFO("%sWoL capable\n",
9048 (bp->flags & NO_WOL_FLAG) ? "not " : "");
9049
9050 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
9051 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
9052 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
9053 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
9054
9055 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
9056 val, val2, val3, val4);
9057 }
9058
9059 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
9060 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
9061
9062 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
9063 {
9064 int pfid = BP_FUNC(bp);
9065 int igu_sb_id;
9066 u32 val;
9067 u8 fid, igu_sb_cnt = 0;
9068
9069 bp->igu_base_sb = 0xff;
9070 if (CHIP_INT_MODE_IS_BC(bp)) {
9071 int vn = BP_VN(bp);
9072 igu_sb_cnt = bp->igu_sb_cnt;
9073 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
9074 FP_SB_MAX_E1x;
9075
9076 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
9077 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
9078
9079 return;
9080 }
9081
9082 /* IGU in normal mode - read CAM */
9083 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
9084 igu_sb_id++) {
9085 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
9086 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
9087 continue;
9088 fid = IGU_FID(val);
9089 if ((fid & IGU_FID_ENCODE_IS_PF)) {
9090 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
9091 continue;
9092 if (IGU_VEC(val) == 0)
9093 /* default status block */
9094 bp->igu_dsb_id = igu_sb_id;
9095 else {
9096 if (bp->igu_base_sb == 0xff)
9097 bp->igu_base_sb = igu_sb_id;
9098 igu_sb_cnt++;
9099 }
9100 }
9101 }
9102
9103 #ifdef CONFIG_PCI_MSI
9104 /*
9105 * It's expected that number of CAM entries for this functions is equal
9106 * to the number evaluated based on the MSI-X table size. We want a
9107 * harsh warning if these values are different!
9108 */
9109 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
9110 #endif
9111
9112 if (igu_sb_cnt == 0)
9113 BNX2X_ERR("CAM configuration error\n");
9114 }
9115
9116 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
9117 u32 switch_cfg)
9118 {
9119 int cfg_size = 0, idx, port = BP_PORT(bp);
9120
9121 /* Aggregation of supported attributes of all external phys */
9122 bp->port.supported[0] = 0;
9123 bp->port.supported[1] = 0;
9124 switch (bp->link_params.num_phys) {
9125 case 1:
9126 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
9127 cfg_size = 1;
9128 break;
9129 case 2:
9130 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
9131 cfg_size = 1;
9132 break;
9133 case 3:
9134 if (bp->link_params.multi_phy_config &
9135 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
9136 bp->port.supported[1] =
9137 bp->link_params.phy[EXT_PHY1].supported;
9138 bp->port.supported[0] =
9139 bp->link_params.phy[EXT_PHY2].supported;
9140 } else {
9141 bp->port.supported[0] =
9142 bp->link_params.phy[EXT_PHY1].supported;
9143 bp->port.supported[1] =
9144 bp->link_params.phy[EXT_PHY2].supported;
9145 }
9146 cfg_size = 2;
9147 break;
9148 }
9149
9150 if (!(bp->port.supported[0] || bp->port.supported[1])) {
9151 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
9152 SHMEM_RD(bp,
9153 dev_info.port_hw_config[port].external_phy_config),
9154 SHMEM_RD(bp,
9155 dev_info.port_hw_config[port].external_phy_config2));
9156 return;
9157 }
9158
9159 if (CHIP_IS_E3(bp))
9160 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
9161 else {
9162 switch (switch_cfg) {
9163 case SWITCH_CFG_1G:
9164 bp->port.phy_addr = REG_RD(
9165 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
9166 break;
9167 case SWITCH_CFG_10G:
9168 bp->port.phy_addr = REG_RD(
9169 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
9170 break;
9171 default:
9172 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
9173 bp->port.link_config[0]);
9174 return;
9175 }
9176 }
9177 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
9178 /* mask what we support according to speed_cap_mask per configuration */
9179 for (idx = 0; idx < cfg_size; idx++) {
9180 if (!(bp->link_params.speed_cap_mask[idx] &
9181 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
9182 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
9183
9184 if (!(bp->link_params.speed_cap_mask[idx] &
9185 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
9186 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
9187
9188 if (!(bp->link_params.speed_cap_mask[idx] &
9189 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
9190 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
9191
9192 if (!(bp->link_params.speed_cap_mask[idx] &
9193 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
9194 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
9195
9196 if (!(bp->link_params.speed_cap_mask[idx] &
9197 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
9198 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
9199 SUPPORTED_1000baseT_Full);
9200
9201 if (!(bp->link_params.speed_cap_mask[idx] &
9202 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
9203 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
9204
9205 if (!(bp->link_params.speed_cap_mask[idx] &
9206 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
9207 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
9208
9209 }
9210
9211 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
9212 bp->port.supported[1]);
9213 }
9214
9215 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9216 {
9217 u32 link_config, idx, cfg_size = 0;
9218 bp->port.advertising[0] = 0;
9219 bp->port.advertising[1] = 0;
9220 switch (bp->link_params.num_phys) {
9221 case 1:
9222 case 2:
9223 cfg_size = 1;
9224 break;
9225 case 3:
9226 cfg_size = 2;
9227 break;
9228 }
9229 for (idx = 0; idx < cfg_size; idx++) {
9230 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
9231 link_config = bp->port.link_config[idx];
9232 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
9233 case PORT_FEATURE_LINK_SPEED_AUTO:
9234 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
9235 bp->link_params.req_line_speed[idx] =
9236 SPEED_AUTO_NEG;
9237 bp->port.advertising[idx] |=
9238 bp->port.supported[idx];
9239 if (bp->link_params.phy[EXT_PHY1].type ==
9240 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9241 bp->port.advertising[idx] |=
9242 (SUPPORTED_100baseT_Half |
9243 SUPPORTED_100baseT_Full);
9244 } else {
9245 /* force 10G, no AN */
9246 bp->link_params.req_line_speed[idx] =
9247 SPEED_10000;
9248 bp->port.advertising[idx] |=
9249 (ADVERTISED_10000baseT_Full |
9250 ADVERTISED_FIBRE);
9251 continue;
9252 }
9253 break;
9254
9255 case PORT_FEATURE_LINK_SPEED_10M_FULL:
9256 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9257 bp->link_params.req_line_speed[idx] =
9258 SPEED_10;
9259 bp->port.advertising[idx] |=
9260 (ADVERTISED_10baseT_Full |
9261 ADVERTISED_TP);
9262 } else {
9263 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9264 link_config,
9265 bp->link_params.speed_cap_mask[idx]);
9266 return;
9267 }
9268 break;
9269
9270 case PORT_FEATURE_LINK_SPEED_10M_HALF:
9271 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
9272 bp->link_params.req_line_speed[idx] =
9273 SPEED_10;
9274 bp->link_params.req_duplex[idx] =
9275 DUPLEX_HALF;
9276 bp->port.advertising[idx] |=
9277 (ADVERTISED_10baseT_Half |
9278 ADVERTISED_TP);
9279 } else {
9280 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9281 link_config,
9282 bp->link_params.speed_cap_mask[idx]);
9283 return;
9284 }
9285 break;
9286
9287 case PORT_FEATURE_LINK_SPEED_100M_FULL:
9288 if (bp->port.supported[idx] &
9289 SUPPORTED_100baseT_Full) {
9290 bp->link_params.req_line_speed[idx] =
9291 SPEED_100;
9292 bp->port.advertising[idx] |=
9293 (ADVERTISED_100baseT_Full |
9294 ADVERTISED_TP);
9295 } else {
9296 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9297 link_config,
9298 bp->link_params.speed_cap_mask[idx]);
9299 return;
9300 }
9301 break;
9302
9303 case PORT_FEATURE_LINK_SPEED_100M_HALF:
9304 if (bp->port.supported[idx] &
9305 SUPPORTED_100baseT_Half) {
9306 bp->link_params.req_line_speed[idx] =
9307 SPEED_100;
9308 bp->link_params.req_duplex[idx] =
9309 DUPLEX_HALF;
9310 bp->port.advertising[idx] |=
9311 (ADVERTISED_100baseT_Half |
9312 ADVERTISED_TP);
9313 } else {
9314 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9315 link_config,
9316 bp->link_params.speed_cap_mask[idx]);
9317 return;
9318 }
9319 break;
9320
9321 case PORT_FEATURE_LINK_SPEED_1G:
9322 if (bp->port.supported[idx] &
9323 SUPPORTED_1000baseT_Full) {
9324 bp->link_params.req_line_speed[idx] =
9325 SPEED_1000;
9326 bp->port.advertising[idx] |=
9327 (ADVERTISED_1000baseT_Full |
9328 ADVERTISED_TP);
9329 } else {
9330 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9331 link_config,
9332 bp->link_params.speed_cap_mask[idx]);
9333 return;
9334 }
9335 break;
9336
9337 case PORT_FEATURE_LINK_SPEED_2_5G:
9338 if (bp->port.supported[idx] &
9339 SUPPORTED_2500baseX_Full) {
9340 bp->link_params.req_line_speed[idx] =
9341 SPEED_2500;
9342 bp->port.advertising[idx] |=
9343 (ADVERTISED_2500baseX_Full |
9344 ADVERTISED_TP);
9345 } else {
9346 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9347 link_config,
9348 bp->link_params.speed_cap_mask[idx]);
9349 return;
9350 }
9351 break;
9352
9353 case PORT_FEATURE_LINK_SPEED_10G_CX4:
9354 if (bp->port.supported[idx] &
9355 SUPPORTED_10000baseT_Full) {
9356 bp->link_params.req_line_speed[idx] =
9357 SPEED_10000;
9358 bp->port.advertising[idx] |=
9359 (ADVERTISED_10000baseT_Full |
9360 ADVERTISED_FIBRE);
9361 } else {
9362 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9363 link_config,
9364 bp->link_params.speed_cap_mask[idx]);
9365 return;
9366 }
9367 break;
9368 case PORT_FEATURE_LINK_SPEED_20G:
9369 bp->link_params.req_line_speed[idx] = SPEED_20000;
9370
9371 break;
9372 default:
9373 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
9374 link_config);
9375 bp->link_params.req_line_speed[idx] =
9376 SPEED_AUTO_NEG;
9377 bp->port.advertising[idx] =
9378 bp->port.supported[idx];
9379 break;
9380 }
9381
9382 bp->link_params.req_flow_ctrl[idx] = (link_config &
9383 PORT_FEATURE_FLOW_CONTROL_MASK);
9384 if ((bp->link_params.req_flow_ctrl[idx] ==
9385 BNX2X_FLOW_CTRL_AUTO) &&
9386 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9387 bp->link_params.req_flow_ctrl[idx] =
9388 BNX2X_FLOW_CTRL_NONE;
9389 }
9390
9391 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
9392 bp->link_params.req_line_speed[idx],
9393 bp->link_params.req_duplex[idx],
9394 bp->link_params.req_flow_ctrl[idx],
9395 bp->port.advertising[idx]);
9396 }
9397 }
9398
9399 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9400 {
9401 mac_hi = cpu_to_be16(mac_hi);
9402 mac_lo = cpu_to_be32(mac_lo);
9403 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9404 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9405 }
9406
9407 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
9408 {
9409 int port = BP_PORT(bp);
9410 u32 config;
9411 u32 ext_phy_type, ext_phy_config;
9412
9413 bp->link_params.bp = bp;
9414 bp->link_params.port = port;
9415
9416 bp->link_params.lane_config =
9417 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
9418
9419 bp->link_params.speed_cap_mask[0] =
9420 SHMEM_RD(bp,
9421 dev_info.port_hw_config[port].speed_capability_mask);
9422 bp->link_params.speed_cap_mask[1] =
9423 SHMEM_RD(bp,
9424 dev_info.port_hw_config[port].speed_capability_mask2);
9425 bp->port.link_config[0] =
9426 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9427
9428 bp->port.link_config[1] =
9429 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
9430
9431 bp->link_params.multi_phy_config =
9432 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
9433 /* If the device is capable of WoL, set the default state according
9434 * to the HW
9435 */
9436 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
9437 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9438 (config & PORT_FEATURE_WOL_ENABLED));
9439
9440 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9441 bp->link_params.lane_config,
9442 bp->link_params.speed_cap_mask[0],
9443 bp->port.link_config[0]);
9444
9445 bp->link_params.switch_cfg = (bp->port.link_config[0] &
9446 PORT_FEATURE_CONNECTED_SWITCH_MASK);
9447 bnx2x_phy_probe(&bp->link_params);
9448 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
9449
9450 bnx2x_link_settings_requested(bp);
9451
9452 /*
9453 * If connected directly, work with the internal PHY, otherwise, work
9454 * with the external PHY
9455 */
9456 ext_phy_config =
9457 SHMEM_RD(bp,
9458 dev_info.port_hw_config[port].external_phy_config);
9459 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
9460 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9461 bp->mdio.prtad = bp->port.phy_addr;
9462
9463 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9464 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9465 bp->mdio.prtad =
9466 XGXS_EXT_PHY_ADDR(ext_phy_config);
9467
9468 /*
9469 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9470 * In MF mode, it is set to cover self test cases
9471 */
9472 if (IS_MF(bp))
9473 bp->port.need_hw_lock = 1;
9474 else
9475 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9476 bp->common.shmem_base,
9477 bp->common.shmem2_base);
9478 }
9479
9480 void bnx2x_get_iscsi_info(struct bnx2x *bp)
9481 {
9482 #ifdef BCM_CNIC
9483 int port = BP_PORT(bp);
9484
9485 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9486 drv_lic_key[port].max_iscsi_conn);
9487
9488 /* Get the number of maximum allowed iSCSI connections */
9489 bp->cnic_eth_dev.max_iscsi_conn =
9490 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9491 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9492
9493 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
9494 bp->cnic_eth_dev.max_iscsi_conn);
9495
9496 /*
9497 * If maximum allowed number of connections is zero -
9498 * disable the feature.
9499 */
9500 if (!bp->cnic_eth_dev.max_iscsi_conn)
9501 bp->flags |= NO_ISCSI_FLAG;
9502 #else
9503 bp->flags |= NO_ISCSI_FLAG;
9504 #endif
9505 }
9506
9507 static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp)
9508 {
9509 #ifdef BCM_CNIC
9510 int port = BP_PORT(bp);
9511 int func = BP_ABS_FUNC(bp);
9512
9513 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9514 drv_lic_key[port].max_fcoe_conn);
9515
9516 /* Get the number of maximum allowed FCoE connections */
9517 bp->cnic_eth_dev.max_fcoe_conn =
9518 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9519 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9520
9521 /* Read the WWN: */
9522 if (!IS_MF(bp)) {
9523 /* Port info */
9524 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9525 SHMEM_RD(bp,
9526 dev_info.port_hw_config[port].
9527 fcoe_wwn_port_name_upper);
9528 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9529 SHMEM_RD(bp,
9530 dev_info.port_hw_config[port].
9531 fcoe_wwn_port_name_lower);
9532
9533 /* Node info */
9534 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9535 SHMEM_RD(bp,
9536 dev_info.port_hw_config[port].
9537 fcoe_wwn_node_name_upper);
9538 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9539 SHMEM_RD(bp,
9540 dev_info.port_hw_config[port].
9541 fcoe_wwn_node_name_lower);
9542 } else if (!IS_MF_SD(bp)) {
9543 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9544
9545 /*
9546 * Read the WWN info only if the FCoE feature is enabled for
9547 * this function.
9548 */
9549 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9550 /* Port info */
9551 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9552 MF_CFG_RD(bp, func_ext_config[func].
9553 fcoe_wwn_port_name_upper);
9554 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9555 MF_CFG_RD(bp, func_ext_config[func].
9556 fcoe_wwn_port_name_lower);
9557
9558 /* Node info */
9559 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9560 MF_CFG_RD(bp, func_ext_config[func].
9561 fcoe_wwn_node_name_upper);
9562 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9563 MF_CFG_RD(bp, func_ext_config[func].
9564 fcoe_wwn_node_name_lower);
9565 }
9566 }
9567
9568 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
9569
9570 /*
9571 * If maximum allowed number of connections is zero -
9572 * disable the feature.
9573 */
9574 if (!bp->cnic_eth_dev.max_fcoe_conn)
9575 bp->flags |= NO_FCOE_FLAG;
9576 #else
9577 bp->flags |= NO_FCOE_FLAG;
9578 #endif
9579 }
9580
9581 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9582 {
9583 /*
9584 * iSCSI may be dynamically disabled but reading
9585 * info here we will decrease memory usage by driver
9586 * if the feature is disabled for good
9587 */
9588 bnx2x_get_iscsi_info(bp);
9589 bnx2x_get_fcoe_info(bp);
9590 }
9591
9592 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9593 {
9594 u32 val, val2;
9595 int func = BP_ABS_FUNC(bp);
9596 int port = BP_PORT(bp);
9597 #ifdef BCM_CNIC
9598 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9599 u8 *fip_mac = bp->fip_mac;
9600 #endif
9601
9602 /* Zero primary MAC configuration */
9603 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9604
9605 if (BP_NOMCP(bp)) {
9606 BNX2X_ERROR("warning: random MAC workaround active\n");
9607 eth_hw_addr_random(bp->dev);
9608 } else if (IS_MF(bp)) {
9609 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9610 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9611 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9612 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9613 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9614
9615 #ifdef BCM_CNIC
9616 /*
9617 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9618 * FCoE MAC then the appropriate feature should be disabled.
9619 */
9620 if (IS_MF_SI(bp)) {
9621 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9622 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9623 val2 = MF_CFG_RD(bp, func_ext_config[func].
9624 iscsi_mac_addr_upper);
9625 val = MF_CFG_RD(bp, func_ext_config[func].
9626 iscsi_mac_addr_lower);
9627 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9628 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9629 iscsi_mac);
9630 } else
9631 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9632
9633 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9634 val2 = MF_CFG_RD(bp, func_ext_config[func].
9635 fcoe_mac_addr_upper);
9636 val = MF_CFG_RD(bp, func_ext_config[func].
9637 fcoe_mac_addr_lower);
9638 bnx2x_set_mac_buf(fip_mac, val, val2);
9639 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
9640 fip_mac);
9641
9642 } else
9643 bp->flags |= NO_FCOE_FLAG;
9644 } else { /* SD mode */
9645 if (BNX2X_IS_MF_PROTOCOL_ISCSI(bp)) {
9646 /* use primary mac as iscsi mac */
9647 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
9648 /* Zero primary MAC configuration */
9649 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9650
9651 BNX2X_DEV_INFO("SD ISCSI MODE\n");
9652 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9653 iscsi_mac);
9654 }
9655 }
9656 #endif
9657 } else {
9658 /* in SF read MACs from port configuration */
9659 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9660 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9661 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9662
9663 #ifdef BCM_CNIC
9664 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9665 iscsi_mac_upper);
9666 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9667 iscsi_mac_lower);
9668 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9669
9670 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9671 fcoe_fip_mac_upper);
9672 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9673 fcoe_fip_mac_lower);
9674 bnx2x_set_mac_buf(fip_mac, val, val2);
9675 #endif
9676 }
9677
9678 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9679 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9680
9681 #ifdef BCM_CNIC
9682 /* Set the FCoE MAC in MF_SD mode */
9683 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp))
9684 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
9685
9686 /* Disable iSCSI if MAC configuration is
9687 * invalid.
9688 */
9689 if (!is_valid_ether_addr(iscsi_mac)) {
9690 bp->flags |= NO_ISCSI_FLAG;
9691 memset(iscsi_mac, 0, ETH_ALEN);
9692 }
9693
9694 /* Disable FCoE if MAC configuration is
9695 * invalid.
9696 */
9697 if (!is_valid_ether_addr(fip_mac)) {
9698 bp->flags |= NO_FCOE_FLAG;
9699 memset(bp->fip_mac, 0, ETH_ALEN);
9700 }
9701 #endif
9702
9703 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
9704 dev_err(&bp->pdev->dev,
9705 "bad Ethernet MAC address configuration: %pM\n"
9706 "change it manually before bringing up the appropriate network interface\n",
9707 bp->dev->dev_addr);
9708
9709
9710 }
9711
9712 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9713 {
9714 int /*abs*/func = BP_ABS_FUNC(bp);
9715 int vn;
9716 u32 val = 0;
9717 int rc = 0;
9718
9719 bnx2x_get_common_hwinfo(bp);
9720
9721 /*
9722 * initialize IGU parameters
9723 */
9724 if (CHIP_IS_E1x(bp)) {
9725 bp->common.int_block = INT_BLOCK_HC;
9726
9727 bp->igu_dsb_id = DEF_SB_IGU_ID;
9728 bp->igu_base_sb = 0;
9729 } else {
9730 bp->common.int_block = INT_BLOCK_IGU;
9731
9732 /* do not allow device reset during IGU info preocessing */
9733 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9734
9735 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9736
9737 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9738 int tout = 5000;
9739
9740 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9741
9742 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9743 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9744 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9745
9746 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9747 tout--;
9748 usleep_range(1000, 1000);
9749 }
9750
9751 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9752 dev_err(&bp->pdev->dev,
9753 "FORCING Normal Mode failed!!!\n");
9754 return -EPERM;
9755 }
9756 }
9757
9758 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9759 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
9760 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9761 } else
9762 BNX2X_DEV_INFO("IGU Normal Mode\n");
9763
9764 bnx2x_get_igu_cam_info(bp);
9765
9766 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9767 }
9768
9769 /*
9770 * set base FW non-default (fast path) status block id, this value is
9771 * used to initialize the fw_sb_id saved on the fp/queue structure to
9772 * determine the id used by the FW.
9773 */
9774 if (CHIP_IS_E1x(bp))
9775 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9776 else /*
9777 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9778 * the same queue are indicated on the same IGU SB). So we prefer
9779 * FW and IGU SBs to be the same value.
9780 */
9781 bp->base_fw_ndsb = bp->igu_base_sb;
9782
9783 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9784 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9785 bp->igu_sb_cnt, bp->base_fw_ndsb);
9786
9787 /*
9788 * Initialize MF configuration
9789 */
9790
9791 bp->mf_ov = 0;
9792 bp->mf_mode = 0;
9793 vn = BP_VN(bp);
9794
9795 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
9796 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9797 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9798 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9799
9800 if (SHMEM2_HAS(bp, mf_cfg_addr))
9801 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9802 else
9803 bp->common.mf_cfg_base = bp->common.shmem_base +
9804 offsetof(struct shmem_region, func_mb) +
9805 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
9806 /*
9807 * get mf configuration:
9808 * 1. existence of MF configuration
9809 * 2. MAC address must be legal (check only upper bytes)
9810 * for Switch-Independent mode;
9811 * OVLAN must be legal for Switch-Dependent mode
9812 * 3. SF_MODE configures specific MF mode
9813 */
9814 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9815 /* get mf configuration */
9816 val = SHMEM_RD(bp,
9817 dev_info.shared_feature_config.config);
9818 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9819
9820 switch (val) {
9821 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9822 val = MF_CFG_RD(bp, func_mf_config[func].
9823 mac_upper);
9824 /* check for legal mac (upper bytes)*/
9825 if (val != 0xffff) {
9826 bp->mf_mode = MULTI_FUNCTION_SI;
9827 bp->mf_config[vn] = MF_CFG_RD(bp,
9828 func_mf_config[func].config);
9829 } else
9830 BNX2X_DEV_INFO("illegal MAC address for SI\n");
9831 break;
9832 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9833 /* get OV configuration */
9834 val = MF_CFG_RD(bp,
9835 func_mf_config[FUNC_0].e1hov_tag);
9836 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9837
9838 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9839 bp->mf_mode = MULTI_FUNCTION_SD;
9840 bp->mf_config[vn] = MF_CFG_RD(bp,
9841 func_mf_config[func].config);
9842 } else
9843 BNX2X_DEV_INFO("illegal OV for SD\n");
9844 break;
9845 default:
9846 /* Unknown configuration: reset mf_config */
9847 bp->mf_config[vn] = 0;
9848 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
9849 }
9850 }
9851
9852 BNX2X_DEV_INFO("%s function mode\n",
9853 IS_MF(bp) ? "multi" : "single");
9854
9855 switch (bp->mf_mode) {
9856 case MULTI_FUNCTION_SD:
9857 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9858 FUNC_MF_CFG_E1HOV_TAG_MASK;
9859 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9860 bp->mf_ov = val;
9861 bp->path_has_ovlan = true;
9862
9863 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
9864 func, bp->mf_ov, bp->mf_ov);
9865 } else {
9866 dev_err(&bp->pdev->dev,
9867 "No valid MF OV for func %d, aborting\n",
9868 func);
9869 return -EPERM;
9870 }
9871 break;
9872 case MULTI_FUNCTION_SI:
9873 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
9874 func);
9875 break;
9876 default:
9877 if (vn) {
9878 dev_err(&bp->pdev->dev,
9879 "VN %d is in a single function mode, aborting\n",
9880 vn);
9881 return -EPERM;
9882 }
9883 break;
9884 }
9885
9886 /* check if other port on the path needs ovlan:
9887 * Since MF configuration is shared between ports
9888 * Possible mixed modes are only
9889 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9890 */
9891 if (CHIP_MODE_IS_4_PORT(bp) &&
9892 !bp->path_has_ovlan &&
9893 !IS_MF(bp) &&
9894 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9895 u8 other_port = !BP_PORT(bp);
9896 u8 other_func = BP_PATH(bp) + 2*other_port;
9897 val = MF_CFG_RD(bp,
9898 func_mf_config[other_func].e1hov_tag);
9899 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9900 bp->path_has_ovlan = true;
9901 }
9902 }
9903
9904 /* adjust igu_sb_cnt to MF for E1x */
9905 if (CHIP_IS_E1x(bp) && IS_MF(bp))
9906 bp->igu_sb_cnt /= E1HVN_MAX;
9907
9908 /* port info */
9909 bnx2x_get_port_hwinfo(bp);
9910
9911 /* Get MAC addresses */
9912 bnx2x_get_mac_hwinfo(bp);
9913
9914 bnx2x_get_cnic_info(bp);
9915
9916 return rc;
9917 }
9918
9919 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9920 {
9921 int cnt, i, block_end, rodi;
9922 char vpd_start[BNX2X_VPD_LEN+1];
9923 char str_id_reg[VENDOR_ID_LEN+1];
9924 char str_id_cap[VENDOR_ID_LEN+1];
9925 char *vpd_data;
9926 char *vpd_extended_data = NULL;
9927 u8 len;
9928
9929 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
9930 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9931
9932 if (cnt < BNX2X_VPD_LEN)
9933 goto out_not_found;
9934
9935 /* VPD RO tag should be first tag after identifier string, hence
9936 * we should be able to find it in first BNX2X_VPD_LEN chars
9937 */
9938 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
9939 PCI_VPD_LRDT_RO_DATA);
9940 if (i < 0)
9941 goto out_not_found;
9942
9943 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9944 pci_vpd_lrdt_size(&vpd_start[i]);
9945
9946 i += PCI_VPD_LRDT_TAG_SIZE;
9947
9948 if (block_end > BNX2X_VPD_LEN) {
9949 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
9950 if (vpd_extended_data == NULL)
9951 goto out_not_found;
9952
9953 /* read rest of vpd image into vpd_extended_data */
9954 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
9955 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
9956 block_end - BNX2X_VPD_LEN,
9957 vpd_extended_data + BNX2X_VPD_LEN);
9958 if (cnt < (block_end - BNX2X_VPD_LEN))
9959 goto out_not_found;
9960 vpd_data = vpd_extended_data;
9961 } else
9962 vpd_data = vpd_start;
9963
9964 /* now vpd_data holds full vpd content in both cases */
9965
9966 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9967 PCI_VPD_RO_KEYWORD_MFR_ID);
9968 if (rodi < 0)
9969 goto out_not_found;
9970
9971 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9972
9973 if (len != VENDOR_ID_LEN)
9974 goto out_not_found;
9975
9976 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9977
9978 /* vendor specific info */
9979 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9980 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9981 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9982 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9983
9984 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9985 PCI_VPD_RO_KEYWORD_VENDOR0);
9986 if (rodi >= 0) {
9987 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9988
9989 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9990
9991 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9992 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9993 bp->fw_ver[len] = ' ';
9994 }
9995 }
9996 kfree(vpd_extended_data);
9997 return;
9998 }
9999 out_not_found:
10000 kfree(vpd_extended_data);
10001 return;
10002 }
10003
10004 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
10005 {
10006 u32 flags = 0;
10007
10008 if (CHIP_REV_IS_FPGA(bp))
10009 SET_FLAGS(flags, MODE_FPGA);
10010 else if (CHIP_REV_IS_EMUL(bp))
10011 SET_FLAGS(flags, MODE_EMUL);
10012 else
10013 SET_FLAGS(flags, MODE_ASIC);
10014
10015 if (CHIP_MODE_IS_4_PORT(bp))
10016 SET_FLAGS(flags, MODE_PORT4);
10017 else
10018 SET_FLAGS(flags, MODE_PORT2);
10019
10020 if (CHIP_IS_E2(bp))
10021 SET_FLAGS(flags, MODE_E2);
10022 else if (CHIP_IS_E3(bp)) {
10023 SET_FLAGS(flags, MODE_E3);
10024 if (CHIP_REV(bp) == CHIP_REV_Ax)
10025 SET_FLAGS(flags, MODE_E3_A0);
10026 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
10027 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
10028 }
10029
10030 if (IS_MF(bp)) {
10031 SET_FLAGS(flags, MODE_MF);
10032 switch (bp->mf_mode) {
10033 case MULTI_FUNCTION_SD:
10034 SET_FLAGS(flags, MODE_MF_SD);
10035 break;
10036 case MULTI_FUNCTION_SI:
10037 SET_FLAGS(flags, MODE_MF_SI);
10038 break;
10039 }
10040 } else
10041 SET_FLAGS(flags, MODE_SF);
10042
10043 #if defined(__LITTLE_ENDIAN)
10044 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
10045 #else /*(__BIG_ENDIAN)*/
10046 SET_FLAGS(flags, MODE_BIG_ENDIAN);
10047 #endif
10048 INIT_MODE_FLAGS(bp) = flags;
10049 }
10050
10051 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
10052 {
10053 int func;
10054 int rc;
10055
10056 mutex_init(&bp->port.phy_mutex);
10057 mutex_init(&bp->fw_mb_mutex);
10058 spin_lock_init(&bp->stats_lock);
10059 #ifdef BCM_CNIC
10060 mutex_init(&bp->cnic_mutex);
10061 #endif
10062
10063 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
10064 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
10065 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
10066 rc = bnx2x_get_hwinfo(bp);
10067 if (rc)
10068 return rc;
10069
10070 bnx2x_set_modes_bitmap(bp);
10071
10072 rc = bnx2x_alloc_mem_bp(bp);
10073 if (rc)
10074 return rc;
10075
10076 bnx2x_read_fwinfo(bp);
10077
10078 func = BP_FUNC(bp);
10079
10080 /* need to reset chip if undi was active */
10081 if (!BP_NOMCP(bp))
10082 bnx2x_undi_unload(bp);
10083
10084 if (CHIP_REV_IS_FPGA(bp))
10085 dev_err(&bp->pdev->dev, "FPGA detected\n");
10086
10087 if (BP_NOMCP(bp) && (func == 0))
10088 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
10089
10090 bp->multi_mode = multi_mode;
10091
10092 bp->disable_tpa = disable_tpa;
10093
10094 #ifdef BCM_CNIC
10095 bp->disable_tpa |= IS_MF_ISCSI_SD(bp);
10096 #endif
10097
10098 /* Set TPA flags */
10099 if (bp->disable_tpa) {
10100 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
10101 bp->dev->features &= ~NETIF_F_LRO;
10102 } else {
10103 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
10104 bp->dev->features |= NETIF_F_LRO;
10105 }
10106
10107 if (CHIP_IS_E1(bp))
10108 bp->dropless_fc = 0;
10109 else
10110 bp->dropless_fc = dropless_fc;
10111
10112 bp->mrrs = mrrs;
10113
10114 bp->tx_ring_size = MAX_TX_AVAIL;
10115
10116 /* make sure that the numbers are in the right granularity */
10117 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
10118 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
10119
10120 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
10121
10122 init_timer(&bp->timer);
10123 bp->timer.expires = jiffies + bp->current_interval;
10124 bp->timer.data = (unsigned long) bp;
10125 bp->timer.function = bnx2x_timer;
10126
10127 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
10128 bnx2x_dcbx_init_params(bp);
10129
10130 #ifdef BCM_CNIC
10131 if (CHIP_IS_E1x(bp))
10132 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
10133 else
10134 bp->cnic_base_cl_id = FP_SB_MAX_E2;
10135 #endif
10136
10137 /* multiple tx priority */
10138 if (CHIP_IS_E1x(bp))
10139 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
10140 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
10141 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
10142 if (CHIP_IS_E3B0(bp))
10143 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
10144
10145 bp->gro_check = bnx2x_need_gro_check(bp->dev->mtu);
10146
10147 return rc;
10148 }
10149
10150
10151 /****************************************************************************
10152 * General service functions
10153 ****************************************************************************/
10154
10155 /*
10156 * net_device service functions
10157 */
10158
10159 /* called with rtnl_lock */
10160 static int bnx2x_open(struct net_device *dev)
10161 {
10162 struct bnx2x *bp = netdev_priv(dev);
10163 bool global = false;
10164 int other_engine = BP_PATH(bp) ? 0 : 1;
10165 bool other_load_status, load_status;
10166
10167 bp->stats_init = true;
10168
10169 netif_carrier_off(dev);
10170
10171 bnx2x_set_power_state(bp, PCI_D0);
10172
10173 other_load_status = bnx2x_get_load_status(bp, other_engine);
10174 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
10175
10176 /*
10177 * If parity had happen during the unload, then attentions
10178 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
10179 * want the first function loaded on the current engine to
10180 * complete the recovery.
10181 */
10182 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
10183 bnx2x_chk_parity_attn(bp, &global, true))
10184 do {
10185 /*
10186 * If there are attentions and they are in a global
10187 * blocks, set the GLOBAL_RESET bit regardless whether
10188 * it will be this function that will complete the
10189 * recovery or not.
10190 */
10191 if (global)
10192 bnx2x_set_reset_global(bp);
10193
10194 /*
10195 * Only the first function on the current engine should
10196 * try to recover in open. In case of attentions in
10197 * global blocks only the first in the chip should try
10198 * to recover.
10199 */
10200 if ((!load_status &&
10201 (!global || !other_load_status)) &&
10202 bnx2x_trylock_leader_lock(bp) &&
10203 !bnx2x_leader_reset(bp)) {
10204 netdev_info(bp->dev, "Recovered in open\n");
10205 break;
10206 }
10207
10208 /* recovery has failed... */
10209 bnx2x_set_power_state(bp, PCI_D3hot);
10210 bp->recovery_state = BNX2X_RECOVERY_FAILED;
10211
10212 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
10213 "If you still see this message after a few retries then power cycle is required.\n");
10214
10215 return -EAGAIN;
10216 } while (0);
10217
10218 bp->recovery_state = BNX2X_RECOVERY_DONE;
10219 return bnx2x_nic_load(bp, LOAD_OPEN);
10220 }
10221
10222 /* called with rtnl_lock */
10223 static int bnx2x_close(struct net_device *dev)
10224 {
10225 struct bnx2x *bp = netdev_priv(dev);
10226
10227 /* Unload the driver, release IRQs */
10228 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
10229
10230 /* Power off */
10231 bnx2x_set_power_state(bp, PCI_D3hot);
10232
10233 return 0;
10234 }
10235
10236 static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
10237 struct bnx2x_mcast_ramrod_params *p)
10238 {
10239 int mc_count = netdev_mc_count(bp->dev);
10240 struct bnx2x_mcast_list_elem *mc_mac =
10241 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
10242 struct netdev_hw_addr *ha;
10243
10244 if (!mc_mac)
10245 return -ENOMEM;
10246
10247 INIT_LIST_HEAD(&p->mcast_list);
10248
10249 netdev_for_each_mc_addr(ha, bp->dev) {
10250 mc_mac->mac = bnx2x_mc_addr(ha);
10251 list_add_tail(&mc_mac->link, &p->mcast_list);
10252 mc_mac++;
10253 }
10254
10255 p->mcast_list_len = mc_count;
10256
10257 return 0;
10258 }
10259
10260 static inline void bnx2x_free_mcast_macs_list(
10261 struct bnx2x_mcast_ramrod_params *p)
10262 {
10263 struct bnx2x_mcast_list_elem *mc_mac =
10264 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
10265 link);
10266
10267 WARN_ON(!mc_mac);
10268 kfree(mc_mac);
10269 }
10270
10271 /**
10272 * bnx2x_set_uc_list - configure a new unicast MACs list.
10273 *
10274 * @bp: driver handle
10275 *
10276 * We will use zero (0) as a MAC type for these MACs.
10277 */
10278 static inline int bnx2x_set_uc_list(struct bnx2x *bp)
10279 {
10280 int rc;
10281 struct net_device *dev = bp->dev;
10282 struct netdev_hw_addr *ha;
10283 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
10284 unsigned long ramrod_flags = 0;
10285
10286 /* First schedule a cleanup up of old configuration */
10287 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
10288 if (rc < 0) {
10289 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
10290 return rc;
10291 }
10292
10293 netdev_for_each_uc_addr(ha, dev) {
10294 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
10295 BNX2X_UC_LIST_MAC, &ramrod_flags);
10296 if (rc < 0) {
10297 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
10298 rc);
10299 return rc;
10300 }
10301 }
10302
10303 /* Execute the pending commands */
10304 __set_bit(RAMROD_CONT, &ramrod_flags);
10305 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
10306 BNX2X_UC_LIST_MAC, &ramrod_flags);
10307 }
10308
10309 static inline int bnx2x_set_mc_list(struct bnx2x *bp)
10310 {
10311 struct net_device *dev = bp->dev;
10312 struct bnx2x_mcast_ramrod_params rparam = {0};
10313 int rc = 0;
10314
10315 rparam.mcast_obj = &bp->mcast_obj;
10316
10317 /* first, clear all configured multicast MACs */
10318 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
10319 if (rc < 0) {
10320 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
10321 return rc;
10322 }
10323
10324 /* then, configure a new MACs list */
10325 if (netdev_mc_count(dev)) {
10326 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
10327 if (rc) {
10328 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
10329 rc);
10330 return rc;
10331 }
10332
10333 /* Now add the new MACs */
10334 rc = bnx2x_config_mcast(bp, &rparam,
10335 BNX2X_MCAST_CMD_ADD);
10336 if (rc < 0)
10337 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
10338 rc);
10339
10340 bnx2x_free_mcast_macs_list(&rparam);
10341 }
10342
10343 return rc;
10344 }
10345
10346
10347 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
10348 void bnx2x_set_rx_mode(struct net_device *dev)
10349 {
10350 struct bnx2x *bp = netdev_priv(dev);
10351 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
10352
10353 if (bp->state != BNX2X_STATE_OPEN) {
10354 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10355 return;
10356 }
10357
10358 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
10359
10360 if (dev->flags & IFF_PROMISC)
10361 rx_mode = BNX2X_RX_MODE_PROMISC;
10362 else if ((dev->flags & IFF_ALLMULTI) ||
10363 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10364 CHIP_IS_E1(bp)))
10365 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10366 else {
10367 /* some multicasts */
10368 if (bnx2x_set_mc_list(bp) < 0)
10369 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10370
10371 if (bnx2x_set_uc_list(bp) < 0)
10372 rx_mode = BNX2X_RX_MODE_PROMISC;
10373 }
10374
10375 bp->rx_mode = rx_mode;
10376 #ifdef BCM_CNIC
10377 /* handle ISCSI SD mode */
10378 if (IS_MF_ISCSI_SD(bp))
10379 bp->rx_mode = BNX2X_RX_MODE_NONE;
10380 #endif
10381
10382 /* Schedule the rx_mode command */
10383 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10384 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10385 return;
10386 }
10387
10388 bnx2x_set_storm_rx_mode(bp);
10389 }
10390
10391 /* called with rtnl_lock */
10392 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10393 int devad, u16 addr)
10394 {
10395 struct bnx2x *bp = netdev_priv(netdev);
10396 u16 value;
10397 int rc;
10398
10399 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10400 prtad, devad, addr);
10401
10402 /* The HW expects different devad if CL22 is used */
10403 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10404
10405 bnx2x_acquire_phy_lock(bp);
10406 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
10407 bnx2x_release_phy_lock(bp);
10408 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
10409
10410 if (!rc)
10411 rc = value;
10412 return rc;
10413 }
10414
10415 /* called with rtnl_lock */
10416 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10417 u16 addr, u16 value)
10418 {
10419 struct bnx2x *bp = netdev_priv(netdev);
10420 int rc;
10421
10422 DP(NETIF_MSG_LINK,
10423 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
10424 prtad, devad, addr, value);
10425
10426 /* The HW expects different devad if CL22 is used */
10427 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10428
10429 bnx2x_acquire_phy_lock(bp);
10430 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
10431 bnx2x_release_phy_lock(bp);
10432 return rc;
10433 }
10434
10435 /* called with rtnl_lock */
10436 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10437 {
10438 struct bnx2x *bp = netdev_priv(dev);
10439 struct mii_ioctl_data *mdio = if_mii(ifr);
10440
10441 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10442 mdio->phy_id, mdio->reg_num, mdio->val_in);
10443
10444 if (!netif_running(dev))
10445 return -EAGAIN;
10446
10447 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
10448 }
10449
10450 #ifdef CONFIG_NET_POLL_CONTROLLER
10451 static void poll_bnx2x(struct net_device *dev)
10452 {
10453 struct bnx2x *bp = netdev_priv(dev);
10454
10455 disable_irq(bp->pdev->irq);
10456 bnx2x_interrupt(bp->pdev->irq, dev);
10457 enable_irq(bp->pdev->irq);
10458 }
10459 #endif
10460
10461 static int bnx2x_validate_addr(struct net_device *dev)
10462 {
10463 struct bnx2x *bp = netdev_priv(dev);
10464
10465 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
10466 BNX2X_ERR("Non-valid Ethernet address\n");
10467 return -EADDRNOTAVAIL;
10468 }
10469 return 0;
10470 }
10471
10472 static const struct net_device_ops bnx2x_netdev_ops = {
10473 .ndo_open = bnx2x_open,
10474 .ndo_stop = bnx2x_close,
10475 .ndo_start_xmit = bnx2x_start_xmit,
10476 .ndo_select_queue = bnx2x_select_queue,
10477 .ndo_set_rx_mode = bnx2x_set_rx_mode,
10478 .ndo_set_mac_address = bnx2x_change_mac_addr,
10479 .ndo_validate_addr = bnx2x_validate_addr,
10480 .ndo_do_ioctl = bnx2x_ioctl,
10481 .ndo_change_mtu = bnx2x_change_mtu,
10482 .ndo_fix_features = bnx2x_fix_features,
10483 .ndo_set_features = bnx2x_set_features,
10484 .ndo_tx_timeout = bnx2x_tx_timeout,
10485 #ifdef CONFIG_NET_POLL_CONTROLLER
10486 .ndo_poll_controller = poll_bnx2x,
10487 #endif
10488 .ndo_setup_tc = bnx2x_setup_tc,
10489
10490 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10491 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10492 #endif
10493 };
10494
10495 static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10496 {
10497 struct device *dev = &bp->pdev->dev;
10498
10499 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10500 bp->flags |= USING_DAC_FLAG;
10501 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10502 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
10503 return -EIO;
10504 }
10505 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10506 dev_err(dev, "System does not support DMA, aborting\n");
10507 return -EIO;
10508 }
10509
10510 return 0;
10511 }
10512
10513 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10514 struct net_device *dev,
10515 unsigned long board_type)
10516 {
10517 struct bnx2x *bp;
10518 int rc;
10519 u32 pci_cfg_dword;
10520 bool chip_is_e1x = (board_type == BCM57710 ||
10521 board_type == BCM57711 ||
10522 board_type == BCM57711E);
10523
10524 SET_NETDEV_DEV(dev, &pdev->dev);
10525 bp = netdev_priv(dev);
10526
10527 bp->dev = dev;
10528 bp->pdev = pdev;
10529 bp->flags = 0;
10530
10531 rc = pci_enable_device(pdev);
10532 if (rc) {
10533 dev_err(&bp->pdev->dev,
10534 "Cannot enable PCI device, aborting\n");
10535 goto err_out;
10536 }
10537
10538 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10539 dev_err(&bp->pdev->dev,
10540 "Cannot find PCI device base address, aborting\n");
10541 rc = -ENODEV;
10542 goto err_out_disable;
10543 }
10544
10545 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
10546 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10547 " base address, aborting\n");
10548 rc = -ENODEV;
10549 goto err_out_disable;
10550 }
10551
10552 if (atomic_read(&pdev->enable_cnt) == 1) {
10553 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10554 if (rc) {
10555 dev_err(&bp->pdev->dev,
10556 "Cannot obtain PCI resources, aborting\n");
10557 goto err_out_disable;
10558 }
10559
10560 pci_set_master(pdev);
10561 pci_save_state(pdev);
10562 }
10563
10564 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10565 if (bp->pm_cap == 0) {
10566 dev_err(&bp->pdev->dev,
10567 "Cannot find power management capability, aborting\n");
10568 rc = -EIO;
10569 goto err_out_release;
10570 }
10571
10572 if (!pci_is_pcie(pdev)) {
10573 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
10574 rc = -EIO;
10575 goto err_out_release;
10576 }
10577
10578 rc = bnx2x_set_coherency_mask(bp);
10579 if (rc)
10580 goto err_out_release;
10581
10582 dev->mem_start = pci_resource_start(pdev, 0);
10583 dev->base_addr = dev->mem_start;
10584 dev->mem_end = pci_resource_end(pdev, 0);
10585
10586 dev->irq = pdev->irq;
10587
10588 bp->regview = pci_ioremap_bar(pdev, 0);
10589 if (!bp->regview) {
10590 dev_err(&bp->pdev->dev,
10591 "Cannot map register space, aborting\n");
10592 rc = -ENOMEM;
10593 goto err_out_release;
10594 }
10595
10596 /* In E1/E1H use pci device function given by kernel.
10597 * In E2/E3 read physical function from ME register since these chips
10598 * support Physical Device Assignment where kernel BDF maybe arbitrary
10599 * (depending on hypervisor).
10600 */
10601 if (chip_is_e1x)
10602 bp->pf_num = PCI_FUNC(pdev->devfn);
10603 else {/* chip is E2/3*/
10604 pci_read_config_dword(bp->pdev,
10605 PCICFG_ME_REGISTER, &pci_cfg_dword);
10606 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
10607 ME_REG_ABS_PF_NUM_SHIFT);
10608 }
10609 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
10610
10611 bnx2x_set_power_state(bp, PCI_D0);
10612
10613 /* clean indirect addresses */
10614 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10615 PCICFG_VENDOR_ID_OFFSET);
10616 /*
10617 * Clean the following indirect addresses for all functions since it
10618 * is not used by the driver.
10619 */
10620 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
10621 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
10622 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
10623 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
10624
10625 if (chip_is_e1x) {
10626 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
10627 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
10628 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
10629 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
10630 }
10631
10632 /*
10633 * Enable internal target-read (in case we are probed after PF FLR).
10634 * Must be done prior to any BAR read access. Only for 57712 and up
10635 */
10636 if (!chip_is_e1x)
10637 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10638
10639 /* Reset the load counter */
10640 bnx2x_clear_load_status(bp);
10641
10642 dev->watchdog_timeo = TX_TIMEOUT;
10643
10644 dev->netdev_ops = &bnx2x_netdev_ops;
10645 bnx2x_set_ethtool_ops(dev);
10646
10647 dev->priv_flags |= IFF_UNICAST_FLT;
10648
10649 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10650 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
10651 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
10652 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
10653
10654 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10655 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10656
10657 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
10658 if (bp->flags & USING_DAC_FLAG)
10659 dev->features |= NETIF_F_HIGHDMA;
10660
10661 /* Add Loopback capability to the device */
10662 dev->hw_features |= NETIF_F_LOOPBACK;
10663
10664 #ifdef BCM_DCBNL
10665 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10666 #endif
10667
10668 /* get_port_hwinfo() will set prtad and mmds properly */
10669 bp->mdio.prtad = MDIO_PRTAD_NONE;
10670 bp->mdio.mmds = 0;
10671 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10672 bp->mdio.dev = dev;
10673 bp->mdio.mdio_read = bnx2x_mdio_read;
10674 bp->mdio.mdio_write = bnx2x_mdio_write;
10675
10676 return 0;
10677
10678 err_out_release:
10679 if (atomic_read(&pdev->enable_cnt) == 1)
10680 pci_release_regions(pdev);
10681
10682 err_out_disable:
10683 pci_disable_device(pdev);
10684 pci_set_drvdata(pdev, NULL);
10685
10686 err_out:
10687 return rc;
10688 }
10689
10690 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10691 int *width, int *speed)
10692 {
10693 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10694
10695 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
10696
10697 /* return value of 1=2.5GHz 2=5GHz */
10698 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
10699 }
10700
10701 static int bnx2x_check_firmware(struct bnx2x *bp)
10702 {
10703 const struct firmware *firmware = bp->firmware;
10704 struct bnx2x_fw_file_hdr *fw_hdr;
10705 struct bnx2x_fw_file_section *sections;
10706 u32 offset, len, num_ops;
10707 u16 *ops_offsets;
10708 int i;
10709 const u8 *fw_ver;
10710
10711 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
10712 BNX2X_ERR("Wrong FW size\n");
10713 return -EINVAL;
10714 }
10715
10716 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10717 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10718
10719 /* Make sure none of the offsets and sizes make us read beyond
10720 * the end of the firmware data */
10721 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10722 offset = be32_to_cpu(sections[i].offset);
10723 len = be32_to_cpu(sections[i].len);
10724 if (offset + len > firmware->size) {
10725 BNX2X_ERR("Section %d length is out of bounds\n", i);
10726 return -EINVAL;
10727 }
10728 }
10729
10730 /* Likewise for the init_ops offsets */
10731 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10732 ops_offsets = (u16 *)(firmware->data + offset);
10733 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10734
10735 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10736 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
10737 BNX2X_ERR("Section offset %d is out of bounds\n", i);
10738 return -EINVAL;
10739 }
10740 }
10741
10742 /* Check FW version */
10743 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10744 fw_ver = firmware->data + offset;
10745 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10746 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10747 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10748 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
10749 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10750 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
10751 BCM_5710_FW_MAJOR_VERSION,
10752 BCM_5710_FW_MINOR_VERSION,
10753 BCM_5710_FW_REVISION_VERSION,
10754 BCM_5710_FW_ENGINEERING_VERSION);
10755 return -EINVAL;
10756 }
10757
10758 return 0;
10759 }
10760
10761 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10762 {
10763 const __be32 *source = (const __be32 *)_source;
10764 u32 *target = (u32 *)_target;
10765 u32 i;
10766
10767 for (i = 0; i < n/4; i++)
10768 target[i] = be32_to_cpu(source[i]);
10769 }
10770
10771 /*
10772 Ops array is stored in the following format:
10773 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10774 */
10775 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
10776 {
10777 const __be32 *source = (const __be32 *)_source;
10778 struct raw_op *target = (struct raw_op *)_target;
10779 u32 i, j, tmp;
10780
10781 for (i = 0, j = 0; i < n/8; i++, j += 2) {
10782 tmp = be32_to_cpu(source[j]);
10783 target[i].op = (tmp >> 24) & 0xff;
10784 target[i].offset = tmp & 0xffffff;
10785 target[i].raw_data = be32_to_cpu(source[j + 1]);
10786 }
10787 }
10788
10789 /**
10790 * IRO array is stored in the following format:
10791 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10792 */
10793 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10794 {
10795 const __be32 *source = (const __be32 *)_source;
10796 struct iro *target = (struct iro *)_target;
10797 u32 i, j, tmp;
10798
10799 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10800 target[i].base = be32_to_cpu(source[j]);
10801 j++;
10802 tmp = be32_to_cpu(source[j]);
10803 target[i].m1 = (tmp >> 16) & 0xffff;
10804 target[i].m2 = tmp & 0xffff;
10805 j++;
10806 tmp = be32_to_cpu(source[j]);
10807 target[i].m3 = (tmp >> 16) & 0xffff;
10808 target[i].size = tmp & 0xffff;
10809 j++;
10810 }
10811 }
10812
10813 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10814 {
10815 const __be16 *source = (const __be16 *)_source;
10816 u16 *target = (u16 *)_target;
10817 u32 i;
10818
10819 for (i = 0; i < n/2; i++)
10820 target[i] = be16_to_cpu(source[i]);
10821 }
10822
10823 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10824 do { \
10825 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10826 bp->arr = kmalloc(len, GFP_KERNEL); \
10827 if (!bp->arr) \
10828 goto lbl; \
10829 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10830 (u8 *)bp->arr, len); \
10831 } while (0)
10832
10833 int bnx2x_init_firmware(struct bnx2x *bp)
10834 {
10835 const char *fw_file_name;
10836 struct bnx2x_fw_file_hdr *fw_hdr;
10837 int rc;
10838
10839 if (bp->firmware)
10840 return 0;
10841
10842 if (CHIP_IS_E1(bp))
10843 fw_file_name = FW_FILE_NAME_E1;
10844 else if (CHIP_IS_E1H(bp))
10845 fw_file_name = FW_FILE_NAME_E1H;
10846 else if (!CHIP_IS_E1x(bp))
10847 fw_file_name = FW_FILE_NAME_E2;
10848 else {
10849 BNX2X_ERR("Unsupported chip revision\n");
10850 return -EINVAL;
10851 }
10852 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
10853
10854 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
10855 if (rc) {
10856 BNX2X_ERR("Can't load firmware file %s\n",
10857 fw_file_name);
10858 goto request_firmware_exit;
10859 }
10860
10861 rc = bnx2x_check_firmware(bp);
10862 if (rc) {
10863 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
10864 goto request_firmware_exit;
10865 }
10866
10867 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10868
10869 /* Initialize the pointers to the init arrays */
10870 /* Blob */
10871 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10872
10873 /* Opcodes */
10874 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10875
10876 /* Offsets */
10877 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10878 be16_to_cpu_n);
10879
10880 /* STORMs firmware */
10881 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10882 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10883 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10884 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10885 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10886 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10887 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10888 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10889 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10890 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10891 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10892 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10893 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10894 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10895 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10896 be32_to_cpu(fw_hdr->csem_pram_data.offset);
10897 /* IRO */
10898 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
10899
10900 return 0;
10901
10902 iro_alloc_err:
10903 kfree(bp->init_ops_offsets);
10904 init_offsets_alloc_err:
10905 kfree(bp->init_ops);
10906 init_ops_alloc_err:
10907 kfree(bp->init_data);
10908 request_firmware_exit:
10909 release_firmware(bp->firmware);
10910 bp->firmware = NULL;
10911
10912 return rc;
10913 }
10914
10915 static void bnx2x_release_firmware(struct bnx2x *bp)
10916 {
10917 kfree(bp->init_ops_offsets);
10918 kfree(bp->init_ops);
10919 kfree(bp->init_data);
10920 release_firmware(bp->firmware);
10921 bp->firmware = NULL;
10922 }
10923
10924
10925 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10926 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10927 .init_hw_cmn = bnx2x_init_hw_common,
10928 .init_hw_port = bnx2x_init_hw_port,
10929 .init_hw_func = bnx2x_init_hw_func,
10930
10931 .reset_hw_cmn = bnx2x_reset_common,
10932 .reset_hw_port = bnx2x_reset_port,
10933 .reset_hw_func = bnx2x_reset_func,
10934
10935 .gunzip_init = bnx2x_gunzip_init,
10936 .gunzip_end = bnx2x_gunzip_end,
10937
10938 .init_fw = bnx2x_init_firmware,
10939 .release_fw = bnx2x_release_firmware,
10940 };
10941
10942 void bnx2x__init_func_obj(struct bnx2x *bp)
10943 {
10944 /* Prepare DMAE related driver resources */
10945 bnx2x_setup_dmae(bp);
10946
10947 bnx2x_init_func_obj(bp, &bp->func_obj,
10948 bnx2x_sp(bp, func_rdata),
10949 bnx2x_sp_mapping(bp, func_rdata),
10950 &bnx2x_func_sp_drv);
10951 }
10952
10953 /* must be called after sriov-enable */
10954 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
10955 {
10956 int cid_count = BNX2X_L2_CID_COUNT(bp);
10957
10958 #ifdef BCM_CNIC
10959 cid_count += CNIC_CID_MAX;
10960 #endif
10961 return roundup(cid_count, QM_CID_ROUND);
10962 }
10963
10964 /**
10965 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
10966 *
10967 * @dev: pci device
10968 *
10969 */
10970 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
10971 {
10972 int pos;
10973 u16 control;
10974
10975 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
10976
10977 /*
10978 * If MSI-X is not supported - return number of SBs needed to support
10979 * one fast path queue: one FP queue + SB for CNIC
10980 */
10981 if (!pos)
10982 return 1 + CNIC_PRESENT;
10983
10984 /*
10985 * The value in the PCI configuration space is the index of the last
10986 * entry, namely one less than the actual size of the table, which is
10987 * exactly what we want to return from this function: number of all SBs
10988 * without the default SB.
10989 */
10990 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
10991 return control & PCI_MSIX_FLAGS_QSIZE;
10992 }
10993
10994 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10995 const struct pci_device_id *ent)
10996 {
10997 struct net_device *dev = NULL;
10998 struct bnx2x *bp;
10999 int pcie_width, pcie_speed;
11000 int rc, max_non_def_sbs;
11001 int rx_count, tx_count, rss_count;
11002 /*
11003 * An estimated maximum supported CoS number according to the chip
11004 * version.
11005 * We will try to roughly estimate the maximum number of CoSes this chip
11006 * may support in order to minimize the memory allocated for Tx
11007 * netdev_queue's. This number will be accurately calculated during the
11008 * initialization of bp->max_cos based on the chip versions AND chip
11009 * revision in the bnx2x_init_bp().
11010 */
11011 u8 max_cos_est = 0;
11012
11013 switch (ent->driver_data) {
11014 case BCM57710:
11015 case BCM57711:
11016 case BCM57711E:
11017 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
11018 break;
11019
11020 case BCM57712:
11021 case BCM57712_MF:
11022 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
11023 break;
11024
11025 case BCM57800:
11026 case BCM57800_MF:
11027 case BCM57810:
11028 case BCM57810_MF:
11029 case BCM57840:
11030 case BCM57840_MF:
11031 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
11032 break;
11033
11034 default:
11035 pr_err("Unknown board_type (%ld), aborting\n",
11036 ent->driver_data);
11037 return -ENODEV;
11038 }
11039
11040 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
11041
11042 /* !!! FIXME !!!
11043 * Do not allow the maximum SB count to grow above 16
11044 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
11045 * We will use the FP_SB_MAX_E1x macro for this matter.
11046 */
11047 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
11048
11049 WARN_ON(!max_non_def_sbs);
11050
11051 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
11052 rss_count = max_non_def_sbs - CNIC_PRESENT;
11053
11054 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
11055 rx_count = rss_count + FCOE_PRESENT;
11056
11057 /*
11058 * Maximum number of netdev Tx queues:
11059 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
11060 */
11061 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
11062
11063 /* dev zeroed in init_etherdev */
11064 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
11065 if (!dev)
11066 return -ENOMEM;
11067
11068 bp = netdev_priv(dev);
11069
11070 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
11071 tx_count, rx_count);
11072
11073 bp->igu_sb_cnt = max_non_def_sbs;
11074 bp->msg_enable = debug;
11075 pci_set_drvdata(pdev, dev);
11076
11077 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
11078 if (rc < 0) {
11079 free_netdev(dev);
11080 return rc;
11081 }
11082
11083 BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs);
11084
11085 rc = bnx2x_init_bp(bp);
11086 if (rc)
11087 goto init_one_exit;
11088
11089 /*
11090 * Map doorbels here as we need the real value of bp->max_cos which
11091 * is initialized in bnx2x_init_bp().
11092 */
11093 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
11094 min_t(u64, BNX2X_DB_SIZE(bp),
11095 pci_resource_len(pdev, 2)));
11096 if (!bp->doorbells) {
11097 dev_err(&bp->pdev->dev,
11098 "Cannot map doorbell space, aborting\n");
11099 rc = -ENOMEM;
11100 goto init_one_exit;
11101 }
11102
11103 /* calc qm_cid_count */
11104 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
11105
11106 #ifdef BCM_CNIC
11107 /* disable FCOE L2 queue for E1x */
11108 if (CHIP_IS_E1x(bp))
11109 bp->flags |= NO_FCOE_FLAG;
11110
11111 #endif
11112
11113 /* Configure interrupt mode: try to enable MSI-X/MSI if
11114 * needed, set bp->num_queues appropriately.
11115 */
11116 bnx2x_set_int_mode(bp);
11117
11118 /* Add all NAPI objects */
11119 bnx2x_add_all_napi(bp);
11120
11121 rc = register_netdev(dev);
11122 if (rc) {
11123 dev_err(&pdev->dev, "Cannot register net device\n");
11124 goto init_one_exit;
11125 }
11126
11127 #ifdef BCM_CNIC
11128 if (!NO_FCOE(bp)) {
11129 /* Add storage MAC address */
11130 rtnl_lock();
11131 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11132 rtnl_unlock();
11133 }
11134 #endif
11135
11136 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
11137
11138 BNX2X_DEV_INFO(
11139 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
11140 board_info[ent->driver_data].name,
11141 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
11142 pcie_width,
11143 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
11144 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
11145 "5GHz (Gen2)" : "2.5GHz",
11146 dev->base_addr, bp->pdev->irq, dev->dev_addr);
11147
11148 return 0;
11149
11150 init_one_exit:
11151 if (bp->regview)
11152 iounmap(bp->regview);
11153
11154 if (bp->doorbells)
11155 iounmap(bp->doorbells);
11156
11157 free_netdev(dev);
11158
11159 if (atomic_read(&pdev->enable_cnt) == 1)
11160 pci_release_regions(pdev);
11161
11162 pci_disable_device(pdev);
11163 pci_set_drvdata(pdev, NULL);
11164
11165 return rc;
11166 }
11167
11168 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
11169 {
11170 struct net_device *dev = pci_get_drvdata(pdev);
11171 struct bnx2x *bp;
11172
11173 if (!dev) {
11174 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
11175 return;
11176 }
11177 bp = netdev_priv(dev);
11178
11179 #ifdef BCM_CNIC
11180 /* Delete storage MAC address */
11181 if (!NO_FCOE(bp)) {
11182 rtnl_lock();
11183 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11184 rtnl_unlock();
11185 }
11186 #endif
11187
11188 #ifdef BCM_DCBNL
11189 /* Delete app tlvs from dcbnl */
11190 bnx2x_dcbnl_update_applist(bp, true);
11191 #endif
11192
11193 unregister_netdev(dev);
11194
11195 /* Delete all NAPI objects */
11196 bnx2x_del_all_napi(bp);
11197
11198 /* Power on: we can't let PCI layer write to us while we are in D3 */
11199 bnx2x_set_power_state(bp, PCI_D0);
11200
11201 /* Disable MSI/MSI-X */
11202 bnx2x_disable_msi(bp);
11203
11204 /* Power off */
11205 bnx2x_set_power_state(bp, PCI_D3hot);
11206
11207 /* Make sure RESET task is not scheduled before continuing */
11208 cancel_delayed_work_sync(&bp->sp_rtnl_task);
11209
11210 if (bp->regview)
11211 iounmap(bp->regview);
11212
11213 if (bp->doorbells)
11214 iounmap(bp->doorbells);
11215
11216 bnx2x_release_firmware(bp);
11217
11218 bnx2x_free_mem_bp(bp);
11219
11220 free_netdev(dev);
11221
11222 if (atomic_read(&pdev->enable_cnt) == 1)
11223 pci_release_regions(pdev);
11224
11225 pci_disable_device(pdev);
11226 pci_set_drvdata(pdev, NULL);
11227 }
11228
11229 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
11230 {
11231 int i;
11232
11233 bp->state = BNX2X_STATE_ERROR;
11234
11235 bp->rx_mode = BNX2X_RX_MODE_NONE;
11236
11237 #ifdef BCM_CNIC
11238 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
11239 #endif
11240 /* Stop Tx */
11241 bnx2x_tx_disable(bp);
11242
11243 bnx2x_netif_stop(bp, 0);
11244
11245 del_timer_sync(&bp->timer);
11246
11247 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
11248
11249 /* Release IRQs */
11250 bnx2x_free_irq(bp);
11251
11252 /* Free SKBs, SGEs, TPA pool and driver internals */
11253 bnx2x_free_skbs(bp);
11254
11255 for_each_rx_queue(bp, i)
11256 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
11257
11258 bnx2x_free_mem(bp);
11259
11260 bp->state = BNX2X_STATE_CLOSED;
11261
11262 netif_carrier_off(bp->dev);
11263
11264 return 0;
11265 }
11266
11267 static void bnx2x_eeh_recover(struct bnx2x *bp)
11268 {
11269 u32 val;
11270
11271 mutex_init(&bp->port.phy_mutex);
11272
11273
11274 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
11275 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11276 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11277 BNX2X_ERR("BAD MCP validity signature\n");
11278 }
11279
11280 /**
11281 * bnx2x_io_error_detected - called when PCI error is detected
11282 * @pdev: Pointer to PCI device
11283 * @state: The current pci connection state
11284 *
11285 * This function is called after a PCI bus error affecting
11286 * this device has been detected.
11287 */
11288 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
11289 pci_channel_state_t state)
11290 {
11291 struct net_device *dev = pci_get_drvdata(pdev);
11292 struct bnx2x *bp = netdev_priv(dev);
11293
11294 rtnl_lock();
11295
11296 netif_device_detach(dev);
11297
11298 if (state == pci_channel_io_perm_failure) {
11299 rtnl_unlock();
11300 return PCI_ERS_RESULT_DISCONNECT;
11301 }
11302
11303 if (netif_running(dev))
11304 bnx2x_eeh_nic_unload(bp);
11305
11306 pci_disable_device(pdev);
11307
11308 rtnl_unlock();
11309
11310 /* Request a slot reset */
11311 return PCI_ERS_RESULT_NEED_RESET;
11312 }
11313
11314 /**
11315 * bnx2x_io_slot_reset - called after the PCI bus has been reset
11316 * @pdev: Pointer to PCI device
11317 *
11318 * Restart the card from scratch, as if from a cold-boot.
11319 */
11320 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
11321 {
11322 struct net_device *dev = pci_get_drvdata(pdev);
11323 struct bnx2x *bp = netdev_priv(dev);
11324
11325 rtnl_lock();
11326
11327 if (pci_enable_device(pdev)) {
11328 dev_err(&pdev->dev,
11329 "Cannot re-enable PCI device after reset\n");
11330 rtnl_unlock();
11331 return PCI_ERS_RESULT_DISCONNECT;
11332 }
11333
11334 pci_set_master(pdev);
11335 pci_restore_state(pdev);
11336
11337 if (netif_running(dev))
11338 bnx2x_set_power_state(bp, PCI_D0);
11339
11340 rtnl_unlock();
11341
11342 return PCI_ERS_RESULT_RECOVERED;
11343 }
11344
11345 /**
11346 * bnx2x_io_resume - called when traffic can start flowing again
11347 * @pdev: Pointer to PCI device
11348 *
11349 * This callback is called when the error recovery driver tells us that
11350 * its OK to resume normal operation.
11351 */
11352 static void bnx2x_io_resume(struct pci_dev *pdev)
11353 {
11354 struct net_device *dev = pci_get_drvdata(pdev);
11355 struct bnx2x *bp = netdev_priv(dev);
11356
11357 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
11358 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
11359 return;
11360 }
11361
11362 rtnl_lock();
11363
11364 bnx2x_eeh_recover(bp);
11365
11366 if (netif_running(dev))
11367 bnx2x_nic_load(bp, LOAD_NORMAL);
11368
11369 netif_device_attach(dev);
11370
11371 rtnl_unlock();
11372 }
11373
11374 static struct pci_error_handlers bnx2x_err_handler = {
11375 .error_detected = bnx2x_io_error_detected,
11376 .slot_reset = bnx2x_io_slot_reset,
11377 .resume = bnx2x_io_resume,
11378 };
11379
11380 static struct pci_driver bnx2x_pci_driver = {
11381 .name = DRV_MODULE_NAME,
11382 .id_table = bnx2x_pci_tbl,
11383 .probe = bnx2x_init_one,
11384 .remove = __devexit_p(bnx2x_remove_one),
11385 .suspend = bnx2x_suspend,
11386 .resume = bnx2x_resume,
11387 .err_handler = &bnx2x_err_handler,
11388 };
11389
11390 static int __init bnx2x_init(void)
11391 {
11392 int ret;
11393
11394 pr_info("%s", version);
11395
11396 bnx2x_wq = create_singlethread_workqueue("bnx2x");
11397 if (bnx2x_wq == NULL) {
11398 pr_err("Cannot create workqueue\n");
11399 return -ENOMEM;
11400 }
11401
11402 ret = pci_register_driver(&bnx2x_pci_driver);
11403 if (ret) {
11404 pr_err("Cannot register driver\n");
11405 destroy_workqueue(bnx2x_wq);
11406 }
11407 return ret;
11408 }
11409
11410 static void __exit bnx2x_cleanup(void)
11411 {
11412 pci_unregister_driver(&bnx2x_pci_driver);
11413
11414 destroy_workqueue(bnx2x_wq);
11415 }
11416
11417 void bnx2x_notify_link_changed(struct bnx2x *bp)
11418 {
11419 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11420 }
11421
11422 module_init(bnx2x_init);
11423 module_exit(bnx2x_cleanup);
11424
11425 #ifdef BCM_CNIC
11426 /**
11427 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11428 *
11429 * @bp: driver handle
11430 * @set: set or clear the CAM entry
11431 *
11432 * This function will wait until the ramdord completion returns.
11433 * Return 0 if success, -ENODEV if ramrod doesn't return.
11434 */
11435 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11436 {
11437 unsigned long ramrod_flags = 0;
11438
11439 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11440 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11441 &bp->iscsi_l2_mac_obj, true,
11442 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11443 }
11444
11445 /* count denotes the number of new completions we have seen */
11446 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11447 {
11448 struct eth_spe *spe;
11449
11450 #ifdef BNX2X_STOP_ON_ERROR
11451 if (unlikely(bp->panic))
11452 return;
11453 #endif
11454
11455 spin_lock_bh(&bp->spq_lock);
11456 BUG_ON(bp->cnic_spq_pending < count);
11457 bp->cnic_spq_pending -= count;
11458
11459
11460 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11461 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11462 & SPE_HDR_CONN_TYPE) >>
11463 SPE_HDR_CONN_TYPE_SHIFT;
11464 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11465 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
11466
11467 /* Set validation for iSCSI L2 client before sending SETUP
11468 * ramrod
11469 */
11470 if (type == ETH_CONNECTION_TYPE) {
11471 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
11472 bnx2x_set_ctx_validation(bp, &bp->context.
11473 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11474 BNX2X_ISCSI_ETH_CID);
11475 }
11476
11477 /*
11478 * There may be not more than 8 L2, not more than 8 L5 SPEs
11479 * and in the air. We also check that number of outstanding
11480 * COMMON ramrods is not more than the EQ and SPQ can
11481 * accommodate.
11482 */
11483 if (type == ETH_CONNECTION_TYPE) {
11484 if (!atomic_read(&bp->cq_spq_left))
11485 break;
11486 else
11487 atomic_dec(&bp->cq_spq_left);
11488 } else if (type == NONE_CONNECTION_TYPE) {
11489 if (!atomic_read(&bp->eq_spq_left))
11490 break;
11491 else
11492 atomic_dec(&bp->eq_spq_left);
11493 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11494 (type == FCOE_CONNECTION_TYPE)) {
11495 if (bp->cnic_spq_pending >=
11496 bp->cnic_eth_dev.max_kwqe_pending)
11497 break;
11498 else
11499 bp->cnic_spq_pending++;
11500 } else {
11501 BNX2X_ERR("Unknown SPE type: %d\n", type);
11502 bnx2x_panic();
11503 break;
11504 }
11505
11506 spe = bnx2x_sp_get_next(bp);
11507 *spe = *bp->cnic_kwq_cons;
11508
11509 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
11510 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11511
11512 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11513 bp->cnic_kwq_cons = bp->cnic_kwq;
11514 else
11515 bp->cnic_kwq_cons++;
11516 }
11517 bnx2x_sp_prod_update(bp);
11518 spin_unlock_bh(&bp->spq_lock);
11519 }
11520
11521 static int bnx2x_cnic_sp_queue(struct net_device *dev,
11522 struct kwqe_16 *kwqes[], u32 count)
11523 {
11524 struct bnx2x *bp = netdev_priv(dev);
11525 int i;
11526
11527 #ifdef BNX2X_STOP_ON_ERROR
11528 if (unlikely(bp->panic)) {
11529 BNX2X_ERR("Can't post to SP queue while panic\n");
11530 return -EIO;
11531 }
11532 #endif
11533
11534 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
11535 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
11536 BNX2X_ERR("Handling parity error recovery. Try again later\n");
11537 return -EAGAIN;
11538 }
11539
11540 spin_lock_bh(&bp->spq_lock);
11541
11542 for (i = 0; i < count; i++) {
11543 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11544
11545 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11546 break;
11547
11548 *bp->cnic_kwq_prod = *spe;
11549
11550 bp->cnic_kwq_pending++;
11551
11552 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
11553 spe->hdr.conn_and_cmd_data, spe->hdr.type,
11554 spe->data.update_data_addr.hi,
11555 spe->data.update_data_addr.lo,
11556 bp->cnic_kwq_pending);
11557
11558 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11559 bp->cnic_kwq_prod = bp->cnic_kwq;
11560 else
11561 bp->cnic_kwq_prod++;
11562 }
11563
11564 spin_unlock_bh(&bp->spq_lock);
11565
11566 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11567 bnx2x_cnic_sp_post(bp, 0);
11568
11569 return i;
11570 }
11571
11572 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11573 {
11574 struct cnic_ops *c_ops;
11575 int rc = 0;
11576
11577 mutex_lock(&bp->cnic_mutex);
11578 c_ops = rcu_dereference_protected(bp->cnic_ops,
11579 lockdep_is_held(&bp->cnic_mutex));
11580 if (c_ops)
11581 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11582 mutex_unlock(&bp->cnic_mutex);
11583
11584 return rc;
11585 }
11586
11587 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11588 {
11589 struct cnic_ops *c_ops;
11590 int rc = 0;
11591
11592 rcu_read_lock();
11593 c_ops = rcu_dereference(bp->cnic_ops);
11594 if (c_ops)
11595 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11596 rcu_read_unlock();
11597
11598 return rc;
11599 }
11600
11601 /*
11602 * for commands that have no data
11603 */
11604 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
11605 {
11606 struct cnic_ctl_info ctl = {0};
11607
11608 ctl.cmd = cmd;
11609
11610 return bnx2x_cnic_ctl_send(bp, &ctl);
11611 }
11612
11613 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
11614 {
11615 struct cnic_ctl_info ctl = {0};
11616
11617 /* first we tell CNIC and only then we count this as a completion */
11618 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11619 ctl.data.comp.cid = cid;
11620 ctl.data.comp.error = err;
11621
11622 bnx2x_cnic_ctl_send_bh(bp, &ctl);
11623 bnx2x_cnic_sp_post(bp, 0);
11624 }
11625
11626
11627 /* Called with netif_addr_lock_bh() taken.
11628 * Sets an rx_mode config for an iSCSI ETH client.
11629 * Doesn't block.
11630 * Completion should be checked outside.
11631 */
11632 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11633 {
11634 unsigned long accept_flags = 0, ramrod_flags = 0;
11635 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11636 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11637
11638 if (start) {
11639 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11640 * because it's the only way for UIO Queue to accept
11641 * multicasts (in non-promiscuous mode only one Queue per
11642 * function will receive multicast packets (leading in our
11643 * case).
11644 */
11645 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11646 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11647 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11648 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11649
11650 /* Clear STOP_PENDING bit if START is requested */
11651 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11652
11653 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11654 } else
11655 /* Clear START_PENDING bit if STOP is requested */
11656 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11657
11658 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11659 set_bit(sched_state, &bp->sp_state);
11660 else {
11661 __set_bit(RAMROD_RX, &ramrod_flags);
11662 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11663 ramrod_flags);
11664 }
11665 }
11666
11667
11668 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11669 {
11670 struct bnx2x *bp = netdev_priv(dev);
11671 int rc = 0;
11672
11673 switch (ctl->cmd) {
11674 case DRV_CTL_CTXTBL_WR_CMD: {
11675 u32 index = ctl->data.io.offset;
11676 dma_addr_t addr = ctl->data.io.dma_addr;
11677
11678 bnx2x_ilt_wr(bp, index, addr);
11679 break;
11680 }
11681
11682 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11683 int count = ctl->data.credit.credit_count;
11684
11685 bnx2x_cnic_sp_post(bp, count);
11686 break;
11687 }
11688
11689 /* rtnl_lock is held. */
11690 case DRV_CTL_START_L2_CMD: {
11691 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11692 unsigned long sp_bits = 0;
11693
11694 /* Configure the iSCSI classification object */
11695 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11696 cp->iscsi_l2_client_id,
11697 cp->iscsi_l2_cid, BP_FUNC(bp),
11698 bnx2x_sp(bp, mac_rdata),
11699 bnx2x_sp_mapping(bp, mac_rdata),
11700 BNX2X_FILTER_MAC_PENDING,
11701 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11702 &bp->macs_pool);
11703
11704 /* Set iSCSI MAC address */
11705 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11706 if (rc)
11707 break;
11708
11709 mmiowb();
11710 barrier();
11711
11712 /* Start accepting on iSCSI L2 ring */
11713
11714 netif_addr_lock_bh(dev);
11715 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11716 netif_addr_unlock_bh(dev);
11717
11718 /* bits to wait on */
11719 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11720 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11721
11722 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11723 BNX2X_ERR("rx_mode completion timed out!\n");
11724
11725 break;
11726 }
11727
11728 /* rtnl_lock is held. */
11729 case DRV_CTL_STOP_L2_CMD: {
11730 unsigned long sp_bits = 0;
11731
11732 /* Stop accepting on iSCSI L2 ring */
11733 netif_addr_lock_bh(dev);
11734 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11735 netif_addr_unlock_bh(dev);
11736
11737 /* bits to wait on */
11738 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11739 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11740
11741 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11742 BNX2X_ERR("rx_mode completion timed out!\n");
11743
11744 mmiowb();
11745 barrier();
11746
11747 /* Unset iSCSI L2 MAC */
11748 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11749 BNX2X_ISCSI_ETH_MAC, true);
11750 break;
11751 }
11752 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11753 int count = ctl->data.credit.credit_count;
11754
11755 smp_mb__before_atomic_inc();
11756 atomic_add(count, &bp->cq_spq_left);
11757 smp_mb__after_atomic_inc();
11758 break;
11759 }
11760 case DRV_CTL_ULP_REGISTER_CMD: {
11761 int ulp_type = ctl->data.ulp_type;
11762
11763 if (CHIP_IS_E3(bp)) {
11764 int idx = BP_FW_MB_IDX(bp);
11765 u32 cap;
11766
11767 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
11768 if (ulp_type == CNIC_ULP_ISCSI)
11769 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
11770 else if (ulp_type == CNIC_ULP_FCOE)
11771 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
11772 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
11773 }
11774 break;
11775 }
11776 case DRV_CTL_ULP_UNREGISTER_CMD: {
11777 int ulp_type = ctl->data.ulp_type;
11778
11779 if (CHIP_IS_E3(bp)) {
11780 int idx = BP_FW_MB_IDX(bp);
11781 u32 cap;
11782
11783 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
11784 if (ulp_type == CNIC_ULP_ISCSI)
11785 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
11786 else if (ulp_type == CNIC_ULP_FCOE)
11787 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
11788 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
11789 }
11790 break;
11791 }
11792
11793 default:
11794 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11795 rc = -EINVAL;
11796 }
11797
11798 return rc;
11799 }
11800
11801 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
11802 {
11803 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11804
11805 if (bp->flags & USING_MSIX_FLAG) {
11806 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11807 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11808 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11809 } else {
11810 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11811 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11812 }
11813 if (!CHIP_IS_E1x(bp))
11814 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11815 else
11816 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11817
11818 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11819 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
11820 cp->irq_arr[1].status_blk = bp->def_status_blk;
11821 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
11822 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
11823
11824 cp->num_irq = 2;
11825 }
11826
11827 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11828 void *data)
11829 {
11830 struct bnx2x *bp = netdev_priv(dev);
11831 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11832
11833 if (ops == NULL) {
11834 BNX2X_ERR("NULL ops received\n");
11835 return -EINVAL;
11836 }
11837
11838 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11839 if (!bp->cnic_kwq)
11840 return -ENOMEM;
11841
11842 bp->cnic_kwq_cons = bp->cnic_kwq;
11843 bp->cnic_kwq_prod = bp->cnic_kwq;
11844 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11845
11846 bp->cnic_spq_pending = 0;
11847 bp->cnic_kwq_pending = 0;
11848
11849 bp->cnic_data = data;
11850
11851 cp->num_irq = 0;
11852 cp->drv_state |= CNIC_DRV_STATE_REGD;
11853 cp->iro_arr = bp->iro_arr;
11854
11855 bnx2x_setup_cnic_irq_info(bp);
11856
11857 rcu_assign_pointer(bp->cnic_ops, ops);
11858
11859 return 0;
11860 }
11861
11862 static int bnx2x_unregister_cnic(struct net_device *dev)
11863 {
11864 struct bnx2x *bp = netdev_priv(dev);
11865 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11866
11867 mutex_lock(&bp->cnic_mutex);
11868 cp->drv_state = 0;
11869 RCU_INIT_POINTER(bp->cnic_ops, NULL);
11870 mutex_unlock(&bp->cnic_mutex);
11871 synchronize_rcu();
11872 kfree(bp->cnic_kwq);
11873 bp->cnic_kwq = NULL;
11874
11875 return 0;
11876 }
11877
11878 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11879 {
11880 struct bnx2x *bp = netdev_priv(dev);
11881 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11882
11883 /* If both iSCSI and FCoE are disabled - return NULL in
11884 * order to indicate CNIC that it should not try to work
11885 * with this device.
11886 */
11887 if (NO_ISCSI(bp) && NO_FCOE(bp))
11888 return NULL;
11889
11890 cp->drv_owner = THIS_MODULE;
11891 cp->chip_id = CHIP_ID(bp);
11892 cp->pdev = bp->pdev;
11893 cp->io_base = bp->regview;
11894 cp->io_base2 = bp->doorbells;
11895 cp->max_kwqe_pending = 8;
11896 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
11897 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11898 bnx2x_cid_ilt_lines(bp);
11899 cp->ctx_tbl_len = CNIC_ILT_LINES;
11900 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
11901 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11902 cp->drv_ctl = bnx2x_drv_ctl;
11903 cp->drv_register_cnic = bnx2x_register_cnic;
11904 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
11905 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
11906 cp->iscsi_l2_client_id =
11907 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11908 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11909
11910 if (NO_ISCSI_OOO(bp))
11911 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11912
11913 if (NO_ISCSI(bp))
11914 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11915
11916 if (NO_FCOE(bp))
11917 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11918
11919 BNX2X_DEV_INFO(
11920 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
11921 cp->ctx_blk_size,
11922 cp->ctx_tbl_offset,
11923 cp->ctx_tbl_len,
11924 cp->starting_cid);
11925 return cp;
11926 }
11927 EXPORT_SYMBOL(bnx2x_cnic_probe);
11928
11929 #endif /* BCM_CNIC */
11930
kernel source for telekom puls (alcatel/mediatek)