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Merge branch 'delete-8390-EISA' of git://git.kernel.org/pub/scm/linux/kernel/git...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_cmn.c
1 /* bnx2x_cmn.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2012 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/etherdevice.h>
21 #include <linux/if_vlan.h>
22 #include <linux/interrupt.h>
23 #include <linux/ip.h>
24 #include <net/ipv6.h>
25 #include <net/ip6_checksum.h>
26 #include <linux/prefetch.h>
27 #include "bnx2x_cmn.h"
28 #include "bnx2x_init.h"
29 #include "bnx2x_sp.h"
30
31 /**
32 * bnx2x_move_fp - move content of the fastpath structure.
33 *
34 * @bp: driver handle
35 * @from: source FP index
36 * @to: destination FP index
37 *
38 * Makes sure the contents of the bp->fp[to].napi is kept
39 * intact. This is done by first copying the napi struct from
40 * the target to the source, and then mem copying the entire
41 * source onto the target. Update txdata pointers and related
42 * content.
43 */
44 static inline void bnx2x_move_fp(struct bnx2x *bp, int from, int to)
45 {
46 struct bnx2x_fastpath *from_fp = &bp->fp[from];
47 struct bnx2x_fastpath *to_fp = &bp->fp[to];
48 struct bnx2x_sp_objs *from_sp_objs = &bp->sp_objs[from];
49 struct bnx2x_sp_objs *to_sp_objs = &bp->sp_objs[to];
50 struct bnx2x_fp_stats *from_fp_stats = &bp->fp_stats[from];
51 struct bnx2x_fp_stats *to_fp_stats = &bp->fp_stats[to];
52 int old_max_eth_txqs, new_max_eth_txqs;
53 int old_txdata_index = 0, new_txdata_index = 0;
54
55 /* Copy the NAPI object as it has been already initialized */
56 from_fp->napi = to_fp->napi;
57
58 /* Move bnx2x_fastpath contents */
59 memcpy(to_fp, from_fp, sizeof(*to_fp));
60 to_fp->index = to;
61
62 /* move sp_objs contents as well, as their indices match fp ones */
63 memcpy(to_sp_objs, from_sp_objs, sizeof(*to_sp_objs));
64
65 /* move fp_stats contents as well, as their indices match fp ones */
66 memcpy(to_fp_stats, from_fp_stats, sizeof(*to_fp_stats));
67
68 /* Update txdata pointers in fp and move txdata content accordingly:
69 * Each fp consumes 'max_cos' txdata structures, so the index should be
70 * decremented by max_cos x delta.
71 */
72
73 old_max_eth_txqs = BNX2X_NUM_ETH_QUEUES(bp) * (bp)->max_cos;
74 new_max_eth_txqs = (BNX2X_NUM_ETH_QUEUES(bp) - from + to) *
75 (bp)->max_cos;
76 if (from == FCOE_IDX(bp)) {
77 old_txdata_index = old_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
78 new_txdata_index = new_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
79 }
80
81 memcpy(&bp->bnx2x_txq[old_txdata_index],
82 &bp->bnx2x_txq[new_txdata_index],
83 sizeof(struct bnx2x_fp_txdata));
84 to_fp->txdata_ptr[0] = &bp->bnx2x_txq[new_txdata_index];
85 }
86
87 /**
88 * bnx2x_fill_fw_str - Fill buffer with FW version string.
89 *
90 * @bp: driver handle
91 * @buf: character buffer to fill with the fw name
92 * @buf_len: length of the above buffer
93 *
94 */
95 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len)
96 {
97 if (IS_PF(bp)) {
98 u8 phy_fw_ver[PHY_FW_VER_LEN];
99
100 phy_fw_ver[0] = '\0';
101 bnx2x_get_ext_phy_fw_version(&bp->link_params,
102 phy_fw_ver, PHY_FW_VER_LEN);
103 strlcpy(buf, bp->fw_ver, buf_len);
104 snprintf(buf + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
105 "bc %d.%d.%d%s%s",
106 (bp->common.bc_ver & 0xff0000) >> 16,
107 (bp->common.bc_ver & 0xff00) >> 8,
108 (bp->common.bc_ver & 0xff),
109 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
110 } else {
111 bnx2x_vf_fill_fw_str(bp, buf, buf_len);
112 }
113 }
114
115 int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
116
117 /* free skb in the packet ring at pos idx
118 * return idx of last bd freed
119 */
120 static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata,
121 u16 idx, unsigned int *pkts_compl,
122 unsigned int *bytes_compl)
123 {
124 struct sw_tx_bd *tx_buf = &txdata->tx_buf_ring[idx];
125 struct eth_tx_start_bd *tx_start_bd;
126 struct eth_tx_bd *tx_data_bd;
127 struct sk_buff *skb = tx_buf->skb;
128 u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
129 int nbd;
130
131 /* prefetch skb end pointer to speedup dev_kfree_skb() */
132 prefetch(&skb->end);
133
134 DP(NETIF_MSG_TX_DONE, "fp[%d]: pkt_idx %d buff @(%p)->skb %p\n",
135 txdata->txq_index, idx, tx_buf, skb);
136
137 /* unmap first bd */
138 tx_start_bd = &txdata->tx_desc_ring[bd_idx].start_bd;
139 dma_unmap_single(&bp->pdev->dev, BD_UNMAP_ADDR(tx_start_bd),
140 BD_UNMAP_LEN(tx_start_bd), DMA_TO_DEVICE);
141
142
143 nbd = le16_to_cpu(tx_start_bd->nbd) - 1;
144 #ifdef BNX2X_STOP_ON_ERROR
145 if ((nbd - 1) > (MAX_SKB_FRAGS + 2)) {
146 BNX2X_ERR("BAD nbd!\n");
147 bnx2x_panic();
148 }
149 #endif
150 new_cons = nbd + tx_buf->first_bd;
151
152 /* Get the next bd */
153 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
154
155 /* Skip a parse bd... */
156 --nbd;
157 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
158
159 /* ...and the TSO split header bd since they have no mapping */
160 if (tx_buf->flags & BNX2X_TSO_SPLIT_BD) {
161 --nbd;
162 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
163 }
164
165 /* now free frags */
166 while (nbd > 0) {
167
168 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
169 dma_unmap_page(&bp->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
170 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
171 if (--nbd)
172 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
173 }
174
175 /* release skb */
176 WARN_ON(!skb);
177 if (likely(skb)) {
178 (*pkts_compl)++;
179 (*bytes_compl) += skb->len;
180 }
181
182 dev_kfree_skb_any(skb);
183 tx_buf->first_bd = 0;
184 tx_buf->skb = NULL;
185
186 return new_cons;
187 }
188
189 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata)
190 {
191 struct netdev_queue *txq;
192 u16 hw_cons, sw_cons, bd_cons = txdata->tx_bd_cons;
193 unsigned int pkts_compl = 0, bytes_compl = 0;
194
195 #ifdef BNX2X_STOP_ON_ERROR
196 if (unlikely(bp->panic))
197 return -1;
198 #endif
199
200 txq = netdev_get_tx_queue(bp->dev, txdata->txq_index);
201 hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
202 sw_cons = txdata->tx_pkt_cons;
203
204 while (sw_cons != hw_cons) {
205 u16 pkt_cons;
206
207 pkt_cons = TX_BD(sw_cons);
208
209 DP(NETIF_MSG_TX_DONE,
210 "queue[%d]: hw_cons %u sw_cons %u pkt_cons %u\n",
211 txdata->txq_index, hw_cons, sw_cons, pkt_cons);
212
213 bd_cons = bnx2x_free_tx_pkt(bp, txdata, pkt_cons,
214 &pkts_compl, &bytes_compl);
215
216 sw_cons++;
217 }
218
219 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
220
221 txdata->tx_pkt_cons = sw_cons;
222 txdata->tx_bd_cons = bd_cons;
223
224 /* Need to make the tx_bd_cons update visible to start_xmit()
225 * before checking for netif_tx_queue_stopped(). Without the
226 * memory barrier, there is a small possibility that
227 * start_xmit() will miss it and cause the queue to be stopped
228 * forever.
229 * On the other hand we need an rmb() here to ensure the proper
230 * ordering of bit testing in the following
231 * netif_tx_queue_stopped(txq) call.
232 */
233 smp_mb();
234
235 if (unlikely(netif_tx_queue_stopped(txq))) {
236 /* Taking tx_lock() is needed to prevent reenabling the queue
237 * while it's empty. This could have happen if rx_action() gets
238 * suspended in bnx2x_tx_int() after the condition before
239 * netif_tx_wake_queue(), while tx_action (bnx2x_start_xmit()):
240 *
241 * stops the queue->sees fresh tx_bd_cons->releases the queue->
242 * sends some packets consuming the whole queue again->
243 * stops the queue
244 */
245
246 __netif_tx_lock(txq, smp_processor_id());
247
248 if ((netif_tx_queue_stopped(txq)) &&
249 (bp->state == BNX2X_STATE_OPEN) &&
250 (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT))
251 netif_tx_wake_queue(txq);
252
253 __netif_tx_unlock(txq);
254 }
255 return 0;
256 }
257
258 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
259 u16 idx)
260 {
261 u16 last_max = fp->last_max_sge;
262
263 if (SUB_S16(idx, last_max) > 0)
264 fp->last_max_sge = idx;
265 }
266
267 static inline void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
268 u16 sge_len,
269 struct eth_end_agg_rx_cqe *cqe)
270 {
271 struct bnx2x *bp = fp->bp;
272 u16 last_max, last_elem, first_elem;
273 u16 delta = 0;
274 u16 i;
275
276 if (!sge_len)
277 return;
278
279 /* First mark all used pages */
280 for (i = 0; i < sge_len; i++)
281 BIT_VEC64_CLEAR_BIT(fp->sge_mask,
282 RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[i])));
283
284 DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
285 sge_len - 1, le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
286
287 /* Here we assume that the last SGE index is the biggest */
288 prefetch((void *)(fp->sge_mask));
289 bnx2x_update_last_max_sge(fp,
290 le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
291
292 last_max = RX_SGE(fp->last_max_sge);
293 last_elem = last_max >> BIT_VEC64_ELEM_SHIFT;
294 first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT;
295
296 /* If ring is not full */
297 if (last_elem + 1 != first_elem)
298 last_elem++;
299
300 /* Now update the prod */
301 for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
302 if (likely(fp->sge_mask[i]))
303 break;
304
305 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK;
306 delta += BIT_VEC64_ELEM_SZ;
307 }
308
309 if (delta > 0) {
310 fp->rx_sge_prod += delta;
311 /* clear page-end entries */
312 bnx2x_clear_sge_mask_next_elems(fp);
313 }
314
315 DP(NETIF_MSG_RX_STATUS,
316 "fp->last_max_sge = %d fp->rx_sge_prod = %d\n",
317 fp->last_max_sge, fp->rx_sge_prod);
318 }
319
320 /* Set Toeplitz hash value in the skb using the value from the
321 * CQE (calculated by HW).
322 */
323 static u32 bnx2x_get_rxhash(const struct bnx2x *bp,
324 const struct eth_fast_path_rx_cqe *cqe,
325 bool *l4_rxhash)
326 {
327 /* Set Toeplitz hash from CQE */
328 if ((bp->dev->features & NETIF_F_RXHASH) &&
329 (cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG)) {
330 enum eth_rss_hash_type htype;
331
332 htype = cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE;
333 *l4_rxhash = (htype == TCP_IPV4_HASH_TYPE) ||
334 (htype == TCP_IPV6_HASH_TYPE);
335 return le32_to_cpu(cqe->rss_hash_result);
336 }
337 *l4_rxhash = false;
338 return 0;
339 }
340
341 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
342 u16 cons, u16 prod,
343 struct eth_fast_path_rx_cqe *cqe)
344 {
345 struct bnx2x *bp = fp->bp;
346 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
347 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
348 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
349 dma_addr_t mapping;
350 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[queue];
351 struct sw_rx_bd *first_buf = &tpa_info->first_buf;
352
353 /* print error if current state != stop */
354 if (tpa_info->tpa_state != BNX2X_TPA_STOP)
355 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
356
357 /* Try to map an empty data buffer from the aggregation info */
358 mapping = dma_map_single(&bp->pdev->dev,
359 first_buf->data + NET_SKB_PAD,
360 fp->rx_buf_size, DMA_FROM_DEVICE);
361 /*
362 * ...if it fails - move the skb from the consumer to the producer
363 * and set the current aggregation state as ERROR to drop it
364 * when TPA_STOP arrives.
365 */
366
367 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
368 /* Move the BD from the consumer to the producer */
369 bnx2x_reuse_rx_data(fp, cons, prod);
370 tpa_info->tpa_state = BNX2X_TPA_ERROR;
371 return;
372 }
373
374 /* move empty data from pool to prod */
375 prod_rx_buf->data = first_buf->data;
376 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
377 /* point prod_bd to new data */
378 prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
379 prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
380
381 /* move partial skb from cons to pool (don't unmap yet) */
382 *first_buf = *cons_rx_buf;
383
384 /* mark bin state as START */
385 tpa_info->parsing_flags =
386 le16_to_cpu(cqe->pars_flags.flags);
387 tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
388 tpa_info->tpa_state = BNX2X_TPA_START;
389 tpa_info->len_on_bd = le16_to_cpu(cqe->len_on_bd);
390 tpa_info->placement_offset = cqe->placement_offset;
391 tpa_info->rxhash = bnx2x_get_rxhash(bp, cqe, &tpa_info->l4_rxhash);
392 if (fp->mode == TPA_MODE_GRO) {
393 u16 gro_size = le16_to_cpu(cqe->pkt_len_or_gro_seg_len);
394 tpa_info->full_page =
395 SGE_PAGE_SIZE * PAGES_PER_SGE / gro_size * gro_size;
396 tpa_info->gro_size = gro_size;
397 }
398
399 #ifdef BNX2X_STOP_ON_ERROR
400 fp->tpa_queue_used |= (1 << queue);
401 #ifdef _ASM_GENERIC_INT_L64_H
402 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
403 #else
404 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
405 #endif
406 fp->tpa_queue_used);
407 #endif
408 }
409
410 /* Timestamp option length allowed for TPA aggregation:
411 *
412 * nop nop kind length echo val
413 */
414 #define TPA_TSTAMP_OPT_LEN 12
415 /**
416 * bnx2x_set_lro_mss - calculate the approximate value of the MSS
417 *
418 * @bp: driver handle
419 * @parsing_flags: parsing flags from the START CQE
420 * @len_on_bd: total length of the first packet for the
421 * aggregation.
422 *
423 * Approximate value of the MSS for this aggregation calculated using
424 * the first packet of it.
425 */
426 static u16 bnx2x_set_lro_mss(struct bnx2x *bp, u16 parsing_flags,
427 u16 len_on_bd)
428 {
429 /*
430 * TPA arrgregation won't have either IP options or TCP options
431 * other than timestamp or IPv6 extension headers.
432 */
433 u16 hdrs_len = ETH_HLEN + sizeof(struct tcphdr);
434
435 if (GET_FLAG(parsing_flags, PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) ==
436 PRS_FLAG_OVERETH_IPV6)
437 hdrs_len += sizeof(struct ipv6hdr);
438 else /* IPv4 */
439 hdrs_len += sizeof(struct iphdr);
440
441
442 /* Check if there was a TCP timestamp, if there is it's will
443 * always be 12 bytes length: nop nop kind length echo val.
444 *
445 * Otherwise FW would close the aggregation.
446 */
447 if (parsing_flags & PARSING_FLAGS_TIME_STAMP_EXIST_FLAG)
448 hdrs_len += TPA_TSTAMP_OPT_LEN;
449
450 return len_on_bd - hdrs_len;
451 }
452
453 static int bnx2x_alloc_rx_sge(struct bnx2x *bp,
454 struct bnx2x_fastpath *fp, u16 index)
455 {
456 struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
457 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
458 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
459 dma_addr_t mapping;
460
461 if (unlikely(page == NULL)) {
462 BNX2X_ERR("Can't alloc sge\n");
463 return -ENOMEM;
464 }
465
466 mapping = dma_map_page(&bp->pdev->dev, page, 0,
467 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
468 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
469 __free_pages(page, PAGES_PER_SGE_SHIFT);
470 BNX2X_ERR("Can't map sge\n");
471 return -ENOMEM;
472 }
473
474 sw_buf->page = page;
475 dma_unmap_addr_set(sw_buf, mapping, mapping);
476
477 sge->addr_hi = cpu_to_le32(U64_HI(mapping));
478 sge->addr_lo = cpu_to_le32(U64_LO(mapping));
479
480 return 0;
481 }
482
483 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
484 struct bnx2x_agg_info *tpa_info,
485 u16 pages,
486 struct sk_buff *skb,
487 struct eth_end_agg_rx_cqe *cqe,
488 u16 cqe_idx)
489 {
490 struct sw_rx_page *rx_pg, old_rx_pg;
491 u32 i, frag_len, frag_size;
492 int err, j, frag_id = 0;
493 u16 len_on_bd = tpa_info->len_on_bd;
494 u16 full_page = 0, gro_size = 0;
495
496 frag_size = le16_to_cpu(cqe->pkt_len) - len_on_bd;
497
498 if (fp->mode == TPA_MODE_GRO) {
499 gro_size = tpa_info->gro_size;
500 full_page = tpa_info->full_page;
501 }
502
503 /* This is needed in order to enable forwarding support */
504 if (frag_size) {
505 skb_shinfo(skb)->gso_size = bnx2x_set_lro_mss(bp,
506 tpa_info->parsing_flags, len_on_bd);
507
508 /* set for GRO */
509 if (fp->mode == TPA_MODE_GRO)
510 skb_shinfo(skb)->gso_type =
511 (GET_FLAG(tpa_info->parsing_flags,
512 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) ==
513 PRS_FLAG_OVERETH_IPV6) ?
514 SKB_GSO_TCPV6 : SKB_GSO_TCPV4;
515 }
516
517
518 #ifdef BNX2X_STOP_ON_ERROR
519 if (pages > min_t(u32, 8, MAX_SKB_FRAGS)*SGE_PAGE_SIZE*PAGES_PER_SGE) {
520 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
521 pages, cqe_idx);
522 BNX2X_ERR("cqe->pkt_len = %d\n", cqe->pkt_len);
523 bnx2x_panic();
524 return -EINVAL;
525 }
526 #endif
527
528 /* Run through the SGL and compose the fragmented skb */
529 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
530 u16 sge_idx = RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[j]));
531
532 /* FW gives the indices of the SGE as if the ring is an array
533 (meaning that "next" element will consume 2 indices) */
534 if (fp->mode == TPA_MODE_GRO)
535 frag_len = min_t(u32, frag_size, (u32)full_page);
536 else /* LRO */
537 frag_len = min_t(u32, frag_size,
538 (u32)(SGE_PAGE_SIZE * PAGES_PER_SGE));
539
540 rx_pg = &fp->rx_page_ring[sge_idx];
541 old_rx_pg = *rx_pg;
542
543 /* If we fail to allocate a substitute page, we simply stop
544 where we are and drop the whole packet */
545 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
546 if (unlikely(err)) {
547 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
548 return err;
549 }
550
551 /* Unmap the page as we r going to pass it to the stack */
552 dma_unmap_page(&bp->pdev->dev,
553 dma_unmap_addr(&old_rx_pg, mapping),
554 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
555 /* Add one frag and update the appropriate fields in the skb */
556 if (fp->mode == TPA_MODE_LRO)
557 skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
558 else { /* GRO */
559 int rem;
560 int offset = 0;
561 for (rem = frag_len; rem > 0; rem -= gro_size) {
562 int len = rem > gro_size ? gro_size : rem;
563 skb_fill_page_desc(skb, frag_id++,
564 old_rx_pg.page, offset, len);
565 if (offset)
566 get_page(old_rx_pg.page);
567 offset += len;
568 }
569 }
570
571 skb->data_len += frag_len;
572 skb->truesize += SGE_PAGE_SIZE * PAGES_PER_SGE;
573 skb->len += frag_len;
574
575 frag_size -= frag_len;
576 }
577
578 return 0;
579 }
580
581 static void bnx2x_frag_free(const struct bnx2x_fastpath *fp, void *data)
582 {
583 if (fp->rx_frag_size)
584 put_page(virt_to_head_page(data));
585 else
586 kfree(data);
587 }
588
589 static void *bnx2x_frag_alloc(const struct bnx2x_fastpath *fp)
590 {
591 if (fp->rx_frag_size)
592 return netdev_alloc_frag(fp->rx_frag_size);
593
594 return kmalloc(fp->rx_buf_size + NET_SKB_PAD, GFP_ATOMIC);
595 }
596
597
598 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
599 struct bnx2x_agg_info *tpa_info,
600 u16 pages,
601 struct eth_end_agg_rx_cqe *cqe,
602 u16 cqe_idx)
603 {
604 struct sw_rx_bd *rx_buf = &tpa_info->first_buf;
605 u8 pad = tpa_info->placement_offset;
606 u16 len = tpa_info->len_on_bd;
607 struct sk_buff *skb = NULL;
608 u8 *new_data, *data = rx_buf->data;
609 u8 old_tpa_state = tpa_info->tpa_state;
610
611 tpa_info->tpa_state = BNX2X_TPA_STOP;
612
613 /* If we there was an error during the handling of the TPA_START -
614 * drop this aggregation.
615 */
616 if (old_tpa_state == BNX2X_TPA_ERROR)
617 goto drop;
618
619 /* Try to allocate the new data */
620 new_data = bnx2x_frag_alloc(fp);
621 /* Unmap skb in the pool anyway, as we are going to change
622 pool entry status to BNX2X_TPA_STOP even if new skb allocation
623 fails. */
624 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(rx_buf, mapping),
625 fp->rx_buf_size, DMA_FROM_DEVICE);
626 if (likely(new_data))
627 skb = build_skb(data, fp->rx_frag_size);
628
629 if (likely(skb)) {
630 #ifdef BNX2X_STOP_ON_ERROR
631 if (pad + len > fp->rx_buf_size) {
632 BNX2X_ERR("skb_put is about to fail... pad %d len %d rx_buf_size %d\n",
633 pad, len, fp->rx_buf_size);
634 bnx2x_panic();
635 return;
636 }
637 #endif
638
639 skb_reserve(skb, pad + NET_SKB_PAD);
640 skb_put(skb, len);
641 skb->rxhash = tpa_info->rxhash;
642 skb->l4_rxhash = tpa_info->l4_rxhash;
643
644 skb->protocol = eth_type_trans(skb, bp->dev);
645 skb->ip_summed = CHECKSUM_UNNECESSARY;
646
647 if (!bnx2x_fill_frag_skb(bp, fp, tpa_info, pages,
648 skb, cqe, cqe_idx)) {
649 if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN)
650 __vlan_hwaccel_put_tag(skb, tpa_info->vlan_tag);
651 napi_gro_receive(&fp->napi, skb);
652 } else {
653 DP(NETIF_MSG_RX_STATUS,
654 "Failed to allocate new pages - dropping packet!\n");
655 dev_kfree_skb_any(skb);
656 }
657
658
659 /* put new data in bin */
660 rx_buf->data = new_data;
661
662 return;
663 }
664 bnx2x_frag_free(fp, new_data);
665 drop:
666 /* drop the packet and keep the buffer in the bin */
667 DP(NETIF_MSG_RX_STATUS,
668 "Failed to allocate or map a new skb - dropping packet!\n");
669 bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed++;
670 }
671
672 static int bnx2x_alloc_rx_data(struct bnx2x *bp,
673 struct bnx2x_fastpath *fp, u16 index)
674 {
675 u8 *data;
676 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
677 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
678 dma_addr_t mapping;
679
680 data = bnx2x_frag_alloc(fp);
681 if (unlikely(data == NULL))
682 return -ENOMEM;
683
684 mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD,
685 fp->rx_buf_size,
686 DMA_FROM_DEVICE);
687 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
688 bnx2x_frag_free(fp, data);
689 BNX2X_ERR("Can't map rx data\n");
690 return -ENOMEM;
691 }
692
693 rx_buf->data = data;
694 dma_unmap_addr_set(rx_buf, mapping, mapping);
695
696 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
697 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
698
699 return 0;
700 }
701
702 static
703 void bnx2x_csum_validate(struct sk_buff *skb, union eth_rx_cqe *cqe,
704 struct bnx2x_fastpath *fp,
705 struct bnx2x_eth_q_stats *qstats)
706 {
707 /* Do nothing if no L4 csum validation was done.
708 * We do not check whether IP csum was validated. For IPv4 we assume
709 * that if the card got as far as validating the L4 csum, it also
710 * validated the IP csum. IPv6 has no IP csum.
711 */
712 if (cqe->fast_path_cqe.status_flags &
713 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)
714 return;
715
716 /* If L4 validation was done, check if an error was found. */
717
718 if (cqe->fast_path_cqe.type_error_flags &
719 (ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG |
720 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
721 qstats->hw_csum_err++;
722 else
723 skb->ip_summed = CHECKSUM_UNNECESSARY;
724 }
725
726 int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
727 {
728 struct bnx2x *bp = fp->bp;
729 u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
730 u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
731 int rx_pkt = 0;
732
733 #ifdef BNX2X_STOP_ON_ERROR
734 if (unlikely(bp->panic))
735 return 0;
736 #endif
737
738 /* CQ "next element" is of the size of the regular element,
739 that's why it's ok here */
740 hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
741 if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
742 hw_comp_cons++;
743
744 bd_cons = fp->rx_bd_cons;
745 bd_prod = fp->rx_bd_prod;
746 bd_prod_fw = bd_prod;
747 sw_comp_cons = fp->rx_comp_cons;
748 sw_comp_prod = fp->rx_comp_prod;
749
750 /* Memory barrier necessary as speculative reads of the rx
751 * buffer can be ahead of the index in the status block
752 */
753 rmb();
754
755 DP(NETIF_MSG_RX_STATUS,
756 "queue[%d]: hw_comp_cons %u sw_comp_cons %u\n",
757 fp->index, hw_comp_cons, sw_comp_cons);
758
759 while (sw_comp_cons != hw_comp_cons) {
760 struct sw_rx_bd *rx_buf = NULL;
761 struct sk_buff *skb;
762 union eth_rx_cqe *cqe;
763 struct eth_fast_path_rx_cqe *cqe_fp;
764 u8 cqe_fp_flags;
765 enum eth_rx_cqe_type cqe_fp_type;
766 u16 len, pad, queue;
767 u8 *data;
768 bool l4_rxhash;
769
770 #ifdef BNX2X_STOP_ON_ERROR
771 if (unlikely(bp->panic))
772 return 0;
773 #endif
774
775 comp_ring_cons = RCQ_BD(sw_comp_cons);
776 bd_prod = RX_BD(bd_prod);
777 bd_cons = RX_BD(bd_cons);
778
779 cqe = &fp->rx_comp_ring[comp_ring_cons];
780 cqe_fp = &cqe->fast_path_cqe;
781 cqe_fp_flags = cqe_fp->type_error_flags;
782 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
783
784 DP(NETIF_MSG_RX_STATUS,
785 "CQE type %x err %x status %x queue %x vlan %x len %u\n",
786 CQE_TYPE(cqe_fp_flags),
787 cqe_fp_flags, cqe_fp->status_flags,
788 le32_to_cpu(cqe_fp->rss_hash_result),
789 le16_to_cpu(cqe_fp->vlan_tag),
790 le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len));
791
792 /* is this a slowpath msg? */
793 if (unlikely(CQE_TYPE_SLOW(cqe_fp_type))) {
794 bnx2x_sp_event(fp, cqe);
795 goto next_cqe;
796 }
797
798 rx_buf = &fp->rx_buf_ring[bd_cons];
799 data = rx_buf->data;
800
801 if (!CQE_TYPE_FAST(cqe_fp_type)) {
802 struct bnx2x_agg_info *tpa_info;
803 u16 frag_size, pages;
804 #ifdef BNX2X_STOP_ON_ERROR
805 /* sanity check */
806 if (fp->disable_tpa &&
807 (CQE_TYPE_START(cqe_fp_type) ||
808 CQE_TYPE_STOP(cqe_fp_type)))
809 BNX2X_ERR("START/STOP packet while disable_tpa type %x\n",
810 CQE_TYPE(cqe_fp_type));
811 #endif
812
813 if (CQE_TYPE_START(cqe_fp_type)) {
814 u16 queue = cqe_fp->queue_index;
815 DP(NETIF_MSG_RX_STATUS,
816 "calling tpa_start on queue %d\n",
817 queue);
818
819 bnx2x_tpa_start(fp, queue,
820 bd_cons, bd_prod,
821 cqe_fp);
822
823 goto next_rx;
824
825 }
826 queue = cqe->end_agg_cqe.queue_index;
827 tpa_info = &fp->tpa_info[queue];
828 DP(NETIF_MSG_RX_STATUS,
829 "calling tpa_stop on queue %d\n",
830 queue);
831
832 frag_size = le16_to_cpu(cqe->end_agg_cqe.pkt_len) -
833 tpa_info->len_on_bd;
834
835 if (fp->mode == TPA_MODE_GRO)
836 pages = (frag_size + tpa_info->full_page - 1) /
837 tpa_info->full_page;
838 else
839 pages = SGE_PAGE_ALIGN(frag_size) >>
840 SGE_PAGE_SHIFT;
841
842 bnx2x_tpa_stop(bp, fp, tpa_info, pages,
843 &cqe->end_agg_cqe, comp_ring_cons);
844 #ifdef BNX2X_STOP_ON_ERROR
845 if (bp->panic)
846 return 0;
847 #endif
848
849 bnx2x_update_sge_prod(fp, pages, &cqe->end_agg_cqe);
850 goto next_cqe;
851 }
852 /* non TPA */
853 len = le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len);
854 pad = cqe_fp->placement_offset;
855 dma_sync_single_for_cpu(&bp->pdev->dev,
856 dma_unmap_addr(rx_buf, mapping),
857 pad + RX_COPY_THRESH,
858 DMA_FROM_DEVICE);
859 pad += NET_SKB_PAD;
860 prefetch(data + pad); /* speedup eth_type_trans() */
861 /* is this an error packet? */
862 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
863 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
864 "ERROR flags %x rx packet %u\n",
865 cqe_fp_flags, sw_comp_cons);
866 bnx2x_fp_qstats(bp, fp)->rx_err_discard_pkt++;
867 goto reuse_rx;
868 }
869
870 /* Since we don't have a jumbo ring
871 * copy small packets if mtu > 1500
872 */
873 if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
874 (len <= RX_COPY_THRESH)) {
875 skb = netdev_alloc_skb_ip_align(bp->dev, len);
876 if (skb == NULL) {
877 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
878 "ERROR packet dropped because of alloc failure\n");
879 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
880 goto reuse_rx;
881 }
882 memcpy(skb->data, data + pad, len);
883 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
884 } else {
885 if (likely(bnx2x_alloc_rx_data(bp, fp, bd_prod) == 0)) {
886 dma_unmap_single(&bp->pdev->dev,
887 dma_unmap_addr(rx_buf, mapping),
888 fp->rx_buf_size,
889 DMA_FROM_DEVICE);
890 skb = build_skb(data, fp->rx_frag_size);
891 if (unlikely(!skb)) {
892 bnx2x_frag_free(fp, data);
893 bnx2x_fp_qstats(bp, fp)->
894 rx_skb_alloc_failed++;
895 goto next_rx;
896 }
897 skb_reserve(skb, pad);
898 } else {
899 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
900 "ERROR packet dropped because of alloc failure\n");
901 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
902 reuse_rx:
903 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
904 goto next_rx;
905 }
906 }
907
908 skb_put(skb, len);
909 skb->protocol = eth_type_trans(skb, bp->dev);
910
911 /* Set Toeplitz hash for a none-LRO skb */
912 skb->rxhash = bnx2x_get_rxhash(bp, cqe_fp, &l4_rxhash);
913 skb->l4_rxhash = l4_rxhash;
914
915 skb_checksum_none_assert(skb);
916
917 if (bp->dev->features & NETIF_F_RXCSUM)
918 bnx2x_csum_validate(skb, cqe, fp,
919 bnx2x_fp_qstats(bp, fp));
920
921 skb_record_rx_queue(skb, fp->rx_queue);
922
923 if (le16_to_cpu(cqe_fp->pars_flags.flags) &
924 PARSING_FLAGS_VLAN)
925 __vlan_hwaccel_put_tag(skb,
926 le16_to_cpu(cqe_fp->vlan_tag));
927 napi_gro_receive(&fp->napi, skb);
928
929
930 next_rx:
931 rx_buf->data = NULL;
932
933 bd_cons = NEXT_RX_IDX(bd_cons);
934 bd_prod = NEXT_RX_IDX(bd_prod);
935 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
936 rx_pkt++;
937 next_cqe:
938 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
939 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
940
941 if (rx_pkt == budget)
942 break;
943 } /* while */
944
945 fp->rx_bd_cons = bd_cons;
946 fp->rx_bd_prod = bd_prod_fw;
947 fp->rx_comp_cons = sw_comp_cons;
948 fp->rx_comp_prod = sw_comp_prod;
949
950 /* Update producers */
951 bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
952 fp->rx_sge_prod);
953
954 fp->rx_pkt += rx_pkt;
955 fp->rx_calls++;
956
957 return rx_pkt;
958 }
959
960 static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
961 {
962 struct bnx2x_fastpath *fp = fp_cookie;
963 struct bnx2x *bp = fp->bp;
964 u8 cos;
965
966 DP(NETIF_MSG_INTR,
967 "got an MSI-X interrupt on IDX:SB [fp %d fw_sd %d igusb %d]\n",
968 fp->index, fp->fw_sb_id, fp->igu_sb_id);
969 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
970
971 #ifdef BNX2X_STOP_ON_ERROR
972 if (unlikely(bp->panic))
973 return IRQ_HANDLED;
974 #endif
975
976 /* Handle Rx and Tx according to MSI-X vector */
977 prefetch(fp->rx_cons_sb);
978
979 for_each_cos_in_tx_queue(fp, cos)
980 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
981
982 prefetch(&fp->sb_running_index[SM_RX_ID]);
983 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
984
985 return IRQ_HANDLED;
986 }
987
988 /* HW Lock for shared dual port PHYs */
989 void bnx2x_acquire_phy_lock(struct bnx2x *bp)
990 {
991 mutex_lock(&bp->port.phy_mutex);
992
993 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
994 }
995
996 void bnx2x_release_phy_lock(struct bnx2x *bp)
997 {
998 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
999
1000 mutex_unlock(&bp->port.phy_mutex);
1001 }
1002
1003 /* calculates MF speed according to current linespeed and MF configuration */
1004 u16 bnx2x_get_mf_speed(struct bnx2x *bp)
1005 {
1006 u16 line_speed = bp->link_vars.line_speed;
1007 if (IS_MF(bp)) {
1008 u16 maxCfg = bnx2x_extract_max_cfg(bp,
1009 bp->mf_config[BP_VN(bp)]);
1010
1011 /* Calculate the current MAX line speed limit for the MF
1012 * devices
1013 */
1014 if (IS_MF_SI(bp))
1015 line_speed = (line_speed * maxCfg) / 100;
1016 else { /* SD mode */
1017 u16 vn_max_rate = maxCfg * 100;
1018
1019 if (vn_max_rate < line_speed)
1020 line_speed = vn_max_rate;
1021 }
1022 }
1023
1024 return line_speed;
1025 }
1026
1027 /**
1028 * bnx2x_fill_report_data - fill link report data to report
1029 *
1030 * @bp: driver handle
1031 * @data: link state to update
1032 *
1033 * It uses a none-atomic bit operations because is called under the mutex.
1034 */
1035 static void bnx2x_fill_report_data(struct bnx2x *bp,
1036 struct bnx2x_link_report_data *data)
1037 {
1038 u16 line_speed = bnx2x_get_mf_speed(bp);
1039
1040 memset(data, 0, sizeof(*data));
1041
1042 /* Fill the report data: efective line speed */
1043 data->line_speed = line_speed;
1044
1045 /* Link is down */
1046 if (!bp->link_vars.link_up || (bp->flags & MF_FUNC_DIS))
1047 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1048 &data->link_report_flags);
1049
1050 /* Full DUPLEX */
1051 if (bp->link_vars.duplex == DUPLEX_FULL)
1052 __set_bit(BNX2X_LINK_REPORT_FD, &data->link_report_flags);
1053
1054 /* Rx Flow Control is ON */
1055 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX)
1056 __set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
1057
1058 /* Tx Flow Control is ON */
1059 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
1060 __set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
1061 }
1062
1063 /**
1064 * bnx2x_link_report - report link status to OS.
1065 *
1066 * @bp: driver handle
1067 *
1068 * Calls the __bnx2x_link_report() under the same locking scheme
1069 * as a link/PHY state managing code to ensure a consistent link
1070 * reporting.
1071 */
1072
1073 void bnx2x_link_report(struct bnx2x *bp)
1074 {
1075 bnx2x_acquire_phy_lock(bp);
1076 __bnx2x_link_report(bp);
1077 bnx2x_release_phy_lock(bp);
1078 }
1079
1080 /**
1081 * __bnx2x_link_report - report link status to OS.
1082 *
1083 * @bp: driver handle
1084 *
1085 * None atomic inmlementation.
1086 * Should be called under the phy_lock.
1087 */
1088 void __bnx2x_link_report(struct bnx2x *bp)
1089 {
1090 struct bnx2x_link_report_data cur_data;
1091
1092 /* reread mf_cfg */
1093 if (IS_PF(bp) && !CHIP_IS_E1(bp))
1094 bnx2x_read_mf_cfg(bp);
1095
1096 /* Read the current link report info */
1097 bnx2x_fill_report_data(bp, &cur_data);
1098
1099 /* Don't report link down or exactly the same link status twice */
1100 if (!memcmp(&cur_data, &bp->last_reported_link, sizeof(cur_data)) ||
1101 (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1102 &bp->last_reported_link.link_report_flags) &&
1103 test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1104 &cur_data.link_report_flags)))
1105 return;
1106
1107 bp->link_cnt++;
1108
1109 /* We are going to report a new link parameters now -
1110 * remember the current data for the next time.
1111 */
1112 memcpy(&bp->last_reported_link, &cur_data, sizeof(cur_data));
1113
1114 if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1115 &cur_data.link_report_flags)) {
1116 netif_carrier_off(bp->dev);
1117 netdev_err(bp->dev, "NIC Link is Down\n");
1118 return;
1119 } else {
1120 const char *duplex;
1121 const char *flow;
1122
1123 netif_carrier_on(bp->dev);
1124
1125 if (test_and_clear_bit(BNX2X_LINK_REPORT_FD,
1126 &cur_data.link_report_flags))
1127 duplex = "full";
1128 else
1129 duplex = "half";
1130
1131 /* Handle the FC at the end so that only these flags would be
1132 * possibly set. This way we may easily check if there is no FC
1133 * enabled.
1134 */
1135 if (cur_data.link_report_flags) {
1136 if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1137 &cur_data.link_report_flags)) {
1138 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1139 &cur_data.link_report_flags))
1140 flow = "ON - receive & transmit";
1141 else
1142 flow = "ON - receive";
1143 } else {
1144 flow = "ON - transmit";
1145 }
1146 } else {
1147 flow = "none";
1148 }
1149 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
1150 cur_data.line_speed, duplex, flow);
1151 }
1152 }
1153
1154 static void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
1155 {
1156 int i;
1157
1158 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1159 struct eth_rx_sge *sge;
1160
1161 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
1162 sge->addr_hi =
1163 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
1164 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1165
1166 sge->addr_lo =
1167 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
1168 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1169 }
1170 }
1171
1172 static void bnx2x_free_tpa_pool(struct bnx2x *bp,
1173 struct bnx2x_fastpath *fp, int last)
1174 {
1175 int i;
1176
1177 for (i = 0; i < last; i++) {
1178 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i];
1179 struct sw_rx_bd *first_buf = &tpa_info->first_buf;
1180 u8 *data = first_buf->data;
1181
1182 if (data == NULL) {
1183 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
1184 continue;
1185 }
1186 if (tpa_info->tpa_state == BNX2X_TPA_START)
1187 dma_unmap_single(&bp->pdev->dev,
1188 dma_unmap_addr(first_buf, mapping),
1189 fp->rx_buf_size, DMA_FROM_DEVICE);
1190 bnx2x_frag_free(fp, data);
1191 first_buf->data = NULL;
1192 }
1193 }
1194
1195 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp)
1196 {
1197 int j;
1198
1199 for_each_rx_queue_cnic(bp, j) {
1200 struct bnx2x_fastpath *fp = &bp->fp[j];
1201
1202 fp->rx_bd_cons = 0;
1203
1204 /* Activate BD ring */
1205 /* Warning!
1206 * this will generate an interrupt (to the TSTORM)
1207 * must only be done after chip is initialized
1208 */
1209 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1210 fp->rx_sge_prod);
1211 }
1212 }
1213
1214 void bnx2x_init_rx_rings(struct bnx2x *bp)
1215 {
1216 int func = BP_FUNC(bp);
1217 u16 ring_prod;
1218 int i, j;
1219
1220 /* Allocate TPA resources */
1221 for_each_eth_queue(bp, j) {
1222 struct bnx2x_fastpath *fp = &bp->fp[j];
1223
1224 DP(NETIF_MSG_IFUP,
1225 "mtu %d rx_buf_size %d\n", bp->dev->mtu, fp->rx_buf_size);
1226
1227 if (!fp->disable_tpa) {
1228 /* Fill the per-aggregtion pool */
1229 for (i = 0; i < MAX_AGG_QS(bp); i++) {
1230 struct bnx2x_agg_info *tpa_info =
1231 &fp->tpa_info[i];
1232 struct sw_rx_bd *first_buf =
1233 &tpa_info->first_buf;
1234
1235 first_buf->data = bnx2x_frag_alloc(fp);
1236 if (!first_buf->data) {
1237 BNX2X_ERR("Failed to allocate TPA skb pool for queue[%d] - disabling TPA on this queue!\n",
1238 j);
1239 bnx2x_free_tpa_pool(bp, fp, i);
1240 fp->disable_tpa = 1;
1241 break;
1242 }
1243 dma_unmap_addr_set(first_buf, mapping, 0);
1244 tpa_info->tpa_state = BNX2X_TPA_STOP;
1245 }
1246
1247 /* "next page" elements initialization */
1248 bnx2x_set_next_page_sgl(fp);
1249
1250 /* set SGEs bit mask */
1251 bnx2x_init_sge_ring_bit_mask(fp);
1252
1253 /* Allocate SGEs and initialize the ring elements */
1254 for (i = 0, ring_prod = 0;
1255 i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
1256
1257 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
1258 BNX2X_ERR("was only able to allocate %d rx sges\n",
1259 i);
1260 BNX2X_ERR("disabling TPA for queue[%d]\n",
1261 j);
1262 /* Cleanup already allocated elements */
1263 bnx2x_free_rx_sge_range(bp, fp,
1264 ring_prod);
1265 bnx2x_free_tpa_pool(bp, fp,
1266 MAX_AGG_QS(bp));
1267 fp->disable_tpa = 1;
1268 ring_prod = 0;
1269 break;
1270 }
1271 ring_prod = NEXT_SGE_IDX(ring_prod);
1272 }
1273
1274 fp->rx_sge_prod = ring_prod;
1275 }
1276 }
1277
1278 for_each_eth_queue(bp, j) {
1279 struct bnx2x_fastpath *fp = &bp->fp[j];
1280
1281 fp->rx_bd_cons = 0;
1282
1283 /* Activate BD ring */
1284 /* Warning!
1285 * this will generate an interrupt (to the TSTORM)
1286 * must only be done after chip is initialized
1287 */
1288 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1289 fp->rx_sge_prod);
1290
1291 if (j != 0)
1292 continue;
1293
1294 if (CHIP_IS_E1(bp)) {
1295 REG_WR(bp, BAR_USTRORM_INTMEM +
1296 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
1297 U64_LO(fp->rx_comp_mapping));
1298 REG_WR(bp, BAR_USTRORM_INTMEM +
1299 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
1300 U64_HI(fp->rx_comp_mapping));
1301 }
1302 }
1303 }
1304
1305 static void bnx2x_free_tx_skbs_queue(struct bnx2x_fastpath *fp)
1306 {
1307 u8 cos;
1308 struct bnx2x *bp = fp->bp;
1309
1310 for_each_cos_in_tx_queue(fp, cos) {
1311 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1312 unsigned pkts_compl = 0, bytes_compl = 0;
1313
1314 u16 sw_prod = txdata->tx_pkt_prod;
1315 u16 sw_cons = txdata->tx_pkt_cons;
1316
1317 while (sw_cons != sw_prod) {
1318 bnx2x_free_tx_pkt(bp, txdata, TX_BD(sw_cons),
1319 &pkts_compl, &bytes_compl);
1320 sw_cons++;
1321 }
1322
1323 netdev_tx_reset_queue(
1324 netdev_get_tx_queue(bp->dev,
1325 txdata->txq_index));
1326 }
1327 }
1328
1329 static void bnx2x_free_tx_skbs_cnic(struct bnx2x *bp)
1330 {
1331 int i;
1332
1333 for_each_tx_queue_cnic(bp, i) {
1334 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1335 }
1336 }
1337
1338 static void bnx2x_free_tx_skbs(struct bnx2x *bp)
1339 {
1340 int i;
1341
1342 for_each_eth_queue(bp, i) {
1343 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1344 }
1345 }
1346
1347 static void bnx2x_free_rx_bds(struct bnx2x_fastpath *fp)
1348 {
1349 struct bnx2x *bp = fp->bp;
1350 int i;
1351
1352 /* ring wasn't allocated */
1353 if (fp->rx_buf_ring == NULL)
1354 return;
1355
1356 for (i = 0; i < NUM_RX_BD; i++) {
1357 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
1358 u8 *data = rx_buf->data;
1359
1360 if (data == NULL)
1361 continue;
1362 dma_unmap_single(&bp->pdev->dev,
1363 dma_unmap_addr(rx_buf, mapping),
1364 fp->rx_buf_size, DMA_FROM_DEVICE);
1365
1366 rx_buf->data = NULL;
1367 bnx2x_frag_free(fp, data);
1368 }
1369 }
1370
1371 static void bnx2x_free_rx_skbs_cnic(struct bnx2x *bp)
1372 {
1373 int j;
1374
1375 for_each_rx_queue_cnic(bp, j) {
1376 bnx2x_free_rx_bds(&bp->fp[j]);
1377 }
1378 }
1379
1380 static void bnx2x_free_rx_skbs(struct bnx2x *bp)
1381 {
1382 int j;
1383
1384 for_each_eth_queue(bp, j) {
1385 struct bnx2x_fastpath *fp = &bp->fp[j];
1386
1387 bnx2x_free_rx_bds(fp);
1388
1389 if (!fp->disable_tpa)
1390 bnx2x_free_tpa_pool(bp, fp, MAX_AGG_QS(bp));
1391 }
1392 }
1393
1394 void bnx2x_free_skbs_cnic(struct bnx2x *bp)
1395 {
1396 bnx2x_free_tx_skbs_cnic(bp);
1397 bnx2x_free_rx_skbs_cnic(bp);
1398 }
1399
1400 void bnx2x_free_skbs(struct bnx2x *bp)
1401 {
1402 bnx2x_free_tx_skbs(bp);
1403 bnx2x_free_rx_skbs(bp);
1404 }
1405
1406 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value)
1407 {
1408 /* load old values */
1409 u32 mf_cfg = bp->mf_config[BP_VN(bp)];
1410
1411 if (value != bnx2x_extract_max_cfg(bp, mf_cfg)) {
1412 /* leave all but MAX value */
1413 mf_cfg &= ~FUNC_MF_CFG_MAX_BW_MASK;
1414
1415 /* set new MAX value */
1416 mf_cfg |= (value << FUNC_MF_CFG_MAX_BW_SHIFT)
1417 & FUNC_MF_CFG_MAX_BW_MASK;
1418
1419 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, mf_cfg);
1420 }
1421 }
1422
1423 /**
1424 * bnx2x_free_msix_irqs - free previously requested MSI-X IRQ vectors
1425 *
1426 * @bp: driver handle
1427 * @nvecs: number of vectors to be released
1428 */
1429 static void bnx2x_free_msix_irqs(struct bnx2x *bp, int nvecs)
1430 {
1431 int i, offset = 0;
1432
1433 if (nvecs == offset)
1434 return;
1435
1436 /* VFs don't have a default SB */
1437 if (IS_PF(bp)) {
1438 free_irq(bp->msix_table[offset].vector, bp->dev);
1439 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
1440 bp->msix_table[offset].vector);
1441 offset++;
1442 }
1443
1444 if (CNIC_SUPPORT(bp)) {
1445 if (nvecs == offset)
1446 return;
1447 offset++;
1448 }
1449
1450 for_each_eth_queue(bp, i) {
1451 if (nvecs == offset)
1452 return;
1453 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq\n",
1454 i, bp->msix_table[offset].vector);
1455
1456 free_irq(bp->msix_table[offset++].vector, &bp->fp[i]);
1457 }
1458 }
1459
1460 void bnx2x_free_irq(struct bnx2x *bp)
1461 {
1462 if (bp->flags & USING_MSIX_FLAG &&
1463 !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1464 int nvecs = BNX2X_NUM_ETH_QUEUES(bp) + CNIC_SUPPORT(bp);
1465
1466 /* vfs don't have a default status block */
1467 if (IS_PF(bp))
1468 nvecs++;
1469
1470 bnx2x_free_msix_irqs(bp, nvecs);
1471 } else {
1472 free_irq(bp->dev->irq, bp->dev);
1473 }
1474 }
1475
1476 int bnx2x_enable_msix(struct bnx2x *bp)
1477 {
1478 int msix_vec = 0, i, rc;
1479
1480 /* VFs don't have a default status block */
1481 if (IS_PF(bp)) {
1482 bp->msix_table[msix_vec].entry = msix_vec;
1483 BNX2X_DEV_INFO("msix_table[0].entry = %d (slowpath)\n",
1484 bp->msix_table[0].entry);
1485 msix_vec++;
1486 }
1487
1488 /* Cnic requires an msix vector for itself */
1489 if (CNIC_SUPPORT(bp)) {
1490 bp->msix_table[msix_vec].entry = msix_vec;
1491 BNX2X_DEV_INFO("msix_table[%d].entry = %d (CNIC)\n",
1492 msix_vec, bp->msix_table[msix_vec].entry);
1493 msix_vec++;
1494 }
1495
1496 /* We need separate vectors for ETH queues only (not FCoE) */
1497 for_each_eth_queue(bp, i) {
1498 bp->msix_table[msix_vec].entry = msix_vec;
1499 BNX2X_DEV_INFO("msix_table[%d].entry = %d (fastpath #%u)\n",
1500 msix_vec, msix_vec, i);
1501 msix_vec++;
1502 }
1503
1504 DP(BNX2X_MSG_SP, "about to request enable msix with %d vectors\n",
1505 msix_vec);
1506
1507 rc = pci_enable_msix(bp->pdev, &bp->msix_table[0], msix_vec);
1508
1509 /*
1510 * reconfigure number of tx/rx queues according to available
1511 * MSI-X vectors
1512 */
1513 if (rc >= BNX2X_MIN_MSIX_VEC_CNT(bp)) {
1514 /* how less vectors we will have? */
1515 int diff = msix_vec - rc;
1516
1517 BNX2X_DEV_INFO("Trying to use less MSI-X vectors: %d\n", rc);
1518
1519 rc = pci_enable_msix(bp->pdev, &bp->msix_table[0], rc);
1520
1521 if (rc) {
1522 BNX2X_DEV_INFO("MSI-X is not attainable rc %d\n", rc);
1523 goto no_msix;
1524 }
1525 /*
1526 * decrease number of queues by number of unallocated entries
1527 */
1528 bp->num_ethernet_queues -= diff;
1529 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1530
1531 BNX2X_DEV_INFO("New queue configuration set: %d\n",
1532 bp->num_queues);
1533 } else if (rc > 0) {
1534 /* Get by with single vector */
1535 rc = pci_enable_msix(bp->pdev, &bp->msix_table[0], 1);
1536 if (rc) {
1537 BNX2X_DEV_INFO("Single MSI-X is not attainable rc %d\n",
1538 rc);
1539 goto no_msix;
1540 }
1541
1542 BNX2X_DEV_INFO("Using single MSI-X vector\n");
1543 bp->flags |= USING_SINGLE_MSIX_FLAG;
1544
1545 BNX2X_DEV_INFO("set number of queues to 1\n");
1546 bp->num_ethernet_queues = 1;
1547 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1548 } else if (rc < 0) {
1549 BNX2X_DEV_INFO("MSI-X is not attainable rc %d\n", rc);
1550 goto no_msix;
1551 }
1552
1553 bp->flags |= USING_MSIX_FLAG;
1554
1555 return 0;
1556
1557 no_msix:
1558 /* fall to INTx if not enough memory */
1559 if (rc == -ENOMEM)
1560 bp->flags |= DISABLE_MSI_FLAG;
1561
1562 return rc;
1563 }
1564
1565 static int bnx2x_req_msix_irqs(struct bnx2x *bp)
1566 {
1567 int i, rc, offset = 0;
1568
1569 /* no default status block for vf */
1570 if (IS_PF(bp)) {
1571 rc = request_irq(bp->msix_table[offset++].vector,
1572 bnx2x_msix_sp_int, 0,
1573 bp->dev->name, bp->dev);
1574 if (rc) {
1575 BNX2X_ERR("request sp irq failed\n");
1576 return -EBUSY;
1577 }
1578 }
1579
1580 if (CNIC_SUPPORT(bp))
1581 offset++;
1582
1583 for_each_eth_queue(bp, i) {
1584 struct bnx2x_fastpath *fp = &bp->fp[i];
1585 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
1586 bp->dev->name, i);
1587
1588 rc = request_irq(bp->msix_table[offset].vector,
1589 bnx2x_msix_fp_int, 0, fp->name, fp);
1590 if (rc) {
1591 BNX2X_ERR("request fp #%d irq (%d) failed rc %d\n", i,
1592 bp->msix_table[offset].vector, rc);
1593 bnx2x_free_msix_irqs(bp, offset);
1594 return -EBUSY;
1595 }
1596
1597 offset++;
1598 }
1599
1600 i = BNX2X_NUM_ETH_QUEUES(bp);
1601 if (IS_PF(bp)) {
1602 offset = 1 + CNIC_SUPPORT(bp);
1603 netdev_info(bp->dev,
1604 "using MSI-X IRQs: sp %d fp[%d] %d ... fp[%d] %d\n",
1605 bp->msix_table[0].vector,
1606 0, bp->msix_table[offset].vector,
1607 i - 1, bp->msix_table[offset + i - 1].vector);
1608 } else {
1609 offset = CNIC_SUPPORT(bp);
1610 netdev_info(bp->dev,
1611 "using MSI-X IRQs: fp[%d] %d ... fp[%d] %d\n",
1612 0, bp->msix_table[offset].vector,
1613 i - 1, bp->msix_table[offset + i - 1].vector);
1614 }
1615 return 0;
1616 }
1617
1618 int bnx2x_enable_msi(struct bnx2x *bp)
1619 {
1620 int rc;
1621
1622 rc = pci_enable_msi(bp->pdev);
1623 if (rc) {
1624 BNX2X_DEV_INFO("MSI is not attainable\n");
1625 return -1;
1626 }
1627 bp->flags |= USING_MSI_FLAG;
1628
1629 return 0;
1630 }
1631
1632 static int bnx2x_req_irq(struct bnx2x *bp)
1633 {
1634 unsigned long flags;
1635 unsigned int irq;
1636
1637 if (bp->flags & (USING_MSI_FLAG | USING_MSIX_FLAG))
1638 flags = 0;
1639 else
1640 flags = IRQF_SHARED;
1641
1642 if (bp->flags & USING_MSIX_FLAG)
1643 irq = bp->msix_table[0].vector;
1644 else
1645 irq = bp->pdev->irq;
1646
1647 return request_irq(irq, bnx2x_interrupt, flags, bp->dev->name, bp->dev);
1648 }
1649
1650 static int bnx2x_setup_irqs(struct bnx2x *bp)
1651 {
1652 int rc = 0;
1653 if (bp->flags & USING_MSIX_FLAG &&
1654 !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1655 rc = bnx2x_req_msix_irqs(bp);
1656 if (rc)
1657 return rc;
1658 } else {
1659 bnx2x_ack_int(bp);
1660 rc = bnx2x_req_irq(bp);
1661 if (rc) {
1662 BNX2X_ERR("IRQ request failed rc %d, aborting\n", rc);
1663 return rc;
1664 }
1665 if (bp->flags & USING_MSI_FLAG) {
1666 bp->dev->irq = bp->pdev->irq;
1667 netdev_info(bp->dev, "using MSI IRQ %d\n",
1668 bp->dev->irq);
1669 }
1670 if (bp->flags & USING_MSIX_FLAG) {
1671 bp->dev->irq = bp->msix_table[0].vector;
1672 netdev_info(bp->dev, "using MSIX IRQ %d\n",
1673 bp->dev->irq);
1674 }
1675 }
1676
1677 return 0;
1678 }
1679
1680 static void bnx2x_napi_enable_cnic(struct bnx2x *bp)
1681 {
1682 int i;
1683
1684 for_each_rx_queue_cnic(bp, i)
1685 napi_enable(&bnx2x_fp(bp, i, napi));
1686 }
1687
1688 static void bnx2x_napi_enable(struct bnx2x *bp)
1689 {
1690 int i;
1691
1692 for_each_eth_queue(bp, i)
1693 napi_enable(&bnx2x_fp(bp, i, napi));
1694 }
1695
1696 static void bnx2x_napi_disable_cnic(struct bnx2x *bp)
1697 {
1698 int i;
1699
1700 for_each_rx_queue_cnic(bp, i)
1701 napi_disable(&bnx2x_fp(bp, i, napi));
1702 }
1703
1704 static void bnx2x_napi_disable(struct bnx2x *bp)
1705 {
1706 int i;
1707
1708 for_each_eth_queue(bp, i)
1709 napi_disable(&bnx2x_fp(bp, i, napi));
1710 }
1711
1712 void bnx2x_netif_start(struct bnx2x *bp)
1713 {
1714 if (netif_running(bp->dev)) {
1715 bnx2x_napi_enable(bp);
1716 if (CNIC_LOADED(bp))
1717 bnx2x_napi_enable_cnic(bp);
1718 bnx2x_int_enable(bp);
1719 if (bp->state == BNX2X_STATE_OPEN)
1720 netif_tx_wake_all_queues(bp->dev);
1721 }
1722 }
1723
1724 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
1725 {
1726 bnx2x_int_disable_sync(bp, disable_hw);
1727 bnx2x_napi_disable(bp);
1728 if (CNIC_LOADED(bp))
1729 bnx2x_napi_disable_cnic(bp);
1730 }
1731
1732 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb)
1733 {
1734 struct bnx2x *bp = netdev_priv(dev);
1735
1736 if (CNIC_LOADED(bp) && !NO_FCOE(bp)) {
1737 struct ethhdr *hdr = (struct ethhdr *)skb->data;
1738 u16 ether_type = ntohs(hdr->h_proto);
1739
1740 /* Skip VLAN tag if present */
1741 if (ether_type == ETH_P_8021Q) {
1742 struct vlan_ethhdr *vhdr =
1743 (struct vlan_ethhdr *)skb->data;
1744
1745 ether_type = ntohs(vhdr->h_vlan_encapsulated_proto);
1746 }
1747
1748 /* If ethertype is FCoE or FIP - use FCoE ring */
1749 if ((ether_type == ETH_P_FCOE) || (ether_type == ETH_P_FIP))
1750 return bnx2x_fcoe_tx(bp, txq_index);
1751 }
1752
1753 /* select a non-FCoE queue */
1754 return __skb_tx_hash(dev, skb, BNX2X_NUM_ETH_QUEUES(bp));
1755 }
1756
1757
1758 void bnx2x_set_num_queues(struct bnx2x *bp)
1759 {
1760 /* RSS queues */
1761 bp->num_ethernet_queues = bnx2x_calc_num_queues(bp);
1762
1763 /* override in STORAGE SD modes */
1764 if (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))
1765 bp->num_ethernet_queues = 1;
1766
1767 /* Add special queues */
1768 bp->num_cnic_queues = CNIC_SUPPORT(bp); /* For FCOE */
1769 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1770
1771 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
1772 }
1773
1774 /**
1775 * bnx2x_set_real_num_queues - configure netdev->real_num_[tx,rx]_queues
1776 *
1777 * @bp: Driver handle
1778 *
1779 * We currently support for at most 16 Tx queues for each CoS thus we will
1780 * allocate a multiple of 16 for ETH L2 rings according to the value of the
1781 * bp->max_cos.
1782 *
1783 * If there is an FCoE L2 queue the appropriate Tx queue will have the next
1784 * index after all ETH L2 indices.
1785 *
1786 * If the actual number of Tx queues (for each CoS) is less than 16 then there
1787 * will be the holes at the end of each group of 16 ETh L2 indices (0..15,
1788 * 16..31,...) with indicies that are not coupled with any real Tx queue.
1789 *
1790 * The proper configuration of skb->queue_mapping is handled by
1791 * bnx2x_select_queue() and __skb_tx_hash().
1792 *
1793 * bnx2x_setup_tc() takes care of the proper TC mappings so that __skb_tx_hash()
1794 * will return a proper Tx index if TC is enabled (netdev->num_tc > 0).
1795 */
1796 static int bnx2x_set_real_num_queues(struct bnx2x *bp, int include_cnic)
1797 {
1798 int rc, tx, rx;
1799
1800 tx = BNX2X_NUM_ETH_QUEUES(bp) * bp->max_cos;
1801 rx = BNX2X_NUM_ETH_QUEUES(bp);
1802
1803 /* account for fcoe queue */
1804 if (include_cnic && !NO_FCOE(bp)) {
1805 rx++;
1806 tx++;
1807 }
1808
1809 rc = netif_set_real_num_tx_queues(bp->dev, tx);
1810 if (rc) {
1811 BNX2X_ERR("Failed to set real number of Tx queues: %d\n", rc);
1812 return rc;
1813 }
1814 rc = netif_set_real_num_rx_queues(bp->dev, rx);
1815 if (rc) {
1816 BNX2X_ERR("Failed to set real number of Rx queues: %d\n", rc);
1817 return rc;
1818 }
1819
1820 DP(NETIF_MSG_IFUP, "Setting real num queues to (tx, rx) (%d, %d)\n",
1821 tx, rx);
1822
1823 return rc;
1824 }
1825
1826 static void bnx2x_set_rx_buf_size(struct bnx2x *bp)
1827 {
1828 int i;
1829
1830 for_each_queue(bp, i) {
1831 struct bnx2x_fastpath *fp = &bp->fp[i];
1832 u32 mtu;
1833
1834 /* Always use a mini-jumbo MTU for the FCoE L2 ring */
1835 if (IS_FCOE_IDX(i))
1836 /*
1837 * Although there are no IP frames expected to arrive to
1838 * this ring we still want to add an
1839 * IP_HEADER_ALIGNMENT_PADDING to prevent a buffer
1840 * overrun attack.
1841 */
1842 mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
1843 else
1844 mtu = bp->dev->mtu;
1845 fp->rx_buf_size = BNX2X_FW_RX_ALIGN_START +
1846 IP_HEADER_ALIGNMENT_PADDING +
1847 ETH_OVREHEAD +
1848 mtu +
1849 BNX2X_FW_RX_ALIGN_END;
1850 /* Note : rx_buf_size doesnt take into account NET_SKB_PAD */
1851 if (fp->rx_buf_size + NET_SKB_PAD <= PAGE_SIZE)
1852 fp->rx_frag_size = fp->rx_buf_size + NET_SKB_PAD;
1853 else
1854 fp->rx_frag_size = 0;
1855 }
1856 }
1857
1858 static int bnx2x_init_rss_pf(struct bnx2x *bp)
1859 {
1860 int i;
1861 u8 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
1862
1863 /* Prepare the initial contents fo the indirection table if RSS is
1864 * enabled
1865 */
1866 for (i = 0; i < sizeof(bp->rss_conf_obj.ind_table); i++)
1867 bp->rss_conf_obj.ind_table[i] =
1868 bp->fp->cl_id +
1869 ethtool_rxfh_indir_default(i, num_eth_queues);
1870
1871 /*
1872 * For 57710 and 57711 SEARCHER configuration (rss_keys) is
1873 * per-port, so if explicit configuration is needed , do it only
1874 * for a PMF.
1875 *
1876 * For 57712 and newer on the other hand it's a per-function
1877 * configuration.
1878 */
1879 return bnx2x_config_rss_eth(bp, bp->port.pmf || !CHIP_IS_E1x(bp));
1880 }
1881
1882 int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
1883 bool config_hash)
1884 {
1885 struct bnx2x_config_rss_params params = {NULL};
1886
1887 /* Although RSS is meaningless when there is a single HW queue we
1888 * still need it enabled in order to have HW Rx hash generated.
1889 *
1890 * if (!is_eth_multi(bp))
1891 * bp->multi_mode = ETH_RSS_MODE_DISABLED;
1892 */
1893
1894 params.rss_obj = rss_obj;
1895
1896 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
1897
1898 __set_bit(BNX2X_RSS_MODE_REGULAR, &params.rss_flags);
1899
1900 /* RSS configuration */
1901 __set_bit(BNX2X_RSS_IPV4, &params.rss_flags);
1902 __set_bit(BNX2X_RSS_IPV4_TCP, &params.rss_flags);
1903 __set_bit(BNX2X_RSS_IPV6, &params.rss_flags);
1904 __set_bit(BNX2X_RSS_IPV6_TCP, &params.rss_flags);
1905 if (rss_obj->udp_rss_v4)
1906 __set_bit(BNX2X_RSS_IPV4_UDP, &params.rss_flags);
1907 if (rss_obj->udp_rss_v6)
1908 __set_bit(BNX2X_RSS_IPV6_UDP, &params.rss_flags);
1909
1910 /* Hash bits */
1911 params.rss_result_mask = MULTI_MASK;
1912
1913 memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table));
1914
1915 if (config_hash) {
1916 /* RSS keys */
1917 prandom_bytes(params.rss_key, sizeof(params.rss_key));
1918 __set_bit(BNX2X_RSS_SET_SRCH, &params.rss_flags);
1919 }
1920
1921 return bnx2x_config_rss(bp, &params);
1922 }
1923
1924 static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
1925 {
1926 struct bnx2x_func_state_params func_params = {NULL};
1927
1928 /* Prepare parameters for function state transitions */
1929 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1930
1931 func_params.f_obj = &bp->func_obj;
1932 func_params.cmd = BNX2X_F_CMD_HW_INIT;
1933
1934 func_params.params.hw_init.load_phase = load_code;
1935
1936 return bnx2x_func_state_change(bp, &func_params);
1937 }
1938
1939 /*
1940 * Cleans the object that have internal lists without sending
1941 * ramrods. Should be run when interrutps are disabled.
1942 */
1943 static void bnx2x_squeeze_objects(struct bnx2x *bp)
1944 {
1945 int rc;
1946 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1947 struct bnx2x_mcast_ramrod_params rparam = {NULL};
1948 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
1949
1950 /***************** Cleanup MACs' object first *************************/
1951
1952 /* Wait for completion of requested */
1953 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1954 /* Perform a dry cleanup */
1955 __set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1956
1957 /* Clean ETH primary MAC */
1958 __set_bit(BNX2X_ETH_MAC, &vlan_mac_flags);
1959 rc = mac_obj->delete_all(bp, &bp->sp_objs->mac_obj, &vlan_mac_flags,
1960 &ramrod_flags);
1961 if (rc != 0)
1962 BNX2X_ERR("Failed to clean ETH MACs: %d\n", rc);
1963
1964 /* Cleanup UC list */
1965 vlan_mac_flags = 0;
1966 __set_bit(BNX2X_UC_LIST_MAC, &vlan_mac_flags);
1967 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags,
1968 &ramrod_flags);
1969 if (rc != 0)
1970 BNX2X_ERR("Failed to clean UC list MACs: %d\n", rc);
1971
1972 /***************** Now clean mcast object *****************************/
1973 rparam.mcast_obj = &bp->mcast_obj;
1974 __set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1975
1976 /* Add a DEL command... */
1977 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
1978 if (rc < 0)
1979 BNX2X_ERR("Failed to add a new DEL command to a multi-cast object: %d\n",
1980 rc);
1981
1982 /* ...and wait until all pending commands are cleared */
1983 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
1984 while (rc != 0) {
1985 if (rc < 0) {
1986 BNX2X_ERR("Failed to clean multi-cast object: %d\n",
1987 rc);
1988 return;
1989 }
1990
1991 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
1992 }
1993 }
1994
1995 #ifndef BNX2X_STOP_ON_ERROR
1996 #define LOAD_ERROR_EXIT(bp, label) \
1997 do { \
1998 (bp)->state = BNX2X_STATE_ERROR; \
1999 goto label; \
2000 } while (0)
2001
2002 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2003 do { \
2004 bp->cnic_loaded = false; \
2005 goto label; \
2006 } while (0)
2007 #else /*BNX2X_STOP_ON_ERROR*/
2008 #define LOAD_ERROR_EXIT(bp, label) \
2009 do { \
2010 (bp)->state = BNX2X_STATE_ERROR; \
2011 (bp)->panic = 1; \
2012 return -EBUSY; \
2013 } while (0)
2014 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2015 do { \
2016 bp->cnic_loaded = false; \
2017 (bp)->panic = 1; \
2018 return -EBUSY; \
2019 } while (0)
2020 #endif /*BNX2X_STOP_ON_ERROR*/
2021
2022 static void bnx2x_free_fw_stats_mem(struct bnx2x *bp)
2023 {
2024 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
2025 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2026 return;
2027 }
2028
2029 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
2030 {
2031 int num_groups, vf_headroom = 0;
2032 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
2033
2034 /* number of queues for statistics is number of eth queues + FCoE */
2035 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
2036
2037 /* Total number of FW statistics requests =
2038 * 1 for port stats + 1 for PF stats + potential 2 for FCoE (fcoe proper
2039 * and fcoe l2 queue) stats + num of queues (which includes another 1
2040 * for fcoe l2 queue if applicable)
2041 */
2042 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
2043
2044 /* vf stats appear in the request list, but their data is allocated by
2045 * the VFs themselves. We don't include them in the bp->fw_stats_num as
2046 * it is used to determine where to place the vf stats queries in the
2047 * request struct
2048 */
2049 if (IS_SRIOV(bp))
2050 vf_headroom = bnx2x_vf_headroom(bp);
2051
2052 /* Request is built from stats_query_header and an array of
2053 * stats_query_cmd_group each of which contains
2054 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
2055 * configured in the stats_query_header.
2056 */
2057 num_groups =
2058 (((bp->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT) +
2059 (((bp->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT) ?
2060 1 : 0));
2061
2062 DP(BNX2X_MSG_SP, "stats fw_stats_num %d, vf headroom %d, num_groups %d\n",
2063 bp->fw_stats_num, vf_headroom, num_groups);
2064 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
2065 num_groups * sizeof(struct stats_query_cmd_group);
2066
2067 /* Data for statistics requests + stats_counter
2068 * stats_counter holds per-STORM counters that are incremented
2069 * when STORM has finished with the current request.
2070 * memory for FCoE offloaded statistics are counted anyway,
2071 * even if they will not be sent.
2072 * VF stats are not accounted for here as the data of VF stats is stored
2073 * in memory allocated by the VF, not here.
2074 */
2075 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
2076 sizeof(struct per_pf_stats) +
2077 sizeof(struct fcoe_statistics_params) +
2078 sizeof(struct per_queue_stats) * num_queue_stats +
2079 sizeof(struct stats_counter);
2080
2081 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
2082 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2083
2084 /* Set shortcuts */
2085 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
2086 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
2087 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
2088 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
2089 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
2090 bp->fw_stats_req_sz;
2091
2092 DP(BNX2X_MSG_SP, "statistics request base address set to %x %x",
2093 U64_HI(bp->fw_stats_req_mapping),
2094 U64_LO(bp->fw_stats_req_mapping));
2095 DP(BNX2X_MSG_SP, "statistics data base address set to %x %x",
2096 U64_HI(bp->fw_stats_data_mapping),
2097 U64_LO(bp->fw_stats_data_mapping));
2098 return 0;
2099
2100 alloc_mem_err:
2101 bnx2x_free_fw_stats_mem(bp);
2102 BNX2X_ERR("Can't allocate FW stats memory\n");
2103 return -ENOMEM;
2104 }
2105
2106 /* send load request to mcp and analyze response */
2107 static int bnx2x_nic_load_request(struct bnx2x *bp, u32 *load_code)
2108 {
2109 /* init fw_seq */
2110 bp->fw_seq =
2111 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
2112 DRV_MSG_SEQ_NUMBER_MASK);
2113 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
2114
2115 /* Get current FW pulse sequence */
2116 bp->fw_drv_pulse_wr_seq =
2117 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb) &
2118 DRV_PULSE_SEQ_MASK);
2119 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
2120
2121 /* load request */
2122 (*load_code) = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
2123 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2124
2125 /* if mcp fails to respond we must abort */
2126 if (!(*load_code)) {
2127 BNX2X_ERR("MCP response failure, aborting\n");
2128 return -EBUSY;
2129 }
2130
2131 /* If mcp refused (e.g. other port is in diagnostic mode) we
2132 * must abort
2133 */
2134 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2135 BNX2X_ERR("MCP refused load request, aborting\n");
2136 return -EBUSY;
2137 }
2138 return 0;
2139 }
2140
2141 /* check whether another PF has already loaded FW to chip. In
2142 * virtualized environments a pf from another VM may have already
2143 * initialized the device including loading FW
2144 */
2145 int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code)
2146 {
2147 /* is another pf loaded on this engine? */
2148 if (load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP &&
2149 load_code != FW_MSG_CODE_DRV_LOAD_COMMON) {
2150 /* build my FW version dword */
2151 u32 my_fw = (BCM_5710_FW_MAJOR_VERSION) +
2152 (BCM_5710_FW_MINOR_VERSION << 8) +
2153 (BCM_5710_FW_REVISION_VERSION << 16) +
2154 (BCM_5710_FW_ENGINEERING_VERSION << 24);
2155
2156 /* read loaded FW from chip */
2157 u32 loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
2158
2159 DP(BNX2X_MSG_SP, "loaded fw %x, my fw %x\n",
2160 loaded_fw, my_fw);
2161
2162 /* abort nic load if version mismatch */
2163 if (my_fw != loaded_fw) {
2164 BNX2X_ERR("bnx2x with FW %x was already loaded which mismatches my %x FW. aborting\n",
2165 loaded_fw, my_fw);
2166 return -EBUSY;
2167 }
2168 }
2169 return 0;
2170 }
2171
2172 /* returns the "mcp load_code" according to global load_count array */
2173 static int bnx2x_nic_load_no_mcp(struct bnx2x *bp, int port)
2174 {
2175 int path = BP_PATH(bp);
2176
2177 DP(NETIF_MSG_IFUP, "NO MCP - load counts[%d] %d, %d, %d\n",
2178 path, load_count[path][0], load_count[path][1],
2179 load_count[path][2]);
2180 load_count[path][0]++;
2181 load_count[path][1 + port]++;
2182 DP(NETIF_MSG_IFUP, "NO MCP - new load counts[%d] %d, %d, %d\n",
2183 path, load_count[path][0], load_count[path][1],
2184 load_count[path][2]);
2185 if (load_count[path][0] == 1)
2186 return FW_MSG_CODE_DRV_LOAD_COMMON;
2187 else if (load_count[path][1 + port] == 1)
2188 return FW_MSG_CODE_DRV_LOAD_PORT;
2189 else
2190 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
2191 }
2192
2193 /* mark PMF if applicable */
2194 static void bnx2x_nic_load_pmf(struct bnx2x *bp, u32 load_code)
2195 {
2196 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2197 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2198 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2199 bp->port.pmf = 1;
2200 /* We need the barrier to ensure the ordering between the
2201 * writing to bp->port.pmf here and reading it from the
2202 * bnx2x_periodic_task().
2203 */
2204 smp_mb();
2205 } else {
2206 bp->port.pmf = 0;
2207 }
2208
2209 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2210 }
2211
2212 static void bnx2x_nic_load_afex_dcc(struct bnx2x *bp, int load_code)
2213 {
2214 if (((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2215 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP)) &&
2216 (bp->common.shmem2_base)) {
2217 if (SHMEM2_HAS(bp, dcc_support))
2218 SHMEM2_WR(bp, dcc_support,
2219 (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
2220 SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));
2221 if (SHMEM2_HAS(bp, afex_driver_support))
2222 SHMEM2_WR(bp, afex_driver_support,
2223 SHMEM_AFEX_SUPPORTED_VERSION_ONE);
2224 }
2225
2226 /* Set AFEX default VLAN tag to an invalid value */
2227 bp->afex_def_vlan_tag = -1;
2228 }
2229
2230 /**
2231 * bnx2x_bz_fp - zero content of the fastpath structure.
2232 *
2233 * @bp: driver handle
2234 * @index: fastpath index to be zeroed
2235 *
2236 * Makes sure the contents of the bp->fp[index].napi is kept
2237 * intact.
2238 */
2239 static void bnx2x_bz_fp(struct bnx2x *bp, int index)
2240 {
2241 struct bnx2x_fastpath *fp = &bp->fp[index];
2242 struct bnx2x_fp_stats *fp_stats = &bp->fp_stats[index];
2243
2244 int cos;
2245 struct napi_struct orig_napi = fp->napi;
2246 struct bnx2x_agg_info *orig_tpa_info = fp->tpa_info;
2247 /* bzero bnx2x_fastpath contents */
2248 if (bp->stats_init) {
2249 memset(fp->tpa_info, 0, sizeof(*fp->tpa_info));
2250 memset(fp, 0, sizeof(*fp));
2251 } else {
2252 /* Keep Queue statistics */
2253 struct bnx2x_eth_q_stats *tmp_eth_q_stats;
2254 struct bnx2x_eth_q_stats_old *tmp_eth_q_stats_old;
2255
2256 tmp_eth_q_stats = kzalloc(sizeof(struct bnx2x_eth_q_stats),
2257 GFP_KERNEL);
2258 if (tmp_eth_q_stats)
2259 memcpy(tmp_eth_q_stats, &fp_stats->eth_q_stats,
2260 sizeof(struct bnx2x_eth_q_stats));
2261
2262 tmp_eth_q_stats_old =
2263 kzalloc(sizeof(struct bnx2x_eth_q_stats_old),
2264 GFP_KERNEL);
2265 if (tmp_eth_q_stats_old)
2266 memcpy(tmp_eth_q_stats_old, &fp_stats->eth_q_stats_old,
2267 sizeof(struct bnx2x_eth_q_stats_old));
2268
2269 memset(fp->tpa_info, 0, sizeof(*fp->tpa_info));
2270 memset(fp, 0, sizeof(*fp));
2271
2272 if (tmp_eth_q_stats) {
2273 memcpy(&fp_stats->eth_q_stats, tmp_eth_q_stats,
2274 sizeof(struct bnx2x_eth_q_stats));
2275 kfree(tmp_eth_q_stats);
2276 }
2277
2278 if (tmp_eth_q_stats_old) {
2279 memcpy(&fp_stats->eth_q_stats_old, tmp_eth_q_stats_old,
2280 sizeof(struct bnx2x_eth_q_stats_old));
2281 kfree(tmp_eth_q_stats_old);
2282 }
2283
2284 }
2285
2286 /* Restore the NAPI object as it has been already initialized */
2287 fp->napi = orig_napi;
2288 fp->tpa_info = orig_tpa_info;
2289 fp->bp = bp;
2290 fp->index = index;
2291 if (IS_ETH_FP(fp))
2292 fp->max_cos = bp->max_cos;
2293 else
2294 /* Special queues support only one CoS */
2295 fp->max_cos = 1;
2296
2297 /* Init txdata pointers */
2298 if (IS_FCOE_FP(fp))
2299 fp->txdata_ptr[0] = &bp->bnx2x_txq[FCOE_TXQ_IDX(bp)];
2300 if (IS_ETH_FP(fp))
2301 for_each_cos_in_tx_queue(fp, cos)
2302 fp->txdata_ptr[cos] = &bp->bnx2x_txq[cos *
2303 BNX2X_NUM_ETH_QUEUES(bp) + index];
2304
2305 /*
2306 * set the tpa flag for each queue. The tpa flag determines the queue
2307 * minimal size so it must be set prior to queue memory allocation
2308 */
2309 fp->disable_tpa = !(bp->flags & TPA_ENABLE_FLAG ||
2310 (bp->flags & GRO_ENABLE_FLAG &&
2311 bnx2x_mtu_allows_gro(bp->dev->mtu)));
2312 if (bp->flags & TPA_ENABLE_FLAG)
2313 fp->mode = TPA_MODE_LRO;
2314 else if (bp->flags & GRO_ENABLE_FLAG)
2315 fp->mode = TPA_MODE_GRO;
2316
2317 /* We don't want TPA on an FCoE L2 ring */
2318 if (IS_FCOE_FP(fp))
2319 fp->disable_tpa = 1;
2320 }
2321
2322 int bnx2x_load_cnic(struct bnx2x *bp)
2323 {
2324 int i, rc, port = BP_PORT(bp);
2325
2326 DP(NETIF_MSG_IFUP, "Starting CNIC-related load\n");
2327
2328 mutex_init(&bp->cnic_mutex);
2329
2330 if (IS_PF(bp)) {
2331 rc = bnx2x_alloc_mem_cnic(bp);
2332 if (rc) {
2333 BNX2X_ERR("Unable to allocate bp memory for cnic\n");
2334 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2335 }
2336 }
2337
2338 rc = bnx2x_alloc_fp_mem_cnic(bp);
2339 if (rc) {
2340 BNX2X_ERR("Unable to allocate memory for cnic fps\n");
2341 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2342 }
2343
2344 /* Update the number of queues with the cnic queues */
2345 rc = bnx2x_set_real_num_queues(bp, 1);
2346 if (rc) {
2347 BNX2X_ERR("Unable to set real_num_queues including cnic\n");
2348 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2349 }
2350
2351 /* Add all CNIC NAPI objects */
2352 bnx2x_add_all_napi_cnic(bp);
2353 DP(NETIF_MSG_IFUP, "cnic napi added\n");
2354 bnx2x_napi_enable_cnic(bp);
2355
2356 rc = bnx2x_init_hw_func_cnic(bp);
2357 if (rc)
2358 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic1);
2359
2360 bnx2x_nic_init_cnic(bp);
2361
2362 if (IS_PF(bp)) {
2363 /* Enable Timer scan */
2364 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 1);
2365
2366 /* setup cnic queues */
2367 for_each_cnic_queue(bp, i) {
2368 rc = bnx2x_setup_queue(bp, &bp->fp[i], 0);
2369 if (rc) {
2370 BNX2X_ERR("Queue setup failed\n");
2371 LOAD_ERROR_EXIT(bp, load_error_cnic2);
2372 }
2373 }
2374 }
2375
2376 /* Initialize Rx filter. */
2377 netif_addr_lock_bh(bp->dev);
2378 bnx2x_set_rx_mode(bp->dev);
2379 netif_addr_unlock_bh(bp->dev);
2380
2381 /* re-read iscsi info */
2382 bnx2x_get_iscsi_info(bp);
2383 bnx2x_setup_cnic_irq_info(bp);
2384 bnx2x_setup_cnic_info(bp);
2385 bp->cnic_loaded = true;
2386 if (bp->state == BNX2X_STATE_OPEN)
2387 bnx2x_cnic_notify(bp, CNIC_CTL_START_CMD);
2388
2389
2390 DP(NETIF_MSG_IFUP, "Ending successfully CNIC-related load\n");
2391
2392 return 0;
2393
2394 #ifndef BNX2X_STOP_ON_ERROR
2395 load_error_cnic2:
2396 /* Disable Timer scan */
2397 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
2398
2399 load_error_cnic1:
2400 bnx2x_napi_disable_cnic(bp);
2401 /* Update the number of queues without the cnic queues */
2402 rc = bnx2x_set_real_num_queues(bp, 0);
2403 if (rc)
2404 BNX2X_ERR("Unable to set real_num_queues not including cnic\n");
2405 load_error_cnic0:
2406 BNX2X_ERR("CNIC-related load failed\n");
2407 bnx2x_free_fp_mem_cnic(bp);
2408 bnx2x_free_mem_cnic(bp);
2409 return rc;
2410 #endif /* ! BNX2X_STOP_ON_ERROR */
2411 }
2412
2413
2414 /* must be called with rtnl_lock */
2415 int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
2416 {
2417 int port = BP_PORT(bp);
2418 int i, rc = 0, load_code = 0;
2419
2420 DP(NETIF_MSG_IFUP, "Starting NIC load\n");
2421 DP(NETIF_MSG_IFUP,
2422 "CNIC is %s\n", CNIC_ENABLED(bp) ? "enabled" : "disabled");
2423
2424 #ifdef BNX2X_STOP_ON_ERROR
2425 if (unlikely(bp->panic)) {
2426 BNX2X_ERR("Can't load NIC when there is panic\n");
2427 return -EPERM;
2428 }
2429 #endif
2430
2431 bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
2432
2433 /* Set the initial link reported state to link down */
2434 bnx2x_acquire_phy_lock(bp);
2435 memset(&bp->last_reported_link, 0, sizeof(bp->last_reported_link));
2436 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
2437 &bp->last_reported_link.link_report_flags);
2438 bnx2x_release_phy_lock(bp);
2439
2440 if (IS_PF(bp))
2441 /* must be called before memory allocation and HW init */
2442 bnx2x_ilt_set_info(bp);
2443
2444 /*
2445 * Zero fastpath structures preserving invariants like napi, which are
2446 * allocated only once, fp index, max_cos, bp pointer.
2447 * Also set fp->disable_tpa and txdata_ptr.
2448 */
2449 DP(NETIF_MSG_IFUP, "num queues: %d", bp->num_queues);
2450 for_each_queue(bp, i)
2451 bnx2x_bz_fp(bp, i);
2452 memset(bp->bnx2x_txq, 0, (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS +
2453 bp->num_cnic_queues) *
2454 sizeof(struct bnx2x_fp_txdata));
2455
2456 bp->fcoe_init = false;
2457
2458 /* Set the receive queues buffer size */
2459 bnx2x_set_rx_buf_size(bp);
2460
2461 if (IS_PF(bp)) {
2462 rc = bnx2x_alloc_mem(bp);
2463 if (rc) {
2464 BNX2X_ERR("Unable to allocate bp memory\n");
2465 return rc;
2466 }
2467 }
2468
2469 /* Allocated memory for FW statistics */
2470 if (bnx2x_alloc_fw_stats_mem(bp))
2471 LOAD_ERROR_EXIT(bp, load_error0);
2472
2473 /* need to be done after alloc mem, since it's self adjusting to amount
2474 * of memory available for RSS queues
2475 */
2476 rc = bnx2x_alloc_fp_mem(bp);
2477 if (rc) {
2478 BNX2X_ERR("Unable to allocate memory for fps\n");
2479 LOAD_ERROR_EXIT(bp, load_error0);
2480 }
2481
2482 /* request pf to initialize status blocks */
2483 if (IS_VF(bp)) {
2484 rc = bnx2x_vfpf_init(bp);
2485 if (rc)
2486 LOAD_ERROR_EXIT(bp, load_error0);
2487 }
2488
2489 /* As long as bnx2x_alloc_mem() may possibly update
2490 * bp->num_queues, bnx2x_set_real_num_queues() should always
2491 * come after it. At this stage cnic queues are not counted.
2492 */
2493 rc = bnx2x_set_real_num_queues(bp, 0);
2494 if (rc) {
2495 BNX2X_ERR("Unable to set real_num_queues\n");
2496 LOAD_ERROR_EXIT(bp, load_error0);
2497 }
2498
2499 /* configure multi cos mappings in kernel.
2500 * this configuration may be overriden by a multi class queue discipline
2501 * or by a dcbx negotiation result.
2502 */
2503 bnx2x_setup_tc(bp->dev, bp->max_cos);
2504
2505 /* Add all NAPI objects */
2506 bnx2x_add_all_napi(bp);
2507 DP(NETIF_MSG_IFUP, "napi added\n");
2508 bnx2x_napi_enable(bp);
2509
2510 if (IS_PF(bp)) {
2511 /* set pf load just before approaching the MCP */
2512 bnx2x_set_pf_load(bp);
2513
2514 /* if mcp exists send load request and analyze response */
2515 if (!BP_NOMCP(bp)) {
2516 /* attempt to load pf */
2517 rc = bnx2x_nic_load_request(bp, &load_code);
2518 if (rc)
2519 LOAD_ERROR_EXIT(bp, load_error1);
2520
2521 /* what did mcp say? */
2522 rc = bnx2x_nic_load_analyze_req(bp, load_code);
2523 if (rc) {
2524 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2525 LOAD_ERROR_EXIT(bp, load_error2);
2526 }
2527 } else {
2528 load_code = bnx2x_nic_load_no_mcp(bp, port);
2529 }
2530
2531 /* mark pmf if applicable */
2532 bnx2x_nic_load_pmf(bp, load_code);
2533
2534 /* Init Function state controlling object */
2535 bnx2x__init_func_obj(bp);
2536
2537 /* Initialize HW */
2538 rc = bnx2x_init_hw(bp, load_code);
2539 if (rc) {
2540 BNX2X_ERR("HW init failed, aborting\n");
2541 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2542 LOAD_ERROR_EXIT(bp, load_error2);
2543 }
2544 }
2545
2546 /* Connect to IRQs */
2547 rc = bnx2x_setup_irqs(bp);
2548 if (rc) {
2549 BNX2X_ERR("setup irqs failed\n");
2550 if (IS_PF(bp))
2551 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2552 LOAD_ERROR_EXIT(bp, load_error2);
2553 }
2554
2555 /* Setup NIC internals and enable interrupts */
2556 bnx2x_nic_init(bp, load_code);
2557
2558 /* Init per-function objects */
2559 if (IS_PF(bp)) {
2560 bnx2x_init_bp_objs(bp);
2561 bnx2x_iov_nic_init(bp);
2562
2563 /* Set AFEX default VLAN tag to an invalid value */
2564 bp->afex_def_vlan_tag = -1;
2565 bnx2x_nic_load_afex_dcc(bp, load_code);
2566 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
2567 rc = bnx2x_func_start(bp);
2568 if (rc) {
2569 BNX2X_ERR("Function start failed!\n");
2570 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2571
2572 LOAD_ERROR_EXIT(bp, load_error3);
2573 }
2574
2575 /* Send LOAD_DONE command to MCP */
2576 if (!BP_NOMCP(bp)) {
2577 load_code = bnx2x_fw_command(bp,
2578 DRV_MSG_CODE_LOAD_DONE, 0);
2579 if (!load_code) {
2580 BNX2X_ERR("MCP response failure, aborting\n");
2581 rc = -EBUSY;
2582 LOAD_ERROR_EXIT(bp, load_error3);
2583 }
2584 }
2585
2586 /* setup the leading queue */
2587 rc = bnx2x_setup_leading(bp);
2588 if (rc) {
2589 BNX2X_ERR("Setup leading failed!\n");
2590 LOAD_ERROR_EXIT(bp, load_error3);
2591 }
2592
2593 /* set up the rest of the queues */
2594 for_each_nondefault_eth_queue(bp, i) {
2595 rc = bnx2x_setup_queue(bp, &bp->fp[i], 0);
2596 if (rc) {
2597 BNX2X_ERR("Queue setup failed\n");
2598 LOAD_ERROR_EXIT(bp, load_error3);
2599 }
2600 }
2601
2602 /* setup rss */
2603 rc = bnx2x_init_rss_pf(bp);
2604 if (rc) {
2605 BNX2X_ERR("PF RSS init failed\n");
2606 LOAD_ERROR_EXIT(bp, load_error3);
2607 }
2608
2609 } else { /* vf */
2610 for_each_eth_queue(bp, i) {
2611 rc = bnx2x_vfpf_setup_q(bp, i);
2612 if (rc) {
2613 BNX2X_ERR("Queue setup failed\n");
2614 LOAD_ERROR_EXIT(bp, load_error3);
2615 }
2616 }
2617 }
2618
2619 /* Now when Clients are configured we are ready to work */
2620 bp->state = BNX2X_STATE_OPEN;
2621
2622 /* Configure a ucast MAC */
2623 if (IS_PF(bp))
2624 rc = bnx2x_set_eth_mac(bp, true);
2625 else /* vf */
2626 rc = bnx2x_vfpf_set_mac(bp);
2627 if (rc) {
2628 BNX2X_ERR("Setting Ethernet MAC failed\n");
2629 LOAD_ERROR_EXIT(bp, load_error3);
2630 }
2631
2632 if (IS_PF(bp) && bp->pending_max) {
2633 bnx2x_update_max_mf_config(bp, bp->pending_max);
2634 bp->pending_max = 0;
2635 }
2636
2637 if (bp->port.pmf) {
2638 rc = bnx2x_initial_phy_init(bp, load_mode);
2639 if (rc)
2640 LOAD_ERROR_EXIT(bp, load_error3);
2641 }
2642 bp->link_params.feature_config_flags &= ~FEATURE_CONFIG_BOOT_FROM_SAN;
2643
2644 /* Start fast path */
2645
2646 /* Initialize Rx filter. */
2647 netif_addr_lock_bh(bp->dev);
2648 bnx2x_set_rx_mode(bp->dev);
2649 netif_addr_unlock_bh(bp->dev);
2650
2651 /* Start the Tx */
2652 switch (load_mode) {
2653 case LOAD_NORMAL:
2654 /* Tx queue should be only reenabled */
2655 netif_tx_wake_all_queues(bp->dev);
2656 break;
2657
2658 case LOAD_OPEN:
2659 netif_tx_start_all_queues(bp->dev);
2660 smp_mb__after_clear_bit();
2661 break;
2662
2663 case LOAD_DIAG:
2664 case LOAD_LOOPBACK_EXT:
2665 bp->state = BNX2X_STATE_DIAG;
2666 break;
2667
2668 default:
2669 break;
2670 }
2671
2672 if (bp->port.pmf)
2673 bnx2x_update_drv_flags(bp, 1 << DRV_FLAGS_PORT_MASK, 0);
2674 else
2675 bnx2x__link_status_update(bp);
2676
2677 /* start the timer */
2678 mod_timer(&bp->timer, jiffies + bp->current_interval);
2679
2680 if (CNIC_ENABLED(bp))
2681 bnx2x_load_cnic(bp);
2682
2683 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2684 /* mark driver is loaded in shmem2 */
2685 u32 val;
2686 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2687 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2688 val | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
2689 DRV_FLAGS_CAPABILITIES_LOADED_L2);
2690 }
2691
2692 /* Wait for all pending SP commands to complete */
2693 if (IS_PF(bp) && !bnx2x_wait_sp_comp(bp, ~0x0UL)) {
2694 BNX2X_ERR("Timeout waiting for SP elements to complete\n");
2695 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
2696 return -EBUSY;
2697 }
2698
2699 /* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */
2700 if (bp->port.pmf && (bp->state != BNX2X_STATE_DIAG))
2701 bnx2x_dcbx_init(bp, false);
2702
2703 DP(NETIF_MSG_IFUP, "Ending successfully NIC load\n");
2704
2705 return 0;
2706
2707 #ifndef BNX2X_STOP_ON_ERROR
2708 load_error3:
2709 if (IS_PF(bp)) {
2710 bnx2x_int_disable_sync(bp, 1);
2711
2712 /* Clean queueable objects */
2713 bnx2x_squeeze_objects(bp);
2714 }
2715
2716 /* Free SKBs, SGEs, TPA pool and driver internals */
2717 bnx2x_free_skbs(bp);
2718 for_each_rx_queue(bp, i)
2719 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
2720
2721 /* Release IRQs */
2722 bnx2x_free_irq(bp);
2723 load_error2:
2724 if (IS_PF(bp) && !BP_NOMCP(bp)) {
2725 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
2726 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
2727 }
2728
2729 bp->port.pmf = 0;
2730 load_error1:
2731 bnx2x_napi_disable(bp);
2732
2733 /* clear pf_load status, as it was already set */
2734 if (IS_PF(bp))
2735 bnx2x_clear_pf_load(bp);
2736 load_error0:
2737 bnx2x_free_fp_mem(bp);
2738 bnx2x_free_fw_stats_mem(bp);
2739 bnx2x_free_mem(bp);
2740
2741 return rc;
2742 #endif /* ! BNX2X_STOP_ON_ERROR */
2743 }
2744
2745 static int bnx2x_drain_tx_queues(struct bnx2x *bp)
2746 {
2747 u8 rc = 0, cos, i;
2748
2749 /* Wait until tx fastpath tasks complete */
2750 for_each_tx_queue(bp, i) {
2751 struct bnx2x_fastpath *fp = &bp->fp[i];
2752
2753 for_each_cos_in_tx_queue(fp, cos)
2754 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
2755 if (rc)
2756 return rc;
2757 }
2758 return 0;
2759 }
2760
2761 /* must be called with rtnl_lock */
2762 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link)
2763 {
2764 int i;
2765 bool global = false;
2766
2767 DP(NETIF_MSG_IFUP, "Starting NIC unload\n");
2768
2769 /* mark driver is unloaded in shmem2 */
2770 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2771 u32 val;
2772 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2773 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2774 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2775 }
2776
2777 if (IS_PF(bp) &&
2778 (bp->state == BNX2X_STATE_CLOSED ||
2779 bp->state == BNX2X_STATE_ERROR)) {
2780 /* We can get here if the driver has been unloaded
2781 * during parity error recovery and is either waiting for a
2782 * leader to complete or for other functions to unload and
2783 * then ifdown has been issued. In this case we want to
2784 * unload and let other functions to complete a recovery
2785 * process.
2786 */
2787 bp->recovery_state = BNX2X_RECOVERY_DONE;
2788 bp->is_leader = 0;
2789 bnx2x_release_leader_lock(bp);
2790 smp_mb();
2791
2792 DP(NETIF_MSG_IFDOWN, "Releasing a leadership...\n");
2793 BNX2X_ERR("Can't unload in closed or error state\n");
2794 return -EINVAL;
2795 }
2796
2797 /*
2798 * It's important to set the bp->state to the value different from
2799 * BNX2X_STATE_OPEN and only then stop the Tx. Otherwise bnx2x_tx_int()
2800 * may restart the Tx from the NAPI context (see bnx2x_tx_int()).
2801 */
2802 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
2803 smp_mb();
2804
2805 if (CNIC_LOADED(bp))
2806 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
2807
2808 /* Stop Tx */
2809 bnx2x_tx_disable(bp);
2810 netdev_reset_tc(bp->dev);
2811
2812 bp->rx_mode = BNX2X_RX_MODE_NONE;
2813
2814 del_timer_sync(&bp->timer);
2815
2816 if (IS_PF(bp)) {
2817 /* Set ALWAYS_ALIVE bit in shmem */
2818 bp->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2819 bnx2x_drv_pulse(bp);
2820 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2821 bnx2x_save_statistics(bp);
2822 }
2823
2824 /* wait till consumers catch up with producers in all queues */
2825 bnx2x_drain_tx_queues(bp);
2826
2827 /* if VF indicate to PF this function is going down (PF will delete sp
2828 * elements and clear initializations
2829 */
2830 if (IS_VF(bp))
2831 bnx2x_vfpf_close_vf(bp);
2832 else if (unload_mode != UNLOAD_RECOVERY)
2833 /* if this is a normal/close unload need to clean up chip*/
2834 bnx2x_chip_cleanup(bp, unload_mode, keep_link);
2835 else {
2836 /* Send the UNLOAD_REQUEST to the MCP */
2837 bnx2x_send_unload_req(bp, unload_mode);
2838
2839 /*
2840 * Prevent transactions to host from the functions on the
2841 * engine that doesn't reset global blocks in case of global
2842 * attention once gloabl blocks are reset and gates are opened
2843 * (the engine which leader will perform the recovery
2844 * last).
2845 */
2846 if (!CHIP_IS_E1x(bp))
2847 bnx2x_pf_disable(bp);
2848
2849 /* Disable HW interrupts, NAPI */
2850 bnx2x_netif_stop(bp, 1);
2851 /* Delete all NAPI objects */
2852 bnx2x_del_all_napi(bp);
2853 if (CNIC_LOADED(bp))
2854 bnx2x_del_all_napi_cnic(bp);
2855 /* Release IRQs */
2856 bnx2x_free_irq(bp);
2857
2858 /* Report UNLOAD_DONE to MCP */
2859 bnx2x_send_unload_done(bp, false);
2860 }
2861
2862 /*
2863 * At this stage no more interrupts will arrive so we may safly clean
2864 * the queueable objects here in case they failed to get cleaned so far.
2865 */
2866 if (IS_PF(bp))
2867 bnx2x_squeeze_objects(bp);
2868
2869 /* There should be no more pending SP commands at this stage */
2870 bp->sp_state = 0;
2871
2872 bp->port.pmf = 0;
2873
2874 /* Free SKBs, SGEs, TPA pool and driver internals */
2875 bnx2x_free_skbs(bp);
2876 if (CNIC_LOADED(bp))
2877 bnx2x_free_skbs_cnic(bp);
2878 for_each_rx_queue(bp, i)
2879 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
2880
2881 bnx2x_free_fp_mem(bp);
2882 if (CNIC_LOADED(bp))
2883 bnx2x_free_fp_mem_cnic(bp);
2884
2885 if (IS_PF(bp)) {
2886 bnx2x_free_mem(bp);
2887 if (CNIC_LOADED(bp))
2888 bnx2x_free_mem_cnic(bp);
2889 }
2890 bp->state = BNX2X_STATE_CLOSED;
2891 bp->cnic_loaded = false;
2892
2893 /* Check if there are pending parity attentions. If there are - set
2894 * RECOVERY_IN_PROGRESS.
2895 */
2896 if (IS_PF(bp) && bnx2x_chk_parity_attn(bp, &global, false)) {
2897 bnx2x_set_reset_in_progress(bp);
2898
2899 /* Set RESET_IS_GLOBAL if needed */
2900 if (global)
2901 bnx2x_set_reset_global(bp);
2902 }
2903
2904
2905 /* The last driver must disable a "close the gate" if there is no
2906 * parity attention or "process kill" pending.
2907 */
2908 if (IS_PF(bp) &&
2909 !bnx2x_clear_pf_load(bp) &&
2910 bnx2x_reset_is_done(bp, BP_PATH(bp)))
2911 bnx2x_disable_close_the_gate(bp);
2912
2913 DP(NETIF_MSG_IFUP, "Ending NIC unload\n");
2914
2915 return 0;
2916 }
2917
2918 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
2919 {
2920 u16 pmcsr;
2921
2922 /* If there is no power capability, silently succeed */
2923 if (!bp->pm_cap) {
2924 BNX2X_DEV_INFO("No power capability. Breaking.\n");
2925 return 0;
2926 }
2927
2928 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2929
2930 switch (state) {
2931 case PCI_D0:
2932 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2933 ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2934 PCI_PM_CTRL_PME_STATUS));
2935
2936 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2937 /* delay required during transition out of D3hot */
2938 msleep(20);
2939 break;
2940
2941 case PCI_D3hot:
2942 /* If there are other clients above don't
2943 shut down the power */
2944 if (atomic_read(&bp->pdev->enable_cnt) != 1)
2945 return 0;
2946 /* Don't shut down the power for emulation and FPGA */
2947 if (CHIP_REV_IS_SLOW(bp))
2948 return 0;
2949
2950 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2951 pmcsr |= 3;
2952
2953 if (bp->wol)
2954 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2955
2956 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2957 pmcsr);
2958
2959 /* No more memory access after this point until
2960 * device is brought back to D0.
2961 */
2962 break;
2963
2964 default:
2965 dev_err(&bp->pdev->dev, "Can't support state = %d\n", state);
2966 return -EINVAL;
2967 }
2968 return 0;
2969 }
2970
2971 /*
2972 * net_device service functions
2973 */
2974 int bnx2x_poll(struct napi_struct *napi, int budget)
2975 {
2976 int work_done = 0;
2977 u8 cos;
2978 struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
2979 napi);
2980 struct bnx2x *bp = fp->bp;
2981
2982 while (1) {
2983 #ifdef BNX2X_STOP_ON_ERROR
2984 if (unlikely(bp->panic)) {
2985 napi_complete(napi);
2986 return 0;
2987 }
2988 #endif
2989
2990 for_each_cos_in_tx_queue(fp, cos)
2991 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
2992 bnx2x_tx_int(bp, fp->txdata_ptr[cos]);
2993
2994
2995 if (bnx2x_has_rx_work(fp)) {
2996 work_done += bnx2x_rx_int(fp, budget - work_done);
2997
2998 /* must not complete if we consumed full budget */
2999 if (work_done >= budget)
3000 break;
3001 }
3002
3003 /* Fall out from the NAPI loop if needed */
3004 if (!(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
3005
3006 /* No need to update SB for FCoE L2 ring as long as
3007 * it's connected to the default SB and the SB
3008 * has been updated when NAPI was scheduled.
3009 */
3010 if (IS_FCOE_FP(fp)) {
3011 napi_complete(napi);
3012 break;
3013 }
3014 bnx2x_update_fpsb_idx(fp);
3015 /* bnx2x_has_rx_work() reads the status block,
3016 * thus we need to ensure that status block indices
3017 * have been actually read (bnx2x_update_fpsb_idx)
3018 * prior to this check (bnx2x_has_rx_work) so that
3019 * we won't write the "newer" value of the status block
3020 * to IGU (if there was a DMA right after
3021 * bnx2x_has_rx_work and if there is no rmb, the memory
3022 * reading (bnx2x_update_fpsb_idx) may be postponed
3023 * to right before bnx2x_ack_sb). In this case there
3024 * will never be another interrupt until there is
3025 * another update of the status block, while there
3026 * is still unhandled work.
3027 */
3028 rmb();
3029
3030 if (!(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
3031 napi_complete(napi);
3032 /* Re-enable interrupts */
3033 DP(NETIF_MSG_RX_STATUS,
3034 "Update index to %d\n", fp->fp_hc_idx);
3035 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID,
3036 le16_to_cpu(fp->fp_hc_idx),
3037 IGU_INT_ENABLE, 1);
3038 break;
3039 }
3040 }
3041 }
3042
3043 return work_done;
3044 }
3045
3046 /* we split the first BD into headers and data BDs
3047 * to ease the pain of our fellow microcode engineers
3048 * we use one mapping for both BDs
3049 */
3050 static noinline u16 bnx2x_tx_split(struct bnx2x *bp,
3051 struct bnx2x_fp_txdata *txdata,
3052 struct sw_tx_bd *tx_buf,
3053 struct eth_tx_start_bd **tx_bd, u16 hlen,
3054 u16 bd_prod, int nbd)
3055 {
3056 struct eth_tx_start_bd *h_tx_bd = *tx_bd;
3057 struct eth_tx_bd *d_tx_bd;
3058 dma_addr_t mapping;
3059 int old_len = le16_to_cpu(h_tx_bd->nbytes);
3060
3061 /* first fix first BD */
3062 h_tx_bd->nbd = cpu_to_le16(nbd);
3063 h_tx_bd->nbytes = cpu_to_le16(hlen);
3064
3065 DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d (%x:%x) nbd %d\n",
3066 h_tx_bd->nbytes, h_tx_bd->addr_hi, h_tx_bd->addr_lo, h_tx_bd->nbd);
3067
3068 /* now get a new data BD
3069 * (after the pbd) and fill it */
3070 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3071 d_tx_bd = &txdata->tx_desc_ring[bd_prod].reg_bd;
3072
3073 mapping = HILO_U64(le32_to_cpu(h_tx_bd->addr_hi),
3074 le32_to_cpu(h_tx_bd->addr_lo)) + hlen;
3075
3076 d_tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
3077 d_tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
3078 d_tx_bd->nbytes = cpu_to_le16(old_len - hlen);
3079
3080 /* this marks the BD as one that has no individual mapping */
3081 tx_buf->flags |= BNX2X_TSO_SPLIT_BD;
3082
3083 DP(NETIF_MSG_TX_QUEUED,
3084 "TSO split data size is %d (%x:%x)\n",
3085 d_tx_bd->nbytes, d_tx_bd->addr_hi, d_tx_bd->addr_lo);
3086
3087 /* update tx_bd */
3088 *tx_bd = (struct eth_tx_start_bd *)d_tx_bd;
3089
3090 return bd_prod;
3091 }
3092
3093 static inline u16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix)
3094 {
3095 if (fix > 0)
3096 csum = (u16) ~csum_fold(csum_sub(csum,
3097 csum_partial(t_header - fix, fix, 0)));
3098
3099 else if (fix < 0)
3100 csum = (u16) ~csum_fold(csum_add(csum,
3101 csum_partial(t_header, -fix, 0)));
3102
3103 return swab16(csum);
3104 }
3105
3106 static inline u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
3107 {
3108 u32 rc;
3109
3110 if (skb->ip_summed != CHECKSUM_PARTIAL)
3111 rc = XMIT_PLAIN;
3112
3113 else {
3114 if (vlan_get_protocol(skb) == htons(ETH_P_IPV6)) {
3115 rc = XMIT_CSUM_V6;
3116 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3117 rc |= XMIT_CSUM_TCP;
3118
3119 } else {
3120 rc = XMIT_CSUM_V4;
3121 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3122 rc |= XMIT_CSUM_TCP;
3123 }
3124 }
3125
3126 if (skb_is_gso_v6(skb))
3127 rc |= XMIT_GSO_V6 | XMIT_CSUM_TCP | XMIT_CSUM_V6;
3128 else if (skb_is_gso(skb))
3129 rc |= XMIT_GSO_V4 | XMIT_CSUM_V4 | XMIT_CSUM_TCP;
3130
3131 return rc;
3132 }
3133
3134 #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
3135 /* check if packet requires linearization (packet is too fragmented)
3136 no need to check fragmentation if page size > 8K (there will be no
3137 violation to FW restrictions) */
3138 static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
3139 u32 xmit_type)
3140 {
3141 int to_copy = 0;
3142 int hlen = 0;
3143 int first_bd_sz = 0;
3144
3145 /* 3 = 1 (for linear data BD) + 2 (for PBD and last BD) */
3146 if (skb_shinfo(skb)->nr_frags >= (MAX_FETCH_BD - 3)) {
3147
3148 if (xmit_type & XMIT_GSO) {
3149 unsigned short lso_mss = skb_shinfo(skb)->gso_size;
3150 /* Check if LSO packet needs to be copied:
3151 3 = 1 (for headers BD) + 2 (for PBD and last BD) */
3152 int wnd_size = MAX_FETCH_BD - 3;
3153 /* Number of windows to check */
3154 int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size;
3155 int wnd_idx = 0;
3156 int frag_idx = 0;
3157 u32 wnd_sum = 0;
3158
3159 /* Headers length */
3160 hlen = (int)(skb_transport_header(skb) - skb->data) +
3161 tcp_hdrlen(skb);
3162
3163 /* Amount of data (w/o headers) on linear part of SKB*/
3164 first_bd_sz = skb_headlen(skb) - hlen;
3165
3166 wnd_sum = first_bd_sz;
3167
3168 /* Calculate the first sum - it's special */
3169 for (frag_idx = 0; frag_idx < wnd_size - 1; frag_idx++)
3170 wnd_sum +=
3171 skb_frag_size(&skb_shinfo(skb)->frags[frag_idx]);
3172
3173 /* If there was data on linear skb data - check it */
3174 if (first_bd_sz > 0) {
3175 if (unlikely(wnd_sum < lso_mss)) {
3176 to_copy = 1;
3177 goto exit_lbl;
3178 }
3179
3180 wnd_sum -= first_bd_sz;
3181 }
3182
3183 /* Others are easier: run through the frag list and
3184 check all windows */
3185 for (wnd_idx = 0; wnd_idx <= num_wnds; wnd_idx++) {
3186 wnd_sum +=
3187 skb_frag_size(&skb_shinfo(skb)->frags[wnd_idx + wnd_size - 1]);
3188
3189 if (unlikely(wnd_sum < lso_mss)) {
3190 to_copy = 1;
3191 break;
3192 }
3193 wnd_sum -=
3194 skb_frag_size(&skb_shinfo(skb)->frags[wnd_idx]);
3195 }
3196 } else {
3197 /* in non-LSO too fragmented packet should always
3198 be linearized */
3199 to_copy = 1;
3200 }
3201 }
3202
3203 exit_lbl:
3204 if (unlikely(to_copy))
3205 DP(NETIF_MSG_TX_QUEUED,
3206 "Linearization IS REQUIRED for %s packet. num_frags %d hlen %d first_bd_sz %d\n",
3207 (xmit_type & XMIT_GSO) ? "LSO" : "non-LSO",
3208 skb_shinfo(skb)->nr_frags, hlen, first_bd_sz);
3209
3210 return to_copy;
3211 }
3212 #endif
3213
3214 static inline void bnx2x_set_pbd_gso_e2(struct sk_buff *skb, u32 *parsing_data,
3215 u32 xmit_type)
3216 {
3217 *parsing_data |= (skb_shinfo(skb)->gso_size <<
3218 ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) &
3219 ETH_TX_PARSE_BD_E2_LSO_MSS;
3220 if ((xmit_type & XMIT_GSO_V6) &&
3221 (ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
3222 *parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR;
3223 }
3224
3225 /**
3226 * bnx2x_set_pbd_gso - update PBD in GSO case.
3227 *
3228 * @skb: packet skb
3229 * @pbd: parse BD
3230 * @xmit_type: xmit flags
3231 */
3232 static inline void bnx2x_set_pbd_gso(struct sk_buff *skb,
3233 struct eth_tx_parse_bd_e1x *pbd,
3234 u32 xmit_type)
3235 {
3236 pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
3237 pbd->tcp_send_seq = swab32(tcp_hdr(skb)->seq);
3238 pbd->tcp_flags = pbd_tcp_flags(skb);
3239
3240 if (xmit_type & XMIT_GSO_V4) {
3241 pbd->ip_id = swab16(ip_hdr(skb)->id);
3242 pbd->tcp_pseudo_csum =
3243 swab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
3244 ip_hdr(skb)->daddr,
3245 0, IPPROTO_TCP, 0));
3246
3247 } else
3248 pbd->tcp_pseudo_csum =
3249 swab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3250 &ipv6_hdr(skb)->daddr,
3251 0, IPPROTO_TCP, 0));
3252
3253 pbd->global_data |= ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN;
3254 }
3255
3256 /**
3257 * bnx2x_set_pbd_csum_e2 - update PBD with checksum and return header length
3258 *
3259 * @bp: driver handle
3260 * @skb: packet skb
3261 * @parsing_data: data to be updated
3262 * @xmit_type: xmit flags
3263 *
3264 * 57712 related
3265 */
3266 static inline u8 bnx2x_set_pbd_csum_e2(struct bnx2x *bp, struct sk_buff *skb,
3267 u32 *parsing_data, u32 xmit_type)
3268 {
3269 *parsing_data |=
3270 ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) <<
3271 ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT) &
3272 ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W;
3273
3274 if (xmit_type & XMIT_CSUM_TCP) {
3275 *parsing_data |= ((tcp_hdrlen(skb) / 4) <<
3276 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) &
3277 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW;
3278
3279 return skb_transport_header(skb) + tcp_hdrlen(skb) - skb->data;
3280 } else
3281 /* We support checksum offload for TCP and UDP only.
3282 * No need to pass the UDP header length - it's a constant.
3283 */
3284 return skb_transport_header(skb) +
3285 sizeof(struct udphdr) - skb->data;
3286 }
3287
3288 static inline void bnx2x_set_sbd_csum(struct bnx2x *bp, struct sk_buff *skb,
3289 struct eth_tx_start_bd *tx_start_bd, u32 xmit_type)
3290 {
3291 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
3292
3293 if (xmit_type & XMIT_CSUM_V4)
3294 tx_start_bd->bd_flags.as_bitfield |=
3295 ETH_TX_BD_FLAGS_IP_CSUM;
3296 else
3297 tx_start_bd->bd_flags.as_bitfield |=
3298 ETH_TX_BD_FLAGS_IPV6;
3299
3300 if (!(xmit_type & XMIT_CSUM_TCP))
3301 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IS_UDP;
3302 }
3303
3304 /**
3305 * bnx2x_set_pbd_csum - update PBD with checksum and return header length
3306 *
3307 * @bp: driver handle
3308 * @skb: packet skb
3309 * @pbd: parse BD to be updated
3310 * @xmit_type: xmit flags
3311 */
3312 static inline u8 bnx2x_set_pbd_csum(struct bnx2x *bp, struct sk_buff *skb,
3313 struct eth_tx_parse_bd_e1x *pbd,
3314 u32 xmit_type)
3315 {
3316 u8 hlen = (skb_network_header(skb) - skb->data) >> 1;
3317
3318 /* for now NS flag is not used in Linux */
3319 pbd->global_data =
3320 (hlen | ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) <<
3321 ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT));
3322
3323 pbd->ip_hlen_w = (skb_transport_header(skb) -
3324 skb_network_header(skb)) >> 1;
3325
3326 hlen += pbd->ip_hlen_w;
3327
3328 /* We support checksum offload for TCP and UDP only */
3329 if (xmit_type & XMIT_CSUM_TCP)
3330 hlen += tcp_hdrlen(skb) / 2;
3331 else
3332 hlen += sizeof(struct udphdr) / 2;
3333
3334 pbd->total_hlen_w = cpu_to_le16(hlen);
3335 hlen = hlen*2;
3336
3337 if (xmit_type & XMIT_CSUM_TCP) {
3338 pbd->tcp_pseudo_csum = swab16(tcp_hdr(skb)->check);
3339
3340 } else {
3341 s8 fix = SKB_CS_OFF(skb); /* signed! */
3342
3343 DP(NETIF_MSG_TX_QUEUED,
3344 "hlen %d fix %d csum before fix %x\n",
3345 le16_to_cpu(pbd->total_hlen_w), fix, SKB_CS(skb));
3346
3347 /* HW bug: fixup the CSUM */
3348 pbd->tcp_pseudo_csum =
3349 bnx2x_csum_fix(skb_transport_header(skb),
3350 SKB_CS(skb), fix);
3351
3352 DP(NETIF_MSG_TX_QUEUED, "csum after fix %x\n",
3353 pbd->tcp_pseudo_csum);
3354 }
3355
3356 return hlen;
3357 }
3358
3359 /* called with netif_tx_lock
3360 * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
3361 * netif_wake_queue()
3362 */
3363 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
3364 {
3365 struct bnx2x *bp = netdev_priv(dev);
3366
3367 struct netdev_queue *txq;
3368 struct bnx2x_fp_txdata *txdata;
3369 struct sw_tx_bd *tx_buf;
3370 struct eth_tx_start_bd *tx_start_bd, *first_bd;
3371 struct eth_tx_bd *tx_data_bd, *total_pkt_bd = NULL;
3372 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
3373 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
3374 u32 pbd_e2_parsing_data = 0;
3375 u16 pkt_prod, bd_prod;
3376 int nbd, txq_index;
3377 dma_addr_t mapping;
3378 u32 xmit_type = bnx2x_xmit_type(bp, skb);
3379 int i;
3380 u8 hlen = 0;
3381 __le16 pkt_size = 0;
3382 struct ethhdr *eth;
3383 u8 mac_type = UNICAST_ADDRESS;
3384
3385 #ifdef BNX2X_STOP_ON_ERROR
3386 if (unlikely(bp->panic))
3387 return NETDEV_TX_BUSY;
3388 #endif
3389
3390 txq_index = skb_get_queue_mapping(skb);
3391 txq = netdev_get_tx_queue(dev, txq_index);
3392
3393 BUG_ON(txq_index >= MAX_ETH_TXQ_IDX(bp) + (CNIC_LOADED(bp) ? 1 : 0));
3394
3395 txdata = &bp->bnx2x_txq[txq_index];
3396
3397 /* enable this debug print to view the transmission queue being used
3398 DP(NETIF_MSG_TX_QUEUED, "indices: txq %d, fp %d, txdata %d\n",
3399 txq_index, fp_index, txdata_index); */
3400
3401 /* enable this debug print to view the tranmission details
3402 DP(NETIF_MSG_TX_QUEUED,
3403 "transmitting packet cid %d fp index %d txdata_index %d tx_data ptr %p fp pointer %p\n",
3404 txdata->cid, fp_index, txdata_index, txdata, fp); */
3405
3406 if (unlikely(bnx2x_tx_avail(bp, txdata) <
3407 skb_shinfo(skb)->nr_frags +
3408 BDS_PER_TX_PKT +
3409 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))) {
3410 /* Handle special storage cases separately */
3411 if (txdata->tx_ring_size == 0) {
3412 struct bnx2x_eth_q_stats *q_stats =
3413 bnx2x_fp_qstats(bp, txdata->parent_fp);
3414 q_stats->driver_filtered_tx_pkt++;
3415 dev_kfree_skb(skb);
3416 return NETDEV_TX_OK;
3417 }
3418 bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++;
3419 netif_tx_stop_queue(txq);
3420 BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
3421
3422 return NETDEV_TX_BUSY;
3423 }
3424
3425 DP(NETIF_MSG_TX_QUEUED,
3426 "queue[%d]: SKB: summed %x protocol %x protocol(%x,%x) gso type %x xmit_type %x\n",
3427 txq_index, skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr,
3428 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type);
3429
3430 eth = (struct ethhdr *)skb->data;
3431
3432 /* set flag according to packet type (UNICAST_ADDRESS is default)*/
3433 if (unlikely(is_multicast_ether_addr(eth->h_dest))) {
3434 if (is_broadcast_ether_addr(eth->h_dest))
3435 mac_type = BROADCAST_ADDRESS;
3436 else
3437 mac_type = MULTICAST_ADDRESS;
3438 }
3439
3440 #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
3441 /* First, check if we need to linearize the skb (due to FW
3442 restrictions). No need to check fragmentation if page size > 8K
3443 (there will be no violation to FW restrictions) */
3444 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
3445 /* Statistics of linearization */
3446 bp->lin_cnt++;
3447 if (skb_linearize(skb) != 0) {
3448 DP(NETIF_MSG_TX_QUEUED,
3449 "SKB linearization failed - silently dropping this SKB\n");
3450 dev_kfree_skb_any(skb);
3451 return NETDEV_TX_OK;
3452 }
3453 }
3454 #endif
3455 /* Map skb linear data for DMA */
3456 mapping = dma_map_single(&bp->pdev->dev, skb->data,
3457 skb_headlen(skb), DMA_TO_DEVICE);
3458 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
3459 DP(NETIF_MSG_TX_QUEUED,
3460 "SKB mapping failed - silently dropping this SKB\n");
3461 dev_kfree_skb_any(skb);
3462 return NETDEV_TX_OK;
3463 }
3464 /*
3465 Please read carefully. First we use one BD which we mark as start,
3466 then we have a parsing info BD (used for TSO or xsum),
3467 and only then we have the rest of the TSO BDs.
3468 (don't forget to mark the last one as last,
3469 and to unmap only AFTER you write to the BD ...)
3470 And above all, all pdb sizes are in words - NOT DWORDS!
3471 */
3472
3473 /* get current pkt produced now - advance it just before sending packet
3474 * since mapping of pages may fail and cause packet to be dropped
3475 */
3476 pkt_prod = txdata->tx_pkt_prod;
3477 bd_prod = TX_BD(txdata->tx_bd_prod);
3478
3479 /* get a tx_buf and first BD
3480 * tx_start_bd may be changed during SPLIT,
3481 * but first_bd will always stay first
3482 */
3483 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
3484 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
3485 first_bd = tx_start_bd;
3486
3487 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
3488 SET_FLAG(tx_start_bd->general_data,
3489 ETH_TX_START_BD_PARSE_NBDS,
3490 0);
3491
3492 /* header nbd */
3493 SET_FLAG(tx_start_bd->general_data, ETH_TX_START_BD_HDR_NBDS, 1);
3494
3495 /* remember the first BD of the packet */
3496 tx_buf->first_bd = txdata->tx_bd_prod;
3497 tx_buf->skb = skb;
3498 tx_buf->flags = 0;
3499
3500 DP(NETIF_MSG_TX_QUEUED,
3501 "sending pkt %u @%p next_idx %u bd %u @%p\n",
3502 pkt_prod, tx_buf, txdata->tx_pkt_prod, bd_prod, tx_start_bd);
3503
3504 if (vlan_tx_tag_present(skb)) {
3505 tx_start_bd->vlan_or_ethertype =
3506 cpu_to_le16(vlan_tx_tag_get(skb));
3507 tx_start_bd->bd_flags.as_bitfield |=
3508 (X_ETH_OUTBAND_VLAN << ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
3509 } else {
3510 /* when transmitting in a vf, start bd must hold the ethertype
3511 * for fw to enforce it
3512 */
3513 if (IS_VF(bp)) {
3514 tx_start_bd->vlan_or_ethertype =
3515 cpu_to_le16(ntohs(eth->h_proto));
3516 } else {
3517 /* used by FW for packet accounting */
3518 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
3519 }
3520 }
3521
3522 /* turn on parsing and get a BD */
3523 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3524
3525 if (xmit_type & XMIT_CSUM)
3526 bnx2x_set_sbd_csum(bp, skb, tx_start_bd, xmit_type);
3527
3528 if (!CHIP_IS_E1x(bp)) {
3529 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
3530 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
3531 /* Set PBD in checksum offload case */
3532 if (xmit_type & XMIT_CSUM)
3533 hlen = bnx2x_set_pbd_csum_e2(bp, skb,
3534 &pbd_e2_parsing_data,
3535 xmit_type);
3536
3537 if (IS_MF_SI(bp) || IS_VF(bp)) {
3538 /* fill in the MAC addresses in the PBD - for local
3539 * switching
3540 */
3541 bnx2x_set_fw_mac_addr(&pbd_e2->src_mac_addr_hi,
3542 &pbd_e2->src_mac_addr_mid,
3543 &pbd_e2->src_mac_addr_lo,
3544 eth->h_source);
3545 bnx2x_set_fw_mac_addr(&pbd_e2->dst_mac_addr_hi,
3546 &pbd_e2->dst_mac_addr_mid,
3547 &pbd_e2->dst_mac_addr_lo,
3548 eth->h_dest);
3549 }
3550
3551 SET_FLAG(pbd_e2_parsing_data,
3552 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, mac_type);
3553 } else {
3554 u16 global_data = 0;
3555 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
3556 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
3557 /* Set PBD in checksum offload case */
3558 if (xmit_type & XMIT_CSUM)
3559 hlen = bnx2x_set_pbd_csum(bp, skb, pbd_e1x, xmit_type);
3560
3561 SET_FLAG(global_data,
3562 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type);
3563 pbd_e1x->global_data |= cpu_to_le16(global_data);
3564 }
3565
3566 /* Setup the data pointer of the first BD of the packet */
3567 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
3568 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
3569 nbd = 2; /* start_bd + pbd + frags (updated when pages are mapped) */
3570 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
3571 pkt_size = tx_start_bd->nbytes;
3572
3573 DP(NETIF_MSG_TX_QUEUED,
3574 "first bd @%p addr (%x:%x) nbd %d nbytes %d flags %x vlan %x\n",
3575 tx_start_bd, tx_start_bd->addr_hi, tx_start_bd->addr_lo,
3576 le16_to_cpu(tx_start_bd->nbd), le16_to_cpu(tx_start_bd->nbytes),
3577 tx_start_bd->bd_flags.as_bitfield,
3578 le16_to_cpu(tx_start_bd->vlan_or_ethertype));
3579
3580 if (xmit_type & XMIT_GSO) {
3581
3582 DP(NETIF_MSG_TX_QUEUED,
3583 "TSO packet len %d hlen %d total len %d tso size %d\n",
3584 skb->len, hlen, skb_headlen(skb),
3585 skb_shinfo(skb)->gso_size);
3586
3587 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
3588
3589 if (unlikely(skb_headlen(skb) > hlen))
3590 bd_prod = bnx2x_tx_split(bp, txdata, tx_buf,
3591 &tx_start_bd, hlen,
3592 bd_prod, ++nbd);
3593 if (!CHIP_IS_E1x(bp))
3594 bnx2x_set_pbd_gso_e2(skb, &pbd_e2_parsing_data,
3595 xmit_type);
3596 else
3597 bnx2x_set_pbd_gso(skb, pbd_e1x, xmit_type);
3598 }
3599
3600 /* Set the PBD's parsing_data field if not zero
3601 * (for the chips newer than 57711).
3602 */
3603 if (pbd_e2_parsing_data)
3604 pbd_e2->parsing_data = cpu_to_le32(pbd_e2_parsing_data);
3605
3606 tx_data_bd = (struct eth_tx_bd *)tx_start_bd;
3607
3608 /* Handle fragmented skb */
3609 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3610 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3611
3612 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0,
3613 skb_frag_size(frag), DMA_TO_DEVICE);
3614 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
3615 unsigned int pkts_compl = 0, bytes_compl = 0;
3616
3617 DP(NETIF_MSG_TX_QUEUED,
3618 "Unable to map page - dropping packet...\n");
3619
3620 /* we need unmap all buffers already mapped
3621 * for this SKB;
3622 * first_bd->nbd need to be properly updated
3623 * before call to bnx2x_free_tx_pkt
3624 */
3625 first_bd->nbd = cpu_to_le16(nbd);
3626 bnx2x_free_tx_pkt(bp, txdata,
3627 TX_BD(txdata->tx_pkt_prod),
3628 &pkts_compl, &bytes_compl);
3629 return NETDEV_TX_OK;
3630 }
3631
3632 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3633 tx_data_bd = &txdata->tx_desc_ring[bd_prod].reg_bd;
3634 if (total_pkt_bd == NULL)
3635 total_pkt_bd = &txdata->tx_desc_ring[bd_prod].reg_bd;
3636
3637 tx_data_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
3638 tx_data_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
3639 tx_data_bd->nbytes = cpu_to_le16(skb_frag_size(frag));
3640 le16_add_cpu(&pkt_size, skb_frag_size(frag));
3641 nbd++;
3642
3643 DP(NETIF_MSG_TX_QUEUED,
3644 "frag %d bd @%p addr (%x:%x) nbytes %d\n",
3645 i, tx_data_bd, tx_data_bd->addr_hi, tx_data_bd->addr_lo,
3646 le16_to_cpu(tx_data_bd->nbytes));
3647 }
3648
3649 DP(NETIF_MSG_TX_QUEUED, "last bd @%p\n", tx_data_bd);
3650
3651 /* update with actual num BDs */
3652 first_bd->nbd = cpu_to_le16(nbd);
3653
3654 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3655
3656 /* now send a tx doorbell, counting the next BD
3657 * if the packet contains or ends with it
3658 */
3659 if (TX_BD_POFF(bd_prod) < nbd)
3660 nbd++;
3661
3662 /* total_pkt_bytes should be set on the first data BD if
3663 * it's not an LSO packet and there is more than one
3664 * data BD. In this case pkt_size is limited by an MTU value.
3665 * However we prefer to set it for an LSO packet (while we don't
3666 * have to) in order to save some CPU cycles in a none-LSO
3667 * case, when we much more care about them.
3668 */
3669 if (total_pkt_bd != NULL)
3670 total_pkt_bd->total_pkt_bytes = pkt_size;
3671
3672 if (pbd_e1x)
3673 DP(NETIF_MSG_TX_QUEUED,
3674 "PBD (E1X) @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u tcp_flags %x xsum %x seq %u hlen %u\n",
3675 pbd_e1x, pbd_e1x->global_data, pbd_e1x->ip_hlen_w,
3676 pbd_e1x->ip_id, pbd_e1x->lso_mss, pbd_e1x->tcp_flags,
3677 pbd_e1x->tcp_pseudo_csum, pbd_e1x->tcp_send_seq,
3678 le16_to_cpu(pbd_e1x->total_hlen_w));
3679 if (pbd_e2)
3680 DP(NETIF_MSG_TX_QUEUED,
3681 "PBD (E2) @%p dst %x %x %x src %x %x %x parsing_data %x\n",
3682 pbd_e2, pbd_e2->dst_mac_addr_hi, pbd_e2->dst_mac_addr_mid,
3683 pbd_e2->dst_mac_addr_lo, pbd_e2->src_mac_addr_hi,
3684 pbd_e2->src_mac_addr_mid, pbd_e2->src_mac_addr_lo,
3685 pbd_e2->parsing_data);
3686 DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d bd %u\n", nbd, bd_prod);
3687
3688 netdev_tx_sent_queue(txq, skb->len);
3689
3690 skb_tx_timestamp(skb);
3691
3692 txdata->tx_pkt_prod++;
3693 /*
3694 * Make sure that the BD data is updated before updating the producer
3695 * since FW might read the BD right after the producer is updated.
3696 * This is only applicable for weak-ordered memory model archs such
3697 * as IA-64. The following barrier is also mandatory since FW will
3698 * assumes packets must have BDs.
3699 */
3700 wmb();
3701
3702 txdata->tx_db.data.prod += nbd;
3703 barrier();
3704
3705 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
3706
3707 mmiowb();
3708
3709 txdata->tx_bd_prod += nbd;
3710
3711 if (unlikely(bnx2x_tx_avail(bp, txdata) < MAX_DESC_PER_TX_PKT)) {
3712 netif_tx_stop_queue(txq);
3713
3714 /* paired memory barrier is in bnx2x_tx_int(), we have to keep
3715 * ordering of set_bit() in netif_tx_stop_queue() and read of
3716 * fp->bd_tx_cons */
3717 smp_mb();
3718
3719 bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++;
3720 if (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT)
3721 netif_tx_wake_queue(txq);
3722 }
3723 txdata->tx_pkt++;
3724
3725 return NETDEV_TX_OK;
3726 }
3727
3728 /**
3729 * bnx2x_setup_tc - routine to configure net_device for multi tc
3730 *
3731 * @netdev: net device to configure
3732 * @tc: number of traffic classes to enable
3733 *
3734 * callback connected to the ndo_setup_tc function pointer
3735 */
3736 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc)
3737 {
3738 int cos, prio, count, offset;
3739 struct bnx2x *bp = netdev_priv(dev);
3740
3741 /* setup tc must be called under rtnl lock */
3742 ASSERT_RTNL();
3743
3744 /* no traffic classes requested. aborting */
3745 if (!num_tc) {
3746 netdev_reset_tc(dev);
3747 return 0;
3748 }
3749
3750 /* requested to support too many traffic classes */
3751 if (num_tc > bp->max_cos) {
3752 BNX2X_ERR("support for too many traffic classes requested: %d. max supported is %d\n",
3753 num_tc, bp->max_cos);
3754 return -EINVAL;
3755 }
3756
3757 /* declare amount of supported traffic classes */
3758 if (netdev_set_num_tc(dev, num_tc)) {
3759 BNX2X_ERR("failed to declare %d traffic classes\n", num_tc);
3760 return -EINVAL;
3761 }
3762
3763 /* configure priority to traffic class mapping */
3764 for (prio = 0; prio < BNX2X_MAX_PRIORITY; prio++) {
3765 netdev_set_prio_tc_map(dev, prio, bp->prio_to_cos[prio]);
3766 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
3767 "mapping priority %d to tc %d\n",
3768 prio, bp->prio_to_cos[prio]);
3769 }
3770
3771
3772 /* Use this configuration to diffrentiate tc0 from other COSes
3773 This can be used for ets or pfc, and save the effort of setting
3774 up a multio class queue disc or negotiating DCBX with a switch
3775 netdev_set_prio_tc_map(dev, 0, 0);
3776 DP(BNX2X_MSG_SP, "mapping priority %d to tc %d\n", 0, 0);
3777 for (prio = 1; prio < 16; prio++) {
3778 netdev_set_prio_tc_map(dev, prio, 1);
3779 DP(BNX2X_MSG_SP, "mapping priority %d to tc %d\n", prio, 1);
3780 } */
3781
3782 /* configure traffic class to transmission queue mapping */
3783 for (cos = 0; cos < bp->max_cos; cos++) {
3784 count = BNX2X_NUM_ETH_QUEUES(bp);
3785 offset = cos * BNX2X_NUM_NON_CNIC_QUEUES(bp);
3786 netdev_set_tc_queue(dev, cos, count, offset);
3787 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
3788 "mapping tc %d to offset %d count %d\n",
3789 cos, offset, count);
3790 }
3791
3792 return 0;
3793 }
3794
3795 /* called with rtnl_lock */
3796 int bnx2x_change_mac_addr(struct net_device *dev, void *p)
3797 {
3798 struct sockaddr *addr = p;
3799 struct bnx2x *bp = netdev_priv(dev);
3800 int rc = 0;
3801
3802 if (!bnx2x_is_valid_ether_addr(bp, addr->sa_data)) {
3803 BNX2X_ERR("Requested MAC address is not valid\n");
3804 return -EINVAL;
3805 }
3806
3807 if ((IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp)) &&
3808 !is_zero_ether_addr(addr->sa_data)) {
3809 BNX2X_ERR("Can't configure non-zero address on iSCSI or FCoE functions in MF-SD mode\n");
3810 return -EINVAL;
3811 }
3812
3813 if (netif_running(dev)) {
3814 rc = bnx2x_set_eth_mac(bp, false);
3815 if (rc)
3816 return rc;
3817 }
3818
3819 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3820
3821 if (netif_running(dev))
3822 rc = bnx2x_set_eth_mac(bp, true);
3823
3824 return rc;
3825 }
3826
3827 static void bnx2x_free_fp_mem_at(struct bnx2x *bp, int fp_index)
3828 {
3829 union host_hc_status_block *sb = &bnx2x_fp(bp, fp_index, status_blk);
3830 struct bnx2x_fastpath *fp = &bp->fp[fp_index];
3831 u8 cos;
3832
3833 /* Common */
3834
3835 if (IS_FCOE_IDX(fp_index)) {
3836 memset(sb, 0, sizeof(union host_hc_status_block));
3837 fp->status_blk_mapping = 0;
3838 } else {
3839 /* status blocks */
3840 if (!CHIP_IS_E1x(bp))
3841 BNX2X_PCI_FREE(sb->e2_sb,
3842 bnx2x_fp(bp, fp_index,
3843 status_blk_mapping),
3844 sizeof(struct host_hc_status_block_e2));
3845 else
3846 BNX2X_PCI_FREE(sb->e1x_sb,
3847 bnx2x_fp(bp, fp_index,
3848 status_blk_mapping),
3849 sizeof(struct host_hc_status_block_e1x));
3850 }
3851
3852 /* Rx */
3853 if (!skip_rx_queue(bp, fp_index)) {
3854 bnx2x_free_rx_bds(fp);
3855
3856 /* fastpath rx rings: rx_buf rx_desc rx_comp */
3857 BNX2X_FREE(bnx2x_fp(bp, fp_index, rx_buf_ring));
3858 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_desc_ring),
3859 bnx2x_fp(bp, fp_index, rx_desc_mapping),
3860 sizeof(struct eth_rx_bd) * NUM_RX_BD);
3861
3862 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_comp_ring),
3863 bnx2x_fp(bp, fp_index, rx_comp_mapping),
3864 sizeof(struct eth_fast_path_rx_cqe) *
3865 NUM_RCQ_BD);
3866
3867 /* SGE ring */
3868 BNX2X_FREE(bnx2x_fp(bp, fp_index, rx_page_ring));
3869 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_sge_ring),
3870 bnx2x_fp(bp, fp_index, rx_sge_mapping),
3871 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
3872 }
3873
3874 /* Tx */
3875 if (!skip_tx_queue(bp, fp_index)) {
3876 /* fastpath tx rings: tx_buf tx_desc */
3877 for_each_cos_in_tx_queue(fp, cos) {
3878 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
3879
3880 DP(NETIF_MSG_IFDOWN,
3881 "freeing tx memory of fp %d cos %d cid %d\n",
3882 fp_index, cos, txdata->cid);
3883
3884 BNX2X_FREE(txdata->tx_buf_ring);
3885 BNX2X_PCI_FREE(txdata->tx_desc_ring,
3886 txdata->tx_desc_mapping,
3887 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
3888 }
3889 }
3890 /* end of fastpath */
3891 }
3892
3893 void bnx2x_free_fp_mem_cnic(struct bnx2x *bp)
3894 {
3895 int i;
3896 for_each_cnic_queue(bp, i)
3897 bnx2x_free_fp_mem_at(bp, i);
3898 }
3899
3900 void bnx2x_free_fp_mem(struct bnx2x *bp)
3901 {
3902 int i;
3903 for_each_eth_queue(bp, i)
3904 bnx2x_free_fp_mem_at(bp, i);
3905 }
3906
3907 static void set_sb_shortcuts(struct bnx2x *bp, int index)
3908 {
3909 union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk);
3910 if (!CHIP_IS_E1x(bp)) {
3911 bnx2x_fp(bp, index, sb_index_values) =
3912 (__le16 *)status_blk.e2_sb->sb.index_values;
3913 bnx2x_fp(bp, index, sb_running_index) =
3914 (__le16 *)status_blk.e2_sb->sb.running_index;
3915 } else {
3916 bnx2x_fp(bp, index, sb_index_values) =
3917 (__le16 *)status_blk.e1x_sb->sb.index_values;
3918 bnx2x_fp(bp, index, sb_running_index) =
3919 (__le16 *)status_blk.e1x_sb->sb.running_index;
3920 }
3921 }
3922
3923 /* Returns the number of actually allocated BDs */
3924 static int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp,
3925 int rx_ring_size)
3926 {
3927 struct bnx2x *bp = fp->bp;
3928 u16 ring_prod, cqe_ring_prod;
3929 int i, failure_cnt = 0;
3930
3931 fp->rx_comp_cons = 0;
3932 cqe_ring_prod = ring_prod = 0;
3933
3934 /* This routine is called only during fo init so
3935 * fp->eth_q_stats.rx_skb_alloc_failed = 0
3936 */
3937 for (i = 0; i < rx_ring_size; i++) {
3938 if (bnx2x_alloc_rx_data(bp, fp, ring_prod) < 0) {
3939 failure_cnt++;
3940 continue;
3941 }
3942 ring_prod = NEXT_RX_IDX(ring_prod);
3943 cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
3944 WARN_ON(ring_prod <= (i - failure_cnt));
3945 }
3946
3947 if (failure_cnt)
3948 BNX2X_ERR("was only able to allocate %d rx skbs on queue[%d]\n",
3949 i - failure_cnt, fp->index);
3950
3951 fp->rx_bd_prod = ring_prod;
3952 /* Limit the CQE producer by the CQE ring size */
3953 fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT,
3954 cqe_ring_prod);
3955 fp->rx_pkt = fp->rx_calls = 0;
3956
3957 bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed += failure_cnt;
3958
3959 return i - failure_cnt;
3960 }
3961
3962 static void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
3963 {
3964 int i;
3965
3966 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
3967 struct eth_rx_cqe_next_page *nextpg;
3968
3969 nextpg = (struct eth_rx_cqe_next_page *)
3970 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
3971 nextpg->addr_hi =
3972 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
3973 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
3974 nextpg->addr_lo =
3975 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
3976 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
3977 }
3978 }
3979
3980 static int bnx2x_alloc_fp_mem_at(struct bnx2x *bp, int index)
3981 {
3982 union host_hc_status_block *sb;
3983 struct bnx2x_fastpath *fp = &bp->fp[index];
3984 int ring_size = 0;
3985 u8 cos;
3986 int rx_ring_size = 0;
3987
3988 if (!bp->rx_ring_size &&
3989 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
3990 rx_ring_size = MIN_RX_SIZE_NONTPA;
3991 bp->rx_ring_size = rx_ring_size;
3992 } else if (!bp->rx_ring_size) {
3993 rx_ring_size = MAX_RX_AVAIL/BNX2X_NUM_RX_QUEUES(bp);
3994
3995 if (CHIP_IS_E3(bp)) {
3996 u32 cfg = SHMEM_RD(bp,
3997 dev_info.port_hw_config[BP_PORT(bp)].
3998 default_cfg);
3999
4000 /* Decrease ring size for 1G functions */
4001 if ((cfg & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
4002 PORT_HW_CFG_NET_SERDES_IF_SGMII)
4003 rx_ring_size /= 10;
4004 }
4005
4006 /* allocate at least number of buffers required by FW */
4007 rx_ring_size = max_t(int, bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
4008 MIN_RX_SIZE_TPA, rx_ring_size);
4009
4010 bp->rx_ring_size = rx_ring_size;
4011 } else /* if rx_ring_size specified - use it */
4012 rx_ring_size = bp->rx_ring_size;
4013
4014 /* Common */
4015 sb = &bnx2x_fp(bp, index, status_blk);
4016
4017 if (!IS_FCOE_IDX(index)) {
4018 /* status blocks */
4019 if (!CHIP_IS_E1x(bp))
4020 BNX2X_PCI_ALLOC(sb->e2_sb,
4021 &bnx2x_fp(bp, index, status_blk_mapping),
4022 sizeof(struct host_hc_status_block_e2));
4023 else
4024 BNX2X_PCI_ALLOC(sb->e1x_sb,
4025 &bnx2x_fp(bp, index, status_blk_mapping),
4026 sizeof(struct host_hc_status_block_e1x));
4027 }
4028
4029 /* FCoE Queue uses Default SB and doesn't ACK the SB, thus no need to
4030 * set shortcuts for it.
4031 */
4032 if (!IS_FCOE_IDX(index))
4033 set_sb_shortcuts(bp, index);
4034
4035 /* Tx */
4036 if (!skip_tx_queue(bp, index)) {
4037 /* fastpath tx rings: tx_buf tx_desc */
4038 for_each_cos_in_tx_queue(fp, cos) {
4039 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
4040
4041 DP(NETIF_MSG_IFUP,
4042 "allocating tx memory of fp %d cos %d\n",
4043 index, cos);
4044
4045 BNX2X_ALLOC(txdata->tx_buf_ring,
4046 sizeof(struct sw_tx_bd) * NUM_TX_BD);
4047 BNX2X_PCI_ALLOC(txdata->tx_desc_ring,
4048 &txdata->tx_desc_mapping,
4049 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
4050 }
4051 }
4052
4053 /* Rx */
4054 if (!skip_rx_queue(bp, index)) {
4055 /* fastpath rx rings: rx_buf rx_desc rx_comp */
4056 BNX2X_ALLOC(bnx2x_fp(bp, index, rx_buf_ring),
4057 sizeof(struct sw_rx_bd) * NUM_RX_BD);
4058 BNX2X_PCI_ALLOC(bnx2x_fp(bp, index, rx_desc_ring),
4059 &bnx2x_fp(bp, index, rx_desc_mapping),
4060 sizeof(struct eth_rx_bd) * NUM_RX_BD);
4061
4062 BNX2X_PCI_ALLOC(bnx2x_fp(bp, index, rx_comp_ring),
4063 &bnx2x_fp(bp, index, rx_comp_mapping),
4064 sizeof(struct eth_fast_path_rx_cqe) *
4065 NUM_RCQ_BD);
4066
4067 /* SGE ring */
4068 BNX2X_ALLOC(bnx2x_fp(bp, index, rx_page_ring),
4069 sizeof(struct sw_rx_page) * NUM_RX_SGE);
4070 BNX2X_PCI_ALLOC(bnx2x_fp(bp, index, rx_sge_ring),
4071 &bnx2x_fp(bp, index, rx_sge_mapping),
4072 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
4073 /* RX BD ring */
4074 bnx2x_set_next_page_rx_bd(fp);
4075
4076 /* CQ ring */
4077 bnx2x_set_next_page_rx_cq(fp);
4078
4079 /* BDs */
4080 ring_size = bnx2x_alloc_rx_bds(fp, rx_ring_size);
4081 if (ring_size < rx_ring_size)
4082 goto alloc_mem_err;
4083 }
4084
4085 return 0;
4086
4087 /* handles low memory cases */
4088 alloc_mem_err:
4089 BNX2X_ERR("Unable to allocate full memory for queue %d (size %d)\n",
4090 index, ring_size);
4091 /* FW will drop all packets if queue is not big enough,
4092 * In these cases we disable the queue
4093 * Min size is different for OOO, TPA and non-TPA queues
4094 */
4095 if (ring_size < (fp->disable_tpa ?
4096 MIN_RX_SIZE_NONTPA : MIN_RX_SIZE_TPA)) {
4097 /* release memory allocated for this queue */
4098 bnx2x_free_fp_mem_at(bp, index);
4099 return -ENOMEM;
4100 }
4101 return 0;
4102 }
4103
4104 int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp)
4105 {
4106 if (!NO_FCOE(bp))
4107 /* FCoE */
4108 if (bnx2x_alloc_fp_mem_at(bp, FCOE_IDX(bp)))
4109 /* we will fail load process instead of mark
4110 * NO_FCOE_FLAG
4111 */
4112 return -ENOMEM;
4113
4114 return 0;
4115 }
4116
4117 int bnx2x_alloc_fp_mem(struct bnx2x *bp)
4118 {
4119 int i;
4120
4121 /* 1. Allocate FP for leading - fatal if error
4122 * 2. Allocate RSS - fix number of queues if error
4123 */
4124
4125 /* leading */
4126 if (bnx2x_alloc_fp_mem_at(bp, 0))
4127 return -ENOMEM;
4128
4129 /* RSS */
4130 for_each_nondefault_eth_queue(bp, i)
4131 if (bnx2x_alloc_fp_mem_at(bp, i))
4132 break;
4133
4134 /* handle memory failures */
4135 if (i != BNX2X_NUM_ETH_QUEUES(bp)) {
4136 int delta = BNX2X_NUM_ETH_QUEUES(bp) - i;
4137
4138 WARN_ON(delta < 0);
4139 if (CNIC_SUPPORT(bp))
4140 /* move non eth FPs next to last eth FP
4141 * must be done in that order
4142 * FCOE_IDX < FWD_IDX < OOO_IDX
4143 */
4144
4145 /* move FCoE fp even NO_FCOE_FLAG is on */
4146 bnx2x_move_fp(bp, FCOE_IDX(bp), FCOE_IDX(bp) - delta);
4147 bp->num_ethernet_queues -= delta;
4148 bp->num_queues = bp->num_ethernet_queues +
4149 bp->num_cnic_queues;
4150 BNX2X_ERR("Adjusted num of queues from %d to %d\n",
4151 bp->num_queues + delta, bp->num_queues);
4152 }
4153
4154 return 0;
4155 }
4156
4157 void bnx2x_free_mem_bp(struct bnx2x *bp)
4158 {
4159 kfree(bp->fp->tpa_info);
4160 kfree(bp->fp);
4161 kfree(bp->sp_objs);
4162 kfree(bp->fp_stats);
4163 kfree(bp->bnx2x_txq);
4164 kfree(bp->msix_table);
4165 kfree(bp->ilt);
4166 }
4167
4168 int bnx2x_alloc_mem_bp(struct bnx2x *bp)
4169 {
4170 struct bnx2x_fastpath *fp;
4171 struct msix_entry *tbl;
4172 struct bnx2x_ilt *ilt;
4173 int msix_table_size = 0;
4174 int fp_array_size, txq_array_size;
4175 int i;
4176
4177 /*
4178 * The biggest MSI-X table we might need is as a maximum number of fast
4179 * path IGU SBs plus default SB (for PF).
4180 */
4181 msix_table_size = bp->igu_sb_cnt;
4182 if (IS_PF(bp))
4183 msix_table_size++;
4184 BNX2X_DEV_INFO("msix_table_size %d\n", msix_table_size);
4185
4186 /* fp array: RSS plus CNIC related L2 queues */
4187 fp_array_size = BNX2X_MAX_RSS_COUNT(bp) + CNIC_SUPPORT(bp);
4188 BNX2X_DEV_INFO("fp_array_size %d", fp_array_size);
4189
4190 fp = kcalloc(fp_array_size, sizeof(*fp), GFP_KERNEL);
4191 if (!fp)
4192 goto alloc_err;
4193 for (i = 0; i < fp_array_size; i++) {
4194 fp[i].tpa_info =
4195 kcalloc(ETH_MAX_AGGREGATION_QUEUES_E1H_E2,
4196 sizeof(struct bnx2x_agg_info), GFP_KERNEL);
4197 if (!(fp[i].tpa_info))
4198 goto alloc_err;
4199 }
4200
4201 bp->fp = fp;
4202
4203 /* allocate sp objs */
4204 bp->sp_objs = kcalloc(fp_array_size, sizeof(struct bnx2x_sp_objs),
4205 GFP_KERNEL);
4206 if (!bp->sp_objs)
4207 goto alloc_err;
4208
4209 /* allocate fp_stats */
4210 bp->fp_stats = kcalloc(fp_array_size, sizeof(struct bnx2x_fp_stats),
4211 GFP_KERNEL);
4212 if (!bp->fp_stats)
4213 goto alloc_err;
4214
4215 /* Allocate memory for the transmission queues array */
4216 txq_array_size =
4217 BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS + CNIC_SUPPORT(bp);
4218 BNX2X_DEV_INFO("txq_array_size %d", txq_array_size);
4219
4220 bp->bnx2x_txq = kcalloc(txq_array_size, sizeof(struct bnx2x_fp_txdata),
4221 GFP_KERNEL);
4222 if (!bp->bnx2x_txq)
4223 goto alloc_err;
4224
4225 /* msix table */
4226 tbl = kcalloc(msix_table_size, sizeof(*tbl), GFP_KERNEL);
4227 if (!tbl)
4228 goto alloc_err;
4229 bp->msix_table = tbl;
4230
4231 /* ilt */
4232 ilt = kzalloc(sizeof(*ilt), GFP_KERNEL);
4233 if (!ilt)
4234 goto alloc_err;
4235 bp->ilt = ilt;
4236
4237 return 0;
4238 alloc_err:
4239 bnx2x_free_mem_bp(bp);
4240 return -ENOMEM;
4241
4242 }
4243
4244 int bnx2x_reload_if_running(struct net_device *dev)
4245 {
4246 struct bnx2x *bp = netdev_priv(dev);
4247
4248 if (unlikely(!netif_running(dev)))
4249 return 0;
4250
4251 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
4252 return bnx2x_nic_load(bp, LOAD_NORMAL);
4253 }
4254
4255 int bnx2x_get_cur_phy_idx(struct bnx2x *bp)
4256 {
4257 u32 sel_phy_idx = 0;
4258 if (bp->link_params.num_phys <= 1)
4259 return INT_PHY;
4260
4261 if (bp->link_vars.link_up) {
4262 sel_phy_idx = EXT_PHY1;
4263 /* In case link is SERDES, check if the EXT_PHY2 is the one */
4264 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
4265 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
4266 sel_phy_idx = EXT_PHY2;
4267 } else {
4268
4269 switch (bnx2x_phy_selection(&bp->link_params)) {
4270 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
4271 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
4272 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
4273 sel_phy_idx = EXT_PHY1;
4274 break;
4275 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
4276 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
4277 sel_phy_idx = EXT_PHY2;
4278 break;
4279 }
4280 }
4281
4282 return sel_phy_idx;
4283
4284 }
4285 int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
4286 {
4287 u32 sel_phy_idx = bnx2x_get_cur_phy_idx(bp);
4288 /*
4289 * The selected actived PHY is always after swapping (in case PHY
4290 * swapping is enabled). So when swapping is enabled, we need to reverse
4291 * the configuration
4292 */
4293
4294 if (bp->link_params.multi_phy_config &
4295 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
4296 if (sel_phy_idx == EXT_PHY1)
4297 sel_phy_idx = EXT_PHY2;
4298 else if (sel_phy_idx == EXT_PHY2)
4299 sel_phy_idx = EXT_PHY1;
4300 }
4301 return LINK_CONFIG_IDX(sel_phy_idx);
4302 }
4303
4304 #ifdef NETDEV_FCOE_WWNN
4305 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type)
4306 {
4307 struct bnx2x *bp = netdev_priv(dev);
4308 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
4309
4310 switch (type) {
4311 case NETDEV_FCOE_WWNN:
4312 *wwn = HILO_U64(cp->fcoe_wwn_node_name_hi,
4313 cp->fcoe_wwn_node_name_lo);
4314 break;
4315 case NETDEV_FCOE_WWPN:
4316 *wwn = HILO_U64(cp->fcoe_wwn_port_name_hi,
4317 cp->fcoe_wwn_port_name_lo);
4318 break;
4319 default:
4320 BNX2X_ERR("Wrong WWN type requested - %d\n", type);
4321 return -EINVAL;
4322 }
4323
4324 return 0;
4325 }
4326 #endif
4327
4328 /* called with rtnl_lock */
4329 int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
4330 {
4331 struct bnx2x *bp = netdev_priv(dev);
4332
4333 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
4334 BNX2X_ERR("Can't perform change MTU during parity recovery\n");
4335 return -EAGAIN;
4336 }
4337
4338 if ((new_mtu > ETH_MAX_JUMBO_PACKET_SIZE) ||
4339 ((new_mtu + ETH_HLEN) < ETH_MIN_PACKET_SIZE)) {
4340 BNX2X_ERR("Can't support requested MTU size\n");
4341 return -EINVAL;
4342 }
4343
4344 /* This does not race with packet allocation
4345 * because the actual alloc size is
4346 * only updated as part of load
4347 */
4348 dev->mtu = new_mtu;
4349
4350 return bnx2x_reload_if_running(dev);
4351 }
4352
4353 netdev_features_t bnx2x_fix_features(struct net_device *dev,
4354 netdev_features_t features)
4355 {
4356 struct bnx2x *bp = netdev_priv(dev);
4357
4358 /* TPA requires Rx CSUM offloading */
4359 if (!(features & NETIF_F_RXCSUM) || bp->disable_tpa) {
4360 features &= ~NETIF_F_LRO;
4361 features &= ~NETIF_F_GRO;
4362 }
4363
4364 return features;
4365 }
4366
4367 int bnx2x_set_features(struct net_device *dev, netdev_features_t features)
4368 {
4369 struct bnx2x *bp = netdev_priv(dev);
4370 u32 flags = bp->flags;
4371 bool bnx2x_reload = false;
4372
4373 if (features & NETIF_F_LRO)
4374 flags |= TPA_ENABLE_FLAG;
4375 else
4376 flags &= ~TPA_ENABLE_FLAG;
4377
4378 if (features & NETIF_F_GRO)
4379 flags |= GRO_ENABLE_FLAG;
4380 else
4381 flags &= ~GRO_ENABLE_FLAG;
4382
4383 if (features & NETIF_F_LOOPBACK) {
4384 if (bp->link_params.loopback_mode != LOOPBACK_BMAC) {
4385 bp->link_params.loopback_mode = LOOPBACK_BMAC;
4386 bnx2x_reload = true;
4387 }
4388 } else {
4389 if (bp->link_params.loopback_mode != LOOPBACK_NONE) {
4390 bp->link_params.loopback_mode = LOOPBACK_NONE;
4391 bnx2x_reload = true;
4392 }
4393 }
4394
4395 if (flags ^ bp->flags) {
4396 bp->flags = flags;
4397 bnx2x_reload = true;
4398 }
4399
4400 if (bnx2x_reload) {
4401 if (bp->recovery_state == BNX2X_RECOVERY_DONE)
4402 return bnx2x_reload_if_running(dev);
4403 /* else: bnx2x_nic_load() will be called at end of recovery */
4404 }
4405
4406 return 0;
4407 }
4408
4409 void bnx2x_tx_timeout(struct net_device *dev)
4410 {
4411 struct bnx2x *bp = netdev_priv(dev);
4412
4413 #ifdef BNX2X_STOP_ON_ERROR
4414 if (!bp->panic)
4415 bnx2x_panic();
4416 #endif
4417
4418 smp_mb__before_clear_bit();
4419 set_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state);
4420 smp_mb__after_clear_bit();
4421
4422 /* This allows the netif to be shutdown gracefully before resetting */
4423 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4424 }
4425
4426 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
4427 {
4428 struct net_device *dev = pci_get_drvdata(pdev);
4429 struct bnx2x *bp;
4430
4431 if (!dev) {
4432 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
4433 return -ENODEV;
4434 }
4435 bp = netdev_priv(dev);
4436
4437 rtnl_lock();
4438
4439 pci_save_state(pdev);
4440
4441 if (!netif_running(dev)) {
4442 rtnl_unlock();
4443 return 0;
4444 }
4445
4446 netif_device_detach(dev);
4447
4448 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
4449
4450 bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
4451
4452 rtnl_unlock();
4453
4454 return 0;
4455 }
4456
4457 int bnx2x_resume(struct pci_dev *pdev)
4458 {
4459 struct net_device *dev = pci_get_drvdata(pdev);
4460 struct bnx2x *bp;
4461 int rc;
4462
4463 if (!dev) {
4464 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
4465 return -ENODEV;
4466 }
4467 bp = netdev_priv(dev);
4468
4469 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
4470 BNX2X_ERR("Handling parity error recovery. Try again later\n");
4471 return -EAGAIN;
4472 }
4473
4474 rtnl_lock();
4475
4476 pci_restore_state(pdev);
4477
4478 if (!netif_running(dev)) {
4479 rtnl_unlock();
4480 return 0;
4481 }
4482
4483 bnx2x_set_power_state(bp, PCI_D0);
4484 netif_device_attach(dev);
4485
4486 rc = bnx2x_nic_load(bp, LOAD_OPEN);
4487
4488 rtnl_unlock();
4489
4490 return rc;
4491 }
4492
4493
4494 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
4495 u32 cid)
4496 {
4497 /* ustorm cxt validation */
4498 cxt->ustorm_ag_context.cdu_usage =
4499 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, cid),
4500 CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE);
4501 /* xcontext validation */
4502 cxt->xstorm_ag_context.cdu_reserved =
4503 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, cid),
4504 CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE);
4505 }
4506
4507 static void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
4508 u8 fw_sb_id, u8 sb_index,
4509 u8 ticks)
4510 {
4511
4512 u32 addr = BAR_CSTRORM_INTMEM +
4513 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index);
4514 REG_WR8(bp, addr, ticks);
4515 DP(NETIF_MSG_IFUP,
4516 "port %x fw_sb_id %d sb_index %d ticks %d\n",
4517 port, fw_sb_id, sb_index, ticks);
4518 }
4519
4520 static void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
4521 u16 fw_sb_id, u8 sb_index,
4522 u8 disable)
4523 {
4524 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
4525 u32 addr = BAR_CSTRORM_INTMEM +
4526 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index);
4527 u16 flags = REG_RD16(bp, addr);
4528 /* clear and set */
4529 flags &= ~HC_INDEX_DATA_HC_ENABLED;
4530 flags |= enable_flag;
4531 REG_WR16(bp, addr, flags);
4532 DP(NETIF_MSG_IFUP,
4533 "port %x fw_sb_id %d sb_index %d disable %d\n",
4534 port, fw_sb_id, sb_index, disable);
4535 }
4536
4537 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
4538 u8 sb_index, u8 disable, u16 usec)
4539 {
4540 int port = BP_PORT(bp);
4541 u8 ticks = usec / BNX2X_BTR;
4542
4543 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4544
4545 disable = disable ? 1 : (usec ? 0 : 1);
4546 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4547 }
kernel source for telekom puls (alcatel/mediatek)